1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
259 bfd_reloc_code_real_type reloc
;
262 /* Macros to define the register types and masks for the purpose
265 #undef AARCH64_REG_TYPES
266 #define AARCH64_REG_TYPES \
267 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
268 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
269 BASIC_REG_TYPE(SP_32) /* wsp */ \
270 BASIC_REG_TYPE(SP_64) /* sp */ \
271 BASIC_REG_TYPE(Z_32) /* wzr */ \
272 BASIC_REG_TYPE(Z_64) /* xzr */ \
273 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
274 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
275 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
276 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
277 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
278 BASIC_REG_TYPE(VN) /* v[0-31] */ \
279 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
280 BASIC_REG_TYPE(PN) /* p[0-15] */ \
281 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
282 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
283 /* Typecheck: same, plus SVE registers. */ \
284 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
286 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
287 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
293 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
294 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
296 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
297 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
299 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
300 /* Typecheck: any [BHSDQ]P FP. */ \
301 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
302 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
303 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
304 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
306 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
307 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
308 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
309 be used for SVE instructions, since Zn and Pn are valid symbols \
310 in other contexts. */ \
311 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
314 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
315 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
316 | REG_TYPE(ZN) | REG_TYPE(PN)) \
317 /* Any integer register; used for error messages only. */ \
318 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
321 /* Pseudo type to mark the end of the enumerator sequence. */ \
324 #undef BASIC_REG_TYPE
325 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
326 #undef MULTI_REG_TYPE
327 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
329 /* Register type enumerators. */
330 typedef enum aarch64_reg_type_
332 /* A list of REG_TYPE_*. */
336 #undef BASIC_REG_TYPE
337 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
339 #define REG_TYPE(T) (1 << REG_TYPE_##T)
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) V,
343 /* Structure for a hash table entry for a register. */
347 unsigned char number
;
348 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
349 unsigned char builtin
;
352 /* Values indexed by aarch64_reg_type to assist the type checking. */
353 static const unsigned reg_type_masks
[] =
358 #undef BASIC_REG_TYPE
360 #undef MULTI_REG_TYPE
361 #undef AARCH64_REG_TYPES
363 /* Diagnostics used when we don't get a register of the expected type.
364 Note: this has to synchronized with aarch64_reg_type definitions
367 get_reg_expected_msg (aarch64_reg_type reg_type
)
374 msg
= N_("integer 32-bit register expected");
377 msg
= N_("integer 64-bit register expected");
380 msg
= N_("integer register expected");
382 case REG_TYPE_R64_SP
:
383 msg
= N_("64-bit integer or SP register expected");
385 case REG_TYPE_SVE_BASE
:
386 msg
= N_("base register expected");
389 msg
= N_("integer or zero register expected");
391 case REG_TYPE_SVE_OFFSET
:
392 msg
= N_("offset register expected");
395 msg
= N_("integer or SP register expected");
397 case REG_TYPE_R_Z_SP
:
398 msg
= N_("integer, zero or SP register expected");
401 msg
= N_("8-bit SIMD scalar register expected");
404 msg
= N_("16-bit SIMD scalar or floating-point half precision "
405 "register expected");
408 msg
= N_("32-bit SIMD scalar or floating-point single precision "
409 "register expected");
412 msg
= N_("64-bit SIMD scalar or floating-point double precision "
413 "register expected");
416 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
417 "register expected");
419 case REG_TYPE_R_Z_BHSDQ_V
:
420 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
421 msg
= N_("register expected");
423 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
424 msg
= N_("SIMD scalar or floating-point register expected");
426 case REG_TYPE_VN
: /* any V reg */
427 msg
= N_("vector register expected");
430 msg
= N_("SVE vector register expected");
433 msg
= N_("SVE predicate register expected");
436 as_fatal (_("invalid register type %d"), reg_type
);
441 /* Some well known registers that we refer to directly elsewhere. */
445 /* Instructions take 4 bytes in the object file. */
448 static htab_t aarch64_ops_hsh
;
449 static htab_t aarch64_cond_hsh
;
450 static htab_t aarch64_shift_hsh
;
451 static htab_t aarch64_sys_regs_hsh
;
452 static htab_t aarch64_pstatefield_hsh
;
453 static htab_t aarch64_sys_regs_ic_hsh
;
454 static htab_t aarch64_sys_regs_dc_hsh
;
455 static htab_t aarch64_sys_regs_at_hsh
;
456 static htab_t aarch64_sys_regs_tlbi_hsh
;
457 static htab_t aarch64_sys_regs_sr_hsh
;
458 static htab_t aarch64_reg_hsh
;
459 static htab_t aarch64_barrier_opt_hsh
;
460 static htab_t aarch64_nzcv_hsh
;
461 static htab_t aarch64_pldop_hsh
;
462 static htab_t aarch64_hint_opt_hsh
;
464 /* Stuff needed to resolve the label ambiguity
473 static symbolS
*last_label_seen
;
475 /* Literal pool structure. Held on a per-section
476 and per-sub-section basis. */
478 #define MAX_LITERAL_POOL_SIZE 1024
479 typedef struct literal_expression
482 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
483 LITTLENUM_TYPE
* bignum
;
484 } literal_expression
;
486 typedef struct literal_pool
488 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
489 unsigned int next_free_entry
;
495 struct literal_pool
*next
;
498 /* Pointer to a linked list of literal pools. */
499 static literal_pool
*list_of_pools
= NULL
;
503 /* This array holds the chars that always start a comment. If the
504 pre-processor is disabled, these aren't very useful. */
505 const char comment_chars
[] = "";
507 /* This array holds the chars that only start a comment at the beginning of
508 a line. If the line seems to have the form '# 123 filename'
509 .line and .file directives will appear in the pre-processed output. */
510 /* Note that input_file.c hand checks for '#' at the beginning of the
511 first line of the input file. This is because the compiler outputs
512 #NO_APP at the beginning of its output. */
513 /* Also note that comments like this one will always work. */
514 const char line_comment_chars
[] = "#";
516 const char line_separator_chars
[] = ";";
518 /* Chars that can be used to separate mant
519 from exp in floating point numbers. */
520 const char EXP_CHARS
[] = "eE";
522 /* Chars that mean this number is a floating point constant. */
526 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
528 /* Prefix character that indicates the start of an immediate value. */
529 #define is_immediate_prefix(C) ((C) == '#')
531 /* Separator character handling. */
533 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
535 static inline bfd_boolean
536 skip_past_char (char **str
, char c
)
547 #define skip_past_comma(str) skip_past_char (str, ',')
549 /* Arithmetic expressions (possibly involving symbols). */
551 static bfd_boolean in_my_get_expression_p
= FALSE
;
553 /* Third argument to my_get_expression. */
554 #define GE_NO_PREFIX 0
555 #define GE_OPT_PREFIX 1
557 /* Return TRUE if the string pointed by *STR is successfully parsed
558 as an valid expression; *EP will be filled with the information of
559 such an expression. Otherwise return FALSE. */
562 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
567 int prefix_present_p
= 0;
574 if (is_immediate_prefix (**str
))
577 prefix_present_p
= 1;
584 memset (ep
, 0, sizeof (expressionS
));
586 save_in
= input_line_pointer
;
587 input_line_pointer
= *str
;
588 in_my_get_expression_p
= TRUE
;
589 seg
= expression (ep
);
590 in_my_get_expression_p
= FALSE
;
592 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
594 /* We found a bad expression in md_operand(). */
595 *str
= input_line_pointer
;
596 input_line_pointer
= save_in
;
597 if (prefix_present_p
&& ! error_p ())
598 set_fatal_syntax_error (_("bad expression"));
600 set_first_syntax_error (_("bad expression"));
605 if (seg
!= absolute_section
606 && seg
!= text_section
607 && seg
!= data_section
608 && seg
!= bss_section
&& seg
!= undefined_section
)
610 set_syntax_error (_("bad segment"));
611 *str
= input_line_pointer
;
612 input_line_pointer
= save_in
;
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
624 /* Turn a string in input_line_pointer into a floating point constant
625 of type TYPE, and store the appropriate bytes in *LITP. The number
626 of LITTLENUMS emitted is stored in *SIZEP. An error message is
627 returned, or NULL on OK. */
630 md_atof (int type
, char *litP
, int *sizeP
)
632 /* If this is a bfloat16 type, then parse it slightly differently -
633 as it does not follow the IEEE standard exactly. */
637 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
638 FLONUM_TYPE generic_float
;
640 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
643 input_line_pointer
= t
;
645 return _("invalid floating point number");
647 switch (generic_float
.sign
)
660 /* bfloat16 has two types of NaN - quiet and signalling.
661 Quiet NaN has bit[6] == 1 && faction != 0, whereas
662 signalling Nan's have bit[0] == 0 && fraction != 0.
663 Chose this specific encoding as it is the same form
664 as used by other IEEE 754 encodings in GAS. */
675 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
680 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
683 /* We handle all bad expressions here, so that we can report the faulty
684 instruction in the error message. */
686 md_operand (expressionS
* exp
)
688 if (in_my_get_expression_p
)
689 exp
->X_op
= O_illegal
;
692 /* Immediate values. */
694 /* Errors may be set multiple times during parsing or bit encoding
695 (particularly in the Neon bits), but usually the earliest error which is set
696 will be the most meaningful. Avoid overwriting it with later (cascading)
697 errors by calling this function. */
700 first_error (const char *error
)
703 set_syntax_error (error
);
706 /* Similar to first_error, but this function accepts formatted error
709 first_error_fmt (const char *format
, ...)
714 /* N.B. this single buffer will not cause error messages for different
715 instructions to pollute each other; this is because at the end of
716 processing of each assembly line, error message if any will be
717 collected by as_bad. */
718 static char buffer
[size
];
722 int ret ATTRIBUTE_UNUSED
;
723 va_start (args
, format
);
724 ret
= vsnprintf (buffer
, size
, format
, args
);
725 know (ret
<= size
- 1 && ret
>= 0);
727 set_syntax_error (buffer
);
731 /* Register parsing. */
733 /* Generic register parser which is called by other specialized
735 CCP points to what should be the beginning of a register name.
736 If it is indeed a valid register name, advance CCP over it and
737 return the reg_entry structure; otherwise return NULL.
738 It does not issue diagnostics. */
741 parse_reg (char **ccp
)
747 #ifdef REGISTER_PREFIX
748 if (*start
!= REGISTER_PREFIX
)
754 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
759 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
761 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
770 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
773 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
775 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
778 /* Try to parse a base or offset register. Allow SVE base and offset
779 registers if REG_TYPE includes SVE registers. Return the register
780 entry on success, setting *QUALIFIER to the register qualifier.
781 Return null otherwise.
783 Note that this function does not issue any diagnostics. */
785 static const reg_entry
*
786 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
787 aarch64_opnd_qualifier_t
*qualifier
)
790 const reg_entry
*reg
= parse_reg (&str
);
800 *qualifier
= AARCH64_OPND_QLF_W
;
806 *qualifier
= AARCH64_OPND_QLF_X
;
810 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
813 switch (TOLOWER (str
[1]))
816 *qualifier
= AARCH64_OPND_QLF_S_S
;
819 *qualifier
= AARCH64_OPND_QLF_S_D
;
836 /* Try to parse a base or offset register. Return the register entry
837 on success, setting *QUALIFIER to the register qualifier. Return null
840 Note that this function does not issue any diagnostics. */
842 static const reg_entry
*
843 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
845 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
848 /* Parse the qualifier of a vector register or vector element of type
849 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
850 succeeds; otherwise return FALSE.
852 Accept only one occurrence of:
853 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
856 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
857 struct vector_type_el
*parsed_type
, char **str
)
861 unsigned element_size
;
862 enum vector_el_type type
;
865 gas_assert (*ptr
== '.');
868 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
873 width
= strtoul (ptr
, &ptr
, 10);
874 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
876 first_error_fmt (_("bad size %d in vector width specifier"), width
);
881 switch (TOLOWER (*ptr
))
900 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
909 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
911 first_error (_("missing element size"));
914 if (width
!= 0 && width
* element_size
!= 64
915 && width
* element_size
!= 128
916 && !(width
== 2 && element_size
== 16)
917 && !(width
== 4 && element_size
== 8))
920 ("invalid element size %d and vector size combination %c"),
926 parsed_type
->type
= type
;
927 parsed_type
->width
= width
;
934 /* *STR contains an SVE zero/merge predication suffix. Parse it into
935 *PARSED_TYPE and point *STR at the end of the suffix. */
938 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
943 gas_assert (*ptr
== '/');
945 switch (TOLOWER (*ptr
))
948 parsed_type
->type
= NT_zero
;
951 parsed_type
->type
= NT_merge
;
954 if (*ptr
!= '\0' && *ptr
!= ',')
955 first_error_fmt (_("unexpected character `%c' in predication type"),
958 first_error (_("missing predication type"));
961 parsed_type
->width
= 0;
966 /* Parse a register of the type TYPE.
968 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
969 name or the parsed register is not of TYPE.
971 Otherwise return the register number, and optionally fill in the actual
972 type of the register in *RTYPE when multiple alternatives were given, and
973 return the register shape and element index information in *TYPEINFO.
975 IN_REG_LIST should be set with TRUE if the caller is parsing a register
979 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
980 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
983 const reg_entry
*reg
= parse_reg (&str
);
984 struct vector_type_el atype
;
985 struct vector_type_el parsetype
;
986 bfd_boolean is_typed_vecreg
= FALSE
;
989 atype
.type
= NT_invtype
;
997 set_default_error ();
1001 if (! aarch64_check_reg_type (reg
, type
))
1003 DEBUG_TRACE ("reg type check failed");
1004 set_default_error ();
1009 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1010 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1014 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1019 if (!parse_predication_for_operand (&parsetype
, &str
))
1023 /* Register if of the form Vn.[bhsdq]. */
1024 is_typed_vecreg
= TRUE
;
1026 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1028 /* The width is always variable; we don't allow an integer width
1030 gas_assert (parsetype
.width
== 0);
1031 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1033 else if (parsetype
.width
== 0)
1034 /* Expect index. In the new scheme we cannot have
1035 Vn.[bhsdq] represent a scalar. Therefore any
1036 Vn.[bhsdq] should have an index following it.
1037 Except in reglists of course. */
1038 atype
.defined
|= NTA_HASINDEX
;
1040 atype
.defined
|= NTA_HASTYPE
;
1042 atype
.type
= parsetype
.type
;
1043 atype
.width
= parsetype
.width
;
1046 if (skip_past_char (&str
, '['))
1050 /* Reject Sn[index] syntax. */
1051 if (!is_typed_vecreg
)
1053 first_error (_("this type of register can't be indexed"));
1059 first_error (_("index not allowed inside register list"));
1063 atype
.defined
|= NTA_HASINDEX
;
1065 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1067 if (exp
.X_op
!= O_constant
)
1069 first_error (_("constant expression required"));
1073 if (! skip_past_char (&str
, ']'))
1076 atype
.index
= exp
.X_add_number
;
1078 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1080 /* Indexed vector register expected. */
1081 first_error (_("indexed vector register expected"));
1085 /* A vector reg Vn should be typed or indexed. */
1086 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1088 first_error (_("invalid use of vector register"));
1104 Return the register number on success; return PARSE_FAIL otherwise.
1106 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1107 the register (e.g. NEON double or quad reg when either has been requested).
1109 If this is a NEON vector register with additional type information, fill
1110 in the struct pointed to by VECTYPE (if non-NULL).
1112 This parser does not handle register list. */
1115 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1116 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1118 struct vector_type_el atype
;
1120 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1121 /*in_reg_list= */ FALSE
);
1123 if (reg
== PARSE_FAIL
)
1134 static inline bfd_boolean
1135 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1139 && e1
.defined
== e2
.defined
1140 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1143 /* This function parses a list of vector registers of type TYPE.
1144 On success, it returns the parsed register list information in the
1145 following encoded format:
1147 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1148 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1150 The information of the register shape and/or index is returned in
1153 It returns PARSE_FAIL if the register list is invalid.
1155 The list contains one to four registers.
1156 Each register can be one of:
1159 All <T> should be identical.
1160 All <index> should be identical.
1161 There are restrictions on <Vt> numbers which are checked later
1162 (by reg_list_valid_p). */
1165 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1166 struct vector_type_el
*vectype
)
1170 struct vector_type_el typeinfo
, typeinfo_first
;
1175 bfd_boolean error
= FALSE
;
1176 bfd_boolean expect_index
= FALSE
;
1180 set_syntax_error (_("expecting {"));
1186 typeinfo_first
.defined
= 0;
1187 typeinfo_first
.type
= NT_invtype
;
1188 typeinfo_first
.width
= -1;
1189 typeinfo_first
.index
= 0;
1198 str
++; /* skip over '-' */
1201 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1202 /*in_reg_list= */ TRUE
);
1203 if (val
== PARSE_FAIL
)
1205 set_first_syntax_error (_("invalid vector register in list"));
1209 /* reject [bhsd]n */
1210 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1212 set_first_syntax_error (_("invalid scalar register in list"));
1217 if (typeinfo
.defined
& NTA_HASINDEX
)
1218 expect_index
= TRUE
;
1222 if (val
< val_range
)
1224 set_first_syntax_error
1225 (_("invalid range in vector register list"));
1234 typeinfo_first
= typeinfo
;
1235 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1237 set_first_syntax_error
1238 (_("type mismatch in vector register list"));
1243 for (i
= val_range
; i
<= val
; i
++)
1245 ret_val
|= i
<< (5 * nb_regs
);
1250 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1252 skip_whitespace (str
);
1255 set_first_syntax_error (_("end of vector register list not found"));
1260 skip_whitespace (str
);
1264 if (skip_past_char (&str
, '['))
1268 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1269 if (exp
.X_op
!= O_constant
)
1271 set_first_syntax_error (_("constant expression required."));
1274 if (! skip_past_char (&str
, ']'))
1277 typeinfo_first
.index
= exp
.X_add_number
;
1281 set_first_syntax_error (_("expected index"));
1288 set_first_syntax_error (_("too many registers in vector register list"));
1291 else if (nb_regs
== 0)
1293 set_first_syntax_error (_("empty vector register list"));
1299 *vectype
= typeinfo_first
;
1301 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1304 /* Directives: register aliases. */
1307 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1312 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1315 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1318 /* Only warn about a redefinition if it's not defined as the
1320 else if (new->number
!= number
|| new->type
!= type
)
1321 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1326 name
= xstrdup (str
);
1327 new = XNEW (reg_entry
);
1330 new->number
= number
;
1332 new->builtin
= FALSE
;
1334 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1339 /* Look for the .req directive. This is of the form:
1341 new_register_name .req existing_register_name
1343 If we find one, or if it looks sufficiently like one that we want to
1344 handle any error here, return TRUE. Otherwise return FALSE. */
1347 create_register_alias (char *newname
, char *p
)
1349 const reg_entry
*old
;
1350 char *oldname
, *nbuf
;
1353 /* The input scrubber ensures that whitespace after the mnemonic is
1354 collapsed to single spaces. */
1356 if (strncmp (oldname
, " .req ", 6) != 0)
1360 if (*oldname
== '\0')
1363 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1366 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1370 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1371 the desired alias name, and p points to its end. If not, then
1372 the desired alias name is in the global original_case_string. */
1373 #ifdef TC_CASE_SENSITIVE
1376 newname
= original_case_string
;
1377 nlen
= strlen (newname
);
1380 nbuf
= xmemdup0 (newname
, nlen
);
1382 /* Create aliases under the new name as stated; an all-lowercase
1383 version of the new name; and an all-uppercase version of the new
1385 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1387 for (p
= nbuf
; *p
; p
++)
1390 if (strncmp (nbuf
, newname
, nlen
))
1392 /* If this attempt to create an additional alias fails, do not bother
1393 trying to create the all-lower case alias. We will fail and issue
1394 a second, duplicate error message. This situation arises when the
1395 programmer does something like:
1398 The second .req creates the "Foo" alias but then fails to create
1399 the artificial FOO alias because it has already been created by the
1401 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1408 for (p
= nbuf
; *p
; p
++)
1411 if (strncmp (nbuf
, newname
, nlen
))
1412 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1419 /* Should never be called, as .req goes between the alias and the
1420 register name, not at the beginning of the line. */
1422 s_req (int a ATTRIBUTE_UNUSED
)
1424 as_bad (_("invalid syntax for .req directive"));
1427 /* The .unreq directive deletes an alias which was previously defined
1428 by .req. For example:
1434 s_unreq (int a ATTRIBUTE_UNUSED
)
1439 name
= input_line_pointer
;
1441 while (*input_line_pointer
!= 0
1442 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1443 ++input_line_pointer
;
1445 saved_char
= *input_line_pointer
;
1446 *input_line_pointer
= 0;
1449 as_bad (_("invalid syntax for .unreq directive"));
1452 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1455 as_bad (_("unknown register alias '%s'"), name
);
1456 else if (reg
->builtin
)
1457 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1464 str_hash_delete (aarch64_reg_hsh
, name
);
1465 free ((char *) reg
->name
);
1468 /* Also locate the all upper case and all lower case versions.
1469 Do not complain if we cannot find one or the other as it
1470 was probably deleted above. */
1472 nbuf
= strdup (name
);
1473 for (p
= nbuf
; *p
; p
++)
1475 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1478 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1479 free ((char *) reg
->name
);
1483 for (p
= nbuf
; *p
; p
++)
1485 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1488 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1489 free ((char *) reg
->name
);
1497 *input_line_pointer
= saved_char
;
1498 demand_empty_rest_of_line ();
1501 /* Directives: Instruction set selection. */
1504 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1505 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1506 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1507 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1509 /* Create a new mapping symbol for the transition to STATE. */
1512 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1515 const char *symname
;
1522 type
= BSF_NO_FLAGS
;
1526 type
= BSF_NO_FLAGS
;
1532 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1533 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1535 /* Save the mapping symbols for future reference. Also check that
1536 we do not place two mapping symbols at the same offset within a
1537 frag. We'll handle overlap between frags in
1538 check_mapping_symbols.
1540 If .fill or other data filling directive generates zero sized data,
1541 the mapping symbol for the following code will have the same value
1542 as the one generated for the data filling directive. In this case,
1543 we replace the old symbol with the new one at the same address. */
1546 if (frag
->tc_frag_data
.first_map
!= NULL
)
1548 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1549 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1552 frag
->tc_frag_data
.first_map
= symbolP
;
1554 if (frag
->tc_frag_data
.last_map
!= NULL
)
1556 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1557 S_GET_VALUE (symbolP
));
1558 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1559 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1562 frag
->tc_frag_data
.last_map
= symbolP
;
1565 /* We must sometimes convert a region marked as code to data during
1566 code alignment, if an odd number of bytes have to be padded. The
1567 code mapping symbol is pushed to an aligned address. */
1570 insert_data_mapping_symbol (enum mstate state
,
1571 valueT value
, fragS
* frag
, offsetT bytes
)
1573 /* If there was already a mapping symbol, remove it. */
1574 if (frag
->tc_frag_data
.last_map
!= NULL
1575 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1576 frag
->fr_address
+ value
)
1578 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1582 know (frag
->tc_frag_data
.first_map
== symp
);
1583 frag
->tc_frag_data
.first_map
= NULL
;
1585 frag
->tc_frag_data
.last_map
= NULL
;
1586 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1589 make_mapping_symbol (MAP_DATA
, value
, frag
);
1590 make_mapping_symbol (state
, value
+ bytes
, frag
);
1593 static void mapping_state_2 (enum mstate state
, int max_chars
);
1595 /* Set the mapping state to STATE. Only call this when about to
1596 emit some STATE bytes to the file. */
1599 mapping_state (enum mstate state
)
1601 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1603 if (state
== MAP_INSN
)
1604 /* AArch64 instructions require 4-byte alignment. When emitting
1605 instructions into any section, record the appropriate section
1607 record_alignment (now_seg
, 2);
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1615 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1616 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1617 evaluated later in the next else. */
1619 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1621 /* Only add the symbol if the offset is > 0:
1622 if we're at the first frag, check it's size > 0;
1623 if we're not at the first frag, then for sure
1624 the offset is > 0. */
1625 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1626 const int add_symbol
= (frag_now
!= frag_first
)
1627 || (frag_now_fix () > 0);
1630 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1634 mapping_state_2 (state
, 0);
1637 /* Same as mapping_state, but MAX_CHARS bytes have already been
1638 allocated. Put the mapping symbol that far back. */
1641 mapping_state_2 (enum mstate state
, int max_chars
)
1643 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1645 if (!SEG_NORMAL (now_seg
))
1648 if (mapstate
== state
)
1649 /* The mapping symbol has already been emitted.
1650 There is nothing else to do. */
1653 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1654 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1657 #define mapping_state(x) /* nothing */
1658 #define mapping_state_2(x, y) /* nothing */
1661 /* Directives: sectioning and alignment. */
1664 s_bss (int ignore ATTRIBUTE_UNUSED
)
1666 /* We don't support putting frags in the BSS segment, we fake it by
1667 marking in_bss, then looking at s_skip for clues. */
1668 subseg_set (bss_section
, 0);
1669 demand_empty_rest_of_line ();
1670 mapping_state (MAP_DATA
);
1674 s_even (int ignore ATTRIBUTE_UNUSED
)
1676 /* Never make frag if expect extra pass. */
1678 frag_align (1, 0, 0);
1680 record_alignment (now_seg
, 1);
1682 demand_empty_rest_of_line ();
1685 /* Directives: Literal pools. */
1687 static literal_pool
*
1688 find_literal_pool (int size
)
1692 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1694 if (pool
->section
== now_seg
1695 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1702 static literal_pool
*
1703 find_or_make_literal_pool (int size
)
1705 /* Next literal pool ID number. */
1706 static unsigned int latest_pool_num
= 1;
1709 pool
= find_literal_pool (size
);
1713 /* Create a new pool. */
1714 pool
= XNEW (literal_pool
);
1718 /* Currently we always put the literal pool in the current text
1719 section. If we were generating "small" model code where we
1720 knew that all code and initialised data was within 1MB then
1721 we could output literals to mergeable, read-only data
1724 pool
->next_free_entry
= 0;
1725 pool
->section
= now_seg
;
1726 pool
->sub_section
= now_subseg
;
1728 pool
->next
= list_of_pools
;
1729 pool
->symbol
= NULL
;
1731 /* Add it to the list. */
1732 list_of_pools
= pool
;
1735 /* New pools, and emptied pools, will have a NULL symbol. */
1736 if (pool
->symbol
== NULL
)
1738 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1739 &zero_address_frag
, 0);
1740 pool
->id
= latest_pool_num
++;
1747 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1748 Return TRUE on success, otherwise return FALSE. */
1750 add_to_lit_pool (expressionS
*exp
, int size
)
1755 pool
= find_or_make_literal_pool (size
);
1757 /* Check if this literal value is already in the pool. */
1758 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1760 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1762 if ((litexp
->X_op
== exp
->X_op
)
1763 && (exp
->X_op
== O_constant
)
1764 && (litexp
->X_add_number
== exp
->X_add_number
)
1765 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1768 if ((litexp
->X_op
== exp
->X_op
)
1769 && (exp
->X_op
== O_symbol
)
1770 && (litexp
->X_add_number
== exp
->X_add_number
)
1771 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1772 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1776 /* Do we need to create a new entry? */
1777 if (entry
== pool
->next_free_entry
)
1779 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1781 set_syntax_error (_("literal pool overflow"));
1785 pool
->literals
[entry
].exp
= *exp
;
1786 pool
->next_free_entry
+= 1;
1787 if (exp
->X_op
== O_big
)
1789 /* PR 16688: Bignums are held in a single global array. We must
1790 copy and preserve that value now, before it is overwritten. */
1791 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1793 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1794 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1797 pool
->literals
[entry
].bignum
= NULL
;
1800 exp
->X_op
= O_symbol
;
1801 exp
->X_add_number
= ((int) entry
) * size
;
1802 exp
->X_add_symbol
= pool
->symbol
;
1807 /* Can't use symbol_new here, so have to create a symbol and then at
1808 a later date assign it a value. That's what these functions do. */
1811 symbol_locate (symbolS
* symbolP
,
1812 const char *name
,/* It is copied, the caller can modify. */
1813 segT segment
, /* Segment identifier (SEG_<something>). */
1814 valueT valu
, /* Symbol value. */
1815 fragS
* frag
) /* Associated fragment. */
1818 char *preserved_copy_of_name
;
1820 name_length
= strlen (name
) + 1; /* +1 for \0. */
1821 obstack_grow (¬es
, name
, name_length
);
1822 preserved_copy_of_name
= obstack_finish (¬es
);
1824 #ifdef tc_canonicalize_symbol_name
1825 preserved_copy_of_name
=
1826 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1829 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1831 S_SET_SEGMENT (symbolP
, segment
);
1832 S_SET_VALUE (symbolP
, valu
);
1833 symbol_clear_list_pointers (symbolP
);
1835 symbol_set_frag (symbolP
, frag
);
1837 /* Link to end of symbol chain. */
1839 extern int symbol_table_frozen
;
1841 if (symbol_table_frozen
)
1845 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1847 obj_symbol_new_hook (symbolP
);
1849 #ifdef tc_symbol_new_hook
1850 tc_symbol_new_hook (symbolP
);
1854 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1855 #endif /* DEBUG_SYMS */
1860 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1867 for (align
= 2; align
<= 4; align
++)
1869 int size
= 1 << align
;
1871 pool
= find_literal_pool (size
);
1872 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1875 /* Align pool as you have word accesses.
1876 Only make a frag if we have to. */
1878 frag_align (align
, 0, 0);
1880 mapping_state (MAP_DATA
);
1882 record_alignment (now_seg
, align
);
1884 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1886 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1887 (valueT
) frag_now_fix (), frag_now
);
1888 symbol_table_insert (pool
->symbol
);
1890 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1892 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1894 if (exp
->X_op
== O_big
)
1896 /* PR 16688: Restore the global bignum value. */
1897 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1898 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1899 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1902 /* First output the expression in the instruction to the pool. */
1903 emit_expr (exp
, size
); /* .word|.xword */
1905 if (exp
->X_op
== O_big
)
1907 free (pool
->literals
[entry
].bignum
);
1908 pool
->literals
[entry
].bignum
= NULL
;
1912 /* Mark the pool as empty. */
1913 pool
->next_free_entry
= 0;
1914 pool
->symbol
= NULL
;
1919 /* Forward declarations for functions below, in the MD interface
1921 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1922 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1924 /* Directives: Data. */
1925 /* N.B. the support for relocation suffix in this directive needs to be
1926 implemented properly. */
1929 s_aarch64_elf_cons (int nbytes
)
1933 #ifdef md_flush_pending_output
1934 md_flush_pending_output ();
1937 if (is_it_end_of_statement ())
1939 demand_empty_rest_of_line ();
1943 #ifdef md_cons_align
1944 md_cons_align (nbytes
);
1947 mapping_state (MAP_DATA
);
1950 struct reloc_table_entry
*reloc
;
1954 if (exp
.X_op
!= O_symbol
)
1955 emit_expr (&exp
, (unsigned int) nbytes
);
1958 skip_past_char (&input_line_pointer
, '#');
1959 if (skip_past_char (&input_line_pointer
, ':'))
1961 reloc
= find_reloc_table_entry (&input_line_pointer
);
1963 as_bad (_("unrecognized relocation suffix"));
1965 as_bad (_("unimplemented relocation suffix"));
1966 ignore_rest_of_line ();
1970 emit_expr (&exp
, (unsigned int) nbytes
);
1973 while (*input_line_pointer
++ == ',');
1975 /* Put terminator back into stream. */
1976 input_line_pointer
--;
1977 demand_empty_rest_of_line ();
1980 /* Mark symbol that it follows a variant PCS convention. */
1983 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1989 elf_symbol_type
*elfsym
;
1991 c
= get_symbol_name (&name
);
1993 as_bad (_("Missing symbol name in directive"));
1994 sym
= symbol_find_or_make (name
);
1995 restore_line_pointer (c
);
1996 demand_empty_rest_of_line ();
1997 bfdsym
= symbol_get_bfdsym (sym
);
1998 elfsym
= elf_symbol_from (bfdsym
);
1999 gas_assert (elfsym
);
2000 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2002 #endif /* OBJ_ELF */
2004 /* Output a 32-bit word, but mark as an instruction. */
2007 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2011 #ifdef md_flush_pending_output
2012 md_flush_pending_output ();
2015 if (is_it_end_of_statement ())
2017 demand_empty_rest_of_line ();
2021 /* Sections are assumed to start aligned. In executable section, there is no
2022 MAP_DATA symbol pending. So we only align the address during
2023 MAP_DATA --> MAP_INSN transition.
2024 For other sections, this is not guaranteed. */
2025 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2026 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2027 frag_align_code (2, 0);
2030 mapping_state (MAP_INSN
);
2036 if (exp
.X_op
!= O_constant
)
2038 as_bad (_("constant expression required"));
2039 ignore_rest_of_line ();
2043 if (target_big_endian
)
2045 unsigned int val
= exp
.X_add_number
;
2046 exp
.X_add_number
= SWAP_32 (val
);
2048 emit_expr (&exp
, 4);
2050 while (*input_line_pointer
++ == ',');
2052 /* Put terminator back into stream. */
2053 input_line_pointer
--;
2054 demand_empty_rest_of_line ();
2058 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2060 demand_empty_rest_of_line ();
2061 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2062 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2066 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2069 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2075 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2076 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2078 demand_empty_rest_of_line ();
2081 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2084 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2088 /* Since we're just labelling the code, there's no need to define a
2091 /* Make sure there is enough room in this frag for the following
2092 blr. This trick only works if the blr follows immediately after
2093 the .tlsdesc directive. */
2095 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2096 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2098 demand_empty_rest_of_line ();
2101 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2104 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2110 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2111 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2113 demand_empty_rest_of_line ();
2115 #endif /* OBJ_ELF */
2117 static void s_aarch64_arch (int);
2118 static void s_aarch64_cpu (int);
2119 static void s_aarch64_arch_extension (int);
2121 /* This table describes all the machine specific pseudo-ops the assembler
2122 has to support. The fields are:
2123 pseudo-op name without dot
2124 function to call to execute this pseudo-op
2125 Integer arg to pass to the function. */
2127 const pseudo_typeS md_pseudo_table
[] = {
2128 /* Never called because '.req' does not start a line. */
2130 {"unreq", s_unreq
, 0},
2132 {"even", s_even
, 0},
2133 {"ltorg", s_ltorg
, 0},
2134 {"pool", s_ltorg
, 0},
2135 {"cpu", s_aarch64_cpu
, 0},
2136 {"arch", s_aarch64_arch
, 0},
2137 {"arch_extension", s_aarch64_arch_extension
, 0},
2138 {"inst", s_aarch64_inst
, 0},
2139 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2141 {"tlsdescadd", s_tlsdescadd
, 0},
2142 {"tlsdesccall", s_tlsdesccall
, 0},
2143 {"tlsdescldr", s_tlsdescldr
, 0},
2144 {"word", s_aarch64_elf_cons
, 4},
2145 {"long", s_aarch64_elf_cons
, 4},
2146 {"xword", s_aarch64_elf_cons
, 8},
2147 {"dword", s_aarch64_elf_cons
, 8},
2148 {"variant_pcs", s_variant_pcs
, 0},
2150 {"float16", float_cons
, 'h'},
2151 {"bfloat16", float_cons
, 'b'},
2156 /* Check whether STR points to a register name followed by a comma or the
2157 end of line; REG_TYPE indicates which register types are checked
2158 against. Return TRUE if STR is such a register name; otherwise return
2159 FALSE. The function does not intend to produce any diagnostics, but since
2160 the register parser aarch64_reg_parse, which is called by this function,
2161 does produce diagnostics, we call clear_error to clear any diagnostics
2162 that may be generated by aarch64_reg_parse.
2163 Also, the function returns FALSE directly if there is any user error
2164 present at the function entry. This prevents the existing diagnostics
2165 state from being spoiled.
2166 The function currently serves parse_constant_immediate and
2167 parse_big_immediate only. */
2169 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2173 /* Prevent the diagnostics state from being spoiled. */
2177 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2179 /* Clear the parsing error that may be set by the reg parser. */
2182 if (reg
== PARSE_FAIL
)
2185 skip_whitespace (str
);
2186 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2192 /* Parser functions used exclusively in instruction operands. */
2194 /* Parse an immediate expression which may not be constant.
2196 To prevent the expression parser from pushing a register name
2197 into the symbol table as an undefined symbol, firstly a check is
2198 done to find out whether STR is a register of type REG_TYPE followed
2199 by a comma or the end of line. Return FALSE if STR is such a string. */
2202 parse_immediate_expression (char **str
, expressionS
*exp
,
2203 aarch64_reg_type reg_type
)
2205 if (reg_name_p (*str
, reg_type
))
2207 set_recoverable_error (_("immediate operand required"));
2211 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2213 if (exp
->X_op
== O_absent
)
2215 set_fatal_syntax_error (_("missing immediate expression"));
2222 /* Constant immediate-value read function for use in insn parsing.
2223 STR points to the beginning of the immediate (with the optional
2224 leading #); *VAL receives the value. REG_TYPE says which register
2225 names should be treated as registers rather than as symbolic immediates.
2227 Return TRUE on success; otherwise return FALSE. */
2230 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2234 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2237 if (exp
.X_op
!= O_constant
)
2239 set_syntax_error (_("constant expression required"));
2243 *val
= exp
.X_add_number
;
2248 encode_imm_float_bits (uint32_t imm
)
2250 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2251 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2254 /* Return TRUE if the single-precision floating-point value encoded in IMM
2255 can be expressed in the AArch64 8-bit signed floating-point format with
2256 3-bit exponent and normalized 4 bits of precision; in other words, the
2257 floating-point value must be expressable as
2258 (+/-) n / 16 * power (2, r)
2259 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2262 aarch64_imm_float_p (uint32_t imm
)
2264 /* If a single-precision floating-point value has the following bit
2265 pattern, it can be expressed in the AArch64 8-bit floating-point
2268 3 32222222 2221111111111
2269 1 09876543 21098765432109876543210
2270 n Eeeeeexx xxxx0000000000000000000
2272 where n, e and each x are either 0 or 1 independently, with
2277 /* Prepare the pattern for 'Eeeeee'. */
2278 if (((imm
>> 30) & 0x1) == 0)
2279 pattern
= 0x3e000000;
2281 pattern
= 0x40000000;
2283 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2284 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2287 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2288 as an IEEE float without any loss of precision. Store the value in
2292 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2294 /* If a double-precision floating-point value has the following bit
2295 pattern, it can be expressed in a float:
2297 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2298 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2299 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2301 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2302 if Eeee_eeee != 1111_1111
2304 where n, e, s and S are either 0 or 1 independently and where ~ is the
2308 uint32_t high32
= imm
>> 32;
2309 uint32_t low32
= imm
;
2311 /* Lower 29 bits need to be 0s. */
2312 if ((imm
& 0x1fffffff) != 0)
2315 /* Prepare the pattern for 'Eeeeeeeee'. */
2316 if (((high32
>> 30) & 0x1) == 0)
2317 pattern
= 0x38000000;
2319 pattern
= 0x40000000;
2322 if ((high32
& 0x78000000) != pattern
)
2325 /* Check Eeee_eeee != 1111_1111. */
2326 if ((high32
& 0x7ff00000) == 0x47f00000)
2329 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2330 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2331 | (low32
>> 29)); /* 3 S bits. */
2335 /* Return true if we should treat OPERAND as a double-precision
2336 floating-point operand rather than a single-precision one. */
2338 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2340 /* Check for unsuffixed SVE registers, which are allowed
2341 for LDR and STR but not in instructions that require an
2342 immediate. We get better error messages if we arbitrarily
2343 pick one size, parse the immediate normally, and then
2344 report the match failure in the normal way. */
2345 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2346 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2349 /* Parse a floating-point immediate. Return TRUE on success and return the
2350 value in *IMMED in the format of IEEE754 single-precision encoding.
2351 *CCP points to the start of the string; DP_P is TRUE when the immediate
2352 is expected to be in double-precision (N.B. this only matters when
2353 hexadecimal representation is involved). REG_TYPE says which register
2354 names should be treated as registers rather than as symbolic immediates.
2356 This routine accepts any IEEE float; it is up to the callers to reject
2360 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2361 aarch64_reg_type reg_type
)
2365 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2367 unsigned fpword
= 0;
2368 bfd_boolean hex_p
= FALSE
;
2370 skip_past_char (&str
, '#');
2373 skip_whitespace (fpnum
);
2375 if (strncmp (fpnum
, "0x", 2) == 0)
2377 /* Support the hexadecimal representation of the IEEE754 encoding.
2378 Double-precision is expected when DP_P is TRUE, otherwise the
2379 representation should be in single-precision. */
2380 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2385 if (!can_convert_double_to_float (val
, &fpword
))
2388 else if ((uint64_t) val
> 0xffffffff)
2395 else if (reg_name_p (str
, reg_type
))
2397 set_recoverable_error (_("immediate operand required"));
2405 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2408 /* Our FP word must be 32 bits (single-precision FP). */
2409 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2411 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2421 set_fatal_syntax_error (_("invalid floating-point constant"));
2425 /* Less-generic immediate-value read function with the possibility of loading
2426 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2429 To prevent the expression parser from pushing a register name into the
2430 symbol table as an undefined symbol, a check is firstly done to find
2431 out whether STR is a register of type REG_TYPE followed by a comma or
2432 the end of line. Return FALSE if STR is such a register. */
2435 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2439 if (reg_name_p (ptr
, reg_type
))
2441 set_syntax_error (_("immediate operand required"));
2445 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2447 if (inst
.reloc
.exp
.X_op
== O_constant
)
2448 *imm
= inst
.reloc
.exp
.X_add_number
;
2455 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2456 if NEED_LIBOPCODES is non-zero, the fixup will need
2457 assistance from the libopcodes. */
2460 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2461 const aarch64_opnd_info
*operand
,
2462 int need_libopcodes_p
)
2464 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2465 reloc
->opnd
= operand
->type
;
2466 if (need_libopcodes_p
)
2467 reloc
->need_libopcodes_p
= 1;
2470 /* Return TRUE if the instruction needs to be fixed up later internally by
2471 the GAS; otherwise return FALSE. */
2473 static inline bfd_boolean
2474 aarch64_gas_internal_fixup_p (void)
2476 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2479 /* Assign the immediate value to the relevant field in *OPERAND if
2480 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2481 needs an internal fixup in a later stage.
2482 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2483 IMM.VALUE that may get assigned with the constant. */
2485 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2486 aarch64_opnd_info
*operand
,
2488 int need_libopcodes_p
,
2491 if (reloc
->exp
.X_op
== O_constant
)
2494 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2496 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2497 reloc
->type
= BFD_RELOC_UNUSED
;
2501 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2502 /* Tell libopcodes to ignore this operand or not. This is helpful
2503 when one of the operands needs to be fixed up later but we need
2504 libopcodes to check the other operands. */
2505 operand
->skip
= skip_p
;
2509 /* Relocation modifiers. Each entry in the table contains the textual
2510 name for the relocation which may be placed before a symbol used as
2511 a load/store offset, or add immediate. It must be surrounded by a
2512 leading and trailing colon, for example:
2514 ldr x0, [x1, #:rello:varsym]
2515 add x0, x1, #:rello:varsym */
2517 struct reloc_table_entry
2521 bfd_reloc_code_real_type adr_type
;
2522 bfd_reloc_code_real_type adrp_type
;
2523 bfd_reloc_code_real_type movw_type
;
2524 bfd_reloc_code_real_type add_type
;
2525 bfd_reloc_code_real_type ldst_type
;
2526 bfd_reloc_code_real_type ld_literal_type
;
2529 static struct reloc_table_entry reloc_table
[] = {
2530 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2535 BFD_RELOC_AARCH64_ADD_LO12
,
2536 BFD_RELOC_AARCH64_LDST_LO12
,
2539 /* Higher 21 bits of pc-relative page offset: ADRP */
2542 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2548 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2551 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2557 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2561 BFD_RELOC_AARCH64_MOVW_G0
,
2566 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2570 BFD_RELOC_AARCH64_MOVW_G0_S
,
2575 /* Less significant bits 0-15 of address/value: MOVK, no check */
2579 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2584 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2588 BFD_RELOC_AARCH64_MOVW_G1
,
2593 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2597 BFD_RELOC_AARCH64_MOVW_G1_S
,
2602 /* Less significant bits 16-31 of address/value: MOVK, no check */
2606 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2611 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2615 BFD_RELOC_AARCH64_MOVW_G2
,
2620 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2624 BFD_RELOC_AARCH64_MOVW_G2_S
,
2629 /* Less significant bits 32-47 of address/value: MOVK, no check */
2633 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2638 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2642 BFD_RELOC_AARCH64_MOVW_G3
,
2647 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2651 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2656 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2660 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2665 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2669 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2674 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2678 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2683 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2687 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2692 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2696 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2701 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2705 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2710 /* Get to the page containing GOT entry for a symbol. */
2713 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2717 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2719 /* 12 bit offset into the page containing GOT entry for that symbol. */
2725 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2728 /* 0-15 bits of address/value: MOVk, no check. */
2732 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2737 /* Most significant bits 16-31 of address/value: MOVZ. */
2741 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2746 /* 15 bit offset into the page containing GOT entry for that symbol. */
2752 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2755 /* Get to the page containing GOT TLS entry for a symbol */
2756 {"gottprel_g0_nc", 0,
2759 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2764 /* Get to the page containing GOT TLS entry for a symbol */
2768 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2773 /* Get to the page containing GOT TLS entry for a symbol */
2775 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2776 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2782 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2787 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2791 /* Lower 16 bits address/value: MOVk. */
2795 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2800 /* Most significant bits 16-31 of address/value: MOVZ. */
2804 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2809 /* Get to the page containing GOT TLS entry for a symbol */
2811 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2812 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2816 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2818 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2823 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2824 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2827 /* Get to the page containing GOT TLS entry for a symbol.
2828 The same as GD, we allocate two consecutive GOT slots
2829 for module index and module offset, the only difference
2830 with GD is the module offset should be initialized to
2831 zero without any outstanding runtime relocation. */
2833 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2834 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2840 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2841 {"tlsldm_lo12_nc", 0,
2845 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2849 /* 12 bit offset into the module TLS base address. */
2854 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2855 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2858 /* Same as dtprel_lo12, no overflow check. */
2859 {"dtprel_lo12_nc", 0,
2863 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2864 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2867 /* bits[23:12] of offset to the module TLS base address. */
2872 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2876 /* bits[15:0] of offset to the module TLS base address. */
2880 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2885 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2889 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2894 /* bits[31:16] of offset to the module TLS base address. */
2898 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2903 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2907 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2912 /* bits[47:32] of offset to the module TLS base address. */
2916 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2921 /* Lower 16 bit offset into GOT entry for a symbol */
2922 {"tlsdesc_off_g0_nc", 0,
2925 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2930 /* Higher 16 bit offset into GOT entry for a symbol */
2931 {"tlsdesc_off_g1", 0,
2934 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2939 /* Get to the page containing GOT TLS entry for a symbol */
2942 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2946 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2948 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2949 {"gottprel_lo12", 0,
2954 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2957 /* Get tp offset for a symbol. */
2962 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2966 /* Get tp offset for a symbol. */
2971 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2972 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2975 /* Get tp offset for a symbol. */
2980 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2984 /* Get tp offset for a symbol. */
2985 {"tprel_lo12_nc", 0,
2989 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2990 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2993 /* Most significant bits 32-47 of address/value: MOVZ. */
2997 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3002 /* Most significant bits 16-31 of address/value: MOVZ. */
3006 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3011 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3015 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3020 /* Most significant bits 0-15 of address/value: MOVZ. */
3024 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3029 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3033 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3038 /* 15bit offset from got entry to base address of GOT table. */
3044 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3047 /* 14bit offset from got entry to base address of GOT table. */
3053 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3057 /* Given the address of a pointer pointing to the textual name of a
3058 relocation as may appear in assembler source, attempt to find its
3059 details in reloc_table. The pointer will be updated to the character
3060 after the trailing colon. On failure, NULL will be returned;
3061 otherwise return the reloc_table_entry. */
3063 static struct reloc_table_entry
*
3064 find_reloc_table_entry (char **str
)
3067 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3069 int length
= strlen (reloc_table
[i
].name
);
3071 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3072 && (*str
)[length
] == ':')
3074 *str
+= (length
+ 1);
3075 return &reloc_table
[i
];
3082 /* Mode argument to parse_shift and parser_shifter_operand. */
3083 enum parse_shift_mode
3085 SHIFTED_NONE
, /* no shifter allowed */
3086 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3088 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3090 SHIFTED_LSL
, /* bare "lsl #n" */
3091 SHIFTED_MUL
, /* bare "mul #n" */
3092 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3093 SHIFTED_MUL_VL
, /* "mul vl" */
3094 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3097 /* Parse a <shift> operator on an AArch64 data processing instruction.
3098 Return TRUE on success; otherwise return FALSE. */
3100 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3102 const struct aarch64_name_value_pair
*shift_op
;
3103 enum aarch64_modifier_kind kind
;
3109 for (p
= *str
; ISALPHA (*p
); p
++)
3114 set_syntax_error (_("shift expression expected"));
3118 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3120 if (shift_op
== NULL
)
3122 set_syntax_error (_("shift operator expected"));
3126 kind
= aarch64_get_operand_modifier (shift_op
);
3128 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3130 set_syntax_error (_("invalid use of 'MSL'"));
3134 if (kind
== AARCH64_MOD_MUL
3135 && mode
!= SHIFTED_MUL
3136 && mode
!= SHIFTED_MUL_VL
)
3138 set_syntax_error (_("invalid use of 'MUL'"));
3144 case SHIFTED_LOGIC_IMM
:
3145 if (aarch64_extend_operator_p (kind
))
3147 set_syntax_error (_("extending shift is not permitted"));
3152 case SHIFTED_ARITH_IMM
:
3153 if (kind
== AARCH64_MOD_ROR
)
3155 set_syntax_error (_("'ROR' shift is not permitted"));
3161 if (kind
!= AARCH64_MOD_LSL
)
3163 set_syntax_error (_("only 'LSL' shift is permitted"));
3169 if (kind
!= AARCH64_MOD_MUL
)
3171 set_syntax_error (_("only 'MUL' is permitted"));
3176 case SHIFTED_MUL_VL
:
3177 /* "MUL VL" consists of two separate tokens. Require the first
3178 token to be "MUL" and look for a following "VL". */
3179 if (kind
== AARCH64_MOD_MUL
)
3181 skip_whitespace (p
);
3182 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3185 kind
= AARCH64_MOD_MUL_VL
;
3189 set_syntax_error (_("only 'MUL VL' is permitted"));
3192 case SHIFTED_REG_OFFSET
:
3193 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3194 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3196 set_fatal_syntax_error
3197 (_("invalid shift for the register offset addressing mode"));
3202 case SHIFTED_LSL_MSL
:
3203 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3205 set_syntax_error (_("invalid shift operator"));
3214 /* Whitespace can appear here if the next thing is a bare digit. */
3215 skip_whitespace (p
);
3217 /* Parse shift amount. */
3219 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3220 exp
.X_op
= O_absent
;
3223 if (is_immediate_prefix (*p
))
3228 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3230 if (kind
== AARCH64_MOD_MUL_VL
)
3231 /* For consistency, give MUL VL the same shift amount as an implicit
3233 operand
->shifter
.amount
= 1;
3234 else if (exp
.X_op
== O_absent
)
3236 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3238 set_syntax_error (_("missing shift amount"));
3241 operand
->shifter
.amount
= 0;
3243 else if (exp
.X_op
!= O_constant
)
3245 set_syntax_error (_("constant shift amount required"));
3248 /* For parsing purposes, MUL #n has no inherent range. The range
3249 depends on the operand and will be checked by operand-specific
3251 else if (kind
!= AARCH64_MOD_MUL
3252 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3254 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3259 operand
->shifter
.amount
= exp
.X_add_number
;
3260 operand
->shifter
.amount_present
= 1;
3263 operand
->shifter
.operator_present
= 1;
3264 operand
->shifter
.kind
= kind
;
3270 /* Parse a <shifter_operand> for a data processing instruction:
3273 #<immediate>, LSL #imm
3275 Validation of immediate operands is deferred to md_apply_fix.
3277 Return TRUE on success; otherwise return FALSE. */
3280 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3281 enum parse_shift_mode mode
)
3285 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3290 /* Accept an immediate expression. */
3291 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3294 /* Accept optional LSL for arithmetic immediate values. */
3295 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3296 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3299 /* Not accept any shifter for logical immediate values. */
3300 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3301 && parse_shift (&p
, operand
, mode
))
3303 set_syntax_error (_("unexpected shift operator"));
3311 /* Parse a <shifter_operand> for a data processing instruction:
3316 #<immediate>, LSL #imm
3318 where <shift> is handled by parse_shift above, and the last two
3319 cases are handled by the function above.
3321 Validation of immediate operands is deferred to md_apply_fix.
3323 Return TRUE on success; otherwise return FALSE. */
3326 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3327 enum parse_shift_mode mode
)
3329 const reg_entry
*reg
;
3330 aarch64_opnd_qualifier_t qualifier
;
3331 enum aarch64_operand_class opd_class
3332 = aarch64_get_operand_class (operand
->type
);
3334 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3337 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3339 set_syntax_error (_("unexpected register in the immediate operand"));
3343 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3345 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3349 operand
->reg
.regno
= reg
->number
;
3350 operand
->qualifier
= qualifier
;
3352 /* Accept optional shift operation on register. */
3353 if (! skip_past_comma (str
))
3356 if (! parse_shift (str
, operand
, mode
))
3361 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3364 (_("integer register expected in the extended/shifted operand "
3369 /* We have a shifted immediate variable. */
3370 return parse_shifter_operand_imm (str
, operand
, mode
);
3373 /* Return TRUE on success; return FALSE otherwise. */
3376 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3377 enum parse_shift_mode mode
)
3381 /* Determine if we have the sequence of characters #: or just :
3382 coming next. If we do, then we check for a :rello: relocation
3383 modifier. If we don't, punt the whole lot to
3384 parse_shifter_operand. */
3386 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3388 struct reloc_table_entry
*entry
;
3396 /* Try to parse a relocation. Anything else is an error. */
3397 if (!(entry
= find_reloc_table_entry (str
)))
3399 set_syntax_error (_("unknown relocation modifier"));
3403 if (entry
->add_type
== 0)
3406 (_("this relocation modifier is not allowed on this instruction"));
3410 /* Save str before we decompose it. */
3413 /* Next, we parse the expression. */
3414 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3417 /* Record the relocation type (use the ADD variant here). */
3418 inst
.reloc
.type
= entry
->add_type
;
3419 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3421 /* If str is empty, we've reached the end, stop here. */
3425 /* Otherwise, we have a shifted reloc modifier, so rewind to
3426 recover the variable name and continue parsing for the shifter. */
3428 return parse_shifter_operand_imm (str
, operand
, mode
);
3431 return parse_shifter_operand (str
, operand
, mode
);
3434 /* Parse all forms of an address expression. Information is written
3435 to *OPERAND and/or inst.reloc.
3437 The A64 instruction set has the following addressing modes:
3440 [base] // in SIMD ld/st structure
3441 [base{,#0}] // in ld/st exclusive
3443 [base,Xm{,LSL #imm}]
3444 [base,Xm,SXTX {#imm}]
3445 [base,Wm,(S|U)XTW {#imm}]
3447 [base]! // in ldraa/ldrab exclusive
3451 [base],Xm // in SIMD ld/st structure
3452 PC-relative (literal)
3456 [base,Zm.D{,LSL #imm}]
3457 [base,Zm.S,(S|U)XTW {#imm}]
3458 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3462 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3463 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3464 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3466 (As a convenience, the notation "=immediate" is permitted in conjunction
3467 with the pc-relative literal load instructions to automatically place an
3468 immediate value or symbolic address in a nearby literal pool and generate
3469 a hidden label which references it.)
3471 Upon a successful parsing, the address structure in *OPERAND will be
3472 filled in the following way:
3474 .base_regno = <base>
3475 .offset.is_reg // 1 if the offset is a register
3477 .offset.regno = <Rm>
3479 For different addressing modes defined in the A64 ISA:
3482 .pcrel=0; .preind=1; .postind=0; .writeback=0
3484 .pcrel=0; .preind=1; .postind=0; .writeback=1
3486 .pcrel=0; .preind=0; .postind=1; .writeback=1
3487 PC-relative (literal)
3488 .pcrel=1; .preind=1; .postind=0; .writeback=0
3490 The shift/extension information, if any, will be stored in .shifter.
3491 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3492 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3493 corresponding register.
3495 BASE_TYPE says which types of base register should be accepted and
3496 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3497 is the type of shifter that is allowed for immediate offsets,
3498 or SHIFTED_NONE if none.
3500 In all other respects, it is the caller's responsibility to check
3501 for addressing modes not supported by the instruction, and to set
3505 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3506 aarch64_opnd_qualifier_t
*base_qualifier
,
3507 aarch64_opnd_qualifier_t
*offset_qualifier
,
3508 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3509 enum parse_shift_mode imm_shift_mode
)
3512 const reg_entry
*reg
;
3513 expressionS
*exp
= &inst
.reloc
.exp
;
3515 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3516 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3517 if (! skip_past_char (&p
, '['))
3519 /* =immediate or label. */
3520 operand
->addr
.pcrel
= 1;
3521 operand
->addr
.preind
= 1;
3523 /* #:<reloc_op>:<symbol> */
3524 skip_past_char (&p
, '#');
3525 if (skip_past_char (&p
, ':'))
3527 bfd_reloc_code_real_type ty
;
3528 struct reloc_table_entry
*entry
;
3530 /* Try to parse a relocation modifier. Anything else is
3532 entry
= find_reloc_table_entry (&p
);
3535 set_syntax_error (_("unknown relocation modifier"));
3539 switch (operand
->type
)
3541 case AARCH64_OPND_ADDR_PCREL21
:
3543 ty
= entry
->adr_type
;
3547 ty
= entry
->ld_literal_type
;
3554 (_("this relocation modifier is not allowed on this "
3560 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3562 set_syntax_error (_("invalid relocation expression"));
3566 /* #:<reloc_op>:<expr> */
3567 /* Record the relocation type. */
3568 inst
.reloc
.type
= ty
;
3569 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3574 if (skip_past_char (&p
, '='))
3575 /* =immediate; need to generate the literal in the literal pool. */
3576 inst
.gen_lit_pool
= 1;
3578 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3580 set_syntax_error (_("invalid address"));
3591 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3592 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3594 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3597 operand
->addr
.base_regno
= reg
->number
;
3600 if (skip_past_comma (&p
))
3603 operand
->addr
.preind
= 1;
3605 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3608 if (!aarch64_check_reg_type (reg
, offset_type
))
3610 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3615 operand
->addr
.offset
.regno
= reg
->number
;
3616 operand
->addr
.offset
.is_reg
= 1;
3617 /* Shifted index. */
3618 if (skip_past_comma (&p
))
3621 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3622 /* Use the diagnostics set in parse_shift, so not set new
3623 error message here. */
3627 [base,Xm] # For vector plus scalar SVE2 indexing.
3628 [base,Xm{,LSL #imm}]
3629 [base,Xm,SXTX {#imm}]
3630 [base,Wm,(S|U)XTW {#imm}] */
3631 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3632 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3633 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3635 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3637 set_syntax_error (_("invalid use of 32-bit register offset"));
3640 if (aarch64_get_qualifier_esize (*base_qualifier
)
3641 != aarch64_get_qualifier_esize (*offset_qualifier
)
3642 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3643 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3644 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3646 set_syntax_error (_("offset has different size from base"));
3650 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3652 set_syntax_error (_("invalid use of 64-bit register offset"));
3658 /* [Xn,#:<reloc_op>:<symbol> */
3659 skip_past_char (&p
, '#');
3660 if (skip_past_char (&p
, ':'))
3662 struct reloc_table_entry
*entry
;
3664 /* Try to parse a relocation modifier. Anything else is
3666 if (!(entry
= find_reloc_table_entry (&p
)))
3668 set_syntax_error (_("unknown relocation modifier"));
3672 if (entry
->ldst_type
== 0)
3675 (_("this relocation modifier is not allowed on this "
3680 /* [Xn,#:<reloc_op>: */
3681 /* We now have the group relocation table entry corresponding to
3682 the name in the assembler source. Next, we parse the
3684 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3686 set_syntax_error (_("invalid relocation expression"));
3690 /* [Xn,#:<reloc_op>:<expr> */
3691 /* Record the load/store relocation type. */
3692 inst
.reloc
.type
= entry
->ldst_type
;
3693 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3697 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3699 set_syntax_error (_("invalid expression in the address"));
3703 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3704 /* [Xn,<expr>,<shifter> */
3705 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3711 if (! skip_past_char (&p
, ']'))
3713 set_syntax_error (_("']' expected"));
3717 if (skip_past_char (&p
, '!'))
3719 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3721 set_syntax_error (_("register offset not allowed in pre-indexed "
3722 "addressing mode"));
3726 operand
->addr
.writeback
= 1;
3728 else if (skip_past_comma (&p
))
3731 operand
->addr
.postind
= 1;
3732 operand
->addr
.writeback
= 1;
3734 if (operand
->addr
.preind
)
3736 set_syntax_error (_("cannot combine pre- and post-indexing"));
3740 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3744 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3746 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3750 operand
->addr
.offset
.regno
= reg
->number
;
3751 operand
->addr
.offset
.is_reg
= 1;
3753 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3756 set_syntax_error (_("invalid expression in the address"));
3761 /* If at this point neither .preind nor .postind is set, we have a
3762 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3763 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3764 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3766 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3768 if (operand
->addr
.writeback
)
3770 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3772 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3773 operand
->addr
.offset
.is_reg
= 0;
3774 operand
->addr
.offset
.imm
= 0;
3775 operand
->addr
.preind
= 1;
3780 set_syntax_error (_("missing offset in the pre-indexed address"));
3786 operand
->addr
.preind
= 1;
3787 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3789 operand
->addr
.offset
.is_reg
= 1;
3790 operand
->addr
.offset
.regno
= REG_ZR
;
3791 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3795 inst
.reloc
.exp
.X_op
= O_constant
;
3796 inst
.reloc
.exp
.X_add_number
= 0;
3805 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3808 parse_address (char **str
, aarch64_opnd_info
*operand
)
3810 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3811 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3812 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3815 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3816 The arguments have the same meaning as for parse_address_main.
3817 Return TRUE on success. */
3819 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3820 aarch64_opnd_qualifier_t
*base_qualifier
,
3821 aarch64_opnd_qualifier_t
*offset_qualifier
)
3823 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3824 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3828 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3829 Return TRUE on success; otherwise return FALSE. */
3831 parse_half (char **str
, int *internal_fixup_p
)
3835 skip_past_char (&p
, '#');
3837 gas_assert (internal_fixup_p
);
3838 *internal_fixup_p
= 0;
3842 struct reloc_table_entry
*entry
;
3844 /* Try to parse a relocation. Anything else is an error. */
3846 if (!(entry
= find_reloc_table_entry (&p
)))
3848 set_syntax_error (_("unknown relocation modifier"));
3852 if (entry
->movw_type
== 0)
3855 (_("this relocation modifier is not allowed on this instruction"));
3859 inst
.reloc
.type
= entry
->movw_type
;
3862 *internal_fixup_p
= 1;
3864 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3871 /* Parse an operand for an ADRP instruction:
3873 Return TRUE on success; otherwise return FALSE. */
3876 parse_adrp (char **str
)
3883 struct reloc_table_entry
*entry
;
3885 /* Try to parse a relocation. Anything else is an error. */
3887 if (!(entry
= find_reloc_table_entry (&p
)))
3889 set_syntax_error (_("unknown relocation modifier"));
3893 if (entry
->adrp_type
== 0)
3896 (_("this relocation modifier is not allowed on this instruction"));
3900 inst
.reloc
.type
= entry
->adrp_type
;
3903 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3905 inst
.reloc
.pc_rel
= 1;
3907 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3914 /* Miscellaneous. */
3916 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3917 of SIZE tokens in which index I gives the token for field value I,
3918 or is null if field value I is invalid. REG_TYPE says which register
3919 names should be treated as registers rather than as symbolic immediates.
3921 Return true on success, moving *STR past the operand and storing the
3922 field value in *VAL. */
3925 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3926 size_t size
, aarch64_reg_type reg_type
)
3932 /* Match C-like tokens. */
3934 while (ISALNUM (*q
))
3937 for (i
= 0; i
< size
; ++i
)
3939 && strncasecmp (array
[i
], p
, q
- p
) == 0
3940 && array
[i
][q
- p
] == 0)
3947 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3950 if (exp
.X_op
== O_constant
3951 && (uint64_t) exp
.X_add_number
< size
)
3953 *val
= exp
.X_add_number
;
3958 /* Use the default error for this operand. */
3962 /* Parse an option for a preload instruction. Returns the encoding for the
3963 option, or PARSE_FAIL. */
3966 parse_pldop (char **str
)
3969 const struct aarch64_name_value_pair
*o
;
3972 while (ISALNUM (*q
))
3975 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3983 /* Parse an option for a barrier instruction. Returns the encoding for the
3984 option, or PARSE_FAIL. */
3987 parse_barrier (char **str
)
3990 const struct aarch64_name_value_pair
*o
;
3993 while (ISALPHA (*q
))
3996 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4004 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4005 return 0 if successful. Otherwise return PARSE_FAIL. */
4008 parse_barrier_psb (char **str
,
4009 const struct aarch64_name_value_pair
** hint_opt
)
4012 const struct aarch64_name_value_pair
*o
;
4015 while (ISALPHA (*q
))
4018 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4021 set_fatal_syntax_error
4022 ( _("unknown or missing option to PSB/TSB"));
4026 if (o
->value
!= 0x11)
4028 /* PSB only accepts option name 'CSYNC'. */
4030 (_("the specified option is not accepted for PSB/TSB"));
4039 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4040 return 0 if successful. Otherwise return PARSE_FAIL. */
4043 parse_bti_operand (char **str
,
4044 const struct aarch64_name_value_pair
** hint_opt
)
4047 const struct aarch64_name_value_pair
*o
;
4050 while (ISALPHA (*q
))
4053 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4056 set_fatal_syntax_error
4057 ( _("unknown option to BTI"));
4063 /* Valid BTI operands. */
4071 (_("unknown option to BTI"));
4080 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4081 Returns the encoding for the option, or PARSE_FAIL.
4083 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4084 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4086 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4087 field, otherwise as a system register.
4091 parse_sys_reg (char **str
, htab_t sys_regs
,
4092 int imple_defined_p
, int pstatefield_p
,
4096 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4097 const aarch64_sys_reg
*o
;
4101 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4102 if (p
< buf
+ (sizeof (buf
) - 1))
4103 *p
++ = TOLOWER (*q
);
4106 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4107 valid system register. This is enforced by construction of the hash
4109 if (p
- buf
!= q
- *str
)
4112 o
= str_hash_find (sys_regs
, buf
);
4115 if (!imple_defined_p
)
4119 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4120 unsigned int op0
, op1
, cn
, cm
, op2
;
4122 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4125 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4127 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4134 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4135 as_bad (_("selected processor does not support PSTATE field "
4138 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4139 o
->value
, o
->flags
, o
->features
))
4140 as_bad (_("selected processor does not support system register "
4142 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4143 as_warn (_("system register name '%s' is deprecated and may be "
4144 "removed in a future release"), buf
);
4154 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4155 for the option, or NULL. */
4157 static const aarch64_sys_ins_reg
*
4158 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4161 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4162 const aarch64_sys_ins_reg
*o
;
4165 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4166 if (p
< buf
+ (sizeof (buf
) - 1))
4167 *p
++ = TOLOWER (*q
);
4170 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4171 valid system register. This is enforced by construction of the hash
4173 if (p
- buf
!= q
- *str
)
4176 o
= str_hash_find (sys_ins_regs
, buf
);
4180 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4181 o
->name
, o
->value
, o
->flags
, 0))
4182 as_bad (_("selected processor does not support system register "
4184 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4185 as_warn (_("system register name '%s' is deprecated and may be "
4186 "removed in a future release"), buf
);
4192 #define po_char_or_fail(chr) do { \
4193 if (! skip_past_char (&str, chr)) \
4197 #define po_reg_or_fail(regtype) do { \
4198 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4199 if (val == PARSE_FAIL) \
4201 set_default_error (); \
4206 #define po_int_reg_or_fail(reg_type) do { \
4207 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4208 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4210 set_default_error (); \
4213 info->reg.regno = reg->number; \
4214 info->qualifier = qualifier; \
4217 #define po_imm_nc_or_fail() do { \
4218 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4222 #define po_imm_or_fail(min, max) do { \
4223 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4225 if (val < min || val > max) \
4227 set_fatal_syntax_error (_("immediate value out of range "\
4228 #min " to "#max)); \
4233 #define po_enum_or_fail(array) do { \
4234 if (!parse_enum_string (&str, &val, array, \
4235 ARRAY_SIZE (array), imm_reg_type)) \
4239 #define po_misc_or_fail(expr) do { \
4244 /* encode the 12-bit imm field of Add/sub immediate */
4245 static inline uint32_t
4246 encode_addsub_imm (uint32_t imm
)
4251 /* encode the shift amount field of Add/sub immediate */
4252 static inline uint32_t
4253 encode_addsub_imm_shift_amount (uint32_t cnt
)
4259 /* encode the imm field of Adr instruction */
4260 static inline uint32_t
4261 encode_adr_imm (uint32_t imm
)
4263 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4264 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4267 /* encode the immediate field of Move wide immediate */
4268 static inline uint32_t
4269 encode_movw_imm (uint32_t imm
)
4274 /* encode the 26-bit offset of unconditional branch */
4275 static inline uint32_t
4276 encode_branch_ofs_26 (uint32_t ofs
)
4278 return ofs
& ((1 << 26) - 1);
4281 /* encode the 19-bit offset of conditional branch and compare & branch */
4282 static inline uint32_t
4283 encode_cond_branch_ofs_19 (uint32_t ofs
)
4285 return (ofs
& ((1 << 19) - 1)) << 5;
4288 /* encode the 19-bit offset of ld literal */
4289 static inline uint32_t
4290 encode_ld_lit_ofs_19 (uint32_t ofs
)
4292 return (ofs
& ((1 << 19) - 1)) << 5;
4295 /* Encode the 14-bit offset of test & branch. */
4296 static inline uint32_t
4297 encode_tst_branch_ofs_14 (uint32_t ofs
)
4299 return (ofs
& ((1 << 14) - 1)) << 5;
4302 /* Encode the 16-bit imm field of svc/hvc/smc. */
4303 static inline uint32_t
4304 encode_svc_imm (uint32_t imm
)
4309 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4310 static inline uint32_t
4311 reencode_addsub_switch_add_sub (uint32_t opcode
)
4313 return opcode
^ (1 << 30);
4316 static inline uint32_t
4317 reencode_movzn_to_movz (uint32_t opcode
)
4319 return opcode
| (1 << 30);
4322 static inline uint32_t
4323 reencode_movzn_to_movn (uint32_t opcode
)
4325 return opcode
& ~(1 << 30);
4328 /* Overall per-instruction processing. */
4330 /* We need to be able to fix up arbitrary expressions in some statements.
4331 This is so that we can handle symbols that are an arbitrary distance from
4332 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4333 which returns part of an address in a form which will be valid for
4334 a data instruction. We do this by pushing the expression into a symbol
4335 in the expr_section, and creating a fix for that. */
4338 fix_new_aarch64 (fragS
* frag
,
4353 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4357 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4364 /* Diagnostics on operands errors. */
4366 /* By default, output verbose error message.
4367 Disable the verbose error message by -mno-verbose-error. */
4368 static int verbose_error_p
= 1;
4370 #ifdef DEBUG_AARCH64
4371 /* N.B. this is only for the purpose of debugging. */
4372 const char* operand_mismatch_kind_names
[] =
4375 "AARCH64_OPDE_RECOVERABLE",
4376 "AARCH64_OPDE_SYNTAX_ERROR",
4377 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4378 "AARCH64_OPDE_INVALID_VARIANT",
4379 "AARCH64_OPDE_OUT_OF_RANGE",
4380 "AARCH64_OPDE_UNALIGNED",
4381 "AARCH64_OPDE_REG_LIST",
4382 "AARCH64_OPDE_OTHER_ERROR",
4384 #endif /* DEBUG_AARCH64 */
4386 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4388 When multiple errors of different kinds are found in the same assembly
4389 line, only the error of the highest severity will be picked up for
4390 issuing the diagnostics. */
4392 static inline bfd_boolean
4393 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4394 enum aarch64_operand_error_kind rhs
)
4396 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4397 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4398 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4399 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4400 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4401 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4402 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4403 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4407 /* Helper routine to get the mnemonic name from the assembly instruction
4408 line; should only be called for the diagnosis purpose, as there is
4409 string copy operation involved, which may affect the runtime
4410 performance if used in elsewhere. */
4413 get_mnemonic_name (const char *str
)
4415 static char mnemonic
[32];
4418 /* Get the first 15 bytes and assume that the full name is included. */
4419 strncpy (mnemonic
, str
, 31);
4420 mnemonic
[31] = '\0';
4422 /* Scan up to the end of the mnemonic, which must end in white space,
4423 '.', or end of string. */
4424 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4429 /* Append '...' to the truncated long name. */
4430 if (ptr
- mnemonic
== 31)
4431 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4437 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4439 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4440 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4443 /* Data structures storing one user error in the assembly code related to
4446 struct operand_error_record
4448 const aarch64_opcode
*opcode
;
4449 aarch64_operand_error detail
;
4450 struct operand_error_record
*next
;
4453 typedef struct operand_error_record operand_error_record
;
4455 struct operand_errors
4457 operand_error_record
*head
;
4458 operand_error_record
*tail
;
4461 typedef struct operand_errors operand_errors
;
4463 /* Top-level data structure reporting user errors for the current line of
4465 The way md_assemble works is that all opcodes sharing the same mnemonic
4466 name are iterated to find a match to the assembly line. In this data
4467 structure, each of the such opcodes will have one operand_error_record
4468 allocated and inserted. In other words, excessive errors related with
4469 a single opcode are disregarded. */
4470 operand_errors operand_error_report
;
4472 /* Free record nodes. */
4473 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4475 /* Initialize the data structure that stores the operand mismatch
4476 information on assembling one line of the assembly code. */
4478 init_operand_error_report (void)
4480 if (operand_error_report
.head
!= NULL
)
4482 gas_assert (operand_error_report
.tail
!= NULL
);
4483 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4484 free_opnd_error_record_nodes
= operand_error_report
.head
;
4485 operand_error_report
.head
= NULL
;
4486 operand_error_report
.tail
= NULL
;
4489 gas_assert (operand_error_report
.tail
== NULL
);
4492 /* Return TRUE if some operand error has been recorded during the
4493 parsing of the current assembly line using the opcode *OPCODE;
4494 otherwise return FALSE. */
4495 static inline bfd_boolean
4496 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4498 operand_error_record
*record
= operand_error_report
.head
;
4499 return record
&& record
->opcode
== opcode
;
4502 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4503 OPCODE field is initialized with OPCODE.
4504 N.B. only one record for each opcode, i.e. the maximum of one error is
4505 recorded for each instruction template. */
4508 add_operand_error_record (const operand_error_record
* new_record
)
4510 const aarch64_opcode
*opcode
= new_record
->opcode
;
4511 operand_error_record
* record
= operand_error_report
.head
;
4513 /* The record may have been created for this opcode. If not, we need
4515 if (! opcode_has_operand_error_p (opcode
))
4517 /* Get one empty record. */
4518 if (free_opnd_error_record_nodes
== NULL
)
4520 record
= XNEW (operand_error_record
);
4524 record
= free_opnd_error_record_nodes
;
4525 free_opnd_error_record_nodes
= record
->next
;
4527 record
->opcode
= opcode
;
4528 /* Insert at the head. */
4529 record
->next
= operand_error_report
.head
;
4530 operand_error_report
.head
= record
;
4531 if (operand_error_report
.tail
== NULL
)
4532 operand_error_report
.tail
= record
;
4534 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4535 && record
->detail
.index
<= new_record
->detail
.index
4536 && operand_error_higher_severity_p (record
->detail
.kind
,
4537 new_record
->detail
.kind
))
4539 /* In the case of multiple errors found on operands related with a
4540 single opcode, only record the error of the leftmost operand and
4541 only if the error is of higher severity. */
4542 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4543 " the existing error %s on operand %d",
4544 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4545 new_record
->detail
.index
,
4546 operand_mismatch_kind_names
[record
->detail
.kind
],
4547 record
->detail
.index
);
4551 record
->detail
= new_record
->detail
;
4555 record_operand_error_info (const aarch64_opcode
*opcode
,
4556 aarch64_operand_error
*error_info
)
4558 operand_error_record record
;
4559 record
.opcode
= opcode
;
4560 record
.detail
= *error_info
;
4561 add_operand_error_record (&record
);
4564 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4565 error message *ERROR, for operand IDX (count from 0). */
4568 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4569 enum aarch64_operand_error_kind kind
,
4572 aarch64_operand_error info
;
4573 memset(&info
, 0, sizeof (info
));
4577 info
.non_fatal
= FALSE
;
4578 record_operand_error_info (opcode
, &info
);
4582 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4583 enum aarch64_operand_error_kind kind
,
4584 const char* error
, const int *extra_data
)
4586 aarch64_operand_error info
;
4590 info
.data
[0] = extra_data
[0];
4591 info
.data
[1] = extra_data
[1];
4592 info
.data
[2] = extra_data
[2];
4593 info
.non_fatal
= FALSE
;
4594 record_operand_error_info (opcode
, &info
);
4598 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4599 const char* error
, int lower_bound
,
4602 int data
[3] = {lower_bound
, upper_bound
, 0};
4603 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4607 /* Remove the operand error record for *OPCODE. */
4608 static void ATTRIBUTE_UNUSED
4609 remove_operand_error_record (const aarch64_opcode
*opcode
)
4611 if (opcode_has_operand_error_p (opcode
))
4613 operand_error_record
* record
= operand_error_report
.head
;
4614 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4615 operand_error_report
.head
= record
->next
;
4616 record
->next
= free_opnd_error_record_nodes
;
4617 free_opnd_error_record_nodes
= record
;
4618 if (operand_error_report
.head
== NULL
)
4620 gas_assert (operand_error_report
.tail
== record
);
4621 operand_error_report
.tail
= NULL
;
4626 /* Given the instruction in *INSTR, return the index of the best matched
4627 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4629 Return -1 if there is no qualifier sequence; return the first match
4630 if there is multiple matches found. */
4633 find_best_match (const aarch64_inst
*instr
,
4634 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4636 int i
, num_opnds
, max_num_matched
, idx
;
4638 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4641 DEBUG_TRACE ("no operand");
4645 max_num_matched
= 0;
4648 /* For each pattern. */
4649 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4652 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4654 /* Most opcodes has much fewer patterns in the list. */
4655 if (empty_qualifier_sequence_p (qualifiers
))
4657 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4661 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4662 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4665 if (num_matched
> max_num_matched
)
4667 max_num_matched
= num_matched
;
4672 DEBUG_TRACE ("return with %d", idx
);
4676 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4677 corresponding operands in *INSTR. */
4680 assign_qualifier_sequence (aarch64_inst
*instr
,
4681 const aarch64_opnd_qualifier_t
*qualifiers
)
4684 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4685 gas_assert (num_opnds
);
4686 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4687 instr
->operands
[i
].qualifier
= *qualifiers
;
4690 /* Print operands for the diagnosis purpose. */
4693 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4694 const aarch64_opnd_info
*opnds
)
4698 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4702 /* We regard the opcode operand info more, however we also look into
4703 the inst->operands to support the disassembling of the optional
4705 The two operand code should be the same in all cases, apart from
4706 when the operand can be optional. */
4707 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4708 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4711 /* Generate the operand string in STR. */
4712 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4717 strcat (buf
, i
== 0 ? " " : ", ");
4719 /* Append the operand string. */
4724 /* Send to stderr a string as information. */
4727 output_info (const char *format
, ...)
4733 file
= as_where (&line
);
4737 fprintf (stderr
, "%s:%u: ", file
, line
);
4739 fprintf (stderr
, "%s: ", file
);
4741 fprintf (stderr
, _("Info: "));
4742 va_start (args
, format
);
4743 vfprintf (stderr
, format
, args
);
4745 (void) putc ('\n', stderr
);
4748 /* Output one operand error record. */
4751 output_operand_error_record (const operand_error_record
*record
, char *str
)
4753 const aarch64_operand_error
*detail
= &record
->detail
;
4754 int idx
= detail
->index
;
4755 const aarch64_opcode
*opcode
= record
->opcode
;
4756 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4757 : AARCH64_OPND_NIL
);
4759 typedef void (*handler_t
)(const char *format
, ...);
4760 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4762 switch (detail
->kind
)
4764 case AARCH64_OPDE_NIL
:
4767 case AARCH64_OPDE_SYNTAX_ERROR
:
4768 case AARCH64_OPDE_RECOVERABLE
:
4769 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4770 case AARCH64_OPDE_OTHER_ERROR
:
4771 /* Use the prepared error message if there is, otherwise use the
4772 operand description string to describe the error. */
4773 if (detail
->error
!= NULL
)
4776 handler (_("%s -- `%s'"), detail
->error
, str
);
4778 handler (_("%s at operand %d -- `%s'"),
4779 detail
->error
, idx
+ 1, str
);
4783 gas_assert (idx
>= 0);
4784 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4785 aarch64_get_operand_desc (opd_code
), str
);
4789 case AARCH64_OPDE_INVALID_VARIANT
:
4790 handler (_("operand mismatch -- `%s'"), str
);
4791 if (verbose_error_p
)
4793 /* We will try to correct the erroneous instruction and also provide
4794 more information e.g. all other valid variants.
4796 The string representation of the corrected instruction and other
4797 valid variants are generated by
4799 1) obtaining the intermediate representation of the erroneous
4801 2) manipulating the IR, e.g. replacing the operand qualifier;
4802 3) printing out the instruction by calling the printer functions
4803 shared with the disassembler.
4805 The limitation of this method is that the exact input assembly
4806 line cannot be accurately reproduced in some cases, for example an
4807 optional operand present in the actual assembly line will be
4808 omitted in the output; likewise for the optional syntax rules,
4809 e.g. the # before the immediate. Another limitation is that the
4810 assembly symbols and relocation operations in the assembly line
4811 currently cannot be printed out in the error report. Last but not
4812 least, when there is other error(s) co-exist with this error, the
4813 'corrected' instruction may be still incorrect, e.g. given
4814 'ldnp h0,h1,[x0,#6]!'
4815 this diagnosis will provide the version:
4816 'ldnp s0,s1,[x0,#6]!'
4817 which is still not right. */
4818 size_t len
= strlen (get_mnemonic_name (str
));
4822 aarch64_inst
*inst_base
= &inst
.base
;
4823 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4826 reset_aarch64_instruction (&inst
);
4827 inst_base
->opcode
= opcode
;
4829 /* Reset the error report so that there is no side effect on the
4830 following operand parsing. */
4831 init_operand_error_report ();
4834 result
= parse_operands (str
+ len
, opcode
)
4835 && programmer_friendly_fixup (&inst
);
4836 gas_assert (result
);
4837 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4838 NULL
, NULL
, insn_sequence
);
4839 gas_assert (!result
);
4841 /* Find the most matched qualifier sequence. */
4842 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4843 gas_assert (qlf_idx
> -1);
4845 /* Assign the qualifiers. */
4846 assign_qualifier_sequence (inst_base
,
4847 opcode
->qualifiers_list
[qlf_idx
]);
4849 /* Print the hint. */
4850 output_info (_(" did you mean this?"));
4851 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4852 print_operands (buf
, opcode
, inst_base
->operands
);
4853 output_info (_(" %s"), buf
);
4855 /* Print out other variant(s) if there is any. */
4857 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4858 output_info (_(" other valid variant(s):"));
4860 /* For each pattern. */
4861 qualifiers_list
= opcode
->qualifiers_list
;
4862 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4864 /* Most opcodes has much fewer patterns in the list.
4865 First NIL qualifier indicates the end in the list. */
4866 if (empty_qualifier_sequence_p (*qualifiers_list
))
4871 /* Mnemonics name. */
4872 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4874 /* Assign the qualifiers. */
4875 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4877 /* Print instruction. */
4878 print_operands (buf
, opcode
, inst_base
->operands
);
4880 output_info (_(" %s"), buf
);
4886 case AARCH64_OPDE_UNTIED_OPERAND
:
4887 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4888 detail
->index
+ 1, str
);
4891 case AARCH64_OPDE_OUT_OF_RANGE
:
4892 if (detail
->data
[0] != detail
->data
[1])
4893 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4894 detail
->error
? detail
->error
: _("immediate value"),
4895 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4897 handler (_("%s must be %d at operand %d -- `%s'"),
4898 detail
->error
? detail
->error
: _("immediate value"),
4899 detail
->data
[0], idx
+ 1, str
);
4902 case AARCH64_OPDE_REG_LIST
:
4903 if (detail
->data
[0] == 1)
4904 handler (_("invalid number of registers in the list; "
4905 "only 1 register is expected at operand %d -- `%s'"),
4908 handler (_("invalid number of registers in the list; "
4909 "%d registers are expected at operand %d -- `%s'"),
4910 detail
->data
[0], idx
+ 1, str
);
4913 case AARCH64_OPDE_UNALIGNED
:
4914 handler (_("immediate value must be a multiple of "
4915 "%d at operand %d -- `%s'"),
4916 detail
->data
[0], idx
+ 1, str
);
4925 /* Process and output the error message about the operand mismatching.
4927 When this function is called, the operand error information had
4928 been collected for an assembly line and there will be multiple
4929 errors in the case of multiple instruction templates; output the
4930 error message that most closely describes the problem.
4932 The errors to be printed can be filtered on printing all errors
4933 or only non-fatal errors. This distinction has to be made because
4934 the error buffer may already be filled with fatal errors we don't want to
4935 print due to the different instruction templates. */
4938 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4940 int largest_error_pos
;
4941 const char *msg
= NULL
;
4942 enum aarch64_operand_error_kind kind
;
4943 operand_error_record
*curr
;
4944 operand_error_record
*head
= operand_error_report
.head
;
4945 operand_error_record
*record
= NULL
;
4947 /* No error to report. */
4951 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4953 /* Only one error. */
4954 if (head
== operand_error_report
.tail
)
4956 /* If the only error is a non-fatal one and we don't want to print it,
4958 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4960 DEBUG_TRACE ("single opcode entry with error kind: %s",
4961 operand_mismatch_kind_names
[head
->detail
.kind
]);
4962 output_operand_error_record (head
, str
);
4967 /* Find the error kind of the highest severity. */
4968 DEBUG_TRACE ("multiple opcode entries with error kind");
4969 kind
= AARCH64_OPDE_NIL
;
4970 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4972 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4973 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4974 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4975 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4976 kind
= curr
->detail
.kind
;
4979 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4981 /* Pick up one of errors of KIND to report. */
4982 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4983 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4985 /* If we don't want to print non-fatal errors then don't consider them
4987 if (curr
->detail
.kind
!= kind
4988 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4990 /* If there are multiple errors, pick up the one with the highest
4991 mismatching operand index. In the case of multiple errors with
4992 the equally highest operand index, pick up the first one or the
4993 first one with non-NULL error message. */
4994 if (curr
->detail
.index
> largest_error_pos
4995 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4996 && curr
->detail
.error
!= NULL
))
4998 largest_error_pos
= curr
->detail
.index
;
5000 msg
= record
->detail
.error
;
5004 /* The way errors are collected in the back-end is a bit non-intuitive. But
5005 essentially, because each operand template is tried recursively you may
5006 always have errors collected from the previous tried OPND. These are
5007 usually skipped if there is one successful match. However now with the
5008 non-fatal errors we have to ignore those previously collected hard errors
5009 when we're only interested in printing the non-fatal ones. This condition
5010 prevents us from printing errors that are not appropriate, since we did
5011 match a condition, but it also has warnings that it wants to print. */
5012 if (non_fatal_only
&& !record
)
5015 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5016 DEBUG_TRACE ("Pick up error kind %s to report",
5017 operand_mismatch_kind_names
[record
->detail
.kind
]);
5020 output_operand_error_record (record
, str
);
5023 /* Write an AARCH64 instruction to buf - always little-endian. */
5025 put_aarch64_insn (char *buf
, uint32_t insn
)
5027 unsigned char *where
= (unsigned char *) buf
;
5029 where
[1] = insn
>> 8;
5030 where
[2] = insn
>> 16;
5031 where
[3] = insn
>> 24;
5035 get_aarch64_insn (char *buf
)
5037 unsigned char *where
= (unsigned char *) buf
;
5039 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5040 | ((uint32_t) where
[3] << 24)));
5045 output_inst (struct aarch64_inst
*new_inst
)
5049 to
= frag_more (INSN_SIZE
);
5051 frag_now
->tc_frag_data
.recorded
= 1;
5053 put_aarch64_insn (to
, inst
.base
.value
);
5055 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5057 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5058 INSN_SIZE
, &inst
.reloc
.exp
,
5061 DEBUG_TRACE ("Prepared relocation fix up");
5062 /* Don't check the addend value against the instruction size,
5063 that's the job of our code in md_apply_fix(). */
5064 fixp
->fx_no_overflow
= 1;
5065 if (new_inst
!= NULL
)
5066 fixp
->tc_fix_data
.inst
= new_inst
;
5067 if (aarch64_gas_internal_fixup_p ())
5069 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5070 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5071 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5075 dwarf2_emit_insn (INSN_SIZE
);
5078 /* Link together opcodes of the same name. */
5082 aarch64_opcode
*opcode
;
5083 struct templates
*next
;
5086 typedef struct templates templates
;
5089 lookup_mnemonic (const char *start
, int len
)
5091 templates
*templ
= NULL
;
5093 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5097 /* Subroutine of md_assemble, responsible for looking up the primary
5098 opcode from the mnemonic the user wrote. STR points to the
5099 beginning of the mnemonic. */
5102 opcode_lookup (char **str
)
5104 char *end
, *base
, *dot
;
5105 const aarch64_cond
*cond
;
5109 /* Scan up to the end of the mnemonic, which must end in white space,
5110 '.', or end of string. */
5112 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5113 if (*end
== '.' && !dot
)
5116 if (end
== base
|| dot
== base
)
5119 inst
.cond
= COND_ALWAYS
;
5121 /* Handle a possible condition. */
5124 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5127 inst
.cond
= cond
->value
;
5143 if (inst
.cond
== COND_ALWAYS
)
5145 /* Look for unaffixed mnemonic. */
5146 return lookup_mnemonic (base
, len
);
5150 /* append ".c" to mnemonic if conditional */
5151 memcpy (condname
, base
, len
);
5152 memcpy (condname
+ len
, ".c", 2);
5155 return lookup_mnemonic (base
, len
);
5161 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5162 to a corresponding operand qualifier. */
5164 static inline aarch64_opnd_qualifier_t
5165 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5167 /* Element size in bytes indexed by vector_el_type. */
5168 const unsigned char ele_size
[5]
5170 const unsigned int ele_base
[5] =
5172 AARCH64_OPND_QLF_V_4B
,
5173 AARCH64_OPND_QLF_V_2H
,
5174 AARCH64_OPND_QLF_V_2S
,
5175 AARCH64_OPND_QLF_V_1D
,
5176 AARCH64_OPND_QLF_V_1Q
5179 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5180 goto vectype_conversion_fail
;
5182 if (vectype
->type
== NT_zero
)
5183 return AARCH64_OPND_QLF_P_Z
;
5184 if (vectype
->type
== NT_merge
)
5185 return AARCH64_OPND_QLF_P_M
;
5187 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5189 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5191 /* Special case S_4B. */
5192 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5193 return AARCH64_OPND_QLF_S_4B
;
5195 /* Special case S_2H. */
5196 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5197 return AARCH64_OPND_QLF_S_2H
;
5199 /* Vector element register. */
5200 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5204 /* Vector register. */
5205 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5208 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5209 goto vectype_conversion_fail
;
5211 /* The conversion is by calculating the offset from the base operand
5212 qualifier for the vector type. The operand qualifiers are regular
5213 enough that the offset can established by shifting the vector width by
5214 a vector-type dependent amount. */
5216 if (vectype
->type
== NT_b
)
5218 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5220 else if (vectype
->type
>= NT_d
)
5225 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5226 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5227 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5231 vectype_conversion_fail
:
5232 first_error (_("bad vector arrangement type"));
5233 return AARCH64_OPND_QLF_NIL
;
5236 /* Process an optional operand that is found omitted from the assembly line.
5237 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5238 instruction's opcode entry while IDX is the index of this omitted operand.
5242 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5243 int idx
, aarch64_opnd_info
*operand
)
5245 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5246 gas_assert (optional_operand_p (opcode
, idx
));
5247 gas_assert (!operand
->present
);
5251 case AARCH64_OPND_Rd
:
5252 case AARCH64_OPND_Rn
:
5253 case AARCH64_OPND_Rm
:
5254 case AARCH64_OPND_Rt
:
5255 case AARCH64_OPND_Rt2
:
5256 case AARCH64_OPND_Rt_SP
:
5257 case AARCH64_OPND_Rs
:
5258 case AARCH64_OPND_Ra
:
5259 case AARCH64_OPND_Rt_SYS
:
5260 case AARCH64_OPND_Rd_SP
:
5261 case AARCH64_OPND_Rn_SP
:
5262 case AARCH64_OPND_Rm_SP
:
5263 case AARCH64_OPND_Fd
:
5264 case AARCH64_OPND_Fn
:
5265 case AARCH64_OPND_Fm
:
5266 case AARCH64_OPND_Fa
:
5267 case AARCH64_OPND_Ft
:
5268 case AARCH64_OPND_Ft2
:
5269 case AARCH64_OPND_Sd
:
5270 case AARCH64_OPND_Sn
:
5271 case AARCH64_OPND_Sm
:
5272 case AARCH64_OPND_Va
:
5273 case AARCH64_OPND_Vd
:
5274 case AARCH64_OPND_Vn
:
5275 case AARCH64_OPND_Vm
:
5276 case AARCH64_OPND_VdD1
:
5277 case AARCH64_OPND_VnD1
:
5278 operand
->reg
.regno
= default_value
;
5281 case AARCH64_OPND_Ed
:
5282 case AARCH64_OPND_En
:
5283 case AARCH64_OPND_Em
:
5284 case AARCH64_OPND_Em16
:
5285 case AARCH64_OPND_SM3_IMM2
:
5286 operand
->reglane
.regno
= default_value
;
5289 case AARCH64_OPND_IDX
:
5290 case AARCH64_OPND_BIT_NUM
:
5291 case AARCH64_OPND_IMMR
:
5292 case AARCH64_OPND_IMMS
:
5293 case AARCH64_OPND_SHLL_IMM
:
5294 case AARCH64_OPND_IMM_VLSL
:
5295 case AARCH64_OPND_IMM_VLSR
:
5296 case AARCH64_OPND_CCMP_IMM
:
5297 case AARCH64_OPND_FBITS
:
5298 case AARCH64_OPND_UIMM4
:
5299 case AARCH64_OPND_UIMM3_OP1
:
5300 case AARCH64_OPND_UIMM3_OP2
:
5301 case AARCH64_OPND_IMM
:
5302 case AARCH64_OPND_IMM_2
:
5303 case AARCH64_OPND_WIDTH
:
5304 case AARCH64_OPND_UIMM7
:
5305 case AARCH64_OPND_NZCV
:
5306 case AARCH64_OPND_SVE_PATTERN
:
5307 case AARCH64_OPND_SVE_PRFOP
:
5308 operand
->imm
.value
= default_value
;
5311 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5312 operand
->imm
.value
= default_value
;
5313 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5314 operand
->shifter
.amount
= 1;
5317 case AARCH64_OPND_EXCEPTION
:
5318 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5321 case AARCH64_OPND_BARRIER_ISB
:
5322 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5325 case AARCH64_OPND_BTI_TARGET
:
5326 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5334 /* Process the relocation type for move wide instructions.
5335 Return TRUE on success; otherwise return FALSE. */
5338 process_movw_reloc_info (void)
5343 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5345 if (inst
.base
.opcode
->op
== OP_MOVK
)
5346 switch (inst
.reloc
.type
)
5348 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5349 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5350 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5351 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5352 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5353 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5354 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5355 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5356 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5357 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5358 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5360 (_("the specified relocation type is not allowed for MOVK"));
5366 switch (inst
.reloc
.type
)
5368 case BFD_RELOC_AARCH64_MOVW_G0
:
5369 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5370 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5371 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5372 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5373 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5374 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5375 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5376 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5377 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5378 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5379 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5380 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5383 case BFD_RELOC_AARCH64_MOVW_G1
:
5384 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5385 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5386 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5387 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5388 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5389 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5390 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5391 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5392 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5393 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5394 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5395 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5398 case BFD_RELOC_AARCH64_MOVW_G2
:
5399 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5400 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5401 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5402 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5403 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5404 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5407 set_fatal_syntax_error
5408 (_("the specified relocation type is not allowed for 32-bit "
5414 case BFD_RELOC_AARCH64_MOVW_G3
:
5415 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5418 set_fatal_syntax_error
5419 (_("the specified relocation type is not allowed for 32-bit "
5426 /* More cases should be added when more MOVW-related relocation types
5427 are supported in GAS. */
5428 gas_assert (aarch64_gas_internal_fixup_p ());
5429 /* The shift amount should have already been set by the parser. */
5432 inst
.base
.operands
[1].shifter
.amount
= shift
;
5436 /* A primitive log calculator. */
5438 static inline unsigned int
5439 get_logsz (unsigned int size
)
5441 const unsigned char ls
[16] =
5442 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5448 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5449 return ls
[size
- 1];
5452 /* Determine and return the real reloc type code for an instruction
5453 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5455 static inline bfd_reloc_code_real_type
5456 ldst_lo12_determine_real_reloc_type (void)
5459 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5460 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5462 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5464 BFD_RELOC_AARCH64_LDST8_LO12
,
5465 BFD_RELOC_AARCH64_LDST16_LO12
,
5466 BFD_RELOC_AARCH64_LDST32_LO12
,
5467 BFD_RELOC_AARCH64_LDST64_LO12
,
5468 BFD_RELOC_AARCH64_LDST128_LO12
5471 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5472 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5473 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5474 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5475 BFD_RELOC_AARCH64_NONE
5478 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5479 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5480 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5481 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5482 BFD_RELOC_AARCH64_NONE
5485 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5486 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5487 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5488 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5489 BFD_RELOC_AARCH64_NONE
5492 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5493 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5494 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5495 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5496 BFD_RELOC_AARCH64_NONE
5500 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5501 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5503 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5505 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5507 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5508 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5510 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5512 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5514 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5516 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5517 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5518 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5519 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5520 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5521 gas_assert (logsz
<= 3);
5523 gas_assert (logsz
<= 4);
5525 /* In reloc.c, these pseudo relocation types should be defined in similar
5526 order as above reloc_ldst_lo12 array. Because the array index calculation
5527 below relies on this. */
5528 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5531 /* Check whether a register list REGINFO is valid. The registers must be
5532 numbered in increasing order (modulo 32), in increments of one or two.
5534 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5537 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5540 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5542 uint32_t i
, nb_regs
, prev_regno
, incr
;
5544 nb_regs
= 1 + (reginfo
& 0x3);
5546 prev_regno
= reginfo
& 0x1f;
5547 incr
= accept_alternate
? 2 : 1;
5549 for (i
= 1; i
< nb_regs
; ++i
)
5551 uint32_t curr_regno
;
5553 curr_regno
= reginfo
& 0x1f;
5554 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5556 prev_regno
= curr_regno
;
5562 /* Generic instruction operand parser. This does no encoding and no
5563 semantic validation; it merely squirrels values away in the inst
5564 structure. Returns TRUE or FALSE depending on whether the
5565 specified grammar matched. */
5568 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5571 char *backtrack_pos
= 0;
5572 const enum aarch64_opnd
*operands
= opcode
->operands
;
5573 aarch64_reg_type imm_reg_type
;
5576 skip_whitespace (str
);
5578 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5579 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5581 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5583 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5586 const reg_entry
*reg
;
5587 int comma_skipped_p
= 0;
5588 aarch64_reg_type rtype
;
5589 struct vector_type_el vectype
;
5590 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5591 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5592 aarch64_reg_type reg_type
;
5594 DEBUG_TRACE ("parse operand %d", i
);
5596 /* Assign the operand code. */
5597 info
->type
= operands
[i
];
5599 if (optional_operand_p (opcode
, i
))
5601 /* Remember where we are in case we need to backtrack. */
5602 gas_assert (!backtrack_pos
);
5603 backtrack_pos
= str
;
5606 /* Expect comma between operands; the backtrack mechanism will take
5607 care of cases of omitted optional operand. */
5608 if (i
> 0 && ! skip_past_char (&str
, ','))
5610 set_syntax_error (_("comma expected between operands"));
5614 comma_skipped_p
= 1;
5616 switch (operands
[i
])
5618 case AARCH64_OPND_Rd
:
5619 case AARCH64_OPND_Rn
:
5620 case AARCH64_OPND_Rm
:
5621 case AARCH64_OPND_Rt
:
5622 case AARCH64_OPND_Rt2
:
5623 case AARCH64_OPND_Rs
:
5624 case AARCH64_OPND_Ra
:
5625 case AARCH64_OPND_Rt_SYS
:
5626 case AARCH64_OPND_PAIRREG
:
5627 case AARCH64_OPND_SVE_Rm
:
5628 po_int_reg_or_fail (REG_TYPE_R_Z
);
5631 case AARCH64_OPND_Rd_SP
:
5632 case AARCH64_OPND_Rn_SP
:
5633 case AARCH64_OPND_Rt_SP
:
5634 case AARCH64_OPND_SVE_Rn_SP
:
5635 case AARCH64_OPND_Rm_SP
:
5636 po_int_reg_or_fail (REG_TYPE_R_SP
);
5639 case AARCH64_OPND_Rm_EXT
:
5640 case AARCH64_OPND_Rm_SFT
:
5641 po_misc_or_fail (parse_shifter_operand
5642 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5644 : SHIFTED_LOGIC_IMM
)));
5645 if (!info
->shifter
.operator_present
)
5647 /* Default to LSL if not present. Libopcodes prefers shifter
5648 kind to be explicit. */
5649 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5650 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5651 /* For Rm_EXT, libopcodes will carry out further check on whether
5652 or not stack pointer is used in the instruction (Recall that
5653 "the extend operator is not optional unless at least one of
5654 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5658 case AARCH64_OPND_Fd
:
5659 case AARCH64_OPND_Fn
:
5660 case AARCH64_OPND_Fm
:
5661 case AARCH64_OPND_Fa
:
5662 case AARCH64_OPND_Ft
:
5663 case AARCH64_OPND_Ft2
:
5664 case AARCH64_OPND_Sd
:
5665 case AARCH64_OPND_Sn
:
5666 case AARCH64_OPND_Sm
:
5667 case AARCH64_OPND_SVE_VZn
:
5668 case AARCH64_OPND_SVE_Vd
:
5669 case AARCH64_OPND_SVE_Vm
:
5670 case AARCH64_OPND_SVE_Vn
:
5671 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5672 if (val
== PARSE_FAIL
)
5674 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5677 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5679 info
->reg
.regno
= val
;
5680 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5683 case AARCH64_OPND_SVE_Pd
:
5684 case AARCH64_OPND_SVE_Pg3
:
5685 case AARCH64_OPND_SVE_Pg4_5
:
5686 case AARCH64_OPND_SVE_Pg4_10
:
5687 case AARCH64_OPND_SVE_Pg4_16
:
5688 case AARCH64_OPND_SVE_Pm
:
5689 case AARCH64_OPND_SVE_Pn
:
5690 case AARCH64_OPND_SVE_Pt
:
5691 reg_type
= REG_TYPE_PN
;
5694 case AARCH64_OPND_SVE_Za_5
:
5695 case AARCH64_OPND_SVE_Za_16
:
5696 case AARCH64_OPND_SVE_Zd
:
5697 case AARCH64_OPND_SVE_Zm_5
:
5698 case AARCH64_OPND_SVE_Zm_16
:
5699 case AARCH64_OPND_SVE_Zn
:
5700 case AARCH64_OPND_SVE_Zt
:
5701 reg_type
= REG_TYPE_ZN
;
5704 case AARCH64_OPND_Va
:
5705 case AARCH64_OPND_Vd
:
5706 case AARCH64_OPND_Vn
:
5707 case AARCH64_OPND_Vm
:
5708 reg_type
= REG_TYPE_VN
;
5710 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5711 if (val
== PARSE_FAIL
)
5713 first_error (_(get_reg_expected_msg (reg_type
)));
5716 if (vectype
.defined
& NTA_HASINDEX
)
5719 info
->reg
.regno
= val
;
5720 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5721 && vectype
.type
== NT_invtype
)
5722 /* Unqualified Pn and Zn registers are allowed in certain
5723 contexts. Rely on F_STRICT qualifier checking to catch
5725 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5728 info
->qualifier
= vectype_to_qualifier (&vectype
);
5729 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5734 case AARCH64_OPND_VdD1
:
5735 case AARCH64_OPND_VnD1
:
5736 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5737 if (val
== PARSE_FAIL
)
5739 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5742 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5744 set_fatal_syntax_error
5745 (_("the top half of a 128-bit FP/SIMD register is expected"));
5748 info
->reg
.regno
= val
;
5749 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5750 here; it is correct for the purpose of encoding/decoding since
5751 only the register number is explicitly encoded in the related
5752 instructions, although this appears a bit hacky. */
5753 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5756 case AARCH64_OPND_SVE_Zm3_INDEX
:
5757 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5758 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5759 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5760 case AARCH64_OPND_SVE_Zm4_INDEX
:
5761 case AARCH64_OPND_SVE_Zn_INDEX
:
5762 reg_type
= REG_TYPE_ZN
;
5763 goto vector_reg_index
;
5765 case AARCH64_OPND_Ed
:
5766 case AARCH64_OPND_En
:
5767 case AARCH64_OPND_Em
:
5768 case AARCH64_OPND_Em16
:
5769 case AARCH64_OPND_SM3_IMM2
:
5770 reg_type
= REG_TYPE_VN
;
5772 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5773 if (val
== PARSE_FAIL
)
5775 first_error (_(get_reg_expected_msg (reg_type
)));
5778 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5781 info
->reglane
.regno
= val
;
5782 info
->reglane
.index
= vectype
.index
;
5783 info
->qualifier
= vectype_to_qualifier (&vectype
);
5784 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5788 case AARCH64_OPND_SVE_ZnxN
:
5789 case AARCH64_OPND_SVE_ZtxN
:
5790 reg_type
= REG_TYPE_ZN
;
5791 goto vector_reg_list
;
5793 case AARCH64_OPND_LVn
:
5794 case AARCH64_OPND_LVt
:
5795 case AARCH64_OPND_LVt_AL
:
5796 case AARCH64_OPND_LEt
:
5797 reg_type
= REG_TYPE_VN
;
5799 if (reg_type
== REG_TYPE_ZN
5800 && get_opcode_dependent_value (opcode
) == 1
5803 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5804 if (val
== PARSE_FAIL
)
5806 first_error (_(get_reg_expected_msg (reg_type
)));
5809 info
->reglist
.first_regno
= val
;
5810 info
->reglist
.num_regs
= 1;
5814 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5815 if (val
== PARSE_FAIL
)
5818 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5820 set_fatal_syntax_error (_("invalid register list"));
5824 if (vectype
.width
!= 0 && *str
!= ',')
5826 set_fatal_syntax_error
5827 (_("expected element type rather than vector type"));
5831 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5832 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5834 if (operands
[i
] == AARCH64_OPND_LEt
)
5836 if (!(vectype
.defined
& NTA_HASINDEX
))
5838 info
->reglist
.has_index
= 1;
5839 info
->reglist
.index
= vectype
.index
;
5843 if (vectype
.defined
& NTA_HASINDEX
)
5845 if (!(vectype
.defined
& NTA_HASTYPE
))
5847 if (reg_type
== REG_TYPE_ZN
)
5848 set_fatal_syntax_error (_("missing type suffix"));
5852 info
->qualifier
= vectype_to_qualifier (&vectype
);
5853 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5857 case AARCH64_OPND_CRn
:
5858 case AARCH64_OPND_CRm
:
5860 char prefix
= *(str
++);
5861 if (prefix
!= 'c' && prefix
!= 'C')
5864 po_imm_nc_or_fail ();
5867 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5870 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5871 info
->imm
.value
= val
;
5875 case AARCH64_OPND_SHLL_IMM
:
5876 case AARCH64_OPND_IMM_VLSR
:
5877 po_imm_or_fail (1, 64);
5878 info
->imm
.value
= val
;
5881 case AARCH64_OPND_CCMP_IMM
:
5882 case AARCH64_OPND_SIMM5
:
5883 case AARCH64_OPND_FBITS
:
5884 case AARCH64_OPND_TME_UIMM16
:
5885 case AARCH64_OPND_UIMM4
:
5886 case AARCH64_OPND_UIMM4_ADDG
:
5887 case AARCH64_OPND_UIMM10
:
5888 case AARCH64_OPND_UIMM3_OP1
:
5889 case AARCH64_OPND_UIMM3_OP2
:
5890 case AARCH64_OPND_IMM_VLSL
:
5891 case AARCH64_OPND_IMM
:
5892 case AARCH64_OPND_IMM_2
:
5893 case AARCH64_OPND_WIDTH
:
5894 case AARCH64_OPND_SVE_INV_LIMM
:
5895 case AARCH64_OPND_SVE_LIMM
:
5896 case AARCH64_OPND_SVE_LIMM_MOV
:
5897 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5898 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5899 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5900 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5901 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5902 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5903 case AARCH64_OPND_SVE_SIMM5
:
5904 case AARCH64_OPND_SVE_SIMM5B
:
5905 case AARCH64_OPND_SVE_SIMM6
:
5906 case AARCH64_OPND_SVE_SIMM8
:
5907 case AARCH64_OPND_SVE_UIMM3
:
5908 case AARCH64_OPND_SVE_UIMM7
:
5909 case AARCH64_OPND_SVE_UIMM8
:
5910 case AARCH64_OPND_SVE_UIMM8_53
:
5911 case AARCH64_OPND_IMM_ROT1
:
5912 case AARCH64_OPND_IMM_ROT2
:
5913 case AARCH64_OPND_IMM_ROT3
:
5914 case AARCH64_OPND_SVE_IMM_ROT1
:
5915 case AARCH64_OPND_SVE_IMM_ROT2
:
5916 case AARCH64_OPND_SVE_IMM_ROT3
:
5917 po_imm_nc_or_fail ();
5918 info
->imm
.value
= val
;
5921 case AARCH64_OPND_SVE_AIMM
:
5922 case AARCH64_OPND_SVE_ASIMM
:
5923 po_imm_nc_or_fail ();
5924 info
->imm
.value
= val
;
5925 skip_whitespace (str
);
5926 if (skip_past_comma (&str
))
5927 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5929 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5932 case AARCH64_OPND_SVE_PATTERN
:
5933 po_enum_or_fail (aarch64_sve_pattern_array
);
5934 info
->imm
.value
= val
;
5937 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5938 po_enum_or_fail (aarch64_sve_pattern_array
);
5939 info
->imm
.value
= val
;
5940 if (skip_past_comma (&str
)
5941 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5943 if (!info
->shifter
.operator_present
)
5945 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5946 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5947 info
->shifter
.amount
= 1;
5951 case AARCH64_OPND_SVE_PRFOP
:
5952 po_enum_or_fail (aarch64_sve_prfop_array
);
5953 info
->imm
.value
= val
;
5956 case AARCH64_OPND_UIMM7
:
5957 po_imm_or_fail (0, 127);
5958 info
->imm
.value
= val
;
5961 case AARCH64_OPND_IDX
:
5962 case AARCH64_OPND_MASK
:
5963 case AARCH64_OPND_BIT_NUM
:
5964 case AARCH64_OPND_IMMR
:
5965 case AARCH64_OPND_IMMS
:
5966 po_imm_or_fail (0, 63);
5967 info
->imm
.value
= val
;
5970 case AARCH64_OPND_IMM0
:
5971 po_imm_nc_or_fail ();
5974 set_fatal_syntax_error (_("immediate zero expected"));
5977 info
->imm
.value
= 0;
5980 case AARCH64_OPND_FPIMM0
:
5983 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5984 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5985 it is probably not worth the effort to support it. */
5986 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5989 || !(res2
= parse_constant_immediate (&str
, &val
,
5992 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5994 info
->imm
.value
= 0;
5995 info
->imm
.is_fp
= 1;
5998 set_fatal_syntax_error (_("immediate zero expected"));
6002 case AARCH64_OPND_IMM_MOV
:
6005 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6006 reg_name_p (str
, REG_TYPE_VN
))
6009 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6011 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6012 later. fix_mov_imm_insn will try to determine a machine
6013 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6014 message if the immediate cannot be moved by a single
6016 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6017 inst
.base
.operands
[i
].skip
= 1;
6021 case AARCH64_OPND_SIMD_IMM
:
6022 case AARCH64_OPND_SIMD_IMM_SFT
:
6023 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6025 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6027 /* need_libopcodes_p */ 1,
6030 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6031 shift, we don't check it here; we leave the checking to
6032 the libopcodes (operand_general_constraint_met_p). By
6033 doing this, we achieve better diagnostics. */
6034 if (skip_past_comma (&str
)
6035 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6037 if (!info
->shifter
.operator_present
6038 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6040 /* Default to LSL if not present. Libopcodes prefers shifter
6041 kind to be explicit. */
6042 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6043 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6047 case AARCH64_OPND_FPIMM
:
6048 case AARCH64_OPND_SIMD_FPIMM
:
6049 case AARCH64_OPND_SVE_FPIMM8
:
6054 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6055 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6056 || !aarch64_imm_float_p (qfloat
))
6059 set_fatal_syntax_error (_("invalid floating-point"
6063 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6064 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6068 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6069 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6070 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6075 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6076 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6079 set_fatal_syntax_error (_("invalid floating-point"
6083 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6084 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6088 case AARCH64_OPND_LIMM
:
6089 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6090 SHIFTED_LOGIC_IMM
));
6091 if (info
->shifter
.operator_present
)
6093 set_fatal_syntax_error
6094 (_("shift not allowed for bitmask immediate"));
6097 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6099 /* need_libopcodes_p */ 1,
6103 case AARCH64_OPND_AIMM
:
6104 if (opcode
->op
== OP_ADD
)
6105 /* ADD may have relocation types. */
6106 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6107 SHIFTED_ARITH_IMM
));
6109 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6110 SHIFTED_ARITH_IMM
));
6111 switch (inst
.reloc
.type
)
6113 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6114 info
->shifter
.amount
= 12;
6116 case BFD_RELOC_UNUSED
:
6117 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6118 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6119 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6120 inst
.reloc
.pc_rel
= 0;
6125 info
->imm
.value
= 0;
6126 if (!info
->shifter
.operator_present
)
6128 /* Default to LSL if not present. Libopcodes prefers shifter
6129 kind to be explicit. */
6130 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6131 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6135 case AARCH64_OPND_HALF
:
6137 /* #<imm16> or relocation. */
6138 int internal_fixup_p
;
6139 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6140 if (internal_fixup_p
)
6141 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6142 skip_whitespace (str
);
6143 if (skip_past_comma (&str
))
6145 /* {, LSL #<shift>} */
6146 if (! aarch64_gas_internal_fixup_p ())
6148 set_fatal_syntax_error (_("can't mix relocation modifier "
6149 "with explicit shift"));
6152 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6155 inst
.base
.operands
[i
].shifter
.amount
= 0;
6156 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6157 inst
.base
.operands
[i
].imm
.value
= 0;
6158 if (! process_movw_reloc_info ())
6163 case AARCH64_OPND_EXCEPTION
:
6164 case AARCH64_OPND_UNDEFINED
:
6165 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6167 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6169 /* need_libopcodes_p */ 0,
6173 case AARCH64_OPND_NZCV
:
6175 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6179 info
->imm
.value
= nzcv
->value
;
6182 po_imm_or_fail (0, 15);
6183 info
->imm
.value
= val
;
6187 case AARCH64_OPND_COND
:
6188 case AARCH64_OPND_COND1
:
6193 while (ISALPHA (*str
));
6194 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6195 if (info
->cond
== NULL
)
6197 set_syntax_error (_("invalid condition"));
6200 else if (operands
[i
] == AARCH64_OPND_COND1
6201 && (info
->cond
->value
& 0xe) == 0xe)
6203 /* Do not allow AL or NV. */
6204 set_default_error ();
6210 case AARCH64_OPND_ADDR_ADRP
:
6211 po_misc_or_fail (parse_adrp (&str
));
6212 /* Clear the value as operand needs to be relocated. */
6213 info
->imm
.value
= 0;
6216 case AARCH64_OPND_ADDR_PCREL14
:
6217 case AARCH64_OPND_ADDR_PCREL19
:
6218 case AARCH64_OPND_ADDR_PCREL21
:
6219 case AARCH64_OPND_ADDR_PCREL26
:
6220 po_misc_or_fail (parse_address (&str
, info
));
6221 if (!info
->addr
.pcrel
)
6223 set_syntax_error (_("invalid pc-relative address"));
6226 if (inst
.gen_lit_pool
6227 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6229 /* Only permit "=value" in the literal load instructions.
6230 The literal will be generated by programmer_friendly_fixup. */
6231 set_syntax_error (_("invalid use of \"=immediate\""));
6234 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6236 set_syntax_error (_("unrecognized relocation suffix"));
6239 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6241 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6242 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6246 info
->imm
.value
= 0;
6247 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6248 switch (opcode
->iclass
)
6252 /* e.g. CBZ or B.COND */
6253 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6254 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6258 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6259 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6263 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6265 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6266 : BFD_RELOC_AARCH64_JUMP26
;
6269 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6270 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6273 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6274 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6280 inst
.reloc
.pc_rel
= 1;
6284 case AARCH64_OPND_ADDR_SIMPLE
:
6285 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6287 /* [<Xn|SP>{, #<simm>}] */
6289 /* First use the normal address-parsing routines, to get
6290 the usual syntax errors. */
6291 po_misc_or_fail (parse_address (&str
, info
));
6292 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6293 || !info
->addr
.preind
|| info
->addr
.postind
6294 || info
->addr
.writeback
)
6296 set_syntax_error (_("invalid addressing mode"));
6300 /* Then retry, matching the specific syntax of these addresses. */
6302 po_char_or_fail ('[');
6303 po_reg_or_fail (REG_TYPE_R64_SP
);
6304 /* Accept optional ", #0". */
6305 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6306 && skip_past_char (&str
, ','))
6308 skip_past_char (&str
, '#');
6309 if (! skip_past_char (&str
, '0'))
6311 set_fatal_syntax_error
6312 (_("the optional immediate offset can only be 0"));
6316 po_char_or_fail (']');
6320 case AARCH64_OPND_ADDR_REGOFF
:
6321 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6322 po_misc_or_fail (parse_address (&str
, info
));
6324 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6325 || !info
->addr
.preind
|| info
->addr
.postind
6326 || info
->addr
.writeback
)
6328 set_syntax_error (_("invalid addressing mode"));
6331 if (!info
->shifter
.operator_present
)
6333 /* Default to LSL if not present. Libopcodes prefers shifter
6334 kind to be explicit. */
6335 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6336 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6338 /* Qualifier to be deduced by libopcodes. */
6341 case AARCH64_OPND_ADDR_SIMM7
:
6342 po_misc_or_fail (parse_address (&str
, info
));
6343 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6344 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6346 set_syntax_error (_("invalid addressing mode"));
6349 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6351 set_syntax_error (_("relocation not allowed"));
6354 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6356 /* need_libopcodes_p */ 1,
6360 case AARCH64_OPND_ADDR_SIMM9
:
6361 case AARCH64_OPND_ADDR_SIMM9_2
:
6362 case AARCH64_OPND_ADDR_SIMM11
:
6363 case AARCH64_OPND_ADDR_SIMM13
:
6364 po_misc_or_fail (parse_address (&str
, info
));
6365 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6366 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6367 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6368 && info
->addr
.writeback
))
6370 set_syntax_error (_("invalid addressing mode"));
6373 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6375 set_syntax_error (_("relocation not allowed"));
6378 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6380 /* need_libopcodes_p */ 1,
6384 case AARCH64_OPND_ADDR_SIMM10
:
6385 case AARCH64_OPND_ADDR_OFFSET
:
6386 po_misc_or_fail (parse_address (&str
, info
));
6387 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6388 || !info
->addr
.preind
|| info
->addr
.postind
)
6390 set_syntax_error (_("invalid addressing mode"));
6393 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6395 set_syntax_error (_("relocation not allowed"));
6398 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6400 /* need_libopcodes_p */ 1,
6404 case AARCH64_OPND_ADDR_UIMM12
:
6405 po_misc_or_fail (parse_address (&str
, info
));
6406 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6407 || !info
->addr
.preind
|| info
->addr
.writeback
)
6409 set_syntax_error (_("invalid addressing mode"));
6412 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6413 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6414 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6416 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6418 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6420 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6422 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6423 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6424 /* Leave qualifier to be determined by libopcodes. */
6427 case AARCH64_OPND_SIMD_ADDR_POST
:
6428 /* [<Xn|SP>], <Xm|#<amount>> */
6429 po_misc_or_fail (parse_address (&str
, info
));
6430 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6432 set_syntax_error (_("invalid addressing mode"));
6435 if (!info
->addr
.offset
.is_reg
)
6437 if (inst
.reloc
.exp
.X_op
== O_constant
)
6438 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6441 set_fatal_syntax_error
6442 (_("writeback value must be an immediate constant"));
6449 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6450 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6451 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6452 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6453 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6454 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6455 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6456 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6457 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6458 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6459 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6460 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6461 /* [X<n>{, #imm, MUL VL}]
6463 but recognizing SVE registers. */
6464 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6465 &offset_qualifier
));
6466 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6468 set_syntax_error (_("invalid addressing mode"));
6472 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6473 || !info
->addr
.preind
|| info
->addr
.writeback
)
6475 set_syntax_error (_("invalid addressing mode"));
6478 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6479 || inst
.reloc
.exp
.X_op
!= O_constant
)
6481 /* Make sure this has priority over
6482 "invalid addressing mode". */
6483 set_fatal_syntax_error (_("constant offset required"));
6486 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6489 case AARCH64_OPND_SVE_ADDR_R
:
6490 /* [<Xn|SP>{, <R><m>}]
6491 but recognizing SVE registers. */
6492 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6493 &offset_qualifier
));
6494 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6496 offset_qualifier
= AARCH64_OPND_QLF_X
;
6497 info
->addr
.offset
.is_reg
= 1;
6498 info
->addr
.offset
.regno
= 31;
6500 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6501 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6503 set_syntax_error (_("invalid addressing mode"));
6508 case AARCH64_OPND_SVE_ADDR_RR
:
6509 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6510 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6511 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6512 case AARCH64_OPND_SVE_ADDR_RX
:
6513 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6514 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6515 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6516 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6517 but recognizing SVE registers. */
6518 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6519 &offset_qualifier
));
6520 if (base_qualifier
!= AARCH64_OPND_QLF_X
6521 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6523 set_syntax_error (_("invalid addressing mode"));
6528 case AARCH64_OPND_SVE_ADDR_RZ
:
6529 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6530 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6531 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6532 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6533 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6534 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6535 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6536 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6537 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6538 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6539 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6540 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6541 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6542 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6543 &offset_qualifier
));
6544 if (base_qualifier
!= AARCH64_OPND_QLF_X
6545 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6546 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6548 set_syntax_error (_("invalid addressing mode"));
6551 info
->qualifier
= offset_qualifier
;
6554 case AARCH64_OPND_SVE_ADDR_ZX
:
6555 /* [Zn.<T>{, <Xm>}]. */
6556 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6557 &offset_qualifier
));
6559 base_qualifier either S_S or S_D
6560 offset_qualifier must be X
6562 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6563 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6564 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6566 set_syntax_error (_("invalid addressing mode"));
6569 info
->qualifier
= base_qualifier
;
6570 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6571 || !info
->addr
.preind
|| info
->addr
.writeback
6572 || info
->shifter
.operator_present
!= 0)
6574 set_syntax_error (_("invalid addressing mode"));
6577 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6581 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6582 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6583 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6584 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6585 /* [Z<n>.<T>{, #imm}] */
6586 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6587 &offset_qualifier
));
6588 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6589 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6591 set_syntax_error (_("invalid addressing mode"));
6594 info
->qualifier
= base_qualifier
;
6597 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6598 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6599 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6600 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6601 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6605 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6607 here since we get better error messages by leaving it to
6608 the qualifier checking routines. */
6609 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6610 &offset_qualifier
));
6611 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6612 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6613 || offset_qualifier
!= base_qualifier
)
6615 set_syntax_error (_("invalid addressing mode"));
6618 info
->qualifier
= base_qualifier
;
6621 case AARCH64_OPND_SYSREG
:
6623 uint32_t sysreg_flags
;
6624 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6625 &sysreg_flags
)) == PARSE_FAIL
)
6627 set_syntax_error (_("unknown or missing system register name"));
6630 inst
.base
.operands
[i
].sysreg
.value
= val
;
6631 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6635 case AARCH64_OPND_PSTATEFIELD
:
6636 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6639 set_syntax_error (_("unknown or missing PSTATE field name"));
6642 inst
.base
.operands
[i
].pstatefield
= val
;
6645 case AARCH64_OPND_SYSREG_IC
:
6646 inst
.base
.operands
[i
].sysins_op
=
6647 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6650 case AARCH64_OPND_SYSREG_DC
:
6651 inst
.base
.operands
[i
].sysins_op
=
6652 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6655 case AARCH64_OPND_SYSREG_AT
:
6656 inst
.base
.operands
[i
].sysins_op
=
6657 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6660 case AARCH64_OPND_SYSREG_SR
:
6661 inst
.base
.operands
[i
].sysins_op
=
6662 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6665 case AARCH64_OPND_SYSREG_TLBI
:
6666 inst
.base
.operands
[i
].sysins_op
=
6667 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6669 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6671 set_fatal_syntax_error ( _("unknown or missing operation name"));
6676 case AARCH64_OPND_BARRIER
:
6677 case AARCH64_OPND_BARRIER_ISB
:
6678 val
= parse_barrier (&str
);
6679 if (val
!= PARSE_FAIL
6680 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6682 /* ISB only accepts options name 'sy'. */
6684 (_("the specified option is not accepted in ISB"));
6685 /* Turn off backtrack as this optional operand is present. */
6689 /* This is an extension to accept a 0..15 immediate. */
6690 if (val
== PARSE_FAIL
)
6691 po_imm_or_fail (0, 15);
6692 info
->barrier
= aarch64_barrier_options
+ val
;
6695 case AARCH64_OPND_PRFOP
:
6696 val
= parse_pldop (&str
);
6697 /* This is an extension to accept a 0..31 immediate. */
6698 if (val
== PARSE_FAIL
)
6699 po_imm_or_fail (0, 31);
6700 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6703 case AARCH64_OPND_BARRIER_PSB
:
6704 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6705 if (val
== PARSE_FAIL
)
6709 case AARCH64_OPND_BTI_TARGET
:
6710 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6711 if (val
== PARSE_FAIL
)
6716 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6719 /* If we get here, this operand was successfully parsed. */
6720 inst
.base
.operands
[i
].present
= 1;
6724 /* The parse routine should already have set the error, but in case
6725 not, set a default one here. */
6727 set_default_error ();
6729 if (! backtrack_pos
)
6730 goto parse_operands_return
;
6733 /* We reach here because this operand is marked as optional, and
6734 either no operand was supplied or the operand was supplied but it
6735 was syntactically incorrect. In the latter case we report an
6736 error. In the former case we perform a few more checks before
6737 dropping through to the code to insert the default operand. */
6739 char *tmp
= backtrack_pos
;
6740 char endchar
= END_OF_INSN
;
6742 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6744 skip_past_char (&tmp
, ',');
6746 if (*tmp
!= endchar
)
6747 /* The user has supplied an operand in the wrong format. */
6748 goto parse_operands_return
;
6750 /* Make sure there is not a comma before the optional operand.
6751 For example the fifth operand of 'sys' is optional:
6753 sys #0,c0,c0,#0, <--- wrong
6754 sys #0,c0,c0,#0 <--- correct. */
6755 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6757 set_fatal_syntax_error
6758 (_("unexpected comma before the omitted optional operand"));
6759 goto parse_operands_return
;
6763 /* Reaching here means we are dealing with an optional operand that is
6764 omitted from the assembly line. */
6765 gas_assert (optional_operand_p (opcode
, i
));
6767 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6769 /* Try again, skipping the optional operand at backtrack_pos. */
6770 str
= backtrack_pos
;
6773 /* Clear any error record after the omitted optional operand has been
6774 successfully handled. */
6778 /* Check if we have parsed all the operands. */
6779 if (*str
!= '\0' && ! error_p ())
6781 /* Set I to the index of the last present operand; this is
6782 for the purpose of diagnostics. */
6783 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6785 set_fatal_syntax_error
6786 (_("unexpected characters following instruction"));
6789 parse_operands_return
:
6793 DEBUG_TRACE ("parsing FAIL: %s - %s",
6794 operand_mismatch_kind_names
[get_error_kind ()],
6795 get_error_message ());
6796 /* Record the operand error properly; this is useful when there
6797 are multiple instruction templates for a mnemonic name, so that
6798 later on, we can select the error that most closely describes
6800 record_operand_error (opcode
, i
, get_error_kind (),
6801 get_error_message ());
6806 DEBUG_TRACE ("parsing SUCCESS");
6811 /* It does some fix-up to provide some programmer friendly feature while
6812 keeping the libopcodes happy, i.e. libopcodes only accepts
6813 the preferred architectural syntax.
6814 Return FALSE if there is any failure; otherwise return TRUE. */
6817 programmer_friendly_fixup (aarch64_instruction
*instr
)
6819 aarch64_inst
*base
= &instr
->base
;
6820 const aarch64_opcode
*opcode
= base
->opcode
;
6821 enum aarch64_op op
= opcode
->op
;
6822 aarch64_opnd_info
*operands
= base
->operands
;
6824 DEBUG_TRACE ("enter");
6826 switch (opcode
->iclass
)
6829 /* TBNZ Xn|Wn, #uimm6, label
6830 Test and Branch Not Zero: conditionally jumps to label if bit number
6831 uimm6 in register Xn is not zero. The bit number implies the width of
6832 the register, which may be written and should be disassembled as Wn if
6833 uimm is less than 32. */
6834 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6836 if (operands
[1].imm
.value
>= 32)
6838 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6842 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6846 /* LDR Wt, label | =value
6847 As a convenience assemblers will typically permit the notation
6848 "=value" in conjunction with the pc-relative literal load instructions
6849 to automatically place an immediate value or symbolic address in a
6850 nearby literal pool and generate a hidden label which references it.
6851 ISREG has been set to 0 in the case of =value. */
6852 if (instr
->gen_lit_pool
6853 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6855 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6856 if (op
== OP_LDRSW_LIT
)
6858 if (instr
->reloc
.exp
.X_op
!= O_constant
6859 && instr
->reloc
.exp
.X_op
!= O_big
6860 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6862 record_operand_error (opcode
, 1,
6863 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6864 _("constant expression expected"));
6867 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6869 record_operand_error (opcode
, 1,
6870 AARCH64_OPDE_OTHER_ERROR
,
6871 _("literal pool insertion failed"));
6879 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6880 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6881 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6882 A programmer-friendly assembler should accept a destination Xd in
6883 place of Wd, however that is not the preferred form for disassembly.
6885 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6886 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6887 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6888 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6893 /* In the 64-bit form, the final register operand is written as Wm
6894 for all but the (possibly omitted) UXTX/LSL and SXTX
6896 As a programmer-friendly assembler, we accept e.g.
6897 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6898 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6899 int idx
= aarch64_operand_index (opcode
->operands
,
6900 AARCH64_OPND_Rm_EXT
);
6901 gas_assert (idx
== 1 || idx
== 2);
6902 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6903 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6904 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6905 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6906 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6907 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6915 DEBUG_TRACE ("exit with SUCCESS");
6919 /* Check for loads and stores that will cause unpredictable behavior. */
6922 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6924 aarch64_inst
*base
= &instr
->base
;
6925 const aarch64_opcode
*opcode
= base
->opcode
;
6926 const aarch64_opnd_info
*opnds
= base
->operands
;
6927 switch (opcode
->iclass
)
6934 /* Loading/storing the base register is unpredictable if writeback. */
6935 if ((aarch64_get_operand_class (opnds
[0].type
)
6936 == AARCH64_OPND_CLASS_INT_REG
)
6937 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6938 && opnds
[1].addr
.base_regno
!= REG_SP
6939 /* Exempt STG/STZG/ST2G/STZ2G. */
6940 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6941 && opnds
[1].addr
.writeback
)
6942 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6946 case ldstnapair_offs
:
6947 case ldstpair_indexed
:
6948 /* Loading/storing the base register is unpredictable if writeback. */
6949 if ((aarch64_get_operand_class (opnds
[0].type
)
6950 == AARCH64_OPND_CLASS_INT_REG
)
6951 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6952 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6953 && opnds
[2].addr
.base_regno
!= REG_SP
6955 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6956 && opnds
[2].addr
.writeback
)
6957 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6958 /* Load operations must load different registers. */
6959 if ((opcode
->opcode
& (1 << 22))
6960 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6961 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6965 /* It is unpredictable if the destination and status registers are the
6967 if ((aarch64_get_operand_class (opnds
[0].type
)
6968 == AARCH64_OPND_CLASS_INT_REG
)
6969 && (aarch64_get_operand_class (opnds
[1].type
)
6970 == AARCH64_OPND_CLASS_INT_REG
)
6971 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6972 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6973 as_warn (_("unpredictable: identical transfer and status registers"
6985 force_automatic_sequence_close (void)
6987 if (now_instr_sequence
.instr
)
6989 as_warn (_("previous `%s' sequence has not been closed"),
6990 now_instr_sequence
.instr
->opcode
->name
);
6991 init_insn_sequence (NULL
, &now_instr_sequence
);
6995 /* A wrapper function to interface with libopcodes on encoding and
6996 record the error message if there is any.
6998 Return TRUE on success; otherwise return FALSE. */
7001 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7004 aarch64_operand_error error_info
;
7005 memset (&error_info
, '\0', sizeof (error_info
));
7006 error_info
.kind
= AARCH64_OPDE_NIL
;
7007 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7008 && !error_info
.non_fatal
)
7011 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7012 record_operand_error_info (opcode
, &error_info
);
7013 return error_info
.non_fatal
;
7016 #ifdef DEBUG_AARCH64
7018 dump_opcode_operands (const aarch64_opcode
*opcode
)
7021 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7023 aarch64_verbose ("\t\t opnd%d: %s", i
,
7024 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7025 ? aarch64_get_operand_name (opcode
->operands
[i
])
7026 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7030 #endif /* DEBUG_AARCH64 */
7032 /* This is the guts of the machine-dependent assembler. STR points to a
7033 machine dependent instruction. This function is supposed to emit
7034 the frags/bytes it assembles to. */
7037 md_assemble (char *str
)
7040 templates
*template;
7041 aarch64_opcode
*opcode
;
7042 aarch64_inst
*inst_base
;
7043 unsigned saved_cond
;
7045 /* Align the previous label if needed. */
7046 if (last_label_seen
!= NULL
)
7048 symbol_set_frag (last_label_seen
, frag_now
);
7049 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7050 S_SET_SEGMENT (last_label_seen
, now_seg
);
7053 /* Update the current insn_sequence from the segment. */
7054 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7056 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7058 DEBUG_TRACE ("\n\n");
7059 DEBUG_TRACE ("==============================");
7060 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7062 template = opcode_lookup (&p
);
7065 /* It wasn't an instruction, but it might be a register alias of
7066 the form alias .req reg directive. */
7067 if (!create_register_alias (str
, p
))
7068 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7073 skip_whitespace (p
);
7076 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7077 get_mnemonic_name (str
), str
);
7081 init_operand_error_report ();
7083 /* Sections are assumed to start aligned. In executable section, there is no
7084 MAP_DATA symbol pending. So we only align the address during
7085 MAP_DATA --> MAP_INSN transition.
7086 For other sections, this is not guaranteed. */
7087 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7088 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7089 frag_align_code (2, 0);
7091 saved_cond
= inst
.cond
;
7092 reset_aarch64_instruction (&inst
);
7093 inst
.cond
= saved_cond
;
7095 /* Iterate through all opcode entries with the same mnemonic name. */
7098 opcode
= template->opcode
;
7100 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7101 #ifdef DEBUG_AARCH64
7103 dump_opcode_operands (opcode
);
7104 #endif /* DEBUG_AARCH64 */
7106 mapping_state (MAP_INSN
);
7108 inst_base
= &inst
.base
;
7109 inst_base
->opcode
= opcode
;
7111 /* Truly conditionally executed instructions, e.g. b.cond. */
7112 if (opcode
->flags
& F_COND
)
7114 gas_assert (inst
.cond
!= COND_ALWAYS
);
7115 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7116 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7118 else if (inst
.cond
!= COND_ALWAYS
)
7120 /* It shouldn't arrive here, where the assembly looks like a
7121 conditional instruction but the found opcode is unconditional. */
7126 if (parse_operands (p
, opcode
)
7127 && programmer_friendly_fixup (&inst
)
7128 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7130 /* Check that this instruction is supported for this CPU. */
7131 if (!opcode
->avariant
7132 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7134 as_bad (_("selected processor does not support `%s'"), str
);
7138 warn_unpredictable_ldst (&inst
, str
);
7140 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7141 || !inst
.reloc
.need_libopcodes_p
)
7145 /* If there is relocation generated for the instruction,
7146 store the instruction information for the future fix-up. */
7147 struct aarch64_inst
*copy
;
7148 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7149 copy
= XNEW (struct aarch64_inst
);
7150 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7154 /* Issue non-fatal messages if any. */
7155 output_operand_error_report (str
, TRUE
);
7159 template = template->next
;
7160 if (template != NULL
)
7162 reset_aarch64_instruction (&inst
);
7163 inst
.cond
= saved_cond
;
7166 while (template != NULL
);
7168 /* Issue the error messages if any. */
7169 output_operand_error_report (str
, FALSE
);
7172 /* Various frobbings of labels and their addresses. */
7175 aarch64_start_line_hook (void)
7177 last_label_seen
= NULL
;
7181 aarch64_frob_label (symbolS
* sym
)
7183 last_label_seen
= sym
;
7185 dwarf2_emit_label (sym
);
7189 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7191 /* Check to see if we have a block to close. */
7192 force_automatic_sequence_close ();
7196 aarch64_data_in_code (void)
7198 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7200 *input_line_pointer
= '/';
7201 input_line_pointer
+= 5;
7202 *input_line_pointer
= 0;
7210 aarch64_canonicalize_symbol_name (char *name
)
7214 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7215 *(name
+ len
- 5) = 0;
7220 /* Table of all register names defined by default. The user can
7221 define additional names with .req. Note that all register names
7222 should appear in both upper and lowercase variants. Some registers
7223 also have mixed-case names. */
7225 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7226 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7227 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7228 #define REGSET16(p,t) \
7229 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7230 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7231 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7232 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7233 #define REGSET31(p,t) \
7235 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7236 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7237 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7238 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7239 #define REGSET(p,t) \
7240 REGSET31(p,t), REGNUM(p,31,t)
7242 /* These go into aarch64_reg_hsh hash-table. */
7243 static const reg_entry reg_names
[] = {
7244 /* Integer registers. */
7245 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7246 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7248 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7249 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7250 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7251 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7252 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7253 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7255 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7256 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7258 /* Floating-point single precision registers. */
7259 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7261 /* Floating-point double precision registers. */
7262 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7264 /* Floating-point half precision registers. */
7265 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7267 /* Floating-point byte precision registers. */
7268 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7270 /* Floating-point quad precision registers. */
7271 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7273 /* FP/SIMD registers. */
7274 REGSET (v
, VN
), REGSET (V
, VN
),
7276 /* SVE vector registers. */
7277 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7279 /* SVE predicate registers. */
7280 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7298 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7299 static const asm_nzcv nzcv_names
[] = {
7300 {"nzcv", B (n
, z
, c
, v
)},
7301 {"nzcV", B (n
, z
, c
, V
)},
7302 {"nzCv", B (n
, z
, C
, v
)},
7303 {"nzCV", B (n
, z
, C
, V
)},
7304 {"nZcv", B (n
, Z
, c
, v
)},
7305 {"nZcV", B (n
, Z
, c
, V
)},
7306 {"nZCv", B (n
, Z
, C
, v
)},
7307 {"nZCV", B (n
, Z
, C
, V
)},
7308 {"Nzcv", B (N
, z
, c
, v
)},
7309 {"NzcV", B (N
, z
, c
, V
)},
7310 {"NzCv", B (N
, z
, C
, v
)},
7311 {"NzCV", B (N
, z
, C
, V
)},
7312 {"NZcv", B (N
, Z
, c
, v
)},
7313 {"NZcV", B (N
, Z
, c
, V
)},
7314 {"NZCv", B (N
, Z
, C
, v
)},
7315 {"NZCV", B (N
, Z
, C
, V
)}
7328 /* MD interface: bits in the object file. */
7330 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7331 for use in the a.out file, and stores them in the array pointed to by buf.
7332 This knows about the endian-ness of the target machine and does
7333 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7334 2 (short) and 4 (long) Floating numbers are put out as a series of
7335 LITTLENUMS (shorts, here at least). */
7338 md_number_to_chars (char *buf
, valueT val
, int n
)
7340 if (target_big_endian
)
7341 number_to_chars_bigendian (buf
, val
, n
);
7343 number_to_chars_littleendian (buf
, val
, n
);
7346 /* MD interface: Sections. */
7348 /* Estimate the size of a frag before relaxing. Assume everything fits in
7352 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7358 /* Round up a section size to the appropriate boundary. */
7361 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7366 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7367 of an rs_align_code fragment.
7369 Here we fill the frag with the appropriate info for padding the
7370 output stream. The resulting frag will consist of a fixed (fr_fix)
7371 and of a repeating (fr_var) part.
7373 The fixed content is always emitted before the repeating content and
7374 these two parts are used as follows in constructing the output:
7375 - the fixed part will be used to align to a valid instruction word
7376 boundary, in case that we start at a misaligned address; as no
7377 executable instruction can live at the misaligned location, we
7378 simply fill with zeros;
7379 - the variable part will be used to cover the remaining padding and
7380 we fill using the AArch64 NOP instruction.
7382 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7383 enough storage space for up to 3 bytes for padding the back to a valid
7384 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7387 aarch64_handle_align (fragS
* fragP
)
7389 /* NOP = d503201f */
7390 /* AArch64 instructions are always little-endian. */
7391 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7393 int bytes
, fix
, noop_size
;
7396 if (fragP
->fr_type
!= rs_align_code
)
7399 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7400 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7403 gas_assert (fragP
->tc_frag_data
.recorded
);
7406 noop_size
= sizeof (aarch64_noop
);
7408 fix
= bytes
& (noop_size
- 1);
7412 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7416 fragP
->fr_fix
+= fix
;
7420 memcpy (p
, aarch64_noop
, noop_size
);
7421 fragP
->fr_var
= noop_size
;
7424 /* Perform target specific initialisation of a frag.
7425 Note - despite the name this initialisation is not done when the frag
7426 is created, but only when its type is assigned. A frag can be created
7427 and used a long time before its type is set, so beware of assuming that
7428 this initialisation is performed first. */
7432 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7433 int max_chars ATTRIBUTE_UNUSED
)
7437 #else /* OBJ_ELF is defined. */
7439 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7441 /* Record a mapping symbol for alignment frags. We will delete this
7442 later if the alignment ends up empty. */
7443 if (!fragP
->tc_frag_data
.recorded
)
7444 fragP
->tc_frag_data
.recorded
= 1;
7446 /* PR 21809: Do not set a mapping state for debug sections
7447 - it just confuses other tools. */
7448 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7451 switch (fragP
->fr_type
)
7455 mapping_state_2 (MAP_DATA
, max_chars
);
7458 /* PR 20364: We can get alignment frags in code sections,
7459 so do not just assume that we should use the MAP_DATA state. */
7460 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7463 mapping_state_2 (MAP_INSN
, max_chars
);
7470 /* Initialize the DWARF-2 unwind information for this procedure. */
7473 tc_aarch64_frame_initial_instructions (void)
7475 cfi_add_CFA_def_cfa (REG_SP
, 0);
7477 #endif /* OBJ_ELF */
7479 /* Convert REGNAME to a DWARF-2 register number. */
7482 tc_aarch64_regname_to_dw2regnum (char *regname
)
7484 const reg_entry
*reg
= parse_reg (®name
);
7490 case REG_TYPE_SP_32
:
7491 case REG_TYPE_SP_64
:
7501 return reg
->number
+ 64;
7509 /* Implement DWARF2_ADDR_SIZE. */
7512 aarch64_dwarf2_addr_size (void)
7514 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7518 return bfd_arch_bits_per_address (stdoutput
) / 8;
7521 /* MD interface: Symbol and relocation handling. */
7523 /* Return the address within the segment that a PC-relative fixup is
7524 relative to. For AArch64 PC-relative fixups applied to instructions
7525 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7528 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7530 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7532 /* If this is pc-relative and we are going to emit a relocation
7533 then we just want to put out any pipeline compensation that the linker
7534 will need. Otherwise we want to use the calculated base. */
7536 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7537 || aarch64_force_relocation (fixP
)))
7540 /* AArch64 should be consistent for all pc-relative relocations. */
7541 return base
+ AARCH64_PCREL_OFFSET
;
7544 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7545 Otherwise we have no need to default values of symbols. */
7548 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7551 if (name
[0] == '_' && name
[1] == 'G'
7552 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7556 if (symbol_find (name
))
7557 as_bad (_("GOT already in the symbol table"));
7559 GOT_symbol
= symbol_new (name
, undefined_section
,
7560 &zero_address_frag
, 0);
7570 /* Return non-zero if the indicated VALUE has overflowed the maximum
7571 range expressible by a unsigned number with the indicated number of
7575 unsigned_overflow (valueT value
, unsigned bits
)
7578 if (bits
>= sizeof (valueT
) * 8)
7580 lim
= (valueT
) 1 << bits
;
7581 return (value
>= lim
);
7585 /* Return non-zero if the indicated VALUE has overflowed the maximum
7586 range expressible by an signed number with the indicated number of
7590 signed_overflow (offsetT value
, unsigned bits
)
7593 if (bits
>= sizeof (offsetT
) * 8)
7595 lim
= (offsetT
) 1 << (bits
- 1);
7596 return (value
< -lim
|| value
>= lim
);
7599 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7600 unsigned immediate offset load/store instruction, try to encode it as
7601 an unscaled, 9-bit, signed immediate offset load/store instruction.
7602 Return TRUE if it is successful; otherwise return FALSE.
7604 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7605 in response to the standard LDR/STR mnemonics when the immediate offset is
7606 unambiguous, i.e. when it is negative or unaligned. */
7609 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7612 enum aarch64_op new_op
;
7613 const aarch64_opcode
*new_opcode
;
7615 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7617 switch (instr
->opcode
->op
)
7619 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7620 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7621 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7622 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7623 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7624 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7625 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7626 case OP_STR_POS
: new_op
= OP_STUR
; break;
7627 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7628 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7629 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7630 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7631 default: new_op
= OP_NIL
; break;
7634 if (new_op
== OP_NIL
)
7637 new_opcode
= aarch64_get_opcode (new_op
);
7638 gas_assert (new_opcode
!= NULL
);
7640 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7641 instr
->opcode
->op
, new_opcode
->op
);
7643 aarch64_replace_opcode (instr
, new_opcode
);
7645 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7646 qualifier matching may fail because the out-of-date qualifier will
7647 prevent the operand being updated with a new and correct qualifier. */
7648 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7649 AARCH64_OPND_ADDR_SIMM9
);
7650 gas_assert (idx
== 1);
7651 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7653 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7655 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7662 /* Called by fix_insn to fix a MOV immediate alias instruction.
7664 Operand for a generic move immediate instruction, which is an alias
7665 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7666 a 32-bit/64-bit immediate value into general register. An assembler error
7667 shall result if the immediate cannot be created by a single one of these
7668 instructions. If there is a choice, then to ensure reversability an
7669 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7672 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7674 const aarch64_opcode
*opcode
;
7676 /* Need to check if the destination is SP/ZR. The check has to be done
7677 before any aarch64_replace_opcode. */
7678 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7679 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7681 instr
->operands
[1].imm
.value
= value
;
7682 instr
->operands
[1].skip
= 0;
7686 /* Try the MOVZ alias. */
7687 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7688 aarch64_replace_opcode (instr
, opcode
);
7689 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7690 &instr
->value
, NULL
, NULL
, insn_sequence
))
7692 put_aarch64_insn (buf
, instr
->value
);
7695 /* Try the MOVK alias. */
7696 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7697 aarch64_replace_opcode (instr
, opcode
);
7698 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7699 &instr
->value
, NULL
, NULL
, insn_sequence
))
7701 put_aarch64_insn (buf
, instr
->value
);
7706 if (try_mov_bitmask_p
)
7708 /* Try the ORR alias. */
7709 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7710 aarch64_replace_opcode (instr
, opcode
);
7711 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7712 &instr
->value
, NULL
, NULL
, insn_sequence
))
7714 put_aarch64_insn (buf
, instr
->value
);
7719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7720 _("immediate cannot be moved by a single instruction"));
7723 /* An instruction operand which is immediate related may have symbol used
7724 in the assembly, e.g.
7727 .set u32, 0x00ffff00
7729 At the time when the assembly instruction is parsed, a referenced symbol,
7730 like 'u32' in the above example may not have been seen; a fixS is created
7731 in such a case and is handled here after symbols have been resolved.
7732 Instruction is fixed up with VALUE using the information in *FIXP plus
7733 extra information in FLAGS.
7735 This function is called by md_apply_fix to fix up instructions that need
7736 a fix-up described above but does not involve any linker-time relocation. */
7739 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7743 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7744 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7745 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7749 /* Now the instruction is about to be fixed-up, so the operand that
7750 was previously marked as 'ignored' needs to be unmarked in order
7751 to get the encoding done properly. */
7752 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7753 new_inst
->operands
[idx
].skip
= 0;
7756 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7760 case AARCH64_OPND_EXCEPTION
:
7761 case AARCH64_OPND_UNDEFINED
:
7762 if (unsigned_overflow (value
, 16))
7763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7764 _("immediate out of range"));
7765 insn
= get_aarch64_insn (buf
);
7766 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
7767 put_aarch64_insn (buf
, insn
);
7770 case AARCH64_OPND_AIMM
:
7771 /* ADD or SUB with immediate.
7772 NOTE this assumes we come here with a add/sub shifted reg encoding
7773 3 322|2222|2 2 2 21111 111111
7774 1 098|7654|3 2 1 09876 543210 98765 43210
7775 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7776 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7777 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7778 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7780 3 322|2222|2 2 221111111111
7781 1 098|7654|3 2 109876543210 98765 43210
7782 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7783 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7784 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7785 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7786 Fields sf Rn Rd are already set. */
7787 insn
= get_aarch64_insn (buf
);
7791 insn
= reencode_addsub_switch_add_sub (insn
);
7795 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7796 && unsigned_overflow (value
, 12))
7798 /* Try to shift the value by 12 to make it fit. */
7799 if (((value
>> 12) << 12) == value
7800 && ! unsigned_overflow (value
, 12 + 12))
7803 insn
|= encode_addsub_imm_shift_amount (1);
7807 if (unsigned_overflow (value
, 12))
7808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7809 _("immediate out of range"));
7811 insn
|= encode_addsub_imm (value
);
7813 put_aarch64_insn (buf
, insn
);
7816 case AARCH64_OPND_SIMD_IMM
:
7817 case AARCH64_OPND_SIMD_IMM_SFT
:
7818 case AARCH64_OPND_LIMM
:
7819 /* Bit mask immediate. */
7820 gas_assert (new_inst
!= NULL
);
7821 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7822 new_inst
->operands
[idx
].imm
.value
= value
;
7823 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7824 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7825 put_aarch64_insn (buf
, new_inst
->value
);
7827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7828 _("invalid immediate"));
7831 case AARCH64_OPND_HALF
:
7832 /* 16-bit unsigned immediate. */
7833 if (unsigned_overflow (value
, 16))
7834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7835 _("immediate out of range"));
7836 insn
= get_aarch64_insn (buf
);
7837 insn
|= encode_movw_imm (value
& 0xffff);
7838 put_aarch64_insn (buf
, insn
);
7841 case AARCH64_OPND_IMM_MOV
:
7842 /* Operand for a generic move immediate instruction, which is
7843 an alias instruction that generates a single MOVZ, MOVN or ORR
7844 instruction to loads a 32-bit/64-bit immediate value into general
7845 register. An assembler error shall result if the immediate cannot be
7846 created by a single one of these instructions. If there is a choice,
7847 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7848 and MOVZ or MOVN to ORR. */
7849 gas_assert (new_inst
!= NULL
);
7850 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7853 case AARCH64_OPND_ADDR_SIMM7
:
7854 case AARCH64_OPND_ADDR_SIMM9
:
7855 case AARCH64_OPND_ADDR_SIMM9_2
:
7856 case AARCH64_OPND_ADDR_SIMM10
:
7857 case AARCH64_OPND_ADDR_UIMM12
:
7858 case AARCH64_OPND_ADDR_SIMM11
:
7859 case AARCH64_OPND_ADDR_SIMM13
:
7860 /* Immediate offset in an address. */
7861 insn
= get_aarch64_insn (buf
);
7863 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7864 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7865 || new_inst
->opcode
->operands
[2] == opnd
);
7867 /* Get the index of the address operand. */
7868 if (new_inst
->opcode
->operands
[1] == opnd
)
7869 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7872 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7875 /* Update the resolved offset value. */
7876 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7878 /* Encode/fix-up. */
7879 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7880 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7882 put_aarch64_insn (buf
, new_inst
->value
);
7885 else if (new_inst
->opcode
->iclass
== ldst_pos
7886 && try_to_encode_as_unscaled_ldst (new_inst
))
7888 put_aarch64_insn (buf
, new_inst
->value
);
7892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7893 _("immediate offset out of range"));
7898 as_fatal (_("unhandled operand code %d"), opnd
);
7902 /* Apply a fixup (fixP) to segment data, once it has been determined
7903 by our caller that we have all the info we need to fix it up.
7905 Parameter valP is the pointer to the value of the bits. */
7908 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7910 offsetT value
= *valP
;
7912 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7914 unsigned flags
= fixP
->fx_addnumber
;
7916 DEBUG_TRACE ("\n\n");
7917 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7918 DEBUG_TRACE ("Enter md_apply_fix");
7920 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7922 /* Note whether this will delete the relocation. */
7924 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7927 /* Process the relocations. */
7928 switch (fixP
->fx_r_type
)
7930 case BFD_RELOC_NONE
:
7931 /* This will need to go in the object file. */
7936 case BFD_RELOC_8_PCREL
:
7937 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7938 md_number_to_chars (buf
, value
, 1);
7942 case BFD_RELOC_16_PCREL
:
7943 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7944 md_number_to_chars (buf
, value
, 2);
7948 case BFD_RELOC_32_PCREL
:
7949 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7950 md_number_to_chars (buf
, value
, 4);
7954 case BFD_RELOC_64_PCREL
:
7955 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7956 md_number_to_chars (buf
, value
, 8);
7959 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7960 /* We claim that these fixups have been processed here, even if
7961 in fact we generate an error because we do not have a reloc
7962 for them, so tc_gen_reloc() will reject them. */
7964 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7967 _("undefined symbol %s used as an immediate value"),
7968 S_GET_NAME (fixP
->fx_addsy
));
7969 goto apply_fix_return
;
7971 fix_insn (fixP
, flags
, value
);
7974 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7975 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7979 _("pc-relative load offset not word aligned"));
7980 if (signed_overflow (value
, 21))
7981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7982 _("pc-relative load offset out of range"));
7983 insn
= get_aarch64_insn (buf
);
7984 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7985 put_aarch64_insn (buf
, insn
);
7989 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7990 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7992 if (signed_overflow (value
, 21))
7993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7994 _("pc-relative address offset out of range"));
7995 insn
= get_aarch64_insn (buf
);
7996 insn
|= encode_adr_imm (value
);
7997 put_aarch64_insn (buf
, insn
);
8001 case BFD_RELOC_AARCH64_BRANCH19
:
8002 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8006 _("conditional branch target not word aligned"));
8007 if (signed_overflow (value
, 21))
8008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8009 _("conditional branch out of range"));
8010 insn
= get_aarch64_insn (buf
);
8011 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8012 put_aarch64_insn (buf
, insn
);
8016 case BFD_RELOC_AARCH64_TSTBR14
:
8017 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8021 _("conditional branch target not word aligned"));
8022 if (signed_overflow (value
, 16))
8023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8024 _("conditional branch out of range"));
8025 insn
= get_aarch64_insn (buf
);
8026 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8027 put_aarch64_insn (buf
, insn
);
8031 case BFD_RELOC_AARCH64_CALL26
:
8032 case BFD_RELOC_AARCH64_JUMP26
:
8033 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8037 _("branch target not word aligned"));
8038 if (signed_overflow (value
, 28))
8039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8040 _("branch out of range"));
8041 insn
= get_aarch64_insn (buf
);
8042 insn
|= encode_branch_ofs_26 (value
>> 2);
8043 put_aarch64_insn (buf
, insn
);
8047 case BFD_RELOC_AARCH64_MOVW_G0
:
8048 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8049 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8050 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8051 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8052 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8055 case BFD_RELOC_AARCH64_MOVW_G1
:
8056 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8057 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8058 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8059 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8060 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8063 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8065 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8066 /* Should always be exported to object file, see
8067 aarch64_force_relocation(). */
8068 gas_assert (!fixP
->fx_done
);
8069 gas_assert (seg
->use_rela_p
);
8071 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8073 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8074 /* Should always be exported to object file, see
8075 aarch64_force_relocation(). */
8076 gas_assert (!fixP
->fx_done
);
8077 gas_assert (seg
->use_rela_p
);
8079 case BFD_RELOC_AARCH64_MOVW_G2
:
8080 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8081 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8082 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8083 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8086 case BFD_RELOC_AARCH64_MOVW_G3
:
8087 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8090 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8092 insn
= get_aarch64_insn (buf
);
8096 /* REL signed addend must fit in 16 bits */
8097 if (signed_overflow (value
, 16))
8098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8099 _("offset out of range"));
8103 /* Check for overflow and scale. */
8104 switch (fixP
->fx_r_type
)
8106 case BFD_RELOC_AARCH64_MOVW_G0
:
8107 case BFD_RELOC_AARCH64_MOVW_G1
:
8108 case BFD_RELOC_AARCH64_MOVW_G2
:
8109 case BFD_RELOC_AARCH64_MOVW_G3
:
8110 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8111 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8112 if (unsigned_overflow (value
, scale
+ 16))
8113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8114 _("unsigned value out of range"));
8116 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8117 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8118 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8119 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8120 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8121 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8122 /* NOTE: We can only come here with movz or movn. */
8123 if (signed_overflow (value
, scale
+ 16))
8124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8125 _("signed value out of range"));
8128 /* Force use of MOVN. */
8130 insn
= reencode_movzn_to_movn (insn
);
8134 /* Force use of MOVZ. */
8135 insn
= reencode_movzn_to_movz (insn
);
8139 /* Unchecked relocations. */
8145 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8146 insn
|= encode_movw_imm (value
& 0xffff);
8148 put_aarch64_insn (buf
, insn
);
8152 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8153 fixP
->fx_r_type
= (ilp32_p
8154 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8155 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8156 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8157 /* Should always be exported to object file, see
8158 aarch64_force_relocation(). */
8159 gas_assert (!fixP
->fx_done
);
8160 gas_assert (seg
->use_rela_p
);
8163 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8164 fixP
->fx_r_type
= (ilp32_p
8165 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8166 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8167 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8168 /* Should always be exported to object file, see
8169 aarch64_force_relocation(). */
8170 gas_assert (!fixP
->fx_done
);
8171 gas_assert (seg
->use_rela_p
);
8174 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8175 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8176 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8177 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8178 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8179 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8180 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8181 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8182 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8183 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8184 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8185 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8186 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8187 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8188 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8189 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8190 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8191 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8192 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8193 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8194 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8195 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8196 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8197 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8198 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8199 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8200 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8201 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8202 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8203 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8204 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8205 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8206 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8207 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8208 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8209 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8210 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8211 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8212 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8213 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8214 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8215 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8216 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8217 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8218 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8219 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8220 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8221 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8222 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8223 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8224 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8225 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8226 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8227 /* Should always be exported to object file, see
8228 aarch64_force_relocation(). */
8229 gas_assert (!fixP
->fx_done
);
8230 gas_assert (seg
->use_rela_p
);
8233 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8234 /* Should always be exported to object file, see
8235 aarch64_force_relocation(). */
8236 fixP
->fx_r_type
= (ilp32_p
8237 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8238 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8239 gas_assert (!fixP
->fx_done
);
8240 gas_assert (seg
->use_rela_p
);
8243 case BFD_RELOC_AARCH64_ADD_LO12
:
8244 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8245 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8246 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8247 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8248 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8249 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8250 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8251 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8252 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8253 case BFD_RELOC_AARCH64_LDST128_LO12
:
8254 case BFD_RELOC_AARCH64_LDST16_LO12
:
8255 case BFD_RELOC_AARCH64_LDST32_LO12
:
8256 case BFD_RELOC_AARCH64_LDST64_LO12
:
8257 case BFD_RELOC_AARCH64_LDST8_LO12
:
8258 /* Should always be exported to object file, see
8259 aarch64_force_relocation(). */
8260 gas_assert (!fixP
->fx_done
);
8261 gas_assert (seg
->use_rela_p
);
8264 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8265 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8266 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8269 case BFD_RELOC_UNUSED
:
8270 /* An error will already have been reported. */
8274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8275 _("unexpected %s fixup"),
8276 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8281 /* Free the allocated the struct aarch64_inst.
8282 N.B. currently there are very limited number of fix-up types actually use
8283 this field, so the impact on the performance should be minimal . */
8284 free (fixP
->tc_fix_data
.inst
);
8289 /* Translate internal representation of relocation info to BFD target
8293 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8296 bfd_reloc_code_real_type code
;
8298 reloc
= XNEW (arelent
);
8300 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8301 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8302 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8306 if (section
->use_rela_p
)
8307 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8309 fixp
->fx_offset
= reloc
->address
;
8311 reloc
->addend
= fixp
->fx_offset
;
8313 code
= fixp
->fx_r_type
;
8318 code
= BFD_RELOC_16_PCREL
;
8323 code
= BFD_RELOC_32_PCREL
;
8328 code
= BFD_RELOC_64_PCREL
;
8335 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8336 if (reloc
->howto
== NULL
)
8338 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8340 ("cannot represent %s relocation in this object file format"),
8341 bfd_get_reloc_code_name (code
));
8348 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8351 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8353 bfd_reloc_code_real_type type
;
8357 FIXME: @@ Should look at CPU word size. */
8364 type
= BFD_RELOC_16
;
8367 type
= BFD_RELOC_32
;
8370 type
= BFD_RELOC_64
;
8373 as_bad (_("cannot do %u-byte relocation"), size
);
8374 type
= BFD_RELOC_UNUSED
;
8378 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8382 aarch64_force_relocation (struct fix
*fixp
)
8384 switch (fixp
->fx_r_type
)
8386 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8387 /* Perform these "immediate" internal relocations
8388 even if the symbol is extern or weak. */
8391 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8392 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8393 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8394 /* Pseudo relocs that need to be fixed up according to
8398 case BFD_RELOC_AARCH64_ADD_LO12
:
8399 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8400 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8401 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8402 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8403 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8404 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8405 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8406 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8407 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8408 case BFD_RELOC_AARCH64_LDST128_LO12
:
8409 case BFD_RELOC_AARCH64_LDST16_LO12
:
8410 case BFD_RELOC_AARCH64_LDST32_LO12
:
8411 case BFD_RELOC_AARCH64_LDST64_LO12
:
8412 case BFD_RELOC_AARCH64_LDST8_LO12
:
8413 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8414 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8415 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8416 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8417 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8418 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8419 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8420 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8421 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8422 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8423 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8424 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8425 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8426 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8427 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8428 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8429 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8430 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8431 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8432 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8433 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8434 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8435 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8436 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8437 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8438 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8439 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8440 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8441 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8442 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8443 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8444 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8445 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8446 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8447 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8448 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8449 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8450 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8451 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8452 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8453 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8454 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8455 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8456 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8457 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8458 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8459 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8460 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8461 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8462 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8463 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8464 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8465 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8466 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8467 /* Always leave these relocations for the linker. */
8474 return generic_force_reloc (fixp
);
8479 /* Implement md_after_parse_args. This is the earliest time we need to decide
8480 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8483 aarch64_after_parse_args (void)
8485 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8488 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8489 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8490 aarch64_abi
= AARCH64_ABI_ILP32
;
8492 aarch64_abi
= AARCH64_ABI_LP64
;
8496 elf64_aarch64_target_format (void)
8499 /* FIXME: What to do for ilp32_p ? */
8500 if (target_big_endian
)
8501 return "elf64-bigaarch64-cloudabi";
8503 return "elf64-littleaarch64-cloudabi";
8505 if (target_big_endian
)
8506 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8508 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8513 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8515 elf_frob_symbol (symp
, puntp
);
8519 /* MD interface: Finalization. */
8521 /* A good place to do this, although this was probably not intended
8522 for this kind of use. We need to dump the literal pool before
8523 references are made to a null symbol pointer. */
8526 aarch64_cleanup (void)
8530 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8532 /* Put it at the end of the relevant section. */
8533 subseg_set (pool
->section
, pool
->sub_section
);
8539 /* Remove any excess mapping symbols generated for alignment frags in
8540 SEC. We may have created a mapping symbol before a zero byte
8541 alignment; remove it if there's a mapping symbol after the
8544 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8545 void *dummy ATTRIBUTE_UNUSED
)
8547 segment_info_type
*seginfo
= seg_info (sec
);
8550 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8553 for (fragp
= seginfo
->frchainP
->frch_root
;
8554 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8556 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8557 fragS
*next
= fragp
->fr_next
;
8559 /* Variable-sized frags have been converted to fixed size by
8560 this point. But if this was variable-sized to start with,
8561 there will be a fixed-size frag after it. So don't handle
8563 if (sym
== NULL
|| next
== NULL
)
8566 if (S_GET_VALUE (sym
) < next
->fr_address
)
8567 /* Not at the end of this frag. */
8569 know (S_GET_VALUE (sym
) == next
->fr_address
);
8573 if (next
->tc_frag_data
.first_map
!= NULL
)
8575 /* Next frag starts with a mapping symbol. Discard this
8577 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8581 if (next
->fr_next
== NULL
)
8583 /* This mapping symbol is at the end of the section. Discard
8585 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8586 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8590 /* As long as we have empty frags without any mapping symbols,
8592 /* If the next frag is non-empty and does not start with a
8593 mapping symbol, then this mapping symbol is required. */
8594 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8597 next
= next
->fr_next
;
8599 while (next
!= NULL
);
8604 /* Adjust the symbol table. */
8607 aarch64_adjust_symtab (void)
8610 /* Remove any overlapping mapping symbols generated by alignment frags. */
8611 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8612 /* Now do generic ELF adjustments. */
8613 elf_adjust_symtab ();
8618 checked_hash_insert (htab_t table
, const char *key
, void *value
)
8620 str_hash_insert (table
, key
, value
, 0);
8624 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
8626 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
8627 checked_hash_insert (table
, key
, value
);
8631 fill_instruction_hash_table (void)
8633 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8635 while (opcode
->name
!= NULL
)
8637 templates
*templ
, *new_templ
;
8638 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
8640 new_templ
= XNEW (templates
);
8641 new_templ
->opcode
= opcode
;
8642 new_templ
->next
= NULL
;
8645 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8648 new_templ
->next
= templ
->next
;
8649 templ
->next
= new_templ
;
8656 convert_to_upper (char *dst
, const char *src
, size_t num
)
8659 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8660 *dst
= TOUPPER (*src
);
8664 /* Assume STR point to a lower-case string, allocate, convert and return
8665 the corresponding upper-case string. */
8666 static inline const char*
8667 get_upper_str (const char *str
)
8670 size_t len
= strlen (str
);
8671 ret
= XNEWVEC (char, len
+ 1);
8672 convert_to_upper (ret
, str
, len
);
8676 /* MD interface: Initialization. */
8684 aarch64_ops_hsh
= str_htab_create ();
8685 aarch64_cond_hsh
= str_htab_create ();
8686 aarch64_shift_hsh
= str_htab_create ();
8687 aarch64_sys_regs_hsh
= str_htab_create ();
8688 aarch64_pstatefield_hsh
= str_htab_create ();
8689 aarch64_sys_regs_ic_hsh
= str_htab_create ();
8690 aarch64_sys_regs_dc_hsh
= str_htab_create ();
8691 aarch64_sys_regs_at_hsh
= str_htab_create ();
8692 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
8693 aarch64_sys_regs_sr_hsh
= str_htab_create ();
8694 aarch64_reg_hsh
= str_htab_create ();
8695 aarch64_barrier_opt_hsh
= str_htab_create ();
8696 aarch64_nzcv_hsh
= str_htab_create ();
8697 aarch64_pldop_hsh
= str_htab_create ();
8698 aarch64_hint_opt_hsh
= str_htab_create ();
8700 fill_instruction_hash_table ();
8702 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8703 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8704 (void *) (aarch64_sys_regs
+ i
));
8706 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8707 sysreg_hash_insert (aarch64_pstatefield_hsh
,
8708 aarch64_pstatefields
[i
].name
,
8709 (void *) (aarch64_pstatefields
+ i
));
8711 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8712 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
8713 aarch64_sys_regs_ic
[i
].name
,
8714 (void *) (aarch64_sys_regs_ic
+ i
));
8716 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8717 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
8718 aarch64_sys_regs_dc
[i
].name
,
8719 (void *) (aarch64_sys_regs_dc
+ i
));
8721 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8722 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
8723 aarch64_sys_regs_at
[i
].name
,
8724 (void *) (aarch64_sys_regs_at
+ i
));
8726 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8727 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8728 aarch64_sys_regs_tlbi
[i
].name
,
8729 (void *) (aarch64_sys_regs_tlbi
+ i
));
8731 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8732 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
8733 aarch64_sys_regs_sr
[i
].name
,
8734 (void *) (aarch64_sys_regs_sr
+ i
));
8736 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8737 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8738 (void *) (reg_names
+ i
));
8740 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8741 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8742 (void *) (nzcv_names
+ i
));
8744 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8746 const char *name
= aarch64_operand_modifiers
[i
].name
;
8747 checked_hash_insert (aarch64_shift_hsh
, name
,
8748 (void *) (aarch64_operand_modifiers
+ i
));
8749 /* Also hash the name in the upper case. */
8750 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8751 (void *) (aarch64_operand_modifiers
+ i
));
8754 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8757 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8758 the same condition code. */
8759 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8761 const char *name
= aarch64_conds
[i
].names
[j
];
8764 checked_hash_insert (aarch64_cond_hsh
, name
,
8765 (void *) (aarch64_conds
+ i
));
8766 /* Also hash the name in the upper case. */
8767 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8768 (void *) (aarch64_conds
+ i
));
8772 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8774 const char *name
= aarch64_barrier_options
[i
].name
;
8775 /* Skip xx00 - the unallocated values of option. */
8778 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8779 (void *) (aarch64_barrier_options
+ i
));
8780 /* Also hash the name in the upper case. */
8781 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8782 (void *) (aarch64_barrier_options
+ i
));
8785 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8787 const char* name
= aarch64_prfops
[i
].name
;
8788 /* Skip the unallocated hint encodings. */
8791 checked_hash_insert (aarch64_pldop_hsh
, name
,
8792 (void *) (aarch64_prfops
+ i
));
8793 /* Also hash the name in the upper case. */
8794 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8795 (void *) (aarch64_prfops
+ i
));
8798 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8800 const char* name
= aarch64_hint_options
[i
].name
;
8801 const char* upper_name
= get_upper_str(name
);
8803 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8804 (void *) (aarch64_hint_options
+ i
));
8806 /* Also hash the name in the upper case if not the same. */
8807 if (strcmp (name
, upper_name
) != 0)
8808 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
8809 (void *) (aarch64_hint_options
+ i
));
8812 /* Set the cpu variant based on the command-line options. */
8814 mcpu_cpu_opt
= march_cpu_opt
;
8817 mcpu_cpu_opt
= &cpu_default
;
8819 cpu_variant
= *mcpu_cpu_opt
;
8821 /* Record the CPU type. */
8822 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8824 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8827 /* Command line processing. */
8829 const char *md_shortopts
= "m:";
8831 #ifdef AARCH64_BI_ENDIAN
8832 #define OPTION_EB (OPTION_MD_BASE + 0)
8833 #define OPTION_EL (OPTION_MD_BASE + 1)
8835 #if TARGET_BYTES_BIG_ENDIAN
8836 #define OPTION_EB (OPTION_MD_BASE + 0)
8838 #define OPTION_EL (OPTION_MD_BASE + 1)
8842 struct option md_longopts
[] = {
8844 {"EB", no_argument
, NULL
, OPTION_EB
},
8847 {"EL", no_argument
, NULL
, OPTION_EL
},
8849 {NULL
, no_argument
, NULL
, 0}
8852 size_t md_longopts_size
= sizeof (md_longopts
);
8854 struct aarch64_option_table
8856 const char *option
; /* Option name to match. */
8857 const char *help
; /* Help information. */
8858 int *var
; /* Variable to change. */
8859 int value
; /* What to change it to. */
8860 char *deprecated
; /* If non-null, print this message. */
8863 static struct aarch64_option_table aarch64_opts
[] = {
8864 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8865 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8867 #ifdef DEBUG_AARCH64
8868 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8869 #endif /* DEBUG_AARCH64 */
8870 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8872 {"mno-verbose-error", N_("do not output verbose error messages"),
8873 &verbose_error_p
, 0, NULL
},
8874 {NULL
, NULL
, NULL
, 0, NULL
}
8877 struct aarch64_cpu_option_table
8880 const aarch64_feature_set value
;
8881 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8883 const char *canonical_name
;
8886 /* This list should, at a minimum, contain all the cpu names
8887 recognized by GCC. */
8888 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8889 {"all", AARCH64_ANY
, NULL
},
8890 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8891 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8892 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8893 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8894 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8895 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8896 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8897 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8898 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8899 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8900 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8901 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8902 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8903 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8905 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8906 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8908 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8909 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8911 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8912 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8913 | AARCH64_FEATURE_DOTPROD
8914 | AARCH64_FEATURE_SSBS
),
8916 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8917 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8918 | AARCH64_FEATURE_DOTPROD
8919 | AARCH64_FEATURE_SSBS
),
8921 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8922 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8923 | AARCH64_FEATURE_DOTPROD
8924 | AARCH64_FEATURE_SSBS
),
8926 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8927 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8928 | AARCH64_FEATURE_DOTPROD
8929 | AARCH64_FEATURE_SSBS
),
8931 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8933 | AARCH64_FEATURE_RCPC
8934 | AARCH64_FEATURE_DOTPROD
8935 | AARCH64_FEATURE_SSBS
8936 | AARCH64_FEATURE_PROFILE
),
8938 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8940 | AARCH64_FEATURE_RCPC
8941 | AARCH64_FEATURE_DOTPROD
8942 | AARCH64_FEATURE_SSBS
8943 | AARCH64_FEATURE_PROFILE
),
8945 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8946 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8947 | AARCH64_FEATURE_DOTPROD
8948 | AARCH64_FEATURE_PROFILE
),
8950 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8951 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8952 "Samsung Exynos M1"},
8953 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8954 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8955 | AARCH64_FEATURE_RDMA
),
8957 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8958 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8959 | AARCH64_FEATURE_DOTPROD
8960 | AARCH64_FEATURE_SSBS
),
8962 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8963 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8964 | AARCH64_FEATURE_DOTPROD
8965 | AARCH64_FEATURE_PROFILE
),
8967 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
8968 AARCH64_FEATURE_BFLOAT16
8969 | AARCH64_FEATURE_I8MM
8970 | AARCH64_FEATURE_F16
8971 | AARCH64_FEATURE_SVE
8972 | AARCH64_FEATURE_SVE2
8973 | AARCH64_FEATURE_SVE2_BITPERM
8974 | AARCH64_FEATURE_MEMTAG
8975 | AARCH64_FEATURE_RNG
),
8977 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8978 AARCH64_FEATURE_PROFILE
8979 | AARCH64_FEATURE_CVADP
8980 | AARCH64_FEATURE_SVE
8981 | AARCH64_FEATURE_SSBS
8982 | AARCH64_FEATURE_RNG
8983 | AARCH64_FEATURE_F16
8984 | AARCH64_FEATURE_BFLOAT16
8985 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
8986 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8987 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8988 | AARCH64_FEATURE_RDMA
),
8989 "Qualcomm QDF24XX"},
8990 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8991 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8992 "Qualcomm Saphira"},
8993 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8994 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8996 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8997 AARCH64_FEATURE_CRYPTO
),
8999 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9000 in earlier releases and is superseded by 'xgene1' in all
9002 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9003 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9004 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9005 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9006 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9007 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9009 | AARCH64_FEATURE_RCPC
9010 | AARCH64_FEATURE_DOTPROD
9011 | AARCH64_FEATURE_SSBS
9012 | AARCH64_FEATURE_PROFILE
),
9014 {"generic", AARCH64_ARCH_V8
, NULL
},
9016 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9019 struct aarch64_arch_option_table
9022 const aarch64_feature_set value
;
9025 /* This list should, at a minimum, contain all the architecture names
9026 recognized by GCC. */
9027 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9028 {"all", AARCH64_ANY
},
9029 {"armv8-a", AARCH64_ARCH_V8
},
9030 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9031 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9032 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9033 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9034 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9035 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9036 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9037 {"armv8-r", AARCH64_ARCH_V8_R
},
9038 {NULL
, AARCH64_ARCH_NONE
}
9041 /* ISA extensions. */
9042 struct aarch64_option_cpu_value_table
9045 const aarch64_feature_set value
;
9046 const aarch64_feature_set require
; /* Feature dependencies. */
9049 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9050 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9052 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9053 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9054 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9056 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9058 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9059 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9060 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9062 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9064 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9066 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9067 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9068 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9069 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9070 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9071 AARCH64_FEATURE (AARCH64_FEATURE_FP
9072 | AARCH64_FEATURE_F16
, 0)},
9073 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9075 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9076 AARCH64_FEATURE (AARCH64_FEATURE_F16
9077 | AARCH64_FEATURE_SIMD
9078 | AARCH64_FEATURE_COMPNUM
, 0)},
9079 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9081 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9082 AARCH64_FEATURE (AARCH64_FEATURE_F16
9083 | AARCH64_FEATURE_SIMD
, 0)},
9084 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9086 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9088 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9090 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9092 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9094 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9096 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9098 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9099 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9100 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9102 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9104 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9106 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9107 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9108 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9109 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9110 | AARCH64_FEATURE_SM4
, 0)},
9111 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9112 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9113 | AARCH64_FEATURE_AES
, 0)},
9114 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9115 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9116 | AARCH64_FEATURE_SHA3
, 0)},
9117 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9118 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9119 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9121 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9123 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9124 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9125 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9126 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9127 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9130 struct aarch64_long_option_table
9132 const char *option
; /* Substring to match. */
9133 const char *help
; /* Help information. */
9134 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9135 char *deprecated
; /* If non-null, print this message. */
9138 /* Transitive closure of features depending on set. */
9139 static aarch64_feature_set
9140 aarch64_feature_disable_set (aarch64_feature_set set
)
9142 const struct aarch64_option_cpu_value_table
*opt
;
9143 aarch64_feature_set prev
= 0;
9145 while (prev
!= set
) {
9147 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9148 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9149 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9154 /* Transitive closure of dependencies of set. */
9155 static aarch64_feature_set
9156 aarch64_feature_enable_set (aarch64_feature_set set
)
9158 const struct aarch64_option_cpu_value_table
*opt
;
9159 aarch64_feature_set prev
= 0;
9161 while (prev
!= set
) {
9163 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9164 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9165 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9171 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9172 bfd_boolean ext_only
)
9174 /* We insist on extensions being added before being removed. We achieve
9175 this by using the ADDING_VALUE variable to indicate whether we are
9176 adding an extension (1) or removing it (0) and only allowing it to
9177 change in the order -1 -> 1 -> 0. */
9178 int adding_value
= -1;
9179 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9181 /* Copy the feature set, so that we can modify it. */
9185 while (str
!= NULL
&& *str
!= 0)
9187 const struct aarch64_option_cpu_value_table
*opt
;
9188 const char *ext
= NULL
;
9195 as_bad (_("invalid architectural extension"));
9199 ext
= strchr (++str
, '+');
9205 optlen
= strlen (str
);
9207 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9209 if (adding_value
!= 0)
9214 else if (optlen
> 0)
9216 if (adding_value
== -1)
9218 else if (adding_value
!= 1)
9220 as_bad (_("must specify extensions to add before specifying "
9221 "those to remove"));
9228 as_bad (_("missing architectural extension"));
9232 gas_assert (adding_value
!= -1);
9234 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9235 if (strncmp (opt
->name
, str
, optlen
) == 0)
9237 aarch64_feature_set set
;
9239 /* Add or remove the extension. */
9242 set
= aarch64_feature_enable_set (opt
->value
);
9243 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9247 set
= aarch64_feature_disable_set (opt
->value
);
9248 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9253 if (opt
->name
== NULL
)
9255 as_bad (_("unknown architectural extension `%s'"), str
);
9266 aarch64_parse_cpu (const char *str
)
9268 const struct aarch64_cpu_option_table
*opt
;
9269 const char *ext
= strchr (str
, '+');
9275 optlen
= strlen (str
);
9279 as_bad (_("missing cpu name `%s'"), str
);
9283 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9284 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9286 mcpu_cpu_opt
= &opt
->value
;
9288 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9293 as_bad (_("unknown cpu `%s'"), str
);
9298 aarch64_parse_arch (const char *str
)
9300 const struct aarch64_arch_option_table
*opt
;
9301 const char *ext
= strchr (str
, '+');
9307 optlen
= strlen (str
);
9311 as_bad (_("missing architecture name `%s'"), str
);
9315 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9316 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9318 march_cpu_opt
= &opt
->value
;
9320 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9325 as_bad (_("unknown architecture `%s'\n"), str
);
9330 struct aarch64_option_abi_value_table
9333 enum aarch64_abi_type value
;
9336 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9337 {"ilp32", AARCH64_ABI_ILP32
},
9338 {"lp64", AARCH64_ABI_LP64
},
9342 aarch64_parse_abi (const char *str
)
9348 as_bad (_("missing abi name `%s'"), str
);
9352 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9353 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9355 aarch64_abi
= aarch64_abis
[i
].value
;
9359 as_bad (_("unknown abi `%s'\n"), str
);
9363 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9365 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9366 aarch64_parse_abi
, NULL
},
9367 #endif /* OBJ_ELF */
9368 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9369 aarch64_parse_cpu
, NULL
},
9370 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9371 aarch64_parse_arch
, NULL
},
9372 {NULL
, NULL
, 0, NULL
}
9376 md_parse_option (int c
, const char *arg
)
9378 struct aarch64_option_table
*opt
;
9379 struct aarch64_long_option_table
*lopt
;
9385 target_big_endian
= 1;
9391 target_big_endian
= 0;
9396 /* Listing option. Just ignore these, we don't support additional
9401 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9403 if (c
== opt
->option
[0]
9404 && ((arg
== NULL
&& opt
->option
[1] == 0)
9405 || streq (arg
, opt
->option
+ 1)))
9407 /* If the option is deprecated, tell the user. */
9408 if (opt
->deprecated
!= NULL
)
9409 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9410 arg
? arg
: "", _(opt
->deprecated
));
9412 if (opt
->var
!= NULL
)
9413 *opt
->var
= opt
->value
;
9419 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9421 /* These options are expected to have an argument. */
9422 if (c
== lopt
->option
[0]
9424 && strncmp (arg
, lopt
->option
+ 1,
9425 strlen (lopt
->option
+ 1)) == 0)
9427 /* If the option is deprecated, tell the user. */
9428 if (lopt
->deprecated
!= NULL
)
9429 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9430 _(lopt
->deprecated
));
9432 /* Call the sup-option parser. */
9433 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9444 md_show_usage (FILE * fp
)
9446 struct aarch64_option_table
*opt
;
9447 struct aarch64_long_option_table
*lopt
;
9449 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9451 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9452 if (opt
->help
!= NULL
)
9453 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9455 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9456 if (lopt
->help
!= NULL
)
9457 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9461 -EB assemble code for a big-endian cpu\n"));
9466 -EL assemble code for a little-endian cpu\n"));
9470 /* Parse a .cpu directive. */
9473 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9475 const struct aarch64_cpu_option_table
*opt
;
9481 name
= input_line_pointer
;
9482 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9483 input_line_pointer
++;
9484 saved_char
= *input_line_pointer
;
9485 *input_line_pointer
= 0;
9487 ext
= strchr (name
, '+');
9490 optlen
= ext
- name
;
9492 optlen
= strlen (name
);
9494 /* Skip the first "all" entry. */
9495 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9496 if (strlen (opt
->name
) == optlen
9497 && strncmp (name
, opt
->name
, optlen
) == 0)
9499 mcpu_cpu_opt
= &opt
->value
;
9501 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9504 cpu_variant
= *mcpu_cpu_opt
;
9506 *input_line_pointer
= saved_char
;
9507 demand_empty_rest_of_line ();
9510 as_bad (_("unknown cpu `%s'"), name
);
9511 *input_line_pointer
= saved_char
;
9512 ignore_rest_of_line ();
9516 /* Parse a .arch directive. */
9519 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9521 const struct aarch64_arch_option_table
*opt
;
9527 name
= input_line_pointer
;
9528 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9529 input_line_pointer
++;
9530 saved_char
= *input_line_pointer
;
9531 *input_line_pointer
= 0;
9533 ext
= strchr (name
, '+');
9536 optlen
= ext
- name
;
9538 optlen
= strlen (name
);
9540 /* Skip the first "all" entry. */
9541 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9542 if (strlen (opt
->name
) == optlen
9543 && strncmp (name
, opt
->name
, optlen
) == 0)
9545 mcpu_cpu_opt
= &opt
->value
;
9547 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9550 cpu_variant
= *mcpu_cpu_opt
;
9552 *input_line_pointer
= saved_char
;
9553 demand_empty_rest_of_line ();
9557 as_bad (_("unknown architecture `%s'\n"), name
);
9558 *input_line_pointer
= saved_char
;
9559 ignore_rest_of_line ();
9562 /* Parse a .arch_extension directive. */
9565 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9568 char *ext
= input_line_pointer
;;
9570 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9571 input_line_pointer
++;
9572 saved_char
= *input_line_pointer
;
9573 *input_line_pointer
= 0;
9575 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9578 cpu_variant
= *mcpu_cpu_opt
;
9580 *input_line_pointer
= saved_char
;
9581 demand_empty_rest_of_line ();
9584 /* Copy symbol information. */
9587 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9589 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9593 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9594 This is needed so AArch64 specific st_other values can be independently
9595 specified for an IFUNC resolver (that is called by the dynamic linker)
9596 and the symbol it resolves (aliased to the resolver). In particular,
9597 if a function symbol has special st_other value set via directives,
9598 then attaching an IFUNC resolver to that symbol should not override
9599 the st_other setting. Requiring the directive on the IFUNC resolver
9600 symbol would be unexpected and problematic in C code, where the two
9601 symbols appear as two independent function declarations. */
9604 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9606 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9607 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9610 if (destelf
->size
== NULL
)
9611 destelf
->size
= XNEW (expressionS
);
9612 *destelf
->size
= *srcelf
->size
;
9616 free (destelf
->size
);
9617 destelf
->size
= NULL
;
9619 S_SET_SIZE (dest
, S_GET_SIZE (src
));