1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
175 set_error_message (const char *error
)
177 inst
.parsing_error
.error
= error
;
180 static inline enum aarch64_operand_error_kind
181 get_error_kind (void)
183 return inst
.parsing_error
.kind
;
187 set_error_kind (enum aarch64_operand_error_kind kind
)
189 inst
.parsing_error
.kind
= kind
;
193 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
195 inst
.parsing_error
.kind
= kind
;
196 inst
.parsing_error
.error
= error
;
200 set_recoverable_error (const char *error
)
202 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
205 /* Use the DESC field of the corresponding aarch64_operand entry to compose
206 the error message. */
208 set_default_error (void)
210 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
214 set_syntax_error (const char *error
)
216 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
220 set_first_syntax_error (const char *error
)
223 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
227 set_fatal_syntax_error (const char *error
)
229 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
232 /* Number of littlenums required to hold an extended precision number. */
233 #define MAX_LITTLENUMS 6
235 /* Return value for certain parsers when the parsing fails; those parsers
236 return the information of the parsed result, e.g. register number, on
238 #define PARSE_FAIL -1
240 /* This is an invalid condition code that means no conditional field is
242 #define COND_ALWAYS 0x10
246 const char *template;
252 const char *template;
259 bfd_reloc_code_real_type reloc
;
262 /* Structure for a hash table entry for a register. */
266 unsigned char number
;
268 unsigned char builtin
;
271 /* Macros to define the register types and masks for the purpose
274 #undef AARCH64_REG_TYPES
275 #define AARCH64_REG_TYPES \
276 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
277 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
278 BASIC_REG_TYPE(SP_32) /* wsp */ \
279 BASIC_REG_TYPE(SP_64) /* sp */ \
280 BASIC_REG_TYPE(Z_32) /* wzr */ \
281 BASIC_REG_TYPE(Z_64) /* xzr */ \
282 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
283 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
284 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
285 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
286 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
287 BASIC_REG_TYPE(CN) /* c[0-7] */ \
288 BASIC_REG_TYPE(VN) /* v[0-31] */ \
289 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
290 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
291 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
292 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Typecheck: any [BHSDQ]P FP. */ \
296 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
297 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
298 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
299 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
301 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
302 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
303 /* Any integer register; used for error messages only. */ \
304 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
306 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
307 /* Pseudo type to mark the end of the enumerator sequence. */ \
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
312 #undef MULTI_REG_TYPE
313 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
315 /* Register type enumerators. */
318 /* A list of REG_TYPE_*. */
322 #undef BASIC_REG_TYPE
323 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
325 #define REG_TYPE(T) (1 << REG_TYPE_##T)
326 #undef MULTI_REG_TYPE
327 #define MULTI_REG_TYPE(T,V) V,
329 /* Values indexed by aarch64_reg_type to assist the type checking. */
330 static const unsigned reg_type_masks
[] =
335 #undef BASIC_REG_TYPE
337 #undef MULTI_REG_TYPE
338 #undef AARCH64_REG_TYPES
340 /* Diagnostics used when we don't get a register of the expected type.
341 Note: this has to synchronized with aarch64_reg_type definitions
344 get_reg_expected_msg (aarch64_reg_type reg_type
)
351 msg
= N_("integer 32-bit register expected");
354 msg
= N_("integer 64-bit register expected");
357 msg
= N_("integer register expected");
359 case REG_TYPE_R_Z_SP
:
360 msg
= N_("integer, zero or SP register expected");
363 msg
= N_("8-bit SIMD scalar register expected");
366 msg
= N_("16-bit SIMD scalar or floating-point half precision "
367 "register expected");
370 msg
= N_("32-bit SIMD scalar or floating-point single precision "
371 "register expected");
374 msg
= N_("64-bit SIMD scalar or floating-point double precision "
375 "register expected");
378 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
379 "register expected");
382 msg
= N_("C0 - C15 expected");
384 case REG_TYPE_R_Z_BHSDQ_V
:
385 msg
= N_("register expected");
387 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
388 msg
= N_("SIMD scalar or floating-point register expected");
390 case REG_TYPE_VN
: /* any V reg */
391 msg
= N_("vector register expected");
394 as_fatal (_("invalid register type %d"), reg_type
);
399 /* Some well known registers that we refer to directly elsewhere. */
402 /* Instructions take 4 bytes in the object file. */
405 /* Define some common error messages. */
406 #define BAD_SP _("SP not allowed here")
408 static struct hash_control
*aarch64_ops_hsh
;
409 static struct hash_control
*aarch64_cond_hsh
;
410 static struct hash_control
*aarch64_shift_hsh
;
411 static struct hash_control
*aarch64_sys_regs_hsh
;
412 static struct hash_control
*aarch64_pstatefield_hsh
;
413 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
414 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
415 static struct hash_control
*aarch64_sys_regs_at_hsh
;
416 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
417 static struct hash_control
*aarch64_reg_hsh
;
418 static struct hash_control
*aarch64_barrier_opt_hsh
;
419 static struct hash_control
*aarch64_nzcv_hsh
;
420 static struct hash_control
*aarch64_pldop_hsh
;
422 /* Stuff needed to resolve the label ambiguity
431 static symbolS
*last_label_seen
;
433 /* Literal pool structure. Held on a per-section
434 and per-sub-section basis. */
436 #define MAX_LITERAL_POOL_SIZE 1024
437 typedef struct literal_expression
440 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
441 LITTLENUM_TYPE
* bignum
;
442 } literal_expression
;
444 typedef struct literal_pool
446 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
447 unsigned int next_free_entry
;
453 struct literal_pool
*next
;
456 /* Pointer to a linked list of literal pools. */
457 static literal_pool
*list_of_pools
= NULL
;
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. */
463 const char comment_chars
[] = "";
465 /* This array holds the chars that only start a comment at the beginning of
466 a line. If the line seems to have the form '# 123 filename'
467 .line and .file directives will appear in the pre-processed output. */
468 /* Note that input_file.c hand checks for '#' at the beginning of the
469 first line of the input file. This is because the compiler outputs
470 #NO_APP at the beginning of its output. */
471 /* Also note that comments like this one will always work. */
472 const char line_comment_chars
[] = "#";
474 const char line_separator_chars
[] = ";";
476 /* Chars that can be used to separate mant
477 from exp in floating point numbers. */
478 const char EXP_CHARS
[] = "eE";
480 /* Chars that mean this number is a floating point constant. */
484 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
486 /* Prefix character that indicates the start of an immediate value. */
487 #define is_immediate_prefix(C) ((C) == '#')
489 /* Separator character handling. */
491 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
493 static inline bfd_boolean
494 skip_past_char (char **str
, char c
)
505 #define skip_past_comma(str) skip_past_char (str, ',')
507 /* Arithmetic expressions (possibly involving symbols). */
509 static bfd_boolean in_my_get_expression_p
= FALSE
;
511 /* Third argument to my_get_expression. */
512 #define GE_NO_PREFIX 0
513 #define GE_OPT_PREFIX 1
515 /* Return TRUE if the string pointed by *STR is successfully parsed
516 as an valid expression; *EP will be filled with the information of
517 such an expression. Otherwise return FALSE. */
520 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
525 int prefix_present_p
= 0;
532 if (is_immediate_prefix (**str
))
535 prefix_present_p
= 1;
542 memset (ep
, 0, sizeof (expressionS
));
544 save_in
= input_line_pointer
;
545 input_line_pointer
= *str
;
546 in_my_get_expression_p
= TRUE
;
547 seg
= expression (ep
);
548 in_my_get_expression_p
= FALSE
;
550 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
552 /* We found a bad expression in md_operand(). */
553 *str
= input_line_pointer
;
554 input_line_pointer
= save_in
;
555 if (prefix_present_p
&& ! error_p ())
556 set_fatal_syntax_error (_("bad expression"));
558 set_first_syntax_error (_("bad expression"));
563 if (seg
!= absolute_section
564 && seg
!= text_section
565 && seg
!= data_section
566 && seg
!= bss_section
&& seg
!= undefined_section
)
568 set_syntax_error (_("bad segment"));
569 *str
= input_line_pointer
;
570 input_line_pointer
= save_in
;
577 *str
= input_line_pointer
;
578 input_line_pointer
= save_in
;
582 /* Turn a string in input_line_pointer into a floating point constant
583 of type TYPE, and store the appropriate bytes in *LITP. The number
584 of LITTLENUMS emitted is stored in *SIZEP. An error message is
585 returned, or NULL on OK. */
588 md_atof (int type
, char *litP
, int *sizeP
)
590 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
593 /* We handle all bad expressions here, so that we can report the faulty
594 instruction in the error message. */
596 md_operand (expressionS
* exp
)
598 if (in_my_get_expression_p
)
599 exp
->X_op
= O_illegal
;
602 /* Immediate values. */
604 /* Errors may be set multiple times during parsing or bit encoding
605 (particularly in the Neon bits), but usually the earliest error which is set
606 will be the most meaningful. Avoid overwriting it with later (cascading)
607 errors by calling this function. */
610 first_error (const char *error
)
613 set_syntax_error (error
);
616 /* Similiar to first_error, but this function accepts formatted error
619 first_error_fmt (const char *format
, ...)
624 /* N.B. this single buffer will not cause error messages for different
625 instructions to pollute each other; this is because at the end of
626 processing of each assembly line, error message if any will be
627 collected by as_bad. */
628 static char buffer
[size
];
632 int ret ATTRIBUTE_UNUSED
;
633 va_start (args
, format
);
634 ret
= vsnprintf (buffer
, size
, format
, args
);
635 know (ret
<= size
- 1 && ret
>= 0);
637 set_syntax_error (buffer
);
641 /* Register parsing. */
643 /* Generic register parser which is called by other specialized
645 CCP points to what should be the beginning of a register name.
646 If it is indeed a valid register name, advance CCP over it and
647 return the reg_entry structure; otherwise return NULL.
648 It does not issue diagnostics. */
651 parse_reg (char **ccp
)
657 #ifdef REGISTER_PREFIX
658 if (*start
!= REGISTER_PREFIX
)
664 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
669 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
671 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
680 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
683 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
685 if (reg
->type
== type
)
690 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
691 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
692 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
693 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
694 case REG_TYPE_VN
: /* Vector register. */
695 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
696 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
697 == reg_type_masks
[reg
->type
]);
699 as_fatal ("unhandled type %d", type
);
704 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
705 Return the register number otherwise. *ISREG32 is set to one if the
706 register is 32-bit wide; *ISREGZERO is set to one if the register is
707 of type Z_32 or Z_64.
708 Note that this function does not issue any diagnostics. */
711 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
712 int *isreg32
, int *isregzero
)
715 const reg_entry
*reg
= parse_reg (&str
);
720 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
729 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
734 *isreg32
= reg
->type
== REG_TYPE_R_32
;
741 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
753 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
754 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
755 otherwise return FALSE.
757 Accept only one occurrence of:
758 8b 16b 4h 8h 2s 4s 1d 2d
761 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
765 unsigned element_size
;
766 enum neon_el_type type
;
776 width
= strtoul (ptr
, &ptr
, 10);
777 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
779 first_error_fmt (_("bad size %d in vector width specifier"), width
);
784 switch (TOLOWER (*ptr
))
812 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
814 first_error (_("missing element size"));
817 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
820 ("invalid element size %d and vector size combination %c"),
826 parsed_type
->type
= type
;
827 parsed_type
->width
= width
;
834 /* Parse a single type, e.g. ".8b", leading period included.
835 Only applicable to Vn registers.
837 Return TRUE on success; otherwise return FALSE. */
839 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
845 if (! parse_neon_type_for_operand (vectype
, &str
))
847 first_error (_("vector type expected"));
859 /* Parse a register of the type TYPE.
861 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
862 name or the parsed register is not of TYPE.
864 Otherwise return the register number, and optionally fill in the actual
865 type of the register in *RTYPE when multiple alternatives were given, and
866 return the register shape and element index information in *TYPEINFO.
868 IN_REG_LIST should be set with TRUE if the caller is parsing a register
872 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
873 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
876 const reg_entry
*reg
= parse_reg (&str
);
877 struct neon_type_el atype
;
878 struct neon_type_el parsetype
;
879 bfd_boolean is_typed_vecreg
= FALSE
;
882 atype
.type
= NT_invtype
;
890 set_default_error ();
894 if (! aarch64_check_reg_type (reg
, type
))
896 DEBUG_TRACE ("reg type check failed");
897 set_default_error ();
902 if (type
== REG_TYPE_VN
903 && parse_neon_operand_type (&parsetype
, &str
))
905 /* Register if of the form Vn.[bhsdq]. */
906 is_typed_vecreg
= TRUE
;
908 if (parsetype
.width
== 0)
909 /* Expect index. In the new scheme we cannot have
910 Vn.[bhsdq] represent a scalar. Therefore any
911 Vn.[bhsdq] should have an index following it.
912 Except in reglists ofcourse. */
913 atype
.defined
|= NTA_HASINDEX
;
915 atype
.defined
|= NTA_HASTYPE
;
917 atype
.type
= parsetype
.type
;
918 atype
.width
= parsetype
.width
;
921 if (skip_past_char (&str
, '['))
925 /* Reject Sn[index] syntax. */
926 if (!is_typed_vecreg
)
928 first_error (_("this type of register can't be indexed"));
932 if (in_reg_list
== TRUE
)
934 first_error (_("index not allowed inside register list"));
938 atype
.defined
|= NTA_HASINDEX
;
940 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
942 if (exp
.X_op
!= O_constant
)
944 first_error (_("constant expression required"));
948 if (! skip_past_char (&str
, ']'))
951 atype
.index
= exp
.X_add_number
;
953 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
955 /* Indexed vector register expected. */
956 first_error (_("indexed vector register expected"));
960 /* A vector reg Vn should be typed or indexed. */
961 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
963 first_error (_("invalid use of vector register"));
979 Return the register number on success; return PARSE_FAIL otherwise.
981 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
982 the register (e.g. NEON double or quad reg when either has been requested).
984 If this is a NEON vector register with additional type information, fill
985 in the struct pointed to by VECTYPE (if non-NULL).
987 This parser does not handle register list. */
990 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
991 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
993 struct neon_type_el atype
;
995 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
996 /*in_reg_list= */ FALSE
);
998 if (reg
== PARSE_FAIL
)
1009 static inline bfd_boolean
1010 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1014 && e1
.defined
== e2
.defined
1015 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1018 /* This function parses the NEON register list. On success, it returns
1019 the parsed register list information in the following encoded format:
1021 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1022 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1024 The information of the register shape and/or index is returned in
1027 It returns PARSE_FAIL if the register list is invalid.
1029 The list contains one to four registers.
1030 Each register can be one of:
1033 All <T> should be identical.
1034 All <index> should be identical.
1035 There are restrictions on <Vt> numbers which are checked later
1036 (by reg_list_valid_p). */
1039 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1043 struct neon_type_el typeinfo
, typeinfo_first
;
1048 bfd_boolean error
= FALSE
;
1049 bfd_boolean expect_index
= FALSE
;
1053 set_syntax_error (_("expecting {"));
1059 typeinfo_first
.defined
= 0;
1060 typeinfo_first
.type
= NT_invtype
;
1061 typeinfo_first
.width
= -1;
1062 typeinfo_first
.index
= 0;
1071 str
++; /* skip over '-' */
1074 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1075 /*in_reg_list= */ TRUE
);
1076 if (val
== PARSE_FAIL
)
1078 set_first_syntax_error (_("invalid vector register in list"));
1082 /* reject [bhsd]n */
1083 if (typeinfo
.defined
== 0)
1085 set_first_syntax_error (_("invalid scalar register in list"));
1090 if (typeinfo
.defined
& NTA_HASINDEX
)
1091 expect_index
= TRUE
;
1095 if (val
< val_range
)
1097 set_first_syntax_error
1098 (_("invalid range in vector register list"));
1107 typeinfo_first
= typeinfo
;
1108 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1110 set_first_syntax_error
1111 (_("type mismatch in vector register list"));
1116 for (i
= val_range
; i
<= val
; i
++)
1118 ret_val
|= i
<< (5 * nb_regs
);
1123 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1125 skip_whitespace (str
);
1128 set_first_syntax_error (_("end of vector register list not found"));
1133 skip_whitespace (str
);
1137 if (skip_past_char (&str
, '['))
1141 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1142 if (exp
.X_op
!= O_constant
)
1144 set_first_syntax_error (_("constant expression required."));
1147 if (! skip_past_char (&str
, ']'))
1150 typeinfo_first
.index
= exp
.X_add_number
;
1154 set_first_syntax_error (_("expected index"));
1161 set_first_syntax_error (_("too many registers in vector register list"));
1164 else if (nb_regs
== 0)
1166 set_first_syntax_error (_("empty vector register list"));
1172 *vectype
= typeinfo_first
;
1174 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1177 /* Directives: register aliases. */
1180 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1185 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1188 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1191 /* Only warn about a redefinition if it's not defined as the
1193 else if (new->number
!= number
|| new->type
!= type
)
1194 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1199 name
= xstrdup (str
);
1200 new = xmalloc (sizeof (reg_entry
));
1203 new->number
= number
;
1205 new->builtin
= FALSE
;
1207 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1213 /* Look for the .req directive. This is of the form:
1215 new_register_name .req existing_register_name
1217 If we find one, or if it looks sufficiently like one that we want to
1218 handle any error here, return TRUE. Otherwise return FALSE. */
1221 create_register_alias (char *newname
, char *p
)
1223 const reg_entry
*old
;
1224 char *oldname
, *nbuf
;
1227 /* The input scrubber ensures that whitespace after the mnemonic is
1228 collapsed to single spaces. */
1230 if (strncmp (oldname
, " .req ", 6) != 0)
1234 if (*oldname
== '\0')
1237 old
= hash_find (aarch64_reg_hsh
, oldname
);
1240 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1244 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1245 the desired alias name, and p points to its end. If not, then
1246 the desired alias name is in the global original_case_string. */
1247 #ifdef TC_CASE_SENSITIVE
1250 newname
= original_case_string
;
1251 nlen
= strlen (newname
);
1254 nbuf
= alloca (nlen
+ 1);
1255 memcpy (nbuf
, newname
, nlen
);
1258 /* Create aliases under the new name as stated; an all-lowercase
1259 version of the new name; and an all-uppercase version of the new
1261 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1263 for (p
= nbuf
; *p
; p
++)
1266 if (strncmp (nbuf
, newname
, nlen
))
1268 /* If this attempt to create an additional alias fails, do not bother
1269 trying to create the all-lower case alias. We will fail and issue
1270 a second, duplicate error message. This situation arises when the
1271 programmer does something like:
1274 The second .req creates the "Foo" alias but then fails to create
1275 the artificial FOO alias because it has already been created by the
1277 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1281 for (p
= nbuf
; *p
; p
++)
1284 if (strncmp (nbuf
, newname
, nlen
))
1285 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1291 /* Should never be called, as .req goes between the alias and the
1292 register name, not at the beginning of the line. */
1294 s_req (int a ATTRIBUTE_UNUSED
)
1296 as_bad (_("invalid syntax for .req directive"));
1299 /* The .unreq directive deletes an alias which was previously defined
1300 by .req. For example:
1306 s_unreq (int a ATTRIBUTE_UNUSED
)
1311 name
= input_line_pointer
;
1313 while (*input_line_pointer
!= 0
1314 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1315 ++input_line_pointer
;
1317 saved_char
= *input_line_pointer
;
1318 *input_line_pointer
= 0;
1321 as_bad (_("invalid syntax for .unreq directive"));
1324 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1327 as_bad (_("unknown register alias '%s'"), name
);
1328 else if (reg
->builtin
)
1329 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1336 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1337 free ((char *) reg
->name
);
1340 /* Also locate the all upper case and all lower case versions.
1341 Do not complain if we cannot find one or the other as it
1342 was probably deleted above. */
1344 nbuf
= strdup (name
);
1345 for (p
= nbuf
; *p
; p
++)
1347 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1350 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1351 free ((char *) reg
->name
);
1355 for (p
= nbuf
; *p
; p
++)
1357 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1360 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1361 free ((char *) reg
->name
);
1369 *input_line_pointer
= saved_char
;
1370 demand_empty_rest_of_line ();
1373 /* Directives: Instruction set selection. */
1376 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1377 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1378 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1379 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1381 /* Create a new mapping symbol for the transition to STATE. */
1384 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1387 const char *symname
;
1394 type
= BSF_NO_FLAGS
;
1398 type
= BSF_NO_FLAGS
;
1404 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1405 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1407 /* Save the mapping symbols for future reference. Also check that
1408 we do not place two mapping symbols at the same offset within a
1409 frag. We'll handle overlap between frags in
1410 check_mapping_symbols.
1412 If .fill or other data filling directive generates zero sized data,
1413 the mapping symbol for the following code will have the same value
1414 as the one generated for the data filling directive. In this case,
1415 we replace the old symbol with the new one at the same address. */
1418 if (frag
->tc_frag_data
.first_map
!= NULL
)
1420 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1421 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1424 frag
->tc_frag_data
.first_map
= symbolP
;
1426 if (frag
->tc_frag_data
.last_map
!= NULL
)
1428 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1429 S_GET_VALUE (symbolP
));
1430 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1431 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1434 frag
->tc_frag_data
.last_map
= symbolP
;
1437 /* We must sometimes convert a region marked as code to data during
1438 code alignment, if an odd number of bytes have to be padded. The
1439 code mapping symbol is pushed to an aligned address. */
1442 insert_data_mapping_symbol (enum mstate state
,
1443 valueT value
, fragS
* frag
, offsetT bytes
)
1445 /* If there was already a mapping symbol, remove it. */
1446 if (frag
->tc_frag_data
.last_map
!= NULL
1447 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1448 frag
->fr_address
+ value
)
1450 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1454 know (frag
->tc_frag_data
.first_map
== symp
);
1455 frag
->tc_frag_data
.first_map
= NULL
;
1457 frag
->tc_frag_data
.last_map
= NULL
;
1458 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1461 make_mapping_symbol (MAP_DATA
, value
, frag
);
1462 make_mapping_symbol (state
, value
+ bytes
, frag
);
1465 static void mapping_state_2 (enum mstate state
, int max_chars
);
1467 /* Set the mapping state to STATE. Only call this when about to
1468 emit some STATE bytes to the file. */
1470 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1472 mapping_state (enum mstate state
)
1474 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1476 if (mapstate
== state
)
1477 /* The mapping symbol has already been emitted.
1478 There is nothing else to do. */
1481 if (state
== MAP_INSN
)
1482 /* AArch64 instructions require 4-byte alignment. When emitting
1483 instructions into any section, record the appropriate section
1485 record_alignment (now_seg
, 2);
1487 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
1488 /* This case will be evaluated later in the next else. */
1491 mapping_state_2 (state
, 0);
1494 /* Same as mapping_state, but MAX_CHARS bytes have already been
1495 allocated. Put the mapping symbol that far back. */
1498 mapping_state_2 (enum mstate state
, int max_chars
)
1500 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1502 if (!SEG_NORMAL (now_seg
))
1505 if (mapstate
== state
)
1506 /* The mapping symbol has already been emitted.
1507 There is nothing else to do. */
1510 if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1512 /* Only add the symbol if the offset is > 0:
1513 if we're at the first frag, check it's size > 0;
1514 if we're not at the first frag, then for sure
1515 the offset is > 0. */
1516 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1517 const int add_symbol
= (frag_now
!= frag_first
)
1518 || (frag_now_fix () > 0);
1521 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1524 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1525 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1529 #define mapping_state(x) /* nothing */
1530 #define mapping_state_2(x, y) /* nothing */
1533 /* Directives: sectioning and alignment. */
1536 s_bss (int ignore ATTRIBUTE_UNUSED
)
1538 /* We don't support putting frags in the BSS segment, we fake it by
1539 marking in_bss, then looking at s_skip for clues. */
1540 subseg_set (bss_section
, 0);
1541 demand_empty_rest_of_line ();
1542 mapping_state (MAP_DATA
);
1546 s_even (int ignore ATTRIBUTE_UNUSED
)
1548 /* Never make frag if expect extra pass. */
1550 frag_align (1, 0, 0);
1552 record_alignment (now_seg
, 1);
1554 demand_empty_rest_of_line ();
1557 /* Directives: Literal pools. */
1559 static literal_pool
*
1560 find_literal_pool (int size
)
1564 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1566 if (pool
->section
== now_seg
1567 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1574 static literal_pool
*
1575 find_or_make_literal_pool (int size
)
1577 /* Next literal pool ID number. */
1578 static unsigned int latest_pool_num
= 1;
1581 pool
= find_literal_pool (size
);
1585 /* Create a new pool. */
1586 pool
= xmalloc (sizeof (*pool
));
1590 /* Currently we always put the literal pool in the current text
1591 section. If we were generating "small" model code where we
1592 knew that all code and initialised data was within 1MB then
1593 we could output literals to mergeable, read-only data
1596 pool
->next_free_entry
= 0;
1597 pool
->section
= now_seg
;
1598 pool
->sub_section
= now_subseg
;
1600 pool
->next
= list_of_pools
;
1601 pool
->symbol
= NULL
;
1603 /* Add it to the list. */
1604 list_of_pools
= pool
;
1607 /* New pools, and emptied pools, will have a NULL symbol. */
1608 if (pool
->symbol
== NULL
)
1610 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1611 (valueT
) 0, &zero_address_frag
);
1612 pool
->id
= latest_pool_num
++;
1619 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1620 Return TRUE on success, otherwise return FALSE. */
1622 add_to_lit_pool (expressionS
*exp
, int size
)
1627 pool
= find_or_make_literal_pool (size
);
1629 /* Check if this literal value is already in the pool. */
1630 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1632 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1634 if ((litexp
->X_op
== exp
->X_op
)
1635 && (exp
->X_op
== O_constant
)
1636 && (litexp
->X_add_number
== exp
->X_add_number
)
1637 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1640 if ((litexp
->X_op
== exp
->X_op
)
1641 && (exp
->X_op
== O_symbol
)
1642 && (litexp
->X_add_number
== exp
->X_add_number
)
1643 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1644 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1648 /* Do we need to create a new entry? */
1649 if (entry
== pool
->next_free_entry
)
1651 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1653 set_syntax_error (_("literal pool overflow"));
1657 pool
->literals
[entry
].exp
= *exp
;
1658 pool
->next_free_entry
+= 1;
1659 if (exp
->X_op
== O_big
)
1661 /* PR 16688: Bignums are held in a single global array. We must
1662 copy and preserve that value now, before it is overwritten. */
1663 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1664 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1665 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1668 pool
->literals
[entry
].bignum
= NULL
;
1671 exp
->X_op
= O_symbol
;
1672 exp
->X_add_number
= ((int) entry
) * size
;
1673 exp
->X_add_symbol
= pool
->symbol
;
1678 /* Can't use symbol_new here, so have to create a symbol and then at
1679 a later date assign it a value. Thats what these functions do. */
1682 symbol_locate (symbolS
* symbolP
,
1683 const char *name
,/* It is copied, the caller can modify. */
1684 segT segment
, /* Segment identifier (SEG_<something>). */
1685 valueT valu
, /* Symbol value. */
1686 fragS
* frag
) /* Associated fragment. */
1689 char *preserved_copy_of_name
;
1691 name_length
= strlen (name
) + 1; /* +1 for \0. */
1692 obstack_grow (¬es
, name
, name_length
);
1693 preserved_copy_of_name
= obstack_finish (¬es
);
1695 #ifdef tc_canonicalize_symbol_name
1696 preserved_copy_of_name
=
1697 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1700 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1702 S_SET_SEGMENT (symbolP
, segment
);
1703 S_SET_VALUE (symbolP
, valu
);
1704 symbol_clear_list_pointers (symbolP
);
1706 symbol_set_frag (symbolP
, frag
);
1708 /* Link to end of symbol chain. */
1710 extern int symbol_table_frozen
;
1712 if (symbol_table_frozen
)
1716 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1718 obj_symbol_new_hook (symbolP
);
1720 #ifdef tc_symbol_new_hook
1721 tc_symbol_new_hook (symbolP
);
1725 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1726 #endif /* DEBUG_SYMS */
1731 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1738 for (align
= 2; align
<= 4; align
++)
1740 int size
= 1 << align
;
1742 pool
= find_literal_pool (size
);
1743 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1746 mapping_state (MAP_DATA
);
1748 /* Align pool as you have word accesses.
1749 Only make a frag if we have to. */
1751 frag_align (align
, 0, 0);
1753 record_alignment (now_seg
, align
);
1755 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1757 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1758 (valueT
) frag_now_fix (), frag_now
);
1759 symbol_table_insert (pool
->symbol
);
1761 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1763 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1765 if (exp
->X_op
== O_big
)
1767 /* PR 16688: Restore the global bignum value. */
1768 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1769 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1770 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1773 /* First output the expression in the instruction to the pool. */
1774 emit_expr (exp
, size
); /* .word|.xword */
1776 if (exp
->X_op
== O_big
)
1778 free (pool
->literals
[entry
].bignum
);
1779 pool
->literals
[entry
].bignum
= NULL
;
1783 /* Mark the pool as empty. */
1784 pool
->next_free_entry
= 0;
1785 pool
->symbol
= NULL
;
1790 /* Forward declarations for functions below, in the MD interface
1792 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1793 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1795 /* Directives: Data. */
1796 /* N.B. the support for relocation suffix in this directive needs to be
1797 implemented properly. */
1800 s_aarch64_elf_cons (int nbytes
)
1804 #ifdef md_flush_pending_output
1805 md_flush_pending_output ();
1808 if (is_it_end_of_statement ())
1810 demand_empty_rest_of_line ();
1814 #ifdef md_cons_align
1815 md_cons_align (nbytes
);
1818 mapping_state (MAP_DATA
);
1821 struct reloc_table_entry
*reloc
;
1825 if (exp
.X_op
!= O_symbol
)
1826 emit_expr (&exp
, (unsigned int) nbytes
);
1829 skip_past_char (&input_line_pointer
, '#');
1830 if (skip_past_char (&input_line_pointer
, ':'))
1832 reloc
= find_reloc_table_entry (&input_line_pointer
);
1834 as_bad (_("unrecognized relocation suffix"));
1836 as_bad (_("unimplemented relocation suffix"));
1837 ignore_rest_of_line ();
1841 emit_expr (&exp
, (unsigned int) nbytes
);
1844 while (*input_line_pointer
++ == ',');
1846 /* Put terminator back into stream. */
1847 input_line_pointer
--;
1848 demand_empty_rest_of_line ();
1851 #endif /* OBJ_ELF */
1853 /* Output a 32-bit word, but mark as an instruction. */
1856 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1860 #ifdef md_flush_pending_output
1861 md_flush_pending_output ();
1864 if (is_it_end_of_statement ())
1866 demand_empty_rest_of_line ();
1871 frag_align_code (2, 0);
1873 mapping_state (MAP_INSN
);
1879 if (exp
.X_op
!= O_constant
)
1881 as_bad (_("constant expression required"));
1882 ignore_rest_of_line ();
1886 if (target_big_endian
)
1888 unsigned int val
= exp
.X_add_number
;
1889 exp
.X_add_number
= SWAP_32 (val
);
1891 emit_expr (&exp
, 4);
1893 while (*input_line_pointer
++ == ',');
1895 /* Put terminator back into stream. */
1896 input_line_pointer
--;
1897 demand_empty_rest_of_line ();
1901 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1904 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1908 /* Since we're just labelling the code, there's no need to define a
1911 /* Make sure there is enough room in this frag for the following
1912 blr. This trick only works if the blr follows immediately after
1913 the .tlsdesc directive. */
1915 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1916 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1918 demand_empty_rest_of_line ();
1920 #endif /* OBJ_ELF */
1922 static void s_aarch64_arch (int);
1923 static void s_aarch64_cpu (int);
1924 static void s_aarch64_arch_extension (int);
1926 /* This table describes all the machine specific pseudo-ops the assembler
1927 has to support. The fields are:
1928 pseudo-op name without dot
1929 function to call to execute this pseudo-op
1930 Integer arg to pass to the function. */
1932 const pseudo_typeS md_pseudo_table
[] = {
1933 /* Never called because '.req' does not start a line. */
1935 {"unreq", s_unreq
, 0},
1937 {"even", s_even
, 0},
1938 {"ltorg", s_ltorg
, 0},
1939 {"pool", s_ltorg
, 0},
1940 {"cpu", s_aarch64_cpu
, 0},
1941 {"arch", s_aarch64_arch
, 0},
1942 {"arch_extension", s_aarch64_arch_extension
, 0},
1943 {"inst", s_aarch64_inst
, 0},
1945 {"tlsdesccall", s_tlsdesccall
, 0},
1946 {"word", s_aarch64_elf_cons
, 4},
1947 {"long", s_aarch64_elf_cons
, 4},
1948 {"xword", s_aarch64_elf_cons
, 8},
1949 {"dword", s_aarch64_elf_cons
, 8},
1955 /* Check whether STR points to a register name followed by a comma or the
1956 end of line; REG_TYPE indicates which register types are checked
1957 against. Return TRUE if STR is such a register name; otherwise return
1958 FALSE. The function does not intend to produce any diagnostics, but since
1959 the register parser aarch64_reg_parse, which is called by this function,
1960 does produce diagnostics, we call clear_error to clear any diagnostics
1961 that may be generated by aarch64_reg_parse.
1962 Also, the function returns FALSE directly if there is any user error
1963 present at the function entry. This prevents the existing diagnostics
1964 state from being spoiled.
1965 The function currently serves parse_constant_immediate and
1966 parse_big_immediate only. */
1968 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1972 /* Prevent the diagnostics state from being spoiled. */
1976 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1978 /* Clear the parsing error that may be set by the reg parser. */
1981 if (reg
== PARSE_FAIL
)
1984 skip_whitespace (str
);
1985 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1991 /* Parser functions used exclusively in instruction operands. */
1993 /* Parse an immediate expression which may not be constant.
1995 To prevent the expression parser from pushing a register name
1996 into the symbol table as an undefined symbol, firstly a check is
1997 done to find out whether STR is a valid register name followed
1998 by a comma or the end of line. Return FALSE if STR is such a
2002 parse_immediate_expression (char **str
, expressionS
*exp
)
2004 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2006 set_recoverable_error (_("immediate operand required"));
2010 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2012 if (exp
->X_op
== O_absent
)
2014 set_fatal_syntax_error (_("missing immediate expression"));
2021 /* Constant immediate-value read function for use in insn parsing.
2022 STR points to the beginning of the immediate (with the optional
2023 leading #); *VAL receives the value.
2025 Return TRUE on success; otherwise return FALSE. */
2028 parse_constant_immediate (char **str
, int64_t * val
)
2032 if (! parse_immediate_expression (str
, &exp
))
2035 if (exp
.X_op
!= O_constant
)
2037 set_syntax_error (_("constant expression required"));
2041 *val
= exp
.X_add_number
;
2046 encode_imm_float_bits (uint32_t imm
)
2048 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2049 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2052 /* Return TRUE if the single-precision floating-point value encoded in IMM
2053 can be expressed in the AArch64 8-bit signed floating-point format with
2054 3-bit exponent and normalized 4 bits of precision; in other words, the
2055 floating-point value must be expressable as
2056 (+/-) n / 16 * power (2, r)
2057 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2060 aarch64_imm_float_p (uint32_t imm
)
2062 /* If a single-precision floating-point value has the following bit
2063 pattern, it can be expressed in the AArch64 8-bit floating-point
2066 3 32222222 2221111111111
2067 1 09876543 21098765432109876543210
2068 n Eeeeeexx xxxx0000000000000000000
2070 where n, e and each x are either 0 or 1 independently, with
2075 /* Prepare the pattern for 'Eeeeee'. */
2076 if (((imm
>> 30) & 0x1) == 0)
2077 pattern
= 0x3e000000;
2079 pattern
= 0x40000000;
2081 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2082 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2085 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2087 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2088 8-bit signed floating-point format with 3-bit exponent and normalized 4
2089 bits of precision (i.e. can be used in an FMOV instruction); return the
2090 equivalent single-precision encoding in *FPWORD.
2092 Otherwise return FALSE. */
2095 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2097 /* If a double-precision floating-point value has the following bit
2098 pattern, it can be expressed in the AArch64 8-bit floating-point
2101 6 66655555555 554444444...21111111111
2102 3 21098765432 109876543...098765432109876543210
2103 n Eeeeeeeeexx xxxx00000...000000000000000000000
2105 where n, e and each x are either 0 or 1 independently, with
2109 uint32_t high32
= imm
>> 32;
2111 /* Lower 32 bits need to be 0s. */
2112 if ((imm
& 0xffffffff) != 0)
2115 /* Prepare the pattern for 'Eeeeeeeee'. */
2116 if (((high32
>> 30) & 0x1) == 0)
2117 pattern
= 0x3fc00000;
2119 pattern
= 0x40000000;
2121 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2122 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2124 /* Convert to the single-precision encoding.
2126 n Eeeeeeeeexx xxxx00000...000000000000000000000
2128 n Eeeeeexx xxxx0000000000000000000. */
2129 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2130 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2137 /* Parse a floating-point immediate. Return TRUE on success and return the
2138 value in *IMMED in the format of IEEE754 single-precision encoding.
2139 *CCP points to the start of the string; DP_P is TRUE when the immediate
2140 is expected to be in double-precision (N.B. this only matters when
2141 hexadecimal representation is involved).
2143 N.B. 0.0 is accepted by this function. */
2146 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2150 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2151 int found_fpchar
= 0;
2153 unsigned fpword
= 0;
2154 bfd_boolean hex_p
= FALSE
;
2156 skip_past_char (&str
, '#');
2159 skip_whitespace (fpnum
);
2161 if (strncmp (fpnum
, "0x", 2) == 0)
2163 /* Support the hexadecimal representation of the IEEE754 encoding.
2164 Double-precision is expected when DP_P is TRUE, otherwise the
2165 representation should be in single-precision. */
2166 if (! parse_constant_immediate (&str
, &val
))
2171 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2174 else if ((uint64_t) val
> 0xffffffff)
2183 /* We must not accidentally parse an integer as a floating-point number.
2184 Make sure that the value we parse is not an integer by checking for
2185 special characters '.' or 'e'. */
2186 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2187 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2201 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2204 /* Our FP word must be 32 bits (single-precision FP). */
2205 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2207 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2212 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2220 set_fatal_syntax_error (_("invalid floating-point constant"));
2224 /* Less-generic immediate-value read function with the possibility of loading
2225 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2228 To prevent the expression parser from pushing a register name into the
2229 symbol table as an undefined symbol, a check is firstly done to find
2230 out whether STR is a valid register name followed by a comma or the end
2231 of line. Return FALSE if STR is such a register. */
2234 parse_big_immediate (char **str
, int64_t *imm
)
2238 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2240 set_syntax_error (_("immediate operand required"));
2244 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2246 if (inst
.reloc
.exp
.X_op
== O_constant
)
2247 *imm
= inst
.reloc
.exp
.X_add_number
;
2254 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2255 if NEED_LIBOPCODES is non-zero, the fixup will need
2256 assistance from the libopcodes. */
2259 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2260 const aarch64_opnd_info
*operand
,
2261 int need_libopcodes_p
)
2263 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2264 reloc
->opnd
= operand
->type
;
2265 if (need_libopcodes_p
)
2266 reloc
->need_libopcodes_p
= 1;
2269 /* Return TRUE if the instruction needs to be fixed up later internally by
2270 the GAS; otherwise return FALSE. */
2272 static inline bfd_boolean
2273 aarch64_gas_internal_fixup_p (void)
2275 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2278 /* Assign the immediate value to the relavant field in *OPERAND if
2279 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2280 needs an internal fixup in a later stage.
2281 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2282 IMM.VALUE that may get assigned with the constant. */
2284 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2285 aarch64_opnd_info
*operand
,
2287 int need_libopcodes_p
,
2290 if (reloc
->exp
.X_op
== O_constant
)
2293 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2295 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2296 reloc
->type
= BFD_RELOC_UNUSED
;
2300 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2301 /* Tell libopcodes to ignore this operand or not. This is helpful
2302 when one of the operands needs to be fixed up later but we need
2303 libopcodes to check the other operands. */
2304 operand
->skip
= skip_p
;
2308 /* Relocation modifiers. Each entry in the table contains the textual
2309 name for the relocation which may be placed before a symbol used as
2310 a load/store offset, or add immediate. It must be surrounded by a
2311 leading and trailing colon, for example:
2313 ldr x0, [x1, #:rello:varsym]
2314 add x0, x1, #:rello:varsym */
2316 struct reloc_table_entry
2320 bfd_reloc_code_real_type adr_type
;
2321 bfd_reloc_code_real_type adrp_type
;
2322 bfd_reloc_code_real_type movw_type
;
2323 bfd_reloc_code_real_type add_type
;
2324 bfd_reloc_code_real_type ldst_type
;
2325 bfd_reloc_code_real_type ld_literal_type
;
2328 static struct reloc_table_entry reloc_table
[] = {
2329 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2334 BFD_RELOC_AARCH64_ADD_LO12
,
2335 BFD_RELOC_AARCH64_LDST_LO12
,
2338 /* Higher 21 bits of pc-relative page offset: ADRP */
2341 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2347 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2350 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2356 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2360 BFD_RELOC_AARCH64_MOVW_G0
,
2365 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2369 BFD_RELOC_AARCH64_MOVW_G0_S
,
2374 /* Less significant bits 0-15 of address/value: MOVK, no check */
2378 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2383 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2387 BFD_RELOC_AARCH64_MOVW_G1
,
2392 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2396 BFD_RELOC_AARCH64_MOVW_G1_S
,
2401 /* Less significant bits 16-31 of address/value: MOVK, no check */
2405 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2410 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2414 BFD_RELOC_AARCH64_MOVW_G2
,
2419 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2423 BFD_RELOC_AARCH64_MOVW_G2_S
,
2428 /* Less significant bits 32-47 of address/value: MOVK, no check */
2432 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2437 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2441 BFD_RELOC_AARCH64_MOVW_G3
,
2446 /* Get to the page containing GOT entry for a symbol. */
2449 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2453 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2455 /* 12 bit offset into the page containing GOT entry for that symbol. */
2461 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2464 /* Get to the page containing GOT TLS entry for a symbol */
2466 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2467 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2473 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2478 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2482 /* Get to the page containing GOT TLS entry for a symbol */
2484 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2485 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2489 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2491 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2496 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2497 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2500 /* Get to the page containing GOT TLS entry for a symbol */
2503 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2507 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2509 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2510 {"gottprel_lo12", 0,
2515 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2518 /* Get tp offset for a symbol. */
2523 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2527 /* Get tp offset for a symbol. */
2532 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2536 /* Get tp offset for a symbol. */
2541 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2545 /* Get tp offset for a symbol. */
2546 {"tprel_lo12_nc", 0,
2550 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2554 /* Most significant bits 32-47 of address/value: MOVZ. */
2558 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2563 /* Most significant bits 16-31 of address/value: MOVZ. */
2567 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2572 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2576 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2581 /* Most significant bits 0-15 of address/value: MOVZ. */
2585 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2590 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2594 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2600 /* Given the address of a pointer pointing to the textual name of a
2601 relocation as may appear in assembler source, attempt to find its
2602 details in reloc_table. The pointer will be updated to the character
2603 after the trailing colon. On failure, NULL will be returned;
2604 otherwise return the reloc_table_entry. */
2606 static struct reloc_table_entry
*
2607 find_reloc_table_entry (char **str
)
2610 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2612 int length
= strlen (reloc_table
[i
].name
);
2614 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2615 && (*str
)[length
] == ':')
2617 *str
+= (length
+ 1);
2618 return &reloc_table
[i
];
2625 /* Mode argument to parse_shift and parser_shifter_operand. */
2626 enum parse_shift_mode
2628 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2630 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2632 SHIFTED_LSL
, /* bare "lsl #n" */
2633 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2634 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2637 /* Parse a <shift> operator on an AArch64 data processing instruction.
2638 Return TRUE on success; otherwise return FALSE. */
2640 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2642 const struct aarch64_name_value_pair
*shift_op
;
2643 enum aarch64_modifier_kind kind
;
2649 for (p
= *str
; ISALPHA (*p
); p
++)
2654 set_syntax_error (_("shift expression expected"));
2658 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2660 if (shift_op
== NULL
)
2662 set_syntax_error (_("shift operator expected"));
2666 kind
= aarch64_get_operand_modifier (shift_op
);
2668 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2670 set_syntax_error (_("invalid use of 'MSL'"));
2676 case SHIFTED_LOGIC_IMM
:
2677 if (aarch64_extend_operator_p (kind
) == TRUE
)
2679 set_syntax_error (_("extending shift is not permitted"));
2684 case SHIFTED_ARITH_IMM
:
2685 if (kind
== AARCH64_MOD_ROR
)
2687 set_syntax_error (_("'ROR' shift is not permitted"));
2693 if (kind
!= AARCH64_MOD_LSL
)
2695 set_syntax_error (_("only 'LSL' shift is permitted"));
2700 case SHIFTED_REG_OFFSET
:
2701 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2702 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2704 set_fatal_syntax_error
2705 (_("invalid shift for the register offset addressing mode"));
2710 case SHIFTED_LSL_MSL
:
2711 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2713 set_syntax_error (_("invalid shift operator"));
2722 /* Whitespace can appear here if the next thing is a bare digit. */
2723 skip_whitespace (p
);
2725 /* Parse shift amount. */
2727 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2728 exp
.X_op
= O_absent
;
2731 if (is_immediate_prefix (*p
))
2736 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2738 if (exp
.X_op
== O_absent
)
2740 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2742 set_syntax_error (_("missing shift amount"));
2745 operand
->shifter
.amount
= 0;
2747 else if (exp
.X_op
!= O_constant
)
2749 set_syntax_error (_("constant shift amount required"));
2752 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2754 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2759 operand
->shifter
.amount
= exp
.X_add_number
;
2760 operand
->shifter
.amount_present
= 1;
2763 operand
->shifter
.operator_present
= 1;
2764 operand
->shifter
.kind
= kind
;
2770 /* Parse a <shifter_operand> for a data processing instruction:
2773 #<immediate>, LSL #imm
2775 Validation of immediate operands is deferred to md_apply_fix.
2777 Return TRUE on success; otherwise return FALSE. */
2780 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2781 enum parse_shift_mode mode
)
2785 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2790 /* Accept an immediate expression. */
2791 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2794 /* Accept optional LSL for arithmetic immediate values. */
2795 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2796 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2799 /* Not accept any shifter for logical immediate values. */
2800 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2801 && parse_shift (&p
, operand
, mode
))
2803 set_syntax_error (_("unexpected shift operator"));
2811 /* Parse a <shifter_operand> for a data processing instruction:
2816 #<immediate>, LSL #imm
2818 where <shift> is handled by parse_shift above, and the last two
2819 cases are handled by the function above.
2821 Validation of immediate operands is deferred to md_apply_fix.
2823 Return TRUE on success; otherwise return FALSE. */
2826 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2827 enum parse_shift_mode mode
)
2830 int isreg32
, isregzero
;
2831 enum aarch64_operand_class opd_class
2832 = aarch64_get_operand_class (operand
->type
);
2835 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2837 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2839 set_syntax_error (_("unexpected register in the immediate operand"));
2843 if (!isregzero
&& reg
== REG_SP
)
2845 set_syntax_error (BAD_SP
);
2849 operand
->reg
.regno
= reg
;
2850 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2852 /* Accept optional shift operation on register. */
2853 if (! skip_past_comma (str
))
2856 if (! parse_shift (str
, operand
, mode
))
2861 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2864 (_("integer register expected in the extended/shifted operand "
2869 /* We have a shifted immediate variable. */
2870 return parse_shifter_operand_imm (str
, operand
, mode
);
2873 /* Return TRUE on success; return FALSE otherwise. */
2876 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2877 enum parse_shift_mode mode
)
2881 /* Determine if we have the sequence of characters #: or just :
2882 coming next. If we do, then we check for a :rello: relocation
2883 modifier. If we don't, punt the whole lot to
2884 parse_shifter_operand. */
2886 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2888 struct reloc_table_entry
*entry
;
2896 /* Try to parse a relocation. Anything else is an error. */
2897 if (!(entry
= find_reloc_table_entry (str
)))
2899 set_syntax_error (_("unknown relocation modifier"));
2903 if (entry
->add_type
== 0)
2906 (_("this relocation modifier is not allowed on this instruction"));
2910 /* Save str before we decompose it. */
2913 /* Next, we parse the expression. */
2914 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2917 /* Record the relocation type (use the ADD variant here). */
2918 inst
.reloc
.type
= entry
->add_type
;
2919 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2921 /* If str is empty, we've reached the end, stop here. */
2925 /* Otherwise, we have a shifted reloc modifier, so rewind to
2926 recover the variable name and continue parsing for the shifter. */
2928 return parse_shifter_operand_imm (str
, operand
, mode
);
2931 return parse_shifter_operand (str
, operand
, mode
);
2934 /* Parse all forms of an address expression. Information is written
2935 to *OPERAND and/or inst.reloc.
2937 The A64 instruction set has the following addressing modes:
2940 [base] // in SIMD ld/st structure
2941 [base{,#0}] // in ld/st exclusive
2943 [base,Xm{,LSL #imm}]
2944 [base,Xm,SXTX {#imm}]
2945 [base,Wm,(S|U)XTW {#imm}]
2950 [base],Xm // in SIMD ld/st structure
2951 PC-relative (literal)
2955 (As a convenience, the notation "=immediate" is permitted in conjunction
2956 with the pc-relative literal load instructions to automatically place an
2957 immediate value or symbolic address in a nearby literal pool and generate
2958 a hidden label which references it.)
2960 Upon a successful parsing, the address structure in *OPERAND will be
2961 filled in the following way:
2963 .base_regno = <base>
2964 .offset.is_reg // 1 if the offset is a register
2966 .offset.regno = <Rm>
2968 For different addressing modes defined in the A64 ISA:
2971 .pcrel=0; .preind=1; .postind=0; .writeback=0
2973 .pcrel=0; .preind=1; .postind=0; .writeback=1
2975 .pcrel=0; .preind=0; .postind=1; .writeback=1
2976 PC-relative (literal)
2977 .pcrel=1; .preind=1; .postind=0; .writeback=0
2979 The shift/extension information, if any, will be stored in .shifter.
2981 It is the caller's responsibility to check for addressing modes not
2982 supported by the instruction, and to set inst.reloc.type. */
2985 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
2986 int accept_reg_post_index
)
2990 int isreg32
, isregzero
;
2991 expressionS
*exp
= &inst
.reloc
.exp
;
2993 if (! skip_past_char (&p
, '['))
2995 /* =immediate or label. */
2996 operand
->addr
.pcrel
= 1;
2997 operand
->addr
.preind
= 1;
2999 /* #:<reloc_op>:<symbol> */
3000 skip_past_char (&p
, '#');
3001 if (reloc
&& skip_past_char (&p
, ':'))
3003 bfd_reloc_code_real_type ty
;
3004 struct reloc_table_entry
*entry
;
3006 /* Try to parse a relocation modifier. Anything else is
3008 entry
= find_reloc_table_entry (&p
);
3011 set_syntax_error (_("unknown relocation modifier"));
3015 switch (operand
->type
)
3017 case AARCH64_OPND_ADDR_PCREL21
:
3019 ty
= entry
->adr_type
;
3023 ty
= entry
->ld_literal_type
;
3030 (_("this relocation modifier is not allowed on this "
3036 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3038 set_syntax_error (_("invalid relocation expression"));
3042 /* #:<reloc_op>:<expr> */
3043 /* Record the relocation type. */
3044 inst
.reloc
.type
= ty
;
3045 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3050 if (skip_past_char (&p
, '='))
3051 /* =immediate; need to generate the literal in the literal pool. */
3052 inst
.gen_lit_pool
= 1;
3054 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3056 set_syntax_error (_("invalid address"));
3067 /* Accept SP and reject ZR */
3068 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3069 if (reg
== PARSE_FAIL
|| isreg32
)
3071 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3074 operand
->addr
.base_regno
= reg
;
3077 if (skip_past_comma (&p
))
3080 operand
->addr
.preind
= 1;
3082 /* Reject SP and accept ZR */
3083 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3084 if (reg
!= PARSE_FAIL
)
3087 operand
->addr
.offset
.regno
= reg
;
3088 operand
->addr
.offset
.is_reg
= 1;
3089 /* Shifted index. */
3090 if (skip_past_comma (&p
))
3093 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3094 /* Use the diagnostics set in parse_shift, so not set new
3095 error message here. */
3099 [base,Xm{,LSL #imm}]
3100 [base,Xm,SXTX {#imm}]
3101 [base,Wm,(S|U)XTW {#imm}] */
3102 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3103 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3104 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3108 set_syntax_error (_("invalid use of 32-bit register offset"));
3114 set_syntax_error (_("invalid use of 64-bit register offset"));
3120 /* [Xn,#:<reloc_op>:<symbol> */
3121 skip_past_char (&p
, '#');
3122 if (reloc
&& skip_past_char (&p
, ':'))
3124 struct reloc_table_entry
*entry
;
3126 /* Try to parse a relocation modifier. Anything else is
3128 if (!(entry
= find_reloc_table_entry (&p
)))
3130 set_syntax_error (_("unknown relocation modifier"));
3134 if (entry
->ldst_type
== 0)
3137 (_("this relocation modifier is not allowed on this "
3142 /* [Xn,#:<reloc_op>: */
3143 /* We now have the group relocation table entry corresponding to
3144 the name in the assembler source. Next, we parse the
3146 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3148 set_syntax_error (_("invalid relocation expression"));
3152 /* [Xn,#:<reloc_op>:<expr> */
3153 /* Record the load/store relocation type. */
3154 inst
.reloc
.type
= entry
->ldst_type
;
3155 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3157 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3159 set_syntax_error (_("invalid expression in the address"));
3166 if (! skip_past_char (&p
, ']'))
3168 set_syntax_error (_("']' expected"));
3172 if (skip_past_char (&p
, '!'))
3174 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3176 set_syntax_error (_("register offset not allowed in pre-indexed "
3177 "addressing mode"));
3181 operand
->addr
.writeback
= 1;
3183 else if (skip_past_comma (&p
))
3186 operand
->addr
.postind
= 1;
3187 operand
->addr
.writeback
= 1;
3189 if (operand
->addr
.preind
)
3191 set_syntax_error (_("cannot combine pre- and post-indexing"));
3195 if (accept_reg_post_index
3196 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3197 &isregzero
)) != PARSE_FAIL
)
3202 set_syntax_error (_("invalid 32-bit register offset"));
3205 operand
->addr
.offset
.regno
= reg
;
3206 operand
->addr
.offset
.is_reg
= 1;
3208 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3211 set_syntax_error (_("invalid expression in the address"));
3216 /* If at this point neither .preind nor .postind is set, we have a
3217 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3218 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3220 if (operand
->addr
.writeback
)
3223 set_syntax_error (_("missing offset in the pre-indexed address"));
3226 operand
->addr
.preind
= 1;
3227 inst
.reloc
.exp
.X_op
= O_constant
;
3228 inst
.reloc
.exp
.X_add_number
= 0;
3235 /* Return TRUE on success; otherwise return FALSE. */
3237 parse_address (char **str
, aarch64_opnd_info
*operand
,
3238 int accept_reg_post_index
)
3240 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3243 /* Return TRUE on success; otherwise return FALSE. */
3245 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3247 return parse_address_main (str
, operand
, 1, 0);
3250 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3251 Return TRUE on success; otherwise return FALSE. */
3253 parse_half (char **str
, int *internal_fixup_p
)
3259 skip_past_char (&p
, '#');
3261 gas_assert (internal_fixup_p
);
3262 *internal_fixup_p
= 0;
3266 struct reloc_table_entry
*entry
;
3268 /* Try to parse a relocation. Anything else is an error. */
3270 if (!(entry
= find_reloc_table_entry (&p
)))
3272 set_syntax_error (_("unknown relocation modifier"));
3276 if (entry
->movw_type
== 0)
3279 (_("this relocation modifier is not allowed on this instruction"));
3283 inst
.reloc
.type
= entry
->movw_type
;
3286 *internal_fixup_p
= 1;
3288 /* Avoid parsing a register as a general symbol. */
3290 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3294 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3301 /* Parse an operand for an ADRP instruction:
3303 Return TRUE on success; otherwise return FALSE. */
3306 parse_adrp (char **str
)
3313 struct reloc_table_entry
*entry
;
3315 /* Try to parse a relocation. Anything else is an error. */
3317 if (!(entry
= find_reloc_table_entry (&p
)))
3319 set_syntax_error (_("unknown relocation modifier"));
3323 if (entry
->adrp_type
== 0)
3326 (_("this relocation modifier is not allowed on this instruction"));
3330 inst
.reloc
.type
= entry
->adrp_type
;
3333 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3335 inst
.reloc
.pc_rel
= 1;
3337 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3344 /* Miscellaneous. */
3346 /* Parse an option for a preload instruction. Returns the encoding for the
3347 option, or PARSE_FAIL. */
3350 parse_pldop (char **str
)
3353 const struct aarch64_name_value_pair
*o
;
3356 while (ISALNUM (*q
))
3359 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3367 /* Parse an option for a barrier instruction. Returns the encoding for the
3368 option, or PARSE_FAIL. */
3371 parse_barrier (char **str
)
3374 const asm_barrier_opt
*o
;
3377 while (ISALPHA (*q
))
3380 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3388 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3389 Returns the encoding for the option, or PARSE_FAIL.
3391 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3392 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3395 parse_sys_reg (char **str
, struct hash_control
*sys_regs
, int imple_defined_p
)
3399 const aarch64_sys_reg
*o
;
3403 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3405 *p
++ = TOLOWER (*q
);
3407 /* Assert that BUF be large enough. */
3408 gas_assert (p
- buf
== q
- *str
);
3410 o
= hash_find (sys_regs
, buf
);
3413 if (!imple_defined_p
)
3417 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3418 unsigned int op0
, op1
, cn
, cm
, op2
;
3420 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3423 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3425 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3430 if (aarch64_sys_reg_deprecated_p (o
))
3431 as_warn (_("system register name '%s' is deprecated and may be "
3432 "removed in a future release"), buf
);
3440 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3441 for the option, or NULL. */
3443 static const aarch64_sys_ins_reg
*
3444 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3448 const aarch64_sys_ins_reg
*o
;
3451 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3453 *p
++ = TOLOWER (*q
);
3456 o
= hash_find (sys_ins_regs
, buf
);
3464 #define po_char_or_fail(chr) do { \
3465 if (! skip_past_char (&str, chr)) \
3469 #define po_reg_or_fail(regtype) do { \
3470 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3471 if (val == PARSE_FAIL) \
3473 set_default_error (); \
3478 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3479 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3480 &isreg32, &isregzero); \
3481 if (val == PARSE_FAIL) \
3483 set_default_error (); \
3486 info->reg.regno = val; \
3488 info->qualifier = AARCH64_OPND_QLF_W; \
3490 info->qualifier = AARCH64_OPND_QLF_X; \
3493 #define po_imm_nc_or_fail() do { \
3494 if (! parse_constant_immediate (&str, &val)) \
3498 #define po_imm_or_fail(min, max) do { \
3499 if (! parse_constant_immediate (&str, &val)) \
3501 if (val < min || val > max) \
3503 set_fatal_syntax_error (_("immediate value out of range "\
3504 #min " to "#max)); \
3509 #define po_misc_or_fail(expr) do { \
3514 /* encode the 12-bit imm field of Add/sub immediate */
3515 static inline uint32_t
3516 encode_addsub_imm (uint32_t imm
)
3521 /* encode the shift amount field of Add/sub immediate */
3522 static inline uint32_t
3523 encode_addsub_imm_shift_amount (uint32_t cnt
)
3529 /* encode the imm field of Adr instruction */
3530 static inline uint32_t
3531 encode_adr_imm (uint32_t imm
)
3533 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3534 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3537 /* encode the immediate field of Move wide immediate */
3538 static inline uint32_t
3539 encode_movw_imm (uint32_t imm
)
3544 /* encode the 26-bit offset of unconditional branch */
3545 static inline uint32_t
3546 encode_branch_ofs_26 (uint32_t ofs
)
3548 return ofs
& ((1 << 26) - 1);
3551 /* encode the 19-bit offset of conditional branch and compare & branch */
3552 static inline uint32_t
3553 encode_cond_branch_ofs_19 (uint32_t ofs
)
3555 return (ofs
& ((1 << 19) - 1)) << 5;
3558 /* encode the 19-bit offset of ld literal */
3559 static inline uint32_t
3560 encode_ld_lit_ofs_19 (uint32_t ofs
)
3562 return (ofs
& ((1 << 19) - 1)) << 5;
3565 /* Encode the 14-bit offset of test & branch. */
3566 static inline uint32_t
3567 encode_tst_branch_ofs_14 (uint32_t ofs
)
3569 return (ofs
& ((1 << 14) - 1)) << 5;
3572 /* Encode the 16-bit imm field of svc/hvc/smc. */
3573 static inline uint32_t
3574 encode_svc_imm (uint32_t imm
)
3579 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3580 static inline uint32_t
3581 reencode_addsub_switch_add_sub (uint32_t opcode
)
3583 return opcode
^ (1 << 30);
3586 static inline uint32_t
3587 reencode_movzn_to_movz (uint32_t opcode
)
3589 return opcode
| (1 << 30);
3592 static inline uint32_t
3593 reencode_movzn_to_movn (uint32_t opcode
)
3595 return opcode
& ~(1 << 30);
3598 /* Overall per-instruction processing. */
3600 /* We need to be able to fix up arbitrary expressions in some statements.
3601 This is so that we can handle symbols that are an arbitrary distance from
3602 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3603 which returns part of an address in a form which will be valid for
3604 a data instruction. We do this by pushing the expression into a symbol
3605 in the expr_section, and creating a fix for that. */
3608 fix_new_aarch64 (fragS
* frag
,
3610 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3620 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3624 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3631 /* Diagnostics on operands errors. */
3633 /* By default, output verbose error message.
3634 Disable the verbose error message by -mno-verbose-error. */
3635 static int verbose_error_p
= 1;
3637 #ifdef DEBUG_AARCH64
3638 /* N.B. this is only for the purpose of debugging. */
3639 const char* operand_mismatch_kind_names
[] =
3642 "AARCH64_OPDE_RECOVERABLE",
3643 "AARCH64_OPDE_SYNTAX_ERROR",
3644 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3645 "AARCH64_OPDE_INVALID_VARIANT",
3646 "AARCH64_OPDE_OUT_OF_RANGE",
3647 "AARCH64_OPDE_UNALIGNED",
3648 "AARCH64_OPDE_REG_LIST",
3649 "AARCH64_OPDE_OTHER_ERROR",
3651 #endif /* DEBUG_AARCH64 */
3653 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3655 When multiple errors of different kinds are found in the same assembly
3656 line, only the error of the highest severity will be picked up for
3657 issuing the diagnostics. */
3659 static inline bfd_boolean
3660 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3661 enum aarch64_operand_error_kind rhs
)
3663 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3664 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3665 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3666 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3667 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3668 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3669 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3670 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3674 /* Helper routine to get the mnemonic name from the assembly instruction
3675 line; should only be called for the diagnosis purpose, as there is
3676 string copy operation involved, which may affect the runtime
3677 performance if used in elsewhere. */
3680 get_mnemonic_name (const char *str
)
3682 static char mnemonic
[32];
3685 /* Get the first 15 bytes and assume that the full name is included. */
3686 strncpy (mnemonic
, str
, 31);
3687 mnemonic
[31] = '\0';
3689 /* Scan up to the end of the mnemonic, which must end in white space,
3690 '.', or end of string. */
3691 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3696 /* Append '...' to the truncated long name. */
3697 if (ptr
- mnemonic
== 31)
3698 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3704 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3706 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3707 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3710 /* Data strutures storing one user error in the assembly code related to
3713 struct operand_error_record
3715 const aarch64_opcode
*opcode
;
3716 aarch64_operand_error detail
;
3717 struct operand_error_record
*next
;
3720 typedef struct operand_error_record operand_error_record
;
3722 struct operand_errors
3724 operand_error_record
*head
;
3725 operand_error_record
*tail
;
3728 typedef struct operand_errors operand_errors
;
3730 /* Top-level data structure reporting user errors for the current line of
3732 The way md_assemble works is that all opcodes sharing the same mnemonic
3733 name are iterated to find a match to the assembly line. In this data
3734 structure, each of the such opcodes will have one operand_error_record
3735 allocated and inserted. In other words, excessive errors related with
3736 a single opcode are disregarded. */
3737 operand_errors operand_error_report
;
3739 /* Free record nodes. */
3740 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3742 /* Initialize the data structure that stores the operand mismatch
3743 information on assembling one line of the assembly code. */
3745 init_operand_error_report (void)
3747 if (operand_error_report
.head
!= NULL
)
3749 gas_assert (operand_error_report
.tail
!= NULL
);
3750 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3751 free_opnd_error_record_nodes
= operand_error_report
.head
;
3752 operand_error_report
.head
= NULL
;
3753 operand_error_report
.tail
= NULL
;
3756 gas_assert (operand_error_report
.tail
== NULL
);
3759 /* Return TRUE if some operand error has been recorded during the
3760 parsing of the current assembly line using the opcode *OPCODE;
3761 otherwise return FALSE. */
3762 static inline bfd_boolean
3763 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3765 operand_error_record
*record
= operand_error_report
.head
;
3766 return record
&& record
->opcode
== opcode
;
3769 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3770 OPCODE field is initialized with OPCODE.
3771 N.B. only one record for each opcode, i.e. the maximum of one error is
3772 recorded for each instruction template. */
3775 add_operand_error_record (const operand_error_record
* new_record
)
3777 const aarch64_opcode
*opcode
= new_record
->opcode
;
3778 operand_error_record
* record
= operand_error_report
.head
;
3780 /* The record may have been created for this opcode. If not, we need
3782 if (! opcode_has_operand_error_p (opcode
))
3784 /* Get one empty record. */
3785 if (free_opnd_error_record_nodes
== NULL
)
3787 record
= xmalloc (sizeof (operand_error_record
));
3793 record
= free_opnd_error_record_nodes
;
3794 free_opnd_error_record_nodes
= record
->next
;
3796 record
->opcode
= opcode
;
3797 /* Insert at the head. */
3798 record
->next
= operand_error_report
.head
;
3799 operand_error_report
.head
= record
;
3800 if (operand_error_report
.tail
== NULL
)
3801 operand_error_report
.tail
= record
;
3803 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3804 && record
->detail
.index
<= new_record
->detail
.index
3805 && operand_error_higher_severity_p (record
->detail
.kind
,
3806 new_record
->detail
.kind
))
3808 /* In the case of multiple errors found on operands related with a
3809 single opcode, only record the error of the leftmost operand and
3810 only if the error is of higher severity. */
3811 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3812 " the existing error %s on operand %d",
3813 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3814 new_record
->detail
.index
,
3815 operand_mismatch_kind_names
[record
->detail
.kind
],
3816 record
->detail
.index
);
3820 record
->detail
= new_record
->detail
;
3824 record_operand_error_info (const aarch64_opcode
*opcode
,
3825 aarch64_operand_error
*error_info
)
3827 operand_error_record record
;
3828 record
.opcode
= opcode
;
3829 record
.detail
= *error_info
;
3830 add_operand_error_record (&record
);
3833 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3834 error message *ERROR, for operand IDX (count from 0). */
3837 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3838 enum aarch64_operand_error_kind kind
,
3841 aarch64_operand_error info
;
3842 memset(&info
, 0, sizeof (info
));
3846 record_operand_error_info (opcode
, &info
);
3850 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3851 enum aarch64_operand_error_kind kind
,
3852 const char* error
, const int *extra_data
)
3854 aarch64_operand_error info
;
3858 info
.data
[0] = extra_data
[0];
3859 info
.data
[1] = extra_data
[1];
3860 info
.data
[2] = extra_data
[2];
3861 record_operand_error_info (opcode
, &info
);
3865 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3866 const char* error
, int lower_bound
,
3869 int data
[3] = {lower_bound
, upper_bound
, 0};
3870 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3874 /* Remove the operand error record for *OPCODE. */
3875 static void ATTRIBUTE_UNUSED
3876 remove_operand_error_record (const aarch64_opcode
*opcode
)
3878 if (opcode_has_operand_error_p (opcode
))
3880 operand_error_record
* record
= operand_error_report
.head
;
3881 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3882 operand_error_report
.head
= record
->next
;
3883 record
->next
= free_opnd_error_record_nodes
;
3884 free_opnd_error_record_nodes
= record
;
3885 if (operand_error_report
.head
== NULL
)
3887 gas_assert (operand_error_report
.tail
== record
);
3888 operand_error_report
.tail
= NULL
;
3893 /* Given the instruction in *INSTR, return the index of the best matched
3894 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3896 Return -1 if there is no qualifier sequence; return the first match
3897 if there is multiple matches found. */
3900 find_best_match (const aarch64_inst
*instr
,
3901 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3903 int i
, num_opnds
, max_num_matched
, idx
;
3905 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3908 DEBUG_TRACE ("no operand");
3912 max_num_matched
= 0;
3915 /* For each pattern. */
3916 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3919 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3921 /* Most opcodes has much fewer patterns in the list. */
3922 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3924 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3925 if (i
!= 0 && idx
== -1)
3926 /* If nothing has been matched, return the 1st sequence. */
3931 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3932 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3935 if (num_matched
> max_num_matched
)
3937 max_num_matched
= num_matched
;
3942 DEBUG_TRACE ("return with %d", idx
);
3946 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3947 corresponding operands in *INSTR. */
3950 assign_qualifier_sequence (aarch64_inst
*instr
,
3951 const aarch64_opnd_qualifier_t
*qualifiers
)
3954 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3955 gas_assert (num_opnds
);
3956 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3957 instr
->operands
[i
].qualifier
= *qualifiers
;
3960 /* Print operands for the diagnosis purpose. */
3963 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3964 const aarch64_opnd_info
*opnds
)
3968 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3970 const size_t size
= 128;
3973 /* We regard the opcode operand info more, however we also look into
3974 the inst->operands to support the disassembling of the optional
3976 The two operand code should be the same in all cases, apart from
3977 when the operand can be optional. */
3978 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3979 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3982 /* Generate the operand string in STR. */
3983 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
3987 strcat (buf
, i
== 0 ? " " : ",");
3989 /* Append the operand string. */
3994 /* Send to stderr a string as information. */
3997 output_info (const char *format
, ...)
4003 as_where (&file
, &line
);
4007 fprintf (stderr
, "%s:%u: ", file
, line
);
4009 fprintf (stderr
, "%s: ", file
);
4011 fprintf (stderr
, _("Info: "));
4012 va_start (args
, format
);
4013 vfprintf (stderr
, format
, args
);
4015 (void) putc ('\n', stderr
);
4018 /* Output one operand error record. */
4021 output_operand_error_record (const operand_error_record
*record
, char *str
)
4023 const aarch64_operand_error
*detail
= &record
->detail
;
4024 int idx
= detail
->index
;
4025 const aarch64_opcode
*opcode
= record
->opcode
;
4026 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4027 : AARCH64_OPND_NIL
);
4029 switch (detail
->kind
)
4031 case AARCH64_OPDE_NIL
:
4035 case AARCH64_OPDE_SYNTAX_ERROR
:
4036 case AARCH64_OPDE_RECOVERABLE
:
4037 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4038 case AARCH64_OPDE_OTHER_ERROR
:
4039 /* Use the prepared error message if there is, otherwise use the
4040 operand description string to describe the error. */
4041 if (detail
->error
!= NULL
)
4044 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4046 as_bad (_("%s at operand %d -- `%s'"),
4047 detail
->error
, idx
+ 1, str
);
4051 gas_assert (idx
>= 0);
4052 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4053 aarch64_get_operand_desc (opd_code
), str
);
4057 case AARCH64_OPDE_INVALID_VARIANT
:
4058 as_bad (_("operand mismatch -- `%s'"), str
);
4059 if (verbose_error_p
)
4061 /* We will try to correct the erroneous instruction and also provide
4062 more information e.g. all other valid variants.
4064 The string representation of the corrected instruction and other
4065 valid variants are generated by
4067 1) obtaining the intermediate representation of the erroneous
4069 2) manipulating the IR, e.g. replacing the operand qualifier;
4070 3) printing out the instruction by calling the printer functions
4071 shared with the disassembler.
4073 The limitation of this method is that the exact input assembly
4074 line cannot be accurately reproduced in some cases, for example an
4075 optional operand present in the actual assembly line will be
4076 omitted in the output; likewise for the optional syntax rules,
4077 e.g. the # before the immediate. Another limitation is that the
4078 assembly symbols and relocation operations in the assembly line
4079 currently cannot be printed out in the error report. Last but not
4080 least, when there is other error(s) co-exist with this error, the
4081 'corrected' instruction may be still incorrect, e.g. given
4082 'ldnp h0,h1,[x0,#6]!'
4083 this diagnosis will provide the version:
4084 'ldnp s0,s1,[x0,#6]!'
4085 which is still not right. */
4086 size_t len
= strlen (get_mnemonic_name (str
));
4089 const size_t size
= 2048;
4091 aarch64_inst
*inst_base
= &inst
.base
;
4092 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4095 reset_aarch64_instruction (&inst
);
4096 inst_base
->opcode
= opcode
;
4098 /* Reset the error report so that there is no side effect on the
4099 following operand parsing. */
4100 init_operand_error_report ();
4103 result
= parse_operands (str
+ len
, opcode
)
4104 && programmer_friendly_fixup (&inst
);
4105 gas_assert (result
);
4106 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4108 gas_assert (!result
);
4110 /* Find the most matched qualifier sequence. */
4111 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4112 gas_assert (qlf_idx
> -1);
4114 /* Assign the qualifiers. */
4115 assign_qualifier_sequence (inst_base
,
4116 opcode
->qualifiers_list
[qlf_idx
]);
4118 /* Print the hint. */
4119 output_info (_(" did you mean this?"));
4120 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4121 print_operands (buf
, opcode
, inst_base
->operands
);
4122 output_info (_(" %s"), buf
);
4124 /* Print out other variant(s) if there is any. */
4126 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4127 output_info (_(" other valid variant(s):"));
4129 /* For each pattern. */
4130 qualifiers_list
= opcode
->qualifiers_list
;
4131 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4133 /* Most opcodes has much fewer patterns in the list.
4134 First NIL qualifier indicates the end in the list. */
4135 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4140 /* Mnemonics name. */
4141 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4143 /* Assign the qualifiers. */
4144 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4146 /* Print instruction. */
4147 print_operands (buf
, opcode
, inst_base
->operands
);
4149 output_info (_(" %s"), buf
);
4155 case AARCH64_OPDE_OUT_OF_RANGE
:
4156 if (detail
->data
[0] != detail
->data
[1])
4157 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4158 detail
->error
? detail
->error
: _("immediate value"),
4159 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4161 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4162 detail
->error
? detail
->error
: _("immediate value"),
4163 detail
->data
[0], idx
+ 1, str
);
4166 case AARCH64_OPDE_REG_LIST
:
4167 if (detail
->data
[0] == 1)
4168 as_bad (_("invalid number of registers in the list; "
4169 "only 1 register is expected at operand %d -- `%s'"),
4172 as_bad (_("invalid number of registers in the list; "
4173 "%d registers are expected at operand %d -- `%s'"),
4174 detail
->data
[0], idx
+ 1, str
);
4177 case AARCH64_OPDE_UNALIGNED
:
4178 as_bad (_("immediate value should be a multiple of "
4179 "%d at operand %d -- `%s'"),
4180 detail
->data
[0], idx
+ 1, str
);
4189 /* Process and output the error message about the operand mismatching.
4191 When this function is called, the operand error information had
4192 been collected for an assembly line and there will be multiple
4193 errors in the case of mulitple instruction templates; output the
4194 error message that most closely describes the problem. */
4197 output_operand_error_report (char *str
)
4199 int largest_error_pos
;
4200 const char *msg
= NULL
;
4201 enum aarch64_operand_error_kind kind
;
4202 operand_error_record
*curr
;
4203 operand_error_record
*head
= operand_error_report
.head
;
4204 operand_error_record
*record
= NULL
;
4206 /* No error to report. */
4210 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4212 /* Only one error. */
4213 if (head
== operand_error_report
.tail
)
4215 DEBUG_TRACE ("single opcode entry with error kind: %s",
4216 operand_mismatch_kind_names
[head
->detail
.kind
]);
4217 output_operand_error_record (head
, str
);
4221 /* Find the error kind of the highest severity. */
4222 DEBUG_TRACE ("multiple opcode entres with error kind");
4223 kind
= AARCH64_OPDE_NIL
;
4224 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4226 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4227 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4228 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4229 kind
= curr
->detail
.kind
;
4231 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4233 /* Pick up one of errors of KIND to report. */
4234 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4235 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4237 if (curr
->detail
.kind
!= kind
)
4239 /* If there are multiple errors, pick up the one with the highest
4240 mismatching operand index. In the case of multiple errors with
4241 the equally highest operand index, pick up the first one or the
4242 first one with non-NULL error message. */
4243 if (curr
->detail
.index
> largest_error_pos
4244 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4245 && curr
->detail
.error
!= NULL
))
4247 largest_error_pos
= curr
->detail
.index
;
4249 msg
= record
->detail
.error
;
4253 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4254 DEBUG_TRACE ("Pick up error kind %s to report",
4255 operand_mismatch_kind_names
[record
->detail
.kind
]);
4258 output_operand_error_record (record
, str
);
4261 /* Write an AARCH64 instruction to buf - always little-endian. */
4263 put_aarch64_insn (char *buf
, uint32_t insn
)
4265 unsigned char *where
= (unsigned char *) buf
;
4267 where
[1] = insn
>> 8;
4268 where
[2] = insn
>> 16;
4269 where
[3] = insn
>> 24;
4273 get_aarch64_insn (char *buf
)
4275 unsigned char *where
= (unsigned char *) buf
;
4277 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4282 output_inst (struct aarch64_inst
*new_inst
)
4286 to
= frag_more (INSN_SIZE
);
4288 frag_now
->tc_frag_data
.recorded
= 1;
4290 put_aarch64_insn (to
, inst
.base
.value
);
4292 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4294 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4295 INSN_SIZE
, &inst
.reloc
.exp
,
4298 DEBUG_TRACE ("Prepared relocation fix up");
4299 /* Don't check the addend value against the instruction size,
4300 that's the job of our code in md_apply_fix(). */
4301 fixp
->fx_no_overflow
= 1;
4302 if (new_inst
!= NULL
)
4303 fixp
->tc_fix_data
.inst
= new_inst
;
4304 if (aarch64_gas_internal_fixup_p ())
4306 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4307 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4308 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4312 dwarf2_emit_insn (INSN_SIZE
);
4315 /* Link together opcodes of the same name. */
4319 aarch64_opcode
*opcode
;
4320 struct templates
*next
;
4323 typedef struct templates templates
;
4326 lookup_mnemonic (const char *start
, int len
)
4328 templates
*templ
= NULL
;
4330 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4334 /* Subroutine of md_assemble, responsible for looking up the primary
4335 opcode from the mnemonic the user wrote. STR points to the
4336 beginning of the mnemonic. */
4339 opcode_lookup (char **str
)
4342 const aarch64_cond
*cond
;
4346 /* Scan up to the end of the mnemonic, which must end in white space,
4347 '.', or end of string. */
4348 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4355 inst
.cond
= COND_ALWAYS
;
4357 /* Handle a possible condition. */
4360 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4363 inst
.cond
= cond
->value
;
4377 if (inst
.cond
== COND_ALWAYS
)
4379 /* Look for unaffixed mnemonic. */
4380 return lookup_mnemonic (base
, len
);
4384 /* append ".c" to mnemonic if conditional */
4385 memcpy (condname
, base
, len
);
4386 memcpy (condname
+ len
, ".c", 2);
4389 return lookup_mnemonic (base
, len
);
4395 /* Internal helper routine converting a vector neon_type_el structure
4396 *VECTYPE to a corresponding operand qualifier. */
4398 static inline aarch64_opnd_qualifier_t
4399 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4401 /* Element size in bytes indexed by neon_el_type. */
4402 const unsigned char ele_size
[5]
4405 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4406 goto vectype_conversion_fail
;
4408 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4410 if (vectype
->defined
& NTA_HASINDEX
)
4411 /* Vector element register. */
4412 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4415 /* Vector register. */
4416 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4418 if (reg_size
!= 16 && reg_size
!= 8)
4419 goto vectype_conversion_fail
;
4420 /* The conversion is calculated based on the relation of the order of
4421 qualifiers to the vector element size and vector register size. */
4422 offset
= (vectype
->type
== NT_q
)
4423 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4424 gas_assert (offset
<= 8);
4425 return AARCH64_OPND_QLF_V_8B
+ offset
;
4428 vectype_conversion_fail
:
4429 first_error (_("bad vector arrangement type"));
4430 return AARCH64_OPND_QLF_NIL
;
4433 /* Process an optional operand that is found omitted from the assembly line.
4434 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4435 instruction's opcode entry while IDX is the index of this omitted operand.
4439 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4440 int idx
, aarch64_opnd_info
*operand
)
4442 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4443 gas_assert (optional_operand_p (opcode
, idx
));
4444 gas_assert (!operand
->present
);
4448 case AARCH64_OPND_Rd
:
4449 case AARCH64_OPND_Rn
:
4450 case AARCH64_OPND_Rm
:
4451 case AARCH64_OPND_Rt
:
4452 case AARCH64_OPND_Rt2
:
4453 case AARCH64_OPND_Rs
:
4454 case AARCH64_OPND_Ra
:
4455 case AARCH64_OPND_Rt_SYS
:
4456 case AARCH64_OPND_Rd_SP
:
4457 case AARCH64_OPND_Rn_SP
:
4458 case AARCH64_OPND_Fd
:
4459 case AARCH64_OPND_Fn
:
4460 case AARCH64_OPND_Fm
:
4461 case AARCH64_OPND_Fa
:
4462 case AARCH64_OPND_Ft
:
4463 case AARCH64_OPND_Ft2
:
4464 case AARCH64_OPND_Sd
:
4465 case AARCH64_OPND_Sn
:
4466 case AARCH64_OPND_Sm
:
4467 case AARCH64_OPND_Vd
:
4468 case AARCH64_OPND_Vn
:
4469 case AARCH64_OPND_Vm
:
4470 case AARCH64_OPND_VdD1
:
4471 case AARCH64_OPND_VnD1
:
4472 operand
->reg
.regno
= default_value
;
4475 case AARCH64_OPND_Ed
:
4476 case AARCH64_OPND_En
:
4477 case AARCH64_OPND_Em
:
4478 operand
->reglane
.regno
= default_value
;
4481 case AARCH64_OPND_IDX
:
4482 case AARCH64_OPND_BIT_NUM
:
4483 case AARCH64_OPND_IMMR
:
4484 case AARCH64_OPND_IMMS
:
4485 case AARCH64_OPND_SHLL_IMM
:
4486 case AARCH64_OPND_IMM_VLSL
:
4487 case AARCH64_OPND_IMM_VLSR
:
4488 case AARCH64_OPND_CCMP_IMM
:
4489 case AARCH64_OPND_FBITS
:
4490 case AARCH64_OPND_UIMM4
:
4491 case AARCH64_OPND_UIMM3_OP1
:
4492 case AARCH64_OPND_UIMM3_OP2
:
4493 case AARCH64_OPND_IMM
:
4494 case AARCH64_OPND_WIDTH
:
4495 case AARCH64_OPND_UIMM7
:
4496 case AARCH64_OPND_NZCV
:
4497 operand
->imm
.value
= default_value
;
4500 case AARCH64_OPND_EXCEPTION
:
4501 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4504 case AARCH64_OPND_BARRIER_ISB
:
4505 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4512 /* Process the relocation type for move wide instructions.
4513 Return TRUE on success; otherwise return FALSE. */
4516 process_movw_reloc_info (void)
4521 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4523 if (inst
.base
.opcode
->op
== OP_MOVK
)
4524 switch (inst
.reloc
.type
)
4526 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4527 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4528 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4529 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4530 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4531 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4533 (_("the specified relocation type is not allowed for MOVK"));
4539 switch (inst
.reloc
.type
)
4541 case BFD_RELOC_AARCH64_MOVW_G0
:
4542 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4543 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4544 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4545 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4548 case BFD_RELOC_AARCH64_MOVW_G1
:
4549 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4550 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4551 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4552 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4555 case BFD_RELOC_AARCH64_MOVW_G2
:
4556 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4557 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4558 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4561 set_fatal_syntax_error
4562 (_("the specified relocation type is not allowed for 32-bit "
4568 case BFD_RELOC_AARCH64_MOVW_G3
:
4571 set_fatal_syntax_error
4572 (_("the specified relocation type is not allowed for 32-bit "
4579 /* More cases should be added when more MOVW-related relocation types
4580 are supported in GAS. */
4581 gas_assert (aarch64_gas_internal_fixup_p ());
4582 /* The shift amount should have already been set by the parser. */
4585 inst
.base
.operands
[1].shifter
.amount
= shift
;
4589 /* A primitive log caculator. */
4591 static inline unsigned int
4592 get_logsz (unsigned int size
)
4594 const unsigned char ls
[16] =
4595 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4601 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4602 return ls
[size
- 1];
4605 /* Determine and return the real reloc type code for an instruction
4606 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4608 static inline bfd_reloc_code_real_type
4609 ldst_lo12_determine_real_reloc_type (void)
4612 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4613 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4615 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4616 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4617 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4618 BFD_RELOC_AARCH64_LDST128_LO12
4621 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4622 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4624 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4626 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4628 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4630 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4631 gas_assert (logsz
>= 0 && logsz
<= 4);
4633 return reloc_ldst_lo12
[logsz
];
4636 /* Check whether a register list REGINFO is valid. The registers must be
4637 numbered in increasing order (modulo 32), in increments of one or two.
4639 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4642 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4645 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4647 uint32_t i
, nb_regs
, prev_regno
, incr
;
4649 nb_regs
= 1 + (reginfo
& 0x3);
4651 prev_regno
= reginfo
& 0x1f;
4652 incr
= accept_alternate
? 2 : 1;
4654 for (i
= 1; i
< nb_regs
; ++i
)
4656 uint32_t curr_regno
;
4658 curr_regno
= reginfo
& 0x1f;
4659 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4661 prev_regno
= curr_regno
;
4667 /* Generic instruction operand parser. This does no encoding and no
4668 semantic validation; it merely squirrels values away in the inst
4669 structure. Returns TRUE or FALSE depending on whether the
4670 specified grammar matched. */
4673 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4676 char *backtrack_pos
= 0;
4677 const enum aarch64_opnd
*operands
= opcode
->operands
;
4680 skip_whitespace (str
);
4682 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4685 int isreg32
, isregzero
;
4686 int comma_skipped_p
= 0;
4687 aarch64_reg_type rtype
;
4688 struct neon_type_el vectype
;
4689 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4691 DEBUG_TRACE ("parse operand %d", i
);
4693 /* Assign the operand code. */
4694 info
->type
= operands
[i
];
4696 if (optional_operand_p (opcode
, i
))
4698 /* Remember where we are in case we need to backtrack. */
4699 gas_assert (!backtrack_pos
);
4700 backtrack_pos
= str
;
4703 /* Expect comma between operands; the backtrack mechanizm will take
4704 care of cases of omitted optional operand. */
4705 if (i
> 0 && ! skip_past_char (&str
, ','))
4707 set_syntax_error (_("comma expected between operands"));
4711 comma_skipped_p
= 1;
4713 switch (operands
[i
])
4715 case AARCH64_OPND_Rd
:
4716 case AARCH64_OPND_Rn
:
4717 case AARCH64_OPND_Rm
:
4718 case AARCH64_OPND_Rt
:
4719 case AARCH64_OPND_Rt2
:
4720 case AARCH64_OPND_Rs
:
4721 case AARCH64_OPND_Ra
:
4722 case AARCH64_OPND_Rt_SYS
:
4723 case AARCH64_OPND_PAIRREG
:
4724 po_int_reg_or_fail (1, 0);
4727 case AARCH64_OPND_Rd_SP
:
4728 case AARCH64_OPND_Rn_SP
:
4729 po_int_reg_or_fail (0, 1);
4732 case AARCH64_OPND_Rm_EXT
:
4733 case AARCH64_OPND_Rm_SFT
:
4734 po_misc_or_fail (parse_shifter_operand
4735 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4737 : SHIFTED_LOGIC_IMM
)));
4738 if (!info
->shifter
.operator_present
)
4740 /* Default to LSL if not present. Libopcodes prefers shifter
4741 kind to be explicit. */
4742 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4743 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4744 /* For Rm_EXT, libopcodes will carry out further check on whether
4745 or not stack pointer is used in the instruction (Recall that
4746 "the extend operator is not optional unless at least one of
4747 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4751 case AARCH64_OPND_Fd
:
4752 case AARCH64_OPND_Fn
:
4753 case AARCH64_OPND_Fm
:
4754 case AARCH64_OPND_Fa
:
4755 case AARCH64_OPND_Ft
:
4756 case AARCH64_OPND_Ft2
:
4757 case AARCH64_OPND_Sd
:
4758 case AARCH64_OPND_Sn
:
4759 case AARCH64_OPND_Sm
:
4760 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4761 if (val
== PARSE_FAIL
)
4763 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4766 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4768 info
->reg
.regno
= val
;
4769 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4772 case AARCH64_OPND_Vd
:
4773 case AARCH64_OPND_Vn
:
4774 case AARCH64_OPND_Vm
:
4775 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4776 if (val
== PARSE_FAIL
)
4778 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4781 if (vectype
.defined
& NTA_HASINDEX
)
4784 info
->reg
.regno
= val
;
4785 info
->qualifier
= vectype_to_qualifier (&vectype
);
4786 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4790 case AARCH64_OPND_VdD1
:
4791 case AARCH64_OPND_VnD1
:
4792 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4793 if (val
== PARSE_FAIL
)
4795 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4798 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4800 set_fatal_syntax_error
4801 (_("the top half of a 128-bit FP/SIMD register is expected"));
4804 info
->reg
.regno
= val
;
4805 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4806 here; it is correct for the purpose of encoding/decoding since
4807 only the register number is explicitly encoded in the related
4808 instructions, although this appears a bit hacky. */
4809 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4812 case AARCH64_OPND_Ed
:
4813 case AARCH64_OPND_En
:
4814 case AARCH64_OPND_Em
:
4815 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4816 if (val
== PARSE_FAIL
)
4818 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4821 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4824 info
->reglane
.regno
= val
;
4825 info
->reglane
.index
= vectype
.index
;
4826 info
->qualifier
= vectype_to_qualifier (&vectype
);
4827 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4831 case AARCH64_OPND_LVn
:
4832 case AARCH64_OPND_LVt
:
4833 case AARCH64_OPND_LVt_AL
:
4834 case AARCH64_OPND_LEt
:
4835 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4837 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4839 set_fatal_syntax_error (_("invalid register list"));
4842 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4843 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4844 if (operands
[i
] == AARCH64_OPND_LEt
)
4846 if (!(vectype
.defined
& NTA_HASINDEX
))
4848 info
->reglist
.has_index
= 1;
4849 info
->reglist
.index
= vectype
.index
;
4851 else if (!(vectype
.defined
& NTA_HASTYPE
))
4853 info
->qualifier
= vectype_to_qualifier (&vectype
);
4854 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4858 case AARCH64_OPND_Cn
:
4859 case AARCH64_OPND_Cm
:
4860 po_reg_or_fail (REG_TYPE_CN
);
4863 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4866 inst
.base
.operands
[i
].reg
.regno
= val
;
4869 case AARCH64_OPND_SHLL_IMM
:
4870 case AARCH64_OPND_IMM_VLSR
:
4871 po_imm_or_fail (1, 64);
4872 info
->imm
.value
= val
;
4875 case AARCH64_OPND_CCMP_IMM
:
4876 case AARCH64_OPND_FBITS
:
4877 case AARCH64_OPND_UIMM4
:
4878 case AARCH64_OPND_UIMM3_OP1
:
4879 case AARCH64_OPND_UIMM3_OP2
:
4880 case AARCH64_OPND_IMM_VLSL
:
4881 case AARCH64_OPND_IMM
:
4882 case AARCH64_OPND_WIDTH
:
4883 po_imm_nc_or_fail ();
4884 info
->imm
.value
= val
;
4887 case AARCH64_OPND_UIMM7
:
4888 po_imm_or_fail (0, 127);
4889 info
->imm
.value
= val
;
4892 case AARCH64_OPND_IDX
:
4893 case AARCH64_OPND_BIT_NUM
:
4894 case AARCH64_OPND_IMMR
:
4895 case AARCH64_OPND_IMMS
:
4896 po_imm_or_fail (0, 63);
4897 info
->imm
.value
= val
;
4900 case AARCH64_OPND_IMM0
:
4901 po_imm_nc_or_fail ();
4904 set_fatal_syntax_error (_("immediate zero expected"));
4907 info
->imm
.value
= 0;
4910 case AARCH64_OPND_FPIMM0
:
4913 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4914 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4915 it is probably not worth the effort to support it. */
4916 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
4917 && !(res2
= parse_constant_immediate (&str
, &val
)))
4919 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4921 info
->imm
.value
= 0;
4922 info
->imm
.is_fp
= 1;
4925 set_fatal_syntax_error (_("immediate zero expected"));
4929 case AARCH64_OPND_IMM_MOV
:
4932 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
4933 reg_name_p (str
, REG_TYPE_VN
))
4936 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4938 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4939 later. fix_mov_imm_insn will try to determine a machine
4940 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4941 message if the immediate cannot be moved by a single
4943 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4944 inst
.base
.operands
[i
].skip
= 1;
4948 case AARCH64_OPND_SIMD_IMM
:
4949 case AARCH64_OPND_SIMD_IMM_SFT
:
4950 if (! parse_big_immediate (&str
, &val
))
4952 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4954 /* need_libopcodes_p */ 1,
4957 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4958 shift, we don't check it here; we leave the checking to
4959 the libopcodes (operand_general_constraint_met_p). By
4960 doing this, we achieve better diagnostics. */
4961 if (skip_past_comma (&str
)
4962 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4964 if (!info
->shifter
.operator_present
4965 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4967 /* Default to LSL if not present. Libopcodes prefers shifter
4968 kind to be explicit. */
4969 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4970 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4974 case AARCH64_OPND_FPIMM
:
4975 case AARCH64_OPND_SIMD_FPIMM
:
4979 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
4981 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
4985 set_fatal_syntax_error (_("invalid floating-point constant"));
4988 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
4989 inst
.base
.operands
[i
].imm
.is_fp
= 1;
4993 case AARCH64_OPND_LIMM
:
4994 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4995 SHIFTED_LOGIC_IMM
));
4996 if (info
->shifter
.operator_present
)
4998 set_fatal_syntax_error
4999 (_("shift not allowed for bitmask immediate"));
5002 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5004 /* need_libopcodes_p */ 1,
5008 case AARCH64_OPND_AIMM
:
5009 if (opcode
->op
== OP_ADD
)
5010 /* ADD may have relocation types. */
5011 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5012 SHIFTED_ARITH_IMM
));
5014 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5015 SHIFTED_ARITH_IMM
));
5016 switch (inst
.reloc
.type
)
5018 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5019 info
->shifter
.amount
= 12;
5021 case BFD_RELOC_UNUSED
:
5022 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5023 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5024 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5025 inst
.reloc
.pc_rel
= 0;
5030 info
->imm
.value
= 0;
5031 if (!info
->shifter
.operator_present
)
5033 /* Default to LSL if not present. Libopcodes prefers shifter
5034 kind to be explicit. */
5035 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5036 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5040 case AARCH64_OPND_HALF
:
5042 /* #<imm16> or relocation. */
5043 int internal_fixup_p
;
5044 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5045 if (internal_fixup_p
)
5046 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5047 skip_whitespace (str
);
5048 if (skip_past_comma (&str
))
5050 /* {, LSL #<shift>} */
5051 if (! aarch64_gas_internal_fixup_p ())
5053 set_fatal_syntax_error (_("can't mix relocation modifier "
5054 "with explicit shift"));
5057 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5060 inst
.base
.operands
[i
].shifter
.amount
= 0;
5061 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5062 inst
.base
.operands
[i
].imm
.value
= 0;
5063 if (! process_movw_reloc_info ())
5068 case AARCH64_OPND_EXCEPTION
:
5069 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5070 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5072 /* need_libopcodes_p */ 0,
5076 case AARCH64_OPND_NZCV
:
5078 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5082 info
->imm
.value
= nzcv
->value
;
5085 po_imm_or_fail (0, 15);
5086 info
->imm
.value
= val
;
5090 case AARCH64_OPND_COND
:
5091 case AARCH64_OPND_COND1
:
5092 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5094 if (info
->cond
== NULL
)
5096 set_syntax_error (_("invalid condition"));
5099 else if (operands
[i
] == AARCH64_OPND_COND1
5100 && (info
->cond
->value
& 0xe) == 0xe)
5102 /* Not allow AL or NV. */
5103 set_default_error ();
5108 case AARCH64_OPND_ADDR_ADRP
:
5109 po_misc_or_fail (parse_adrp (&str
));
5110 /* Clear the value as operand needs to be relocated. */
5111 info
->imm
.value
= 0;
5114 case AARCH64_OPND_ADDR_PCREL14
:
5115 case AARCH64_OPND_ADDR_PCREL19
:
5116 case AARCH64_OPND_ADDR_PCREL21
:
5117 case AARCH64_OPND_ADDR_PCREL26
:
5118 po_misc_or_fail (parse_address_reloc (&str
, info
));
5119 if (!info
->addr
.pcrel
)
5121 set_syntax_error (_("invalid pc-relative address"));
5124 if (inst
.gen_lit_pool
5125 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5127 /* Only permit "=value" in the literal load instructions.
5128 The literal will be generated by programmer_friendly_fixup. */
5129 set_syntax_error (_("invalid use of \"=immediate\""));
5132 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5134 set_syntax_error (_("unrecognized relocation suffix"));
5137 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5139 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5140 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5144 info
->imm
.value
= 0;
5145 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5146 switch (opcode
->iclass
)
5150 /* e.g. CBZ or B.COND */
5151 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5152 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5156 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5157 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5161 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5163 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5164 : BFD_RELOC_AARCH64_JUMP26
;
5167 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5168 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5171 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5172 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5178 inst
.reloc
.pc_rel
= 1;
5182 case AARCH64_OPND_ADDR_SIMPLE
:
5183 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5184 /* [<Xn|SP>{, #<simm>}] */
5185 po_char_or_fail ('[');
5186 po_reg_or_fail (REG_TYPE_R64_SP
);
5187 /* Accept optional ", #0". */
5188 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5189 && skip_past_char (&str
, ','))
5191 skip_past_char (&str
, '#');
5192 if (! skip_past_char (&str
, '0'))
5194 set_fatal_syntax_error
5195 (_("the optional immediate offset can only be 0"));
5199 po_char_or_fail (']');
5200 info
->addr
.base_regno
= val
;
5203 case AARCH64_OPND_ADDR_REGOFF
:
5204 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5205 po_misc_or_fail (parse_address (&str
, info
, 0));
5206 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5207 || !info
->addr
.preind
|| info
->addr
.postind
5208 || info
->addr
.writeback
)
5210 set_syntax_error (_("invalid addressing mode"));
5213 if (!info
->shifter
.operator_present
)
5215 /* Default to LSL if not present. Libopcodes prefers shifter
5216 kind to be explicit. */
5217 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5218 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5220 /* Qualifier to be deduced by libopcodes. */
5223 case AARCH64_OPND_ADDR_SIMM7
:
5224 po_misc_or_fail (parse_address (&str
, info
, 0));
5225 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5226 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5228 set_syntax_error (_("invalid addressing mode"));
5231 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5233 /* need_libopcodes_p */ 1,
5237 case AARCH64_OPND_ADDR_SIMM9
:
5238 case AARCH64_OPND_ADDR_SIMM9_2
:
5239 po_misc_or_fail (parse_address_reloc (&str
, info
));
5240 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5241 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5242 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5243 && info
->addr
.writeback
))
5245 set_syntax_error (_("invalid addressing mode"));
5248 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5250 set_syntax_error (_("relocation not allowed"));
5253 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5255 /* need_libopcodes_p */ 1,
5259 case AARCH64_OPND_ADDR_UIMM12
:
5260 po_misc_or_fail (parse_address_reloc (&str
, info
));
5261 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5262 || !info
->addr
.preind
|| info
->addr
.writeback
)
5264 set_syntax_error (_("invalid addressing mode"));
5267 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5268 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5269 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5270 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5271 /* Leave qualifier to be determined by libopcodes. */
5274 case AARCH64_OPND_SIMD_ADDR_POST
:
5275 /* [<Xn|SP>], <Xm|#<amount>> */
5276 po_misc_or_fail (parse_address (&str
, info
, 1));
5277 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5279 set_syntax_error (_("invalid addressing mode"));
5282 if (!info
->addr
.offset
.is_reg
)
5284 if (inst
.reloc
.exp
.X_op
== O_constant
)
5285 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5288 set_fatal_syntax_error
5289 (_("writeback value should be an immediate constant"));
5296 case AARCH64_OPND_SYSREG
:
5297 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1))
5300 set_syntax_error (_("unknown or missing system register name"));
5303 inst
.base
.operands
[i
].sysreg
= val
;
5306 case AARCH64_OPND_PSTATEFIELD
:
5307 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0))
5310 set_syntax_error (_("unknown or missing PSTATE field name"));
5313 inst
.base
.operands
[i
].pstatefield
= val
;
5316 case AARCH64_OPND_SYSREG_IC
:
5317 inst
.base
.operands
[i
].sysins_op
=
5318 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5320 case AARCH64_OPND_SYSREG_DC
:
5321 inst
.base
.operands
[i
].sysins_op
=
5322 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5324 case AARCH64_OPND_SYSREG_AT
:
5325 inst
.base
.operands
[i
].sysins_op
=
5326 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5328 case AARCH64_OPND_SYSREG_TLBI
:
5329 inst
.base
.operands
[i
].sysins_op
=
5330 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5332 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5334 set_fatal_syntax_error ( _("unknown or missing operation name"));
5339 case AARCH64_OPND_BARRIER
:
5340 case AARCH64_OPND_BARRIER_ISB
:
5341 val
= parse_barrier (&str
);
5342 if (val
!= PARSE_FAIL
5343 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5345 /* ISB only accepts options name 'sy'. */
5347 (_("the specified option is not accepted in ISB"));
5348 /* Turn off backtrack as this optional operand is present. */
5352 /* This is an extension to accept a 0..15 immediate. */
5353 if (val
== PARSE_FAIL
)
5354 po_imm_or_fail (0, 15);
5355 info
->barrier
= aarch64_barrier_options
+ val
;
5358 case AARCH64_OPND_PRFOP
:
5359 val
= parse_pldop (&str
);
5360 /* This is an extension to accept a 0..31 immediate. */
5361 if (val
== PARSE_FAIL
)
5362 po_imm_or_fail (0, 31);
5363 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5367 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5370 /* If we get here, this operand was successfully parsed. */
5371 inst
.base
.operands
[i
].present
= 1;
5375 /* The parse routine should already have set the error, but in case
5376 not, set a default one here. */
5378 set_default_error ();
5380 if (! backtrack_pos
)
5381 goto parse_operands_return
;
5384 /* We reach here because this operand is marked as optional, and
5385 either no operand was supplied or the operand was supplied but it
5386 was syntactically incorrect. In the latter case we report an
5387 error. In the former case we perform a few more checks before
5388 dropping through to the code to insert the default operand. */
5390 char *tmp
= backtrack_pos
;
5391 char endchar
= END_OF_INSN
;
5393 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5395 skip_past_char (&tmp
, ',');
5397 if (*tmp
!= endchar
)
5398 /* The user has supplied an operand in the wrong format. */
5399 goto parse_operands_return
;
5401 /* Make sure there is not a comma before the optional operand.
5402 For example the fifth operand of 'sys' is optional:
5404 sys #0,c0,c0,#0, <--- wrong
5405 sys #0,c0,c0,#0 <--- correct. */
5406 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5408 set_fatal_syntax_error
5409 (_("unexpected comma before the omitted optional operand"));
5410 goto parse_operands_return
;
5414 /* Reaching here means we are dealing with an optional operand that is
5415 omitted from the assembly line. */
5416 gas_assert (optional_operand_p (opcode
, i
));
5418 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5420 /* Try again, skipping the optional operand at backtrack_pos. */
5421 str
= backtrack_pos
;
5424 /* Clear any error record after the omitted optional operand has been
5425 successfully handled. */
5429 /* Check if we have parsed all the operands. */
5430 if (*str
!= '\0' && ! error_p ())
5432 /* Set I to the index of the last present operand; this is
5433 for the purpose of diagnostics. */
5434 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5436 set_fatal_syntax_error
5437 (_("unexpected characters following instruction"));
5440 parse_operands_return
:
5444 DEBUG_TRACE ("parsing FAIL: %s - %s",
5445 operand_mismatch_kind_names
[get_error_kind ()],
5446 get_error_message ());
5447 /* Record the operand error properly; this is useful when there
5448 are multiple instruction templates for a mnemonic name, so that
5449 later on, we can select the error that most closely describes
5451 record_operand_error (opcode
, i
, get_error_kind (),
5452 get_error_message ());
5457 DEBUG_TRACE ("parsing SUCCESS");
5462 /* It does some fix-up to provide some programmer friendly feature while
5463 keeping the libopcodes happy, i.e. libopcodes only accepts
5464 the preferred architectural syntax.
5465 Return FALSE if there is any failure; otherwise return TRUE. */
5468 programmer_friendly_fixup (aarch64_instruction
*instr
)
5470 aarch64_inst
*base
= &instr
->base
;
5471 const aarch64_opcode
*opcode
= base
->opcode
;
5472 enum aarch64_op op
= opcode
->op
;
5473 aarch64_opnd_info
*operands
= base
->operands
;
5475 DEBUG_TRACE ("enter");
5477 switch (opcode
->iclass
)
5480 /* TBNZ Xn|Wn, #uimm6, label
5481 Test and Branch Not Zero: conditionally jumps to label if bit number
5482 uimm6 in register Xn is not zero. The bit number implies the width of
5483 the register, which may be written and should be disassembled as Wn if
5484 uimm is less than 32. */
5485 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5487 if (operands
[1].imm
.value
>= 32)
5489 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5493 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5497 /* LDR Wt, label | =value
5498 As a convenience assemblers will typically permit the notation
5499 "=value" in conjunction with the pc-relative literal load instructions
5500 to automatically place an immediate value or symbolic address in a
5501 nearby literal pool and generate a hidden label which references it.
5502 ISREG has been set to 0 in the case of =value. */
5503 if (instr
->gen_lit_pool
5504 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5506 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5507 if (op
== OP_LDRSW_LIT
)
5509 if (instr
->reloc
.exp
.X_op
!= O_constant
5510 && instr
->reloc
.exp
.X_op
!= O_big
5511 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5513 record_operand_error (opcode
, 1,
5514 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5515 _("constant expression expected"));
5518 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5520 record_operand_error (opcode
, 1,
5521 AARCH64_OPDE_OTHER_ERROR
,
5522 _("literal pool insertion failed"));
5530 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5531 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5532 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5533 A programmer-friendly assembler should accept a destination Xd in
5534 place of Wd, however that is not the preferred form for disassembly.
5536 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5537 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5538 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5539 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5544 /* In the 64-bit form, the final register operand is written as Wm
5545 for all but the (possibly omitted) UXTX/LSL and SXTX
5547 As a programmer-friendly assembler, we accept e.g.
5548 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5549 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5550 int idx
= aarch64_operand_index (opcode
->operands
,
5551 AARCH64_OPND_Rm_EXT
);
5552 gas_assert (idx
== 1 || idx
== 2);
5553 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5554 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5555 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5556 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5557 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5558 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5566 DEBUG_TRACE ("exit with SUCCESS");
5570 /* Check for loads and stores that will cause unpredictable behavior. */
5573 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5575 aarch64_inst
*base
= &instr
->base
;
5576 const aarch64_opcode
*opcode
= base
->opcode
;
5577 const aarch64_opnd_info
*opnds
= base
->operands
;
5578 switch (opcode
->iclass
)
5584 /* Loading/storing the base register is unpredictable if writeback. */
5585 if ((aarch64_get_operand_class (opnds
[0].type
)
5586 == AARCH64_OPND_CLASS_INT_REG
)
5587 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5588 && opnds
[1].addr
.base_regno
!= REG_SP
5589 && opnds
[1].addr
.writeback
)
5590 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5593 case ldstnapair_offs
:
5594 case ldstpair_indexed
:
5595 /* Loading/storing the base register is unpredictable if writeback. */
5596 if ((aarch64_get_operand_class (opnds
[0].type
)
5597 == AARCH64_OPND_CLASS_INT_REG
)
5598 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5599 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5600 && opnds
[2].addr
.base_regno
!= REG_SP
5601 && opnds
[2].addr
.writeback
)
5602 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5603 /* Load operations must load different registers. */
5604 if ((opcode
->opcode
& (1 << 22))
5605 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5606 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5613 /* A wrapper function to interface with libopcodes on encoding and
5614 record the error message if there is any.
5616 Return TRUE on success; otherwise return FALSE. */
5619 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5622 aarch64_operand_error error_info
;
5623 error_info
.kind
= AARCH64_OPDE_NIL
;
5624 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5628 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5629 record_operand_error_info (opcode
, &error_info
);
5634 #ifdef DEBUG_AARCH64
5636 dump_opcode_operands (const aarch64_opcode
*opcode
)
5639 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5641 aarch64_verbose ("\t\t opnd%d: %s", i
,
5642 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5643 ? aarch64_get_operand_name (opcode
->operands
[i
])
5644 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5648 #endif /* DEBUG_AARCH64 */
5650 /* This is the guts of the machine-dependent assembler. STR points to a
5651 machine dependent instruction. This function is supposed to emit
5652 the frags/bytes it assembles to. */
5655 md_assemble (char *str
)
5658 templates
*template;
5659 aarch64_opcode
*opcode
;
5660 aarch64_inst
*inst_base
;
5661 unsigned saved_cond
;
5663 /* Align the previous label if needed. */
5664 if (last_label_seen
!= NULL
)
5666 symbol_set_frag (last_label_seen
, frag_now
);
5667 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5668 S_SET_SEGMENT (last_label_seen
, now_seg
);
5671 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5673 DEBUG_TRACE ("\n\n");
5674 DEBUG_TRACE ("==============================");
5675 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5677 template = opcode_lookup (&p
);
5680 /* It wasn't an instruction, but it might be a register alias of
5681 the form alias .req reg directive. */
5682 if (!create_register_alias (str
, p
))
5683 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5688 skip_whitespace (p
);
5691 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5692 get_mnemonic_name (str
), str
);
5696 init_operand_error_report ();
5698 saved_cond
= inst
.cond
;
5699 reset_aarch64_instruction (&inst
);
5700 inst
.cond
= saved_cond
;
5702 /* Iterate through all opcode entries with the same mnemonic name. */
5705 opcode
= template->opcode
;
5707 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5708 #ifdef DEBUG_AARCH64
5710 dump_opcode_operands (opcode
);
5711 #endif /* DEBUG_AARCH64 */
5713 mapping_state (MAP_INSN
);
5715 inst_base
= &inst
.base
;
5716 inst_base
->opcode
= opcode
;
5718 /* Truly conditionally executed instructions, e.g. b.cond. */
5719 if (opcode
->flags
& F_COND
)
5721 gas_assert (inst
.cond
!= COND_ALWAYS
);
5722 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5723 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5725 else if (inst
.cond
!= COND_ALWAYS
)
5727 /* It shouldn't arrive here, where the assembly looks like a
5728 conditional instruction but the found opcode is unconditional. */
5733 if (parse_operands (p
, opcode
)
5734 && programmer_friendly_fixup (&inst
)
5735 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5737 /* Check that this instruction is supported for this CPU. */
5738 if (!opcode
->avariant
5739 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5741 as_bad (_("selected processor does not support `%s'"), str
);
5745 warn_unpredictable_ldst (&inst
, str
);
5747 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5748 || !inst
.reloc
.need_libopcodes_p
)
5752 /* If there is relocation generated for the instruction,
5753 store the instruction information for the future fix-up. */
5754 struct aarch64_inst
*copy
;
5755 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5756 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5758 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5764 template = template->next
;
5765 if (template != NULL
)
5767 reset_aarch64_instruction (&inst
);
5768 inst
.cond
= saved_cond
;
5771 while (template != NULL
);
5773 /* Issue the error messages if any. */
5774 output_operand_error_report (str
);
5777 /* Various frobbings of labels and their addresses. */
5780 aarch64_start_line_hook (void)
5782 last_label_seen
= NULL
;
5786 aarch64_frob_label (symbolS
* sym
)
5788 last_label_seen
= sym
;
5790 dwarf2_emit_label (sym
);
5794 aarch64_data_in_code (void)
5796 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5798 *input_line_pointer
= '/';
5799 input_line_pointer
+= 5;
5800 *input_line_pointer
= 0;
5808 aarch64_canonicalize_symbol_name (char *name
)
5812 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5813 *(name
+ len
- 5) = 0;
5818 /* Table of all register names defined by default. The user can
5819 define additional names with .req. Note that all register names
5820 should appear in both upper and lowercase variants. Some registers
5821 also have mixed-case names. */
5823 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5824 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5825 #define REGSET31(p,t) \
5826 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5827 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5828 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5829 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5830 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5831 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5832 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5833 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5834 #define REGSET(p,t) \
5835 REGSET31(p,t), REGNUM(p,31,t)
5837 /* These go into aarch64_reg_hsh hash-table. */
5838 static const reg_entry reg_names
[] = {
5839 /* Integer registers. */
5840 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5841 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5843 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5844 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5846 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5847 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5849 /* Coprocessor register numbers. */
5850 REGSET (c
, CN
), REGSET (C
, CN
),
5852 /* Floating-point single precision registers. */
5853 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5855 /* Floating-point double precision registers. */
5856 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5858 /* Floating-point half precision registers. */
5859 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5861 /* Floating-point byte precision registers. */
5862 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5864 /* Floating-point quad precision registers. */
5865 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5867 /* FP/SIMD registers. */
5868 REGSET (v
, VN
), REGSET (V
, VN
),
5883 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5884 static const asm_nzcv nzcv_names
[] = {
5885 {"nzcv", B (n
, z
, c
, v
)},
5886 {"nzcV", B (n
, z
, c
, V
)},
5887 {"nzCv", B (n
, z
, C
, v
)},
5888 {"nzCV", B (n
, z
, C
, V
)},
5889 {"nZcv", B (n
, Z
, c
, v
)},
5890 {"nZcV", B (n
, Z
, c
, V
)},
5891 {"nZCv", B (n
, Z
, C
, v
)},
5892 {"nZCV", B (n
, Z
, C
, V
)},
5893 {"Nzcv", B (N
, z
, c
, v
)},
5894 {"NzcV", B (N
, z
, c
, V
)},
5895 {"NzCv", B (N
, z
, C
, v
)},
5896 {"NzCV", B (N
, z
, C
, V
)},
5897 {"NZcv", B (N
, Z
, c
, v
)},
5898 {"NZcV", B (N
, Z
, c
, V
)},
5899 {"NZCv", B (N
, Z
, C
, v
)},
5900 {"NZCV", B (N
, Z
, C
, V
)}
5913 /* MD interface: bits in the object file. */
5915 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5916 for use in the a.out file, and stores them in the array pointed to by buf.
5917 This knows about the endian-ness of the target machine and does
5918 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5919 2 (short) and 4 (long) Floating numbers are put out as a series of
5920 LITTLENUMS (shorts, here at least). */
5923 md_number_to_chars (char *buf
, valueT val
, int n
)
5925 if (target_big_endian
)
5926 number_to_chars_bigendian (buf
, val
, n
);
5928 number_to_chars_littleendian (buf
, val
, n
);
5931 /* MD interface: Sections. */
5933 /* Estimate the size of a frag before relaxing. Assume everything fits in
5937 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5943 /* Round up a section size to the appropriate boundary. */
5946 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5951 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5952 of an rs_align_code fragment.
5954 Here we fill the frag with the appropriate info for padding the
5955 output stream. The resulting frag will consist of a fixed (fr_fix)
5956 and of a repeating (fr_var) part.
5958 The fixed content is always emitted before the repeating content and
5959 these two parts are used as follows in constructing the output:
5960 - the fixed part will be used to align to a valid instruction word
5961 boundary, in case that we start at a misaligned address; as no
5962 executable instruction can live at the misaligned location, we
5963 simply fill with zeros;
5964 - the variable part will be used to cover the remaining padding and
5965 we fill using the AArch64 NOP instruction.
5967 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
5968 enough storage space for up to 3 bytes for padding the back to a valid
5969 instruction alignment and exactly 4 bytes to store the NOP pattern. */
5972 aarch64_handle_align (fragS
* fragP
)
5974 /* NOP = d503201f */
5975 /* AArch64 instructions are always little-endian. */
5976 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5978 int bytes
, fix
, noop_size
;
5981 if (fragP
->fr_type
!= rs_align_code
)
5984 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5985 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
5988 gas_assert (fragP
->tc_frag_data
.recorded
);
5991 noop_size
= sizeof (aarch64_noop
);
5993 fix
= bytes
& (noop_size
- 1);
5997 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6001 fragP
->fr_fix
+= fix
;
6005 memcpy (p
, aarch64_noop
, noop_size
);
6006 fragP
->fr_var
= noop_size
;
6009 /* Perform target specific initialisation of a frag.
6010 Note - despite the name this initialisation is not done when the frag
6011 is created, but only when its type is assigned. A frag can be created
6012 and used a long time before its type is set, so beware of assuming that
6013 this initialisationis performed first. */
6017 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6018 int max_chars ATTRIBUTE_UNUSED
)
6022 #else /* OBJ_ELF is defined. */
6024 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6026 /* Record a mapping symbol for alignment frags. We will delete this
6027 later if the alignment ends up empty. */
6028 if (!fragP
->tc_frag_data
.recorded
)
6030 fragP
->tc_frag_data
.recorded
= 1;
6031 switch (fragP
->fr_type
)
6036 mapping_state_2 (MAP_DATA
, max_chars
);
6039 mapping_state_2 (MAP_INSN
, max_chars
);
6047 /* Initialize the DWARF-2 unwind information for this procedure. */
6050 tc_aarch64_frame_initial_instructions (void)
6052 cfi_add_CFA_def_cfa (REG_SP
, 0);
6054 #endif /* OBJ_ELF */
6056 /* Convert REGNAME to a DWARF-2 register number. */
6059 tc_aarch64_regname_to_dw2regnum (char *regname
)
6061 const reg_entry
*reg
= parse_reg (®name
);
6067 case REG_TYPE_SP_32
:
6068 case REG_TYPE_SP_64
:
6078 return reg
->number
+ 64;
6086 /* Implement DWARF2_ADDR_SIZE. */
6089 aarch64_dwarf2_addr_size (void)
6091 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6095 return bfd_arch_bits_per_address (stdoutput
) / 8;
6098 /* MD interface: Symbol and relocation handling. */
6100 /* Return the address within the segment that a PC-relative fixup is
6101 relative to. For AArch64 PC-relative fixups applied to instructions
6102 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6105 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6107 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6109 /* If this is pc-relative and we are going to emit a relocation
6110 then we just want to put out any pipeline compensation that the linker
6111 will need. Otherwise we want to use the calculated base. */
6113 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6114 || aarch64_force_relocation (fixP
)))
6117 /* AArch64 should be consistent for all pc-relative relocations. */
6118 return base
+ AARCH64_PCREL_OFFSET
;
6121 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6122 Otherwise we have no need to default values of symbols. */
6125 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6128 if (name
[0] == '_' && name
[1] == 'G'
6129 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6133 if (symbol_find (name
))
6134 as_bad (_("GOT already in the symbol table"));
6136 GOT_symbol
= symbol_new (name
, undefined_section
,
6137 (valueT
) 0, &zero_address_frag
);
6147 /* Return non-zero if the indicated VALUE has overflowed the maximum
6148 range expressible by a unsigned number with the indicated number of
6152 unsigned_overflow (valueT value
, unsigned bits
)
6155 if (bits
>= sizeof (valueT
) * 8)
6157 lim
= (valueT
) 1 << bits
;
6158 return (value
>= lim
);
6162 /* Return non-zero if the indicated VALUE has overflowed the maximum
6163 range expressible by an signed number with the indicated number of
6167 signed_overflow (offsetT value
, unsigned bits
)
6170 if (bits
>= sizeof (offsetT
) * 8)
6172 lim
= (offsetT
) 1 << (bits
- 1);
6173 return (value
< -lim
|| value
>= lim
);
6176 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6177 unsigned immediate offset load/store instruction, try to encode it as
6178 an unscaled, 9-bit, signed immediate offset load/store instruction.
6179 Return TRUE if it is successful; otherwise return FALSE.
6181 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6182 in response to the standard LDR/STR mnemonics when the immediate offset is
6183 unambiguous, i.e. when it is negative or unaligned. */
6186 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6189 enum aarch64_op new_op
;
6190 const aarch64_opcode
*new_opcode
;
6192 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6194 switch (instr
->opcode
->op
)
6196 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6197 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6198 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6199 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6200 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6201 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6202 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6203 case OP_STR_POS
: new_op
= OP_STUR
; break;
6204 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6205 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6206 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6207 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6208 default: new_op
= OP_NIL
; break;
6211 if (new_op
== OP_NIL
)
6214 new_opcode
= aarch64_get_opcode (new_op
);
6215 gas_assert (new_opcode
!= NULL
);
6217 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6218 instr
->opcode
->op
, new_opcode
->op
);
6220 aarch64_replace_opcode (instr
, new_opcode
);
6222 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6223 qualifier matching may fail because the out-of-date qualifier will
6224 prevent the operand being updated with a new and correct qualifier. */
6225 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6226 AARCH64_OPND_ADDR_SIMM9
);
6227 gas_assert (idx
== 1);
6228 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6230 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6232 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6238 /* Called by fix_insn to fix a MOV immediate alias instruction.
6240 Operand for a generic move immediate instruction, which is an alias
6241 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6242 a 32-bit/64-bit immediate value into general register. An assembler error
6243 shall result if the immediate cannot be created by a single one of these
6244 instructions. If there is a choice, then to ensure reversability an
6245 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6248 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6250 const aarch64_opcode
*opcode
;
6252 /* Need to check if the destination is SP/ZR. The check has to be done
6253 before any aarch64_replace_opcode. */
6254 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6255 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6257 instr
->operands
[1].imm
.value
= value
;
6258 instr
->operands
[1].skip
= 0;
6262 /* Try the MOVZ alias. */
6263 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6264 aarch64_replace_opcode (instr
, opcode
);
6265 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6266 &instr
->value
, NULL
, NULL
))
6268 put_aarch64_insn (buf
, instr
->value
);
6271 /* Try the MOVK alias. */
6272 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6273 aarch64_replace_opcode (instr
, opcode
);
6274 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6275 &instr
->value
, NULL
, NULL
))
6277 put_aarch64_insn (buf
, instr
->value
);
6282 if (try_mov_bitmask_p
)
6284 /* Try the ORR alias. */
6285 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6286 aarch64_replace_opcode (instr
, opcode
);
6287 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6288 &instr
->value
, NULL
, NULL
))
6290 put_aarch64_insn (buf
, instr
->value
);
6295 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6296 _("immediate cannot be moved by a single instruction"));
6299 /* An instruction operand which is immediate related may have symbol used
6300 in the assembly, e.g.
6303 .set u32, 0x00ffff00
6305 At the time when the assembly instruction is parsed, a referenced symbol,
6306 like 'u32' in the above example may not have been seen; a fixS is created
6307 in such a case and is handled here after symbols have been resolved.
6308 Instruction is fixed up with VALUE using the information in *FIXP plus
6309 extra information in FLAGS.
6311 This function is called by md_apply_fix to fix up instructions that need
6312 a fix-up described above but does not involve any linker-time relocation. */
6315 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6319 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6320 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6321 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6325 /* Now the instruction is about to be fixed-up, so the operand that
6326 was previously marked as 'ignored' needs to be unmarked in order
6327 to get the encoding done properly. */
6328 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6329 new_inst
->operands
[idx
].skip
= 0;
6332 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6336 case AARCH64_OPND_EXCEPTION
:
6337 if (unsigned_overflow (value
, 16))
6338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6339 _("immediate out of range"));
6340 insn
= get_aarch64_insn (buf
);
6341 insn
|= encode_svc_imm (value
);
6342 put_aarch64_insn (buf
, insn
);
6345 case AARCH64_OPND_AIMM
:
6346 /* ADD or SUB with immediate.
6347 NOTE this assumes we come here with a add/sub shifted reg encoding
6348 3 322|2222|2 2 2 21111 111111
6349 1 098|7654|3 2 1 09876 543210 98765 43210
6350 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6351 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6352 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6353 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6355 3 322|2222|2 2 221111111111
6356 1 098|7654|3 2 109876543210 98765 43210
6357 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6358 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6359 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6360 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6361 Fields sf Rn Rd are already set. */
6362 insn
= get_aarch64_insn (buf
);
6366 insn
= reencode_addsub_switch_add_sub (insn
);
6370 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6371 && unsigned_overflow (value
, 12))
6373 /* Try to shift the value by 12 to make it fit. */
6374 if (((value
>> 12) << 12) == value
6375 && ! unsigned_overflow (value
, 12 + 12))
6378 insn
|= encode_addsub_imm_shift_amount (1);
6382 if (unsigned_overflow (value
, 12))
6383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6384 _("immediate out of range"));
6386 insn
|= encode_addsub_imm (value
);
6388 put_aarch64_insn (buf
, insn
);
6391 case AARCH64_OPND_SIMD_IMM
:
6392 case AARCH64_OPND_SIMD_IMM_SFT
:
6393 case AARCH64_OPND_LIMM
:
6394 /* Bit mask immediate. */
6395 gas_assert (new_inst
!= NULL
);
6396 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6397 new_inst
->operands
[idx
].imm
.value
= value
;
6398 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6399 &new_inst
->value
, NULL
, NULL
))
6400 put_aarch64_insn (buf
, new_inst
->value
);
6402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6403 _("invalid immediate"));
6406 case AARCH64_OPND_HALF
:
6407 /* 16-bit unsigned immediate. */
6408 if (unsigned_overflow (value
, 16))
6409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6410 _("immediate out of range"));
6411 insn
= get_aarch64_insn (buf
);
6412 insn
|= encode_movw_imm (value
& 0xffff);
6413 put_aarch64_insn (buf
, insn
);
6416 case AARCH64_OPND_IMM_MOV
:
6417 /* Operand for a generic move immediate instruction, which is
6418 an alias instruction that generates a single MOVZ, MOVN or ORR
6419 instruction to loads a 32-bit/64-bit immediate value into general
6420 register. An assembler error shall result if the immediate cannot be
6421 created by a single one of these instructions. If there is a choice,
6422 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6423 and MOVZ or MOVN to ORR. */
6424 gas_assert (new_inst
!= NULL
);
6425 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6428 case AARCH64_OPND_ADDR_SIMM7
:
6429 case AARCH64_OPND_ADDR_SIMM9
:
6430 case AARCH64_OPND_ADDR_SIMM9_2
:
6431 case AARCH64_OPND_ADDR_UIMM12
:
6432 /* Immediate offset in an address. */
6433 insn
= get_aarch64_insn (buf
);
6435 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6436 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6437 || new_inst
->opcode
->operands
[2] == opnd
);
6439 /* Get the index of the address operand. */
6440 if (new_inst
->opcode
->operands
[1] == opnd
)
6441 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6444 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6447 /* Update the resolved offset value. */
6448 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6450 /* Encode/fix-up. */
6451 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6452 &new_inst
->value
, NULL
, NULL
))
6454 put_aarch64_insn (buf
, new_inst
->value
);
6457 else if (new_inst
->opcode
->iclass
== ldst_pos
6458 && try_to_encode_as_unscaled_ldst (new_inst
))
6460 put_aarch64_insn (buf
, new_inst
->value
);
6464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6465 _("immediate offset out of range"));
6470 as_fatal (_("unhandled operand code %d"), opnd
);
6474 /* Apply a fixup (fixP) to segment data, once it has been determined
6475 by our caller that we have all the info we need to fix it up.
6477 Parameter valP is the pointer to the value of the bits. */
6480 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6482 offsetT value
= *valP
;
6484 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6486 unsigned flags
= fixP
->fx_addnumber
;
6488 DEBUG_TRACE ("\n\n");
6489 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6490 DEBUG_TRACE ("Enter md_apply_fix");
6492 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6494 /* Note whether this will delete the relocation. */
6496 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6499 /* Process the relocations. */
6500 switch (fixP
->fx_r_type
)
6502 case BFD_RELOC_NONE
:
6503 /* This will need to go in the object file. */
6508 case BFD_RELOC_8_PCREL
:
6509 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6510 md_number_to_chars (buf
, value
, 1);
6514 case BFD_RELOC_16_PCREL
:
6515 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6516 md_number_to_chars (buf
, value
, 2);
6520 case BFD_RELOC_32_PCREL
:
6521 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6522 md_number_to_chars (buf
, value
, 4);
6526 case BFD_RELOC_64_PCREL
:
6527 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6528 md_number_to_chars (buf
, value
, 8);
6531 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6532 /* We claim that these fixups have been processed here, even if
6533 in fact we generate an error because we do not have a reloc
6534 for them, so tc_gen_reloc() will reject them. */
6536 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6539 _("undefined symbol %s used as an immediate value"),
6540 S_GET_NAME (fixP
->fx_addsy
));
6541 goto apply_fix_return
;
6543 fix_insn (fixP
, flags
, value
);
6546 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6547 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6551 _("pc-relative load offset not word aligned"));
6552 if (signed_overflow (value
, 21))
6553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6554 _("pc-relative load offset out of range"));
6555 insn
= get_aarch64_insn (buf
);
6556 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6557 put_aarch64_insn (buf
, insn
);
6561 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6562 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6564 if (signed_overflow (value
, 21))
6565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6566 _("pc-relative address offset out of range"));
6567 insn
= get_aarch64_insn (buf
);
6568 insn
|= encode_adr_imm (value
);
6569 put_aarch64_insn (buf
, insn
);
6573 case BFD_RELOC_AARCH64_BRANCH19
:
6574 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6578 _("conditional branch target not word aligned"));
6579 if (signed_overflow (value
, 21))
6580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6581 _("conditional branch out of range"));
6582 insn
= get_aarch64_insn (buf
);
6583 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6584 put_aarch64_insn (buf
, insn
);
6588 case BFD_RELOC_AARCH64_TSTBR14
:
6589 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6593 _("conditional branch target not word aligned"));
6594 if (signed_overflow (value
, 16))
6595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6596 _("conditional branch out of range"));
6597 insn
= get_aarch64_insn (buf
);
6598 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6599 put_aarch64_insn (buf
, insn
);
6603 case BFD_RELOC_AARCH64_JUMP26
:
6604 case BFD_RELOC_AARCH64_CALL26
:
6605 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6609 _("branch target not word aligned"));
6610 if (signed_overflow (value
, 28))
6611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6612 _("branch out of range"));
6613 insn
= get_aarch64_insn (buf
);
6614 insn
|= encode_branch_ofs_26 (value
>> 2);
6615 put_aarch64_insn (buf
, insn
);
6619 case BFD_RELOC_AARCH64_MOVW_G0
:
6620 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6621 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6624 case BFD_RELOC_AARCH64_MOVW_G1
:
6625 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6626 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6629 case BFD_RELOC_AARCH64_MOVW_G2
:
6630 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6631 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6634 case BFD_RELOC_AARCH64_MOVW_G3
:
6637 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6639 insn
= get_aarch64_insn (buf
);
6643 /* REL signed addend must fit in 16 bits */
6644 if (signed_overflow (value
, 16))
6645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6646 _("offset out of range"));
6650 /* Check for overflow and scale. */
6651 switch (fixP
->fx_r_type
)
6653 case BFD_RELOC_AARCH64_MOVW_G0
:
6654 case BFD_RELOC_AARCH64_MOVW_G1
:
6655 case BFD_RELOC_AARCH64_MOVW_G2
:
6656 case BFD_RELOC_AARCH64_MOVW_G3
:
6657 if (unsigned_overflow (value
, scale
+ 16))
6658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6659 _("unsigned value out of range"));
6661 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6662 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6663 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6664 /* NOTE: We can only come here with movz or movn. */
6665 if (signed_overflow (value
, scale
+ 16))
6666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6667 _("signed value out of range"));
6670 /* Force use of MOVN. */
6672 insn
= reencode_movzn_to_movn (insn
);
6676 /* Force use of MOVZ. */
6677 insn
= reencode_movzn_to_movz (insn
);
6681 /* Unchecked relocations. */
6687 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6688 insn
|= encode_movw_imm (value
& 0xffff);
6690 put_aarch64_insn (buf
, insn
);
6694 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6695 fixP
->fx_r_type
= (ilp32_p
6696 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6697 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6698 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6699 /* Should always be exported to object file, see
6700 aarch64_force_relocation(). */
6701 gas_assert (!fixP
->fx_done
);
6702 gas_assert (seg
->use_rela_p
);
6705 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6706 fixP
->fx_r_type
= (ilp32_p
6707 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6708 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6709 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6710 /* Should always be exported to object file, see
6711 aarch64_force_relocation(). */
6712 gas_assert (!fixP
->fx_done
);
6713 gas_assert (seg
->use_rela_p
);
6716 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6717 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6718 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6719 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6720 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6721 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6722 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6723 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6724 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6725 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6726 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6727 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6728 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6729 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6730 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6731 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6732 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6733 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6734 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6735 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6736 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6737 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6738 /* Should always be exported to object file, see
6739 aarch64_force_relocation(). */
6740 gas_assert (!fixP
->fx_done
);
6741 gas_assert (seg
->use_rela_p
);
6744 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6745 /* Should always be exported to object file, see
6746 aarch64_force_relocation(). */
6747 fixP
->fx_r_type
= (ilp32_p
6748 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6749 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6750 gas_assert (!fixP
->fx_done
);
6751 gas_assert (seg
->use_rela_p
);
6754 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6755 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6756 case BFD_RELOC_AARCH64_ADD_LO12
:
6757 case BFD_RELOC_AARCH64_LDST8_LO12
:
6758 case BFD_RELOC_AARCH64_LDST16_LO12
:
6759 case BFD_RELOC_AARCH64_LDST32_LO12
:
6760 case BFD_RELOC_AARCH64_LDST64_LO12
:
6761 case BFD_RELOC_AARCH64_LDST128_LO12
:
6762 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6763 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6764 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6765 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6766 /* Should always be exported to object file, see
6767 aarch64_force_relocation(). */
6768 gas_assert (!fixP
->fx_done
);
6769 gas_assert (seg
->use_rela_p
);
6772 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6773 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6774 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6777 case BFD_RELOC_UNUSED
:
6778 /* An error will already have been reported. */
6782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6783 _("unexpected %s fixup"),
6784 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6789 /* Free the allocated the struct aarch64_inst.
6790 N.B. currently there are very limited number of fix-up types actually use
6791 this field, so the impact on the performance should be minimal . */
6792 if (fixP
->tc_fix_data
.inst
!= NULL
)
6793 free (fixP
->tc_fix_data
.inst
);
6798 /* Translate internal representation of relocation info to BFD target
6802 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6805 bfd_reloc_code_real_type code
;
6807 reloc
= xmalloc (sizeof (arelent
));
6809 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6810 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6811 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6815 if (section
->use_rela_p
)
6816 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6818 fixp
->fx_offset
= reloc
->address
;
6820 reloc
->addend
= fixp
->fx_offset
;
6822 code
= fixp
->fx_r_type
;
6827 code
= BFD_RELOC_16_PCREL
;
6832 code
= BFD_RELOC_32_PCREL
;
6837 code
= BFD_RELOC_64_PCREL
;
6844 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6845 if (reloc
->howto
== NULL
)
6847 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6849 ("cannot represent %s relocation in this object file format"),
6850 bfd_get_reloc_code_name (code
));
6857 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6860 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6862 bfd_reloc_code_real_type type
;
6866 FIXME: @@ Should look at CPU word size. */
6873 type
= BFD_RELOC_16
;
6876 type
= BFD_RELOC_32
;
6879 type
= BFD_RELOC_64
;
6882 as_bad (_("cannot do %u-byte relocation"), size
);
6883 type
= BFD_RELOC_UNUSED
;
6887 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6891 aarch64_force_relocation (struct fix
*fixp
)
6893 switch (fixp
->fx_r_type
)
6895 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6896 /* Perform these "immediate" internal relocations
6897 even if the symbol is extern or weak. */
6900 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6901 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6902 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6903 /* Pseudo relocs that need to be fixed up according to
6907 case BFD_RELOC_AARCH64_ADD_LO12
:
6908 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6909 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6910 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6911 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6912 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6913 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6914 case BFD_RELOC_AARCH64_LDST128_LO12
:
6915 case BFD_RELOC_AARCH64_LDST16_LO12
:
6916 case BFD_RELOC_AARCH64_LDST32_LO12
:
6917 case BFD_RELOC_AARCH64_LDST64_LO12
:
6918 case BFD_RELOC_AARCH64_LDST8_LO12
:
6919 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6920 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6921 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6922 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6923 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6924 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6925 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6926 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6927 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6928 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6929 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6930 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6931 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6932 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6933 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6934 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6935 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6936 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6937 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6938 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6939 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6940 /* Always leave these relocations for the linker. */
6947 return generic_force_reloc (fixp
);
6953 elf64_aarch64_target_format (void)
6955 if (target_big_endian
)
6956 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
6958 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
6962 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
6964 elf_frob_symbol (symp
, puntp
);
6968 /* MD interface: Finalization. */
6970 /* A good place to do this, although this was probably not intended
6971 for this kind of use. We need to dump the literal pool before
6972 references are made to a null symbol pointer. */
6975 aarch64_cleanup (void)
6979 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
6981 /* Put it at the end of the relevant section. */
6982 subseg_set (pool
->section
, pool
->sub_section
);
6988 /* Remove any excess mapping symbols generated for alignment frags in
6989 SEC. We may have created a mapping symbol before a zero byte
6990 alignment; remove it if there's a mapping symbol after the
6993 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
6994 void *dummy ATTRIBUTE_UNUSED
)
6996 segment_info_type
*seginfo
= seg_info (sec
);
6999 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7002 for (fragp
= seginfo
->frchainP
->frch_root
;
7003 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7005 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7006 fragS
*next
= fragp
->fr_next
;
7008 /* Variable-sized frags have been converted to fixed size by
7009 this point. But if this was variable-sized to start with,
7010 there will be a fixed-size frag after it. So don't handle
7012 if (sym
== NULL
|| next
== NULL
)
7015 if (S_GET_VALUE (sym
) < next
->fr_address
)
7016 /* Not at the end of this frag. */
7018 know (S_GET_VALUE (sym
) == next
->fr_address
);
7022 if (next
->tc_frag_data
.first_map
!= NULL
)
7024 /* Next frag starts with a mapping symbol. Discard this
7026 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7030 if (next
->fr_next
== NULL
)
7032 /* This mapping symbol is at the end of the section. Discard
7034 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7035 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7039 /* As long as we have empty frags without any mapping symbols,
7041 /* If the next frag is non-empty and does not start with a
7042 mapping symbol, then this mapping symbol is required. */
7043 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7046 next
= next
->fr_next
;
7048 while (next
!= NULL
);
7053 /* Adjust the symbol table. */
7056 aarch64_adjust_symtab (void)
7059 /* Remove any overlapping mapping symbols generated by alignment frags. */
7060 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7061 /* Now do generic ELF adjustments. */
7062 elf_adjust_symtab ();
7067 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7069 const char *hash_err
;
7071 hash_err
= hash_insert (table
, key
, value
);
7073 printf ("Internal Error: Can't hash %s\n", key
);
7077 fill_instruction_hash_table (void)
7079 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7081 while (opcode
->name
!= NULL
)
7083 templates
*templ
, *new_templ
;
7084 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7086 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7087 new_templ
->opcode
= opcode
;
7088 new_templ
->next
= NULL
;
7091 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7094 new_templ
->next
= templ
->next
;
7095 templ
->next
= new_templ
;
7102 convert_to_upper (char *dst
, const char *src
, size_t num
)
7105 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7106 *dst
= TOUPPER (*src
);
7110 /* Assume STR point to a lower-case string, allocate, convert and return
7111 the corresponding upper-case string. */
7112 static inline const char*
7113 get_upper_str (const char *str
)
7116 size_t len
= strlen (str
);
7117 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7119 convert_to_upper (ret
, str
, len
);
7123 /* MD interface: Initialization. */
7131 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7132 || (aarch64_cond_hsh
= hash_new ()) == NULL
7133 || (aarch64_shift_hsh
= hash_new ()) == NULL
7134 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7135 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7136 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7137 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7138 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7139 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7140 || (aarch64_reg_hsh
= hash_new ()) == NULL
7141 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7142 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7143 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7144 as_fatal (_("virtual memory exhausted"));
7146 fill_instruction_hash_table ();
7148 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7149 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7150 (void *) (aarch64_sys_regs
+ i
));
7152 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7153 checked_hash_insert (aarch64_pstatefield_hsh
,
7154 aarch64_pstatefields
[i
].name
,
7155 (void *) (aarch64_pstatefields
+ i
));
7157 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7158 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7159 aarch64_sys_regs_ic
[i
].template,
7160 (void *) (aarch64_sys_regs_ic
+ i
));
7162 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7163 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7164 aarch64_sys_regs_dc
[i
].template,
7165 (void *) (aarch64_sys_regs_dc
+ i
));
7167 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7168 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7169 aarch64_sys_regs_at
[i
].template,
7170 (void *) (aarch64_sys_regs_at
+ i
));
7172 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7173 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7174 aarch64_sys_regs_tlbi
[i
].template,
7175 (void *) (aarch64_sys_regs_tlbi
+ i
));
7177 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7178 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7179 (void *) (reg_names
+ i
));
7181 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7182 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7183 (void *) (nzcv_names
+ i
));
7185 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7187 const char *name
= aarch64_operand_modifiers
[i
].name
;
7188 checked_hash_insert (aarch64_shift_hsh
, name
,
7189 (void *) (aarch64_operand_modifiers
+ i
));
7190 /* Also hash the name in the upper case. */
7191 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7192 (void *) (aarch64_operand_modifiers
+ i
));
7195 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7198 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7199 the same condition code. */
7200 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7202 const char *name
= aarch64_conds
[i
].names
[j
];
7205 checked_hash_insert (aarch64_cond_hsh
, name
,
7206 (void *) (aarch64_conds
+ i
));
7207 /* Also hash the name in the upper case. */
7208 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7209 (void *) (aarch64_conds
+ i
));
7213 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7215 const char *name
= aarch64_barrier_options
[i
].name
;
7216 /* Skip xx00 - the unallocated values of option. */
7219 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7220 (void *) (aarch64_barrier_options
+ i
));
7221 /* Also hash the name in the upper case. */
7222 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7223 (void *) (aarch64_barrier_options
+ i
));
7226 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7228 const char* name
= aarch64_prfops
[i
].name
;
7229 /* Skip the unallocated hint encodings. */
7232 checked_hash_insert (aarch64_pldop_hsh
, name
,
7233 (void *) (aarch64_prfops
+ i
));
7234 /* Also hash the name in the upper case. */
7235 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7236 (void *) (aarch64_prfops
+ i
));
7239 /* Set the cpu variant based on the command-line options. */
7241 mcpu_cpu_opt
= march_cpu_opt
;
7244 mcpu_cpu_opt
= &cpu_default
;
7246 cpu_variant
= *mcpu_cpu_opt
;
7248 /* Record the CPU type. */
7249 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7251 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7254 /* Command line processing. */
7256 const char *md_shortopts
= "m:";
7258 #ifdef AARCH64_BI_ENDIAN
7259 #define OPTION_EB (OPTION_MD_BASE + 0)
7260 #define OPTION_EL (OPTION_MD_BASE + 1)
7262 #if TARGET_BYTES_BIG_ENDIAN
7263 #define OPTION_EB (OPTION_MD_BASE + 0)
7265 #define OPTION_EL (OPTION_MD_BASE + 1)
7269 struct option md_longopts
[] = {
7271 {"EB", no_argument
, NULL
, OPTION_EB
},
7274 {"EL", no_argument
, NULL
, OPTION_EL
},
7276 {NULL
, no_argument
, NULL
, 0}
7279 size_t md_longopts_size
= sizeof (md_longopts
);
7281 struct aarch64_option_table
7283 char *option
; /* Option name to match. */
7284 char *help
; /* Help information. */
7285 int *var
; /* Variable to change. */
7286 int value
; /* What to change it to. */
7287 char *deprecated
; /* If non-null, print this message. */
7290 static struct aarch64_option_table aarch64_opts
[] = {
7291 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7292 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7294 #ifdef DEBUG_AARCH64
7295 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7296 #endif /* DEBUG_AARCH64 */
7297 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7299 {"mno-verbose-error", N_("do not output verbose error messages"),
7300 &verbose_error_p
, 0, NULL
},
7301 {NULL
, NULL
, NULL
, 0, NULL
}
7304 struct aarch64_cpu_option_table
7307 const aarch64_feature_set value
;
7308 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7310 const char *canonical_name
;
7313 /* This list should, at a minimum, contain all the cpu names
7314 recognized by GCC. */
7315 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7316 {"all", AARCH64_ANY
, NULL
},
7317 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7318 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7319 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7320 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7321 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7322 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7323 {"thunderx", AARCH64_ARCH_V8
, "Cavium ThunderX"},
7324 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7325 in earlier releases and is superseded by 'xgene1' in all
7327 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7328 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7329 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7330 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7331 {"generic", AARCH64_ARCH_V8
, NULL
},
7333 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7336 struct aarch64_arch_option_table
7339 const aarch64_feature_set value
;
7342 /* This list should, at a minimum, contain all the architecture names
7343 recognized by GCC. */
7344 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7345 {"all", AARCH64_ANY
},
7346 {"armv8-a", AARCH64_ARCH_V8
},
7347 {NULL
, AARCH64_ARCH_NONE
}
7350 /* ISA extensions. */
7351 struct aarch64_option_cpu_value_table
7354 const aarch64_feature_set value
;
7357 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7358 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7359 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7360 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7361 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7362 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7363 {NULL
, AARCH64_ARCH_NONE
}
7366 struct aarch64_long_option_table
7368 char *option
; /* Substring to match. */
7369 char *help
; /* Help information. */
7370 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7371 char *deprecated
; /* If non-null, print this message. */
7375 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7376 bfd_boolean ext_only
)
7378 /* We insist on extensions being added before being removed. We achieve
7379 this by using the ADDING_VALUE variable to indicate whether we are
7380 adding an extension (1) or removing it (0) and only allowing it to
7381 change in the order -1 -> 1 -> 0. */
7382 int adding_value
= -1;
7383 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7385 /* Copy the feature set, so that we can modify it. */
7389 while (str
!= NULL
&& *str
!= 0)
7391 const struct aarch64_option_cpu_value_table
*opt
;
7399 as_bad (_("invalid architectural extension"));
7403 ext
= strchr (++str
, '+');
7409 optlen
= strlen (str
);
7411 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7413 if (adding_value
!= 0)
7418 else if (optlen
> 0)
7420 if (adding_value
== -1)
7422 else if (adding_value
!= 1)
7424 as_bad (_("must specify extensions to add before specifying "
7425 "those to remove"));
7432 as_bad (_("missing architectural extension"));
7436 gas_assert (adding_value
!= -1);
7438 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7439 if (strncmp (opt
->name
, str
, optlen
) == 0)
7441 /* Add or remove the extension. */
7443 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7445 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7449 if (opt
->name
== NULL
)
7451 as_bad (_("unknown architectural extension `%s'"), str
);
7462 aarch64_parse_cpu (char *str
)
7464 const struct aarch64_cpu_option_table
*opt
;
7465 char *ext
= strchr (str
, '+');
7471 optlen
= strlen (str
);
7475 as_bad (_("missing cpu name `%s'"), str
);
7479 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7480 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7482 mcpu_cpu_opt
= &opt
->value
;
7484 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7489 as_bad (_("unknown cpu `%s'"), str
);
7494 aarch64_parse_arch (char *str
)
7496 const struct aarch64_arch_option_table
*opt
;
7497 char *ext
= strchr (str
, '+');
7503 optlen
= strlen (str
);
7507 as_bad (_("missing architecture name `%s'"), str
);
7511 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7512 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7514 march_cpu_opt
= &opt
->value
;
7516 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7521 as_bad (_("unknown architecture `%s'\n"), str
);
7526 struct aarch64_option_abi_value_table
7529 enum aarch64_abi_type value
;
7532 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7533 {"ilp32", AARCH64_ABI_ILP32
},
7534 {"lp64", AARCH64_ABI_LP64
},
7539 aarch64_parse_abi (char *str
)
7541 const struct aarch64_option_abi_value_table
*opt
;
7542 size_t optlen
= strlen (str
);
7546 as_bad (_("missing abi name `%s'"), str
);
7550 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7551 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7553 aarch64_abi
= opt
->value
;
7557 as_bad (_("unknown abi `%s'\n"), str
);
7561 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7563 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7564 aarch64_parse_abi
, NULL
},
7565 #endif /* OBJ_ELF */
7566 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7567 aarch64_parse_cpu
, NULL
},
7568 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7569 aarch64_parse_arch
, NULL
},
7570 {NULL
, NULL
, 0, NULL
}
7574 md_parse_option (int c
, char *arg
)
7576 struct aarch64_option_table
*opt
;
7577 struct aarch64_long_option_table
*lopt
;
7583 target_big_endian
= 1;
7589 target_big_endian
= 0;
7594 /* Listing option. Just ignore these, we don't support additional
7599 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7601 if (c
== opt
->option
[0]
7602 && ((arg
== NULL
&& opt
->option
[1] == 0)
7603 || streq (arg
, opt
->option
+ 1)))
7605 /* If the option is deprecated, tell the user. */
7606 if (opt
->deprecated
!= NULL
)
7607 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7608 arg
? arg
: "", _(opt
->deprecated
));
7610 if (opt
->var
!= NULL
)
7611 *opt
->var
= opt
->value
;
7617 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7619 /* These options are expected to have an argument. */
7620 if (c
== lopt
->option
[0]
7622 && strncmp (arg
, lopt
->option
+ 1,
7623 strlen (lopt
->option
+ 1)) == 0)
7625 /* If the option is deprecated, tell the user. */
7626 if (lopt
->deprecated
!= NULL
)
7627 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7628 _(lopt
->deprecated
));
7630 /* Call the sup-option parser. */
7631 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7642 md_show_usage (FILE * fp
)
7644 struct aarch64_option_table
*opt
;
7645 struct aarch64_long_option_table
*lopt
;
7647 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7649 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7650 if (opt
->help
!= NULL
)
7651 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7653 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7654 if (lopt
->help
!= NULL
)
7655 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7659 -EB assemble code for a big-endian cpu\n"));
7664 -EL assemble code for a little-endian cpu\n"));
7668 /* Parse a .cpu directive. */
7671 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7673 const struct aarch64_cpu_option_table
*opt
;
7679 name
= input_line_pointer
;
7680 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7681 input_line_pointer
++;
7682 saved_char
= *input_line_pointer
;
7683 *input_line_pointer
= 0;
7685 ext
= strchr (name
, '+');
7688 optlen
= ext
- name
;
7690 optlen
= strlen (name
);
7692 /* Skip the first "all" entry. */
7693 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7694 if (strlen (opt
->name
) == optlen
7695 && strncmp (name
, opt
->name
, optlen
) == 0)
7697 mcpu_cpu_opt
= &opt
->value
;
7699 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7702 cpu_variant
= *mcpu_cpu_opt
;
7704 *input_line_pointer
= saved_char
;
7705 demand_empty_rest_of_line ();
7708 as_bad (_("unknown cpu `%s'"), name
);
7709 *input_line_pointer
= saved_char
;
7710 ignore_rest_of_line ();
7714 /* Parse a .arch directive. */
7717 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7719 const struct aarch64_arch_option_table
*opt
;
7725 name
= input_line_pointer
;
7726 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7727 input_line_pointer
++;
7728 saved_char
= *input_line_pointer
;
7729 *input_line_pointer
= 0;
7731 ext
= strchr (name
, '+');
7734 optlen
= ext
- name
;
7736 optlen
= strlen (name
);
7738 /* Skip the first "all" entry. */
7739 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7740 if (strlen (opt
->name
) == optlen
7741 && strncmp (name
, opt
->name
, optlen
) == 0)
7743 mcpu_cpu_opt
= &opt
->value
;
7745 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7748 cpu_variant
= *mcpu_cpu_opt
;
7750 *input_line_pointer
= saved_char
;
7751 demand_empty_rest_of_line ();
7755 as_bad (_("unknown architecture `%s'\n"), name
);
7756 *input_line_pointer
= saved_char
;
7757 ignore_rest_of_line ();
7760 /* Parse a .arch_extension directive. */
7763 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
7766 char *ext
= input_line_pointer
;;
7768 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7769 input_line_pointer
++;
7770 saved_char
= *input_line_pointer
;
7771 *input_line_pointer
= 0;
7773 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
7776 cpu_variant
= *mcpu_cpu_opt
;
7778 *input_line_pointer
= saved_char
;
7779 demand_empty_rest_of_line ();
7782 /* Copy symbol information. */
7785 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7787 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);