1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in vector_type_el. */
93 #define NTA_HASINDEX 2
94 #define NTA_HASVARWIDTH 4
98 enum vector_el_type type
;
99 unsigned char defined
;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type
;
111 enum aarch64_opnd opnd
;
113 unsigned need_libopcodes_p
: 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind
;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool
: 1;
134 typedef struct aarch64_instruction aarch64_instruction
;
136 static aarch64_instruction inst
;
138 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
139 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
162 inst
.parsing_error
.error
= NULL
;
165 static inline bfd_boolean
168 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
171 static inline const char *
172 get_error_message (void)
174 return inst
.parsing_error
.error
;
177 static inline enum aarch64_operand_error_kind
178 get_error_kind (void)
180 return inst
.parsing_error
.kind
;
184 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
186 inst
.parsing_error
.kind
= kind
;
187 inst
.parsing_error
.error
= error
;
191 set_recoverable_error (const char *error
)
193 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
196 /* Use the DESC field of the corresponding aarch64_operand entry to compose
197 the error message. */
199 set_default_error (void)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
205 set_syntax_error (const char *error
)
207 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
211 set_first_syntax_error (const char *error
)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
218 set_fatal_syntax_error (const char *error
)
220 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
223 /* Number of littlenums required to hold an extended precision number. */
224 #define MAX_LITTLENUMS 6
226 /* Return value for certain parsers when the parsing fails; those parsers
227 return the information of the parsed result, e.g. register number, on
229 #define PARSE_FAIL -1
231 /* This is an invalid condition code that means no conditional field is
233 #define COND_ALWAYS 0x10
237 const char *template;
243 const char *template;
250 bfd_reloc_code_real_type reloc
;
253 /* Macros to define the register types and masks for the purpose
256 #undef AARCH64_REG_TYPES
257 #define AARCH64_REG_TYPES \
258 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
259 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
260 BASIC_REG_TYPE(SP_32) /* wsp */ \
261 BASIC_REG_TYPE(SP_64) /* sp */ \
262 BASIC_REG_TYPE(Z_32) /* wzr */ \
263 BASIC_REG_TYPE(Z_64) /* xzr */ \
264 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
265 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
266 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
267 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
268 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
269 BASIC_REG_TYPE(CN) /* c[0-7] */ \
270 BASIC_REG_TYPE(VN) /* v[0-31] */ \
271 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
272 BASIC_REG_TYPE(PN) /* p[0-15] */ \
273 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
274 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
275 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
276 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
277 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
278 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
279 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
280 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
281 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
282 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
283 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
284 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
285 /* Typecheck: any [BHSDQ]P FP. */ \
286 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
287 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
288 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
289 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
291 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
292 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
293 /* Any integer register; used for error messages only. */ \
294 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
296 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
297 /* Pseudo type to mark the end of the enumerator sequence. */ \
300 #undef BASIC_REG_TYPE
301 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
302 #undef MULTI_REG_TYPE
303 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
305 /* Register type enumerators. */
306 typedef enum aarch64_reg_type_
308 /* A list of REG_TYPE_*. */
312 #undef BASIC_REG_TYPE
313 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
315 #define REG_TYPE(T) (1 << REG_TYPE_##T)
316 #undef MULTI_REG_TYPE
317 #define MULTI_REG_TYPE(T,V) V,
319 /* Structure for a hash table entry for a register. */
323 unsigned char number
;
324 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
325 unsigned char builtin
;
328 /* Values indexed by aarch64_reg_type to assist the type checking. */
329 static const unsigned reg_type_masks
[] =
334 #undef BASIC_REG_TYPE
336 #undef MULTI_REG_TYPE
337 #undef AARCH64_REG_TYPES
339 /* Diagnostics used when we don't get a register of the expected type.
340 Note: this has to synchronized with aarch64_reg_type definitions
343 get_reg_expected_msg (aarch64_reg_type reg_type
)
350 msg
= N_("integer 32-bit register expected");
353 msg
= N_("integer 64-bit register expected");
356 msg
= N_("integer register expected");
358 case REG_TYPE_R64_SP
:
359 msg
= N_("64-bit integer or SP register expected");
362 msg
= N_("integer or zero register expected");
365 msg
= N_("integer or SP register expected");
367 case REG_TYPE_R_Z_SP
:
368 msg
= N_("integer, zero or SP register expected");
371 msg
= N_("8-bit SIMD scalar register expected");
374 msg
= N_("16-bit SIMD scalar or floating-point half precision "
375 "register expected");
378 msg
= N_("32-bit SIMD scalar or floating-point single precision "
379 "register expected");
382 msg
= N_("64-bit SIMD scalar or floating-point double precision "
383 "register expected");
386 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
387 "register expected");
390 msg
= N_("C0 - C15 expected");
392 case REG_TYPE_R_Z_BHSDQ_V
:
393 msg
= N_("register expected");
395 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
396 msg
= N_("SIMD scalar or floating-point register expected");
398 case REG_TYPE_VN
: /* any V reg */
399 msg
= N_("vector register expected");
402 msg
= N_("SVE vector register expected");
405 msg
= N_("SVE predicate register expected");
408 as_fatal (_("invalid register type %d"), reg_type
);
413 /* Some well known registers that we refer to directly elsewhere. */
416 /* Instructions take 4 bytes in the object file. */
419 static struct hash_control
*aarch64_ops_hsh
;
420 static struct hash_control
*aarch64_cond_hsh
;
421 static struct hash_control
*aarch64_shift_hsh
;
422 static struct hash_control
*aarch64_sys_regs_hsh
;
423 static struct hash_control
*aarch64_pstatefield_hsh
;
424 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
425 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
426 static struct hash_control
*aarch64_sys_regs_at_hsh
;
427 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
428 static struct hash_control
*aarch64_reg_hsh
;
429 static struct hash_control
*aarch64_barrier_opt_hsh
;
430 static struct hash_control
*aarch64_nzcv_hsh
;
431 static struct hash_control
*aarch64_pldop_hsh
;
432 static struct hash_control
*aarch64_hint_opt_hsh
;
434 /* Stuff needed to resolve the label ambiguity
443 static symbolS
*last_label_seen
;
445 /* Literal pool structure. Held on a per-section
446 and per-sub-section basis. */
448 #define MAX_LITERAL_POOL_SIZE 1024
449 typedef struct literal_expression
452 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
453 LITTLENUM_TYPE
* bignum
;
454 } literal_expression
;
456 typedef struct literal_pool
458 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
459 unsigned int next_free_entry
;
465 struct literal_pool
*next
;
468 /* Pointer to a linked list of literal pools. */
469 static literal_pool
*list_of_pools
= NULL
;
473 /* This array holds the chars that always start a comment. If the
474 pre-processor is disabled, these aren't very useful. */
475 const char comment_chars
[] = "";
477 /* This array holds the chars that only start a comment at the beginning of
478 a line. If the line seems to have the form '# 123 filename'
479 .line and .file directives will appear in the pre-processed output. */
480 /* Note that input_file.c hand checks for '#' at the beginning of the
481 first line of the input file. This is because the compiler outputs
482 #NO_APP at the beginning of its output. */
483 /* Also note that comments like this one will always work. */
484 const char line_comment_chars
[] = "#";
486 const char line_separator_chars
[] = ";";
488 /* Chars that can be used to separate mant
489 from exp in floating point numbers. */
490 const char EXP_CHARS
[] = "eE";
492 /* Chars that mean this number is a floating point constant. */
496 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
498 /* Prefix character that indicates the start of an immediate value. */
499 #define is_immediate_prefix(C) ((C) == '#')
501 /* Separator character handling. */
503 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
505 static inline bfd_boolean
506 skip_past_char (char **str
, char c
)
517 #define skip_past_comma(str) skip_past_char (str, ',')
519 /* Arithmetic expressions (possibly involving symbols). */
521 static bfd_boolean in_my_get_expression_p
= FALSE
;
523 /* Third argument to my_get_expression. */
524 #define GE_NO_PREFIX 0
525 #define GE_OPT_PREFIX 1
527 /* Return TRUE if the string pointed by *STR is successfully parsed
528 as an valid expression; *EP will be filled with the information of
529 such an expression. Otherwise return FALSE. */
532 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
537 int prefix_present_p
= 0;
544 if (is_immediate_prefix (**str
))
547 prefix_present_p
= 1;
554 memset (ep
, 0, sizeof (expressionS
));
556 save_in
= input_line_pointer
;
557 input_line_pointer
= *str
;
558 in_my_get_expression_p
= TRUE
;
559 seg
= expression (ep
);
560 in_my_get_expression_p
= FALSE
;
562 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
564 /* We found a bad expression in md_operand(). */
565 *str
= input_line_pointer
;
566 input_line_pointer
= save_in
;
567 if (prefix_present_p
&& ! error_p ())
568 set_fatal_syntax_error (_("bad expression"));
570 set_first_syntax_error (_("bad expression"));
575 if (seg
!= absolute_section
576 && seg
!= text_section
577 && seg
!= data_section
578 && seg
!= bss_section
&& seg
!= undefined_section
)
580 set_syntax_error (_("bad segment"));
581 *str
= input_line_pointer
;
582 input_line_pointer
= save_in
;
589 *str
= input_line_pointer
;
590 input_line_pointer
= save_in
;
594 /* Turn a string in input_line_pointer into a floating point constant
595 of type TYPE, and store the appropriate bytes in *LITP. The number
596 of LITTLENUMS emitted is stored in *SIZEP. An error message is
597 returned, or NULL on OK. */
600 md_atof (int type
, char *litP
, int *sizeP
)
602 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
605 /* We handle all bad expressions here, so that we can report the faulty
606 instruction in the error message. */
608 md_operand (expressionS
* exp
)
610 if (in_my_get_expression_p
)
611 exp
->X_op
= O_illegal
;
614 /* Immediate values. */
616 /* Errors may be set multiple times during parsing or bit encoding
617 (particularly in the Neon bits), but usually the earliest error which is set
618 will be the most meaningful. Avoid overwriting it with later (cascading)
619 errors by calling this function. */
622 first_error (const char *error
)
625 set_syntax_error (error
);
628 /* Similiar to first_error, but this function accepts formatted error
631 first_error_fmt (const char *format
, ...)
636 /* N.B. this single buffer will not cause error messages for different
637 instructions to pollute each other; this is because at the end of
638 processing of each assembly line, error message if any will be
639 collected by as_bad. */
640 static char buffer
[size
];
644 int ret ATTRIBUTE_UNUSED
;
645 va_start (args
, format
);
646 ret
= vsnprintf (buffer
, size
, format
, args
);
647 know (ret
<= size
- 1 && ret
>= 0);
649 set_syntax_error (buffer
);
653 /* Register parsing. */
655 /* Generic register parser which is called by other specialized
657 CCP points to what should be the beginning of a register name.
658 If it is indeed a valid register name, advance CCP over it and
659 return the reg_entry structure; otherwise return NULL.
660 It does not issue diagnostics. */
663 parse_reg (char **ccp
)
669 #ifdef REGISTER_PREFIX
670 if (*start
!= REGISTER_PREFIX
)
676 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
681 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
683 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
692 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
695 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
697 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
700 /* Try to parse a base or offset register. Return the register entry
701 on success, setting *QUALIFIER to the register qualifier. Return null
704 Note that this function does not issue any diagnostics. */
706 static const reg_entry
*
707 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
710 const reg_entry
*reg
= parse_reg (&str
);
720 *qualifier
= AARCH64_OPND_QLF_W
;
726 *qualifier
= AARCH64_OPND_QLF_X
;
738 /* Parse the qualifier of a vector register or vector element of type
739 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
740 succeeds; otherwise return FALSE.
742 Accept only one occurrence of:
743 8b 16b 2h 4h 8h 2s 4s 1d 2d
746 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
747 struct vector_type_el
*parsed_type
, char **str
)
751 unsigned element_size
;
752 enum vector_el_type type
;
755 gas_assert (*ptr
== '.');
758 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
763 width
= strtoul (ptr
, &ptr
, 10);
764 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
766 first_error_fmt (_("bad size %d in vector width specifier"), width
);
771 switch (TOLOWER (*ptr
))
799 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
801 first_error (_("missing element size"));
804 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
805 && !(width
== 2 && element_size
== 16))
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type
->type
= type
;
815 parsed_type
->width
= width
;
822 /* *STR contains an SVE zero/merge predication suffix. Parse it into
823 *PARSED_TYPE and point *STR at the end of the suffix. */
826 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
831 gas_assert (*ptr
== '/');
833 switch (TOLOWER (*ptr
))
836 parsed_type
->type
= NT_zero
;
839 parsed_type
->type
= NT_merge
;
842 if (*ptr
!= '\0' && *ptr
!= ',')
843 first_error_fmt (_("unexpected character `%c' in predication type"),
846 first_error (_("missing predication type"));
849 parsed_type
->width
= 0;
854 /* Parse a register of the type TYPE.
856 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
857 name or the parsed register is not of TYPE.
859 Otherwise return the register number, and optionally fill in the actual
860 type of the register in *RTYPE when multiple alternatives were given, and
861 return the register shape and element index information in *TYPEINFO.
863 IN_REG_LIST should be set with TRUE if the caller is parsing a register
867 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
868 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
871 const reg_entry
*reg
= parse_reg (&str
);
872 struct vector_type_el atype
;
873 struct vector_type_el parsetype
;
874 bfd_boolean is_typed_vecreg
= FALSE
;
877 atype
.type
= NT_invtype
;
885 set_default_error ();
889 if (! aarch64_check_reg_type (reg
, type
))
891 DEBUG_TRACE ("reg type check failed");
892 set_default_error ();
897 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
898 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
902 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
907 if (!parse_predication_for_operand (&parsetype
, &str
))
911 /* Register if of the form Vn.[bhsdq]. */
912 is_typed_vecreg
= TRUE
;
914 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
916 /* The width is always variable; we don't allow an integer width
918 gas_assert (parsetype
.width
== 0);
919 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
921 else if (parsetype
.width
== 0)
922 /* Expect index. In the new scheme we cannot have
923 Vn.[bhsdq] represent a scalar. Therefore any
924 Vn.[bhsdq] should have an index following it.
925 Except in reglists ofcourse. */
926 atype
.defined
|= NTA_HASINDEX
;
928 atype
.defined
|= NTA_HASTYPE
;
930 atype
.type
= parsetype
.type
;
931 atype
.width
= parsetype
.width
;
934 if (skip_past_char (&str
, '['))
938 /* Reject Sn[index] syntax. */
939 if (!is_typed_vecreg
)
941 first_error (_("this type of register can't be indexed"));
945 if (in_reg_list
== TRUE
)
947 first_error (_("index not allowed inside register list"));
951 atype
.defined
|= NTA_HASINDEX
;
953 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
955 if (exp
.X_op
!= O_constant
)
957 first_error (_("constant expression required"));
961 if (! skip_past_char (&str
, ']'))
964 atype
.index
= exp
.X_add_number
;
966 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
968 /* Indexed vector register expected. */
969 first_error (_("indexed vector register expected"));
973 /* A vector reg Vn should be typed or indexed. */
974 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
976 first_error (_("invalid use of vector register"));
992 Return the register number on success; return PARSE_FAIL otherwise.
994 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
995 the register (e.g. NEON double or quad reg when either has been requested).
997 If this is a NEON vector register with additional type information, fill
998 in the struct pointed to by VECTYPE (if non-NULL).
1000 This parser does not handle register list. */
1003 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1004 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1006 struct vector_type_el atype
;
1008 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1009 /*in_reg_list= */ FALSE
);
1011 if (reg
== PARSE_FAIL
)
1022 static inline bfd_boolean
1023 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1027 && e1
.defined
== e2
.defined
1028 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1031 /* This function parses a list of vector registers of type TYPE.
1032 On success, it returns the parsed register list information in the
1033 following encoded format:
1035 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1036 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1038 The information of the register shape and/or index is returned in
1041 It returns PARSE_FAIL if the register list is invalid.
1043 The list contains one to four registers.
1044 Each register can be one of:
1047 All <T> should be identical.
1048 All <index> should be identical.
1049 There are restrictions on <Vt> numbers which are checked later
1050 (by reg_list_valid_p). */
1053 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1054 struct vector_type_el
*vectype
)
1058 struct vector_type_el typeinfo
, typeinfo_first
;
1063 bfd_boolean error
= FALSE
;
1064 bfd_boolean expect_index
= FALSE
;
1068 set_syntax_error (_("expecting {"));
1074 typeinfo_first
.defined
= 0;
1075 typeinfo_first
.type
= NT_invtype
;
1076 typeinfo_first
.width
= -1;
1077 typeinfo_first
.index
= 0;
1086 str
++; /* skip over '-' */
1089 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1090 /*in_reg_list= */ TRUE
);
1091 if (val
== PARSE_FAIL
)
1093 set_first_syntax_error (_("invalid vector register in list"));
1097 /* reject [bhsd]n */
1098 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1100 set_first_syntax_error (_("invalid scalar register in list"));
1105 if (typeinfo
.defined
& NTA_HASINDEX
)
1106 expect_index
= TRUE
;
1110 if (val
< val_range
)
1112 set_first_syntax_error
1113 (_("invalid range in vector register list"));
1122 typeinfo_first
= typeinfo
;
1123 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1125 set_first_syntax_error
1126 (_("type mismatch in vector register list"));
1131 for (i
= val_range
; i
<= val
; i
++)
1133 ret_val
|= i
<< (5 * nb_regs
);
1138 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1140 skip_whitespace (str
);
1143 set_first_syntax_error (_("end of vector register list not found"));
1148 skip_whitespace (str
);
1152 if (skip_past_char (&str
, '['))
1156 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1157 if (exp
.X_op
!= O_constant
)
1159 set_first_syntax_error (_("constant expression required."));
1162 if (! skip_past_char (&str
, ']'))
1165 typeinfo_first
.index
= exp
.X_add_number
;
1169 set_first_syntax_error (_("expected index"));
1176 set_first_syntax_error (_("too many registers in vector register list"));
1179 else if (nb_regs
== 0)
1181 set_first_syntax_error (_("empty vector register list"));
1187 *vectype
= typeinfo_first
;
1189 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1192 /* Directives: register aliases. */
1195 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1200 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1203 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1206 /* Only warn about a redefinition if it's not defined as the
1208 else if (new->number
!= number
|| new->type
!= type
)
1209 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1214 name
= xstrdup (str
);
1215 new = XNEW (reg_entry
);
1218 new->number
= number
;
1220 new->builtin
= FALSE
;
1222 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1228 /* Look for the .req directive. This is of the form:
1230 new_register_name .req existing_register_name
1232 If we find one, or if it looks sufficiently like one that we want to
1233 handle any error here, return TRUE. Otherwise return FALSE. */
1236 create_register_alias (char *newname
, char *p
)
1238 const reg_entry
*old
;
1239 char *oldname
, *nbuf
;
1242 /* The input scrubber ensures that whitespace after the mnemonic is
1243 collapsed to single spaces. */
1245 if (strncmp (oldname
, " .req ", 6) != 0)
1249 if (*oldname
== '\0')
1252 old
= hash_find (aarch64_reg_hsh
, oldname
);
1255 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1259 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1260 the desired alias name, and p points to its end. If not, then
1261 the desired alias name is in the global original_case_string. */
1262 #ifdef TC_CASE_SENSITIVE
1265 newname
= original_case_string
;
1266 nlen
= strlen (newname
);
1269 nbuf
= xmemdup0 (newname
, nlen
);
1271 /* Create aliases under the new name as stated; an all-lowercase
1272 version of the new name; and an all-uppercase version of the new
1274 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1276 for (p
= nbuf
; *p
; p
++)
1279 if (strncmp (nbuf
, newname
, nlen
))
1281 /* If this attempt to create an additional alias fails, do not bother
1282 trying to create the all-lower case alias. We will fail and issue
1283 a second, duplicate error message. This situation arises when the
1284 programmer does something like:
1287 The second .req creates the "Foo" alias but then fails to create
1288 the artificial FOO alias because it has already been created by the
1290 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1297 for (p
= nbuf
; *p
; p
++)
1300 if (strncmp (nbuf
, newname
, nlen
))
1301 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1308 /* Should never be called, as .req goes between the alias and the
1309 register name, not at the beginning of the line. */
1311 s_req (int a ATTRIBUTE_UNUSED
)
1313 as_bad (_("invalid syntax for .req directive"));
1316 /* The .unreq directive deletes an alias which was previously defined
1317 by .req. For example:
1323 s_unreq (int a ATTRIBUTE_UNUSED
)
1328 name
= input_line_pointer
;
1330 while (*input_line_pointer
!= 0
1331 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1332 ++input_line_pointer
;
1334 saved_char
= *input_line_pointer
;
1335 *input_line_pointer
= 0;
1338 as_bad (_("invalid syntax for .unreq directive"));
1341 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1344 as_bad (_("unknown register alias '%s'"), name
);
1345 else if (reg
->builtin
)
1346 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1353 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1354 free ((char *) reg
->name
);
1357 /* Also locate the all upper case and all lower case versions.
1358 Do not complain if we cannot find one or the other as it
1359 was probably deleted above. */
1361 nbuf
= strdup (name
);
1362 for (p
= nbuf
; *p
; p
++)
1364 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1367 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1368 free ((char *) reg
->name
);
1372 for (p
= nbuf
; *p
; p
++)
1374 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1377 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1378 free ((char *) reg
->name
);
1386 *input_line_pointer
= saved_char
;
1387 demand_empty_rest_of_line ();
1390 /* Directives: Instruction set selection. */
1393 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1394 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1395 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1396 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1398 /* Create a new mapping symbol for the transition to STATE. */
1401 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1404 const char *symname
;
1411 type
= BSF_NO_FLAGS
;
1415 type
= BSF_NO_FLAGS
;
1421 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1422 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1424 /* Save the mapping symbols for future reference. Also check that
1425 we do not place two mapping symbols at the same offset within a
1426 frag. We'll handle overlap between frags in
1427 check_mapping_symbols.
1429 If .fill or other data filling directive generates zero sized data,
1430 the mapping symbol for the following code will have the same value
1431 as the one generated for the data filling directive. In this case,
1432 we replace the old symbol with the new one at the same address. */
1435 if (frag
->tc_frag_data
.first_map
!= NULL
)
1437 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1438 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1441 frag
->tc_frag_data
.first_map
= symbolP
;
1443 if (frag
->tc_frag_data
.last_map
!= NULL
)
1445 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1446 S_GET_VALUE (symbolP
));
1447 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1448 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1451 frag
->tc_frag_data
.last_map
= symbolP
;
1454 /* We must sometimes convert a region marked as code to data during
1455 code alignment, if an odd number of bytes have to be padded. The
1456 code mapping symbol is pushed to an aligned address. */
1459 insert_data_mapping_symbol (enum mstate state
,
1460 valueT value
, fragS
* frag
, offsetT bytes
)
1462 /* If there was already a mapping symbol, remove it. */
1463 if (frag
->tc_frag_data
.last_map
!= NULL
1464 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1465 frag
->fr_address
+ value
)
1467 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1471 know (frag
->tc_frag_data
.first_map
== symp
);
1472 frag
->tc_frag_data
.first_map
= NULL
;
1474 frag
->tc_frag_data
.last_map
= NULL
;
1475 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1478 make_mapping_symbol (MAP_DATA
, value
, frag
);
1479 make_mapping_symbol (state
, value
+ bytes
, frag
);
1482 static void mapping_state_2 (enum mstate state
, int max_chars
);
1484 /* Set the mapping state to STATE. Only call this when about to
1485 emit some STATE bytes to the file. */
1488 mapping_state (enum mstate state
)
1490 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1492 if (state
== MAP_INSN
)
1493 /* AArch64 instructions require 4-byte alignment. When emitting
1494 instructions into any section, record the appropriate section
1496 record_alignment (now_seg
, 2);
1498 if (mapstate
== state
)
1499 /* The mapping symbol has already been emitted.
1500 There is nothing else to do. */
1503 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1504 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1505 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1506 evaluated later in the next else. */
1508 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1510 /* Only add the symbol if the offset is > 0:
1511 if we're at the first frag, check it's size > 0;
1512 if we're not at the first frag, then for sure
1513 the offset is > 0. */
1514 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1515 const int add_symbol
= (frag_now
!= frag_first
)
1516 || (frag_now_fix () > 0);
1519 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1523 mapping_state_2 (state
, 0);
1526 /* Same as mapping_state, but MAX_CHARS bytes have already been
1527 allocated. Put the mapping symbol that far back. */
1530 mapping_state_2 (enum mstate state
, int max_chars
)
1532 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1534 if (!SEG_NORMAL (now_seg
))
1537 if (mapstate
== state
)
1538 /* The mapping symbol has already been emitted.
1539 There is nothing else to do. */
1542 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1543 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1546 #define mapping_state(x) /* nothing */
1547 #define mapping_state_2(x, y) /* nothing */
1550 /* Directives: sectioning and alignment. */
1553 s_bss (int ignore ATTRIBUTE_UNUSED
)
1555 /* We don't support putting frags in the BSS segment, we fake it by
1556 marking in_bss, then looking at s_skip for clues. */
1557 subseg_set (bss_section
, 0);
1558 demand_empty_rest_of_line ();
1559 mapping_state (MAP_DATA
);
1563 s_even (int ignore ATTRIBUTE_UNUSED
)
1565 /* Never make frag if expect extra pass. */
1567 frag_align (1, 0, 0);
1569 record_alignment (now_seg
, 1);
1571 demand_empty_rest_of_line ();
1574 /* Directives: Literal pools. */
1576 static literal_pool
*
1577 find_literal_pool (int size
)
1581 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1583 if (pool
->section
== now_seg
1584 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1591 static literal_pool
*
1592 find_or_make_literal_pool (int size
)
1594 /* Next literal pool ID number. */
1595 static unsigned int latest_pool_num
= 1;
1598 pool
= find_literal_pool (size
);
1602 /* Create a new pool. */
1603 pool
= XNEW (literal_pool
);
1607 /* Currently we always put the literal pool in the current text
1608 section. If we were generating "small" model code where we
1609 knew that all code and initialised data was within 1MB then
1610 we could output literals to mergeable, read-only data
1613 pool
->next_free_entry
= 0;
1614 pool
->section
= now_seg
;
1615 pool
->sub_section
= now_subseg
;
1617 pool
->next
= list_of_pools
;
1618 pool
->symbol
= NULL
;
1620 /* Add it to the list. */
1621 list_of_pools
= pool
;
1624 /* New pools, and emptied pools, will have a NULL symbol. */
1625 if (pool
->symbol
== NULL
)
1627 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1628 (valueT
) 0, &zero_address_frag
);
1629 pool
->id
= latest_pool_num
++;
1636 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1637 Return TRUE on success, otherwise return FALSE. */
1639 add_to_lit_pool (expressionS
*exp
, int size
)
1644 pool
= find_or_make_literal_pool (size
);
1646 /* Check if this literal value is already in the pool. */
1647 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1649 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1651 if ((litexp
->X_op
== exp
->X_op
)
1652 && (exp
->X_op
== O_constant
)
1653 && (litexp
->X_add_number
== exp
->X_add_number
)
1654 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1657 if ((litexp
->X_op
== exp
->X_op
)
1658 && (exp
->X_op
== O_symbol
)
1659 && (litexp
->X_add_number
== exp
->X_add_number
)
1660 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1661 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1665 /* Do we need to create a new entry? */
1666 if (entry
== pool
->next_free_entry
)
1668 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1670 set_syntax_error (_("literal pool overflow"));
1674 pool
->literals
[entry
].exp
= *exp
;
1675 pool
->next_free_entry
+= 1;
1676 if (exp
->X_op
== O_big
)
1678 /* PR 16688: Bignums are held in a single global array. We must
1679 copy and preserve that value now, before it is overwritten. */
1680 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1682 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1683 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1686 pool
->literals
[entry
].bignum
= NULL
;
1689 exp
->X_op
= O_symbol
;
1690 exp
->X_add_number
= ((int) entry
) * size
;
1691 exp
->X_add_symbol
= pool
->symbol
;
1696 /* Can't use symbol_new here, so have to create a symbol and then at
1697 a later date assign it a value. Thats what these functions do. */
1700 symbol_locate (symbolS
* symbolP
,
1701 const char *name
,/* It is copied, the caller can modify. */
1702 segT segment
, /* Segment identifier (SEG_<something>). */
1703 valueT valu
, /* Symbol value. */
1704 fragS
* frag
) /* Associated fragment. */
1707 char *preserved_copy_of_name
;
1709 name_length
= strlen (name
) + 1; /* +1 for \0. */
1710 obstack_grow (¬es
, name
, name_length
);
1711 preserved_copy_of_name
= obstack_finish (¬es
);
1713 #ifdef tc_canonicalize_symbol_name
1714 preserved_copy_of_name
=
1715 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1718 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1720 S_SET_SEGMENT (symbolP
, segment
);
1721 S_SET_VALUE (symbolP
, valu
);
1722 symbol_clear_list_pointers (symbolP
);
1724 symbol_set_frag (symbolP
, frag
);
1726 /* Link to end of symbol chain. */
1728 extern int symbol_table_frozen
;
1730 if (symbol_table_frozen
)
1734 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1736 obj_symbol_new_hook (symbolP
);
1738 #ifdef tc_symbol_new_hook
1739 tc_symbol_new_hook (symbolP
);
1743 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1744 #endif /* DEBUG_SYMS */
1749 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1756 for (align
= 2; align
<= 4; align
++)
1758 int size
= 1 << align
;
1760 pool
= find_literal_pool (size
);
1761 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1764 /* Align pool as you have word accesses.
1765 Only make a frag if we have to. */
1767 frag_align (align
, 0, 0);
1769 mapping_state (MAP_DATA
);
1771 record_alignment (now_seg
, align
);
1773 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1775 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1776 (valueT
) frag_now_fix (), frag_now
);
1777 symbol_table_insert (pool
->symbol
);
1779 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1781 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1783 if (exp
->X_op
== O_big
)
1785 /* PR 16688: Restore the global bignum value. */
1786 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1787 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1788 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1791 /* First output the expression in the instruction to the pool. */
1792 emit_expr (exp
, size
); /* .word|.xword */
1794 if (exp
->X_op
== O_big
)
1796 free (pool
->literals
[entry
].bignum
);
1797 pool
->literals
[entry
].bignum
= NULL
;
1801 /* Mark the pool as empty. */
1802 pool
->next_free_entry
= 0;
1803 pool
->symbol
= NULL
;
1808 /* Forward declarations for functions below, in the MD interface
1810 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1811 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1813 /* Directives: Data. */
1814 /* N.B. the support for relocation suffix in this directive needs to be
1815 implemented properly. */
1818 s_aarch64_elf_cons (int nbytes
)
1822 #ifdef md_flush_pending_output
1823 md_flush_pending_output ();
1826 if (is_it_end_of_statement ())
1828 demand_empty_rest_of_line ();
1832 #ifdef md_cons_align
1833 md_cons_align (nbytes
);
1836 mapping_state (MAP_DATA
);
1839 struct reloc_table_entry
*reloc
;
1843 if (exp
.X_op
!= O_symbol
)
1844 emit_expr (&exp
, (unsigned int) nbytes
);
1847 skip_past_char (&input_line_pointer
, '#');
1848 if (skip_past_char (&input_line_pointer
, ':'))
1850 reloc
= find_reloc_table_entry (&input_line_pointer
);
1852 as_bad (_("unrecognized relocation suffix"));
1854 as_bad (_("unimplemented relocation suffix"));
1855 ignore_rest_of_line ();
1859 emit_expr (&exp
, (unsigned int) nbytes
);
1862 while (*input_line_pointer
++ == ',');
1864 /* Put terminator back into stream. */
1865 input_line_pointer
--;
1866 demand_empty_rest_of_line ();
1869 #endif /* OBJ_ELF */
1871 /* Output a 32-bit word, but mark as an instruction. */
1874 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1878 #ifdef md_flush_pending_output
1879 md_flush_pending_output ();
1882 if (is_it_end_of_statement ())
1884 demand_empty_rest_of_line ();
1888 /* Sections are assumed to start aligned. In executable section, there is no
1889 MAP_DATA symbol pending. So we only align the address during
1890 MAP_DATA --> MAP_INSN transition.
1891 For other sections, this is not guaranteed. */
1892 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1893 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1894 frag_align_code (2, 0);
1897 mapping_state (MAP_INSN
);
1903 if (exp
.X_op
!= O_constant
)
1905 as_bad (_("constant expression required"));
1906 ignore_rest_of_line ();
1910 if (target_big_endian
)
1912 unsigned int val
= exp
.X_add_number
;
1913 exp
.X_add_number
= SWAP_32 (val
);
1915 emit_expr (&exp
, 4);
1917 while (*input_line_pointer
++ == ',');
1919 /* Put terminator back into stream. */
1920 input_line_pointer
--;
1921 demand_empty_rest_of_line ();
1925 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1928 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1934 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1935 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1937 demand_empty_rest_of_line ();
1940 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1943 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1947 /* Since we're just labelling the code, there's no need to define a
1950 /* Make sure there is enough room in this frag for the following
1951 blr. This trick only works if the blr follows immediately after
1952 the .tlsdesc directive. */
1954 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1955 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1957 demand_empty_rest_of_line ();
1960 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1963 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1969 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1970 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1972 demand_empty_rest_of_line ();
1974 #endif /* OBJ_ELF */
1976 static void s_aarch64_arch (int);
1977 static void s_aarch64_cpu (int);
1978 static void s_aarch64_arch_extension (int);
1980 /* This table describes all the machine specific pseudo-ops the assembler
1981 has to support. The fields are:
1982 pseudo-op name without dot
1983 function to call to execute this pseudo-op
1984 Integer arg to pass to the function. */
1986 const pseudo_typeS md_pseudo_table
[] = {
1987 /* Never called because '.req' does not start a line. */
1989 {"unreq", s_unreq
, 0},
1991 {"even", s_even
, 0},
1992 {"ltorg", s_ltorg
, 0},
1993 {"pool", s_ltorg
, 0},
1994 {"cpu", s_aarch64_cpu
, 0},
1995 {"arch", s_aarch64_arch
, 0},
1996 {"arch_extension", s_aarch64_arch_extension
, 0},
1997 {"inst", s_aarch64_inst
, 0},
1999 {"tlsdescadd", s_tlsdescadd
, 0},
2000 {"tlsdesccall", s_tlsdesccall
, 0},
2001 {"tlsdescldr", s_tlsdescldr
, 0},
2002 {"word", s_aarch64_elf_cons
, 4},
2003 {"long", s_aarch64_elf_cons
, 4},
2004 {"xword", s_aarch64_elf_cons
, 8},
2005 {"dword", s_aarch64_elf_cons
, 8},
2011 /* Check whether STR points to a register name followed by a comma or the
2012 end of line; REG_TYPE indicates which register types are checked
2013 against. Return TRUE if STR is such a register name; otherwise return
2014 FALSE. The function does not intend to produce any diagnostics, but since
2015 the register parser aarch64_reg_parse, which is called by this function,
2016 does produce diagnostics, we call clear_error to clear any diagnostics
2017 that may be generated by aarch64_reg_parse.
2018 Also, the function returns FALSE directly if there is any user error
2019 present at the function entry. This prevents the existing diagnostics
2020 state from being spoiled.
2021 The function currently serves parse_constant_immediate and
2022 parse_big_immediate only. */
2024 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2028 /* Prevent the diagnostics state from being spoiled. */
2032 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2034 /* Clear the parsing error that may be set by the reg parser. */
2037 if (reg
== PARSE_FAIL
)
2040 skip_whitespace (str
);
2041 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2047 /* Parser functions used exclusively in instruction operands. */
2049 /* Parse an immediate expression which may not be constant.
2051 To prevent the expression parser from pushing a register name
2052 into the symbol table as an undefined symbol, firstly a check is
2053 done to find out whether STR is a register of type REG_TYPE followed
2054 by a comma or the end of line. Return FALSE if STR is such a string. */
2057 parse_immediate_expression (char **str
, expressionS
*exp
,
2058 aarch64_reg_type reg_type
)
2060 if (reg_name_p (*str
, reg_type
))
2062 set_recoverable_error (_("immediate operand required"));
2066 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2068 if (exp
->X_op
== O_absent
)
2070 set_fatal_syntax_error (_("missing immediate expression"));
2077 /* Constant immediate-value read function for use in insn parsing.
2078 STR points to the beginning of the immediate (with the optional
2079 leading #); *VAL receives the value. REG_TYPE says which register
2080 names should be treated as registers rather than as symbolic immediates.
2082 Return TRUE on success; otherwise return FALSE. */
2085 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2089 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2092 if (exp
.X_op
!= O_constant
)
2094 set_syntax_error (_("constant expression required"));
2098 *val
= exp
.X_add_number
;
2103 encode_imm_float_bits (uint32_t imm
)
2105 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2106 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2109 /* Return TRUE if the single-precision floating-point value encoded in IMM
2110 can be expressed in the AArch64 8-bit signed floating-point format with
2111 3-bit exponent and normalized 4 bits of precision; in other words, the
2112 floating-point value must be expressable as
2113 (+/-) n / 16 * power (2, r)
2114 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2117 aarch64_imm_float_p (uint32_t imm
)
2119 /* If a single-precision floating-point value has the following bit
2120 pattern, it can be expressed in the AArch64 8-bit floating-point
2123 3 32222222 2221111111111
2124 1 09876543 21098765432109876543210
2125 n Eeeeeexx xxxx0000000000000000000
2127 where n, e and each x are either 0 or 1 independently, with
2132 /* Prepare the pattern for 'Eeeeee'. */
2133 if (((imm
>> 30) & 0x1) == 0)
2134 pattern
= 0x3e000000;
2136 pattern
= 0x40000000;
2138 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2139 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2142 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2143 as an IEEE float without any loss of precision. Store the value in
2147 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2149 /* If a double-precision floating-point value has the following bit
2150 pattern, it can be expressed in a float:
2152 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2153 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2154 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2156 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2157 if Eeee_eeee != 1111_1111
2159 where n, e, s and S are either 0 or 1 independently and where ~ is the
2163 uint32_t high32
= imm
>> 32;
2164 uint32_t low32
= imm
;
2166 /* Lower 29 bits need to be 0s. */
2167 if ((imm
& 0x1fffffff) != 0)
2170 /* Prepare the pattern for 'Eeeeeeeee'. */
2171 if (((high32
>> 30) & 0x1) == 0)
2172 pattern
= 0x38000000;
2174 pattern
= 0x40000000;
2177 if ((high32
& 0x78000000) != pattern
)
2180 /* Check Eeee_eeee != 1111_1111. */
2181 if ((high32
& 0x7ff00000) == 0x47f00000)
2184 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2185 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2186 | (low32
>> 29)); /* 3 S bits. */
2190 /* Parse a floating-point immediate. Return TRUE on success and return the
2191 value in *IMMED in the format of IEEE754 single-precision encoding.
2192 *CCP points to the start of the string; DP_P is TRUE when the immediate
2193 is expected to be in double-precision (N.B. this only matters when
2194 hexadecimal representation is involved). REG_TYPE says which register
2195 names should be treated as registers rather than as symbolic immediates.
2197 This routine accepts any IEEE float; it is up to the callers to reject
2201 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2202 aarch64_reg_type reg_type
)
2206 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2207 int found_fpchar
= 0;
2209 unsigned fpword
= 0;
2210 bfd_boolean hex_p
= FALSE
;
2212 skip_past_char (&str
, '#');
2215 skip_whitespace (fpnum
);
2217 if (strncmp (fpnum
, "0x", 2) == 0)
2219 /* Support the hexadecimal representation of the IEEE754 encoding.
2220 Double-precision is expected when DP_P is TRUE, otherwise the
2221 representation should be in single-precision. */
2222 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2227 if (!can_convert_double_to_float (val
, &fpword
))
2230 else if ((uint64_t) val
> 0xffffffff)
2239 if (reg_name_p (str
, reg_type
))
2241 set_recoverable_error (_("immediate operand required"));
2245 /* We must not accidentally parse an integer as a floating-point number.
2246 Make sure that the value we parse is not an integer by checking for
2247 special characters '.' or 'e'. */
2248 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2249 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2263 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2266 /* Our FP word must be 32 bits (single-precision FP). */
2267 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2269 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2279 set_fatal_syntax_error (_("invalid floating-point constant"));
2283 /* Less-generic immediate-value read function with the possibility of loading
2284 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2287 To prevent the expression parser from pushing a register name into the
2288 symbol table as an undefined symbol, a check is firstly done to find
2289 out whether STR is a register of type REG_TYPE followed by a comma or
2290 the end of line. Return FALSE if STR is such a register. */
2293 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2297 if (reg_name_p (ptr
, reg_type
))
2299 set_syntax_error (_("immediate operand required"));
2303 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2305 if (inst
.reloc
.exp
.X_op
== O_constant
)
2306 *imm
= inst
.reloc
.exp
.X_add_number
;
2313 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2314 if NEED_LIBOPCODES is non-zero, the fixup will need
2315 assistance from the libopcodes. */
2318 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2319 const aarch64_opnd_info
*operand
,
2320 int need_libopcodes_p
)
2322 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2323 reloc
->opnd
= operand
->type
;
2324 if (need_libopcodes_p
)
2325 reloc
->need_libopcodes_p
= 1;
2328 /* Return TRUE if the instruction needs to be fixed up later internally by
2329 the GAS; otherwise return FALSE. */
2331 static inline bfd_boolean
2332 aarch64_gas_internal_fixup_p (void)
2334 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2337 /* Assign the immediate value to the relavant field in *OPERAND if
2338 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2339 needs an internal fixup in a later stage.
2340 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2341 IMM.VALUE that may get assigned with the constant. */
2343 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2344 aarch64_opnd_info
*operand
,
2346 int need_libopcodes_p
,
2349 if (reloc
->exp
.X_op
== O_constant
)
2352 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2354 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2355 reloc
->type
= BFD_RELOC_UNUSED
;
2359 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2360 /* Tell libopcodes to ignore this operand or not. This is helpful
2361 when one of the operands needs to be fixed up later but we need
2362 libopcodes to check the other operands. */
2363 operand
->skip
= skip_p
;
2367 /* Relocation modifiers. Each entry in the table contains the textual
2368 name for the relocation which may be placed before a symbol used as
2369 a load/store offset, or add immediate. It must be surrounded by a
2370 leading and trailing colon, for example:
2372 ldr x0, [x1, #:rello:varsym]
2373 add x0, x1, #:rello:varsym */
2375 struct reloc_table_entry
2379 bfd_reloc_code_real_type adr_type
;
2380 bfd_reloc_code_real_type adrp_type
;
2381 bfd_reloc_code_real_type movw_type
;
2382 bfd_reloc_code_real_type add_type
;
2383 bfd_reloc_code_real_type ldst_type
;
2384 bfd_reloc_code_real_type ld_literal_type
;
2387 static struct reloc_table_entry reloc_table
[] = {
2388 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2393 BFD_RELOC_AARCH64_ADD_LO12
,
2394 BFD_RELOC_AARCH64_LDST_LO12
,
2397 /* Higher 21 bits of pc-relative page offset: ADRP */
2400 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2406 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2409 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2415 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2419 BFD_RELOC_AARCH64_MOVW_G0
,
2424 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2428 BFD_RELOC_AARCH64_MOVW_G0_S
,
2433 /* Less significant bits 0-15 of address/value: MOVK, no check */
2437 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2442 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2446 BFD_RELOC_AARCH64_MOVW_G1
,
2451 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2455 BFD_RELOC_AARCH64_MOVW_G1_S
,
2460 /* Less significant bits 16-31 of address/value: MOVK, no check */
2464 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2469 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2473 BFD_RELOC_AARCH64_MOVW_G2
,
2478 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2482 BFD_RELOC_AARCH64_MOVW_G2_S
,
2487 /* Less significant bits 32-47 of address/value: MOVK, no check */
2491 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2496 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2500 BFD_RELOC_AARCH64_MOVW_G3
,
2505 /* Get to the page containing GOT entry for a symbol. */
2508 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2512 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2514 /* 12 bit offset into the page containing GOT entry for that symbol. */
2520 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2523 /* 0-15 bits of address/value: MOVk, no check. */
2527 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2532 /* Most significant bits 16-31 of address/value: MOVZ. */
2536 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2541 /* 15 bit offset into the page containing GOT entry for that symbol. */
2547 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2550 /* Get to the page containing GOT TLS entry for a symbol */
2551 {"gottprel_g0_nc", 0,
2554 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2559 /* Get to the page containing GOT TLS entry for a symbol */
2563 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2568 /* Get to the page containing GOT TLS entry for a symbol */
2570 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2571 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2577 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2582 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2586 /* Lower 16 bits address/value: MOVk. */
2590 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2595 /* Most significant bits 16-31 of address/value: MOVZ. */
2599 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2604 /* Get to the page containing GOT TLS entry for a symbol */
2606 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2607 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2611 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2613 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2618 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2619 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2622 /* Get to the page containing GOT TLS entry for a symbol.
2623 The same as GD, we allocate two consecutive GOT slots
2624 for module index and module offset, the only difference
2625 with GD is the module offset should be intialized to
2626 zero without any outstanding runtime relocation. */
2628 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2629 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2635 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2636 {"tlsldm_lo12_nc", 0,
2640 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2644 /* 12 bit offset into the module TLS base address. */
2649 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2650 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2653 /* Same as dtprel_lo12, no overflow check. */
2654 {"dtprel_lo12_nc", 0,
2658 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2659 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2662 /* bits[23:12] of offset to the module TLS base address. */
2667 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2671 /* bits[15:0] of offset to the module TLS base address. */
2675 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2680 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2684 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2689 /* bits[31:16] of offset to the module TLS base address. */
2693 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2698 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2702 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2707 /* bits[47:32] of offset to the module TLS base address. */
2711 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2716 /* Lower 16 bit offset into GOT entry for a symbol */
2717 {"tlsdesc_off_g0_nc", 0,
2720 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2725 /* Higher 16 bit offset into GOT entry for a symbol */
2726 {"tlsdesc_off_g1", 0,
2729 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2734 /* Get to the page containing GOT TLS entry for a symbol */
2737 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2741 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2743 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2744 {"gottprel_lo12", 0,
2749 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2752 /* Get tp offset for a symbol. */
2757 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2761 /* Get tp offset for a symbol. */
2766 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2770 /* Get tp offset for a symbol. */
2775 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2779 /* Get tp offset for a symbol. */
2780 {"tprel_lo12_nc", 0,
2784 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2788 /* Most significant bits 32-47 of address/value: MOVZ. */
2792 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2797 /* Most significant bits 16-31 of address/value: MOVZ. */
2801 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2806 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2810 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2815 /* Most significant bits 0-15 of address/value: MOVZ. */
2819 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2824 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2828 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2833 /* 15bit offset from got entry to base address of GOT table. */
2839 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2842 /* 14bit offset from got entry to base address of GOT table. */
2848 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2852 /* Given the address of a pointer pointing to the textual name of a
2853 relocation as may appear in assembler source, attempt to find its
2854 details in reloc_table. The pointer will be updated to the character
2855 after the trailing colon. On failure, NULL will be returned;
2856 otherwise return the reloc_table_entry. */
2858 static struct reloc_table_entry
*
2859 find_reloc_table_entry (char **str
)
2862 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2864 int length
= strlen (reloc_table
[i
].name
);
2866 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2867 && (*str
)[length
] == ':')
2869 *str
+= (length
+ 1);
2870 return &reloc_table
[i
];
2877 /* Mode argument to parse_shift and parser_shifter_operand. */
2878 enum parse_shift_mode
2880 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2882 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2884 SHIFTED_LSL
, /* bare "lsl #n" */
2885 SHIFTED_MUL
, /* bare "mul #n" */
2886 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2887 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2890 /* Parse a <shift> operator on an AArch64 data processing instruction.
2891 Return TRUE on success; otherwise return FALSE. */
2893 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2895 const struct aarch64_name_value_pair
*shift_op
;
2896 enum aarch64_modifier_kind kind
;
2902 for (p
= *str
; ISALPHA (*p
); p
++)
2907 set_syntax_error (_("shift expression expected"));
2911 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2913 if (shift_op
== NULL
)
2915 set_syntax_error (_("shift operator expected"));
2919 kind
= aarch64_get_operand_modifier (shift_op
);
2921 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2923 set_syntax_error (_("invalid use of 'MSL'"));
2927 if (kind
== AARCH64_MOD_MUL
2928 && mode
!= SHIFTED_MUL
)
2930 set_syntax_error (_("invalid use of 'MUL'"));
2936 case SHIFTED_LOGIC_IMM
:
2937 if (aarch64_extend_operator_p (kind
) == TRUE
)
2939 set_syntax_error (_("extending shift is not permitted"));
2944 case SHIFTED_ARITH_IMM
:
2945 if (kind
== AARCH64_MOD_ROR
)
2947 set_syntax_error (_("'ROR' shift is not permitted"));
2953 if (kind
!= AARCH64_MOD_LSL
)
2955 set_syntax_error (_("only 'LSL' shift is permitted"));
2961 if (kind
!= AARCH64_MOD_MUL
)
2963 set_syntax_error (_("only 'MUL' is permitted"));
2968 case SHIFTED_REG_OFFSET
:
2969 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2970 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2972 set_fatal_syntax_error
2973 (_("invalid shift for the register offset addressing mode"));
2978 case SHIFTED_LSL_MSL
:
2979 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2981 set_syntax_error (_("invalid shift operator"));
2990 /* Whitespace can appear here if the next thing is a bare digit. */
2991 skip_whitespace (p
);
2993 /* Parse shift amount. */
2995 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2996 exp
.X_op
= O_absent
;
2999 if (is_immediate_prefix (*p
))
3004 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3006 if (exp
.X_op
== O_absent
)
3008 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
3010 set_syntax_error (_("missing shift amount"));
3013 operand
->shifter
.amount
= 0;
3015 else if (exp
.X_op
!= O_constant
)
3017 set_syntax_error (_("constant shift amount required"));
3020 /* For parsing purposes, MUL #n has no inherent range. The range
3021 depends on the operand and will be checked by operand-specific
3023 else if (kind
!= AARCH64_MOD_MUL
3024 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3026 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3031 operand
->shifter
.amount
= exp
.X_add_number
;
3032 operand
->shifter
.amount_present
= 1;
3035 operand
->shifter
.operator_present
= 1;
3036 operand
->shifter
.kind
= kind
;
3042 /* Parse a <shifter_operand> for a data processing instruction:
3045 #<immediate>, LSL #imm
3047 Validation of immediate operands is deferred to md_apply_fix.
3049 Return TRUE on success; otherwise return FALSE. */
3052 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3053 enum parse_shift_mode mode
)
3057 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3062 /* Accept an immediate expression. */
3063 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3066 /* Accept optional LSL for arithmetic immediate values. */
3067 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3068 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3071 /* Not accept any shifter for logical immediate values. */
3072 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3073 && parse_shift (&p
, operand
, mode
))
3075 set_syntax_error (_("unexpected shift operator"));
3083 /* Parse a <shifter_operand> for a data processing instruction:
3088 #<immediate>, LSL #imm
3090 where <shift> is handled by parse_shift above, and the last two
3091 cases are handled by the function above.
3093 Validation of immediate operands is deferred to md_apply_fix.
3095 Return TRUE on success; otherwise return FALSE. */
3098 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3099 enum parse_shift_mode mode
)
3101 const reg_entry
*reg
;
3102 aarch64_opnd_qualifier_t qualifier
;
3103 enum aarch64_operand_class opd_class
3104 = aarch64_get_operand_class (operand
->type
);
3106 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3109 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3111 set_syntax_error (_("unexpected register in the immediate operand"));
3115 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3117 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3121 operand
->reg
.regno
= reg
->number
;
3122 operand
->qualifier
= qualifier
;
3124 /* Accept optional shift operation on register. */
3125 if (! skip_past_comma (str
))
3128 if (! parse_shift (str
, operand
, mode
))
3133 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3136 (_("integer register expected in the extended/shifted operand "
3141 /* We have a shifted immediate variable. */
3142 return parse_shifter_operand_imm (str
, operand
, mode
);
3145 /* Return TRUE on success; return FALSE otherwise. */
3148 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3149 enum parse_shift_mode mode
)
3153 /* Determine if we have the sequence of characters #: or just :
3154 coming next. If we do, then we check for a :rello: relocation
3155 modifier. If we don't, punt the whole lot to
3156 parse_shifter_operand. */
3158 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3160 struct reloc_table_entry
*entry
;
3168 /* Try to parse a relocation. Anything else is an error. */
3169 if (!(entry
= find_reloc_table_entry (str
)))
3171 set_syntax_error (_("unknown relocation modifier"));
3175 if (entry
->add_type
== 0)
3178 (_("this relocation modifier is not allowed on this instruction"));
3182 /* Save str before we decompose it. */
3185 /* Next, we parse the expression. */
3186 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3189 /* Record the relocation type (use the ADD variant here). */
3190 inst
.reloc
.type
= entry
->add_type
;
3191 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3193 /* If str is empty, we've reached the end, stop here. */
3197 /* Otherwise, we have a shifted reloc modifier, so rewind to
3198 recover the variable name and continue parsing for the shifter. */
3200 return parse_shifter_operand_imm (str
, operand
, mode
);
3203 return parse_shifter_operand (str
, operand
, mode
);
3206 /* Parse all forms of an address expression. Information is written
3207 to *OPERAND and/or inst.reloc.
3209 The A64 instruction set has the following addressing modes:
3212 [base] // in SIMD ld/st structure
3213 [base{,#0}] // in ld/st exclusive
3215 [base,Xm{,LSL #imm}]
3216 [base,Xm,SXTX {#imm}]
3217 [base,Wm,(S|U)XTW {#imm}]
3222 [base],Xm // in SIMD ld/st structure
3223 PC-relative (literal)
3227 (As a convenience, the notation "=immediate" is permitted in conjunction
3228 with the pc-relative literal load instructions to automatically place an
3229 immediate value or symbolic address in a nearby literal pool and generate
3230 a hidden label which references it.)
3232 Upon a successful parsing, the address structure in *OPERAND will be
3233 filled in the following way:
3235 .base_regno = <base>
3236 .offset.is_reg // 1 if the offset is a register
3238 .offset.regno = <Rm>
3240 For different addressing modes defined in the A64 ISA:
3243 .pcrel=0; .preind=1; .postind=0; .writeback=0
3245 .pcrel=0; .preind=1; .postind=0; .writeback=1
3247 .pcrel=0; .preind=0; .postind=1; .writeback=1
3248 PC-relative (literal)
3249 .pcrel=1; .preind=1; .postind=0; .writeback=0
3251 The shift/extension information, if any, will be stored in .shifter.
3253 It is the caller's responsibility to check for addressing modes not
3254 supported by the instruction, and to set inst.reloc.type. */
3257 parse_address_main (char **str
, aarch64_opnd_info
*operand
)
3260 const reg_entry
*reg
;
3261 aarch64_opnd_qualifier_t base_qualifier
;
3262 aarch64_opnd_qualifier_t offset_qualifier
;
3263 expressionS
*exp
= &inst
.reloc
.exp
;
3265 if (! skip_past_char (&p
, '['))
3267 /* =immediate or label. */
3268 operand
->addr
.pcrel
= 1;
3269 operand
->addr
.preind
= 1;
3271 /* #:<reloc_op>:<symbol> */
3272 skip_past_char (&p
, '#');
3273 if (skip_past_char (&p
, ':'))
3275 bfd_reloc_code_real_type ty
;
3276 struct reloc_table_entry
*entry
;
3278 /* Try to parse a relocation modifier. Anything else is
3280 entry
= find_reloc_table_entry (&p
);
3283 set_syntax_error (_("unknown relocation modifier"));
3287 switch (operand
->type
)
3289 case AARCH64_OPND_ADDR_PCREL21
:
3291 ty
= entry
->adr_type
;
3295 ty
= entry
->ld_literal_type
;
3302 (_("this relocation modifier is not allowed on this "
3308 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3310 set_syntax_error (_("invalid relocation expression"));
3314 /* #:<reloc_op>:<expr> */
3315 /* Record the relocation type. */
3316 inst
.reloc
.type
= ty
;
3317 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3322 if (skip_past_char (&p
, '='))
3323 /* =immediate; need to generate the literal in the literal pool. */
3324 inst
.gen_lit_pool
= 1;
3326 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3328 set_syntax_error (_("invalid address"));
3339 reg
= aarch64_reg_parse_32_64 (&p
, &base_qualifier
);
3340 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R64_SP
))
3342 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R64_SP
)));
3345 operand
->addr
.base_regno
= reg
->number
;
3348 if (skip_past_comma (&p
))
3351 operand
->addr
.preind
= 1;
3353 reg
= aarch64_reg_parse_32_64 (&p
, &offset_qualifier
);
3356 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3358 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3363 operand
->addr
.offset
.regno
= reg
->number
;
3364 operand
->addr
.offset
.is_reg
= 1;
3365 /* Shifted index. */
3366 if (skip_past_comma (&p
))
3369 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3370 /* Use the diagnostics set in parse_shift, so not set new
3371 error message here. */
3375 [base,Xm{,LSL #imm}]
3376 [base,Xm,SXTX {#imm}]
3377 [base,Wm,(S|U)XTW {#imm}] */
3378 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3379 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3380 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3382 if (offset_qualifier
== AARCH64_OPND_QLF_W
)
3384 set_syntax_error (_("invalid use of 32-bit register offset"));
3388 else if (offset_qualifier
== AARCH64_OPND_QLF_X
)
3390 set_syntax_error (_("invalid use of 64-bit register offset"));
3396 /* [Xn,#:<reloc_op>:<symbol> */
3397 skip_past_char (&p
, '#');
3398 if (skip_past_char (&p
, ':'))
3400 struct reloc_table_entry
*entry
;
3402 /* Try to parse a relocation modifier. Anything else is
3404 if (!(entry
= find_reloc_table_entry (&p
)))
3406 set_syntax_error (_("unknown relocation modifier"));
3410 if (entry
->ldst_type
== 0)
3413 (_("this relocation modifier is not allowed on this "
3418 /* [Xn,#:<reloc_op>: */
3419 /* We now have the group relocation table entry corresponding to
3420 the name in the assembler source. Next, we parse the
3422 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3424 set_syntax_error (_("invalid relocation expression"));
3428 /* [Xn,#:<reloc_op>:<expr> */
3429 /* Record the load/store relocation type. */
3430 inst
.reloc
.type
= entry
->ldst_type
;
3431 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3433 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3435 set_syntax_error (_("invalid expression in the address"));
3442 if (! skip_past_char (&p
, ']'))
3444 set_syntax_error (_("']' expected"));
3448 if (skip_past_char (&p
, '!'))
3450 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3452 set_syntax_error (_("register offset not allowed in pre-indexed "
3453 "addressing mode"));
3457 operand
->addr
.writeback
= 1;
3459 else if (skip_past_comma (&p
))
3462 operand
->addr
.postind
= 1;
3463 operand
->addr
.writeback
= 1;
3465 if (operand
->addr
.preind
)
3467 set_syntax_error (_("cannot combine pre- and post-indexing"));
3471 reg
= aarch64_reg_parse_32_64 (&p
, &offset_qualifier
);
3475 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3477 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3481 operand
->addr
.offset
.regno
= reg
->number
;
3482 operand
->addr
.offset
.is_reg
= 1;
3484 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3487 set_syntax_error (_("invalid expression in the address"));
3492 /* If at this point neither .preind nor .postind is set, we have a
3493 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3494 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3496 if (operand
->addr
.writeback
)
3499 set_syntax_error (_("missing offset in the pre-indexed address"));
3502 operand
->addr
.preind
= 1;
3503 inst
.reloc
.exp
.X_op
= O_constant
;
3504 inst
.reloc
.exp
.X_add_number
= 0;
3511 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3514 parse_address (char **str
, aarch64_opnd_info
*operand
)
3516 return parse_address_main (str
, operand
);
3519 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3520 Return TRUE on success; otherwise return FALSE. */
3522 parse_half (char **str
, int *internal_fixup_p
)
3526 skip_past_char (&p
, '#');
3528 gas_assert (internal_fixup_p
);
3529 *internal_fixup_p
= 0;
3533 struct reloc_table_entry
*entry
;
3535 /* Try to parse a relocation. Anything else is an error. */
3537 if (!(entry
= find_reloc_table_entry (&p
)))
3539 set_syntax_error (_("unknown relocation modifier"));
3543 if (entry
->movw_type
== 0)
3546 (_("this relocation modifier is not allowed on this instruction"));
3550 inst
.reloc
.type
= entry
->movw_type
;
3553 *internal_fixup_p
= 1;
3555 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3562 /* Parse an operand for an ADRP instruction:
3564 Return TRUE on success; otherwise return FALSE. */
3567 parse_adrp (char **str
)
3574 struct reloc_table_entry
*entry
;
3576 /* Try to parse a relocation. Anything else is an error. */
3578 if (!(entry
= find_reloc_table_entry (&p
)))
3580 set_syntax_error (_("unknown relocation modifier"));
3584 if (entry
->adrp_type
== 0)
3587 (_("this relocation modifier is not allowed on this instruction"));
3591 inst
.reloc
.type
= entry
->adrp_type
;
3594 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3596 inst
.reloc
.pc_rel
= 1;
3598 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3605 /* Miscellaneous. */
3607 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3608 of SIZE tokens in which index I gives the token for field value I,
3609 or is null if field value I is invalid. REG_TYPE says which register
3610 names should be treated as registers rather than as symbolic immediates.
3612 Return true on success, moving *STR past the operand and storing the
3613 field value in *VAL. */
3616 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3617 size_t size
, aarch64_reg_type reg_type
)
3623 /* Match C-like tokens. */
3625 while (ISALNUM (*q
))
3628 for (i
= 0; i
< size
; ++i
)
3630 && strncasecmp (array
[i
], p
, q
- p
) == 0
3631 && array
[i
][q
- p
] == 0)
3638 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3641 if (exp
.X_op
== O_constant
3642 && (uint64_t) exp
.X_add_number
< size
)
3644 *val
= exp
.X_add_number
;
3649 /* Use the default error for this operand. */
3653 /* Parse an option for a preload instruction. Returns the encoding for the
3654 option, or PARSE_FAIL. */
3657 parse_pldop (char **str
)
3660 const struct aarch64_name_value_pair
*o
;
3663 while (ISALNUM (*q
))
3666 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3674 /* Parse an option for a barrier instruction. Returns the encoding for the
3675 option, or PARSE_FAIL. */
3678 parse_barrier (char **str
)
3681 const asm_barrier_opt
*o
;
3684 while (ISALPHA (*q
))
3687 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3695 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3696 return 0 if successful. Otherwise return PARSE_FAIL. */
3699 parse_barrier_psb (char **str
,
3700 const struct aarch64_name_value_pair
** hint_opt
)
3703 const struct aarch64_name_value_pair
*o
;
3706 while (ISALPHA (*q
))
3709 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3712 set_fatal_syntax_error
3713 ( _("unknown or missing option to PSB"));
3717 if (o
->value
!= 0x11)
3719 /* PSB only accepts option name 'CSYNC'. */
3721 (_("the specified option is not accepted for PSB"));
3730 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3731 Returns the encoding for the option, or PARSE_FAIL.
3733 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3734 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3736 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3737 field, otherwise as a system register.
3741 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3742 int imple_defined_p
, int pstatefield_p
)
3746 const aarch64_sys_reg
*o
;
3750 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3752 *p
++ = TOLOWER (*q
);
3754 /* Assert that BUF be large enough. */
3755 gas_assert (p
- buf
== q
- *str
);
3757 o
= hash_find (sys_regs
, buf
);
3760 if (!imple_defined_p
)
3764 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3765 unsigned int op0
, op1
, cn
, cm
, op2
;
3767 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3770 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3772 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3777 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3778 as_bad (_("selected processor does not support PSTATE field "
3780 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3781 as_bad (_("selected processor does not support system register "
3783 if (aarch64_sys_reg_deprecated_p (o
))
3784 as_warn (_("system register name '%s' is deprecated and may be "
3785 "removed in a future release"), buf
);
3793 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3794 for the option, or NULL. */
3796 static const aarch64_sys_ins_reg
*
3797 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3801 const aarch64_sys_ins_reg
*o
;
3804 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3806 *p
++ = TOLOWER (*q
);
3809 o
= hash_find (sys_ins_regs
, buf
);
3813 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3814 as_bad (_("selected processor does not support system register "
3821 #define po_char_or_fail(chr) do { \
3822 if (! skip_past_char (&str, chr)) \
3826 #define po_reg_or_fail(regtype) do { \
3827 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3828 if (val == PARSE_FAIL) \
3830 set_default_error (); \
3835 #define po_int_reg_or_fail(reg_type) do { \
3836 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3837 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3839 set_default_error (); \
3842 info->reg.regno = reg->number; \
3843 info->qualifier = qualifier; \
3846 #define po_imm_nc_or_fail() do { \
3847 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3851 #define po_imm_or_fail(min, max) do { \
3852 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3854 if (val < min || val > max) \
3856 set_fatal_syntax_error (_("immediate value out of range "\
3857 #min " to "#max)); \
3862 #define po_enum_or_fail(array) do { \
3863 if (!parse_enum_string (&str, &val, array, \
3864 ARRAY_SIZE (array), imm_reg_type)) \
3868 #define po_misc_or_fail(expr) do { \
3873 /* encode the 12-bit imm field of Add/sub immediate */
3874 static inline uint32_t
3875 encode_addsub_imm (uint32_t imm
)
3880 /* encode the shift amount field of Add/sub immediate */
3881 static inline uint32_t
3882 encode_addsub_imm_shift_amount (uint32_t cnt
)
3888 /* encode the imm field of Adr instruction */
3889 static inline uint32_t
3890 encode_adr_imm (uint32_t imm
)
3892 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3893 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3896 /* encode the immediate field of Move wide immediate */
3897 static inline uint32_t
3898 encode_movw_imm (uint32_t imm
)
3903 /* encode the 26-bit offset of unconditional branch */
3904 static inline uint32_t
3905 encode_branch_ofs_26 (uint32_t ofs
)
3907 return ofs
& ((1 << 26) - 1);
3910 /* encode the 19-bit offset of conditional branch and compare & branch */
3911 static inline uint32_t
3912 encode_cond_branch_ofs_19 (uint32_t ofs
)
3914 return (ofs
& ((1 << 19) - 1)) << 5;
3917 /* encode the 19-bit offset of ld literal */
3918 static inline uint32_t
3919 encode_ld_lit_ofs_19 (uint32_t ofs
)
3921 return (ofs
& ((1 << 19) - 1)) << 5;
3924 /* Encode the 14-bit offset of test & branch. */
3925 static inline uint32_t
3926 encode_tst_branch_ofs_14 (uint32_t ofs
)
3928 return (ofs
& ((1 << 14) - 1)) << 5;
3931 /* Encode the 16-bit imm field of svc/hvc/smc. */
3932 static inline uint32_t
3933 encode_svc_imm (uint32_t imm
)
3938 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3939 static inline uint32_t
3940 reencode_addsub_switch_add_sub (uint32_t opcode
)
3942 return opcode
^ (1 << 30);
3945 static inline uint32_t
3946 reencode_movzn_to_movz (uint32_t opcode
)
3948 return opcode
| (1 << 30);
3951 static inline uint32_t
3952 reencode_movzn_to_movn (uint32_t opcode
)
3954 return opcode
& ~(1 << 30);
3957 /* Overall per-instruction processing. */
3959 /* We need to be able to fix up arbitrary expressions in some statements.
3960 This is so that we can handle symbols that are an arbitrary distance from
3961 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3962 which returns part of an address in a form which will be valid for
3963 a data instruction. We do this by pushing the expression into a symbol
3964 in the expr_section, and creating a fix for that. */
3967 fix_new_aarch64 (fragS
* frag
,
3969 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3979 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3983 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3990 /* Diagnostics on operands errors. */
3992 /* By default, output verbose error message.
3993 Disable the verbose error message by -mno-verbose-error. */
3994 static int verbose_error_p
= 1;
3996 #ifdef DEBUG_AARCH64
3997 /* N.B. this is only for the purpose of debugging. */
3998 const char* operand_mismatch_kind_names
[] =
4001 "AARCH64_OPDE_RECOVERABLE",
4002 "AARCH64_OPDE_SYNTAX_ERROR",
4003 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4004 "AARCH64_OPDE_INVALID_VARIANT",
4005 "AARCH64_OPDE_OUT_OF_RANGE",
4006 "AARCH64_OPDE_UNALIGNED",
4007 "AARCH64_OPDE_REG_LIST",
4008 "AARCH64_OPDE_OTHER_ERROR",
4010 #endif /* DEBUG_AARCH64 */
4012 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4014 When multiple errors of different kinds are found in the same assembly
4015 line, only the error of the highest severity will be picked up for
4016 issuing the diagnostics. */
4018 static inline bfd_boolean
4019 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4020 enum aarch64_operand_error_kind rhs
)
4022 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4023 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4024 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4025 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4026 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4027 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4028 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4029 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4033 /* Helper routine to get the mnemonic name from the assembly instruction
4034 line; should only be called for the diagnosis purpose, as there is
4035 string copy operation involved, which may affect the runtime
4036 performance if used in elsewhere. */
4039 get_mnemonic_name (const char *str
)
4041 static char mnemonic
[32];
4044 /* Get the first 15 bytes and assume that the full name is included. */
4045 strncpy (mnemonic
, str
, 31);
4046 mnemonic
[31] = '\0';
4048 /* Scan up to the end of the mnemonic, which must end in white space,
4049 '.', or end of string. */
4050 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4055 /* Append '...' to the truncated long name. */
4056 if (ptr
- mnemonic
== 31)
4057 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4063 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4065 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4066 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4069 /* Data strutures storing one user error in the assembly code related to
4072 struct operand_error_record
4074 const aarch64_opcode
*opcode
;
4075 aarch64_operand_error detail
;
4076 struct operand_error_record
*next
;
4079 typedef struct operand_error_record operand_error_record
;
4081 struct operand_errors
4083 operand_error_record
*head
;
4084 operand_error_record
*tail
;
4087 typedef struct operand_errors operand_errors
;
4089 /* Top-level data structure reporting user errors for the current line of
4091 The way md_assemble works is that all opcodes sharing the same mnemonic
4092 name are iterated to find a match to the assembly line. In this data
4093 structure, each of the such opcodes will have one operand_error_record
4094 allocated and inserted. In other words, excessive errors related with
4095 a single opcode are disregarded. */
4096 operand_errors operand_error_report
;
4098 /* Free record nodes. */
4099 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4101 /* Initialize the data structure that stores the operand mismatch
4102 information on assembling one line of the assembly code. */
4104 init_operand_error_report (void)
4106 if (operand_error_report
.head
!= NULL
)
4108 gas_assert (operand_error_report
.tail
!= NULL
);
4109 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4110 free_opnd_error_record_nodes
= operand_error_report
.head
;
4111 operand_error_report
.head
= NULL
;
4112 operand_error_report
.tail
= NULL
;
4115 gas_assert (operand_error_report
.tail
== NULL
);
4118 /* Return TRUE if some operand error has been recorded during the
4119 parsing of the current assembly line using the opcode *OPCODE;
4120 otherwise return FALSE. */
4121 static inline bfd_boolean
4122 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4124 operand_error_record
*record
= operand_error_report
.head
;
4125 return record
&& record
->opcode
== opcode
;
4128 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4129 OPCODE field is initialized with OPCODE.
4130 N.B. only one record for each opcode, i.e. the maximum of one error is
4131 recorded for each instruction template. */
4134 add_operand_error_record (const operand_error_record
* new_record
)
4136 const aarch64_opcode
*opcode
= new_record
->opcode
;
4137 operand_error_record
* record
= operand_error_report
.head
;
4139 /* The record may have been created for this opcode. If not, we need
4141 if (! opcode_has_operand_error_p (opcode
))
4143 /* Get one empty record. */
4144 if (free_opnd_error_record_nodes
== NULL
)
4146 record
= XNEW (operand_error_record
);
4150 record
= free_opnd_error_record_nodes
;
4151 free_opnd_error_record_nodes
= record
->next
;
4153 record
->opcode
= opcode
;
4154 /* Insert at the head. */
4155 record
->next
= operand_error_report
.head
;
4156 operand_error_report
.head
= record
;
4157 if (operand_error_report
.tail
== NULL
)
4158 operand_error_report
.tail
= record
;
4160 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4161 && record
->detail
.index
<= new_record
->detail
.index
4162 && operand_error_higher_severity_p (record
->detail
.kind
,
4163 new_record
->detail
.kind
))
4165 /* In the case of multiple errors found on operands related with a
4166 single opcode, only record the error of the leftmost operand and
4167 only if the error is of higher severity. */
4168 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4169 " the existing error %s on operand %d",
4170 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4171 new_record
->detail
.index
,
4172 operand_mismatch_kind_names
[record
->detail
.kind
],
4173 record
->detail
.index
);
4177 record
->detail
= new_record
->detail
;
4181 record_operand_error_info (const aarch64_opcode
*opcode
,
4182 aarch64_operand_error
*error_info
)
4184 operand_error_record record
;
4185 record
.opcode
= opcode
;
4186 record
.detail
= *error_info
;
4187 add_operand_error_record (&record
);
4190 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4191 error message *ERROR, for operand IDX (count from 0). */
4194 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4195 enum aarch64_operand_error_kind kind
,
4198 aarch64_operand_error info
;
4199 memset(&info
, 0, sizeof (info
));
4203 record_operand_error_info (opcode
, &info
);
4207 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4208 enum aarch64_operand_error_kind kind
,
4209 const char* error
, const int *extra_data
)
4211 aarch64_operand_error info
;
4215 info
.data
[0] = extra_data
[0];
4216 info
.data
[1] = extra_data
[1];
4217 info
.data
[2] = extra_data
[2];
4218 record_operand_error_info (opcode
, &info
);
4222 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4223 const char* error
, int lower_bound
,
4226 int data
[3] = {lower_bound
, upper_bound
, 0};
4227 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4231 /* Remove the operand error record for *OPCODE. */
4232 static void ATTRIBUTE_UNUSED
4233 remove_operand_error_record (const aarch64_opcode
*opcode
)
4235 if (opcode_has_operand_error_p (opcode
))
4237 operand_error_record
* record
= operand_error_report
.head
;
4238 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4239 operand_error_report
.head
= record
->next
;
4240 record
->next
= free_opnd_error_record_nodes
;
4241 free_opnd_error_record_nodes
= record
;
4242 if (operand_error_report
.head
== NULL
)
4244 gas_assert (operand_error_report
.tail
== record
);
4245 operand_error_report
.tail
= NULL
;
4250 /* Given the instruction in *INSTR, return the index of the best matched
4251 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4253 Return -1 if there is no qualifier sequence; return the first match
4254 if there is multiple matches found. */
4257 find_best_match (const aarch64_inst
*instr
,
4258 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4260 int i
, num_opnds
, max_num_matched
, idx
;
4262 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4265 DEBUG_TRACE ("no operand");
4269 max_num_matched
= 0;
4272 /* For each pattern. */
4273 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4276 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4278 /* Most opcodes has much fewer patterns in the list. */
4279 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4281 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4285 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4286 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4289 if (num_matched
> max_num_matched
)
4291 max_num_matched
= num_matched
;
4296 DEBUG_TRACE ("return with %d", idx
);
4300 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4301 corresponding operands in *INSTR. */
4304 assign_qualifier_sequence (aarch64_inst
*instr
,
4305 const aarch64_opnd_qualifier_t
*qualifiers
)
4308 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4309 gas_assert (num_opnds
);
4310 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4311 instr
->operands
[i
].qualifier
= *qualifiers
;
4314 /* Print operands for the diagnosis purpose. */
4317 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4318 const aarch64_opnd_info
*opnds
)
4322 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4326 /* We regard the opcode operand info more, however we also look into
4327 the inst->operands to support the disassembling of the optional
4329 The two operand code should be the same in all cases, apart from
4330 when the operand can be optional. */
4331 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4332 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4335 /* Generate the operand string in STR. */
4336 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4340 strcat (buf
, i
== 0 ? " " : ",");
4342 /* Append the operand string. */
4347 /* Send to stderr a string as information. */
4350 output_info (const char *format
, ...)
4356 file
= as_where (&line
);
4360 fprintf (stderr
, "%s:%u: ", file
, line
);
4362 fprintf (stderr
, "%s: ", file
);
4364 fprintf (stderr
, _("Info: "));
4365 va_start (args
, format
);
4366 vfprintf (stderr
, format
, args
);
4368 (void) putc ('\n', stderr
);
4371 /* Output one operand error record. */
4374 output_operand_error_record (const operand_error_record
*record
, char *str
)
4376 const aarch64_operand_error
*detail
= &record
->detail
;
4377 int idx
= detail
->index
;
4378 const aarch64_opcode
*opcode
= record
->opcode
;
4379 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4380 : AARCH64_OPND_NIL
);
4382 switch (detail
->kind
)
4384 case AARCH64_OPDE_NIL
:
4388 case AARCH64_OPDE_SYNTAX_ERROR
:
4389 case AARCH64_OPDE_RECOVERABLE
:
4390 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4391 case AARCH64_OPDE_OTHER_ERROR
:
4392 /* Use the prepared error message if there is, otherwise use the
4393 operand description string to describe the error. */
4394 if (detail
->error
!= NULL
)
4397 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4399 as_bad (_("%s at operand %d -- `%s'"),
4400 detail
->error
, idx
+ 1, str
);
4404 gas_assert (idx
>= 0);
4405 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4406 aarch64_get_operand_desc (opd_code
), str
);
4410 case AARCH64_OPDE_INVALID_VARIANT
:
4411 as_bad (_("operand mismatch -- `%s'"), str
);
4412 if (verbose_error_p
)
4414 /* We will try to correct the erroneous instruction and also provide
4415 more information e.g. all other valid variants.
4417 The string representation of the corrected instruction and other
4418 valid variants are generated by
4420 1) obtaining the intermediate representation of the erroneous
4422 2) manipulating the IR, e.g. replacing the operand qualifier;
4423 3) printing out the instruction by calling the printer functions
4424 shared with the disassembler.
4426 The limitation of this method is that the exact input assembly
4427 line cannot be accurately reproduced in some cases, for example an
4428 optional operand present in the actual assembly line will be
4429 omitted in the output; likewise for the optional syntax rules,
4430 e.g. the # before the immediate. Another limitation is that the
4431 assembly symbols and relocation operations in the assembly line
4432 currently cannot be printed out in the error report. Last but not
4433 least, when there is other error(s) co-exist with this error, the
4434 'corrected' instruction may be still incorrect, e.g. given
4435 'ldnp h0,h1,[x0,#6]!'
4436 this diagnosis will provide the version:
4437 'ldnp s0,s1,[x0,#6]!'
4438 which is still not right. */
4439 size_t len
= strlen (get_mnemonic_name (str
));
4443 aarch64_inst
*inst_base
= &inst
.base
;
4444 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4447 reset_aarch64_instruction (&inst
);
4448 inst_base
->opcode
= opcode
;
4450 /* Reset the error report so that there is no side effect on the
4451 following operand parsing. */
4452 init_operand_error_report ();
4455 result
= parse_operands (str
+ len
, opcode
)
4456 && programmer_friendly_fixup (&inst
);
4457 gas_assert (result
);
4458 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4460 gas_assert (!result
);
4462 /* Find the most matched qualifier sequence. */
4463 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4464 gas_assert (qlf_idx
> -1);
4466 /* Assign the qualifiers. */
4467 assign_qualifier_sequence (inst_base
,
4468 opcode
->qualifiers_list
[qlf_idx
]);
4470 /* Print the hint. */
4471 output_info (_(" did you mean this?"));
4472 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4473 print_operands (buf
, opcode
, inst_base
->operands
);
4474 output_info (_(" %s"), buf
);
4476 /* Print out other variant(s) if there is any. */
4478 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4479 output_info (_(" other valid variant(s):"));
4481 /* For each pattern. */
4482 qualifiers_list
= opcode
->qualifiers_list
;
4483 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4485 /* Most opcodes has much fewer patterns in the list.
4486 First NIL qualifier indicates the end in the list. */
4487 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4492 /* Mnemonics name. */
4493 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4495 /* Assign the qualifiers. */
4496 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4498 /* Print instruction. */
4499 print_operands (buf
, opcode
, inst_base
->operands
);
4501 output_info (_(" %s"), buf
);
4507 case AARCH64_OPDE_UNTIED_OPERAND
:
4508 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4509 detail
->index
+ 1, str
);
4512 case AARCH64_OPDE_OUT_OF_RANGE
:
4513 if (detail
->data
[0] != detail
->data
[1])
4514 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4515 detail
->error
? detail
->error
: _("immediate value"),
4516 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4518 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4519 detail
->error
? detail
->error
: _("immediate value"),
4520 detail
->data
[0], idx
+ 1, str
);
4523 case AARCH64_OPDE_REG_LIST
:
4524 if (detail
->data
[0] == 1)
4525 as_bad (_("invalid number of registers in the list; "
4526 "only 1 register is expected at operand %d -- `%s'"),
4529 as_bad (_("invalid number of registers in the list; "
4530 "%d registers are expected at operand %d -- `%s'"),
4531 detail
->data
[0], idx
+ 1, str
);
4534 case AARCH64_OPDE_UNALIGNED
:
4535 as_bad (_("immediate value should be a multiple of "
4536 "%d at operand %d -- `%s'"),
4537 detail
->data
[0], idx
+ 1, str
);
4546 /* Process and output the error message about the operand mismatching.
4548 When this function is called, the operand error information had
4549 been collected for an assembly line and there will be multiple
4550 errors in the case of mulitple instruction templates; output the
4551 error message that most closely describes the problem. */
4554 output_operand_error_report (char *str
)
4556 int largest_error_pos
;
4557 const char *msg
= NULL
;
4558 enum aarch64_operand_error_kind kind
;
4559 operand_error_record
*curr
;
4560 operand_error_record
*head
= operand_error_report
.head
;
4561 operand_error_record
*record
= NULL
;
4563 /* No error to report. */
4567 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4569 /* Only one error. */
4570 if (head
== operand_error_report
.tail
)
4572 DEBUG_TRACE ("single opcode entry with error kind: %s",
4573 operand_mismatch_kind_names
[head
->detail
.kind
]);
4574 output_operand_error_record (head
, str
);
4578 /* Find the error kind of the highest severity. */
4579 DEBUG_TRACE ("multiple opcode entres with error kind");
4580 kind
= AARCH64_OPDE_NIL
;
4581 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4583 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4584 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4585 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4586 kind
= curr
->detail
.kind
;
4588 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4590 /* Pick up one of errors of KIND to report. */
4591 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4592 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4594 if (curr
->detail
.kind
!= kind
)
4596 /* If there are multiple errors, pick up the one with the highest
4597 mismatching operand index. In the case of multiple errors with
4598 the equally highest operand index, pick up the first one or the
4599 first one with non-NULL error message. */
4600 if (curr
->detail
.index
> largest_error_pos
4601 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4602 && curr
->detail
.error
!= NULL
))
4604 largest_error_pos
= curr
->detail
.index
;
4606 msg
= record
->detail
.error
;
4610 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4611 DEBUG_TRACE ("Pick up error kind %s to report",
4612 operand_mismatch_kind_names
[record
->detail
.kind
]);
4615 output_operand_error_record (record
, str
);
4618 /* Write an AARCH64 instruction to buf - always little-endian. */
4620 put_aarch64_insn (char *buf
, uint32_t insn
)
4622 unsigned char *where
= (unsigned char *) buf
;
4624 where
[1] = insn
>> 8;
4625 where
[2] = insn
>> 16;
4626 where
[3] = insn
>> 24;
4630 get_aarch64_insn (char *buf
)
4632 unsigned char *where
= (unsigned char *) buf
;
4634 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4639 output_inst (struct aarch64_inst
*new_inst
)
4643 to
= frag_more (INSN_SIZE
);
4645 frag_now
->tc_frag_data
.recorded
= 1;
4647 put_aarch64_insn (to
, inst
.base
.value
);
4649 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4651 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4652 INSN_SIZE
, &inst
.reloc
.exp
,
4655 DEBUG_TRACE ("Prepared relocation fix up");
4656 /* Don't check the addend value against the instruction size,
4657 that's the job of our code in md_apply_fix(). */
4658 fixp
->fx_no_overflow
= 1;
4659 if (new_inst
!= NULL
)
4660 fixp
->tc_fix_data
.inst
= new_inst
;
4661 if (aarch64_gas_internal_fixup_p ())
4663 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4664 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4665 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4669 dwarf2_emit_insn (INSN_SIZE
);
4672 /* Link together opcodes of the same name. */
4676 aarch64_opcode
*opcode
;
4677 struct templates
*next
;
4680 typedef struct templates templates
;
4683 lookup_mnemonic (const char *start
, int len
)
4685 templates
*templ
= NULL
;
4687 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4691 /* Subroutine of md_assemble, responsible for looking up the primary
4692 opcode from the mnemonic the user wrote. STR points to the
4693 beginning of the mnemonic. */
4696 opcode_lookup (char **str
)
4699 const aarch64_cond
*cond
;
4703 /* Scan up to the end of the mnemonic, which must end in white space,
4704 '.', or end of string. */
4705 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4712 inst
.cond
= COND_ALWAYS
;
4714 /* Handle a possible condition. */
4717 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4720 inst
.cond
= cond
->value
;
4734 if (inst
.cond
== COND_ALWAYS
)
4736 /* Look for unaffixed mnemonic. */
4737 return lookup_mnemonic (base
, len
);
4741 /* append ".c" to mnemonic if conditional */
4742 memcpy (condname
, base
, len
);
4743 memcpy (condname
+ len
, ".c", 2);
4746 return lookup_mnemonic (base
, len
);
4752 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4753 to a corresponding operand qualifier. */
4755 static inline aarch64_opnd_qualifier_t
4756 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4758 /* Element size in bytes indexed by vector_el_type. */
4759 const unsigned char ele_size
[5]
4761 const unsigned int ele_base
[5] =
4763 AARCH64_OPND_QLF_V_8B
,
4764 AARCH64_OPND_QLF_V_2H
,
4765 AARCH64_OPND_QLF_V_2S
,
4766 AARCH64_OPND_QLF_V_1D
,
4767 AARCH64_OPND_QLF_V_1Q
4770 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4771 goto vectype_conversion_fail
;
4773 if (vectype
->type
== NT_zero
)
4774 return AARCH64_OPND_QLF_P_Z
;
4775 if (vectype
->type
== NT_merge
)
4776 return AARCH64_OPND_QLF_P_M
;
4778 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4780 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4781 /* Vector element register. */
4782 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4785 /* Vector register. */
4786 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4789 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4790 goto vectype_conversion_fail
;
4792 /* The conversion is by calculating the offset from the base operand
4793 qualifier for the vector type. The operand qualifiers are regular
4794 enough that the offset can established by shifting the vector width by
4795 a vector-type dependent amount. */
4797 if (vectype
->type
== NT_b
)
4799 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4801 else if (vectype
->type
>= NT_d
)
4806 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4807 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4808 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4812 vectype_conversion_fail
:
4813 first_error (_("bad vector arrangement type"));
4814 return AARCH64_OPND_QLF_NIL
;
4817 /* Process an optional operand that is found omitted from the assembly line.
4818 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4819 instruction's opcode entry while IDX is the index of this omitted operand.
4823 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4824 int idx
, aarch64_opnd_info
*operand
)
4826 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4827 gas_assert (optional_operand_p (opcode
, idx
));
4828 gas_assert (!operand
->present
);
4832 case AARCH64_OPND_Rd
:
4833 case AARCH64_OPND_Rn
:
4834 case AARCH64_OPND_Rm
:
4835 case AARCH64_OPND_Rt
:
4836 case AARCH64_OPND_Rt2
:
4837 case AARCH64_OPND_Rs
:
4838 case AARCH64_OPND_Ra
:
4839 case AARCH64_OPND_Rt_SYS
:
4840 case AARCH64_OPND_Rd_SP
:
4841 case AARCH64_OPND_Rn_SP
:
4842 case AARCH64_OPND_Fd
:
4843 case AARCH64_OPND_Fn
:
4844 case AARCH64_OPND_Fm
:
4845 case AARCH64_OPND_Fa
:
4846 case AARCH64_OPND_Ft
:
4847 case AARCH64_OPND_Ft2
:
4848 case AARCH64_OPND_Sd
:
4849 case AARCH64_OPND_Sn
:
4850 case AARCH64_OPND_Sm
:
4851 case AARCH64_OPND_Vd
:
4852 case AARCH64_OPND_Vn
:
4853 case AARCH64_OPND_Vm
:
4854 case AARCH64_OPND_VdD1
:
4855 case AARCH64_OPND_VnD1
:
4856 operand
->reg
.regno
= default_value
;
4859 case AARCH64_OPND_Ed
:
4860 case AARCH64_OPND_En
:
4861 case AARCH64_OPND_Em
:
4862 operand
->reglane
.regno
= default_value
;
4865 case AARCH64_OPND_IDX
:
4866 case AARCH64_OPND_BIT_NUM
:
4867 case AARCH64_OPND_IMMR
:
4868 case AARCH64_OPND_IMMS
:
4869 case AARCH64_OPND_SHLL_IMM
:
4870 case AARCH64_OPND_IMM_VLSL
:
4871 case AARCH64_OPND_IMM_VLSR
:
4872 case AARCH64_OPND_CCMP_IMM
:
4873 case AARCH64_OPND_FBITS
:
4874 case AARCH64_OPND_UIMM4
:
4875 case AARCH64_OPND_UIMM3_OP1
:
4876 case AARCH64_OPND_UIMM3_OP2
:
4877 case AARCH64_OPND_IMM
:
4878 case AARCH64_OPND_WIDTH
:
4879 case AARCH64_OPND_UIMM7
:
4880 case AARCH64_OPND_NZCV
:
4881 case AARCH64_OPND_SVE_PATTERN
:
4882 case AARCH64_OPND_SVE_PRFOP
:
4883 operand
->imm
.value
= default_value
;
4886 case AARCH64_OPND_SVE_PATTERN_SCALED
:
4887 operand
->imm
.value
= default_value
;
4888 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
4889 operand
->shifter
.amount
= 1;
4892 case AARCH64_OPND_EXCEPTION
:
4893 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4896 case AARCH64_OPND_BARRIER_ISB
:
4897 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4904 /* Process the relocation type for move wide instructions.
4905 Return TRUE on success; otherwise return FALSE. */
4908 process_movw_reloc_info (void)
4913 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4915 if (inst
.base
.opcode
->op
== OP_MOVK
)
4916 switch (inst
.reloc
.type
)
4918 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4919 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4920 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4921 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4922 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4923 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4924 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4926 (_("the specified relocation type is not allowed for MOVK"));
4932 switch (inst
.reloc
.type
)
4934 case BFD_RELOC_AARCH64_MOVW_G0
:
4935 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4936 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4937 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4938 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4939 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4940 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4941 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4942 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4943 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4944 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4947 case BFD_RELOC_AARCH64_MOVW_G1
:
4948 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4949 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4950 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4951 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4952 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4953 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4954 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4955 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4956 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4957 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4960 case BFD_RELOC_AARCH64_MOVW_G2
:
4961 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4962 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4963 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4964 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4967 set_fatal_syntax_error
4968 (_("the specified relocation type is not allowed for 32-bit "
4974 case BFD_RELOC_AARCH64_MOVW_G3
:
4977 set_fatal_syntax_error
4978 (_("the specified relocation type is not allowed for 32-bit "
4985 /* More cases should be added when more MOVW-related relocation types
4986 are supported in GAS. */
4987 gas_assert (aarch64_gas_internal_fixup_p ());
4988 /* The shift amount should have already been set by the parser. */
4991 inst
.base
.operands
[1].shifter
.amount
= shift
;
4995 /* A primitive log caculator. */
4997 static inline unsigned int
4998 get_logsz (unsigned int size
)
5000 const unsigned char ls
[16] =
5001 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5007 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5008 return ls
[size
- 1];
5011 /* Determine and return the real reloc type code for an instruction
5012 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5014 static inline bfd_reloc_code_real_type
5015 ldst_lo12_determine_real_reloc_type (void)
5018 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5019 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5021 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
5023 BFD_RELOC_AARCH64_LDST8_LO12
,
5024 BFD_RELOC_AARCH64_LDST16_LO12
,
5025 BFD_RELOC_AARCH64_LDST32_LO12
,
5026 BFD_RELOC_AARCH64_LDST64_LO12
,
5027 BFD_RELOC_AARCH64_LDST128_LO12
5030 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5031 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5032 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5033 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5034 BFD_RELOC_AARCH64_NONE
5037 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5038 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5039 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5040 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5041 BFD_RELOC_AARCH64_NONE
5045 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5046 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5048 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
5049 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5051 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5053 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5055 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5057 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5058 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5059 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5060 gas_assert (logsz
<= 3);
5062 gas_assert (logsz
<= 4);
5064 /* In reloc.c, these pseudo relocation types should be defined in similar
5065 order as above reloc_ldst_lo12 array. Because the array index calcuation
5066 below relies on this. */
5067 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5070 /* Check whether a register list REGINFO is valid. The registers must be
5071 numbered in increasing order (modulo 32), in increments of one or two.
5073 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5076 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5079 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5081 uint32_t i
, nb_regs
, prev_regno
, incr
;
5083 nb_regs
= 1 + (reginfo
& 0x3);
5085 prev_regno
= reginfo
& 0x1f;
5086 incr
= accept_alternate
? 2 : 1;
5088 for (i
= 1; i
< nb_regs
; ++i
)
5090 uint32_t curr_regno
;
5092 curr_regno
= reginfo
& 0x1f;
5093 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5095 prev_regno
= curr_regno
;
5101 /* Generic instruction operand parser. This does no encoding and no
5102 semantic validation; it merely squirrels values away in the inst
5103 structure. Returns TRUE or FALSE depending on whether the
5104 specified grammar matched. */
5107 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5110 char *backtrack_pos
= 0;
5111 const enum aarch64_opnd
*operands
= opcode
->operands
;
5112 aarch64_reg_type imm_reg_type
;
5115 skip_whitespace (str
);
5117 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5119 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5122 const reg_entry
*reg
;
5123 int comma_skipped_p
= 0;
5124 aarch64_reg_type rtype
;
5125 struct vector_type_el vectype
;
5126 aarch64_opnd_qualifier_t qualifier
;
5127 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5128 aarch64_reg_type reg_type
;
5130 DEBUG_TRACE ("parse operand %d", i
);
5132 /* Assign the operand code. */
5133 info
->type
= operands
[i
];
5135 if (optional_operand_p (opcode
, i
))
5137 /* Remember where we are in case we need to backtrack. */
5138 gas_assert (!backtrack_pos
);
5139 backtrack_pos
= str
;
5142 /* Expect comma between operands; the backtrack mechanizm will take
5143 care of cases of omitted optional operand. */
5144 if (i
> 0 && ! skip_past_char (&str
, ','))
5146 set_syntax_error (_("comma expected between operands"));
5150 comma_skipped_p
= 1;
5152 switch (operands
[i
])
5154 case AARCH64_OPND_Rd
:
5155 case AARCH64_OPND_Rn
:
5156 case AARCH64_OPND_Rm
:
5157 case AARCH64_OPND_Rt
:
5158 case AARCH64_OPND_Rt2
:
5159 case AARCH64_OPND_Rs
:
5160 case AARCH64_OPND_Ra
:
5161 case AARCH64_OPND_Rt_SYS
:
5162 case AARCH64_OPND_PAIRREG
:
5163 po_int_reg_or_fail (REG_TYPE_R_Z
);
5166 case AARCH64_OPND_Rd_SP
:
5167 case AARCH64_OPND_Rn_SP
:
5168 po_int_reg_or_fail (REG_TYPE_R_SP
);
5171 case AARCH64_OPND_Rm_EXT
:
5172 case AARCH64_OPND_Rm_SFT
:
5173 po_misc_or_fail (parse_shifter_operand
5174 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5176 : SHIFTED_LOGIC_IMM
)));
5177 if (!info
->shifter
.operator_present
)
5179 /* Default to LSL if not present. Libopcodes prefers shifter
5180 kind to be explicit. */
5181 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5182 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5183 /* For Rm_EXT, libopcodes will carry out further check on whether
5184 or not stack pointer is used in the instruction (Recall that
5185 "the extend operator is not optional unless at least one of
5186 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5190 case AARCH64_OPND_Fd
:
5191 case AARCH64_OPND_Fn
:
5192 case AARCH64_OPND_Fm
:
5193 case AARCH64_OPND_Fa
:
5194 case AARCH64_OPND_Ft
:
5195 case AARCH64_OPND_Ft2
:
5196 case AARCH64_OPND_Sd
:
5197 case AARCH64_OPND_Sn
:
5198 case AARCH64_OPND_Sm
:
5199 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5200 if (val
== PARSE_FAIL
)
5202 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5205 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5207 info
->reg
.regno
= val
;
5208 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5211 case AARCH64_OPND_SVE_Pd
:
5212 case AARCH64_OPND_SVE_Pg3
:
5213 case AARCH64_OPND_SVE_Pg4_5
:
5214 case AARCH64_OPND_SVE_Pg4_10
:
5215 case AARCH64_OPND_SVE_Pg4_16
:
5216 case AARCH64_OPND_SVE_Pm
:
5217 case AARCH64_OPND_SVE_Pn
:
5218 case AARCH64_OPND_SVE_Pt
:
5219 reg_type
= REG_TYPE_PN
;
5222 case AARCH64_OPND_SVE_Za_5
:
5223 case AARCH64_OPND_SVE_Za_16
:
5224 case AARCH64_OPND_SVE_Zd
:
5225 case AARCH64_OPND_SVE_Zm_5
:
5226 case AARCH64_OPND_SVE_Zm_16
:
5227 case AARCH64_OPND_SVE_Zn
:
5228 case AARCH64_OPND_SVE_Zt
:
5229 reg_type
= REG_TYPE_ZN
;
5232 case AARCH64_OPND_Vd
:
5233 case AARCH64_OPND_Vn
:
5234 case AARCH64_OPND_Vm
:
5235 reg_type
= REG_TYPE_VN
;
5237 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5238 if (val
== PARSE_FAIL
)
5240 first_error (_(get_reg_expected_msg (reg_type
)));
5243 if (vectype
.defined
& NTA_HASINDEX
)
5246 info
->reg
.regno
= val
;
5247 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5248 && vectype
.type
== NT_invtype
)
5249 /* Unqualified Pn and Zn registers are allowed in certain
5250 contexts. Rely on F_STRICT qualifier checking to catch
5252 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5255 info
->qualifier
= vectype_to_qualifier (&vectype
);
5256 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5261 case AARCH64_OPND_VdD1
:
5262 case AARCH64_OPND_VnD1
:
5263 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5264 if (val
== PARSE_FAIL
)
5266 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5269 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5271 set_fatal_syntax_error
5272 (_("the top half of a 128-bit FP/SIMD register is expected"));
5275 info
->reg
.regno
= val
;
5276 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5277 here; it is correct for the purpose of encoding/decoding since
5278 only the register number is explicitly encoded in the related
5279 instructions, although this appears a bit hacky. */
5280 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5283 case AARCH64_OPND_SVE_Zn_INDEX
:
5284 reg_type
= REG_TYPE_ZN
;
5285 goto vector_reg_index
;
5287 case AARCH64_OPND_Ed
:
5288 case AARCH64_OPND_En
:
5289 case AARCH64_OPND_Em
:
5290 reg_type
= REG_TYPE_VN
;
5292 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5293 if (val
== PARSE_FAIL
)
5295 first_error (_(get_reg_expected_msg (reg_type
)));
5298 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5301 info
->reglane
.regno
= val
;
5302 info
->reglane
.index
= vectype
.index
;
5303 info
->qualifier
= vectype_to_qualifier (&vectype
);
5304 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5308 case AARCH64_OPND_SVE_ZnxN
:
5309 case AARCH64_OPND_SVE_ZtxN
:
5310 reg_type
= REG_TYPE_ZN
;
5311 goto vector_reg_list
;
5313 case AARCH64_OPND_LVn
:
5314 case AARCH64_OPND_LVt
:
5315 case AARCH64_OPND_LVt_AL
:
5316 case AARCH64_OPND_LEt
:
5317 reg_type
= REG_TYPE_VN
;
5319 if (reg_type
== REG_TYPE_ZN
5320 && get_opcode_dependent_value (opcode
) == 1
5323 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5324 if (val
== PARSE_FAIL
)
5326 first_error (_(get_reg_expected_msg (reg_type
)));
5329 info
->reglist
.first_regno
= val
;
5330 info
->reglist
.num_regs
= 1;
5334 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5335 if (val
== PARSE_FAIL
)
5337 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5339 set_fatal_syntax_error (_("invalid register list"));
5342 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5343 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5345 if (operands
[i
] == AARCH64_OPND_LEt
)
5347 if (!(vectype
.defined
& NTA_HASINDEX
))
5349 info
->reglist
.has_index
= 1;
5350 info
->reglist
.index
= vectype
.index
;
5354 if (vectype
.defined
& NTA_HASINDEX
)
5356 if (!(vectype
.defined
& NTA_HASTYPE
))
5358 if (reg_type
== REG_TYPE_ZN
)
5359 set_fatal_syntax_error (_("missing type suffix"));
5363 info
->qualifier
= vectype_to_qualifier (&vectype
);
5364 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5368 case AARCH64_OPND_Cn
:
5369 case AARCH64_OPND_Cm
:
5370 po_reg_or_fail (REG_TYPE_CN
);
5373 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5376 inst
.base
.operands
[i
].reg
.regno
= val
;
5379 case AARCH64_OPND_SHLL_IMM
:
5380 case AARCH64_OPND_IMM_VLSR
:
5381 po_imm_or_fail (1, 64);
5382 info
->imm
.value
= val
;
5385 case AARCH64_OPND_CCMP_IMM
:
5386 case AARCH64_OPND_FBITS
:
5387 case AARCH64_OPND_UIMM4
:
5388 case AARCH64_OPND_UIMM3_OP1
:
5389 case AARCH64_OPND_UIMM3_OP2
:
5390 case AARCH64_OPND_IMM_VLSL
:
5391 case AARCH64_OPND_IMM
:
5392 case AARCH64_OPND_WIDTH
:
5393 po_imm_nc_or_fail ();
5394 info
->imm
.value
= val
;
5397 case AARCH64_OPND_SVE_PATTERN
:
5398 po_enum_or_fail (aarch64_sve_pattern_array
);
5399 info
->imm
.value
= val
;
5402 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5403 po_enum_or_fail (aarch64_sve_pattern_array
);
5404 info
->imm
.value
= val
;
5405 if (skip_past_comma (&str
)
5406 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5408 if (!info
->shifter
.operator_present
)
5410 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5411 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5412 info
->shifter
.amount
= 1;
5416 case AARCH64_OPND_SVE_PRFOP
:
5417 po_enum_or_fail (aarch64_sve_prfop_array
);
5418 info
->imm
.value
= val
;
5421 case AARCH64_OPND_UIMM7
:
5422 po_imm_or_fail (0, 127);
5423 info
->imm
.value
= val
;
5426 case AARCH64_OPND_IDX
:
5427 case AARCH64_OPND_BIT_NUM
:
5428 case AARCH64_OPND_IMMR
:
5429 case AARCH64_OPND_IMMS
:
5430 po_imm_or_fail (0, 63);
5431 info
->imm
.value
= val
;
5434 case AARCH64_OPND_IMM0
:
5435 po_imm_nc_or_fail ();
5438 set_fatal_syntax_error (_("immediate zero expected"));
5441 info
->imm
.value
= 0;
5444 case AARCH64_OPND_FPIMM0
:
5447 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5448 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5449 it is probably not worth the effort to support it. */
5450 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5453 || !(res2
= parse_constant_immediate (&str
, &val
,
5456 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5458 info
->imm
.value
= 0;
5459 info
->imm
.is_fp
= 1;
5462 set_fatal_syntax_error (_("immediate zero expected"));
5466 case AARCH64_OPND_IMM_MOV
:
5469 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5470 reg_name_p (str
, REG_TYPE_VN
))
5473 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5475 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5476 later. fix_mov_imm_insn will try to determine a machine
5477 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5478 message if the immediate cannot be moved by a single
5480 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5481 inst
.base
.operands
[i
].skip
= 1;
5485 case AARCH64_OPND_SIMD_IMM
:
5486 case AARCH64_OPND_SIMD_IMM_SFT
:
5487 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5489 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5491 /* need_libopcodes_p */ 1,
5494 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5495 shift, we don't check it here; we leave the checking to
5496 the libopcodes (operand_general_constraint_met_p). By
5497 doing this, we achieve better diagnostics. */
5498 if (skip_past_comma (&str
)
5499 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5501 if (!info
->shifter
.operator_present
5502 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5504 /* Default to LSL if not present. Libopcodes prefers shifter
5505 kind to be explicit. */
5506 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5507 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5511 case AARCH64_OPND_FPIMM
:
5512 case AARCH64_OPND_SIMD_FPIMM
:
5516 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5518 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5519 || !aarch64_imm_float_p (qfloat
))
5522 set_fatal_syntax_error (_("invalid floating-point"
5526 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5527 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5531 case AARCH64_OPND_LIMM
:
5532 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5533 SHIFTED_LOGIC_IMM
));
5534 if (info
->shifter
.operator_present
)
5536 set_fatal_syntax_error
5537 (_("shift not allowed for bitmask immediate"));
5540 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5542 /* need_libopcodes_p */ 1,
5546 case AARCH64_OPND_AIMM
:
5547 if (opcode
->op
== OP_ADD
)
5548 /* ADD may have relocation types. */
5549 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5550 SHIFTED_ARITH_IMM
));
5552 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5553 SHIFTED_ARITH_IMM
));
5554 switch (inst
.reloc
.type
)
5556 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5557 info
->shifter
.amount
= 12;
5559 case BFD_RELOC_UNUSED
:
5560 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5561 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5562 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5563 inst
.reloc
.pc_rel
= 0;
5568 info
->imm
.value
= 0;
5569 if (!info
->shifter
.operator_present
)
5571 /* Default to LSL if not present. Libopcodes prefers shifter
5572 kind to be explicit. */
5573 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5574 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5578 case AARCH64_OPND_HALF
:
5580 /* #<imm16> or relocation. */
5581 int internal_fixup_p
;
5582 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5583 if (internal_fixup_p
)
5584 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5585 skip_whitespace (str
);
5586 if (skip_past_comma (&str
))
5588 /* {, LSL #<shift>} */
5589 if (! aarch64_gas_internal_fixup_p ())
5591 set_fatal_syntax_error (_("can't mix relocation modifier "
5592 "with explicit shift"));
5595 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5598 inst
.base
.operands
[i
].shifter
.amount
= 0;
5599 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5600 inst
.base
.operands
[i
].imm
.value
= 0;
5601 if (! process_movw_reloc_info ())
5606 case AARCH64_OPND_EXCEPTION
:
5607 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5609 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5611 /* need_libopcodes_p */ 0,
5615 case AARCH64_OPND_NZCV
:
5617 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5621 info
->imm
.value
= nzcv
->value
;
5624 po_imm_or_fail (0, 15);
5625 info
->imm
.value
= val
;
5629 case AARCH64_OPND_COND
:
5630 case AARCH64_OPND_COND1
:
5631 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5633 if (info
->cond
== NULL
)
5635 set_syntax_error (_("invalid condition"));
5638 else if (operands
[i
] == AARCH64_OPND_COND1
5639 && (info
->cond
->value
& 0xe) == 0xe)
5641 /* Not allow AL or NV. */
5642 set_default_error ();
5647 case AARCH64_OPND_ADDR_ADRP
:
5648 po_misc_or_fail (parse_adrp (&str
));
5649 /* Clear the value as operand needs to be relocated. */
5650 info
->imm
.value
= 0;
5653 case AARCH64_OPND_ADDR_PCREL14
:
5654 case AARCH64_OPND_ADDR_PCREL19
:
5655 case AARCH64_OPND_ADDR_PCREL21
:
5656 case AARCH64_OPND_ADDR_PCREL26
:
5657 po_misc_or_fail (parse_address (&str
, info
));
5658 if (!info
->addr
.pcrel
)
5660 set_syntax_error (_("invalid pc-relative address"));
5663 if (inst
.gen_lit_pool
5664 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5666 /* Only permit "=value" in the literal load instructions.
5667 The literal will be generated by programmer_friendly_fixup. */
5668 set_syntax_error (_("invalid use of \"=immediate\""));
5671 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5673 set_syntax_error (_("unrecognized relocation suffix"));
5676 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5678 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5679 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5683 info
->imm
.value
= 0;
5684 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5685 switch (opcode
->iclass
)
5689 /* e.g. CBZ or B.COND */
5690 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5691 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5695 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5696 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5700 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5702 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5703 : BFD_RELOC_AARCH64_JUMP26
;
5706 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5707 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5710 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5711 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5717 inst
.reloc
.pc_rel
= 1;
5721 case AARCH64_OPND_ADDR_SIMPLE
:
5722 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5724 /* [<Xn|SP>{, #<simm>}] */
5726 /* First use the normal address-parsing routines, to get
5727 the usual syntax errors. */
5728 po_misc_or_fail (parse_address (&str
, info
));
5729 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5730 || !info
->addr
.preind
|| info
->addr
.postind
5731 || info
->addr
.writeback
)
5733 set_syntax_error (_("invalid addressing mode"));
5737 /* Then retry, matching the specific syntax of these addresses. */
5739 po_char_or_fail ('[');
5740 po_reg_or_fail (REG_TYPE_R64_SP
);
5741 /* Accept optional ", #0". */
5742 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5743 && skip_past_char (&str
, ','))
5745 skip_past_char (&str
, '#');
5746 if (! skip_past_char (&str
, '0'))
5748 set_fatal_syntax_error
5749 (_("the optional immediate offset can only be 0"));
5753 po_char_or_fail (']');
5757 case AARCH64_OPND_ADDR_REGOFF
:
5758 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5759 po_misc_or_fail (parse_address (&str
, info
));
5760 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5761 || !info
->addr
.preind
|| info
->addr
.postind
5762 || info
->addr
.writeback
)
5764 set_syntax_error (_("invalid addressing mode"));
5767 if (!info
->shifter
.operator_present
)
5769 /* Default to LSL if not present. Libopcodes prefers shifter
5770 kind to be explicit. */
5771 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5772 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5774 /* Qualifier to be deduced by libopcodes. */
5777 case AARCH64_OPND_ADDR_SIMM7
:
5778 po_misc_or_fail (parse_address (&str
, info
));
5779 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5780 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5782 set_syntax_error (_("invalid addressing mode"));
5785 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5787 set_syntax_error (_("relocation not allowed"));
5790 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5792 /* need_libopcodes_p */ 1,
5796 case AARCH64_OPND_ADDR_SIMM9
:
5797 case AARCH64_OPND_ADDR_SIMM9_2
:
5798 po_misc_or_fail (parse_address (&str
, info
));
5799 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5800 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5801 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5802 && info
->addr
.writeback
))
5804 set_syntax_error (_("invalid addressing mode"));
5807 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5809 set_syntax_error (_("relocation not allowed"));
5812 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5814 /* need_libopcodes_p */ 1,
5818 case AARCH64_OPND_ADDR_UIMM12
:
5819 po_misc_or_fail (parse_address (&str
, info
));
5820 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5821 || !info
->addr
.preind
|| info
->addr
.writeback
)
5823 set_syntax_error (_("invalid addressing mode"));
5826 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5827 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5828 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5830 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5832 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5833 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5834 /* Leave qualifier to be determined by libopcodes. */
5837 case AARCH64_OPND_SIMD_ADDR_POST
:
5838 /* [<Xn|SP>], <Xm|#<amount>> */
5839 po_misc_or_fail (parse_address (&str
, info
));
5840 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5842 set_syntax_error (_("invalid addressing mode"));
5845 if (!info
->addr
.offset
.is_reg
)
5847 if (inst
.reloc
.exp
.X_op
== O_constant
)
5848 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5851 set_fatal_syntax_error
5852 (_("writeback value should be an immediate constant"));
5859 case AARCH64_OPND_SYSREG
:
5860 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5863 set_syntax_error (_("unknown or missing system register name"));
5866 inst
.base
.operands
[i
].sysreg
= val
;
5869 case AARCH64_OPND_PSTATEFIELD
:
5870 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5873 set_syntax_error (_("unknown or missing PSTATE field name"));
5876 inst
.base
.operands
[i
].pstatefield
= val
;
5879 case AARCH64_OPND_SYSREG_IC
:
5880 inst
.base
.operands
[i
].sysins_op
=
5881 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5883 case AARCH64_OPND_SYSREG_DC
:
5884 inst
.base
.operands
[i
].sysins_op
=
5885 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5887 case AARCH64_OPND_SYSREG_AT
:
5888 inst
.base
.operands
[i
].sysins_op
=
5889 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5891 case AARCH64_OPND_SYSREG_TLBI
:
5892 inst
.base
.operands
[i
].sysins_op
=
5893 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5895 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5897 set_fatal_syntax_error ( _("unknown or missing operation name"));
5902 case AARCH64_OPND_BARRIER
:
5903 case AARCH64_OPND_BARRIER_ISB
:
5904 val
= parse_barrier (&str
);
5905 if (val
!= PARSE_FAIL
5906 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5908 /* ISB only accepts options name 'sy'. */
5910 (_("the specified option is not accepted in ISB"));
5911 /* Turn off backtrack as this optional operand is present. */
5915 /* This is an extension to accept a 0..15 immediate. */
5916 if (val
== PARSE_FAIL
)
5917 po_imm_or_fail (0, 15);
5918 info
->barrier
= aarch64_barrier_options
+ val
;
5921 case AARCH64_OPND_PRFOP
:
5922 val
= parse_pldop (&str
);
5923 /* This is an extension to accept a 0..31 immediate. */
5924 if (val
== PARSE_FAIL
)
5925 po_imm_or_fail (0, 31);
5926 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5929 case AARCH64_OPND_BARRIER_PSB
:
5930 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5931 if (val
== PARSE_FAIL
)
5936 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5939 /* If we get here, this operand was successfully parsed. */
5940 inst
.base
.operands
[i
].present
= 1;
5944 /* The parse routine should already have set the error, but in case
5945 not, set a default one here. */
5947 set_default_error ();
5949 if (! backtrack_pos
)
5950 goto parse_operands_return
;
5953 /* We reach here because this operand is marked as optional, and
5954 either no operand was supplied or the operand was supplied but it
5955 was syntactically incorrect. In the latter case we report an
5956 error. In the former case we perform a few more checks before
5957 dropping through to the code to insert the default operand. */
5959 char *tmp
= backtrack_pos
;
5960 char endchar
= END_OF_INSN
;
5962 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5964 skip_past_char (&tmp
, ',');
5966 if (*tmp
!= endchar
)
5967 /* The user has supplied an operand in the wrong format. */
5968 goto parse_operands_return
;
5970 /* Make sure there is not a comma before the optional operand.
5971 For example the fifth operand of 'sys' is optional:
5973 sys #0,c0,c0,#0, <--- wrong
5974 sys #0,c0,c0,#0 <--- correct. */
5975 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5977 set_fatal_syntax_error
5978 (_("unexpected comma before the omitted optional operand"));
5979 goto parse_operands_return
;
5983 /* Reaching here means we are dealing with an optional operand that is
5984 omitted from the assembly line. */
5985 gas_assert (optional_operand_p (opcode
, i
));
5987 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5989 /* Try again, skipping the optional operand at backtrack_pos. */
5990 str
= backtrack_pos
;
5993 /* Clear any error record after the omitted optional operand has been
5994 successfully handled. */
5998 /* Check if we have parsed all the operands. */
5999 if (*str
!= '\0' && ! error_p ())
6001 /* Set I to the index of the last present operand; this is
6002 for the purpose of diagnostics. */
6003 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6005 set_fatal_syntax_error
6006 (_("unexpected characters following instruction"));
6009 parse_operands_return
:
6013 DEBUG_TRACE ("parsing FAIL: %s - %s",
6014 operand_mismatch_kind_names
[get_error_kind ()],
6015 get_error_message ());
6016 /* Record the operand error properly; this is useful when there
6017 are multiple instruction templates for a mnemonic name, so that
6018 later on, we can select the error that most closely describes
6020 record_operand_error (opcode
, i
, get_error_kind (),
6021 get_error_message ());
6026 DEBUG_TRACE ("parsing SUCCESS");
6031 /* It does some fix-up to provide some programmer friendly feature while
6032 keeping the libopcodes happy, i.e. libopcodes only accepts
6033 the preferred architectural syntax.
6034 Return FALSE if there is any failure; otherwise return TRUE. */
6037 programmer_friendly_fixup (aarch64_instruction
*instr
)
6039 aarch64_inst
*base
= &instr
->base
;
6040 const aarch64_opcode
*opcode
= base
->opcode
;
6041 enum aarch64_op op
= opcode
->op
;
6042 aarch64_opnd_info
*operands
= base
->operands
;
6044 DEBUG_TRACE ("enter");
6046 switch (opcode
->iclass
)
6049 /* TBNZ Xn|Wn, #uimm6, label
6050 Test and Branch Not Zero: conditionally jumps to label if bit number
6051 uimm6 in register Xn is not zero. The bit number implies the width of
6052 the register, which may be written and should be disassembled as Wn if
6053 uimm is less than 32. */
6054 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6056 if (operands
[1].imm
.value
>= 32)
6058 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6062 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6066 /* LDR Wt, label | =value
6067 As a convenience assemblers will typically permit the notation
6068 "=value" in conjunction with the pc-relative literal load instructions
6069 to automatically place an immediate value or symbolic address in a
6070 nearby literal pool and generate a hidden label which references it.
6071 ISREG has been set to 0 in the case of =value. */
6072 if (instr
->gen_lit_pool
6073 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6075 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6076 if (op
== OP_LDRSW_LIT
)
6078 if (instr
->reloc
.exp
.X_op
!= O_constant
6079 && instr
->reloc
.exp
.X_op
!= O_big
6080 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6082 record_operand_error (opcode
, 1,
6083 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6084 _("constant expression expected"));
6087 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6089 record_operand_error (opcode
, 1,
6090 AARCH64_OPDE_OTHER_ERROR
,
6091 _("literal pool insertion failed"));
6099 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6100 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6101 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6102 A programmer-friendly assembler should accept a destination Xd in
6103 place of Wd, however that is not the preferred form for disassembly.
6105 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6106 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6107 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6108 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6113 /* In the 64-bit form, the final register operand is written as Wm
6114 for all but the (possibly omitted) UXTX/LSL and SXTX
6116 As a programmer-friendly assembler, we accept e.g.
6117 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6118 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6119 int idx
= aarch64_operand_index (opcode
->operands
,
6120 AARCH64_OPND_Rm_EXT
);
6121 gas_assert (idx
== 1 || idx
== 2);
6122 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6123 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6124 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6125 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6126 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6127 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6135 DEBUG_TRACE ("exit with SUCCESS");
6139 /* Check for loads and stores that will cause unpredictable behavior. */
6142 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6144 aarch64_inst
*base
= &instr
->base
;
6145 const aarch64_opcode
*opcode
= base
->opcode
;
6146 const aarch64_opnd_info
*opnds
= base
->operands
;
6147 switch (opcode
->iclass
)
6153 /* Loading/storing the base register is unpredictable if writeback. */
6154 if ((aarch64_get_operand_class (opnds
[0].type
)
6155 == AARCH64_OPND_CLASS_INT_REG
)
6156 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6157 && opnds
[1].addr
.base_regno
!= REG_SP
6158 && opnds
[1].addr
.writeback
)
6159 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6162 case ldstnapair_offs
:
6163 case ldstpair_indexed
:
6164 /* Loading/storing the base register is unpredictable if writeback. */
6165 if ((aarch64_get_operand_class (opnds
[0].type
)
6166 == AARCH64_OPND_CLASS_INT_REG
)
6167 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6168 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6169 && opnds
[2].addr
.base_regno
!= REG_SP
6170 && opnds
[2].addr
.writeback
)
6171 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6172 /* Load operations must load different registers. */
6173 if ((opcode
->opcode
& (1 << 22))
6174 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6175 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6182 /* A wrapper function to interface with libopcodes on encoding and
6183 record the error message if there is any.
6185 Return TRUE on success; otherwise return FALSE. */
6188 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6191 aarch64_operand_error error_info
;
6192 error_info
.kind
= AARCH64_OPDE_NIL
;
6193 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6197 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6198 record_operand_error_info (opcode
, &error_info
);
6203 #ifdef DEBUG_AARCH64
6205 dump_opcode_operands (const aarch64_opcode
*opcode
)
6208 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6210 aarch64_verbose ("\t\t opnd%d: %s", i
,
6211 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6212 ? aarch64_get_operand_name (opcode
->operands
[i
])
6213 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6217 #endif /* DEBUG_AARCH64 */
6219 /* This is the guts of the machine-dependent assembler. STR points to a
6220 machine dependent instruction. This function is supposed to emit
6221 the frags/bytes it assembles to. */
6224 md_assemble (char *str
)
6227 templates
*template;
6228 aarch64_opcode
*opcode
;
6229 aarch64_inst
*inst_base
;
6230 unsigned saved_cond
;
6232 /* Align the previous label if needed. */
6233 if (last_label_seen
!= NULL
)
6235 symbol_set_frag (last_label_seen
, frag_now
);
6236 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6237 S_SET_SEGMENT (last_label_seen
, now_seg
);
6240 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6242 DEBUG_TRACE ("\n\n");
6243 DEBUG_TRACE ("==============================");
6244 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6246 template = opcode_lookup (&p
);
6249 /* It wasn't an instruction, but it might be a register alias of
6250 the form alias .req reg directive. */
6251 if (!create_register_alias (str
, p
))
6252 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6257 skip_whitespace (p
);
6260 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6261 get_mnemonic_name (str
), str
);
6265 init_operand_error_report ();
6267 /* Sections are assumed to start aligned. In executable section, there is no
6268 MAP_DATA symbol pending. So we only align the address during
6269 MAP_DATA --> MAP_INSN transition.
6270 For other sections, this is not guaranteed. */
6271 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6272 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6273 frag_align_code (2, 0);
6275 saved_cond
= inst
.cond
;
6276 reset_aarch64_instruction (&inst
);
6277 inst
.cond
= saved_cond
;
6279 /* Iterate through all opcode entries with the same mnemonic name. */
6282 opcode
= template->opcode
;
6284 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6285 #ifdef DEBUG_AARCH64
6287 dump_opcode_operands (opcode
);
6288 #endif /* DEBUG_AARCH64 */
6290 mapping_state (MAP_INSN
);
6292 inst_base
= &inst
.base
;
6293 inst_base
->opcode
= opcode
;
6295 /* Truly conditionally executed instructions, e.g. b.cond. */
6296 if (opcode
->flags
& F_COND
)
6298 gas_assert (inst
.cond
!= COND_ALWAYS
);
6299 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6300 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6302 else if (inst
.cond
!= COND_ALWAYS
)
6304 /* It shouldn't arrive here, where the assembly looks like a
6305 conditional instruction but the found opcode is unconditional. */
6310 if (parse_operands (p
, opcode
)
6311 && programmer_friendly_fixup (&inst
)
6312 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6314 /* Check that this instruction is supported for this CPU. */
6315 if (!opcode
->avariant
6316 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6318 as_bad (_("selected processor does not support `%s'"), str
);
6322 warn_unpredictable_ldst (&inst
, str
);
6324 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6325 || !inst
.reloc
.need_libopcodes_p
)
6329 /* If there is relocation generated for the instruction,
6330 store the instruction information for the future fix-up. */
6331 struct aarch64_inst
*copy
;
6332 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6333 copy
= XNEW (struct aarch64_inst
);
6334 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6340 template = template->next
;
6341 if (template != NULL
)
6343 reset_aarch64_instruction (&inst
);
6344 inst
.cond
= saved_cond
;
6347 while (template != NULL
);
6349 /* Issue the error messages if any. */
6350 output_operand_error_report (str
);
6353 /* Various frobbings of labels and their addresses. */
6356 aarch64_start_line_hook (void)
6358 last_label_seen
= NULL
;
6362 aarch64_frob_label (symbolS
* sym
)
6364 last_label_seen
= sym
;
6366 dwarf2_emit_label (sym
);
6370 aarch64_data_in_code (void)
6372 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6374 *input_line_pointer
= '/';
6375 input_line_pointer
+= 5;
6376 *input_line_pointer
= 0;
6384 aarch64_canonicalize_symbol_name (char *name
)
6388 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6389 *(name
+ len
- 5) = 0;
6394 /* Table of all register names defined by default. The user can
6395 define additional names with .req. Note that all register names
6396 should appear in both upper and lowercase variants. Some registers
6397 also have mixed-case names. */
6399 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6400 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6401 #define REGSET16(p,t) \
6402 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6403 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6404 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6405 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6406 #define REGSET31(p,t) \
6408 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6409 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6410 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6411 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6412 #define REGSET(p,t) \
6413 REGSET31(p,t), REGNUM(p,31,t)
6415 /* These go into aarch64_reg_hsh hash-table. */
6416 static const reg_entry reg_names
[] = {
6417 /* Integer registers. */
6418 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6419 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6421 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6422 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6424 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6425 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6427 /* Coprocessor register numbers. */
6428 REGSET (c
, CN
), REGSET (C
, CN
),
6430 /* Floating-point single precision registers. */
6431 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6433 /* Floating-point double precision registers. */
6434 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6436 /* Floating-point half precision registers. */
6437 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6439 /* Floating-point byte precision registers. */
6440 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6442 /* Floating-point quad precision registers. */
6443 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6445 /* FP/SIMD registers. */
6446 REGSET (v
, VN
), REGSET (V
, VN
),
6448 /* SVE vector registers. */
6449 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6451 /* SVE predicate registers. */
6452 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6469 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6470 static const asm_nzcv nzcv_names
[] = {
6471 {"nzcv", B (n
, z
, c
, v
)},
6472 {"nzcV", B (n
, z
, c
, V
)},
6473 {"nzCv", B (n
, z
, C
, v
)},
6474 {"nzCV", B (n
, z
, C
, V
)},
6475 {"nZcv", B (n
, Z
, c
, v
)},
6476 {"nZcV", B (n
, Z
, c
, V
)},
6477 {"nZCv", B (n
, Z
, C
, v
)},
6478 {"nZCV", B (n
, Z
, C
, V
)},
6479 {"Nzcv", B (N
, z
, c
, v
)},
6480 {"NzcV", B (N
, z
, c
, V
)},
6481 {"NzCv", B (N
, z
, C
, v
)},
6482 {"NzCV", B (N
, z
, C
, V
)},
6483 {"NZcv", B (N
, Z
, c
, v
)},
6484 {"NZcV", B (N
, Z
, c
, V
)},
6485 {"NZCv", B (N
, Z
, C
, v
)},
6486 {"NZCV", B (N
, Z
, C
, V
)}
6499 /* MD interface: bits in the object file. */
6501 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6502 for use in the a.out file, and stores them in the array pointed to by buf.
6503 This knows about the endian-ness of the target machine and does
6504 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6505 2 (short) and 4 (long) Floating numbers are put out as a series of
6506 LITTLENUMS (shorts, here at least). */
6509 md_number_to_chars (char *buf
, valueT val
, int n
)
6511 if (target_big_endian
)
6512 number_to_chars_bigendian (buf
, val
, n
);
6514 number_to_chars_littleendian (buf
, val
, n
);
6517 /* MD interface: Sections. */
6519 /* Estimate the size of a frag before relaxing. Assume everything fits in
6523 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6529 /* Round up a section size to the appropriate boundary. */
6532 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6537 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6538 of an rs_align_code fragment.
6540 Here we fill the frag with the appropriate info for padding the
6541 output stream. The resulting frag will consist of a fixed (fr_fix)
6542 and of a repeating (fr_var) part.
6544 The fixed content is always emitted before the repeating content and
6545 these two parts are used as follows in constructing the output:
6546 - the fixed part will be used to align to a valid instruction word
6547 boundary, in case that we start at a misaligned address; as no
6548 executable instruction can live at the misaligned location, we
6549 simply fill with zeros;
6550 - the variable part will be used to cover the remaining padding and
6551 we fill using the AArch64 NOP instruction.
6553 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6554 enough storage space for up to 3 bytes for padding the back to a valid
6555 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6558 aarch64_handle_align (fragS
* fragP
)
6560 /* NOP = d503201f */
6561 /* AArch64 instructions are always little-endian. */
6562 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6564 int bytes
, fix
, noop_size
;
6567 if (fragP
->fr_type
!= rs_align_code
)
6570 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6571 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6574 gas_assert (fragP
->tc_frag_data
.recorded
);
6577 noop_size
= sizeof (aarch64_noop
);
6579 fix
= bytes
& (noop_size
- 1);
6583 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6587 fragP
->fr_fix
+= fix
;
6591 memcpy (p
, aarch64_noop
, noop_size
);
6592 fragP
->fr_var
= noop_size
;
6595 /* Perform target specific initialisation of a frag.
6596 Note - despite the name this initialisation is not done when the frag
6597 is created, but only when its type is assigned. A frag can be created
6598 and used a long time before its type is set, so beware of assuming that
6599 this initialisationis performed first. */
6603 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6604 int max_chars ATTRIBUTE_UNUSED
)
6608 #else /* OBJ_ELF is defined. */
6610 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6612 /* Record a mapping symbol for alignment frags. We will delete this
6613 later if the alignment ends up empty. */
6614 if (!fragP
->tc_frag_data
.recorded
)
6615 fragP
->tc_frag_data
.recorded
= 1;
6617 switch (fragP
->fr_type
)
6621 mapping_state_2 (MAP_DATA
, max_chars
);
6624 /* PR 20364: We can get alignment frags in code sections,
6625 so do not just assume that we should use the MAP_DATA state. */
6626 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
6629 mapping_state_2 (MAP_INSN
, max_chars
);
6636 /* Initialize the DWARF-2 unwind information for this procedure. */
6639 tc_aarch64_frame_initial_instructions (void)
6641 cfi_add_CFA_def_cfa (REG_SP
, 0);
6643 #endif /* OBJ_ELF */
6645 /* Convert REGNAME to a DWARF-2 register number. */
6648 tc_aarch64_regname_to_dw2regnum (char *regname
)
6650 const reg_entry
*reg
= parse_reg (®name
);
6656 case REG_TYPE_SP_32
:
6657 case REG_TYPE_SP_64
:
6667 return reg
->number
+ 64;
6675 /* Implement DWARF2_ADDR_SIZE. */
6678 aarch64_dwarf2_addr_size (void)
6680 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6684 return bfd_arch_bits_per_address (stdoutput
) / 8;
6687 /* MD interface: Symbol and relocation handling. */
6689 /* Return the address within the segment that a PC-relative fixup is
6690 relative to. For AArch64 PC-relative fixups applied to instructions
6691 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6694 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6696 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6698 /* If this is pc-relative and we are going to emit a relocation
6699 then we just want to put out any pipeline compensation that the linker
6700 will need. Otherwise we want to use the calculated base. */
6702 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6703 || aarch64_force_relocation (fixP
)))
6706 /* AArch64 should be consistent for all pc-relative relocations. */
6707 return base
+ AARCH64_PCREL_OFFSET
;
6710 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6711 Otherwise we have no need to default values of symbols. */
6714 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6717 if (name
[0] == '_' && name
[1] == 'G'
6718 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6722 if (symbol_find (name
))
6723 as_bad (_("GOT already in the symbol table"));
6725 GOT_symbol
= symbol_new (name
, undefined_section
,
6726 (valueT
) 0, &zero_address_frag
);
6736 /* Return non-zero if the indicated VALUE has overflowed the maximum
6737 range expressible by a unsigned number with the indicated number of
6741 unsigned_overflow (valueT value
, unsigned bits
)
6744 if (bits
>= sizeof (valueT
) * 8)
6746 lim
= (valueT
) 1 << bits
;
6747 return (value
>= lim
);
6751 /* Return non-zero if the indicated VALUE has overflowed the maximum
6752 range expressible by an signed number with the indicated number of
6756 signed_overflow (offsetT value
, unsigned bits
)
6759 if (bits
>= sizeof (offsetT
) * 8)
6761 lim
= (offsetT
) 1 << (bits
- 1);
6762 return (value
< -lim
|| value
>= lim
);
6765 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6766 unsigned immediate offset load/store instruction, try to encode it as
6767 an unscaled, 9-bit, signed immediate offset load/store instruction.
6768 Return TRUE if it is successful; otherwise return FALSE.
6770 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6771 in response to the standard LDR/STR mnemonics when the immediate offset is
6772 unambiguous, i.e. when it is negative or unaligned. */
6775 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6778 enum aarch64_op new_op
;
6779 const aarch64_opcode
*new_opcode
;
6781 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6783 switch (instr
->opcode
->op
)
6785 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6786 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6787 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6788 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6789 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6790 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6791 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6792 case OP_STR_POS
: new_op
= OP_STUR
; break;
6793 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6794 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6795 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6796 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6797 default: new_op
= OP_NIL
; break;
6800 if (new_op
== OP_NIL
)
6803 new_opcode
= aarch64_get_opcode (new_op
);
6804 gas_assert (new_opcode
!= NULL
);
6806 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6807 instr
->opcode
->op
, new_opcode
->op
);
6809 aarch64_replace_opcode (instr
, new_opcode
);
6811 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6812 qualifier matching may fail because the out-of-date qualifier will
6813 prevent the operand being updated with a new and correct qualifier. */
6814 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6815 AARCH64_OPND_ADDR_SIMM9
);
6816 gas_assert (idx
== 1);
6817 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6819 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6821 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6827 /* Called by fix_insn to fix a MOV immediate alias instruction.
6829 Operand for a generic move immediate instruction, which is an alias
6830 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6831 a 32-bit/64-bit immediate value into general register. An assembler error
6832 shall result if the immediate cannot be created by a single one of these
6833 instructions. If there is a choice, then to ensure reversability an
6834 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6837 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6839 const aarch64_opcode
*opcode
;
6841 /* Need to check if the destination is SP/ZR. The check has to be done
6842 before any aarch64_replace_opcode. */
6843 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6844 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6846 instr
->operands
[1].imm
.value
= value
;
6847 instr
->operands
[1].skip
= 0;
6851 /* Try the MOVZ alias. */
6852 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6853 aarch64_replace_opcode (instr
, opcode
);
6854 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6855 &instr
->value
, NULL
, NULL
))
6857 put_aarch64_insn (buf
, instr
->value
);
6860 /* Try the MOVK alias. */
6861 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6862 aarch64_replace_opcode (instr
, opcode
);
6863 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6864 &instr
->value
, NULL
, NULL
))
6866 put_aarch64_insn (buf
, instr
->value
);
6871 if (try_mov_bitmask_p
)
6873 /* Try the ORR alias. */
6874 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6875 aarch64_replace_opcode (instr
, opcode
);
6876 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6877 &instr
->value
, NULL
, NULL
))
6879 put_aarch64_insn (buf
, instr
->value
);
6884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6885 _("immediate cannot be moved by a single instruction"));
6888 /* An instruction operand which is immediate related may have symbol used
6889 in the assembly, e.g.
6892 .set u32, 0x00ffff00
6894 At the time when the assembly instruction is parsed, a referenced symbol,
6895 like 'u32' in the above example may not have been seen; a fixS is created
6896 in such a case and is handled here after symbols have been resolved.
6897 Instruction is fixed up with VALUE using the information in *FIXP plus
6898 extra information in FLAGS.
6900 This function is called by md_apply_fix to fix up instructions that need
6901 a fix-up described above but does not involve any linker-time relocation. */
6904 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6908 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6909 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6910 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6914 /* Now the instruction is about to be fixed-up, so the operand that
6915 was previously marked as 'ignored' needs to be unmarked in order
6916 to get the encoding done properly. */
6917 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6918 new_inst
->operands
[idx
].skip
= 0;
6921 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6925 case AARCH64_OPND_EXCEPTION
:
6926 if (unsigned_overflow (value
, 16))
6927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6928 _("immediate out of range"));
6929 insn
= get_aarch64_insn (buf
);
6930 insn
|= encode_svc_imm (value
);
6931 put_aarch64_insn (buf
, insn
);
6934 case AARCH64_OPND_AIMM
:
6935 /* ADD or SUB with immediate.
6936 NOTE this assumes we come here with a add/sub shifted reg encoding
6937 3 322|2222|2 2 2 21111 111111
6938 1 098|7654|3 2 1 09876 543210 98765 43210
6939 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6940 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6941 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6942 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6944 3 322|2222|2 2 221111111111
6945 1 098|7654|3 2 109876543210 98765 43210
6946 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6947 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6948 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6949 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6950 Fields sf Rn Rd are already set. */
6951 insn
= get_aarch64_insn (buf
);
6955 insn
= reencode_addsub_switch_add_sub (insn
);
6959 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6960 && unsigned_overflow (value
, 12))
6962 /* Try to shift the value by 12 to make it fit. */
6963 if (((value
>> 12) << 12) == value
6964 && ! unsigned_overflow (value
, 12 + 12))
6967 insn
|= encode_addsub_imm_shift_amount (1);
6971 if (unsigned_overflow (value
, 12))
6972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6973 _("immediate out of range"));
6975 insn
|= encode_addsub_imm (value
);
6977 put_aarch64_insn (buf
, insn
);
6980 case AARCH64_OPND_SIMD_IMM
:
6981 case AARCH64_OPND_SIMD_IMM_SFT
:
6982 case AARCH64_OPND_LIMM
:
6983 /* Bit mask immediate. */
6984 gas_assert (new_inst
!= NULL
);
6985 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6986 new_inst
->operands
[idx
].imm
.value
= value
;
6987 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6988 &new_inst
->value
, NULL
, NULL
))
6989 put_aarch64_insn (buf
, new_inst
->value
);
6991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6992 _("invalid immediate"));
6995 case AARCH64_OPND_HALF
:
6996 /* 16-bit unsigned immediate. */
6997 if (unsigned_overflow (value
, 16))
6998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6999 _("immediate out of range"));
7000 insn
= get_aarch64_insn (buf
);
7001 insn
|= encode_movw_imm (value
& 0xffff);
7002 put_aarch64_insn (buf
, insn
);
7005 case AARCH64_OPND_IMM_MOV
:
7006 /* Operand for a generic move immediate instruction, which is
7007 an alias instruction that generates a single MOVZ, MOVN or ORR
7008 instruction to loads a 32-bit/64-bit immediate value into general
7009 register. An assembler error shall result if the immediate cannot be
7010 created by a single one of these instructions. If there is a choice,
7011 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7012 and MOVZ or MOVN to ORR. */
7013 gas_assert (new_inst
!= NULL
);
7014 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7017 case AARCH64_OPND_ADDR_SIMM7
:
7018 case AARCH64_OPND_ADDR_SIMM9
:
7019 case AARCH64_OPND_ADDR_SIMM9_2
:
7020 case AARCH64_OPND_ADDR_UIMM12
:
7021 /* Immediate offset in an address. */
7022 insn
= get_aarch64_insn (buf
);
7024 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7025 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7026 || new_inst
->opcode
->operands
[2] == opnd
);
7028 /* Get the index of the address operand. */
7029 if (new_inst
->opcode
->operands
[1] == opnd
)
7030 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7033 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7036 /* Update the resolved offset value. */
7037 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7039 /* Encode/fix-up. */
7040 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7041 &new_inst
->value
, NULL
, NULL
))
7043 put_aarch64_insn (buf
, new_inst
->value
);
7046 else if (new_inst
->opcode
->iclass
== ldst_pos
7047 && try_to_encode_as_unscaled_ldst (new_inst
))
7049 put_aarch64_insn (buf
, new_inst
->value
);
7053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7054 _("immediate offset out of range"));
7059 as_fatal (_("unhandled operand code %d"), opnd
);
7063 /* Apply a fixup (fixP) to segment data, once it has been determined
7064 by our caller that we have all the info we need to fix it up.
7066 Parameter valP is the pointer to the value of the bits. */
7069 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7071 offsetT value
= *valP
;
7073 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7075 unsigned flags
= fixP
->fx_addnumber
;
7077 DEBUG_TRACE ("\n\n");
7078 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7079 DEBUG_TRACE ("Enter md_apply_fix");
7081 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7083 /* Note whether this will delete the relocation. */
7085 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7088 /* Process the relocations. */
7089 switch (fixP
->fx_r_type
)
7091 case BFD_RELOC_NONE
:
7092 /* This will need to go in the object file. */
7097 case BFD_RELOC_8_PCREL
:
7098 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7099 md_number_to_chars (buf
, value
, 1);
7103 case BFD_RELOC_16_PCREL
:
7104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7105 md_number_to_chars (buf
, value
, 2);
7109 case BFD_RELOC_32_PCREL
:
7110 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7111 md_number_to_chars (buf
, value
, 4);
7115 case BFD_RELOC_64_PCREL
:
7116 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7117 md_number_to_chars (buf
, value
, 8);
7120 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7121 /* We claim that these fixups have been processed here, even if
7122 in fact we generate an error because we do not have a reloc
7123 for them, so tc_gen_reloc() will reject them. */
7125 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7128 _("undefined symbol %s used as an immediate value"),
7129 S_GET_NAME (fixP
->fx_addsy
));
7130 goto apply_fix_return
;
7132 fix_insn (fixP
, flags
, value
);
7135 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7136 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7140 _("pc-relative load offset not word aligned"));
7141 if (signed_overflow (value
, 21))
7142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7143 _("pc-relative load offset out of range"));
7144 insn
= get_aarch64_insn (buf
);
7145 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7146 put_aarch64_insn (buf
, insn
);
7150 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7151 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7153 if (signed_overflow (value
, 21))
7154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7155 _("pc-relative address offset out of range"));
7156 insn
= get_aarch64_insn (buf
);
7157 insn
|= encode_adr_imm (value
);
7158 put_aarch64_insn (buf
, insn
);
7162 case BFD_RELOC_AARCH64_BRANCH19
:
7163 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7166 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7167 _("conditional branch target not word aligned"));
7168 if (signed_overflow (value
, 21))
7169 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7170 _("conditional branch out of range"));
7171 insn
= get_aarch64_insn (buf
);
7172 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7173 put_aarch64_insn (buf
, insn
);
7177 case BFD_RELOC_AARCH64_TSTBR14
:
7178 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7182 _("conditional branch target not word aligned"));
7183 if (signed_overflow (value
, 16))
7184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7185 _("conditional branch out of range"));
7186 insn
= get_aarch64_insn (buf
);
7187 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7188 put_aarch64_insn (buf
, insn
);
7192 case BFD_RELOC_AARCH64_CALL26
:
7193 case BFD_RELOC_AARCH64_JUMP26
:
7194 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7198 _("branch target not word aligned"));
7199 if (signed_overflow (value
, 28))
7200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7201 _("branch out of range"));
7202 insn
= get_aarch64_insn (buf
);
7203 insn
|= encode_branch_ofs_26 (value
>> 2);
7204 put_aarch64_insn (buf
, insn
);
7208 case BFD_RELOC_AARCH64_MOVW_G0
:
7209 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7210 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7211 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7214 case BFD_RELOC_AARCH64_MOVW_G1
:
7215 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7216 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7217 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7220 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7222 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7223 /* Should always be exported to object file, see
7224 aarch64_force_relocation(). */
7225 gas_assert (!fixP
->fx_done
);
7226 gas_assert (seg
->use_rela_p
);
7228 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7230 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7231 /* Should always be exported to object file, see
7232 aarch64_force_relocation(). */
7233 gas_assert (!fixP
->fx_done
);
7234 gas_assert (seg
->use_rela_p
);
7236 case BFD_RELOC_AARCH64_MOVW_G2
:
7237 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7238 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7241 case BFD_RELOC_AARCH64_MOVW_G3
:
7244 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7246 insn
= get_aarch64_insn (buf
);
7250 /* REL signed addend must fit in 16 bits */
7251 if (signed_overflow (value
, 16))
7252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7253 _("offset out of range"));
7257 /* Check for overflow and scale. */
7258 switch (fixP
->fx_r_type
)
7260 case BFD_RELOC_AARCH64_MOVW_G0
:
7261 case BFD_RELOC_AARCH64_MOVW_G1
:
7262 case BFD_RELOC_AARCH64_MOVW_G2
:
7263 case BFD_RELOC_AARCH64_MOVW_G3
:
7264 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7265 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7266 if (unsigned_overflow (value
, scale
+ 16))
7267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7268 _("unsigned value out of range"));
7270 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7271 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7272 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7273 /* NOTE: We can only come here with movz or movn. */
7274 if (signed_overflow (value
, scale
+ 16))
7275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7276 _("signed value out of range"));
7279 /* Force use of MOVN. */
7281 insn
= reencode_movzn_to_movn (insn
);
7285 /* Force use of MOVZ. */
7286 insn
= reencode_movzn_to_movz (insn
);
7290 /* Unchecked relocations. */
7296 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7297 insn
|= encode_movw_imm (value
& 0xffff);
7299 put_aarch64_insn (buf
, insn
);
7303 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7304 fixP
->fx_r_type
= (ilp32_p
7305 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7306 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7307 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7308 /* Should always be exported to object file, see
7309 aarch64_force_relocation(). */
7310 gas_assert (!fixP
->fx_done
);
7311 gas_assert (seg
->use_rela_p
);
7314 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7315 fixP
->fx_r_type
= (ilp32_p
7316 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7317 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7318 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7319 /* Should always be exported to object file, see
7320 aarch64_force_relocation(). */
7321 gas_assert (!fixP
->fx_done
);
7322 gas_assert (seg
->use_rela_p
);
7325 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7326 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7327 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7328 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7329 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7330 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7331 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7332 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7333 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7334 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7335 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7336 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7337 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7338 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7339 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7340 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7341 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7342 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7343 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7344 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7345 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7346 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7347 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7348 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7349 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7350 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7351 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7352 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7353 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7354 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7355 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7356 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7357 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7358 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7359 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7360 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7361 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7362 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7363 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7364 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7365 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7366 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7367 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7368 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7369 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7370 /* Should always be exported to object file, see
7371 aarch64_force_relocation(). */
7372 gas_assert (!fixP
->fx_done
);
7373 gas_assert (seg
->use_rela_p
);
7376 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7377 /* Should always be exported to object file, see
7378 aarch64_force_relocation(). */
7379 fixP
->fx_r_type
= (ilp32_p
7380 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7381 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7382 gas_assert (!fixP
->fx_done
);
7383 gas_assert (seg
->use_rela_p
);
7386 case BFD_RELOC_AARCH64_ADD_LO12
:
7387 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7388 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7389 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7390 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7391 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7392 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7393 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7394 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7395 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7396 case BFD_RELOC_AARCH64_LDST128_LO12
:
7397 case BFD_RELOC_AARCH64_LDST16_LO12
:
7398 case BFD_RELOC_AARCH64_LDST32_LO12
:
7399 case BFD_RELOC_AARCH64_LDST64_LO12
:
7400 case BFD_RELOC_AARCH64_LDST8_LO12
:
7401 /* Should always be exported to object file, see
7402 aarch64_force_relocation(). */
7403 gas_assert (!fixP
->fx_done
);
7404 gas_assert (seg
->use_rela_p
);
7407 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7408 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7409 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7412 case BFD_RELOC_UNUSED
:
7413 /* An error will already have been reported. */
7417 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7418 _("unexpected %s fixup"),
7419 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7424 /* Free the allocated the struct aarch64_inst.
7425 N.B. currently there are very limited number of fix-up types actually use
7426 this field, so the impact on the performance should be minimal . */
7427 if (fixP
->tc_fix_data
.inst
!= NULL
)
7428 free (fixP
->tc_fix_data
.inst
);
7433 /* Translate internal representation of relocation info to BFD target
7437 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7440 bfd_reloc_code_real_type code
;
7442 reloc
= XNEW (arelent
);
7444 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7445 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7446 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7450 if (section
->use_rela_p
)
7451 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7453 fixp
->fx_offset
= reloc
->address
;
7455 reloc
->addend
= fixp
->fx_offset
;
7457 code
= fixp
->fx_r_type
;
7462 code
= BFD_RELOC_16_PCREL
;
7467 code
= BFD_RELOC_32_PCREL
;
7472 code
= BFD_RELOC_64_PCREL
;
7479 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7480 if (reloc
->howto
== NULL
)
7482 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7484 ("cannot represent %s relocation in this object file format"),
7485 bfd_get_reloc_code_name (code
));
7492 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7495 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7497 bfd_reloc_code_real_type type
;
7501 FIXME: @@ Should look at CPU word size. */
7508 type
= BFD_RELOC_16
;
7511 type
= BFD_RELOC_32
;
7514 type
= BFD_RELOC_64
;
7517 as_bad (_("cannot do %u-byte relocation"), size
);
7518 type
= BFD_RELOC_UNUSED
;
7522 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7526 aarch64_force_relocation (struct fix
*fixp
)
7528 switch (fixp
->fx_r_type
)
7530 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7531 /* Perform these "immediate" internal relocations
7532 even if the symbol is extern or weak. */
7535 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7536 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7537 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7538 /* Pseudo relocs that need to be fixed up according to
7542 case BFD_RELOC_AARCH64_ADD_LO12
:
7543 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7544 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7545 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7546 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7547 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7548 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7549 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7550 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7551 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7552 case BFD_RELOC_AARCH64_LDST128_LO12
:
7553 case BFD_RELOC_AARCH64_LDST16_LO12
:
7554 case BFD_RELOC_AARCH64_LDST32_LO12
:
7555 case BFD_RELOC_AARCH64_LDST64_LO12
:
7556 case BFD_RELOC_AARCH64_LDST8_LO12
:
7557 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7558 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7559 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7560 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7561 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7562 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7563 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7564 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7565 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7566 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7567 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7568 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7569 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7570 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7571 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7572 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7573 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7574 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7575 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7576 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7577 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7578 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7579 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7580 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7581 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7582 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7583 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7584 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7585 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7586 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7587 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7588 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7589 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7590 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7591 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7592 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7593 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7594 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7595 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7596 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7597 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7598 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7599 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7600 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7601 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7602 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7603 /* Always leave these relocations for the linker. */
7610 return generic_force_reloc (fixp
);
7616 elf64_aarch64_target_format (void)
7618 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7620 /* FIXME: What to do for ilp32_p ? */
7621 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7623 if (target_big_endian
)
7624 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7626 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7630 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7632 elf_frob_symbol (symp
, puntp
);
7636 /* MD interface: Finalization. */
7638 /* A good place to do this, although this was probably not intended
7639 for this kind of use. We need to dump the literal pool before
7640 references are made to a null symbol pointer. */
7643 aarch64_cleanup (void)
7647 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7649 /* Put it at the end of the relevant section. */
7650 subseg_set (pool
->section
, pool
->sub_section
);
7656 /* Remove any excess mapping symbols generated for alignment frags in
7657 SEC. We may have created a mapping symbol before a zero byte
7658 alignment; remove it if there's a mapping symbol after the
7661 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7662 void *dummy ATTRIBUTE_UNUSED
)
7664 segment_info_type
*seginfo
= seg_info (sec
);
7667 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7670 for (fragp
= seginfo
->frchainP
->frch_root
;
7671 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7673 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7674 fragS
*next
= fragp
->fr_next
;
7676 /* Variable-sized frags have been converted to fixed size by
7677 this point. But if this was variable-sized to start with,
7678 there will be a fixed-size frag after it. So don't handle
7680 if (sym
== NULL
|| next
== NULL
)
7683 if (S_GET_VALUE (sym
) < next
->fr_address
)
7684 /* Not at the end of this frag. */
7686 know (S_GET_VALUE (sym
) == next
->fr_address
);
7690 if (next
->tc_frag_data
.first_map
!= NULL
)
7692 /* Next frag starts with a mapping symbol. Discard this
7694 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7698 if (next
->fr_next
== NULL
)
7700 /* This mapping symbol is at the end of the section. Discard
7702 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7703 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7707 /* As long as we have empty frags without any mapping symbols,
7709 /* If the next frag is non-empty and does not start with a
7710 mapping symbol, then this mapping symbol is required. */
7711 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7714 next
= next
->fr_next
;
7716 while (next
!= NULL
);
7721 /* Adjust the symbol table. */
7724 aarch64_adjust_symtab (void)
7727 /* Remove any overlapping mapping symbols generated by alignment frags. */
7728 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7729 /* Now do generic ELF adjustments. */
7730 elf_adjust_symtab ();
7735 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7737 const char *hash_err
;
7739 hash_err
= hash_insert (table
, key
, value
);
7741 printf ("Internal Error: Can't hash %s\n", key
);
7745 fill_instruction_hash_table (void)
7747 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7749 while (opcode
->name
!= NULL
)
7751 templates
*templ
, *new_templ
;
7752 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7754 new_templ
= XNEW (templates
);
7755 new_templ
->opcode
= opcode
;
7756 new_templ
->next
= NULL
;
7759 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7762 new_templ
->next
= templ
->next
;
7763 templ
->next
= new_templ
;
7770 convert_to_upper (char *dst
, const char *src
, size_t num
)
7773 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7774 *dst
= TOUPPER (*src
);
7778 /* Assume STR point to a lower-case string, allocate, convert and return
7779 the corresponding upper-case string. */
7780 static inline const char*
7781 get_upper_str (const char *str
)
7784 size_t len
= strlen (str
);
7785 ret
= XNEWVEC (char, len
+ 1);
7786 convert_to_upper (ret
, str
, len
);
7790 /* MD interface: Initialization. */
7798 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7799 || (aarch64_cond_hsh
= hash_new ()) == NULL
7800 || (aarch64_shift_hsh
= hash_new ()) == NULL
7801 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7802 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7803 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7804 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7805 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7806 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7807 || (aarch64_reg_hsh
= hash_new ()) == NULL
7808 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7809 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7810 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7811 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7812 as_fatal (_("virtual memory exhausted"));
7814 fill_instruction_hash_table ();
7816 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7817 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7818 (void *) (aarch64_sys_regs
+ i
));
7820 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7821 checked_hash_insert (aarch64_pstatefield_hsh
,
7822 aarch64_pstatefields
[i
].name
,
7823 (void *) (aarch64_pstatefields
+ i
));
7825 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7826 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7827 aarch64_sys_regs_ic
[i
].name
,
7828 (void *) (aarch64_sys_regs_ic
+ i
));
7830 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7831 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7832 aarch64_sys_regs_dc
[i
].name
,
7833 (void *) (aarch64_sys_regs_dc
+ i
));
7835 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7836 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7837 aarch64_sys_regs_at
[i
].name
,
7838 (void *) (aarch64_sys_regs_at
+ i
));
7840 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7841 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7842 aarch64_sys_regs_tlbi
[i
].name
,
7843 (void *) (aarch64_sys_regs_tlbi
+ i
));
7845 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7846 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7847 (void *) (reg_names
+ i
));
7849 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7850 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7851 (void *) (nzcv_names
+ i
));
7853 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7855 const char *name
= aarch64_operand_modifiers
[i
].name
;
7856 checked_hash_insert (aarch64_shift_hsh
, name
,
7857 (void *) (aarch64_operand_modifiers
+ i
));
7858 /* Also hash the name in the upper case. */
7859 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7860 (void *) (aarch64_operand_modifiers
+ i
));
7863 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7866 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7867 the same condition code. */
7868 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7870 const char *name
= aarch64_conds
[i
].names
[j
];
7873 checked_hash_insert (aarch64_cond_hsh
, name
,
7874 (void *) (aarch64_conds
+ i
));
7875 /* Also hash the name in the upper case. */
7876 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7877 (void *) (aarch64_conds
+ i
));
7881 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7883 const char *name
= aarch64_barrier_options
[i
].name
;
7884 /* Skip xx00 - the unallocated values of option. */
7887 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7888 (void *) (aarch64_barrier_options
+ i
));
7889 /* Also hash the name in the upper case. */
7890 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7891 (void *) (aarch64_barrier_options
+ i
));
7894 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7896 const char* name
= aarch64_prfops
[i
].name
;
7897 /* Skip the unallocated hint encodings. */
7900 checked_hash_insert (aarch64_pldop_hsh
, name
,
7901 (void *) (aarch64_prfops
+ i
));
7902 /* Also hash the name in the upper case. */
7903 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7904 (void *) (aarch64_prfops
+ i
));
7907 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7909 const char* name
= aarch64_hint_options
[i
].name
;
7911 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7912 (void *) (aarch64_hint_options
+ i
));
7913 /* Also hash the name in the upper case. */
7914 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7915 (void *) (aarch64_hint_options
+ i
));
7918 /* Set the cpu variant based on the command-line options. */
7920 mcpu_cpu_opt
= march_cpu_opt
;
7923 mcpu_cpu_opt
= &cpu_default
;
7925 cpu_variant
= *mcpu_cpu_opt
;
7927 /* Record the CPU type. */
7928 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7930 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7933 /* Command line processing. */
7935 const char *md_shortopts
= "m:";
7937 #ifdef AARCH64_BI_ENDIAN
7938 #define OPTION_EB (OPTION_MD_BASE + 0)
7939 #define OPTION_EL (OPTION_MD_BASE + 1)
7941 #if TARGET_BYTES_BIG_ENDIAN
7942 #define OPTION_EB (OPTION_MD_BASE + 0)
7944 #define OPTION_EL (OPTION_MD_BASE + 1)
7948 struct option md_longopts
[] = {
7950 {"EB", no_argument
, NULL
, OPTION_EB
},
7953 {"EL", no_argument
, NULL
, OPTION_EL
},
7955 {NULL
, no_argument
, NULL
, 0}
7958 size_t md_longopts_size
= sizeof (md_longopts
);
7960 struct aarch64_option_table
7962 const char *option
; /* Option name to match. */
7963 const char *help
; /* Help information. */
7964 int *var
; /* Variable to change. */
7965 int value
; /* What to change it to. */
7966 char *deprecated
; /* If non-null, print this message. */
7969 static struct aarch64_option_table aarch64_opts
[] = {
7970 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7971 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7973 #ifdef DEBUG_AARCH64
7974 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7975 #endif /* DEBUG_AARCH64 */
7976 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7978 {"mno-verbose-error", N_("do not output verbose error messages"),
7979 &verbose_error_p
, 0, NULL
},
7980 {NULL
, NULL
, NULL
, 0, NULL
}
7983 struct aarch64_cpu_option_table
7986 const aarch64_feature_set value
;
7987 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7989 const char *canonical_name
;
7992 /* This list should, at a minimum, contain all the cpu names
7993 recognized by GCC. */
7994 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7995 {"all", AARCH64_ANY
, NULL
},
7996 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7997 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7998 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7999 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8000 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8001 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8002 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8003 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8004 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8005 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8006 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8007 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8008 "Samsung Exynos M1"},
8009 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8010 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8011 "Qualcomm QDF24XX"},
8012 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8013 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8015 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8016 AARCH64_FEATURE_CRYPTO
),
8018 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8019 in earlier releases and is superseded by 'xgene1' in all
8021 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8022 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8023 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8024 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8025 {"generic", AARCH64_ARCH_V8
, NULL
},
8027 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8030 struct aarch64_arch_option_table
8033 const aarch64_feature_set value
;
8036 /* This list should, at a minimum, contain all the architecture names
8037 recognized by GCC. */
8038 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8039 {"all", AARCH64_ANY
},
8040 {"armv8-a", AARCH64_ARCH_V8
},
8041 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8042 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8043 {NULL
, AARCH64_ARCH_NONE
}
8046 /* ISA extensions. */
8047 struct aarch64_option_cpu_value_table
8050 const aarch64_feature_set value
;
8051 const aarch64_feature_set require
; /* Feature dependencies. */
8054 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8055 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8057 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
8059 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8061 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8063 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8065 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8067 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8069 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8071 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8072 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8073 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8074 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8075 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8077 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8080 struct aarch64_long_option_table
8082 const char *option
; /* Substring to match. */
8083 const char *help
; /* Help information. */
8084 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8085 char *deprecated
; /* If non-null, print this message. */
8088 /* Transitive closure of features depending on set. */
8089 static aarch64_feature_set
8090 aarch64_feature_disable_set (aarch64_feature_set set
)
8092 const struct aarch64_option_cpu_value_table
*opt
;
8093 aarch64_feature_set prev
= 0;
8095 while (prev
!= set
) {
8097 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8098 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8099 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8104 /* Transitive closure of dependencies of set. */
8105 static aarch64_feature_set
8106 aarch64_feature_enable_set (aarch64_feature_set set
)
8108 const struct aarch64_option_cpu_value_table
*opt
;
8109 aarch64_feature_set prev
= 0;
8111 while (prev
!= set
) {
8113 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8114 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8115 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8121 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8122 bfd_boolean ext_only
)
8124 /* We insist on extensions being added before being removed. We achieve
8125 this by using the ADDING_VALUE variable to indicate whether we are
8126 adding an extension (1) or removing it (0) and only allowing it to
8127 change in the order -1 -> 1 -> 0. */
8128 int adding_value
= -1;
8129 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8131 /* Copy the feature set, so that we can modify it. */
8135 while (str
!= NULL
&& *str
!= 0)
8137 const struct aarch64_option_cpu_value_table
*opt
;
8138 const char *ext
= NULL
;
8145 as_bad (_("invalid architectural extension"));
8149 ext
= strchr (++str
, '+');
8155 optlen
= strlen (str
);
8157 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8159 if (adding_value
!= 0)
8164 else if (optlen
> 0)
8166 if (adding_value
== -1)
8168 else if (adding_value
!= 1)
8170 as_bad (_("must specify extensions to add before specifying "
8171 "those to remove"));
8178 as_bad (_("missing architectural extension"));
8182 gas_assert (adding_value
!= -1);
8184 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8185 if (strncmp (opt
->name
, str
, optlen
) == 0)
8187 aarch64_feature_set set
;
8189 /* Add or remove the extension. */
8192 set
= aarch64_feature_enable_set (opt
->value
);
8193 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8197 set
= aarch64_feature_disable_set (opt
->value
);
8198 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8203 if (opt
->name
== NULL
)
8205 as_bad (_("unknown architectural extension `%s'"), str
);
8216 aarch64_parse_cpu (const char *str
)
8218 const struct aarch64_cpu_option_table
*opt
;
8219 const char *ext
= strchr (str
, '+');
8225 optlen
= strlen (str
);
8229 as_bad (_("missing cpu name `%s'"), str
);
8233 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8234 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8236 mcpu_cpu_opt
= &opt
->value
;
8238 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8243 as_bad (_("unknown cpu `%s'"), str
);
8248 aarch64_parse_arch (const char *str
)
8250 const struct aarch64_arch_option_table
*opt
;
8251 const char *ext
= strchr (str
, '+');
8257 optlen
= strlen (str
);
8261 as_bad (_("missing architecture name `%s'"), str
);
8265 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8266 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8268 march_cpu_opt
= &opt
->value
;
8270 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8275 as_bad (_("unknown architecture `%s'\n"), str
);
8280 struct aarch64_option_abi_value_table
8283 enum aarch64_abi_type value
;
8286 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8287 {"ilp32", AARCH64_ABI_ILP32
},
8288 {"lp64", AARCH64_ABI_LP64
},
8292 aarch64_parse_abi (const char *str
)
8298 as_bad (_("missing abi name `%s'"), str
);
8302 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8303 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8305 aarch64_abi
= aarch64_abis
[i
].value
;
8309 as_bad (_("unknown abi `%s'\n"), str
);
8313 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8315 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8316 aarch64_parse_abi
, NULL
},
8317 #endif /* OBJ_ELF */
8318 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8319 aarch64_parse_cpu
, NULL
},
8320 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8321 aarch64_parse_arch
, NULL
},
8322 {NULL
, NULL
, 0, NULL
}
8326 md_parse_option (int c
, const char *arg
)
8328 struct aarch64_option_table
*opt
;
8329 struct aarch64_long_option_table
*lopt
;
8335 target_big_endian
= 1;
8341 target_big_endian
= 0;
8346 /* Listing option. Just ignore these, we don't support additional
8351 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8353 if (c
== opt
->option
[0]
8354 && ((arg
== NULL
&& opt
->option
[1] == 0)
8355 || streq (arg
, opt
->option
+ 1)))
8357 /* If the option is deprecated, tell the user. */
8358 if (opt
->deprecated
!= NULL
)
8359 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8360 arg
? arg
: "", _(opt
->deprecated
));
8362 if (opt
->var
!= NULL
)
8363 *opt
->var
= opt
->value
;
8369 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8371 /* These options are expected to have an argument. */
8372 if (c
== lopt
->option
[0]
8374 && strncmp (arg
, lopt
->option
+ 1,
8375 strlen (lopt
->option
+ 1)) == 0)
8377 /* If the option is deprecated, tell the user. */
8378 if (lopt
->deprecated
!= NULL
)
8379 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8380 _(lopt
->deprecated
));
8382 /* Call the sup-option parser. */
8383 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8394 md_show_usage (FILE * fp
)
8396 struct aarch64_option_table
*opt
;
8397 struct aarch64_long_option_table
*lopt
;
8399 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8401 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8402 if (opt
->help
!= NULL
)
8403 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8405 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8406 if (lopt
->help
!= NULL
)
8407 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8411 -EB assemble code for a big-endian cpu\n"));
8416 -EL assemble code for a little-endian cpu\n"));
8420 /* Parse a .cpu directive. */
8423 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8425 const struct aarch64_cpu_option_table
*opt
;
8431 name
= input_line_pointer
;
8432 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8433 input_line_pointer
++;
8434 saved_char
= *input_line_pointer
;
8435 *input_line_pointer
= 0;
8437 ext
= strchr (name
, '+');
8440 optlen
= ext
- name
;
8442 optlen
= strlen (name
);
8444 /* Skip the first "all" entry. */
8445 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8446 if (strlen (opt
->name
) == optlen
8447 && strncmp (name
, opt
->name
, optlen
) == 0)
8449 mcpu_cpu_opt
= &opt
->value
;
8451 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8454 cpu_variant
= *mcpu_cpu_opt
;
8456 *input_line_pointer
= saved_char
;
8457 demand_empty_rest_of_line ();
8460 as_bad (_("unknown cpu `%s'"), name
);
8461 *input_line_pointer
= saved_char
;
8462 ignore_rest_of_line ();
8466 /* Parse a .arch directive. */
8469 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8471 const struct aarch64_arch_option_table
*opt
;
8477 name
= input_line_pointer
;
8478 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8479 input_line_pointer
++;
8480 saved_char
= *input_line_pointer
;
8481 *input_line_pointer
= 0;
8483 ext
= strchr (name
, '+');
8486 optlen
= ext
- name
;
8488 optlen
= strlen (name
);
8490 /* Skip the first "all" entry. */
8491 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8492 if (strlen (opt
->name
) == optlen
8493 && strncmp (name
, opt
->name
, optlen
) == 0)
8495 mcpu_cpu_opt
= &opt
->value
;
8497 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8500 cpu_variant
= *mcpu_cpu_opt
;
8502 *input_line_pointer
= saved_char
;
8503 demand_empty_rest_of_line ();
8507 as_bad (_("unknown architecture `%s'\n"), name
);
8508 *input_line_pointer
= saved_char
;
8509 ignore_rest_of_line ();
8512 /* Parse a .arch_extension directive. */
8515 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8518 char *ext
= input_line_pointer
;;
8520 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8521 input_line_pointer
++;
8522 saved_char
= *input_line_pointer
;
8523 *input_line_pointer
= 0;
8525 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8528 cpu_variant
= *mcpu_cpu_opt
;
8530 *input_line_pointer
= saved_char
;
8531 demand_empty_rest_of_line ();
8534 /* Copy symbol information. */
8537 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8539 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);