1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2017 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in vector_type_el. */
93 #define NTA_HASINDEX 2
94 #define NTA_HASVARWIDTH 4
98 enum vector_el_type type
;
99 unsigned char defined
;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type
;
111 enum aarch64_opnd opnd
;
113 unsigned need_libopcodes_p
: 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind
;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool
: 1;
134 typedef struct aarch64_instruction aarch64_instruction
;
136 static aarch64_instruction inst
;
138 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
139 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
162 inst
.parsing_error
.error
= NULL
;
165 static inline bfd_boolean
168 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
171 static inline const char *
172 get_error_message (void)
174 return inst
.parsing_error
.error
;
177 static inline enum aarch64_operand_error_kind
178 get_error_kind (void)
180 return inst
.parsing_error
.kind
;
184 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
186 inst
.parsing_error
.kind
= kind
;
187 inst
.parsing_error
.error
= error
;
191 set_recoverable_error (const char *error
)
193 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
196 /* Use the DESC field of the corresponding aarch64_operand entry to compose
197 the error message. */
199 set_default_error (void)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
205 set_syntax_error (const char *error
)
207 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
211 set_first_syntax_error (const char *error
)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
218 set_fatal_syntax_error (const char *error
)
220 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
223 /* Number of littlenums required to hold an extended precision number. */
224 #define MAX_LITTLENUMS 6
226 /* Return value for certain parsers when the parsing fails; those parsers
227 return the information of the parsed result, e.g. register number, on
229 #define PARSE_FAIL -1
231 /* This is an invalid condition code that means no conditional field is
233 #define COND_ALWAYS 0x10
237 const char *template;
243 const char *template;
250 bfd_reloc_code_real_type reloc
;
253 /* Macros to define the register types and masks for the purpose
256 #undef AARCH64_REG_TYPES
257 #define AARCH64_REG_TYPES \
258 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
259 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
260 BASIC_REG_TYPE(SP_32) /* wsp */ \
261 BASIC_REG_TYPE(SP_64) /* sp */ \
262 BASIC_REG_TYPE(Z_32) /* wzr */ \
263 BASIC_REG_TYPE(Z_64) /* xzr */ \
264 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
265 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
266 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
267 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
268 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
269 BASIC_REG_TYPE(VN) /* v[0-31] */ \
270 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
271 BASIC_REG_TYPE(PN) /* p[0-15] */ \
272 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
273 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
274 /* Typecheck: same, plus SVE registers. */ \
275 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
277 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
278 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
279 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
280 /* Typecheck: same, plus SVE registers. */ \
281 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
284 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
285 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
286 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
287 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
288 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
289 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
291 /* Typecheck: any [BHSDQ]P FP. */ \
292 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
293 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
294 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
295 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
296 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
297 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
298 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
299 /* Typecheck: as above, but also Zn and Pn. This should only be \
300 used for SVE instructions, since Zn and Pn are valid symbols \
301 in other contexts. */ \
302 MULTI_REG_TYPE(R_Z_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
303 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
304 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
305 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
306 | REG_TYPE(ZN) | REG_TYPE(PN)) \
307 /* Any integer register; used for error messages only. */ \
308 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
309 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
310 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
311 /* Pseudo type to mark the end of the enumerator sequence. */ \
314 #undef BASIC_REG_TYPE
315 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
316 #undef MULTI_REG_TYPE
317 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
319 /* Register type enumerators. */
320 typedef enum aarch64_reg_type_
322 /* A list of REG_TYPE_*. */
326 #undef BASIC_REG_TYPE
327 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
329 #define REG_TYPE(T) (1 << REG_TYPE_##T)
330 #undef MULTI_REG_TYPE
331 #define MULTI_REG_TYPE(T,V) V,
333 /* Structure for a hash table entry for a register. */
337 unsigned char number
;
338 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
339 unsigned char builtin
;
342 /* Values indexed by aarch64_reg_type to assist the type checking. */
343 static const unsigned reg_type_masks
[] =
348 #undef BASIC_REG_TYPE
350 #undef MULTI_REG_TYPE
351 #undef AARCH64_REG_TYPES
353 /* Diagnostics used when we don't get a register of the expected type.
354 Note: this has to synchronized with aarch64_reg_type definitions
357 get_reg_expected_msg (aarch64_reg_type reg_type
)
364 msg
= N_("integer 32-bit register expected");
367 msg
= N_("integer 64-bit register expected");
370 msg
= N_("integer register expected");
372 case REG_TYPE_R64_SP
:
373 msg
= N_("64-bit integer or SP register expected");
375 case REG_TYPE_SVE_BASE
:
376 msg
= N_("base register expected");
379 msg
= N_("integer or zero register expected");
381 case REG_TYPE_SVE_OFFSET
:
382 msg
= N_("offset register expected");
385 msg
= N_("integer or SP register expected");
387 case REG_TYPE_R_Z_SP
:
388 msg
= N_("integer, zero or SP register expected");
391 msg
= N_("8-bit SIMD scalar register expected");
394 msg
= N_("16-bit SIMD scalar or floating-point half precision "
395 "register expected");
398 msg
= N_("32-bit SIMD scalar or floating-point single precision "
399 "register expected");
402 msg
= N_("64-bit SIMD scalar or floating-point double precision "
403 "register expected");
406 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
407 "register expected");
409 case REG_TYPE_R_Z_BHSDQ_V
:
410 case REG_TYPE_R_Z_BHSDQ_VZP
:
411 msg
= N_("register expected");
413 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
414 msg
= N_("SIMD scalar or floating-point register expected");
416 case REG_TYPE_VN
: /* any V reg */
417 msg
= N_("vector register expected");
420 msg
= N_("SVE vector register expected");
423 msg
= N_("SVE predicate register expected");
426 as_fatal (_("invalid register type %d"), reg_type
);
431 /* Some well known registers that we refer to directly elsewhere. */
434 /* Instructions take 4 bytes in the object file. */
437 static struct hash_control
*aarch64_ops_hsh
;
438 static struct hash_control
*aarch64_cond_hsh
;
439 static struct hash_control
*aarch64_shift_hsh
;
440 static struct hash_control
*aarch64_sys_regs_hsh
;
441 static struct hash_control
*aarch64_pstatefield_hsh
;
442 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
443 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
444 static struct hash_control
*aarch64_sys_regs_at_hsh
;
445 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
446 static struct hash_control
*aarch64_reg_hsh
;
447 static struct hash_control
*aarch64_barrier_opt_hsh
;
448 static struct hash_control
*aarch64_nzcv_hsh
;
449 static struct hash_control
*aarch64_pldop_hsh
;
450 static struct hash_control
*aarch64_hint_opt_hsh
;
452 /* Stuff needed to resolve the label ambiguity
461 static symbolS
*last_label_seen
;
463 /* Literal pool structure. Held on a per-section
464 and per-sub-section basis. */
466 #define MAX_LITERAL_POOL_SIZE 1024
467 typedef struct literal_expression
470 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
471 LITTLENUM_TYPE
* bignum
;
472 } literal_expression
;
474 typedef struct literal_pool
476 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
477 unsigned int next_free_entry
;
483 struct literal_pool
*next
;
486 /* Pointer to a linked list of literal pools. */
487 static literal_pool
*list_of_pools
= NULL
;
491 /* This array holds the chars that always start a comment. If the
492 pre-processor is disabled, these aren't very useful. */
493 const char comment_chars
[] = "";
495 /* This array holds the chars that only start a comment at the beginning of
496 a line. If the line seems to have the form '# 123 filename'
497 .line and .file directives will appear in the pre-processed output. */
498 /* Note that input_file.c hand checks for '#' at the beginning of the
499 first line of the input file. This is because the compiler outputs
500 #NO_APP at the beginning of its output. */
501 /* Also note that comments like this one will always work. */
502 const char line_comment_chars
[] = "#";
504 const char line_separator_chars
[] = ";";
506 /* Chars that can be used to separate mant
507 from exp in floating point numbers. */
508 const char EXP_CHARS
[] = "eE";
510 /* Chars that mean this number is a floating point constant. */
514 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
516 /* Prefix character that indicates the start of an immediate value. */
517 #define is_immediate_prefix(C) ((C) == '#')
519 /* Separator character handling. */
521 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
523 static inline bfd_boolean
524 skip_past_char (char **str
, char c
)
535 #define skip_past_comma(str) skip_past_char (str, ',')
537 /* Arithmetic expressions (possibly involving symbols). */
539 static bfd_boolean in_my_get_expression_p
= FALSE
;
541 /* Third argument to my_get_expression. */
542 #define GE_NO_PREFIX 0
543 #define GE_OPT_PREFIX 1
545 /* Return TRUE if the string pointed by *STR is successfully parsed
546 as an valid expression; *EP will be filled with the information of
547 such an expression. Otherwise return FALSE. */
550 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
555 int prefix_present_p
= 0;
562 if (is_immediate_prefix (**str
))
565 prefix_present_p
= 1;
572 memset (ep
, 0, sizeof (expressionS
));
574 save_in
= input_line_pointer
;
575 input_line_pointer
= *str
;
576 in_my_get_expression_p
= TRUE
;
577 seg
= expression (ep
);
578 in_my_get_expression_p
= FALSE
;
580 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
582 /* We found a bad expression in md_operand(). */
583 *str
= input_line_pointer
;
584 input_line_pointer
= save_in
;
585 if (prefix_present_p
&& ! error_p ())
586 set_fatal_syntax_error (_("bad expression"));
588 set_first_syntax_error (_("bad expression"));
593 if (seg
!= absolute_section
594 && seg
!= text_section
595 && seg
!= data_section
596 && seg
!= bss_section
&& seg
!= undefined_section
)
598 set_syntax_error (_("bad segment"));
599 *str
= input_line_pointer
;
600 input_line_pointer
= save_in
;
607 *str
= input_line_pointer
;
608 input_line_pointer
= save_in
;
612 /* Turn a string in input_line_pointer into a floating point constant
613 of type TYPE, and store the appropriate bytes in *LITP. The number
614 of LITTLENUMS emitted is stored in *SIZEP. An error message is
615 returned, or NULL on OK. */
618 md_atof (int type
, char *litP
, int *sizeP
)
620 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
623 /* We handle all bad expressions here, so that we can report the faulty
624 instruction in the error message. */
626 md_operand (expressionS
* exp
)
628 if (in_my_get_expression_p
)
629 exp
->X_op
= O_illegal
;
632 /* Immediate values. */
634 /* Errors may be set multiple times during parsing or bit encoding
635 (particularly in the Neon bits), but usually the earliest error which is set
636 will be the most meaningful. Avoid overwriting it with later (cascading)
637 errors by calling this function. */
640 first_error (const char *error
)
643 set_syntax_error (error
);
646 /* Similar to first_error, but this function accepts formatted error
649 first_error_fmt (const char *format
, ...)
654 /* N.B. this single buffer will not cause error messages for different
655 instructions to pollute each other; this is because at the end of
656 processing of each assembly line, error message if any will be
657 collected by as_bad. */
658 static char buffer
[size
];
662 int ret ATTRIBUTE_UNUSED
;
663 va_start (args
, format
);
664 ret
= vsnprintf (buffer
, size
, format
, args
);
665 know (ret
<= size
- 1 && ret
>= 0);
667 set_syntax_error (buffer
);
671 /* Register parsing. */
673 /* Generic register parser which is called by other specialized
675 CCP points to what should be the beginning of a register name.
676 If it is indeed a valid register name, advance CCP over it and
677 return the reg_entry structure; otherwise return NULL.
678 It does not issue diagnostics. */
681 parse_reg (char **ccp
)
687 #ifdef REGISTER_PREFIX
688 if (*start
!= REGISTER_PREFIX
)
694 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
699 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
701 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
710 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
713 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
715 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
718 /* Try to parse a base or offset register. Allow SVE base and offset
719 registers if REG_TYPE includes SVE registers. Return the register
720 entry on success, setting *QUALIFIER to the register qualifier.
721 Return null otherwise.
723 Note that this function does not issue any diagnostics. */
725 static const reg_entry
*
726 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
727 aarch64_opnd_qualifier_t
*qualifier
)
730 const reg_entry
*reg
= parse_reg (&str
);
740 *qualifier
= AARCH64_OPND_QLF_W
;
746 *qualifier
= AARCH64_OPND_QLF_X
;
750 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
753 switch (TOLOWER (str
[1]))
756 *qualifier
= AARCH64_OPND_QLF_S_S
;
759 *qualifier
= AARCH64_OPND_QLF_S_D
;
776 /* Try to parse a base or offset register. Return the register entry
777 on success, setting *QUALIFIER to the register qualifier. Return null
780 Note that this function does not issue any diagnostics. */
782 static const reg_entry
*
783 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
785 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
788 /* Parse the qualifier of a vector register or vector element of type
789 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
790 succeeds; otherwise return FALSE.
792 Accept only one occurrence of:
793 8b 16b 2h 4h 8h 2s 4s 1d 2d
796 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
797 struct vector_type_el
*parsed_type
, char **str
)
801 unsigned element_size
;
802 enum vector_el_type type
;
805 gas_assert (*ptr
== '.');
808 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
813 width
= strtoul (ptr
, &ptr
, 10);
814 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
816 first_error_fmt (_("bad size %d in vector width specifier"), width
);
821 switch (TOLOWER (*ptr
))
849 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
851 first_error (_("missing element size"));
854 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
855 && !(width
== 2 && element_size
== 16))
858 ("invalid element size %d and vector size combination %c"),
864 parsed_type
->type
= type
;
865 parsed_type
->width
= width
;
872 /* *STR contains an SVE zero/merge predication suffix. Parse it into
873 *PARSED_TYPE and point *STR at the end of the suffix. */
876 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
881 gas_assert (*ptr
== '/');
883 switch (TOLOWER (*ptr
))
886 parsed_type
->type
= NT_zero
;
889 parsed_type
->type
= NT_merge
;
892 if (*ptr
!= '\0' && *ptr
!= ',')
893 first_error_fmt (_("unexpected character `%c' in predication type"),
896 first_error (_("missing predication type"));
899 parsed_type
->width
= 0;
904 /* Parse a register of the type TYPE.
906 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
907 name or the parsed register is not of TYPE.
909 Otherwise return the register number, and optionally fill in the actual
910 type of the register in *RTYPE when multiple alternatives were given, and
911 return the register shape and element index information in *TYPEINFO.
913 IN_REG_LIST should be set with TRUE if the caller is parsing a register
917 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
918 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
921 const reg_entry
*reg
= parse_reg (&str
);
922 struct vector_type_el atype
;
923 struct vector_type_el parsetype
;
924 bfd_boolean is_typed_vecreg
= FALSE
;
927 atype
.type
= NT_invtype
;
935 set_default_error ();
939 if (! aarch64_check_reg_type (reg
, type
))
941 DEBUG_TRACE ("reg type check failed");
942 set_default_error ();
947 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
948 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
952 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
957 if (!parse_predication_for_operand (&parsetype
, &str
))
961 /* Register if of the form Vn.[bhsdq]. */
962 is_typed_vecreg
= TRUE
;
964 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
966 /* The width is always variable; we don't allow an integer width
968 gas_assert (parsetype
.width
== 0);
969 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
971 else if (parsetype
.width
== 0)
972 /* Expect index. In the new scheme we cannot have
973 Vn.[bhsdq] represent a scalar. Therefore any
974 Vn.[bhsdq] should have an index following it.
975 Except in reglists ofcourse. */
976 atype
.defined
|= NTA_HASINDEX
;
978 atype
.defined
|= NTA_HASTYPE
;
980 atype
.type
= parsetype
.type
;
981 atype
.width
= parsetype
.width
;
984 if (skip_past_char (&str
, '['))
988 /* Reject Sn[index] syntax. */
989 if (!is_typed_vecreg
)
991 first_error (_("this type of register can't be indexed"));
995 if (in_reg_list
== TRUE
)
997 first_error (_("index not allowed inside register list"));
1001 atype
.defined
|= NTA_HASINDEX
;
1003 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1005 if (exp
.X_op
!= O_constant
)
1007 first_error (_("constant expression required"));
1011 if (! skip_past_char (&str
, ']'))
1014 atype
.index
= exp
.X_add_number
;
1016 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1018 /* Indexed vector register expected. */
1019 first_error (_("indexed vector register expected"));
1023 /* A vector reg Vn should be typed or indexed. */
1024 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1026 first_error (_("invalid use of vector register"));
1042 Return the register number on success; return PARSE_FAIL otherwise.
1044 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1045 the register (e.g. NEON double or quad reg when either has been requested).
1047 If this is a NEON vector register with additional type information, fill
1048 in the struct pointed to by VECTYPE (if non-NULL).
1050 This parser does not handle register list. */
1053 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1054 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1056 struct vector_type_el atype
;
1058 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1059 /*in_reg_list= */ FALSE
);
1061 if (reg
== PARSE_FAIL
)
1072 static inline bfd_boolean
1073 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1077 && e1
.defined
== e2
.defined
1078 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1081 /* This function parses a list of vector registers of type TYPE.
1082 On success, it returns the parsed register list information in the
1083 following encoded format:
1085 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1086 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1088 The information of the register shape and/or index is returned in
1091 It returns PARSE_FAIL if the register list is invalid.
1093 The list contains one to four registers.
1094 Each register can be one of:
1097 All <T> should be identical.
1098 All <index> should be identical.
1099 There are restrictions on <Vt> numbers which are checked later
1100 (by reg_list_valid_p). */
1103 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1104 struct vector_type_el
*vectype
)
1108 struct vector_type_el typeinfo
, typeinfo_first
;
1113 bfd_boolean error
= FALSE
;
1114 bfd_boolean expect_index
= FALSE
;
1118 set_syntax_error (_("expecting {"));
1124 typeinfo_first
.defined
= 0;
1125 typeinfo_first
.type
= NT_invtype
;
1126 typeinfo_first
.width
= -1;
1127 typeinfo_first
.index
= 0;
1136 str
++; /* skip over '-' */
1139 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1140 /*in_reg_list= */ TRUE
);
1141 if (val
== PARSE_FAIL
)
1143 set_first_syntax_error (_("invalid vector register in list"));
1147 /* reject [bhsd]n */
1148 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1150 set_first_syntax_error (_("invalid scalar register in list"));
1155 if (typeinfo
.defined
& NTA_HASINDEX
)
1156 expect_index
= TRUE
;
1160 if (val
< val_range
)
1162 set_first_syntax_error
1163 (_("invalid range in vector register list"));
1172 typeinfo_first
= typeinfo
;
1173 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1175 set_first_syntax_error
1176 (_("type mismatch in vector register list"));
1181 for (i
= val_range
; i
<= val
; i
++)
1183 ret_val
|= i
<< (5 * nb_regs
);
1188 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1190 skip_whitespace (str
);
1193 set_first_syntax_error (_("end of vector register list not found"));
1198 skip_whitespace (str
);
1202 if (skip_past_char (&str
, '['))
1206 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1207 if (exp
.X_op
!= O_constant
)
1209 set_first_syntax_error (_("constant expression required."));
1212 if (! skip_past_char (&str
, ']'))
1215 typeinfo_first
.index
= exp
.X_add_number
;
1219 set_first_syntax_error (_("expected index"));
1226 set_first_syntax_error (_("too many registers in vector register list"));
1229 else if (nb_regs
== 0)
1231 set_first_syntax_error (_("empty vector register list"));
1237 *vectype
= typeinfo_first
;
1239 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1242 /* Directives: register aliases. */
1245 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1250 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1253 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1256 /* Only warn about a redefinition if it's not defined as the
1258 else if (new->number
!= number
|| new->type
!= type
)
1259 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1264 name
= xstrdup (str
);
1265 new = XNEW (reg_entry
);
1268 new->number
= number
;
1270 new->builtin
= FALSE
;
1272 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1278 /* Look for the .req directive. This is of the form:
1280 new_register_name .req existing_register_name
1282 If we find one, or if it looks sufficiently like one that we want to
1283 handle any error here, return TRUE. Otherwise return FALSE. */
1286 create_register_alias (char *newname
, char *p
)
1288 const reg_entry
*old
;
1289 char *oldname
, *nbuf
;
1292 /* The input scrubber ensures that whitespace after the mnemonic is
1293 collapsed to single spaces. */
1295 if (strncmp (oldname
, " .req ", 6) != 0)
1299 if (*oldname
== '\0')
1302 old
= hash_find (aarch64_reg_hsh
, oldname
);
1305 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1309 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1310 the desired alias name, and p points to its end. If not, then
1311 the desired alias name is in the global original_case_string. */
1312 #ifdef TC_CASE_SENSITIVE
1315 newname
= original_case_string
;
1316 nlen
= strlen (newname
);
1319 nbuf
= xmemdup0 (newname
, nlen
);
1321 /* Create aliases under the new name as stated; an all-lowercase
1322 version of the new name; and an all-uppercase version of the new
1324 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1326 for (p
= nbuf
; *p
; p
++)
1329 if (strncmp (nbuf
, newname
, nlen
))
1331 /* If this attempt to create an additional alias fails, do not bother
1332 trying to create the all-lower case alias. We will fail and issue
1333 a second, duplicate error message. This situation arises when the
1334 programmer does something like:
1337 The second .req creates the "Foo" alias but then fails to create
1338 the artificial FOO alias because it has already been created by the
1340 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1347 for (p
= nbuf
; *p
; p
++)
1350 if (strncmp (nbuf
, newname
, nlen
))
1351 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1358 /* Should never be called, as .req goes between the alias and the
1359 register name, not at the beginning of the line. */
1361 s_req (int a ATTRIBUTE_UNUSED
)
1363 as_bad (_("invalid syntax for .req directive"));
1366 /* The .unreq directive deletes an alias which was previously defined
1367 by .req. For example:
1373 s_unreq (int a ATTRIBUTE_UNUSED
)
1378 name
= input_line_pointer
;
1380 while (*input_line_pointer
!= 0
1381 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1382 ++input_line_pointer
;
1384 saved_char
= *input_line_pointer
;
1385 *input_line_pointer
= 0;
1388 as_bad (_("invalid syntax for .unreq directive"));
1391 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1394 as_bad (_("unknown register alias '%s'"), name
);
1395 else if (reg
->builtin
)
1396 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1403 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1404 free ((char *) reg
->name
);
1407 /* Also locate the all upper case and all lower case versions.
1408 Do not complain if we cannot find one or the other as it
1409 was probably deleted above. */
1411 nbuf
= strdup (name
);
1412 for (p
= nbuf
; *p
; p
++)
1414 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1417 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1418 free ((char *) reg
->name
);
1422 for (p
= nbuf
; *p
; p
++)
1424 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1427 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1428 free ((char *) reg
->name
);
1436 *input_line_pointer
= saved_char
;
1437 demand_empty_rest_of_line ();
1440 /* Directives: Instruction set selection. */
1443 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1444 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1445 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1446 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1448 /* Create a new mapping symbol for the transition to STATE. */
1451 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1454 const char *symname
;
1461 type
= BSF_NO_FLAGS
;
1465 type
= BSF_NO_FLAGS
;
1471 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1472 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1474 /* Save the mapping symbols for future reference. Also check that
1475 we do not place two mapping symbols at the same offset within a
1476 frag. We'll handle overlap between frags in
1477 check_mapping_symbols.
1479 If .fill or other data filling directive generates zero sized data,
1480 the mapping symbol for the following code will have the same value
1481 as the one generated for the data filling directive. In this case,
1482 we replace the old symbol with the new one at the same address. */
1485 if (frag
->tc_frag_data
.first_map
!= NULL
)
1487 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1488 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1491 frag
->tc_frag_data
.first_map
= symbolP
;
1493 if (frag
->tc_frag_data
.last_map
!= NULL
)
1495 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1496 S_GET_VALUE (symbolP
));
1497 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1498 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1501 frag
->tc_frag_data
.last_map
= symbolP
;
1504 /* We must sometimes convert a region marked as code to data during
1505 code alignment, if an odd number of bytes have to be padded. The
1506 code mapping symbol is pushed to an aligned address. */
1509 insert_data_mapping_symbol (enum mstate state
,
1510 valueT value
, fragS
* frag
, offsetT bytes
)
1512 /* If there was already a mapping symbol, remove it. */
1513 if (frag
->tc_frag_data
.last_map
!= NULL
1514 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1515 frag
->fr_address
+ value
)
1517 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1521 know (frag
->tc_frag_data
.first_map
== symp
);
1522 frag
->tc_frag_data
.first_map
= NULL
;
1524 frag
->tc_frag_data
.last_map
= NULL
;
1525 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1528 make_mapping_symbol (MAP_DATA
, value
, frag
);
1529 make_mapping_symbol (state
, value
+ bytes
, frag
);
1532 static void mapping_state_2 (enum mstate state
, int max_chars
);
1534 /* Set the mapping state to STATE. Only call this when about to
1535 emit some STATE bytes to the file. */
1538 mapping_state (enum mstate state
)
1540 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1542 if (state
== MAP_INSN
)
1543 /* AArch64 instructions require 4-byte alignment. When emitting
1544 instructions into any section, record the appropriate section
1546 record_alignment (now_seg
, 2);
1548 if (mapstate
== state
)
1549 /* The mapping symbol has already been emitted.
1550 There is nothing else to do. */
1553 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1554 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1555 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1556 evaluated later in the next else. */
1558 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1560 /* Only add the symbol if the offset is > 0:
1561 if we're at the first frag, check it's size > 0;
1562 if we're not at the first frag, then for sure
1563 the offset is > 0. */
1564 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1565 const int add_symbol
= (frag_now
!= frag_first
)
1566 || (frag_now_fix () > 0);
1569 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1573 mapping_state_2 (state
, 0);
1576 /* Same as mapping_state, but MAX_CHARS bytes have already been
1577 allocated. Put the mapping symbol that far back. */
1580 mapping_state_2 (enum mstate state
, int max_chars
)
1582 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1584 if (!SEG_NORMAL (now_seg
))
1587 if (mapstate
== state
)
1588 /* The mapping symbol has already been emitted.
1589 There is nothing else to do. */
1592 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1593 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1596 #define mapping_state(x) /* nothing */
1597 #define mapping_state_2(x, y) /* nothing */
1600 /* Directives: sectioning and alignment. */
1603 s_bss (int ignore ATTRIBUTE_UNUSED
)
1605 /* We don't support putting frags in the BSS segment, we fake it by
1606 marking in_bss, then looking at s_skip for clues. */
1607 subseg_set (bss_section
, 0);
1608 demand_empty_rest_of_line ();
1609 mapping_state (MAP_DATA
);
1613 s_even (int ignore ATTRIBUTE_UNUSED
)
1615 /* Never make frag if expect extra pass. */
1617 frag_align (1, 0, 0);
1619 record_alignment (now_seg
, 1);
1621 demand_empty_rest_of_line ();
1624 /* Directives: Literal pools. */
1626 static literal_pool
*
1627 find_literal_pool (int size
)
1631 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1633 if (pool
->section
== now_seg
1634 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1641 static literal_pool
*
1642 find_or_make_literal_pool (int size
)
1644 /* Next literal pool ID number. */
1645 static unsigned int latest_pool_num
= 1;
1648 pool
= find_literal_pool (size
);
1652 /* Create a new pool. */
1653 pool
= XNEW (literal_pool
);
1657 /* Currently we always put the literal pool in the current text
1658 section. If we were generating "small" model code where we
1659 knew that all code and initialised data was within 1MB then
1660 we could output literals to mergeable, read-only data
1663 pool
->next_free_entry
= 0;
1664 pool
->section
= now_seg
;
1665 pool
->sub_section
= now_subseg
;
1667 pool
->next
= list_of_pools
;
1668 pool
->symbol
= NULL
;
1670 /* Add it to the list. */
1671 list_of_pools
= pool
;
1674 /* New pools, and emptied pools, will have a NULL symbol. */
1675 if (pool
->symbol
== NULL
)
1677 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1678 (valueT
) 0, &zero_address_frag
);
1679 pool
->id
= latest_pool_num
++;
1686 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1687 Return TRUE on success, otherwise return FALSE. */
1689 add_to_lit_pool (expressionS
*exp
, int size
)
1694 pool
= find_or_make_literal_pool (size
);
1696 /* Check if this literal value is already in the pool. */
1697 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1699 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1701 if ((litexp
->X_op
== exp
->X_op
)
1702 && (exp
->X_op
== O_constant
)
1703 && (litexp
->X_add_number
== exp
->X_add_number
)
1704 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1707 if ((litexp
->X_op
== exp
->X_op
)
1708 && (exp
->X_op
== O_symbol
)
1709 && (litexp
->X_add_number
== exp
->X_add_number
)
1710 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1711 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1715 /* Do we need to create a new entry? */
1716 if (entry
== pool
->next_free_entry
)
1718 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1720 set_syntax_error (_("literal pool overflow"));
1724 pool
->literals
[entry
].exp
= *exp
;
1725 pool
->next_free_entry
+= 1;
1726 if (exp
->X_op
== O_big
)
1728 /* PR 16688: Bignums are held in a single global array. We must
1729 copy and preserve that value now, before it is overwritten. */
1730 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1732 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1733 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1736 pool
->literals
[entry
].bignum
= NULL
;
1739 exp
->X_op
= O_symbol
;
1740 exp
->X_add_number
= ((int) entry
) * size
;
1741 exp
->X_add_symbol
= pool
->symbol
;
1746 /* Can't use symbol_new here, so have to create a symbol and then at
1747 a later date assign it a value. Thats what these functions do. */
1750 symbol_locate (symbolS
* symbolP
,
1751 const char *name
,/* It is copied, the caller can modify. */
1752 segT segment
, /* Segment identifier (SEG_<something>). */
1753 valueT valu
, /* Symbol value. */
1754 fragS
* frag
) /* Associated fragment. */
1757 char *preserved_copy_of_name
;
1759 name_length
= strlen (name
) + 1; /* +1 for \0. */
1760 obstack_grow (¬es
, name
, name_length
);
1761 preserved_copy_of_name
= obstack_finish (¬es
);
1763 #ifdef tc_canonicalize_symbol_name
1764 preserved_copy_of_name
=
1765 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1768 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1770 S_SET_SEGMENT (symbolP
, segment
);
1771 S_SET_VALUE (symbolP
, valu
);
1772 symbol_clear_list_pointers (symbolP
);
1774 symbol_set_frag (symbolP
, frag
);
1776 /* Link to end of symbol chain. */
1778 extern int symbol_table_frozen
;
1780 if (symbol_table_frozen
)
1784 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1786 obj_symbol_new_hook (symbolP
);
1788 #ifdef tc_symbol_new_hook
1789 tc_symbol_new_hook (symbolP
);
1793 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1794 #endif /* DEBUG_SYMS */
1799 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1806 for (align
= 2; align
<= 4; align
++)
1808 int size
= 1 << align
;
1810 pool
= find_literal_pool (size
);
1811 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1814 /* Align pool as you have word accesses.
1815 Only make a frag if we have to. */
1817 frag_align (align
, 0, 0);
1819 mapping_state (MAP_DATA
);
1821 record_alignment (now_seg
, align
);
1823 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1825 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1826 (valueT
) frag_now_fix (), frag_now
);
1827 symbol_table_insert (pool
->symbol
);
1829 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1831 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1833 if (exp
->X_op
== O_big
)
1835 /* PR 16688: Restore the global bignum value. */
1836 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1837 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1838 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1841 /* First output the expression in the instruction to the pool. */
1842 emit_expr (exp
, size
); /* .word|.xword */
1844 if (exp
->X_op
== O_big
)
1846 free (pool
->literals
[entry
].bignum
);
1847 pool
->literals
[entry
].bignum
= NULL
;
1851 /* Mark the pool as empty. */
1852 pool
->next_free_entry
= 0;
1853 pool
->symbol
= NULL
;
1858 /* Forward declarations for functions below, in the MD interface
1860 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1861 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1863 /* Directives: Data. */
1864 /* N.B. the support for relocation suffix in this directive needs to be
1865 implemented properly. */
1868 s_aarch64_elf_cons (int nbytes
)
1872 #ifdef md_flush_pending_output
1873 md_flush_pending_output ();
1876 if (is_it_end_of_statement ())
1878 demand_empty_rest_of_line ();
1882 #ifdef md_cons_align
1883 md_cons_align (nbytes
);
1886 mapping_state (MAP_DATA
);
1889 struct reloc_table_entry
*reloc
;
1893 if (exp
.X_op
!= O_symbol
)
1894 emit_expr (&exp
, (unsigned int) nbytes
);
1897 skip_past_char (&input_line_pointer
, '#');
1898 if (skip_past_char (&input_line_pointer
, ':'))
1900 reloc
= find_reloc_table_entry (&input_line_pointer
);
1902 as_bad (_("unrecognized relocation suffix"));
1904 as_bad (_("unimplemented relocation suffix"));
1905 ignore_rest_of_line ();
1909 emit_expr (&exp
, (unsigned int) nbytes
);
1912 while (*input_line_pointer
++ == ',');
1914 /* Put terminator back into stream. */
1915 input_line_pointer
--;
1916 demand_empty_rest_of_line ();
1919 #endif /* OBJ_ELF */
1921 /* Output a 32-bit word, but mark as an instruction. */
1924 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1928 #ifdef md_flush_pending_output
1929 md_flush_pending_output ();
1932 if (is_it_end_of_statement ())
1934 demand_empty_rest_of_line ();
1938 /* Sections are assumed to start aligned. In executable section, there is no
1939 MAP_DATA symbol pending. So we only align the address during
1940 MAP_DATA --> MAP_INSN transition.
1941 For other sections, this is not guaranteed. */
1942 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1943 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1944 frag_align_code (2, 0);
1947 mapping_state (MAP_INSN
);
1953 if (exp
.X_op
!= O_constant
)
1955 as_bad (_("constant expression required"));
1956 ignore_rest_of_line ();
1960 if (target_big_endian
)
1962 unsigned int val
= exp
.X_add_number
;
1963 exp
.X_add_number
= SWAP_32 (val
);
1965 emit_expr (&exp
, 4);
1967 while (*input_line_pointer
++ == ',');
1969 /* Put terminator back into stream. */
1970 input_line_pointer
--;
1971 demand_empty_rest_of_line ();
1975 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1978 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1984 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1985 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1987 demand_empty_rest_of_line ();
1990 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1993 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1997 /* Since we're just labelling the code, there's no need to define a
2000 /* Make sure there is enough room in this frag for the following
2001 blr. This trick only works if the blr follows immediately after
2002 the .tlsdesc directive. */
2004 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2005 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2007 demand_empty_rest_of_line ();
2010 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2013 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2019 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2020 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2022 demand_empty_rest_of_line ();
2024 #endif /* OBJ_ELF */
2026 static void s_aarch64_arch (int);
2027 static void s_aarch64_cpu (int);
2028 static void s_aarch64_arch_extension (int);
2030 /* This table describes all the machine specific pseudo-ops the assembler
2031 has to support. The fields are:
2032 pseudo-op name without dot
2033 function to call to execute this pseudo-op
2034 Integer arg to pass to the function. */
2036 const pseudo_typeS md_pseudo_table
[] = {
2037 /* Never called because '.req' does not start a line. */
2039 {"unreq", s_unreq
, 0},
2041 {"even", s_even
, 0},
2042 {"ltorg", s_ltorg
, 0},
2043 {"pool", s_ltorg
, 0},
2044 {"cpu", s_aarch64_cpu
, 0},
2045 {"arch", s_aarch64_arch
, 0},
2046 {"arch_extension", s_aarch64_arch_extension
, 0},
2047 {"inst", s_aarch64_inst
, 0},
2049 {"tlsdescadd", s_tlsdescadd
, 0},
2050 {"tlsdesccall", s_tlsdesccall
, 0},
2051 {"tlsdescldr", s_tlsdescldr
, 0},
2052 {"word", s_aarch64_elf_cons
, 4},
2053 {"long", s_aarch64_elf_cons
, 4},
2054 {"xword", s_aarch64_elf_cons
, 8},
2055 {"dword", s_aarch64_elf_cons
, 8},
2061 /* Check whether STR points to a register name followed by a comma or the
2062 end of line; REG_TYPE indicates which register types are checked
2063 against. Return TRUE if STR is such a register name; otherwise return
2064 FALSE. The function does not intend to produce any diagnostics, but since
2065 the register parser aarch64_reg_parse, which is called by this function,
2066 does produce diagnostics, we call clear_error to clear any diagnostics
2067 that may be generated by aarch64_reg_parse.
2068 Also, the function returns FALSE directly if there is any user error
2069 present at the function entry. This prevents the existing diagnostics
2070 state from being spoiled.
2071 The function currently serves parse_constant_immediate and
2072 parse_big_immediate only. */
2074 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2078 /* Prevent the diagnostics state from being spoiled. */
2082 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2084 /* Clear the parsing error that may be set by the reg parser. */
2087 if (reg
== PARSE_FAIL
)
2090 skip_whitespace (str
);
2091 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2097 /* Parser functions used exclusively in instruction operands. */
2099 /* Parse an immediate expression which may not be constant.
2101 To prevent the expression parser from pushing a register name
2102 into the symbol table as an undefined symbol, firstly a check is
2103 done to find out whether STR is a register of type REG_TYPE followed
2104 by a comma or the end of line. Return FALSE if STR is such a string. */
2107 parse_immediate_expression (char **str
, expressionS
*exp
,
2108 aarch64_reg_type reg_type
)
2110 if (reg_name_p (*str
, reg_type
))
2112 set_recoverable_error (_("immediate operand required"));
2116 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2118 if (exp
->X_op
== O_absent
)
2120 set_fatal_syntax_error (_("missing immediate expression"));
2127 /* Constant immediate-value read function for use in insn parsing.
2128 STR points to the beginning of the immediate (with the optional
2129 leading #); *VAL receives the value. REG_TYPE says which register
2130 names should be treated as registers rather than as symbolic immediates.
2132 Return TRUE on success; otherwise return FALSE. */
2135 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2139 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2142 if (exp
.X_op
!= O_constant
)
2144 set_syntax_error (_("constant expression required"));
2148 *val
= exp
.X_add_number
;
2153 encode_imm_float_bits (uint32_t imm
)
2155 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2156 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2159 /* Return TRUE if the single-precision floating-point value encoded in IMM
2160 can be expressed in the AArch64 8-bit signed floating-point format with
2161 3-bit exponent and normalized 4 bits of precision; in other words, the
2162 floating-point value must be expressable as
2163 (+/-) n / 16 * power (2, r)
2164 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2167 aarch64_imm_float_p (uint32_t imm
)
2169 /* If a single-precision floating-point value has the following bit
2170 pattern, it can be expressed in the AArch64 8-bit floating-point
2173 3 32222222 2221111111111
2174 1 09876543 21098765432109876543210
2175 n Eeeeeexx xxxx0000000000000000000
2177 where n, e and each x are either 0 or 1 independently, with
2182 /* Prepare the pattern for 'Eeeeee'. */
2183 if (((imm
>> 30) & 0x1) == 0)
2184 pattern
= 0x3e000000;
2186 pattern
= 0x40000000;
2188 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2189 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2192 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2193 as an IEEE float without any loss of precision. Store the value in
2197 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2199 /* If a double-precision floating-point value has the following bit
2200 pattern, it can be expressed in a float:
2202 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2203 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2204 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2206 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2207 if Eeee_eeee != 1111_1111
2209 where n, e, s and S are either 0 or 1 independently and where ~ is the
2213 uint32_t high32
= imm
>> 32;
2214 uint32_t low32
= imm
;
2216 /* Lower 29 bits need to be 0s. */
2217 if ((imm
& 0x1fffffff) != 0)
2220 /* Prepare the pattern for 'Eeeeeeeee'. */
2221 if (((high32
>> 30) & 0x1) == 0)
2222 pattern
= 0x38000000;
2224 pattern
= 0x40000000;
2227 if ((high32
& 0x78000000) != pattern
)
2230 /* Check Eeee_eeee != 1111_1111. */
2231 if ((high32
& 0x7ff00000) == 0x47f00000)
2234 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2235 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2236 | (low32
>> 29)); /* 3 S bits. */
2240 /* Return true if we should treat OPERAND as a double-precision
2241 floating-point operand rather than a single-precision one. */
2243 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2245 /* Check for unsuffixed SVE registers, which are allowed
2246 for LDR and STR but not in instructions that require an
2247 immediate. We get better error messages if we arbitrarily
2248 pick one size, parse the immediate normally, and then
2249 report the match failure in the normal way. */
2250 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2251 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2254 /* Parse a floating-point immediate. Return TRUE on success and return the
2255 value in *IMMED in the format of IEEE754 single-precision encoding.
2256 *CCP points to the start of the string; DP_P is TRUE when the immediate
2257 is expected to be in double-precision (N.B. this only matters when
2258 hexadecimal representation is involved). REG_TYPE says which register
2259 names should be treated as registers rather than as symbolic immediates.
2261 This routine accepts any IEEE float; it is up to the callers to reject
2265 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2266 aarch64_reg_type reg_type
)
2270 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2271 int found_fpchar
= 0;
2273 unsigned fpword
= 0;
2274 bfd_boolean hex_p
= FALSE
;
2276 skip_past_char (&str
, '#');
2279 skip_whitespace (fpnum
);
2281 if (strncmp (fpnum
, "0x", 2) == 0)
2283 /* Support the hexadecimal representation of the IEEE754 encoding.
2284 Double-precision is expected when DP_P is TRUE, otherwise the
2285 representation should be in single-precision. */
2286 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2291 if (!can_convert_double_to_float (val
, &fpword
))
2294 else if ((uint64_t) val
> 0xffffffff)
2303 if (reg_name_p (str
, reg_type
))
2305 set_recoverable_error (_("immediate operand required"));
2309 /* We must not accidentally parse an integer as a floating-point number.
2310 Make sure that the value we parse is not an integer by checking for
2311 special characters '.' or 'e'. */
2312 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2313 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2327 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2330 /* Our FP word must be 32 bits (single-precision FP). */
2331 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2333 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2343 set_fatal_syntax_error (_("invalid floating-point constant"));
2347 /* Less-generic immediate-value read function with the possibility of loading
2348 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2351 To prevent the expression parser from pushing a register name into the
2352 symbol table as an undefined symbol, a check is firstly done to find
2353 out whether STR is a register of type REG_TYPE followed by a comma or
2354 the end of line. Return FALSE if STR is such a register. */
2357 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2361 if (reg_name_p (ptr
, reg_type
))
2363 set_syntax_error (_("immediate operand required"));
2367 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2369 if (inst
.reloc
.exp
.X_op
== O_constant
)
2370 *imm
= inst
.reloc
.exp
.X_add_number
;
2377 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2378 if NEED_LIBOPCODES is non-zero, the fixup will need
2379 assistance from the libopcodes. */
2382 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2383 const aarch64_opnd_info
*operand
,
2384 int need_libopcodes_p
)
2386 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2387 reloc
->opnd
= operand
->type
;
2388 if (need_libopcodes_p
)
2389 reloc
->need_libopcodes_p
= 1;
2392 /* Return TRUE if the instruction needs to be fixed up later internally by
2393 the GAS; otherwise return FALSE. */
2395 static inline bfd_boolean
2396 aarch64_gas_internal_fixup_p (void)
2398 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2401 /* Assign the immediate value to the relavant field in *OPERAND if
2402 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2403 needs an internal fixup in a later stage.
2404 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2405 IMM.VALUE that may get assigned with the constant. */
2407 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2408 aarch64_opnd_info
*operand
,
2410 int need_libopcodes_p
,
2413 if (reloc
->exp
.X_op
== O_constant
)
2416 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2418 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2419 reloc
->type
= BFD_RELOC_UNUSED
;
2423 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2424 /* Tell libopcodes to ignore this operand or not. This is helpful
2425 when one of the operands needs to be fixed up later but we need
2426 libopcodes to check the other operands. */
2427 operand
->skip
= skip_p
;
2431 /* Relocation modifiers. Each entry in the table contains the textual
2432 name for the relocation which may be placed before a symbol used as
2433 a load/store offset, or add immediate. It must be surrounded by a
2434 leading and trailing colon, for example:
2436 ldr x0, [x1, #:rello:varsym]
2437 add x0, x1, #:rello:varsym */
2439 struct reloc_table_entry
2443 bfd_reloc_code_real_type adr_type
;
2444 bfd_reloc_code_real_type adrp_type
;
2445 bfd_reloc_code_real_type movw_type
;
2446 bfd_reloc_code_real_type add_type
;
2447 bfd_reloc_code_real_type ldst_type
;
2448 bfd_reloc_code_real_type ld_literal_type
;
2451 static struct reloc_table_entry reloc_table
[] = {
2452 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2457 BFD_RELOC_AARCH64_ADD_LO12
,
2458 BFD_RELOC_AARCH64_LDST_LO12
,
2461 /* Higher 21 bits of pc-relative page offset: ADRP */
2464 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2470 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2473 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2479 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2483 BFD_RELOC_AARCH64_MOVW_G0
,
2488 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2492 BFD_RELOC_AARCH64_MOVW_G0_S
,
2497 /* Less significant bits 0-15 of address/value: MOVK, no check */
2501 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2506 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2510 BFD_RELOC_AARCH64_MOVW_G1
,
2515 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2519 BFD_RELOC_AARCH64_MOVW_G1_S
,
2524 /* Less significant bits 16-31 of address/value: MOVK, no check */
2528 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2533 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2537 BFD_RELOC_AARCH64_MOVW_G2
,
2542 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2546 BFD_RELOC_AARCH64_MOVW_G2_S
,
2551 /* Less significant bits 32-47 of address/value: MOVK, no check */
2555 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2560 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2564 BFD_RELOC_AARCH64_MOVW_G3
,
2569 /* Get to the page containing GOT entry for a symbol. */
2572 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2576 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2578 /* 12 bit offset into the page containing GOT entry for that symbol. */
2584 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2587 /* 0-15 bits of address/value: MOVk, no check. */
2591 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2596 /* Most significant bits 16-31 of address/value: MOVZ. */
2600 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2605 /* 15 bit offset into the page containing GOT entry for that symbol. */
2611 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2614 /* Get to the page containing GOT TLS entry for a symbol */
2615 {"gottprel_g0_nc", 0,
2618 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2623 /* Get to the page containing GOT TLS entry for a symbol */
2627 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2632 /* Get to the page containing GOT TLS entry for a symbol */
2634 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2635 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2641 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2646 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2650 /* Lower 16 bits address/value: MOVk. */
2654 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2659 /* Most significant bits 16-31 of address/value: MOVZ. */
2663 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2668 /* Get to the page containing GOT TLS entry for a symbol */
2670 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2671 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2675 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2677 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2682 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2683 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2686 /* Get to the page containing GOT TLS entry for a symbol.
2687 The same as GD, we allocate two consecutive GOT slots
2688 for module index and module offset, the only difference
2689 with GD is the module offset should be intialized to
2690 zero without any outstanding runtime relocation. */
2692 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2693 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2699 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2700 {"tlsldm_lo12_nc", 0,
2704 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2708 /* 12 bit offset into the module TLS base address. */
2713 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2714 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2717 /* Same as dtprel_lo12, no overflow check. */
2718 {"dtprel_lo12_nc", 0,
2722 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2723 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2726 /* bits[23:12] of offset to the module TLS base address. */
2731 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2735 /* bits[15:0] of offset to the module TLS base address. */
2739 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2744 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2748 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2753 /* bits[31:16] of offset to the module TLS base address. */
2757 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2762 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2766 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2771 /* bits[47:32] of offset to the module TLS base address. */
2775 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2780 /* Lower 16 bit offset into GOT entry for a symbol */
2781 {"tlsdesc_off_g0_nc", 0,
2784 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2789 /* Higher 16 bit offset into GOT entry for a symbol */
2790 {"tlsdesc_off_g1", 0,
2793 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2798 /* Get to the page containing GOT TLS entry for a symbol */
2801 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2805 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2807 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2808 {"gottprel_lo12", 0,
2813 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2816 /* Get tp offset for a symbol. */
2821 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2825 /* Get tp offset for a symbol. */
2830 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2834 /* Get tp offset for a symbol. */
2839 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2843 /* Get tp offset for a symbol. */
2844 {"tprel_lo12_nc", 0,
2848 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2852 /* Most significant bits 32-47 of address/value: MOVZ. */
2856 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2861 /* Most significant bits 16-31 of address/value: MOVZ. */
2865 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2870 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2874 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2879 /* Most significant bits 0-15 of address/value: MOVZ. */
2883 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2888 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2892 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2897 /* 15bit offset from got entry to base address of GOT table. */
2903 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2906 /* 14bit offset from got entry to base address of GOT table. */
2912 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2916 /* Given the address of a pointer pointing to the textual name of a
2917 relocation as may appear in assembler source, attempt to find its
2918 details in reloc_table. The pointer will be updated to the character
2919 after the trailing colon. On failure, NULL will be returned;
2920 otherwise return the reloc_table_entry. */
2922 static struct reloc_table_entry
*
2923 find_reloc_table_entry (char **str
)
2926 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2928 int length
= strlen (reloc_table
[i
].name
);
2930 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2931 && (*str
)[length
] == ':')
2933 *str
+= (length
+ 1);
2934 return &reloc_table
[i
];
2941 /* Mode argument to parse_shift and parser_shifter_operand. */
2942 enum parse_shift_mode
2944 SHIFTED_NONE
, /* no shifter allowed */
2945 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2947 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2949 SHIFTED_LSL
, /* bare "lsl #n" */
2950 SHIFTED_MUL
, /* bare "mul #n" */
2951 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2952 SHIFTED_MUL_VL
, /* "mul vl" */
2953 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2956 /* Parse a <shift> operator on an AArch64 data processing instruction.
2957 Return TRUE on success; otherwise return FALSE. */
2959 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2961 const struct aarch64_name_value_pair
*shift_op
;
2962 enum aarch64_modifier_kind kind
;
2968 for (p
= *str
; ISALPHA (*p
); p
++)
2973 set_syntax_error (_("shift expression expected"));
2977 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2979 if (shift_op
== NULL
)
2981 set_syntax_error (_("shift operator expected"));
2985 kind
= aarch64_get_operand_modifier (shift_op
);
2987 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2989 set_syntax_error (_("invalid use of 'MSL'"));
2993 if (kind
== AARCH64_MOD_MUL
2994 && mode
!= SHIFTED_MUL
2995 && mode
!= SHIFTED_MUL_VL
)
2997 set_syntax_error (_("invalid use of 'MUL'"));
3003 case SHIFTED_LOGIC_IMM
:
3004 if (aarch64_extend_operator_p (kind
) == TRUE
)
3006 set_syntax_error (_("extending shift is not permitted"));
3011 case SHIFTED_ARITH_IMM
:
3012 if (kind
== AARCH64_MOD_ROR
)
3014 set_syntax_error (_("'ROR' shift is not permitted"));
3020 if (kind
!= AARCH64_MOD_LSL
)
3022 set_syntax_error (_("only 'LSL' shift is permitted"));
3028 if (kind
!= AARCH64_MOD_MUL
)
3030 set_syntax_error (_("only 'MUL' is permitted"));
3035 case SHIFTED_MUL_VL
:
3036 /* "MUL VL" consists of two separate tokens. Require the first
3037 token to be "MUL" and look for a following "VL". */
3038 if (kind
== AARCH64_MOD_MUL
)
3040 skip_whitespace (p
);
3041 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3044 kind
= AARCH64_MOD_MUL_VL
;
3048 set_syntax_error (_("only 'MUL VL' is permitted"));
3051 case SHIFTED_REG_OFFSET
:
3052 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3053 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3055 set_fatal_syntax_error
3056 (_("invalid shift for the register offset addressing mode"));
3061 case SHIFTED_LSL_MSL
:
3062 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3064 set_syntax_error (_("invalid shift operator"));
3073 /* Whitespace can appear here if the next thing is a bare digit. */
3074 skip_whitespace (p
);
3076 /* Parse shift amount. */
3078 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3079 exp
.X_op
= O_absent
;
3082 if (is_immediate_prefix (*p
))
3087 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3089 if (kind
== AARCH64_MOD_MUL_VL
)
3090 /* For consistency, give MUL VL the same shift amount as an implicit
3092 operand
->shifter
.amount
= 1;
3093 else if (exp
.X_op
== O_absent
)
3095 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
3097 set_syntax_error (_("missing shift amount"));
3100 operand
->shifter
.amount
= 0;
3102 else if (exp
.X_op
!= O_constant
)
3104 set_syntax_error (_("constant shift amount required"));
3107 /* For parsing purposes, MUL #n has no inherent range. The range
3108 depends on the operand and will be checked by operand-specific
3110 else if (kind
!= AARCH64_MOD_MUL
3111 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3113 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3118 operand
->shifter
.amount
= exp
.X_add_number
;
3119 operand
->shifter
.amount_present
= 1;
3122 operand
->shifter
.operator_present
= 1;
3123 operand
->shifter
.kind
= kind
;
3129 /* Parse a <shifter_operand> for a data processing instruction:
3132 #<immediate>, LSL #imm
3134 Validation of immediate operands is deferred to md_apply_fix.
3136 Return TRUE on success; otherwise return FALSE. */
3139 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3140 enum parse_shift_mode mode
)
3144 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3149 /* Accept an immediate expression. */
3150 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3153 /* Accept optional LSL for arithmetic immediate values. */
3154 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3155 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3158 /* Not accept any shifter for logical immediate values. */
3159 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3160 && parse_shift (&p
, operand
, mode
))
3162 set_syntax_error (_("unexpected shift operator"));
3170 /* Parse a <shifter_operand> for a data processing instruction:
3175 #<immediate>, LSL #imm
3177 where <shift> is handled by parse_shift above, and the last two
3178 cases are handled by the function above.
3180 Validation of immediate operands is deferred to md_apply_fix.
3182 Return TRUE on success; otherwise return FALSE. */
3185 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3186 enum parse_shift_mode mode
)
3188 const reg_entry
*reg
;
3189 aarch64_opnd_qualifier_t qualifier
;
3190 enum aarch64_operand_class opd_class
3191 = aarch64_get_operand_class (operand
->type
);
3193 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3196 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3198 set_syntax_error (_("unexpected register in the immediate operand"));
3202 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3204 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3208 operand
->reg
.regno
= reg
->number
;
3209 operand
->qualifier
= qualifier
;
3211 /* Accept optional shift operation on register. */
3212 if (! skip_past_comma (str
))
3215 if (! parse_shift (str
, operand
, mode
))
3220 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3223 (_("integer register expected in the extended/shifted operand "
3228 /* We have a shifted immediate variable. */
3229 return parse_shifter_operand_imm (str
, operand
, mode
);
3232 /* Return TRUE on success; return FALSE otherwise. */
3235 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3236 enum parse_shift_mode mode
)
3240 /* Determine if we have the sequence of characters #: or just :
3241 coming next. If we do, then we check for a :rello: relocation
3242 modifier. If we don't, punt the whole lot to
3243 parse_shifter_operand. */
3245 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3247 struct reloc_table_entry
*entry
;
3255 /* Try to parse a relocation. Anything else is an error. */
3256 if (!(entry
= find_reloc_table_entry (str
)))
3258 set_syntax_error (_("unknown relocation modifier"));
3262 if (entry
->add_type
== 0)
3265 (_("this relocation modifier is not allowed on this instruction"));
3269 /* Save str before we decompose it. */
3272 /* Next, we parse the expression. */
3273 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3276 /* Record the relocation type (use the ADD variant here). */
3277 inst
.reloc
.type
= entry
->add_type
;
3278 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3280 /* If str is empty, we've reached the end, stop here. */
3284 /* Otherwise, we have a shifted reloc modifier, so rewind to
3285 recover the variable name and continue parsing for the shifter. */
3287 return parse_shifter_operand_imm (str
, operand
, mode
);
3290 return parse_shifter_operand (str
, operand
, mode
);
3293 /* Parse all forms of an address expression. Information is written
3294 to *OPERAND and/or inst.reloc.
3296 The A64 instruction set has the following addressing modes:
3299 [base] // in SIMD ld/st structure
3300 [base{,#0}] // in ld/st exclusive
3302 [base,Xm{,LSL #imm}]
3303 [base,Xm,SXTX {#imm}]
3304 [base,Wm,(S|U)XTW {#imm}]
3309 [base],Xm // in SIMD ld/st structure
3310 PC-relative (literal)
3314 [base,Zm.D{,LSL #imm}]
3315 [base,Zm.S,(S|U)XTW {#imm}]
3316 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3319 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3320 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3321 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3323 (As a convenience, the notation "=immediate" is permitted in conjunction
3324 with the pc-relative literal load instructions to automatically place an
3325 immediate value or symbolic address in a nearby literal pool and generate
3326 a hidden label which references it.)
3328 Upon a successful parsing, the address structure in *OPERAND will be
3329 filled in the following way:
3331 .base_regno = <base>
3332 .offset.is_reg // 1 if the offset is a register
3334 .offset.regno = <Rm>
3336 For different addressing modes defined in the A64 ISA:
3339 .pcrel=0; .preind=1; .postind=0; .writeback=0
3341 .pcrel=0; .preind=1; .postind=0; .writeback=1
3343 .pcrel=0; .preind=0; .postind=1; .writeback=1
3344 PC-relative (literal)
3345 .pcrel=1; .preind=1; .postind=0; .writeback=0
3347 The shift/extension information, if any, will be stored in .shifter.
3348 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3349 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3350 corresponding register.
3352 BASE_TYPE says which types of base register should be accepted and
3353 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3354 is the type of shifter that is allowed for immediate offsets,
3355 or SHIFTED_NONE if none.
3357 In all other respects, it is the caller's responsibility to check
3358 for addressing modes not supported by the instruction, and to set
3362 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3363 aarch64_opnd_qualifier_t
*base_qualifier
,
3364 aarch64_opnd_qualifier_t
*offset_qualifier
,
3365 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3366 enum parse_shift_mode imm_shift_mode
)
3369 const reg_entry
*reg
;
3370 expressionS
*exp
= &inst
.reloc
.exp
;
3372 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3373 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3374 if (! skip_past_char (&p
, '['))
3376 /* =immediate or label. */
3377 operand
->addr
.pcrel
= 1;
3378 operand
->addr
.preind
= 1;
3380 /* #:<reloc_op>:<symbol> */
3381 skip_past_char (&p
, '#');
3382 if (skip_past_char (&p
, ':'))
3384 bfd_reloc_code_real_type ty
;
3385 struct reloc_table_entry
*entry
;
3387 /* Try to parse a relocation modifier. Anything else is
3389 entry
= find_reloc_table_entry (&p
);
3392 set_syntax_error (_("unknown relocation modifier"));
3396 switch (operand
->type
)
3398 case AARCH64_OPND_ADDR_PCREL21
:
3400 ty
= entry
->adr_type
;
3404 ty
= entry
->ld_literal_type
;
3411 (_("this relocation modifier is not allowed on this "
3417 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3419 set_syntax_error (_("invalid relocation expression"));
3423 /* #:<reloc_op>:<expr> */
3424 /* Record the relocation type. */
3425 inst
.reloc
.type
= ty
;
3426 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3431 if (skip_past_char (&p
, '='))
3432 /* =immediate; need to generate the literal in the literal pool. */
3433 inst
.gen_lit_pool
= 1;
3435 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3437 set_syntax_error (_("invalid address"));
3448 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3449 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3451 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3454 operand
->addr
.base_regno
= reg
->number
;
3457 if (skip_past_comma (&p
))
3460 operand
->addr
.preind
= 1;
3462 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3465 if (!aarch64_check_reg_type (reg
, offset_type
))
3467 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3472 operand
->addr
.offset
.regno
= reg
->number
;
3473 operand
->addr
.offset
.is_reg
= 1;
3474 /* Shifted index. */
3475 if (skip_past_comma (&p
))
3478 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3479 /* Use the diagnostics set in parse_shift, so not set new
3480 error message here. */
3484 [base,Xm{,LSL #imm}]
3485 [base,Xm,SXTX {#imm}]
3486 [base,Wm,(S|U)XTW {#imm}] */
3487 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3488 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3489 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3491 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3493 set_syntax_error (_("invalid use of 32-bit register offset"));
3496 if (aarch64_get_qualifier_esize (*base_qualifier
)
3497 != aarch64_get_qualifier_esize (*offset_qualifier
))
3499 set_syntax_error (_("offset has different size from base"));
3503 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3505 set_syntax_error (_("invalid use of 64-bit register offset"));
3511 /* [Xn,#:<reloc_op>:<symbol> */
3512 skip_past_char (&p
, '#');
3513 if (skip_past_char (&p
, ':'))
3515 struct reloc_table_entry
*entry
;
3517 /* Try to parse a relocation modifier. Anything else is
3519 if (!(entry
= find_reloc_table_entry (&p
)))
3521 set_syntax_error (_("unknown relocation modifier"));
3525 if (entry
->ldst_type
== 0)
3528 (_("this relocation modifier is not allowed on this "
3533 /* [Xn,#:<reloc_op>: */
3534 /* We now have the group relocation table entry corresponding to
3535 the name in the assembler source. Next, we parse the
3537 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3539 set_syntax_error (_("invalid relocation expression"));
3543 /* [Xn,#:<reloc_op>:<expr> */
3544 /* Record the load/store relocation type. */
3545 inst
.reloc
.type
= entry
->ldst_type
;
3546 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3550 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3552 set_syntax_error (_("invalid expression in the address"));
3556 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3557 /* [Xn,<expr>,<shifter> */
3558 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3564 if (! skip_past_char (&p
, ']'))
3566 set_syntax_error (_("']' expected"));
3570 if (skip_past_char (&p
, '!'))
3572 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3574 set_syntax_error (_("register offset not allowed in pre-indexed "
3575 "addressing mode"));
3579 operand
->addr
.writeback
= 1;
3581 else if (skip_past_comma (&p
))
3584 operand
->addr
.postind
= 1;
3585 operand
->addr
.writeback
= 1;
3587 if (operand
->addr
.preind
)
3589 set_syntax_error (_("cannot combine pre- and post-indexing"));
3593 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3597 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3599 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3603 operand
->addr
.offset
.regno
= reg
->number
;
3604 operand
->addr
.offset
.is_reg
= 1;
3606 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3609 set_syntax_error (_("invalid expression in the address"));
3614 /* If at this point neither .preind nor .postind is set, we have a
3615 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3616 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3618 if (operand
->addr
.writeback
)
3621 set_syntax_error (_("missing offset in the pre-indexed address"));
3624 operand
->addr
.preind
= 1;
3625 inst
.reloc
.exp
.X_op
= O_constant
;
3626 inst
.reloc
.exp
.X_add_number
= 0;
3633 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3636 parse_address (char **str
, aarch64_opnd_info
*operand
)
3638 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3639 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3640 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3643 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3644 The arguments have the same meaning as for parse_address_main.
3645 Return TRUE on success. */
3647 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3648 aarch64_opnd_qualifier_t
*base_qualifier
,
3649 aarch64_opnd_qualifier_t
*offset_qualifier
)
3651 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3652 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3656 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3657 Return TRUE on success; otherwise return FALSE. */
3659 parse_half (char **str
, int *internal_fixup_p
)
3663 skip_past_char (&p
, '#');
3665 gas_assert (internal_fixup_p
);
3666 *internal_fixup_p
= 0;
3670 struct reloc_table_entry
*entry
;
3672 /* Try to parse a relocation. Anything else is an error. */
3674 if (!(entry
= find_reloc_table_entry (&p
)))
3676 set_syntax_error (_("unknown relocation modifier"));
3680 if (entry
->movw_type
== 0)
3683 (_("this relocation modifier is not allowed on this instruction"));
3687 inst
.reloc
.type
= entry
->movw_type
;
3690 *internal_fixup_p
= 1;
3692 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3699 /* Parse an operand for an ADRP instruction:
3701 Return TRUE on success; otherwise return FALSE. */
3704 parse_adrp (char **str
)
3711 struct reloc_table_entry
*entry
;
3713 /* Try to parse a relocation. Anything else is an error. */
3715 if (!(entry
= find_reloc_table_entry (&p
)))
3717 set_syntax_error (_("unknown relocation modifier"));
3721 if (entry
->adrp_type
== 0)
3724 (_("this relocation modifier is not allowed on this instruction"));
3728 inst
.reloc
.type
= entry
->adrp_type
;
3731 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3733 inst
.reloc
.pc_rel
= 1;
3735 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3742 /* Miscellaneous. */
3744 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3745 of SIZE tokens in which index I gives the token for field value I,
3746 or is null if field value I is invalid. REG_TYPE says which register
3747 names should be treated as registers rather than as symbolic immediates.
3749 Return true on success, moving *STR past the operand and storing the
3750 field value in *VAL. */
3753 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3754 size_t size
, aarch64_reg_type reg_type
)
3760 /* Match C-like tokens. */
3762 while (ISALNUM (*q
))
3765 for (i
= 0; i
< size
; ++i
)
3767 && strncasecmp (array
[i
], p
, q
- p
) == 0
3768 && array
[i
][q
- p
] == 0)
3775 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3778 if (exp
.X_op
== O_constant
3779 && (uint64_t) exp
.X_add_number
< size
)
3781 *val
= exp
.X_add_number
;
3786 /* Use the default error for this operand. */
3790 /* Parse an option for a preload instruction. Returns the encoding for the
3791 option, or PARSE_FAIL. */
3794 parse_pldop (char **str
)
3797 const struct aarch64_name_value_pair
*o
;
3800 while (ISALNUM (*q
))
3803 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3811 /* Parse an option for a barrier instruction. Returns the encoding for the
3812 option, or PARSE_FAIL. */
3815 parse_barrier (char **str
)
3818 const asm_barrier_opt
*o
;
3821 while (ISALPHA (*q
))
3824 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3832 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3833 return 0 if successful. Otherwise return PARSE_FAIL. */
3836 parse_barrier_psb (char **str
,
3837 const struct aarch64_name_value_pair
** hint_opt
)
3840 const struct aarch64_name_value_pair
*o
;
3843 while (ISALPHA (*q
))
3846 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3849 set_fatal_syntax_error
3850 ( _("unknown or missing option to PSB"));
3854 if (o
->value
!= 0x11)
3856 /* PSB only accepts option name 'CSYNC'. */
3858 (_("the specified option is not accepted for PSB"));
3867 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3868 Returns the encoding for the option, or PARSE_FAIL.
3870 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3871 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3873 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3874 field, otherwise as a system register.
3878 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3879 int imple_defined_p
, int pstatefield_p
)
3883 const aarch64_sys_reg
*o
;
3887 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3889 *p
++ = TOLOWER (*q
);
3891 /* Assert that BUF be large enough. */
3892 gas_assert (p
- buf
== q
- *str
);
3894 o
= hash_find (sys_regs
, buf
);
3897 if (!imple_defined_p
)
3901 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3902 unsigned int op0
, op1
, cn
, cm
, op2
;
3904 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3907 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3909 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3914 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3915 as_bad (_("selected processor does not support PSTATE field "
3917 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3918 as_bad (_("selected processor does not support system register "
3920 if (aarch64_sys_reg_deprecated_p (o
))
3921 as_warn (_("system register name '%s' is deprecated and may be "
3922 "removed in a future release"), buf
);
3930 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3931 for the option, or NULL. */
3933 static const aarch64_sys_ins_reg
*
3934 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3938 const aarch64_sys_ins_reg
*o
;
3941 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3943 *p
++ = TOLOWER (*q
);
3946 o
= hash_find (sys_ins_regs
, buf
);
3950 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3951 as_bad (_("selected processor does not support system register "
3958 #define po_char_or_fail(chr) do { \
3959 if (! skip_past_char (&str, chr)) \
3963 #define po_reg_or_fail(regtype) do { \
3964 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3965 if (val == PARSE_FAIL) \
3967 set_default_error (); \
3972 #define po_int_reg_or_fail(reg_type) do { \
3973 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3974 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3976 set_default_error (); \
3979 info->reg.regno = reg->number; \
3980 info->qualifier = qualifier; \
3983 #define po_imm_nc_or_fail() do { \
3984 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3988 #define po_imm_or_fail(min, max) do { \
3989 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3991 if (val < min || val > max) \
3993 set_fatal_syntax_error (_("immediate value out of range "\
3994 #min " to "#max)); \
3999 #define po_enum_or_fail(array) do { \
4000 if (!parse_enum_string (&str, &val, array, \
4001 ARRAY_SIZE (array), imm_reg_type)) \
4005 #define po_misc_or_fail(expr) do { \
4010 /* encode the 12-bit imm field of Add/sub immediate */
4011 static inline uint32_t
4012 encode_addsub_imm (uint32_t imm
)
4017 /* encode the shift amount field of Add/sub immediate */
4018 static inline uint32_t
4019 encode_addsub_imm_shift_amount (uint32_t cnt
)
4025 /* encode the imm field of Adr instruction */
4026 static inline uint32_t
4027 encode_adr_imm (uint32_t imm
)
4029 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4030 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4033 /* encode the immediate field of Move wide immediate */
4034 static inline uint32_t
4035 encode_movw_imm (uint32_t imm
)
4040 /* encode the 26-bit offset of unconditional branch */
4041 static inline uint32_t
4042 encode_branch_ofs_26 (uint32_t ofs
)
4044 return ofs
& ((1 << 26) - 1);
4047 /* encode the 19-bit offset of conditional branch and compare & branch */
4048 static inline uint32_t
4049 encode_cond_branch_ofs_19 (uint32_t ofs
)
4051 return (ofs
& ((1 << 19) - 1)) << 5;
4054 /* encode the 19-bit offset of ld literal */
4055 static inline uint32_t
4056 encode_ld_lit_ofs_19 (uint32_t ofs
)
4058 return (ofs
& ((1 << 19) - 1)) << 5;
4061 /* Encode the 14-bit offset of test & branch. */
4062 static inline uint32_t
4063 encode_tst_branch_ofs_14 (uint32_t ofs
)
4065 return (ofs
& ((1 << 14) - 1)) << 5;
4068 /* Encode the 16-bit imm field of svc/hvc/smc. */
4069 static inline uint32_t
4070 encode_svc_imm (uint32_t imm
)
4075 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4076 static inline uint32_t
4077 reencode_addsub_switch_add_sub (uint32_t opcode
)
4079 return opcode
^ (1 << 30);
4082 static inline uint32_t
4083 reencode_movzn_to_movz (uint32_t opcode
)
4085 return opcode
| (1 << 30);
4088 static inline uint32_t
4089 reencode_movzn_to_movn (uint32_t opcode
)
4091 return opcode
& ~(1 << 30);
4094 /* Overall per-instruction processing. */
4096 /* We need to be able to fix up arbitrary expressions in some statements.
4097 This is so that we can handle symbols that are an arbitrary distance from
4098 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4099 which returns part of an address in a form which will be valid for
4100 a data instruction. We do this by pushing the expression into a symbol
4101 in the expr_section, and creating a fix for that. */
4104 fix_new_aarch64 (fragS
* frag
,
4106 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4116 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4120 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4127 /* Diagnostics on operands errors. */
4129 /* By default, output verbose error message.
4130 Disable the verbose error message by -mno-verbose-error. */
4131 static int verbose_error_p
= 1;
4133 #ifdef DEBUG_AARCH64
4134 /* N.B. this is only for the purpose of debugging. */
4135 const char* operand_mismatch_kind_names
[] =
4138 "AARCH64_OPDE_RECOVERABLE",
4139 "AARCH64_OPDE_SYNTAX_ERROR",
4140 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4141 "AARCH64_OPDE_INVALID_VARIANT",
4142 "AARCH64_OPDE_OUT_OF_RANGE",
4143 "AARCH64_OPDE_UNALIGNED",
4144 "AARCH64_OPDE_REG_LIST",
4145 "AARCH64_OPDE_OTHER_ERROR",
4147 #endif /* DEBUG_AARCH64 */
4149 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4151 When multiple errors of different kinds are found in the same assembly
4152 line, only the error of the highest severity will be picked up for
4153 issuing the diagnostics. */
4155 static inline bfd_boolean
4156 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4157 enum aarch64_operand_error_kind rhs
)
4159 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4160 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4161 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4162 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4163 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4164 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4165 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4166 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4170 /* Helper routine to get the mnemonic name from the assembly instruction
4171 line; should only be called for the diagnosis purpose, as there is
4172 string copy operation involved, which may affect the runtime
4173 performance if used in elsewhere. */
4176 get_mnemonic_name (const char *str
)
4178 static char mnemonic
[32];
4181 /* Get the first 15 bytes and assume that the full name is included. */
4182 strncpy (mnemonic
, str
, 31);
4183 mnemonic
[31] = '\0';
4185 /* Scan up to the end of the mnemonic, which must end in white space,
4186 '.', or end of string. */
4187 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4192 /* Append '...' to the truncated long name. */
4193 if (ptr
- mnemonic
== 31)
4194 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4200 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4202 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4203 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4206 /* Data strutures storing one user error in the assembly code related to
4209 struct operand_error_record
4211 const aarch64_opcode
*opcode
;
4212 aarch64_operand_error detail
;
4213 struct operand_error_record
*next
;
4216 typedef struct operand_error_record operand_error_record
;
4218 struct operand_errors
4220 operand_error_record
*head
;
4221 operand_error_record
*tail
;
4224 typedef struct operand_errors operand_errors
;
4226 /* Top-level data structure reporting user errors for the current line of
4228 The way md_assemble works is that all opcodes sharing the same mnemonic
4229 name are iterated to find a match to the assembly line. In this data
4230 structure, each of the such opcodes will have one operand_error_record
4231 allocated and inserted. In other words, excessive errors related with
4232 a single opcode are disregarded. */
4233 operand_errors operand_error_report
;
4235 /* Free record nodes. */
4236 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4238 /* Initialize the data structure that stores the operand mismatch
4239 information on assembling one line of the assembly code. */
4241 init_operand_error_report (void)
4243 if (operand_error_report
.head
!= NULL
)
4245 gas_assert (operand_error_report
.tail
!= NULL
);
4246 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4247 free_opnd_error_record_nodes
= operand_error_report
.head
;
4248 operand_error_report
.head
= NULL
;
4249 operand_error_report
.tail
= NULL
;
4252 gas_assert (operand_error_report
.tail
== NULL
);
4255 /* Return TRUE if some operand error has been recorded during the
4256 parsing of the current assembly line using the opcode *OPCODE;
4257 otherwise return FALSE. */
4258 static inline bfd_boolean
4259 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4261 operand_error_record
*record
= operand_error_report
.head
;
4262 return record
&& record
->opcode
== opcode
;
4265 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4266 OPCODE field is initialized with OPCODE.
4267 N.B. only one record for each opcode, i.e. the maximum of one error is
4268 recorded for each instruction template. */
4271 add_operand_error_record (const operand_error_record
* new_record
)
4273 const aarch64_opcode
*opcode
= new_record
->opcode
;
4274 operand_error_record
* record
= operand_error_report
.head
;
4276 /* The record may have been created for this opcode. If not, we need
4278 if (! opcode_has_operand_error_p (opcode
))
4280 /* Get one empty record. */
4281 if (free_opnd_error_record_nodes
== NULL
)
4283 record
= XNEW (operand_error_record
);
4287 record
= free_opnd_error_record_nodes
;
4288 free_opnd_error_record_nodes
= record
->next
;
4290 record
->opcode
= opcode
;
4291 /* Insert at the head. */
4292 record
->next
= operand_error_report
.head
;
4293 operand_error_report
.head
= record
;
4294 if (operand_error_report
.tail
== NULL
)
4295 operand_error_report
.tail
= record
;
4297 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4298 && record
->detail
.index
<= new_record
->detail
.index
4299 && operand_error_higher_severity_p (record
->detail
.kind
,
4300 new_record
->detail
.kind
))
4302 /* In the case of multiple errors found on operands related with a
4303 single opcode, only record the error of the leftmost operand and
4304 only if the error is of higher severity. */
4305 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4306 " the existing error %s on operand %d",
4307 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4308 new_record
->detail
.index
,
4309 operand_mismatch_kind_names
[record
->detail
.kind
],
4310 record
->detail
.index
);
4314 record
->detail
= new_record
->detail
;
4318 record_operand_error_info (const aarch64_opcode
*opcode
,
4319 aarch64_operand_error
*error_info
)
4321 operand_error_record record
;
4322 record
.opcode
= opcode
;
4323 record
.detail
= *error_info
;
4324 add_operand_error_record (&record
);
4327 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4328 error message *ERROR, for operand IDX (count from 0). */
4331 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4332 enum aarch64_operand_error_kind kind
,
4335 aarch64_operand_error info
;
4336 memset(&info
, 0, sizeof (info
));
4340 record_operand_error_info (opcode
, &info
);
4344 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4345 enum aarch64_operand_error_kind kind
,
4346 const char* error
, const int *extra_data
)
4348 aarch64_operand_error info
;
4352 info
.data
[0] = extra_data
[0];
4353 info
.data
[1] = extra_data
[1];
4354 info
.data
[2] = extra_data
[2];
4355 record_operand_error_info (opcode
, &info
);
4359 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4360 const char* error
, int lower_bound
,
4363 int data
[3] = {lower_bound
, upper_bound
, 0};
4364 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4368 /* Remove the operand error record for *OPCODE. */
4369 static void ATTRIBUTE_UNUSED
4370 remove_operand_error_record (const aarch64_opcode
*opcode
)
4372 if (opcode_has_operand_error_p (opcode
))
4374 operand_error_record
* record
= operand_error_report
.head
;
4375 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4376 operand_error_report
.head
= record
->next
;
4377 record
->next
= free_opnd_error_record_nodes
;
4378 free_opnd_error_record_nodes
= record
;
4379 if (operand_error_report
.head
== NULL
)
4381 gas_assert (operand_error_report
.tail
== record
);
4382 operand_error_report
.tail
= NULL
;
4387 /* Given the instruction in *INSTR, return the index of the best matched
4388 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4390 Return -1 if there is no qualifier sequence; return the first match
4391 if there is multiple matches found. */
4394 find_best_match (const aarch64_inst
*instr
,
4395 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4397 int i
, num_opnds
, max_num_matched
, idx
;
4399 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4402 DEBUG_TRACE ("no operand");
4406 max_num_matched
= 0;
4409 /* For each pattern. */
4410 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4413 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4415 /* Most opcodes has much fewer patterns in the list. */
4416 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4418 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4422 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4423 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4426 if (num_matched
> max_num_matched
)
4428 max_num_matched
= num_matched
;
4433 DEBUG_TRACE ("return with %d", idx
);
4437 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4438 corresponding operands in *INSTR. */
4441 assign_qualifier_sequence (aarch64_inst
*instr
,
4442 const aarch64_opnd_qualifier_t
*qualifiers
)
4445 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4446 gas_assert (num_opnds
);
4447 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4448 instr
->operands
[i
].qualifier
= *qualifiers
;
4451 /* Print operands for the diagnosis purpose. */
4454 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4455 const aarch64_opnd_info
*opnds
)
4459 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4463 /* We regard the opcode operand info more, however we also look into
4464 the inst->operands to support the disassembling of the optional
4466 The two operand code should be the same in all cases, apart from
4467 when the operand can be optional. */
4468 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4469 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4472 /* Generate the operand string in STR. */
4473 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4477 strcat (buf
, i
== 0 ? " " : ", ");
4479 /* Append the operand string. */
4484 /* Send to stderr a string as information. */
4487 output_info (const char *format
, ...)
4493 file
= as_where (&line
);
4497 fprintf (stderr
, "%s:%u: ", file
, line
);
4499 fprintf (stderr
, "%s: ", file
);
4501 fprintf (stderr
, _("Info: "));
4502 va_start (args
, format
);
4503 vfprintf (stderr
, format
, args
);
4505 (void) putc ('\n', stderr
);
4508 /* Output one operand error record. */
4511 output_operand_error_record (const operand_error_record
*record
, char *str
)
4513 const aarch64_operand_error
*detail
= &record
->detail
;
4514 int idx
= detail
->index
;
4515 const aarch64_opcode
*opcode
= record
->opcode
;
4516 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4517 : AARCH64_OPND_NIL
);
4519 switch (detail
->kind
)
4521 case AARCH64_OPDE_NIL
:
4525 case AARCH64_OPDE_SYNTAX_ERROR
:
4526 case AARCH64_OPDE_RECOVERABLE
:
4527 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4528 case AARCH64_OPDE_OTHER_ERROR
:
4529 /* Use the prepared error message if there is, otherwise use the
4530 operand description string to describe the error. */
4531 if (detail
->error
!= NULL
)
4534 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4536 as_bad (_("%s at operand %d -- `%s'"),
4537 detail
->error
, idx
+ 1, str
);
4541 gas_assert (idx
>= 0);
4542 as_bad (_("operand %d must be %s -- `%s'"), idx
+ 1,
4543 aarch64_get_operand_desc (opd_code
), str
);
4547 case AARCH64_OPDE_INVALID_VARIANT
:
4548 as_bad (_("operand mismatch -- `%s'"), str
);
4549 if (verbose_error_p
)
4551 /* We will try to correct the erroneous instruction and also provide
4552 more information e.g. all other valid variants.
4554 The string representation of the corrected instruction and other
4555 valid variants are generated by
4557 1) obtaining the intermediate representation of the erroneous
4559 2) manipulating the IR, e.g. replacing the operand qualifier;
4560 3) printing out the instruction by calling the printer functions
4561 shared with the disassembler.
4563 The limitation of this method is that the exact input assembly
4564 line cannot be accurately reproduced in some cases, for example an
4565 optional operand present in the actual assembly line will be
4566 omitted in the output; likewise for the optional syntax rules,
4567 e.g. the # before the immediate. Another limitation is that the
4568 assembly symbols and relocation operations in the assembly line
4569 currently cannot be printed out in the error report. Last but not
4570 least, when there is other error(s) co-exist with this error, the
4571 'corrected' instruction may be still incorrect, e.g. given
4572 'ldnp h0,h1,[x0,#6]!'
4573 this diagnosis will provide the version:
4574 'ldnp s0,s1,[x0,#6]!'
4575 which is still not right. */
4576 size_t len
= strlen (get_mnemonic_name (str
));
4580 aarch64_inst
*inst_base
= &inst
.base
;
4581 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4584 reset_aarch64_instruction (&inst
);
4585 inst_base
->opcode
= opcode
;
4587 /* Reset the error report so that there is no side effect on the
4588 following operand parsing. */
4589 init_operand_error_report ();
4592 result
= parse_operands (str
+ len
, opcode
)
4593 && programmer_friendly_fixup (&inst
);
4594 gas_assert (result
);
4595 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4597 gas_assert (!result
);
4599 /* Find the most matched qualifier sequence. */
4600 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4601 gas_assert (qlf_idx
> -1);
4603 /* Assign the qualifiers. */
4604 assign_qualifier_sequence (inst_base
,
4605 opcode
->qualifiers_list
[qlf_idx
]);
4607 /* Print the hint. */
4608 output_info (_(" did you mean this?"));
4609 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4610 print_operands (buf
, opcode
, inst_base
->operands
);
4611 output_info (_(" %s"), buf
);
4613 /* Print out other variant(s) if there is any. */
4615 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4616 output_info (_(" other valid variant(s):"));
4618 /* For each pattern. */
4619 qualifiers_list
= opcode
->qualifiers_list
;
4620 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4622 /* Most opcodes has much fewer patterns in the list.
4623 First NIL qualifier indicates the end in the list. */
4624 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4629 /* Mnemonics name. */
4630 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4632 /* Assign the qualifiers. */
4633 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4635 /* Print instruction. */
4636 print_operands (buf
, opcode
, inst_base
->operands
);
4638 output_info (_(" %s"), buf
);
4644 case AARCH64_OPDE_UNTIED_OPERAND
:
4645 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4646 detail
->index
+ 1, str
);
4649 case AARCH64_OPDE_OUT_OF_RANGE
:
4650 if (detail
->data
[0] != detail
->data
[1])
4651 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4652 detail
->error
? detail
->error
: _("immediate value"),
4653 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4655 as_bad (_("%s must be %d at operand %d -- `%s'"),
4656 detail
->error
? detail
->error
: _("immediate value"),
4657 detail
->data
[0], idx
+ 1, str
);
4660 case AARCH64_OPDE_REG_LIST
:
4661 if (detail
->data
[0] == 1)
4662 as_bad (_("invalid number of registers in the list; "
4663 "only 1 register is expected at operand %d -- `%s'"),
4666 as_bad (_("invalid number of registers in the list; "
4667 "%d registers are expected at operand %d -- `%s'"),
4668 detail
->data
[0], idx
+ 1, str
);
4671 case AARCH64_OPDE_UNALIGNED
:
4672 as_bad (_("immediate value must be a multiple of "
4673 "%d at operand %d -- `%s'"),
4674 detail
->data
[0], idx
+ 1, str
);
4683 /* Process and output the error message about the operand mismatching.
4685 When this function is called, the operand error information had
4686 been collected for an assembly line and there will be multiple
4687 errors in the case of mulitple instruction templates; output the
4688 error message that most closely describes the problem. */
4691 output_operand_error_report (char *str
)
4693 int largest_error_pos
;
4694 const char *msg
= NULL
;
4695 enum aarch64_operand_error_kind kind
;
4696 operand_error_record
*curr
;
4697 operand_error_record
*head
= operand_error_report
.head
;
4698 operand_error_record
*record
= NULL
;
4700 /* No error to report. */
4704 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4706 /* Only one error. */
4707 if (head
== operand_error_report
.tail
)
4709 DEBUG_TRACE ("single opcode entry with error kind: %s",
4710 operand_mismatch_kind_names
[head
->detail
.kind
]);
4711 output_operand_error_record (head
, str
);
4715 /* Find the error kind of the highest severity. */
4716 DEBUG_TRACE ("multiple opcode entres with error kind");
4717 kind
= AARCH64_OPDE_NIL
;
4718 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4720 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4721 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4722 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4723 kind
= curr
->detail
.kind
;
4725 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4727 /* Pick up one of errors of KIND to report. */
4728 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4729 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4731 if (curr
->detail
.kind
!= kind
)
4733 /* If there are multiple errors, pick up the one with the highest
4734 mismatching operand index. In the case of multiple errors with
4735 the equally highest operand index, pick up the first one or the
4736 first one with non-NULL error message. */
4737 if (curr
->detail
.index
> largest_error_pos
4738 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4739 && curr
->detail
.error
!= NULL
))
4741 largest_error_pos
= curr
->detail
.index
;
4743 msg
= record
->detail
.error
;
4747 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4748 DEBUG_TRACE ("Pick up error kind %s to report",
4749 operand_mismatch_kind_names
[record
->detail
.kind
]);
4752 output_operand_error_record (record
, str
);
4755 /* Write an AARCH64 instruction to buf - always little-endian. */
4757 put_aarch64_insn (char *buf
, uint32_t insn
)
4759 unsigned char *where
= (unsigned char *) buf
;
4761 where
[1] = insn
>> 8;
4762 where
[2] = insn
>> 16;
4763 where
[3] = insn
>> 24;
4767 get_aarch64_insn (char *buf
)
4769 unsigned char *where
= (unsigned char *) buf
;
4771 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4776 output_inst (struct aarch64_inst
*new_inst
)
4780 to
= frag_more (INSN_SIZE
);
4782 frag_now
->tc_frag_data
.recorded
= 1;
4784 put_aarch64_insn (to
, inst
.base
.value
);
4786 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4788 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4789 INSN_SIZE
, &inst
.reloc
.exp
,
4792 DEBUG_TRACE ("Prepared relocation fix up");
4793 /* Don't check the addend value against the instruction size,
4794 that's the job of our code in md_apply_fix(). */
4795 fixp
->fx_no_overflow
= 1;
4796 if (new_inst
!= NULL
)
4797 fixp
->tc_fix_data
.inst
= new_inst
;
4798 if (aarch64_gas_internal_fixup_p ())
4800 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4801 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4802 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4806 dwarf2_emit_insn (INSN_SIZE
);
4809 /* Link together opcodes of the same name. */
4813 aarch64_opcode
*opcode
;
4814 struct templates
*next
;
4817 typedef struct templates templates
;
4820 lookup_mnemonic (const char *start
, int len
)
4822 templates
*templ
= NULL
;
4824 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4828 /* Subroutine of md_assemble, responsible for looking up the primary
4829 opcode from the mnemonic the user wrote. STR points to the
4830 beginning of the mnemonic. */
4833 opcode_lookup (char **str
)
4835 char *end
, *base
, *dot
;
4836 const aarch64_cond
*cond
;
4840 /* Scan up to the end of the mnemonic, which must end in white space,
4841 '.', or end of string. */
4843 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4844 if (*end
== '.' && !dot
)
4847 if (end
== base
|| dot
== base
)
4850 inst
.cond
= COND_ALWAYS
;
4852 /* Handle a possible condition. */
4855 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
4858 inst
.cond
= cond
->value
;
4874 if (inst
.cond
== COND_ALWAYS
)
4876 /* Look for unaffixed mnemonic. */
4877 return lookup_mnemonic (base
, len
);
4881 /* append ".c" to mnemonic if conditional */
4882 memcpy (condname
, base
, len
);
4883 memcpy (condname
+ len
, ".c", 2);
4886 return lookup_mnemonic (base
, len
);
4892 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4893 to a corresponding operand qualifier. */
4895 static inline aarch64_opnd_qualifier_t
4896 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4898 /* Element size in bytes indexed by vector_el_type. */
4899 const unsigned char ele_size
[5]
4901 const unsigned int ele_base
[5] =
4903 AARCH64_OPND_QLF_V_8B
,
4904 AARCH64_OPND_QLF_V_2H
,
4905 AARCH64_OPND_QLF_V_2S
,
4906 AARCH64_OPND_QLF_V_1D
,
4907 AARCH64_OPND_QLF_V_1Q
4910 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4911 goto vectype_conversion_fail
;
4913 if (vectype
->type
== NT_zero
)
4914 return AARCH64_OPND_QLF_P_Z
;
4915 if (vectype
->type
== NT_merge
)
4916 return AARCH64_OPND_QLF_P_M
;
4918 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4920 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4921 /* Vector element register. */
4922 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4925 /* Vector register. */
4926 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4929 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4930 goto vectype_conversion_fail
;
4932 /* The conversion is by calculating the offset from the base operand
4933 qualifier for the vector type. The operand qualifiers are regular
4934 enough that the offset can established by shifting the vector width by
4935 a vector-type dependent amount. */
4937 if (vectype
->type
== NT_b
)
4939 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4941 else if (vectype
->type
>= NT_d
)
4946 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4947 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4948 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4952 vectype_conversion_fail
:
4953 first_error (_("bad vector arrangement type"));
4954 return AARCH64_OPND_QLF_NIL
;
4957 /* Process an optional operand that is found omitted from the assembly line.
4958 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4959 instruction's opcode entry while IDX is the index of this omitted operand.
4963 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4964 int idx
, aarch64_opnd_info
*operand
)
4966 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4967 gas_assert (optional_operand_p (opcode
, idx
));
4968 gas_assert (!operand
->present
);
4972 case AARCH64_OPND_Rd
:
4973 case AARCH64_OPND_Rn
:
4974 case AARCH64_OPND_Rm
:
4975 case AARCH64_OPND_Rt
:
4976 case AARCH64_OPND_Rt2
:
4977 case AARCH64_OPND_Rs
:
4978 case AARCH64_OPND_Ra
:
4979 case AARCH64_OPND_Rt_SYS
:
4980 case AARCH64_OPND_Rd_SP
:
4981 case AARCH64_OPND_Rn_SP
:
4982 case AARCH64_OPND_Rm_SP
:
4983 case AARCH64_OPND_Fd
:
4984 case AARCH64_OPND_Fn
:
4985 case AARCH64_OPND_Fm
:
4986 case AARCH64_OPND_Fa
:
4987 case AARCH64_OPND_Ft
:
4988 case AARCH64_OPND_Ft2
:
4989 case AARCH64_OPND_Sd
:
4990 case AARCH64_OPND_Sn
:
4991 case AARCH64_OPND_Sm
:
4992 case AARCH64_OPND_Vd
:
4993 case AARCH64_OPND_Vn
:
4994 case AARCH64_OPND_Vm
:
4995 case AARCH64_OPND_VdD1
:
4996 case AARCH64_OPND_VnD1
:
4997 operand
->reg
.regno
= default_value
;
5000 case AARCH64_OPND_Ed
:
5001 case AARCH64_OPND_En
:
5002 case AARCH64_OPND_Em
:
5003 operand
->reglane
.regno
= default_value
;
5006 case AARCH64_OPND_IDX
:
5007 case AARCH64_OPND_BIT_NUM
:
5008 case AARCH64_OPND_IMMR
:
5009 case AARCH64_OPND_IMMS
:
5010 case AARCH64_OPND_SHLL_IMM
:
5011 case AARCH64_OPND_IMM_VLSL
:
5012 case AARCH64_OPND_IMM_VLSR
:
5013 case AARCH64_OPND_CCMP_IMM
:
5014 case AARCH64_OPND_FBITS
:
5015 case AARCH64_OPND_UIMM4
:
5016 case AARCH64_OPND_UIMM3_OP1
:
5017 case AARCH64_OPND_UIMM3_OP2
:
5018 case AARCH64_OPND_IMM
:
5019 case AARCH64_OPND_WIDTH
:
5020 case AARCH64_OPND_UIMM7
:
5021 case AARCH64_OPND_NZCV
:
5022 case AARCH64_OPND_SVE_PATTERN
:
5023 case AARCH64_OPND_SVE_PRFOP
:
5024 operand
->imm
.value
= default_value
;
5027 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5028 operand
->imm
.value
= default_value
;
5029 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5030 operand
->shifter
.amount
= 1;
5033 case AARCH64_OPND_EXCEPTION
:
5034 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5037 case AARCH64_OPND_BARRIER_ISB
:
5038 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5045 /* Process the relocation type for move wide instructions.
5046 Return TRUE on success; otherwise return FALSE. */
5049 process_movw_reloc_info (void)
5054 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5056 if (inst
.base
.opcode
->op
== OP_MOVK
)
5057 switch (inst
.reloc
.type
)
5059 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5060 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5061 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5062 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5063 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5064 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5065 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5067 (_("the specified relocation type is not allowed for MOVK"));
5073 switch (inst
.reloc
.type
)
5075 case BFD_RELOC_AARCH64_MOVW_G0
:
5076 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5077 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5078 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5079 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5080 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5081 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5082 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5083 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5084 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5085 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5088 case BFD_RELOC_AARCH64_MOVW_G1
:
5089 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5090 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5091 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5092 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5093 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5094 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5095 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5096 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5097 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5098 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5101 case BFD_RELOC_AARCH64_MOVW_G2
:
5102 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5103 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5104 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5105 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5108 set_fatal_syntax_error
5109 (_("the specified relocation type is not allowed for 32-bit "
5115 case BFD_RELOC_AARCH64_MOVW_G3
:
5118 set_fatal_syntax_error
5119 (_("the specified relocation type is not allowed for 32-bit "
5126 /* More cases should be added when more MOVW-related relocation types
5127 are supported in GAS. */
5128 gas_assert (aarch64_gas_internal_fixup_p ());
5129 /* The shift amount should have already been set by the parser. */
5132 inst
.base
.operands
[1].shifter
.amount
= shift
;
5136 /* A primitive log caculator. */
5138 static inline unsigned int
5139 get_logsz (unsigned int size
)
5141 const unsigned char ls
[16] =
5142 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5148 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5149 return ls
[size
- 1];
5152 /* Determine and return the real reloc type code for an instruction
5153 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5155 static inline bfd_reloc_code_real_type
5156 ldst_lo12_determine_real_reloc_type (void)
5159 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5160 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5162 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
5164 BFD_RELOC_AARCH64_LDST8_LO12
,
5165 BFD_RELOC_AARCH64_LDST16_LO12
,
5166 BFD_RELOC_AARCH64_LDST32_LO12
,
5167 BFD_RELOC_AARCH64_LDST64_LO12
,
5168 BFD_RELOC_AARCH64_LDST128_LO12
5171 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5172 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5173 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5174 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5175 BFD_RELOC_AARCH64_NONE
5178 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5179 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5180 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5181 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5182 BFD_RELOC_AARCH64_NONE
5186 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5187 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5189 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
5190 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5192 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5194 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5196 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5198 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5199 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5200 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5201 gas_assert (logsz
<= 3);
5203 gas_assert (logsz
<= 4);
5205 /* In reloc.c, these pseudo relocation types should be defined in similar
5206 order as above reloc_ldst_lo12 array. Because the array index calcuation
5207 below relies on this. */
5208 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5211 /* Check whether a register list REGINFO is valid. The registers must be
5212 numbered in increasing order (modulo 32), in increments of one or two.
5214 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5217 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5220 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5222 uint32_t i
, nb_regs
, prev_regno
, incr
;
5224 nb_regs
= 1 + (reginfo
& 0x3);
5226 prev_regno
= reginfo
& 0x1f;
5227 incr
= accept_alternate
? 2 : 1;
5229 for (i
= 1; i
< nb_regs
; ++i
)
5231 uint32_t curr_regno
;
5233 curr_regno
= reginfo
& 0x1f;
5234 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5236 prev_regno
= curr_regno
;
5242 /* Generic instruction operand parser. This does no encoding and no
5243 semantic validation; it merely squirrels values away in the inst
5244 structure. Returns TRUE or FALSE depending on whether the
5245 specified grammar matched. */
5248 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5251 char *backtrack_pos
= 0;
5252 const enum aarch64_opnd
*operands
= opcode
->operands
;
5253 aarch64_reg_type imm_reg_type
;
5256 skip_whitespace (str
);
5258 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5259 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_VZP
;
5261 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5263 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5266 const reg_entry
*reg
;
5267 int comma_skipped_p
= 0;
5268 aarch64_reg_type rtype
;
5269 struct vector_type_el vectype
;
5270 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5271 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5272 aarch64_reg_type reg_type
;
5274 DEBUG_TRACE ("parse operand %d", i
);
5276 /* Assign the operand code. */
5277 info
->type
= operands
[i
];
5279 if (optional_operand_p (opcode
, i
))
5281 /* Remember where we are in case we need to backtrack. */
5282 gas_assert (!backtrack_pos
);
5283 backtrack_pos
= str
;
5286 /* Expect comma between operands; the backtrack mechanizm will take
5287 care of cases of omitted optional operand. */
5288 if (i
> 0 && ! skip_past_char (&str
, ','))
5290 set_syntax_error (_("comma expected between operands"));
5294 comma_skipped_p
= 1;
5296 switch (operands
[i
])
5298 case AARCH64_OPND_Rd
:
5299 case AARCH64_OPND_Rn
:
5300 case AARCH64_OPND_Rm
:
5301 case AARCH64_OPND_Rt
:
5302 case AARCH64_OPND_Rt2
:
5303 case AARCH64_OPND_Rs
:
5304 case AARCH64_OPND_Ra
:
5305 case AARCH64_OPND_Rt_SYS
:
5306 case AARCH64_OPND_PAIRREG
:
5307 case AARCH64_OPND_SVE_Rm
:
5308 po_int_reg_or_fail (REG_TYPE_R_Z
);
5311 case AARCH64_OPND_Rd_SP
:
5312 case AARCH64_OPND_Rn_SP
:
5313 case AARCH64_OPND_SVE_Rn_SP
:
5314 case AARCH64_OPND_Rm_SP
:
5315 po_int_reg_or_fail (REG_TYPE_R_SP
);
5318 case AARCH64_OPND_Rm_EXT
:
5319 case AARCH64_OPND_Rm_SFT
:
5320 po_misc_or_fail (parse_shifter_operand
5321 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5323 : SHIFTED_LOGIC_IMM
)));
5324 if (!info
->shifter
.operator_present
)
5326 /* Default to LSL if not present. Libopcodes prefers shifter
5327 kind to be explicit. */
5328 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5329 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5330 /* For Rm_EXT, libopcodes will carry out further check on whether
5331 or not stack pointer is used in the instruction (Recall that
5332 "the extend operator is not optional unless at least one of
5333 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5337 case AARCH64_OPND_Fd
:
5338 case AARCH64_OPND_Fn
:
5339 case AARCH64_OPND_Fm
:
5340 case AARCH64_OPND_Fa
:
5341 case AARCH64_OPND_Ft
:
5342 case AARCH64_OPND_Ft2
:
5343 case AARCH64_OPND_Sd
:
5344 case AARCH64_OPND_Sn
:
5345 case AARCH64_OPND_Sm
:
5346 case AARCH64_OPND_SVE_VZn
:
5347 case AARCH64_OPND_SVE_Vd
:
5348 case AARCH64_OPND_SVE_Vm
:
5349 case AARCH64_OPND_SVE_Vn
:
5350 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5351 if (val
== PARSE_FAIL
)
5353 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5356 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5358 info
->reg
.regno
= val
;
5359 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5362 case AARCH64_OPND_SVE_Pd
:
5363 case AARCH64_OPND_SVE_Pg3
:
5364 case AARCH64_OPND_SVE_Pg4_5
:
5365 case AARCH64_OPND_SVE_Pg4_10
:
5366 case AARCH64_OPND_SVE_Pg4_16
:
5367 case AARCH64_OPND_SVE_Pm
:
5368 case AARCH64_OPND_SVE_Pn
:
5369 case AARCH64_OPND_SVE_Pt
:
5370 reg_type
= REG_TYPE_PN
;
5373 case AARCH64_OPND_SVE_Za_5
:
5374 case AARCH64_OPND_SVE_Za_16
:
5375 case AARCH64_OPND_SVE_Zd
:
5376 case AARCH64_OPND_SVE_Zm_5
:
5377 case AARCH64_OPND_SVE_Zm_16
:
5378 case AARCH64_OPND_SVE_Zn
:
5379 case AARCH64_OPND_SVE_Zt
:
5380 reg_type
= REG_TYPE_ZN
;
5383 case AARCH64_OPND_Vd
:
5384 case AARCH64_OPND_Vn
:
5385 case AARCH64_OPND_Vm
:
5386 reg_type
= REG_TYPE_VN
;
5388 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5389 if (val
== PARSE_FAIL
)
5391 first_error (_(get_reg_expected_msg (reg_type
)));
5394 if (vectype
.defined
& NTA_HASINDEX
)
5397 info
->reg
.regno
= val
;
5398 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5399 && vectype
.type
== NT_invtype
)
5400 /* Unqualified Pn and Zn registers are allowed in certain
5401 contexts. Rely on F_STRICT qualifier checking to catch
5403 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5406 info
->qualifier
= vectype_to_qualifier (&vectype
);
5407 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5412 case AARCH64_OPND_VdD1
:
5413 case AARCH64_OPND_VnD1
:
5414 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5415 if (val
== PARSE_FAIL
)
5417 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5420 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5422 set_fatal_syntax_error
5423 (_("the top half of a 128-bit FP/SIMD register is expected"));
5426 info
->reg
.regno
= val
;
5427 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5428 here; it is correct for the purpose of encoding/decoding since
5429 only the register number is explicitly encoded in the related
5430 instructions, although this appears a bit hacky. */
5431 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5434 case AARCH64_OPND_SVE_Zn_INDEX
:
5435 reg_type
= REG_TYPE_ZN
;
5436 goto vector_reg_index
;
5438 case AARCH64_OPND_Ed
:
5439 case AARCH64_OPND_En
:
5440 case AARCH64_OPND_Em
:
5441 reg_type
= REG_TYPE_VN
;
5443 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5444 if (val
== PARSE_FAIL
)
5446 first_error (_(get_reg_expected_msg (reg_type
)));
5449 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5452 info
->reglane
.regno
= val
;
5453 info
->reglane
.index
= vectype
.index
;
5454 info
->qualifier
= vectype_to_qualifier (&vectype
);
5455 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5459 case AARCH64_OPND_SVE_ZnxN
:
5460 case AARCH64_OPND_SVE_ZtxN
:
5461 reg_type
= REG_TYPE_ZN
;
5462 goto vector_reg_list
;
5464 case AARCH64_OPND_LVn
:
5465 case AARCH64_OPND_LVt
:
5466 case AARCH64_OPND_LVt_AL
:
5467 case AARCH64_OPND_LEt
:
5468 reg_type
= REG_TYPE_VN
;
5470 if (reg_type
== REG_TYPE_ZN
5471 && get_opcode_dependent_value (opcode
) == 1
5474 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5475 if (val
== PARSE_FAIL
)
5477 first_error (_(get_reg_expected_msg (reg_type
)));
5480 info
->reglist
.first_regno
= val
;
5481 info
->reglist
.num_regs
= 1;
5485 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5486 if (val
== PARSE_FAIL
)
5488 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5490 set_fatal_syntax_error (_("invalid register list"));
5493 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5494 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5496 if (operands
[i
] == AARCH64_OPND_LEt
)
5498 if (!(vectype
.defined
& NTA_HASINDEX
))
5500 info
->reglist
.has_index
= 1;
5501 info
->reglist
.index
= vectype
.index
;
5505 if (vectype
.defined
& NTA_HASINDEX
)
5507 if (!(vectype
.defined
& NTA_HASTYPE
))
5509 if (reg_type
== REG_TYPE_ZN
)
5510 set_fatal_syntax_error (_("missing type suffix"));
5514 info
->qualifier
= vectype_to_qualifier (&vectype
);
5515 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5519 case AARCH64_OPND_CRn
:
5520 case AARCH64_OPND_CRm
:
5522 char prefix
= *(str
++);
5523 if (prefix
!= 'c' && prefix
!= 'C')
5526 po_imm_nc_or_fail ();
5529 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5532 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5533 info
->imm
.value
= val
;
5537 case AARCH64_OPND_SHLL_IMM
:
5538 case AARCH64_OPND_IMM_VLSR
:
5539 po_imm_or_fail (1, 64);
5540 info
->imm
.value
= val
;
5543 case AARCH64_OPND_CCMP_IMM
:
5544 case AARCH64_OPND_SIMM5
:
5545 case AARCH64_OPND_FBITS
:
5546 case AARCH64_OPND_UIMM4
:
5547 case AARCH64_OPND_UIMM3_OP1
:
5548 case AARCH64_OPND_UIMM3_OP2
:
5549 case AARCH64_OPND_IMM_VLSL
:
5550 case AARCH64_OPND_IMM
:
5551 case AARCH64_OPND_WIDTH
:
5552 case AARCH64_OPND_SVE_INV_LIMM
:
5553 case AARCH64_OPND_SVE_LIMM
:
5554 case AARCH64_OPND_SVE_LIMM_MOV
:
5555 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5556 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5557 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5558 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5559 case AARCH64_OPND_SVE_SIMM5
:
5560 case AARCH64_OPND_SVE_SIMM5B
:
5561 case AARCH64_OPND_SVE_SIMM6
:
5562 case AARCH64_OPND_SVE_SIMM8
:
5563 case AARCH64_OPND_SVE_UIMM3
:
5564 case AARCH64_OPND_SVE_UIMM7
:
5565 case AARCH64_OPND_SVE_UIMM8
:
5566 case AARCH64_OPND_SVE_UIMM8_53
:
5567 case AARCH64_OPND_IMM_ROT1
:
5568 case AARCH64_OPND_IMM_ROT2
:
5569 case AARCH64_OPND_IMM_ROT3
:
5570 po_imm_nc_or_fail ();
5571 info
->imm
.value
= val
;
5574 case AARCH64_OPND_SVE_AIMM
:
5575 case AARCH64_OPND_SVE_ASIMM
:
5576 po_imm_nc_or_fail ();
5577 info
->imm
.value
= val
;
5578 skip_whitespace (str
);
5579 if (skip_past_comma (&str
))
5580 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5582 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5585 case AARCH64_OPND_SVE_PATTERN
:
5586 po_enum_or_fail (aarch64_sve_pattern_array
);
5587 info
->imm
.value
= val
;
5590 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5591 po_enum_or_fail (aarch64_sve_pattern_array
);
5592 info
->imm
.value
= val
;
5593 if (skip_past_comma (&str
)
5594 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5596 if (!info
->shifter
.operator_present
)
5598 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5599 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5600 info
->shifter
.amount
= 1;
5604 case AARCH64_OPND_SVE_PRFOP
:
5605 po_enum_or_fail (aarch64_sve_prfop_array
);
5606 info
->imm
.value
= val
;
5609 case AARCH64_OPND_UIMM7
:
5610 po_imm_or_fail (0, 127);
5611 info
->imm
.value
= val
;
5614 case AARCH64_OPND_IDX
:
5615 case AARCH64_OPND_BIT_NUM
:
5616 case AARCH64_OPND_IMMR
:
5617 case AARCH64_OPND_IMMS
:
5618 po_imm_or_fail (0, 63);
5619 info
->imm
.value
= val
;
5622 case AARCH64_OPND_IMM0
:
5623 po_imm_nc_or_fail ();
5626 set_fatal_syntax_error (_("immediate zero expected"));
5629 info
->imm
.value
= 0;
5632 case AARCH64_OPND_FPIMM0
:
5635 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5636 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5637 it is probably not worth the effort to support it. */
5638 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5641 || !(res2
= parse_constant_immediate (&str
, &val
,
5644 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5646 info
->imm
.value
= 0;
5647 info
->imm
.is_fp
= 1;
5650 set_fatal_syntax_error (_("immediate zero expected"));
5654 case AARCH64_OPND_IMM_MOV
:
5657 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5658 reg_name_p (str
, REG_TYPE_VN
))
5661 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5663 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5664 later. fix_mov_imm_insn will try to determine a machine
5665 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5666 message if the immediate cannot be moved by a single
5668 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5669 inst
.base
.operands
[i
].skip
= 1;
5673 case AARCH64_OPND_SIMD_IMM
:
5674 case AARCH64_OPND_SIMD_IMM_SFT
:
5675 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5677 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5679 /* need_libopcodes_p */ 1,
5682 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5683 shift, we don't check it here; we leave the checking to
5684 the libopcodes (operand_general_constraint_met_p). By
5685 doing this, we achieve better diagnostics. */
5686 if (skip_past_comma (&str
)
5687 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5689 if (!info
->shifter
.operator_present
5690 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5692 /* Default to LSL if not present. Libopcodes prefers shifter
5693 kind to be explicit. */
5694 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5695 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5699 case AARCH64_OPND_FPIMM
:
5700 case AARCH64_OPND_SIMD_FPIMM
:
5701 case AARCH64_OPND_SVE_FPIMM8
:
5706 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5707 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5708 || !aarch64_imm_float_p (qfloat
))
5711 set_fatal_syntax_error (_("invalid floating-point"
5715 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5716 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5720 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5721 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5722 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5727 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5728 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5731 set_fatal_syntax_error (_("invalid floating-point"
5735 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5736 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5740 case AARCH64_OPND_LIMM
:
5741 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5742 SHIFTED_LOGIC_IMM
));
5743 if (info
->shifter
.operator_present
)
5745 set_fatal_syntax_error
5746 (_("shift not allowed for bitmask immediate"));
5749 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5751 /* need_libopcodes_p */ 1,
5755 case AARCH64_OPND_AIMM
:
5756 if (opcode
->op
== OP_ADD
)
5757 /* ADD may have relocation types. */
5758 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5759 SHIFTED_ARITH_IMM
));
5761 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5762 SHIFTED_ARITH_IMM
));
5763 switch (inst
.reloc
.type
)
5765 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5766 info
->shifter
.amount
= 12;
5768 case BFD_RELOC_UNUSED
:
5769 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5770 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5771 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5772 inst
.reloc
.pc_rel
= 0;
5777 info
->imm
.value
= 0;
5778 if (!info
->shifter
.operator_present
)
5780 /* Default to LSL if not present. Libopcodes prefers shifter
5781 kind to be explicit. */
5782 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5783 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5787 case AARCH64_OPND_HALF
:
5789 /* #<imm16> or relocation. */
5790 int internal_fixup_p
;
5791 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5792 if (internal_fixup_p
)
5793 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5794 skip_whitespace (str
);
5795 if (skip_past_comma (&str
))
5797 /* {, LSL #<shift>} */
5798 if (! aarch64_gas_internal_fixup_p ())
5800 set_fatal_syntax_error (_("can't mix relocation modifier "
5801 "with explicit shift"));
5804 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5807 inst
.base
.operands
[i
].shifter
.amount
= 0;
5808 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5809 inst
.base
.operands
[i
].imm
.value
= 0;
5810 if (! process_movw_reloc_info ())
5815 case AARCH64_OPND_EXCEPTION
:
5816 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5818 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5820 /* need_libopcodes_p */ 0,
5824 case AARCH64_OPND_NZCV
:
5826 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5830 info
->imm
.value
= nzcv
->value
;
5833 po_imm_or_fail (0, 15);
5834 info
->imm
.value
= val
;
5838 case AARCH64_OPND_COND
:
5839 case AARCH64_OPND_COND1
:
5844 while (ISALPHA (*str
));
5845 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
5846 if (info
->cond
== NULL
)
5848 set_syntax_error (_("invalid condition"));
5851 else if (operands
[i
] == AARCH64_OPND_COND1
5852 && (info
->cond
->value
& 0xe) == 0xe)
5854 /* Do not allow AL or NV. */
5855 set_default_error ();
5861 case AARCH64_OPND_ADDR_ADRP
:
5862 po_misc_or_fail (parse_adrp (&str
));
5863 /* Clear the value as operand needs to be relocated. */
5864 info
->imm
.value
= 0;
5867 case AARCH64_OPND_ADDR_PCREL14
:
5868 case AARCH64_OPND_ADDR_PCREL19
:
5869 case AARCH64_OPND_ADDR_PCREL21
:
5870 case AARCH64_OPND_ADDR_PCREL26
:
5871 po_misc_or_fail (parse_address (&str
, info
));
5872 if (!info
->addr
.pcrel
)
5874 set_syntax_error (_("invalid pc-relative address"));
5877 if (inst
.gen_lit_pool
5878 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5880 /* Only permit "=value" in the literal load instructions.
5881 The literal will be generated by programmer_friendly_fixup. */
5882 set_syntax_error (_("invalid use of \"=immediate\""));
5885 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5887 set_syntax_error (_("unrecognized relocation suffix"));
5890 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5892 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5893 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5897 info
->imm
.value
= 0;
5898 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5899 switch (opcode
->iclass
)
5903 /* e.g. CBZ or B.COND */
5904 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5905 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5909 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5910 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5914 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5916 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5917 : BFD_RELOC_AARCH64_JUMP26
;
5920 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5921 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5924 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5925 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5931 inst
.reloc
.pc_rel
= 1;
5935 case AARCH64_OPND_ADDR_SIMPLE
:
5936 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5938 /* [<Xn|SP>{, #<simm>}] */
5940 /* First use the normal address-parsing routines, to get
5941 the usual syntax errors. */
5942 po_misc_or_fail (parse_address (&str
, info
));
5943 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5944 || !info
->addr
.preind
|| info
->addr
.postind
5945 || info
->addr
.writeback
)
5947 set_syntax_error (_("invalid addressing mode"));
5951 /* Then retry, matching the specific syntax of these addresses. */
5953 po_char_or_fail ('[');
5954 po_reg_or_fail (REG_TYPE_R64_SP
);
5955 /* Accept optional ", #0". */
5956 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5957 && skip_past_char (&str
, ','))
5959 skip_past_char (&str
, '#');
5960 if (! skip_past_char (&str
, '0'))
5962 set_fatal_syntax_error
5963 (_("the optional immediate offset can only be 0"));
5967 po_char_or_fail (']');
5971 case AARCH64_OPND_ADDR_REGOFF
:
5972 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5973 po_misc_or_fail (parse_address (&str
, info
));
5975 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5976 || !info
->addr
.preind
|| info
->addr
.postind
5977 || info
->addr
.writeback
)
5979 set_syntax_error (_("invalid addressing mode"));
5982 if (!info
->shifter
.operator_present
)
5984 /* Default to LSL if not present. Libopcodes prefers shifter
5985 kind to be explicit. */
5986 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5987 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5989 /* Qualifier to be deduced by libopcodes. */
5992 case AARCH64_OPND_ADDR_SIMM7
:
5993 po_misc_or_fail (parse_address (&str
, info
));
5994 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5995 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5997 set_syntax_error (_("invalid addressing mode"));
6000 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6002 set_syntax_error (_("relocation not allowed"));
6005 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6007 /* need_libopcodes_p */ 1,
6011 case AARCH64_OPND_ADDR_SIMM9
:
6012 case AARCH64_OPND_ADDR_SIMM9_2
:
6013 po_misc_or_fail (parse_address (&str
, info
));
6014 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6015 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6016 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6017 && info
->addr
.writeback
))
6019 set_syntax_error (_("invalid addressing mode"));
6022 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6024 set_syntax_error (_("relocation not allowed"));
6027 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6029 /* need_libopcodes_p */ 1,
6033 case AARCH64_OPND_ADDR_SIMM10
:
6034 po_misc_or_fail (parse_address (&str
, info
));
6035 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6036 || !info
->addr
.preind
|| info
->addr
.postind
)
6038 set_syntax_error (_("invalid addressing mode"));
6041 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6043 set_syntax_error (_("relocation not allowed"));
6046 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6048 /* need_libopcodes_p */ 1,
6052 case AARCH64_OPND_ADDR_UIMM12
:
6053 po_misc_or_fail (parse_address (&str
, info
));
6054 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6055 || !info
->addr
.preind
|| info
->addr
.writeback
)
6057 set_syntax_error (_("invalid addressing mode"));
6060 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6061 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6062 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6064 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6066 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
6067 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6068 /* Leave qualifier to be determined by libopcodes. */
6071 case AARCH64_OPND_SIMD_ADDR_POST
:
6072 /* [<Xn|SP>], <Xm|#<amount>> */
6073 po_misc_or_fail (parse_address (&str
, info
));
6074 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6076 set_syntax_error (_("invalid addressing mode"));
6079 if (!info
->addr
.offset
.is_reg
)
6081 if (inst
.reloc
.exp
.X_op
== O_constant
)
6082 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6085 set_fatal_syntax_error
6086 (_("writeback value must be an immediate constant"));
6093 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6094 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6095 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6096 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6097 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6098 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6099 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6100 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6101 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6102 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6103 /* [X<n>{, #imm, MUL VL}]
6105 but recognizing SVE registers. */
6106 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6107 &offset_qualifier
));
6108 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6110 set_syntax_error (_("invalid addressing mode"));
6114 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6115 || !info
->addr
.preind
|| info
->addr
.writeback
)
6117 set_syntax_error (_("invalid addressing mode"));
6120 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6121 || inst
.reloc
.exp
.X_op
!= O_constant
)
6123 /* Make sure this has priority over
6124 "invalid addressing mode". */
6125 set_fatal_syntax_error (_("constant offset required"));
6128 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6131 case AARCH64_OPND_SVE_ADDR_RR
:
6132 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6133 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6134 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6135 case AARCH64_OPND_SVE_ADDR_RX
:
6136 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6137 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6138 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6139 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6140 but recognizing SVE registers. */
6141 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6142 &offset_qualifier
));
6143 if (base_qualifier
!= AARCH64_OPND_QLF_X
6144 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6146 set_syntax_error (_("invalid addressing mode"));
6151 case AARCH64_OPND_SVE_ADDR_RZ
:
6152 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6153 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6154 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6155 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6156 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6157 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6158 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6159 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6160 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6161 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6162 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6163 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6164 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6165 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6166 &offset_qualifier
));
6167 if (base_qualifier
!= AARCH64_OPND_QLF_X
6168 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6169 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6171 set_syntax_error (_("invalid addressing mode"));
6174 info
->qualifier
= offset_qualifier
;
6177 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6178 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6179 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6180 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6181 /* [Z<n>.<T>{, #imm}] */
6182 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6183 &offset_qualifier
));
6184 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6185 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6187 set_syntax_error (_("invalid addressing mode"));
6190 info
->qualifier
= base_qualifier
;
6193 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6194 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6195 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6196 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6197 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6201 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6203 here since we get better error messages by leaving it to
6204 the qualifier checking routines. */
6205 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6206 &offset_qualifier
));
6207 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6208 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6209 || offset_qualifier
!= base_qualifier
)
6211 set_syntax_error (_("invalid addressing mode"));
6214 info
->qualifier
= base_qualifier
;
6217 case AARCH64_OPND_SYSREG
:
6218 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
6221 set_syntax_error (_("unknown or missing system register name"));
6224 inst
.base
.operands
[i
].sysreg
= val
;
6227 case AARCH64_OPND_PSTATEFIELD
:
6228 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
6231 set_syntax_error (_("unknown or missing PSTATE field name"));
6234 inst
.base
.operands
[i
].pstatefield
= val
;
6237 case AARCH64_OPND_SYSREG_IC
:
6238 inst
.base
.operands
[i
].sysins_op
=
6239 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6241 case AARCH64_OPND_SYSREG_DC
:
6242 inst
.base
.operands
[i
].sysins_op
=
6243 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6245 case AARCH64_OPND_SYSREG_AT
:
6246 inst
.base
.operands
[i
].sysins_op
=
6247 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6249 case AARCH64_OPND_SYSREG_TLBI
:
6250 inst
.base
.operands
[i
].sysins_op
=
6251 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6253 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6255 set_fatal_syntax_error ( _("unknown or missing operation name"));
6260 case AARCH64_OPND_BARRIER
:
6261 case AARCH64_OPND_BARRIER_ISB
:
6262 val
= parse_barrier (&str
);
6263 if (val
!= PARSE_FAIL
6264 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6266 /* ISB only accepts options name 'sy'. */
6268 (_("the specified option is not accepted in ISB"));
6269 /* Turn off backtrack as this optional operand is present. */
6273 /* This is an extension to accept a 0..15 immediate. */
6274 if (val
== PARSE_FAIL
)
6275 po_imm_or_fail (0, 15);
6276 info
->barrier
= aarch64_barrier_options
+ val
;
6279 case AARCH64_OPND_PRFOP
:
6280 val
= parse_pldop (&str
);
6281 /* This is an extension to accept a 0..31 immediate. */
6282 if (val
== PARSE_FAIL
)
6283 po_imm_or_fail (0, 31);
6284 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6287 case AARCH64_OPND_BARRIER_PSB
:
6288 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6289 if (val
== PARSE_FAIL
)
6294 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6297 /* If we get here, this operand was successfully parsed. */
6298 inst
.base
.operands
[i
].present
= 1;
6302 /* The parse routine should already have set the error, but in case
6303 not, set a default one here. */
6305 set_default_error ();
6307 if (! backtrack_pos
)
6308 goto parse_operands_return
;
6311 /* We reach here because this operand is marked as optional, and
6312 either no operand was supplied or the operand was supplied but it
6313 was syntactically incorrect. In the latter case we report an
6314 error. In the former case we perform a few more checks before
6315 dropping through to the code to insert the default operand. */
6317 char *tmp
= backtrack_pos
;
6318 char endchar
= END_OF_INSN
;
6320 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6322 skip_past_char (&tmp
, ',');
6324 if (*tmp
!= endchar
)
6325 /* The user has supplied an operand in the wrong format. */
6326 goto parse_operands_return
;
6328 /* Make sure there is not a comma before the optional operand.
6329 For example the fifth operand of 'sys' is optional:
6331 sys #0,c0,c0,#0, <--- wrong
6332 sys #0,c0,c0,#0 <--- correct. */
6333 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6335 set_fatal_syntax_error
6336 (_("unexpected comma before the omitted optional operand"));
6337 goto parse_operands_return
;
6341 /* Reaching here means we are dealing with an optional operand that is
6342 omitted from the assembly line. */
6343 gas_assert (optional_operand_p (opcode
, i
));
6345 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6347 /* Try again, skipping the optional operand at backtrack_pos. */
6348 str
= backtrack_pos
;
6351 /* Clear any error record after the omitted optional operand has been
6352 successfully handled. */
6356 /* Check if we have parsed all the operands. */
6357 if (*str
!= '\0' && ! error_p ())
6359 /* Set I to the index of the last present operand; this is
6360 for the purpose of diagnostics. */
6361 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6363 set_fatal_syntax_error
6364 (_("unexpected characters following instruction"));
6367 parse_operands_return
:
6371 DEBUG_TRACE ("parsing FAIL: %s - %s",
6372 operand_mismatch_kind_names
[get_error_kind ()],
6373 get_error_message ());
6374 /* Record the operand error properly; this is useful when there
6375 are multiple instruction templates for a mnemonic name, so that
6376 later on, we can select the error that most closely describes
6378 record_operand_error (opcode
, i
, get_error_kind (),
6379 get_error_message ());
6384 DEBUG_TRACE ("parsing SUCCESS");
6389 /* It does some fix-up to provide some programmer friendly feature while
6390 keeping the libopcodes happy, i.e. libopcodes only accepts
6391 the preferred architectural syntax.
6392 Return FALSE if there is any failure; otherwise return TRUE. */
6395 programmer_friendly_fixup (aarch64_instruction
*instr
)
6397 aarch64_inst
*base
= &instr
->base
;
6398 const aarch64_opcode
*opcode
= base
->opcode
;
6399 enum aarch64_op op
= opcode
->op
;
6400 aarch64_opnd_info
*operands
= base
->operands
;
6402 DEBUG_TRACE ("enter");
6404 switch (opcode
->iclass
)
6407 /* TBNZ Xn|Wn, #uimm6, label
6408 Test and Branch Not Zero: conditionally jumps to label if bit number
6409 uimm6 in register Xn is not zero. The bit number implies the width of
6410 the register, which may be written and should be disassembled as Wn if
6411 uimm is less than 32. */
6412 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6414 if (operands
[1].imm
.value
>= 32)
6416 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6420 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6424 /* LDR Wt, label | =value
6425 As a convenience assemblers will typically permit the notation
6426 "=value" in conjunction with the pc-relative literal load instructions
6427 to automatically place an immediate value or symbolic address in a
6428 nearby literal pool and generate a hidden label which references it.
6429 ISREG has been set to 0 in the case of =value. */
6430 if (instr
->gen_lit_pool
6431 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6433 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6434 if (op
== OP_LDRSW_LIT
)
6436 if (instr
->reloc
.exp
.X_op
!= O_constant
6437 && instr
->reloc
.exp
.X_op
!= O_big
6438 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6440 record_operand_error (opcode
, 1,
6441 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6442 _("constant expression expected"));
6445 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6447 record_operand_error (opcode
, 1,
6448 AARCH64_OPDE_OTHER_ERROR
,
6449 _("literal pool insertion failed"));
6457 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6458 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6459 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6460 A programmer-friendly assembler should accept a destination Xd in
6461 place of Wd, however that is not the preferred form for disassembly.
6463 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6464 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6465 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6466 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6471 /* In the 64-bit form, the final register operand is written as Wm
6472 for all but the (possibly omitted) UXTX/LSL and SXTX
6474 As a programmer-friendly assembler, we accept e.g.
6475 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6476 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6477 int idx
= aarch64_operand_index (opcode
->operands
,
6478 AARCH64_OPND_Rm_EXT
);
6479 gas_assert (idx
== 1 || idx
== 2);
6480 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6481 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6482 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6483 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6484 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6485 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6493 DEBUG_TRACE ("exit with SUCCESS");
6497 /* Check for loads and stores that will cause unpredictable behavior. */
6500 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6502 aarch64_inst
*base
= &instr
->base
;
6503 const aarch64_opcode
*opcode
= base
->opcode
;
6504 const aarch64_opnd_info
*opnds
= base
->operands
;
6505 switch (opcode
->iclass
)
6512 /* Loading/storing the base register is unpredictable if writeback. */
6513 if ((aarch64_get_operand_class (opnds
[0].type
)
6514 == AARCH64_OPND_CLASS_INT_REG
)
6515 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6516 && opnds
[1].addr
.base_regno
!= REG_SP
6517 && opnds
[1].addr
.writeback
)
6518 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6521 case ldstnapair_offs
:
6522 case ldstpair_indexed
:
6523 /* Loading/storing the base register is unpredictable if writeback. */
6524 if ((aarch64_get_operand_class (opnds
[0].type
)
6525 == AARCH64_OPND_CLASS_INT_REG
)
6526 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6527 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6528 && opnds
[2].addr
.base_regno
!= REG_SP
6529 && opnds
[2].addr
.writeback
)
6530 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6531 /* Load operations must load different registers. */
6532 if ((opcode
->opcode
& (1 << 22))
6533 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6534 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6541 /* A wrapper function to interface with libopcodes on encoding and
6542 record the error message if there is any.
6544 Return TRUE on success; otherwise return FALSE. */
6547 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6550 aarch64_operand_error error_info
;
6551 error_info
.kind
= AARCH64_OPDE_NIL
;
6552 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6556 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6557 record_operand_error_info (opcode
, &error_info
);
6562 #ifdef DEBUG_AARCH64
6564 dump_opcode_operands (const aarch64_opcode
*opcode
)
6567 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6569 aarch64_verbose ("\t\t opnd%d: %s", i
,
6570 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6571 ? aarch64_get_operand_name (opcode
->operands
[i
])
6572 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6576 #endif /* DEBUG_AARCH64 */
6578 /* This is the guts of the machine-dependent assembler. STR points to a
6579 machine dependent instruction. This function is supposed to emit
6580 the frags/bytes it assembles to. */
6583 md_assemble (char *str
)
6586 templates
*template;
6587 aarch64_opcode
*opcode
;
6588 aarch64_inst
*inst_base
;
6589 unsigned saved_cond
;
6591 /* Align the previous label if needed. */
6592 if (last_label_seen
!= NULL
)
6594 symbol_set_frag (last_label_seen
, frag_now
);
6595 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6596 S_SET_SEGMENT (last_label_seen
, now_seg
);
6599 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6601 DEBUG_TRACE ("\n\n");
6602 DEBUG_TRACE ("==============================");
6603 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6605 template = opcode_lookup (&p
);
6608 /* It wasn't an instruction, but it might be a register alias of
6609 the form alias .req reg directive. */
6610 if (!create_register_alias (str
, p
))
6611 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6616 skip_whitespace (p
);
6619 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6620 get_mnemonic_name (str
), str
);
6624 init_operand_error_report ();
6626 /* Sections are assumed to start aligned. In executable section, there is no
6627 MAP_DATA symbol pending. So we only align the address during
6628 MAP_DATA --> MAP_INSN transition.
6629 For other sections, this is not guaranteed. */
6630 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6631 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6632 frag_align_code (2, 0);
6634 saved_cond
= inst
.cond
;
6635 reset_aarch64_instruction (&inst
);
6636 inst
.cond
= saved_cond
;
6638 /* Iterate through all opcode entries with the same mnemonic name. */
6641 opcode
= template->opcode
;
6643 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6644 #ifdef DEBUG_AARCH64
6646 dump_opcode_operands (opcode
);
6647 #endif /* DEBUG_AARCH64 */
6649 mapping_state (MAP_INSN
);
6651 inst_base
= &inst
.base
;
6652 inst_base
->opcode
= opcode
;
6654 /* Truly conditionally executed instructions, e.g. b.cond. */
6655 if (opcode
->flags
& F_COND
)
6657 gas_assert (inst
.cond
!= COND_ALWAYS
);
6658 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6659 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6661 else if (inst
.cond
!= COND_ALWAYS
)
6663 /* It shouldn't arrive here, where the assembly looks like a
6664 conditional instruction but the found opcode is unconditional. */
6669 if (parse_operands (p
, opcode
)
6670 && programmer_friendly_fixup (&inst
)
6671 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6673 /* Check that this instruction is supported for this CPU. */
6674 if (!opcode
->avariant
6675 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6677 as_bad (_("selected processor does not support `%s'"), str
);
6681 warn_unpredictable_ldst (&inst
, str
);
6683 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6684 || !inst
.reloc
.need_libopcodes_p
)
6688 /* If there is relocation generated for the instruction,
6689 store the instruction information for the future fix-up. */
6690 struct aarch64_inst
*copy
;
6691 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6692 copy
= XNEW (struct aarch64_inst
);
6693 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6699 template = template->next
;
6700 if (template != NULL
)
6702 reset_aarch64_instruction (&inst
);
6703 inst
.cond
= saved_cond
;
6706 while (template != NULL
);
6708 /* Issue the error messages if any. */
6709 output_operand_error_report (str
);
6712 /* Various frobbings of labels and their addresses. */
6715 aarch64_start_line_hook (void)
6717 last_label_seen
= NULL
;
6721 aarch64_frob_label (symbolS
* sym
)
6723 last_label_seen
= sym
;
6725 dwarf2_emit_label (sym
);
6729 aarch64_data_in_code (void)
6731 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6733 *input_line_pointer
= '/';
6734 input_line_pointer
+= 5;
6735 *input_line_pointer
= 0;
6743 aarch64_canonicalize_symbol_name (char *name
)
6747 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6748 *(name
+ len
- 5) = 0;
6753 /* Table of all register names defined by default. The user can
6754 define additional names with .req. Note that all register names
6755 should appear in both upper and lowercase variants. Some registers
6756 also have mixed-case names. */
6758 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6759 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6760 #define REGSET16(p,t) \
6761 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6762 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6763 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6764 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6765 #define REGSET31(p,t) \
6767 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6768 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6769 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6770 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6771 #define REGSET(p,t) \
6772 REGSET31(p,t), REGNUM(p,31,t)
6774 /* These go into aarch64_reg_hsh hash-table. */
6775 static const reg_entry reg_names
[] = {
6776 /* Integer registers. */
6777 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6778 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6780 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6781 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6783 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6784 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6786 /* Floating-point single precision registers. */
6787 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6789 /* Floating-point double precision registers. */
6790 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6792 /* Floating-point half precision registers. */
6793 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6795 /* Floating-point byte precision registers. */
6796 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6798 /* Floating-point quad precision registers. */
6799 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6801 /* FP/SIMD registers. */
6802 REGSET (v
, VN
), REGSET (V
, VN
),
6804 /* SVE vector registers. */
6805 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6807 /* SVE predicate registers. */
6808 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6825 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6826 static const asm_nzcv nzcv_names
[] = {
6827 {"nzcv", B (n
, z
, c
, v
)},
6828 {"nzcV", B (n
, z
, c
, V
)},
6829 {"nzCv", B (n
, z
, C
, v
)},
6830 {"nzCV", B (n
, z
, C
, V
)},
6831 {"nZcv", B (n
, Z
, c
, v
)},
6832 {"nZcV", B (n
, Z
, c
, V
)},
6833 {"nZCv", B (n
, Z
, C
, v
)},
6834 {"nZCV", B (n
, Z
, C
, V
)},
6835 {"Nzcv", B (N
, z
, c
, v
)},
6836 {"NzcV", B (N
, z
, c
, V
)},
6837 {"NzCv", B (N
, z
, C
, v
)},
6838 {"NzCV", B (N
, z
, C
, V
)},
6839 {"NZcv", B (N
, Z
, c
, v
)},
6840 {"NZcV", B (N
, Z
, c
, V
)},
6841 {"NZCv", B (N
, Z
, C
, v
)},
6842 {"NZCV", B (N
, Z
, C
, V
)}
6855 /* MD interface: bits in the object file. */
6857 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6858 for use in the a.out file, and stores them in the array pointed to by buf.
6859 This knows about the endian-ness of the target machine and does
6860 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6861 2 (short) and 4 (long) Floating numbers are put out as a series of
6862 LITTLENUMS (shorts, here at least). */
6865 md_number_to_chars (char *buf
, valueT val
, int n
)
6867 if (target_big_endian
)
6868 number_to_chars_bigendian (buf
, val
, n
);
6870 number_to_chars_littleendian (buf
, val
, n
);
6873 /* MD interface: Sections. */
6875 /* Estimate the size of a frag before relaxing. Assume everything fits in
6879 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6885 /* Round up a section size to the appropriate boundary. */
6888 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6893 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6894 of an rs_align_code fragment.
6896 Here we fill the frag with the appropriate info for padding the
6897 output stream. The resulting frag will consist of a fixed (fr_fix)
6898 and of a repeating (fr_var) part.
6900 The fixed content is always emitted before the repeating content and
6901 these two parts are used as follows in constructing the output:
6902 - the fixed part will be used to align to a valid instruction word
6903 boundary, in case that we start at a misaligned address; as no
6904 executable instruction can live at the misaligned location, we
6905 simply fill with zeros;
6906 - the variable part will be used to cover the remaining padding and
6907 we fill using the AArch64 NOP instruction.
6909 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6910 enough storage space for up to 3 bytes for padding the back to a valid
6911 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6914 aarch64_handle_align (fragS
* fragP
)
6916 /* NOP = d503201f */
6917 /* AArch64 instructions are always little-endian. */
6918 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6920 int bytes
, fix
, noop_size
;
6923 if (fragP
->fr_type
!= rs_align_code
)
6926 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6927 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6930 gas_assert (fragP
->tc_frag_data
.recorded
);
6933 noop_size
= sizeof (aarch64_noop
);
6935 fix
= bytes
& (noop_size
- 1);
6939 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6943 fragP
->fr_fix
+= fix
;
6947 memcpy (p
, aarch64_noop
, noop_size
);
6948 fragP
->fr_var
= noop_size
;
6951 /* Perform target specific initialisation of a frag.
6952 Note - despite the name this initialisation is not done when the frag
6953 is created, but only when its type is assigned. A frag can be created
6954 and used a long time before its type is set, so beware of assuming that
6955 this initialisationis performed first. */
6959 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6960 int max_chars ATTRIBUTE_UNUSED
)
6964 #else /* OBJ_ELF is defined. */
6966 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6968 /* Record a mapping symbol for alignment frags. We will delete this
6969 later if the alignment ends up empty. */
6970 if (!fragP
->tc_frag_data
.recorded
)
6971 fragP
->tc_frag_data
.recorded
= 1;
6973 switch (fragP
->fr_type
)
6977 mapping_state_2 (MAP_DATA
, max_chars
);
6980 /* PR 20364: We can get alignment frags in code sections,
6981 so do not just assume that we should use the MAP_DATA state. */
6982 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
6985 mapping_state_2 (MAP_INSN
, max_chars
);
6992 /* Initialize the DWARF-2 unwind information for this procedure. */
6995 tc_aarch64_frame_initial_instructions (void)
6997 cfi_add_CFA_def_cfa (REG_SP
, 0);
6999 #endif /* OBJ_ELF */
7001 /* Convert REGNAME to a DWARF-2 register number. */
7004 tc_aarch64_regname_to_dw2regnum (char *regname
)
7006 const reg_entry
*reg
= parse_reg (®name
);
7012 case REG_TYPE_SP_32
:
7013 case REG_TYPE_SP_64
:
7023 return reg
->number
+ 64;
7031 /* Implement DWARF2_ADDR_SIZE. */
7034 aarch64_dwarf2_addr_size (void)
7036 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7040 return bfd_arch_bits_per_address (stdoutput
) / 8;
7043 /* MD interface: Symbol and relocation handling. */
7045 /* Return the address within the segment that a PC-relative fixup is
7046 relative to. For AArch64 PC-relative fixups applied to instructions
7047 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7050 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7052 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7054 /* If this is pc-relative and we are going to emit a relocation
7055 then we just want to put out any pipeline compensation that the linker
7056 will need. Otherwise we want to use the calculated base. */
7058 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7059 || aarch64_force_relocation (fixP
)))
7062 /* AArch64 should be consistent for all pc-relative relocations. */
7063 return base
+ AARCH64_PCREL_OFFSET
;
7066 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7067 Otherwise we have no need to default values of symbols. */
7070 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7073 if (name
[0] == '_' && name
[1] == 'G'
7074 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7078 if (symbol_find (name
))
7079 as_bad (_("GOT already in the symbol table"));
7081 GOT_symbol
= symbol_new (name
, undefined_section
,
7082 (valueT
) 0, &zero_address_frag
);
7092 /* Return non-zero if the indicated VALUE has overflowed the maximum
7093 range expressible by a unsigned number with the indicated number of
7097 unsigned_overflow (valueT value
, unsigned bits
)
7100 if (bits
>= sizeof (valueT
) * 8)
7102 lim
= (valueT
) 1 << bits
;
7103 return (value
>= lim
);
7107 /* Return non-zero if the indicated VALUE has overflowed the maximum
7108 range expressible by an signed number with the indicated number of
7112 signed_overflow (offsetT value
, unsigned bits
)
7115 if (bits
>= sizeof (offsetT
) * 8)
7117 lim
= (offsetT
) 1 << (bits
- 1);
7118 return (value
< -lim
|| value
>= lim
);
7121 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7122 unsigned immediate offset load/store instruction, try to encode it as
7123 an unscaled, 9-bit, signed immediate offset load/store instruction.
7124 Return TRUE if it is successful; otherwise return FALSE.
7126 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7127 in response to the standard LDR/STR mnemonics when the immediate offset is
7128 unambiguous, i.e. when it is negative or unaligned. */
7131 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7134 enum aarch64_op new_op
;
7135 const aarch64_opcode
*new_opcode
;
7137 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7139 switch (instr
->opcode
->op
)
7141 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7142 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7143 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7144 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7145 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7146 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7147 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7148 case OP_STR_POS
: new_op
= OP_STUR
; break;
7149 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7150 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7151 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7152 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7153 default: new_op
= OP_NIL
; break;
7156 if (new_op
== OP_NIL
)
7159 new_opcode
= aarch64_get_opcode (new_op
);
7160 gas_assert (new_opcode
!= NULL
);
7162 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7163 instr
->opcode
->op
, new_opcode
->op
);
7165 aarch64_replace_opcode (instr
, new_opcode
);
7167 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7168 qualifier matching may fail because the out-of-date qualifier will
7169 prevent the operand being updated with a new and correct qualifier. */
7170 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7171 AARCH64_OPND_ADDR_SIMM9
);
7172 gas_assert (idx
== 1);
7173 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7175 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7177 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
7183 /* Called by fix_insn to fix a MOV immediate alias instruction.
7185 Operand for a generic move immediate instruction, which is an alias
7186 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7187 a 32-bit/64-bit immediate value into general register. An assembler error
7188 shall result if the immediate cannot be created by a single one of these
7189 instructions. If there is a choice, then to ensure reversability an
7190 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7193 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7195 const aarch64_opcode
*opcode
;
7197 /* Need to check if the destination is SP/ZR. The check has to be done
7198 before any aarch64_replace_opcode. */
7199 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7200 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7202 instr
->operands
[1].imm
.value
= value
;
7203 instr
->operands
[1].skip
= 0;
7207 /* Try the MOVZ alias. */
7208 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7209 aarch64_replace_opcode (instr
, opcode
);
7210 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7211 &instr
->value
, NULL
, NULL
))
7213 put_aarch64_insn (buf
, instr
->value
);
7216 /* Try the MOVK alias. */
7217 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7218 aarch64_replace_opcode (instr
, opcode
);
7219 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7220 &instr
->value
, NULL
, NULL
))
7222 put_aarch64_insn (buf
, instr
->value
);
7227 if (try_mov_bitmask_p
)
7229 /* Try the ORR alias. */
7230 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7231 aarch64_replace_opcode (instr
, opcode
);
7232 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7233 &instr
->value
, NULL
, NULL
))
7235 put_aarch64_insn (buf
, instr
->value
);
7240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7241 _("immediate cannot be moved by a single instruction"));
7244 /* An instruction operand which is immediate related may have symbol used
7245 in the assembly, e.g.
7248 .set u32, 0x00ffff00
7250 At the time when the assembly instruction is parsed, a referenced symbol,
7251 like 'u32' in the above example may not have been seen; a fixS is created
7252 in such a case and is handled here after symbols have been resolved.
7253 Instruction is fixed up with VALUE using the information in *FIXP plus
7254 extra information in FLAGS.
7256 This function is called by md_apply_fix to fix up instructions that need
7257 a fix-up described above but does not involve any linker-time relocation. */
7260 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7264 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7265 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7266 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7270 /* Now the instruction is about to be fixed-up, so the operand that
7271 was previously marked as 'ignored' needs to be unmarked in order
7272 to get the encoding done properly. */
7273 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7274 new_inst
->operands
[idx
].skip
= 0;
7277 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7281 case AARCH64_OPND_EXCEPTION
:
7282 if (unsigned_overflow (value
, 16))
7283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7284 _("immediate out of range"));
7285 insn
= get_aarch64_insn (buf
);
7286 insn
|= encode_svc_imm (value
);
7287 put_aarch64_insn (buf
, insn
);
7290 case AARCH64_OPND_AIMM
:
7291 /* ADD or SUB with immediate.
7292 NOTE this assumes we come here with a add/sub shifted reg encoding
7293 3 322|2222|2 2 2 21111 111111
7294 1 098|7654|3 2 1 09876 543210 98765 43210
7295 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7296 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7297 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7298 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7300 3 322|2222|2 2 221111111111
7301 1 098|7654|3 2 109876543210 98765 43210
7302 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7303 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7304 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7305 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7306 Fields sf Rn Rd are already set. */
7307 insn
= get_aarch64_insn (buf
);
7311 insn
= reencode_addsub_switch_add_sub (insn
);
7315 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7316 && unsigned_overflow (value
, 12))
7318 /* Try to shift the value by 12 to make it fit. */
7319 if (((value
>> 12) << 12) == value
7320 && ! unsigned_overflow (value
, 12 + 12))
7323 insn
|= encode_addsub_imm_shift_amount (1);
7327 if (unsigned_overflow (value
, 12))
7328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7329 _("immediate out of range"));
7331 insn
|= encode_addsub_imm (value
);
7333 put_aarch64_insn (buf
, insn
);
7336 case AARCH64_OPND_SIMD_IMM
:
7337 case AARCH64_OPND_SIMD_IMM_SFT
:
7338 case AARCH64_OPND_LIMM
:
7339 /* Bit mask immediate. */
7340 gas_assert (new_inst
!= NULL
);
7341 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7342 new_inst
->operands
[idx
].imm
.value
= value
;
7343 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7344 &new_inst
->value
, NULL
, NULL
))
7345 put_aarch64_insn (buf
, new_inst
->value
);
7347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7348 _("invalid immediate"));
7351 case AARCH64_OPND_HALF
:
7352 /* 16-bit unsigned immediate. */
7353 if (unsigned_overflow (value
, 16))
7354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7355 _("immediate out of range"));
7356 insn
= get_aarch64_insn (buf
);
7357 insn
|= encode_movw_imm (value
& 0xffff);
7358 put_aarch64_insn (buf
, insn
);
7361 case AARCH64_OPND_IMM_MOV
:
7362 /* Operand for a generic move immediate instruction, which is
7363 an alias instruction that generates a single MOVZ, MOVN or ORR
7364 instruction to loads a 32-bit/64-bit immediate value into general
7365 register. An assembler error shall result if the immediate cannot be
7366 created by a single one of these instructions. If there is a choice,
7367 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7368 and MOVZ or MOVN to ORR. */
7369 gas_assert (new_inst
!= NULL
);
7370 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7373 case AARCH64_OPND_ADDR_SIMM7
:
7374 case AARCH64_OPND_ADDR_SIMM9
:
7375 case AARCH64_OPND_ADDR_SIMM9_2
:
7376 case AARCH64_OPND_ADDR_SIMM10
:
7377 case AARCH64_OPND_ADDR_UIMM12
:
7378 /* Immediate offset in an address. */
7379 insn
= get_aarch64_insn (buf
);
7381 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7382 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7383 || new_inst
->opcode
->operands
[2] == opnd
);
7385 /* Get the index of the address operand. */
7386 if (new_inst
->opcode
->operands
[1] == opnd
)
7387 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7390 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7393 /* Update the resolved offset value. */
7394 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7396 /* Encode/fix-up. */
7397 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7398 &new_inst
->value
, NULL
, NULL
))
7400 put_aarch64_insn (buf
, new_inst
->value
);
7403 else if (new_inst
->opcode
->iclass
== ldst_pos
7404 && try_to_encode_as_unscaled_ldst (new_inst
))
7406 put_aarch64_insn (buf
, new_inst
->value
);
7410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7411 _("immediate offset out of range"));
7416 as_fatal (_("unhandled operand code %d"), opnd
);
7420 /* Apply a fixup (fixP) to segment data, once it has been determined
7421 by our caller that we have all the info we need to fix it up.
7423 Parameter valP is the pointer to the value of the bits. */
7426 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7428 offsetT value
= *valP
;
7430 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7432 unsigned flags
= fixP
->fx_addnumber
;
7434 DEBUG_TRACE ("\n\n");
7435 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7436 DEBUG_TRACE ("Enter md_apply_fix");
7438 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7440 /* Note whether this will delete the relocation. */
7442 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7445 /* Process the relocations. */
7446 switch (fixP
->fx_r_type
)
7448 case BFD_RELOC_NONE
:
7449 /* This will need to go in the object file. */
7454 case BFD_RELOC_8_PCREL
:
7455 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7456 md_number_to_chars (buf
, value
, 1);
7460 case BFD_RELOC_16_PCREL
:
7461 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7462 md_number_to_chars (buf
, value
, 2);
7466 case BFD_RELOC_32_PCREL
:
7467 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7468 md_number_to_chars (buf
, value
, 4);
7472 case BFD_RELOC_64_PCREL
:
7473 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7474 md_number_to_chars (buf
, value
, 8);
7477 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7478 /* We claim that these fixups have been processed here, even if
7479 in fact we generate an error because we do not have a reloc
7480 for them, so tc_gen_reloc() will reject them. */
7482 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7485 _("undefined symbol %s used as an immediate value"),
7486 S_GET_NAME (fixP
->fx_addsy
));
7487 goto apply_fix_return
;
7489 fix_insn (fixP
, flags
, value
);
7492 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7493 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7497 _("pc-relative load offset not word aligned"));
7498 if (signed_overflow (value
, 21))
7499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7500 _("pc-relative load offset out of range"));
7501 insn
= get_aarch64_insn (buf
);
7502 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7503 put_aarch64_insn (buf
, insn
);
7507 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7508 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7510 if (signed_overflow (value
, 21))
7511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7512 _("pc-relative address offset out of range"));
7513 insn
= get_aarch64_insn (buf
);
7514 insn
|= encode_adr_imm (value
);
7515 put_aarch64_insn (buf
, insn
);
7519 case BFD_RELOC_AARCH64_BRANCH19
:
7520 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7524 _("conditional branch target not word aligned"));
7525 if (signed_overflow (value
, 21))
7526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7527 _("conditional branch out of range"));
7528 insn
= get_aarch64_insn (buf
);
7529 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7530 put_aarch64_insn (buf
, insn
);
7534 case BFD_RELOC_AARCH64_TSTBR14
:
7535 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7539 _("conditional branch target not word aligned"));
7540 if (signed_overflow (value
, 16))
7541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7542 _("conditional branch out of range"));
7543 insn
= get_aarch64_insn (buf
);
7544 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7545 put_aarch64_insn (buf
, insn
);
7549 case BFD_RELOC_AARCH64_CALL26
:
7550 case BFD_RELOC_AARCH64_JUMP26
:
7551 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7555 _("branch target not word aligned"));
7556 if (signed_overflow (value
, 28))
7557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7558 _("branch out of range"));
7559 insn
= get_aarch64_insn (buf
);
7560 insn
|= encode_branch_ofs_26 (value
>> 2);
7561 put_aarch64_insn (buf
, insn
);
7565 case BFD_RELOC_AARCH64_MOVW_G0
:
7566 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7567 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7568 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7571 case BFD_RELOC_AARCH64_MOVW_G1
:
7572 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7573 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7574 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7577 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7579 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7580 /* Should always be exported to object file, see
7581 aarch64_force_relocation(). */
7582 gas_assert (!fixP
->fx_done
);
7583 gas_assert (seg
->use_rela_p
);
7585 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7587 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7588 /* Should always be exported to object file, see
7589 aarch64_force_relocation(). */
7590 gas_assert (!fixP
->fx_done
);
7591 gas_assert (seg
->use_rela_p
);
7593 case BFD_RELOC_AARCH64_MOVW_G2
:
7594 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7595 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7598 case BFD_RELOC_AARCH64_MOVW_G3
:
7601 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7603 insn
= get_aarch64_insn (buf
);
7607 /* REL signed addend must fit in 16 bits */
7608 if (signed_overflow (value
, 16))
7609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7610 _("offset out of range"));
7614 /* Check for overflow and scale. */
7615 switch (fixP
->fx_r_type
)
7617 case BFD_RELOC_AARCH64_MOVW_G0
:
7618 case BFD_RELOC_AARCH64_MOVW_G1
:
7619 case BFD_RELOC_AARCH64_MOVW_G2
:
7620 case BFD_RELOC_AARCH64_MOVW_G3
:
7621 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7622 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7623 if (unsigned_overflow (value
, scale
+ 16))
7624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7625 _("unsigned value out of range"));
7627 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7628 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7629 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7630 /* NOTE: We can only come here with movz or movn. */
7631 if (signed_overflow (value
, scale
+ 16))
7632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7633 _("signed value out of range"));
7636 /* Force use of MOVN. */
7638 insn
= reencode_movzn_to_movn (insn
);
7642 /* Force use of MOVZ. */
7643 insn
= reencode_movzn_to_movz (insn
);
7647 /* Unchecked relocations. */
7653 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7654 insn
|= encode_movw_imm (value
& 0xffff);
7656 put_aarch64_insn (buf
, insn
);
7660 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7661 fixP
->fx_r_type
= (ilp32_p
7662 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7663 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7664 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7665 /* Should always be exported to object file, see
7666 aarch64_force_relocation(). */
7667 gas_assert (!fixP
->fx_done
);
7668 gas_assert (seg
->use_rela_p
);
7671 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7672 fixP
->fx_r_type
= (ilp32_p
7673 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7674 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7675 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7676 /* Should always be exported to object file, see
7677 aarch64_force_relocation(). */
7678 gas_assert (!fixP
->fx_done
);
7679 gas_assert (seg
->use_rela_p
);
7682 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7683 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7684 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7685 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7686 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7687 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7688 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7689 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7690 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7691 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7692 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7693 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7694 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7695 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7696 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7697 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7698 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7699 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7700 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7701 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7702 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7703 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7704 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7705 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7706 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7707 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7708 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7709 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7710 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7711 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7712 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7713 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7714 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7715 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7716 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7717 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7718 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7719 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7720 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7721 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7722 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7723 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7724 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7725 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7726 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7727 /* Should always be exported to object file, see
7728 aarch64_force_relocation(). */
7729 gas_assert (!fixP
->fx_done
);
7730 gas_assert (seg
->use_rela_p
);
7733 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7734 /* Should always be exported to object file, see
7735 aarch64_force_relocation(). */
7736 fixP
->fx_r_type
= (ilp32_p
7737 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7738 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7739 gas_assert (!fixP
->fx_done
);
7740 gas_assert (seg
->use_rela_p
);
7743 case BFD_RELOC_AARCH64_ADD_LO12
:
7744 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7745 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7746 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7747 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7748 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7749 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7750 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7751 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7752 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7753 case BFD_RELOC_AARCH64_LDST128_LO12
:
7754 case BFD_RELOC_AARCH64_LDST16_LO12
:
7755 case BFD_RELOC_AARCH64_LDST32_LO12
:
7756 case BFD_RELOC_AARCH64_LDST64_LO12
:
7757 case BFD_RELOC_AARCH64_LDST8_LO12
:
7758 /* Should always be exported to object file, see
7759 aarch64_force_relocation(). */
7760 gas_assert (!fixP
->fx_done
);
7761 gas_assert (seg
->use_rela_p
);
7764 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7765 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7766 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7769 case BFD_RELOC_UNUSED
:
7770 /* An error will already have been reported. */
7774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7775 _("unexpected %s fixup"),
7776 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7781 /* Free the allocated the struct aarch64_inst.
7782 N.B. currently there are very limited number of fix-up types actually use
7783 this field, so the impact on the performance should be minimal . */
7784 if (fixP
->tc_fix_data
.inst
!= NULL
)
7785 free (fixP
->tc_fix_data
.inst
);
7790 /* Translate internal representation of relocation info to BFD target
7794 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7797 bfd_reloc_code_real_type code
;
7799 reloc
= XNEW (arelent
);
7801 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7802 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7803 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7807 if (section
->use_rela_p
)
7808 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7810 fixp
->fx_offset
= reloc
->address
;
7812 reloc
->addend
= fixp
->fx_offset
;
7814 code
= fixp
->fx_r_type
;
7819 code
= BFD_RELOC_16_PCREL
;
7824 code
= BFD_RELOC_32_PCREL
;
7829 code
= BFD_RELOC_64_PCREL
;
7836 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7837 if (reloc
->howto
== NULL
)
7839 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7841 ("cannot represent %s relocation in this object file format"),
7842 bfd_get_reloc_code_name (code
));
7849 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7852 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7854 bfd_reloc_code_real_type type
;
7858 FIXME: @@ Should look at CPU word size. */
7865 type
= BFD_RELOC_16
;
7868 type
= BFD_RELOC_32
;
7871 type
= BFD_RELOC_64
;
7874 as_bad (_("cannot do %u-byte relocation"), size
);
7875 type
= BFD_RELOC_UNUSED
;
7879 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7883 aarch64_force_relocation (struct fix
*fixp
)
7885 switch (fixp
->fx_r_type
)
7887 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7888 /* Perform these "immediate" internal relocations
7889 even if the symbol is extern or weak. */
7892 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7893 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7894 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7895 /* Pseudo relocs that need to be fixed up according to
7899 case BFD_RELOC_AARCH64_ADD_LO12
:
7900 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7901 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7902 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7903 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7904 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7905 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7906 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7907 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7908 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7909 case BFD_RELOC_AARCH64_LDST128_LO12
:
7910 case BFD_RELOC_AARCH64_LDST16_LO12
:
7911 case BFD_RELOC_AARCH64_LDST32_LO12
:
7912 case BFD_RELOC_AARCH64_LDST64_LO12
:
7913 case BFD_RELOC_AARCH64_LDST8_LO12
:
7914 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7915 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7916 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7917 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7918 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7919 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7920 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7921 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7922 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7923 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7924 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7925 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7926 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7927 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7928 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7929 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7930 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7931 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7932 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7933 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7934 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7935 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7936 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7937 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7938 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7939 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7940 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7941 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7942 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7943 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7944 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7945 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7946 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7947 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7948 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7949 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7950 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7951 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7952 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7953 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7954 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7955 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7956 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7957 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7958 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7959 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7960 /* Always leave these relocations for the linker. */
7967 return generic_force_reloc (fixp
);
7973 elf64_aarch64_target_format (void)
7975 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7977 /* FIXME: What to do for ilp32_p ? */
7978 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7980 if (target_big_endian
)
7981 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7983 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7987 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7989 elf_frob_symbol (symp
, puntp
);
7993 /* MD interface: Finalization. */
7995 /* A good place to do this, although this was probably not intended
7996 for this kind of use. We need to dump the literal pool before
7997 references are made to a null symbol pointer. */
8000 aarch64_cleanup (void)
8004 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8006 /* Put it at the end of the relevant section. */
8007 subseg_set (pool
->section
, pool
->sub_section
);
8013 /* Remove any excess mapping symbols generated for alignment frags in
8014 SEC. We may have created a mapping symbol before a zero byte
8015 alignment; remove it if there's a mapping symbol after the
8018 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8019 void *dummy ATTRIBUTE_UNUSED
)
8021 segment_info_type
*seginfo
= seg_info (sec
);
8024 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8027 for (fragp
= seginfo
->frchainP
->frch_root
;
8028 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8030 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8031 fragS
*next
= fragp
->fr_next
;
8033 /* Variable-sized frags have been converted to fixed size by
8034 this point. But if this was variable-sized to start with,
8035 there will be a fixed-size frag after it. So don't handle
8037 if (sym
== NULL
|| next
== NULL
)
8040 if (S_GET_VALUE (sym
) < next
->fr_address
)
8041 /* Not at the end of this frag. */
8043 know (S_GET_VALUE (sym
) == next
->fr_address
);
8047 if (next
->tc_frag_data
.first_map
!= NULL
)
8049 /* Next frag starts with a mapping symbol. Discard this
8051 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8055 if (next
->fr_next
== NULL
)
8057 /* This mapping symbol is at the end of the section. Discard
8059 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8060 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8064 /* As long as we have empty frags without any mapping symbols,
8066 /* If the next frag is non-empty and does not start with a
8067 mapping symbol, then this mapping symbol is required. */
8068 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8071 next
= next
->fr_next
;
8073 while (next
!= NULL
);
8078 /* Adjust the symbol table. */
8081 aarch64_adjust_symtab (void)
8084 /* Remove any overlapping mapping symbols generated by alignment frags. */
8085 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8086 /* Now do generic ELF adjustments. */
8087 elf_adjust_symtab ();
8092 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8094 const char *hash_err
;
8096 hash_err
= hash_insert (table
, key
, value
);
8098 printf ("Internal Error: Can't hash %s\n", key
);
8102 fill_instruction_hash_table (void)
8104 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8106 while (opcode
->name
!= NULL
)
8108 templates
*templ
, *new_templ
;
8109 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8111 new_templ
= XNEW (templates
);
8112 new_templ
->opcode
= opcode
;
8113 new_templ
->next
= NULL
;
8116 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8119 new_templ
->next
= templ
->next
;
8120 templ
->next
= new_templ
;
8127 convert_to_upper (char *dst
, const char *src
, size_t num
)
8130 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8131 *dst
= TOUPPER (*src
);
8135 /* Assume STR point to a lower-case string, allocate, convert and return
8136 the corresponding upper-case string. */
8137 static inline const char*
8138 get_upper_str (const char *str
)
8141 size_t len
= strlen (str
);
8142 ret
= XNEWVEC (char, len
+ 1);
8143 convert_to_upper (ret
, str
, len
);
8147 /* MD interface: Initialization. */
8155 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8156 || (aarch64_cond_hsh
= hash_new ()) == NULL
8157 || (aarch64_shift_hsh
= hash_new ()) == NULL
8158 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8159 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8160 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8161 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8162 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8163 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8164 || (aarch64_reg_hsh
= hash_new ()) == NULL
8165 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8166 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8167 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8168 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8169 as_fatal (_("virtual memory exhausted"));
8171 fill_instruction_hash_table ();
8173 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8174 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8175 (void *) (aarch64_sys_regs
+ i
));
8177 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8178 checked_hash_insert (aarch64_pstatefield_hsh
,
8179 aarch64_pstatefields
[i
].name
,
8180 (void *) (aarch64_pstatefields
+ i
));
8182 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8183 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8184 aarch64_sys_regs_ic
[i
].name
,
8185 (void *) (aarch64_sys_regs_ic
+ i
));
8187 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8188 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8189 aarch64_sys_regs_dc
[i
].name
,
8190 (void *) (aarch64_sys_regs_dc
+ i
));
8192 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8193 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8194 aarch64_sys_regs_at
[i
].name
,
8195 (void *) (aarch64_sys_regs_at
+ i
));
8197 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8198 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8199 aarch64_sys_regs_tlbi
[i
].name
,
8200 (void *) (aarch64_sys_regs_tlbi
+ i
));
8202 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8203 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8204 (void *) (reg_names
+ i
));
8206 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8207 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8208 (void *) (nzcv_names
+ i
));
8210 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8212 const char *name
= aarch64_operand_modifiers
[i
].name
;
8213 checked_hash_insert (aarch64_shift_hsh
, name
,
8214 (void *) (aarch64_operand_modifiers
+ i
));
8215 /* Also hash the name in the upper case. */
8216 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8217 (void *) (aarch64_operand_modifiers
+ i
));
8220 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8223 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8224 the same condition code. */
8225 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8227 const char *name
= aarch64_conds
[i
].names
[j
];
8230 checked_hash_insert (aarch64_cond_hsh
, name
,
8231 (void *) (aarch64_conds
+ i
));
8232 /* Also hash the name in the upper case. */
8233 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8234 (void *) (aarch64_conds
+ i
));
8238 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8240 const char *name
= aarch64_barrier_options
[i
].name
;
8241 /* Skip xx00 - the unallocated values of option. */
8244 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8245 (void *) (aarch64_barrier_options
+ i
));
8246 /* Also hash the name in the upper case. */
8247 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8248 (void *) (aarch64_barrier_options
+ i
));
8251 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8253 const char* name
= aarch64_prfops
[i
].name
;
8254 /* Skip the unallocated hint encodings. */
8257 checked_hash_insert (aarch64_pldop_hsh
, name
,
8258 (void *) (aarch64_prfops
+ i
));
8259 /* Also hash the name in the upper case. */
8260 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8261 (void *) (aarch64_prfops
+ i
));
8264 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8266 const char* name
= aarch64_hint_options
[i
].name
;
8268 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8269 (void *) (aarch64_hint_options
+ i
));
8270 /* Also hash the name in the upper case. */
8271 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8272 (void *) (aarch64_hint_options
+ i
));
8275 /* Set the cpu variant based on the command-line options. */
8277 mcpu_cpu_opt
= march_cpu_opt
;
8280 mcpu_cpu_opt
= &cpu_default
;
8282 cpu_variant
= *mcpu_cpu_opt
;
8284 /* Record the CPU type. */
8285 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8287 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8290 /* Command line processing. */
8292 const char *md_shortopts
= "m:";
8294 #ifdef AARCH64_BI_ENDIAN
8295 #define OPTION_EB (OPTION_MD_BASE + 0)
8296 #define OPTION_EL (OPTION_MD_BASE + 1)
8298 #if TARGET_BYTES_BIG_ENDIAN
8299 #define OPTION_EB (OPTION_MD_BASE + 0)
8301 #define OPTION_EL (OPTION_MD_BASE + 1)
8305 struct option md_longopts
[] = {
8307 {"EB", no_argument
, NULL
, OPTION_EB
},
8310 {"EL", no_argument
, NULL
, OPTION_EL
},
8312 {NULL
, no_argument
, NULL
, 0}
8315 size_t md_longopts_size
= sizeof (md_longopts
);
8317 struct aarch64_option_table
8319 const char *option
; /* Option name to match. */
8320 const char *help
; /* Help information. */
8321 int *var
; /* Variable to change. */
8322 int value
; /* What to change it to. */
8323 char *deprecated
; /* If non-null, print this message. */
8326 static struct aarch64_option_table aarch64_opts
[] = {
8327 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8328 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8330 #ifdef DEBUG_AARCH64
8331 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8332 #endif /* DEBUG_AARCH64 */
8333 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8335 {"mno-verbose-error", N_("do not output verbose error messages"),
8336 &verbose_error_p
, 0, NULL
},
8337 {NULL
, NULL
, NULL
, 0, NULL
}
8340 struct aarch64_cpu_option_table
8343 const aarch64_feature_set value
;
8344 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8346 const char *canonical_name
;
8349 /* This list should, at a minimum, contain all the cpu names
8350 recognized by GCC. */
8351 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8352 {"all", AARCH64_ANY
, NULL
},
8353 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8354 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8355 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8356 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8357 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8358 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8359 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8360 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8361 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8362 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8363 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8364 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8365 "Samsung Exynos M1"},
8366 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8367 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8369 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8370 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8371 "Qualcomm QDF24XX"},
8372 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8373 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8375 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8376 AARCH64_FEATURE_CRYPTO
),
8378 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8379 in earlier releases and is superseded by 'xgene1' in all
8381 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8382 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8383 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8384 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8385 {"generic", AARCH64_ARCH_V8
, NULL
},
8387 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8390 struct aarch64_arch_option_table
8393 const aarch64_feature_set value
;
8396 /* This list should, at a minimum, contain all the architecture names
8397 recognized by GCC. */
8398 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8399 {"all", AARCH64_ANY
},
8400 {"armv8-a", AARCH64_ARCH_V8
},
8401 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8402 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8403 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8404 {NULL
, AARCH64_ARCH_NONE
}
8407 /* ISA extensions. */
8408 struct aarch64_option_cpu_value_table
8411 const aarch64_feature_set value
;
8412 const aarch64_feature_set require
; /* Feature dependencies. */
8415 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8416 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8418 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
8419 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8420 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8422 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8424 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8425 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8426 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8428 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8430 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8432 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8433 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8434 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8435 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8436 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8438 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8439 AARCH64_FEATURE (AARCH64_FEATURE_FP
8440 | AARCH64_FEATURE_SIMD
, 0)},
8441 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8444 struct aarch64_long_option_table
8446 const char *option
; /* Substring to match. */
8447 const char *help
; /* Help information. */
8448 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8449 char *deprecated
; /* If non-null, print this message. */
8452 /* Transitive closure of features depending on set. */
8453 static aarch64_feature_set
8454 aarch64_feature_disable_set (aarch64_feature_set set
)
8456 const struct aarch64_option_cpu_value_table
*opt
;
8457 aarch64_feature_set prev
= 0;
8459 while (prev
!= set
) {
8461 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8462 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8463 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8468 /* Transitive closure of dependencies of set. */
8469 static aarch64_feature_set
8470 aarch64_feature_enable_set (aarch64_feature_set set
)
8472 const struct aarch64_option_cpu_value_table
*opt
;
8473 aarch64_feature_set prev
= 0;
8475 while (prev
!= set
) {
8477 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8478 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8479 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8485 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8486 bfd_boolean ext_only
)
8488 /* We insist on extensions being added before being removed. We achieve
8489 this by using the ADDING_VALUE variable to indicate whether we are
8490 adding an extension (1) or removing it (0) and only allowing it to
8491 change in the order -1 -> 1 -> 0. */
8492 int adding_value
= -1;
8493 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8495 /* Copy the feature set, so that we can modify it. */
8499 while (str
!= NULL
&& *str
!= 0)
8501 const struct aarch64_option_cpu_value_table
*opt
;
8502 const char *ext
= NULL
;
8509 as_bad (_("invalid architectural extension"));
8513 ext
= strchr (++str
, '+');
8519 optlen
= strlen (str
);
8521 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8523 if (adding_value
!= 0)
8528 else if (optlen
> 0)
8530 if (adding_value
== -1)
8532 else if (adding_value
!= 1)
8534 as_bad (_("must specify extensions to add before specifying "
8535 "those to remove"));
8542 as_bad (_("missing architectural extension"));
8546 gas_assert (adding_value
!= -1);
8548 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8549 if (strncmp (opt
->name
, str
, optlen
) == 0)
8551 aarch64_feature_set set
;
8553 /* Add or remove the extension. */
8556 set
= aarch64_feature_enable_set (opt
->value
);
8557 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8561 set
= aarch64_feature_disable_set (opt
->value
);
8562 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8567 if (opt
->name
== NULL
)
8569 as_bad (_("unknown architectural extension `%s'"), str
);
8580 aarch64_parse_cpu (const char *str
)
8582 const struct aarch64_cpu_option_table
*opt
;
8583 const char *ext
= strchr (str
, '+');
8589 optlen
= strlen (str
);
8593 as_bad (_("missing cpu name `%s'"), str
);
8597 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8598 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8600 mcpu_cpu_opt
= &opt
->value
;
8602 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8607 as_bad (_("unknown cpu `%s'"), str
);
8612 aarch64_parse_arch (const char *str
)
8614 const struct aarch64_arch_option_table
*opt
;
8615 const char *ext
= strchr (str
, '+');
8621 optlen
= strlen (str
);
8625 as_bad (_("missing architecture name `%s'"), str
);
8629 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8630 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8632 march_cpu_opt
= &opt
->value
;
8634 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8639 as_bad (_("unknown architecture `%s'\n"), str
);
8644 struct aarch64_option_abi_value_table
8647 enum aarch64_abi_type value
;
8650 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8651 {"ilp32", AARCH64_ABI_ILP32
},
8652 {"lp64", AARCH64_ABI_LP64
},
8656 aarch64_parse_abi (const char *str
)
8662 as_bad (_("missing abi name `%s'"), str
);
8666 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8667 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8669 aarch64_abi
= aarch64_abis
[i
].value
;
8673 as_bad (_("unknown abi `%s'\n"), str
);
8677 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8679 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8680 aarch64_parse_abi
, NULL
},
8681 #endif /* OBJ_ELF */
8682 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8683 aarch64_parse_cpu
, NULL
},
8684 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8685 aarch64_parse_arch
, NULL
},
8686 {NULL
, NULL
, 0, NULL
}
8690 md_parse_option (int c
, const char *arg
)
8692 struct aarch64_option_table
*opt
;
8693 struct aarch64_long_option_table
*lopt
;
8699 target_big_endian
= 1;
8705 target_big_endian
= 0;
8710 /* Listing option. Just ignore these, we don't support additional
8715 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8717 if (c
== opt
->option
[0]
8718 && ((arg
== NULL
&& opt
->option
[1] == 0)
8719 || streq (arg
, opt
->option
+ 1)))
8721 /* If the option is deprecated, tell the user. */
8722 if (opt
->deprecated
!= NULL
)
8723 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8724 arg
? arg
: "", _(opt
->deprecated
));
8726 if (opt
->var
!= NULL
)
8727 *opt
->var
= opt
->value
;
8733 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8735 /* These options are expected to have an argument. */
8736 if (c
== lopt
->option
[0]
8738 && strncmp (arg
, lopt
->option
+ 1,
8739 strlen (lopt
->option
+ 1)) == 0)
8741 /* If the option is deprecated, tell the user. */
8742 if (lopt
->deprecated
!= NULL
)
8743 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8744 _(lopt
->deprecated
));
8746 /* Call the sup-option parser. */
8747 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8758 md_show_usage (FILE * fp
)
8760 struct aarch64_option_table
*opt
;
8761 struct aarch64_long_option_table
*lopt
;
8763 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8765 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8766 if (opt
->help
!= NULL
)
8767 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8769 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8770 if (lopt
->help
!= NULL
)
8771 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8775 -EB assemble code for a big-endian cpu\n"));
8780 -EL assemble code for a little-endian cpu\n"));
8784 /* Parse a .cpu directive. */
8787 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8789 const struct aarch64_cpu_option_table
*opt
;
8795 name
= input_line_pointer
;
8796 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8797 input_line_pointer
++;
8798 saved_char
= *input_line_pointer
;
8799 *input_line_pointer
= 0;
8801 ext
= strchr (name
, '+');
8804 optlen
= ext
- name
;
8806 optlen
= strlen (name
);
8808 /* Skip the first "all" entry. */
8809 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8810 if (strlen (opt
->name
) == optlen
8811 && strncmp (name
, opt
->name
, optlen
) == 0)
8813 mcpu_cpu_opt
= &opt
->value
;
8815 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8818 cpu_variant
= *mcpu_cpu_opt
;
8820 *input_line_pointer
= saved_char
;
8821 demand_empty_rest_of_line ();
8824 as_bad (_("unknown cpu `%s'"), name
);
8825 *input_line_pointer
= saved_char
;
8826 ignore_rest_of_line ();
8830 /* Parse a .arch directive. */
8833 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8835 const struct aarch64_arch_option_table
*opt
;
8841 name
= input_line_pointer
;
8842 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8843 input_line_pointer
++;
8844 saved_char
= *input_line_pointer
;
8845 *input_line_pointer
= 0;
8847 ext
= strchr (name
, '+');
8850 optlen
= ext
- name
;
8852 optlen
= strlen (name
);
8854 /* Skip the first "all" entry. */
8855 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8856 if (strlen (opt
->name
) == optlen
8857 && strncmp (name
, opt
->name
, optlen
) == 0)
8859 mcpu_cpu_opt
= &opt
->value
;
8861 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8864 cpu_variant
= *mcpu_cpu_opt
;
8866 *input_line_pointer
= saved_char
;
8867 demand_empty_rest_of_line ();
8871 as_bad (_("unknown architecture `%s'\n"), name
);
8872 *input_line_pointer
= saved_char
;
8873 ignore_rest_of_line ();
8876 /* Parse a .arch_extension directive. */
8879 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8882 char *ext
= input_line_pointer
;;
8884 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8885 input_line_pointer
++;
8886 saved_char
= *input_line_pointer
;
8887 *input_line_pointer
= 0;
8889 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8892 cpu_variant
= *mcpu_cpu_opt
;
8894 *input_line_pointer
= saved_char
;
8895 demand_empty_rest_of_line ();
8898 /* Copy symbol information. */
8901 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8903 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);