1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
71 #define DEFAULT_ARCH "aarch64"
74 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
75 static const char *default_arch
= DEFAULT_ARCH
;
77 /* AArch64 ABI for the output file. */
78 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
80 /* When non-zero, program to a 32-bit model, in which the C data types
81 int, long and all pointer types are 32-bit objects (ILP32); or to a
82 64-bit model, in which the C int type is 32-bits but the C long type
83 and all pointer types are 64-bit objects (LP64). */
84 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
99 /* Bits for DEFINED field in vector_type_el. */
100 #define NTA_HASTYPE 1
101 #define NTA_HASINDEX 2
102 #define NTA_HASVARWIDTH 4
104 struct vector_type_el
106 enum vector_el_type type
;
107 unsigned char defined
;
112 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
116 bfd_reloc_code_real_type type
;
119 enum aarch64_opnd opnd
;
121 unsigned need_libopcodes_p
: 1;
124 struct aarch64_instruction
126 /* libopcodes structure for instruction intermediate representation. */
128 /* Record assembly errors found during the parsing. */
131 enum aarch64_operand_error_kind kind
;
134 /* The condition that appears in the assembly line. */
136 /* Relocation information (including the GAS internal fixup). */
138 /* Need to generate an immediate in the literal pool. */
139 unsigned gen_lit_pool
: 1;
142 typedef struct aarch64_instruction aarch64_instruction
;
144 static aarch64_instruction inst
;
146 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
147 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
149 /* Diagnostics inline function utilities.
151 These are lightweight utilities which should only be called by parse_operands
152 and other parsers. GAS processes each assembly line by parsing it against
153 instruction template(s), in the case of multiple templates (for the same
154 mnemonic name), those templates are tried one by one until one succeeds or
155 all fail. An assembly line may fail a few templates before being
156 successfully parsed; an error saved here in most cases is not a user error
157 but an error indicating the current template is not the right template.
158 Therefore it is very important that errors can be saved at a low cost during
159 the parsing; we don't want to slow down the whole parsing by recording
160 non-user errors in detail.
162 Remember that the objective is to help GAS pick up the most appropriate
163 error message in the case of multiple templates, e.g. FMOV which has 8
169 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
170 inst
.parsing_error
.error
= NULL
;
173 static inline bfd_boolean
176 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
179 static inline const char *
180 get_error_message (void)
182 return inst
.parsing_error
.error
;
185 static inline enum aarch64_operand_error_kind
186 get_error_kind (void)
188 return inst
.parsing_error
.kind
;
192 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
194 inst
.parsing_error
.kind
= kind
;
195 inst
.parsing_error
.error
= error
;
199 set_recoverable_error (const char *error
)
201 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
204 /* Use the DESC field of the corresponding aarch64_operand entry to compose
205 the error message. */
207 set_default_error (void)
209 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
213 set_syntax_error (const char *error
)
215 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
219 set_first_syntax_error (const char *error
)
222 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
226 set_fatal_syntax_error (const char *error
)
228 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
231 /* Number of littlenums required to hold an extended precision number. */
232 #define MAX_LITTLENUMS 6
234 /* Return value for certain parsers when the parsing fails; those parsers
235 return the information of the parsed result, e.g. register number, on
237 #define PARSE_FAIL -1
239 /* This is an invalid condition code that means no conditional field is
241 #define COND_ALWAYS 0x10
245 const char *template;
251 const char *template;
258 bfd_reloc_code_real_type reloc
;
261 /* Macros to define the register types and masks for the purpose
264 #undef AARCH64_REG_TYPES
265 #define AARCH64_REG_TYPES \
266 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
267 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
268 BASIC_REG_TYPE(SP_32) /* wsp */ \
269 BASIC_REG_TYPE(SP_64) /* sp */ \
270 BASIC_REG_TYPE(Z_32) /* wzr */ \
271 BASIC_REG_TYPE(Z_64) /* xzr */ \
272 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
273 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
274 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
275 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
276 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
277 BASIC_REG_TYPE(VN) /* v[0-31] */ \
278 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
279 BASIC_REG_TYPE(PN) /* p[0-15] */ \
280 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
281 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
282 /* Typecheck: same, plus SVE registers. */ \
283 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
285 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
286 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
288 /* Typecheck: same, plus SVE registers. */ \
289 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
292 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
293 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
295 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
299 /* Typecheck: any [BHSDQ]P FP. */ \
300 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
301 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
302 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
305 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
306 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
307 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
308 be used for SVE instructions, since Zn and Pn are valid symbols \
309 in other contexts. */ \
310 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
312 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
313 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
314 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
315 | REG_TYPE(ZN) | REG_TYPE(PN)) \
316 /* Any integer register; used for error messages only. */ \
317 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
320 /* Pseudo type to mark the end of the enumerator sequence. */ \
323 #undef BASIC_REG_TYPE
324 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
325 #undef MULTI_REG_TYPE
326 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
328 /* Register type enumerators. */
329 typedef enum aarch64_reg_type_
331 /* A list of REG_TYPE_*. */
335 #undef BASIC_REG_TYPE
336 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
338 #define REG_TYPE(T) (1 << REG_TYPE_##T)
339 #undef MULTI_REG_TYPE
340 #define MULTI_REG_TYPE(T,V) V,
342 /* Structure for a hash table entry for a register. */
346 unsigned char number
;
347 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
348 unsigned char builtin
;
351 /* Values indexed by aarch64_reg_type to assist the type checking. */
352 static const unsigned reg_type_masks
[] =
357 #undef BASIC_REG_TYPE
359 #undef MULTI_REG_TYPE
360 #undef AARCH64_REG_TYPES
362 /* Diagnostics used when we don't get a register of the expected type.
363 Note: this has to synchronized with aarch64_reg_type definitions
366 get_reg_expected_msg (aarch64_reg_type reg_type
)
373 msg
= N_("integer 32-bit register expected");
376 msg
= N_("integer 64-bit register expected");
379 msg
= N_("integer register expected");
381 case REG_TYPE_R64_SP
:
382 msg
= N_("64-bit integer or SP register expected");
384 case REG_TYPE_SVE_BASE
:
385 msg
= N_("base register expected");
388 msg
= N_("integer or zero register expected");
390 case REG_TYPE_SVE_OFFSET
:
391 msg
= N_("offset register expected");
394 msg
= N_("integer or SP register expected");
396 case REG_TYPE_R_Z_SP
:
397 msg
= N_("integer, zero or SP register expected");
400 msg
= N_("8-bit SIMD scalar register expected");
403 msg
= N_("16-bit SIMD scalar or floating-point half precision "
404 "register expected");
407 msg
= N_("32-bit SIMD scalar or floating-point single precision "
408 "register expected");
411 msg
= N_("64-bit SIMD scalar or floating-point double precision "
412 "register expected");
415 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
416 "register expected");
418 case REG_TYPE_R_Z_BHSDQ_V
:
419 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
420 msg
= N_("register expected");
422 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
423 msg
= N_("SIMD scalar or floating-point register expected");
425 case REG_TYPE_VN
: /* any V reg */
426 msg
= N_("vector register expected");
429 msg
= N_("SVE vector register expected");
432 msg
= N_("SVE predicate register expected");
435 as_fatal (_("invalid register type %d"), reg_type
);
440 /* Some well known registers that we refer to directly elsewhere. */
443 /* Instructions take 4 bytes in the object file. */
446 static struct hash_control
*aarch64_ops_hsh
;
447 static struct hash_control
*aarch64_cond_hsh
;
448 static struct hash_control
*aarch64_shift_hsh
;
449 static struct hash_control
*aarch64_sys_regs_hsh
;
450 static struct hash_control
*aarch64_pstatefield_hsh
;
451 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
452 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
453 static struct hash_control
*aarch64_sys_regs_at_hsh
;
454 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
455 static struct hash_control
*aarch64_reg_hsh
;
456 static struct hash_control
*aarch64_barrier_opt_hsh
;
457 static struct hash_control
*aarch64_nzcv_hsh
;
458 static struct hash_control
*aarch64_pldop_hsh
;
459 static struct hash_control
*aarch64_hint_opt_hsh
;
461 /* Stuff needed to resolve the label ambiguity
470 static symbolS
*last_label_seen
;
472 /* Literal pool structure. Held on a per-section
473 and per-sub-section basis. */
475 #define MAX_LITERAL_POOL_SIZE 1024
476 typedef struct literal_expression
479 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
480 LITTLENUM_TYPE
* bignum
;
481 } literal_expression
;
483 typedef struct literal_pool
485 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
486 unsigned int next_free_entry
;
492 struct literal_pool
*next
;
495 /* Pointer to a linked list of literal pools. */
496 static literal_pool
*list_of_pools
= NULL
;
500 /* This array holds the chars that always start a comment. If the
501 pre-processor is disabled, these aren't very useful. */
502 const char comment_chars
[] = "";
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output. */
507 /* Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output. */
510 /* Also note that comments like this one will always work. */
511 const char line_comment_chars
[] = "#";
513 const char line_separator_chars
[] = ";";
515 /* Chars that can be used to separate mant
516 from exp in floating point numbers. */
517 const char EXP_CHARS
[] = "eE";
519 /* Chars that mean this number is a floating point constant. */
523 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
525 /* Prefix character that indicates the start of an immediate value. */
526 #define is_immediate_prefix(C) ((C) == '#')
528 /* Separator character handling. */
530 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
532 static inline bfd_boolean
533 skip_past_char (char **str
, char c
)
544 #define skip_past_comma(str) skip_past_char (str, ',')
546 /* Arithmetic expressions (possibly involving symbols). */
548 static bfd_boolean in_my_get_expression_p
= FALSE
;
550 /* Third argument to my_get_expression. */
551 #define GE_NO_PREFIX 0
552 #define GE_OPT_PREFIX 1
554 /* Return TRUE if the string pointed by *STR is successfully parsed
555 as an valid expression; *EP will be filled with the information of
556 such an expression. Otherwise return FALSE. */
559 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
564 int prefix_present_p
= 0;
571 if (is_immediate_prefix (**str
))
574 prefix_present_p
= 1;
581 memset (ep
, 0, sizeof (expressionS
));
583 save_in
= input_line_pointer
;
584 input_line_pointer
= *str
;
585 in_my_get_expression_p
= TRUE
;
586 seg
= expression (ep
);
587 in_my_get_expression_p
= FALSE
;
589 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
591 /* We found a bad expression in md_operand(). */
592 *str
= input_line_pointer
;
593 input_line_pointer
= save_in
;
594 if (prefix_present_p
&& ! error_p ())
595 set_fatal_syntax_error (_("bad expression"));
597 set_first_syntax_error (_("bad expression"));
602 if (seg
!= absolute_section
603 && seg
!= text_section
604 && seg
!= data_section
605 && seg
!= bss_section
&& seg
!= undefined_section
)
607 set_syntax_error (_("bad segment"));
608 *str
= input_line_pointer
;
609 input_line_pointer
= save_in
;
616 *str
= input_line_pointer
;
617 input_line_pointer
= save_in
;
621 /* Turn a string in input_line_pointer into a floating point constant
622 of type TYPE, and store the appropriate bytes in *LITP. The number
623 of LITTLENUMS emitted is stored in *SIZEP. An error message is
624 returned, or NULL on OK. */
627 md_atof (int type
, char *litP
, int *sizeP
)
629 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
632 /* We handle all bad expressions here, so that we can report the faulty
633 instruction in the error message. */
635 md_operand (expressionS
* exp
)
637 if (in_my_get_expression_p
)
638 exp
->X_op
= O_illegal
;
641 /* Immediate values. */
643 /* Errors may be set multiple times during parsing or bit encoding
644 (particularly in the Neon bits), but usually the earliest error which is set
645 will be the most meaningful. Avoid overwriting it with later (cascading)
646 errors by calling this function. */
649 first_error (const char *error
)
652 set_syntax_error (error
);
655 /* Similar to first_error, but this function accepts formatted error
658 first_error_fmt (const char *format
, ...)
663 /* N.B. this single buffer will not cause error messages for different
664 instructions to pollute each other; this is because at the end of
665 processing of each assembly line, error message if any will be
666 collected by as_bad. */
667 static char buffer
[size
];
671 int ret ATTRIBUTE_UNUSED
;
672 va_start (args
, format
);
673 ret
= vsnprintf (buffer
, size
, format
, args
);
674 know (ret
<= size
- 1 && ret
>= 0);
676 set_syntax_error (buffer
);
680 /* Register parsing. */
682 /* Generic register parser which is called by other specialized
684 CCP points to what should be the beginning of a register name.
685 If it is indeed a valid register name, advance CCP over it and
686 return the reg_entry structure; otherwise return NULL.
687 It does not issue diagnostics. */
690 parse_reg (char **ccp
)
696 #ifdef REGISTER_PREFIX
697 if (*start
!= REGISTER_PREFIX
)
703 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
708 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
710 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
719 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
722 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
724 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
727 /* Try to parse a base or offset register. Allow SVE base and offset
728 registers if REG_TYPE includes SVE registers. Return the register
729 entry on success, setting *QUALIFIER to the register qualifier.
730 Return null otherwise.
732 Note that this function does not issue any diagnostics. */
734 static const reg_entry
*
735 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
736 aarch64_opnd_qualifier_t
*qualifier
)
739 const reg_entry
*reg
= parse_reg (&str
);
749 *qualifier
= AARCH64_OPND_QLF_W
;
755 *qualifier
= AARCH64_OPND_QLF_X
;
759 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
762 switch (TOLOWER (str
[1]))
765 *qualifier
= AARCH64_OPND_QLF_S_S
;
768 *qualifier
= AARCH64_OPND_QLF_S_D
;
785 /* Try to parse a base or offset register. Return the register entry
786 on success, setting *QUALIFIER to the register qualifier. Return null
789 Note that this function does not issue any diagnostics. */
791 static const reg_entry
*
792 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
794 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
797 /* Parse the qualifier of a vector register or vector element of type
798 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
799 succeeds; otherwise return FALSE.
801 Accept only one occurrence of:
802 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
805 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
806 struct vector_type_el
*parsed_type
, char **str
)
810 unsigned element_size
;
811 enum vector_el_type type
;
814 gas_assert (*ptr
== '.');
817 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
822 width
= strtoul (ptr
, &ptr
, 10);
823 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
825 first_error_fmt (_("bad size %d in vector width specifier"), width
);
830 switch (TOLOWER (*ptr
))
849 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
858 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
860 first_error (_("missing element size"));
863 if (width
!= 0 && width
* element_size
!= 64
864 && width
* element_size
!= 128
865 && !(width
== 2 && element_size
== 16)
866 && !(width
== 4 && element_size
== 8))
869 ("invalid element size %d and vector size combination %c"),
875 parsed_type
->type
= type
;
876 parsed_type
->width
= width
;
883 /* *STR contains an SVE zero/merge predication suffix. Parse it into
884 *PARSED_TYPE and point *STR at the end of the suffix. */
887 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
892 gas_assert (*ptr
== '/');
894 switch (TOLOWER (*ptr
))
897 parsed_type
->type
= NT_zero
;
900 parsed_type
->type
= NT_merge
;
903 if (*ptr
!= '\0' && *ptr
!= ',')
904 first_error_fmt (_("unexpected character `%c' in predication type"),
907 first_error (_("missing predication type"));
910 parsed_type
->width
= 0;
915 /* Parse a register of the type TYPE.
917 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
918 name or the parsed register is not of TYPE.
920 Otherwise return the register number, and optionally fill in the actual
921 type of the register in *RTYPE when multiple alternatives were given, and
922 return the register shape and element index information in *TYPEINFO.
924 IN_REG_LIST should be set with TRUE if the caller is parsing a register
928 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
929 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
932 const reg_entry
*reg
= parse_reg (&str
);
933 struct vector_type_el atype
;
934 struct vector_type_el parsetype
;
935 bfd_boolean is_typed_vecreg
= FALSE
;
938 atype
.type
= NT_invtype
;
946 set_default_error ();
950 if (! aarch64_check_reg_type (reg
, type
))
952 DEBUG_TRACE ("reg type check failed");
953 set_default_error ();
958 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
959 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
963 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
968 if (!parse_predication_for_operand (&parsetype
, &str
))
972 /* Register if of the form Vn.[bhsdq]. */
973 is_typed_vecreg
= TRUE
;
975 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
977 /* The width is always variable; we don't allow an integer width
979 gas_assert (parsetype
.width
== 0);
980 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
982 else if (parsetype
.width
== 0)
983 /* Expect index. In the new scheme we cannot have
984 Vn.[bhsdq] represent a scalar. Therefore any
985 Vn.[bhsdq] should have an index following it.
986 Except in reglists of course. */
987 atype
.defined
|= NTA_HASINDEX
;
989 atype
.defined
|= NTA_HASTYPE
;
991 atype
.type
= parsetype
.type
;
992 atype
.width
= parsetype
.width
;
995 if (skip_past_char (&str
, '['))
999 /* Reject Sn[index] syntax. */
1000 if (!is_typed_vecreg
)
1002 first_error (_("this type of register can't be indexed"));
1008 first_error (_("index not allowed inside register list"));
1012 atype
.defined
|= NTA_HASINDEX
;
1014 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1016 if (exp
.X_op
!= O_constant
)
1018 first_error (_("constant expression required"));
1022 if (! skip_past_char (&str
, ']'))
1025 atype
.index
= exp
.X_add_number
;
1027 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1029 /* Indexed vector register expected. */
1030 first_error (_("indexed vector register expected"));
1034 /* A vector reg Vn should be typed or indexed. */
1035 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1037 first_error (_("invalid use of vector register"));
1053 Return the register number on success; return PARSE_FAIL otherwise.
1055 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1056 the register (e.g. NEON double or quad reg when either has been requested).
1058 If this is a NEON vector register with additional type information, fill
1059 in the struct pointed to by VECTYPE (if non-NULL).
1061 This parser does not handle register list. */
1064 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1065 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1067 struct vector_type_el atype
;
1069 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1070 /*in_reg_list= */ FALSE
);
1072 if (reg
== PARSE_FAIL
)
1083 static inline bfd_boolean
1084 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1088 && e1
.defined
== e2
.defined
1089 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1092 /* This function parses a list of vector registers of type TYPE.
1093 On success, it returns the parsed register list information in the
1094 following encoded format:
1096 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1097 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1099 The information of the register shape and/or index is returned in
1102 It returns PARSE_FAIL if the register list is invalid.
1104 The list contains one to four registers.
1105 Each register can be one of:
1108 All <T> should be identical.
1109 All <index> should be identical.
1110 There are restrictions on <Vt> numbers which are checked later
1111 (by reg_list_valid_p). */
1114 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1115 struct vector_type_el
*vectype
)
1119 struct vector_type_el typeinfo
, typeinfo_first
;
1124 bfd_boolean error
= FALSE
;
1125 bfd_boolean expect_index
= FALSE
;
1129 set_syntax_error (_("expecting {"));
1135 typeinfo_first
.defined
= 0;
1136 typeinfo_first
.type
= NT_invtype
;
1137 typeinfo_first
.width
= -1;
1138 typeinfo_first
.index
= 0;
1147 str
++; /* skip over '-' */
1150 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1151 /*in_reg_list= */ TRUE
);
1152 if (val
== PARSE_FAIL
)
1154 set_first_syntax_error (_("invalid vector register in list"));
1158 /* reject [bhsd]n */
1159 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1161 set_first_syntax_error (_("invalid scalar register in list"));
1166 if (typeinfo
.defined
& NTA_HASINDEX
)
1167 expect_index
= TRUE
;
1171 if (val
< val_range
)
1173 set_first_syntax_error
1174 (_("invalid range in vector register list"));
1183 typeinfo_first
= typeinfo
;
1184 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1186 set_first_syntax_error
1187 (_("type mismatch in vector register list"));
1192 for (i
= val_range
; i
<= val
; i
++)
1194 ret_val
|= i
<< (5 * nb_regs
);
1199 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1201 skip_whitespace (str
);
1204 set_first_syntax_error (_("end of vector register list not found"));
1209 skip_whitespace (str
);
1213 if (skip_past_char (&str
, '['))
1217 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1218 if (exp
.X_op
!= O_constant
)
1220 set_first_syntax_error (_("constant expression required."));
1223 if (! skip_past_char (&str
, ']'))
1226 typeinfo_first
.index
= exp
.X_add_number
;
1230 set_first_syntax_error (_("expected index"));
1237 set_first_syntax_error (_("too many registers in vector register list"));
1240 else if (nb_regs
== 0)
1242 set_first_syntax_error (_("empty vector register list"));
1248 *vectype
= typeinfo_first
;
1250 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1253 /* Directives: register aliases. */
1256 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1261 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1264 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1267 /* Only warn about a redefinition if it's not defined as the
1269 else if (new->number
!= number
|| new->type
!= type
)
1270 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1275 name
= xstrdup (str
);
1276 new = XNEW (reg_entry
);
1279 new->number
= number
;
1281 new->builtin
= FALSE
;
1283 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1289 /* Look for the .req directive. This is of the form:
1291 new_register_name .req existing_register_name
1293 If we find one, or if it looks sufficiently like one that we want to
1294 handle any error here, return TRUE. Otherwise return FALSE. */
1297 create_register_alias (char *newname
, char *p
)
1299 const reg_entry
*old
;
1300 char *oldname
, *nbuf
;
1303 /* The input scrubber ensures that whitespace after the mnemonic is
1304 collapsed to single spaces. */
1306 if (strncmp (oldname
, " .req ", 6) != 0)
1310 if (*oldname
== '\0')
1313 old
= hash_find (aarch64_reg_hsh
, oldname
);
1316 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1320 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1321 the desired alias name, and p points to its end. If not, then
1322 the desired alias name is in the global original_case_string. */
1323 #ifdef TC_CASE_SENSITIVE
1326 newname
= original_case_string
;
1327 nlen
= strlen (newname
);
1330 nbuf
= xmemdup0 (newname
, nlen
);
1332 /* Create aliases under the new name as stated; an all-lowercase
1333 version of the new name; and an all-uppercase version of the new
1335 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1337 for (p
= nbuf
; *p
; p
++)
1340 if (strncmp (nbuf
, newname
, nlen
))
1342 /* If this attempt to create an additional alias fails, do not bother
1343 trying to create the all-lower case alias. We will fail and issue
1344 a second, duplicate error message. This situation arises when the
1345 programmer does something like:
1348 The second .req creates the "Foo" alias but then fails to create
1349 the artificial FOO alias because it has already been created by the
1351 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1358 for (p
= nbuf
; *p
; p
++)
1361 if (strncmp (nbuf
, newname
, nlen
))
1362 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1369 /* Should never be called, as .req goes between the alias and the
1370 register name, not at the beginning of the line. */
1372 s_req (int a ATTRIBUTE_UNUSED
)
1374 as_bad (_("invalid syntax for .req directive"));
1377 /* The .unreq directive deletes an alias which was previously defined
1378 by .req. For example:
1384 s_unreq (int a ATTRIBUTE_UNUSED
)
1389 name
= input_line_pointer
;
1391 while (*input_line_pointer
!= 0
1392 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1393 ++input_line_pointer
;
1395 saved_char
= *input_line_pointer
;
1396 *input_line_pointer
= 0;
1399 as_bad (_("invalid syntax for .unreq directive"));
1402 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1405 as_bad (_("unknown register alias '%s'"), name
);
1406 else if (reg
->builtin
)
1407 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1414 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1415 free ((char *) reg
->name
);
1418 /* Also locate the all upper case and all lower case versions.
1419 Do not complain if we cannot find one or the other as it
1420 was probably deleted above. */
1422 nbuf
= strdup (name
);
1423 for (p
= nbuf
; *p
; p
++)
1425 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1428 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1429 free ((char *) reg
->name
);
1433 for (p
= nbuf
; *p
; p
++)
1435 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1438 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1439 free ((char *) reg
->name
);
1447 *input_line_pointer
= saved_char
;
1448 demand_empty_rest_of_line ();
1451 /* Directives: Instruction set selection. */
1454 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1455 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1456 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1457 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1459 /* Create a new mapping symbol for the transition to STATE. */
1462 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1465 const char *symname
;
1472 type
= BSF_NO_FLAGS
;
1476 type
= BSF_NO_FLAGS
;
1482 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1483 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1485 /* Save the mapping symbols for future reference. Also check that
1486 we do not place two mapping symbols at the same offset within a
1487 frag. We'll handle overlap between frags in
1488 check_mapping_symbols.
1490 If .fill or other data filling directive generates zero sized data,
1491 the mapping symbol for the following code will have the same value
1492 as the one generated for the data filling directive. In this case,
1493 we replace the old symbol with the new one at the same address. */
1496 if (frag
->tc_frag_data
.first_map
!= NULL
)
1498 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1499 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1502 frag
->tc_frag_data
.first_map
= symbolP
;
1504 if (frag
->tc_frag_data
.last_map
!= NULL
)
1506 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1507 S_GET_VALUE (symbolP
));
1508 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1509 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1512 frag
->tc_frag_data
.last_map
= symbolP
;
1515 /* We must sometimes convert a region marked as code to data during
1516 code alignment, if an odd number of bytes have to be padded. The
1517 code mapping symbol is pushed to an aligned address. */
1520 insert_data_mapping_symbol (enum mstate state
,
1521 valueT value
, fragS
* frag
, offsetT bytes
)
1523 /* If there was already a mapping symbol, remove it. */
1524 if (frag
->tc_frag_data
.last_map
!= NULL
1525 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1526 frag
->fr_address
+ value
)
1528 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1532 know (frag
->tc_frag_data
.first_map
== symp
);
1533 frag
->tc_frag_data
.first_map
= NULL
;
1535 frag
->tc_frag_data
.last_map
= NULL
;
1536 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1539 make_mapping_symbol (MAP_DATA
, value
, frag
);
1540 make_mapping_symbol (state
, value
+ bytes
, frag
);
1543 static void mapping_state_2 (enum mstate state
, int max_chars
);
1545 /* Set the mapping state to STATE. Only call this when about to
1546 emit some STATE bytes to the file. */
1549 mapping_state (enum mstate state
)
1551 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1553 if (state
== MAP_INSN
)
1554 /* AArch64 instructions require 4-byte alignment. When emitting
1555 instructions into any section, record the appropriate section
1557 record_alignment (now_seg
, 2);
1559 if (mapstate
== state
)
1560 /* The mapping symbol has already been emitted.
1561 There is nothing else to do. */
1564 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1565 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1566 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1567 evaluated later in the next else. */
1569 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1571 /* Only add the symbol if the offset is > 0:
1572 if we're at the first frag, check it's size > 0;
1573 if we're not at the first frag, then for sure
1574 the offset is > 0. */
1575 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1576 const int add_symbol
= (frag_now
!= frag_first
)
1577 || (frag_now_fix () > 0);
1580 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1584 mapping_state_2 (state
, 0);
1587 /* Same as mapping_state, but MAX_CHARS bytes have already been
1588 allocated. Put the mapping symbol that far back. */
1591 mapping_state_2 (enum mstate state
, int max_chars
)
1593 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1595 if (!SEG_NORMAL (now_seg
))
1598 if (mapstate
== state
)
1599 /* The mapping symbol has already been emitted.
1600 There is nothing else to do. */
1603 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1604 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1607 #define mapping_state(x) /* nothing */
1608 #define mapping_state_2(x, y) /* nothing */
1611 /* Directives: sectioning and alignment. */
1614 s_bss (int ignore ATTRIBUTE_UNUSED
)
1616 /* We don't support putting frags in the BSS segment, we fake it by
1617 marking in_bss, then looking at s_skip for clues. */
1618 subseg_set (bss_section
, 0);
1619 demand_empty_rest_of_line ();
1620 mapping_state (MAP_DATA
);
1624 s_even (int ignore ATTRIBUTE_UNUSED
)
1626 /* Never make frag if expect extra pass. */
1628 frag_align (1, 0, 0);
1630 record_alignment (now_seg
, 1);
1632 demand_empty_rest_of_line ();
1635 /* Directives: Literal pools. */
1637 static literal_pool
*
1638 find_literal_pool (int size
)
1642 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1644 if (pool
->section
== now_seg
1645 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1652 static literal_pool
*
1653 find_or_make_literal_pool (int size
)
1655 /* Next literal pool ID number. */
1656 static unsigned int latest_pool_num
= 1;
1659 pool
= find_literal_pool (size
);
1663 /* Create a new pool. */
1664 pool
= XNEW (literal_pool
);
1668 /* Currently we always put the literal pool in the current text
1669 section. If we were generating "small" model code where we
1670 knew that all code and initialised data was within 1MB then
1671 we could output literals to mergeable, read-only data
1674 pool
->next_free_entry
= 0;
1675 pool
->section
= now_seg
;
1676 pool
->sub_section
= now_subseg
;
1678 pool
->next
= list_of_pools
;
1679 pool
->symbol
= NULL
;
1681 /* Add it to the list. */
1682 list_of_pools
= pool
;
1685 /* New pools, and emptied pools, will have a NULL symbol. */
1686 if (pool
->symbol
== NULL
)
1688 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1689 (valueT
) 0, &zero_address_frag
);
1690 pool
->id
= latest_pool_num
++;
1697 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1698 Return TRUE on success, otherwise return FALSE. */
1700 add_to_lit_pool (expressionS
*exp
, int size
)
1705 pool
= find_or_make_literal_pool (size
);
1707 /* Check if this literal value is already in the pool. */
1708 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1710 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1712 if ((litexp
->X_op
== exp
->X_op
)
1713 && (exp
->X_op
== O_constant
)
1714 && (litexp
->X_add_number
== exp
->X_add_number
)
1715 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1718 if ((litexp
->X_op
== exp
->X_op
)
1719 && (exp
->X_op
== O_symbol
)
1720 && (litexp
->X_add_number
== exp
->X_add_number
)
1721 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1722 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1726 /* Do we need to create a new entry? */
1727 if (entry
== pool
->next_free_entry
)
1729 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1731 set_syntax_error (_("literal pool overflow"));
1735 pool
->literals
[entry
].exp
= *exp
;
1736 pool
->next_free_entry
+= 1;
1737 if (exp
->X_op
== O_big
)
1739 /* PR 16688: Bignums are held in a single global array. We must
1740 copy and preserve that value now, before it is overwritten. */
1741 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1743 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1744 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1747 pool
->literals
[entry
].bignum
= NULL
;
1750 exp
->X_op
= O_symbol
;
1751 exp
->X_add_number
= ((int) entry
) * size
;
1752 exp
->X_add_symbol
= pool
->symbol
;
1757 /* Can't use symbol_new here, so have to create a symbol and then at
1758 a later date assign it a value. That's what these functions do. */
1761 symbol_locate (symbolS
* symbolP
,
1762 const char *name
,/* It is copied, the caller can modify. */
1763 segT segment
, /* Segment identifier (SEG_<something>). */
1764 valueT valu
, /* Symbol value. */
1765 fragS
* frag
) /* Associated fragment. */
1768 char *preserved_copy_of_name
;
1770 name_length
= strlen (name
) + 1; /* +1 for \0. */
1771 obstack_grow (¬es
, name
, name_length
);
1772 preserved_copy_of_name
= obstack_finish (¬es
);
1774 #ifdef tc_canonicalize_symbol_name
1775 preserved_copy_of_name
=
1776 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1779 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1781 S_SET_SEGMENT (symbolP
, segment
);
1782 S_SET_VALUE (symbolP
, valu
);
1783 symbol_clear_list_pointers (symbolP
);
1785 symbol_set_frag (symbolP
, frag
);
1787 /* Link to end of symbol chain. */
1789 extern int symbol_table_frozen
;
1791 if (symbol_table_frozen
)
1795 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1797 obj_symbol_new_hook (symbolP
);
1799 #ifdef tc_symbol_new_hook
1800 tc_symbol_new_hook (symbolP
);
1804 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1805 #endif /* DEBUG_SYMS */
1810 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1817 for (align
= 2; align
<= 4; align
++)
1819 int size
= 1 << align
;
1821 pool
= find_literal_pool (size
);
1822 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1825 /* Align pool as you have word accesses.
1826 Only make a frag if we have to. */
1828 frag_align (align
, 0, 0);
1830 mapping_state (MAP_DATA
);
1832 record_alignment (now_seg
, align
);
1834 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1836 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1837 (valueT
) frag_now_fix (), frag_now
);
1838 symbol_table_insert (pool
->symbol
);
1840 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1842 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1844 if (exp
->X_op
== O_big
)
1846 /* PR 16688: Restore the global bignum value. */
1847 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1848 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1849 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1852 /* First output the expression in the instruction to the pool. */
1853 emit_expr (exp
, size
); /* .word|.xword */
1855 if (exp
->X_op
== O_big
)
1857 free (pool
->literals
[entry
].bignum
);
1858 pool
->literals
[entry
].bignum
= NULL
;
1862 /* Mark the pool as empty. */
1863 pool
->next_free_entry
= 0;
1864 pool
->symbol
= NULL
;
1869 /* Forward declarations for functions below, in the MD interface
1871 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1872 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1874 /* Directives: Data. */
1875 /* N.B. the support for relocation suffix in this directive needs to be
1876 implemented properly. */
1879 s_aarch64_elf_cons (int nbytes
)
1883 #ifdef md_flush_pending_output
1884 md_flush_pending_output ();
1887 if (is_it_end_of_statement ())
1889 demand_empty_rest_of_line ();
1893 #ifdef md_cons_align
1894 md_cons_align (nbytes
);
1897 mapping_state (MAP_DATA
);
1900 struct reloc_table_entry
*reloc
;
1904 if (exp
.X_op
!= O_symbol
)
1905 emit_expr (&exp
, (unsigned int) nbytes
);
1908 skip_past_char (&input_line_pointer
, '#');
1909 if (skip_past_char (&input_line_pointer
, ':'))
1911 reloc
= find_reloc_table_entry (&input_line_pointer
);
1913 as_bad (_("unrecognized relocation suffix"));
1915 as_bad (_("unimplemented relocation suffix"));
1916 ignore_rest_of_line ();
1920 emit_expr (&exp
, (unsigned int) nbytes
);
1923 while (*input_line_pointer
++ == ',');
1925 /* Put terminator back into stream. */
1926 input_line_pointer
--;
1927 demand_empty_rest_of_line ();
1930 #endif /* OBJ_ELF */
1932 /* Output a 32-bit word, but mark as an instruction. */
1935 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1939 #ifdef md_flush_pending_output
1940 md_flush_pending_output ();
1943 if (is_it_end_of_statement ())
1945 demand_empty_rest_of_line ();
1949 /* Sections are assumed to start aligned. In executable section, there is no
1950 MAP_DATA symbol pending. So we only align the address during
1951 MAP_DATA --> MAP_INSN transition.
1952 For other sections, this is not guaranteed. */
1953 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1954 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1955 frag_align_code (2, 0);
1958 mapping_state (MAP_INSN
);
1964 if (exp
.X_op
!= O_constant
)
1966 as_bad (_("constant expression required"));
1967 ignore_rest_of_line ();
1971 if (target_big_endian
)
1973 unsigned int val
= exp
.X_add_number
;
1974 exp
.X_add_number
= SWAP_32 (val
);
1976 emit_expr (&exp
, 4);
1978 while (*input_line_pointer
++ == ',');
1980 /* Put terminator back into stream. */
1981 input_line_pointer
--;
1982 demand_empty_rest_of_line ();
1986 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1989 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1995 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1996 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1998 demand_empty_rest_of_line ();
2001 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2004 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2008 /* Since we're just labelling the code, there's no need to define a
2011 /* Make sure there is enough room in this frag for the following
2012 blr. This trick only works if the blr follows immediately after
2013 the .tlsdesc directive. */
2015 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2016 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2018 demand_empty_rest_of_line ();
2021 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2024 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2030 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2031 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2033 demand_empty_rest_of_line ();
2035 #endif /* OBJ_ELF */
2037 static void s_aarch64_arch (int);
2038 static void s_aarch64_cpu (int);
2039 static void s_aarch64_arch_extension (int);
2041 /* This table describes all the machine specific pseudo-ops the assembler
2042 has to support. The fields are:
2043 pseudo-op name without dot
2044 function to call to execute this pseudo-op
2045 Integer arg to pass to the function. */
2047 const pseudo_typeS md_pseudo_table
[] = {
2048 /* Never called because '.req' does not start a line. */
2050 {"unreq", s_unreq
, 0},
2052 {"even", s_even
, 0},
2053 {"ltorg", s_ltorg
, 0},
2054 {"pool", s_ltorg
, 0},
2055 {"cpu", s_aarch64_cpu
, 0},
2056 {"arch", s_aarch64_arch
, 0},
2057 {"arch_extension", s_aarch64_arch_extension
, 0},
2058 {"inst", s_aarch64_inst
, 0},
2060 {"tlsdescadd", s_tlsdescadd
, 0},
2061 {"tlsdesccall", s_tlsdesccall
, 0},
2062 {"tlsdescldr", s_tlsdescldr
, 0},
2063 {"word", s_aarch64_elf_cons
, 4},
2064 {"long", s_aarch64_elf_cons
, 4},
2065 {"xword", s_aarch64_elf_cons
, 8},
2066 {"dword", s_aarch64_elf_cons
, 8},
2072 /* Check whether STR points to a register name followed by a comma or the
2073 end of line; REG_TYPE indicates which register types are checked
2074 against. Return TRUE if STR is such a register name; otherwise return
2075 FALSE. The function does not intend to produce any diagnostics, but since
2076 the register parser aarch64_reg_parse, which is called by this function,
2077 does produce diagnostics, we call clear_error to clear any diagnostics
2078 that may be generated by aarch64_reg_parse.
2079 Also, the function returns FALSE directly if there is any user error
2080 present at the function entry. This prevents the existing diagnostics
2081 state from being spoiled.
2082 The function currently serves parse_constant_immediate and
2083 parse_big_immediate only. */
2085 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2089 /* Prevent the diagnostics state from being spoiled. */
2093 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2095 /* Clear the parsing error that may be set by the reg parser. */
2098 if (reg
== PARSE_FAIL
)
2101 skip_whitespace (str
);
2102 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2108 /* Parser functions used exclusively in instruction operands. */
2110 /* Parse an immediate expression which may not be constant.
2112 To prevent the expression parser from pushing a register name
2113 into the symbol table as an undefined symbol, firstly a check is
2114 done to find out whether STR is a register of type REG_TYPE followed
2115 by a comma or the end of line. Return FALSE if STR is such a string. */
2118 parse_immediate_expression (char **str
, expressionS
*exp
,
2119 aarch64_reg_type reg_type
)
2121 if (reg_name_p (*str
, reg_type
))
2123 set_recoverable_error (_("immediate operand required"));
2127 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2129 if (exp
->X_op
== O_absent
)
2131 set_fatal_syntax_error (_("missing immediate expression"));
2138 /* Constant immediate-value read function for use in insn parsing.
2139 STR points to the beginning of the immediate (with the optional
2140 leading #); *VAL receives the value. REG_TYPE says which register
2141 names should be treated as registers rather than as symbolic immediates.
2143 Return TRUE on success; otherwise return FALSE. */
2146 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2150 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2153 if (exp
.X_op
!= O_constant
)
2155 set_syntax_error (_("constant expression required"));
2159 *val
= exp
.X_add_number
;
2164 encode_imm_float_bits (uint32_t imm
)
2166 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2167 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2170 /* Return TRUE if the single-precision floating-point value encoded in IMM
2171 can be expressed in the AArch64 8-bit signed floating-point format with
2172 3-bit exponent and normalized 4 bits of precision; in other words, the
2173 floating-point value must be expressable as
2174 (+/-) n / 16 * power (2, r)
2175 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2178 aarch64_imm_float_p (uint32_t imm
)
2180 /* If a single-precision floating-point value has the following bit
2181 pattern, it can be expressed in the AArch64 8-bit floating-point
2184 3 32222222 2221111111111
2185 1 09876543 21098765432109876543210
2186 n Eeeeeexx xxxx0000000000000000000
2188 where n, e and each x are either 0 or 1 independently, with
2193 /* Prepare the pattern for 'Eeeeee'. */
2194 if (((imm
>> 30) & 0x1) == 0)
2195 pattern
= 0x3e000000;
2197 pattern
= 0x40000000;
2199 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2200 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2203 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2204 as an IEEE float without any loss of precision. Store the value in
2208 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2210 /* If a double-precision floating-point value has the following bit
2211 pattern, it can be expressed in a float:
2213 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2214 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2215 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2217 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2218 if Eeee_eeee != 1111_1111
2220 where n, e, s and S are either 0 or 1 independently and where ~ is the
2224 uint32_t high32
= imm
>> 32;
2225 uint32_t low32
= imm
;
2227 /* Lower 29 bits need to be 0s. */
2228 if ((imm
& 0x1fffffff) != 0)
2231 /* Prepare the pattern for 'Eeeeeeeee'. */
2232 if (((high32
>> 30) & 0x1) == 0)
2233 pattern
= 0x38000000;
2235 pattern
= 0x40000000;
2238 if ((high32
& 0x78000000) != pattern
)
2241 /* Check Eeee_eeee != 1111_1111. */
2242 if ((high32
& 0x7ff00000) == 0x47f00000)
2245 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2246 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2247 | (low32
>> 29)); /* 3 S bits. */
2251 /* Return true if we should treat OPERAND as a double-precision
2252 floating-point operand rather than a single-precision one. */
2254 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2256 /* Check for unsuffixed SVE registers, which are allowed
2257 for LDR and STR but not in instructions that require an
2258 immediate. We get better error messages if we arbitrarily
2259 pick one size, parse the immediate normally, and then
2260 report the match failure in the normal way. */
2261 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2262 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2265 /* Parse a floating-point immediate. Return TRUE on success and return the
2266 value in *IMMED in the format of IEEE754 single-precision encoding.
2267 *CCP points to the start of the string; DP_P is TRUE when the immediate
2268 is expected to be in double-precision (N.B. this only matters when
2269 hexadecimal representation is involved). REG_TYPE says which register
2270 names should be treated as registers rather than as symbolic immediates.
2272 This routine accepts any IEEE float; it is up to the callers to reject
2276 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2277 aarch64_reg_type reg_type
)
2281 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2283 unsigned fpword
= 0;
2284 bfd_boolean hex_p
= FALSE
;
2286 skip_past_char (&str
, '#');
2289 skip_whitespace (fpnum
);
2291 if (strncmp (fpnum
, "0x", 2) == 0)
2293 /* Support the hexadecimal representation of the IEEE754 encoding.
2294 Double-precision is expected when DP_P is TRUE, otherwise the
2295 representation should be in single-precision. */
2296 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2301 if (!can_convert_double_to_float (val
, &fpword
))
2304 else if ((uint64_t) val
> 0xffffffff)
2311 else if (reg_name_p (str
, reg_type
))
2313 set_recoverable_error (_("immediate operand required"));
2321 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2324 /* Our FP word must be 32 bits (single-precision FP). */
2325 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2327 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2337 set_fatal_syntax_error (_("invalid floating-point constant"));
2341 /* Less-generic immediate-value read function with the possibility of loading
2342 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2345 To prevent the expression parser from pushing a register name into the
2346 symbol table as an undefined symbol, a check is firstly done to find
2347 out whether STR is a register of type REG_TYPE followed by a comma or
2348 the end of line. Return FALSE if STR is such a register. */
2351 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2355 if (reg_name_p (ptr
, reg_type
))
2357 set_syntax_error (_("immediate operand required"));
2361 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2363 if (inst
.reloc
.exp
.X_op
== O_constant
)
2364 *imm
= inst
.reloc
.exp
.X_add_number
;
2371 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2372 if NEED_LIBOPCODES is non-zero, the fixup will need
2373 assistance from the libopcodes. */
2376 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2377 const aarch64_opnd_info
*operand
,
2378 int need_libopcodes_p
)
2380 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2381 reloc
->opnd
= operand
->type
;
2382 if (need_libopcodes_p
)
2383 reloc
->need_libopcodes_p
= 1;
2386 /* Return TRUE if the instruction needs to be fixed up later internally by
2387 the GAS; otherwise return FALSE. */
2389 static inline bfd_boolean
2390 aarch64_gas_internal_fixup_p (void)
2392 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2395 /* Assign the immediate value to the relevant field in *OPERAND if
2396 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2397 needs an internal fixup in a later stage.
2398 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2399 IMM.VALUE that may get assigned with the constant. */
2401 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2402 aarch64_opnd_info
*operand
,
2404 int need_libopcodes_p
,
2407 if (reloc
->exp
.X_op
== O_constant
)
2410 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2412 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2413 reloc
->type
= BFD_RELOC_UNUSED
;
2417 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2418 /* Tell libopcodes to ignore this operand or not. This is helpful
2419 when one of the operands needs to be fixed up later but we need
2420 libopcodes to check the other operands. */
2421 operand
->skip
= skip_p
;
2425 /* Relocation modifiers. Each entry in the table contains the textual
2426 name for the relocation which may be placed before a symbol used as
2427 a load/store offset, or add immediate. It must be surrounded by a
2428 leading and trailing colon, for example:
2430 ldr x0, [x1, #:rello:varsym]
2431 add x0, x1, #:rello:varsym */
2433 struct reloc_table_entry
2437 bfd_reloc_code_real_type adr_type
;
2438 bfd_reloc_code_real_type adrp_type
;
2439 bfd_reloc_code_real_type movw_type
;
2440 bfd_reloc_code_real_type add_type
;
2441 bfd_reloc_code_real_type ldst_type
;
2442 bfd_reloc_code_real_type ld_literal_type
;
2445 static struct reloc_table_entry reloc_table
[] = {
2446 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2451 BFD_RELOC_AARCH64_ADD_LO12
,
2452 BFD_RELOC_AARCH64_LDST_LO12
,
2455 /* Higher 21 bits of pc-relative page offset: ADRP */
2458 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2464 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2467 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2473 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2477 BFD_RELOC_AARCH64_MOVW_G0
,
2482 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2486 BFD_RELOC_AARCH64_MOVW_G0_S
,
2491 /* Less significant bits 0-15 of address/value: MOVK, no check */
2495 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2500 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2504 BFD_RELOC_AARCH64_MOVW_G1
,
2509 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2513 BFD_RELOC_AARCH64_MOVW_G1_S
,
2518 /* Less significant bits 16-31 of address/value: MOVK, no check */
2522 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2527 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2531 BFD_RELOC_AARCH64_MOVW_G2
,
2536 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2540 BFD_RELOC_AARCH64_MOVW_G2_S
,
2545 /* Less significant bits 32-47 of address/value: MOVK, no check */
2549 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2554 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2558 BFD_RELOC_AARCH64_MOVW_G3
,
2563 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2567 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2572 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2576 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2581 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2585 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2590 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2594 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2599 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2603 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2608 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2612 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2617 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2621 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2626 /* Get to the page containing GOT entry for a symbol. */
2629 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2633 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2635 /* 12 bit offset into the page containing GOT entry for that symbol. */
2641 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2644 /* 0-15 bits of address/value: MOVk, no check. */
2648 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2653 /* Most significant bits 16-31 of address/value: MOVZ. */
2657 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2662 /* 15 bit offset into the page containing GOT entry for that symbol. */
2668 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2671 /* Get to the page containing GOT TLS entry for a symbol */
2672 {"gottprel_g0_nc", 0,
2675 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2680 /* Get to the page containing GOT TLS entry for a symbol */
2684 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2689 /* Get to the page containing GOT TLS entry for a symbol */
2691 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2692 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2698 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2703 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2707 /* Lower 16 bits address/value: MOVk. */
2711 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2716 /* Most significant bits 16-31 of address/value: MOVZ. */
2720 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2725 /* Get to the page containing GOT TLS entry for a symbol */
2727 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2728 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2732 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2734 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2739 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2740 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2743 /* Get to the page containing GOT TLS entry for a symbol.
2744 The same as GD, we allocate two consecutive GOT slots
2745 for module index and module offset, the only difference
2746 with GD is the module offset should be initialized to
2747 zero without any outstanding runtime relocation. */
2749 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2750 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2756 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2757 {"tlsldm_lo12_nc", 0,
2761 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2765 /* 12 bit offset into the module TLS base address. */
2770 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2771 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2774 /* Same as dtprel_lo12, no overflow check. */
2775 {"dtprel_lo12_nc", 0,
2779 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2780 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2783 /* bits[23:12] of offset to the module TLS base address. */
2788 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2792 /* bits[15:0] of offset to the module TLS base address. */
2796 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2801 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2805 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2810 /* bits[31:16] of offset to the module TLS base address. */
2814 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2819 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2823 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2828 /* bits[47:32] of offset to the module TLS base address. */
2832 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2837 /* Lower 16 bit offset into GOT entry for a symbol */
2838 {"tlsdesc_off_g0_nc", 0,
2841 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2846 /* Higher 16 bit offset into GOT entry for a symbol */
2847 {"tlsdesc_off_g1", 0,
2850 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2855 /* Get to the page containing GOT TLS entry for a symbol */
2858 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2862 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2864 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2865 {"gottprel_lo12", 0,
2870 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2873 /* Get tp offset for a symbol. */
2878 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2882 /* Get tp offset for a symbol. */
2887 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2888 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2891 /* Get tp offset for a symbol. */
2896 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2900 /* Get tp offset for a symbol. */
2901 {"tprel_lo12_nc", 0,
2905 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2906 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2909 /* Most significant bits 32-47 of address/value: MOVZ. */
2913 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2918 /* Most significant bits 16-31 of address/value: MOVZ. */
2922 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2927 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2931 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2936 /* Most significant bits 0-15 of address/value: MOVZ. */
2940 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2945 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2949 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2954 /* 15bit offset from got entry to base address of GOT table. */
2960 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2963 /* 14bit offset from got entry to base address of GOT table. */
2969 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2973 /* Given the address of a pointer pointing to the textual name of a
2974 relocation as may appear in assembler source, attempt to find its
2975 details in reloc_table. The pointer will be updated to the character
2976 after the trailing colon. On failure, NULL will be returned;
2977 otherwise return the reloc_table_entry. */
2979 static struct reloc_table_entry
*
2980 find_reloc_table_entry (char **str
)
2983 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2985 int length
= strlen (reloc_table
[i
].name
);
2987 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2988 && (*str
)[length
] == ':')
2990 *str
+= (length
+ 1);
2991 return &reloc_table
[i
];
2998 /* Mode argument to parse_shift and parser_shifter_operand. */
2999 enum parse_shift_mode
3001 SHIFTED_NONE
, /* no shifter allowed */
3002 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3004 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3006 SHIFTED_LSL
, /* bare "lsl #n" */
3007 SHIFTED_MUL
, /* bare "mul #n" */
3008 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3009 SHIFTED_MUL_VL
, /* "mul vl" */
3010 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3013 /* Parse a <shift> operator on an AArch64 data processing instruction.
3014 Return TRUE on success; otherwise return FALSE. */
3016 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3018 const struct aarch64_name_value_pair
*shift_op
;
3019 enum aarch64_modifier_kind kind
;
3025 for (p
= *str
; ISALPHA (*p
); p
++)
3030 set_syntax_error (_("shift expression expected"));
3034 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3036 if (shift_op
== NULL
)
3038 set_syntax_error (_("shift operator expected"));
3042 kind
= aarch64_get_operand_modifier (shift_op
);
3044 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3046 set_syntax_error (_("invalid use of 'MSL'"));
3050 if (kind
== AARCH64_MOD_MUL
3051 && mode
!= SHIFTED_MUL
3052 && mode
!= SHIFTED_MUL_VL
)
3054 set_syntax_error (_("invalid use of 'MUL'"));
3060 case SHIFTED_LOGIC_IMM
:
3061 if (aarch64_extend_operator_p (kind
))
3063 set_syntax_error (_("extending shift is not permitted"));
3068 case SHIFTED_ARITH_IMM
:
3069 if (kind
== AARCH64_MOD_ROR
)
3071 set_syntax_error (_("'ROR' shift is not permitted"));
3077 if (kind
!= AARCH64_MOD_LSL
)
3079 set_syntax_error (_("only 'LSL' shift is permitted"));
3085 if (kind
!= AARCH64_MOD_MUL
)
3087 set_syntax_error (_("only 'MUL' is permitted"));
3092 case SHIFTED_MUL_VL
:
3093 /* "MUL VL" consists of two separate tokens. Require the first
3094 token to be "MUL" and look for a following "VL". */
3095 if (kind
== AARCH64_MOD_MUL
)
3097 skip_whitespace (p
);
3098 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3101 kind
= AARCH64_MOD_MUL_VL
;
3105 set_syntax_error (_("only 'MUL VL' is permitted"));
3108 case SHIFTED_REG_OFFSET
:
3109 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3110 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3112 set_fatal_syntax_error
3113 (_("invalid shift for the register offset addressing mode"));
3118 case SHIFTED_LSL_MSL
:
3119 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3121 set_syntax_error (_("invalid shift operator"));
3130 /* Whitespace can appear here if the next thing is a bare digit. */
3131 skip_whitespace (p
);
3133 /* Parse shift amount. */
3135 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3136 exp
.X_op
= O_absent
;
3139 if (is_immediate_prefix (*p
))
3144 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3146 if (kind
== AARCH64_MOD_MUL_VL
)
3147 /* For consistency, give MUL VL the same shift amount as an implicit
3149 operand
->shifter
.amount
= 1;
3150 else if (exp
.X_op
== O_absent
)
3152 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3154 set_syntax_error (_("missing shift amount"));
3157 operand
->shifter
.amount
= 0;
3159 else if (exp
.X_op
!= O_constant
)
3161 set_syntax_error (_("constant shift amount required"));
3164 /* For parsing purposes, MUL #n has no inherent range. The range
3165 depends on the operand and will be checked by operand-specific
3167 else if (kind
!= AARCH64_MOD_MUL
3168 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3170 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3175 operand
->shifter
.amount
= exp
.X_add_number
;
3176 operand
->shifter
.amount_present
= 1;
3179 operand
->shifter
.operator_present
= 1;
3180 operand
->shifter
.kind
= kind
;
3186 /* Parse a <shifter_operand> for a data processing instruction:
3189 #<immediate>, LSL #imm
3191 Validation of immediate operands is deferred to md_apply_fix.
3193 Return TRUE on success; otherwise return FALSE. */
3196 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3197 enum parse_shift_mode mode
)
3201 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3206 /* Accept an immediate expression. */
3207 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3210 /* Accept optional LSL for arithmetic immediate values. */
3211 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3212 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3215 /* Not accept any shifter for logical immediate values. */
3216 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3217 && parse_shift (&p
, operand
, mode
))
3219 set_syntax_error (_("unexpected shift operator"));
3227 /* Parse a <shifter_operand> for a data processing instruction:
3232 #<immediate>, LSL #imm
3234 where <shift> is handled by parse_shift above, and the last two
3235 cases are handled by the function above.
3237 Validation of immediate operands is deferred to md_apply_fix.
3239 Return TRUE on success; otherwise return FALSE. */
3242 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3243 enum parse_shift_mode mode
)
3245 const reg_entry
*reg
;
3246 aarch64_opnd_qualifier_t qualifier
;
3247 enum aarch64_operand_class opd_class
3248 = aarch64_get_operand_class (operand
->type
);
3250 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3253 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3255 set_syntax_error (_("unexpected register in the immediate operand"));
3259 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3261 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3265 operand
->reg
.regno
= reg
->number
;
3266 operand
->qualifier
= qualifier
;
3268 /* Accept optional shift operation on register. */
3269 if (! skip_past_comma (str
))
3272 if (! parse_shift (str
, operand
, mode
))
3277 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3280 (_("integer register expected in the extended/shifted operand "
3285 /* We have a shifted immediate variable. */
3286 return parse_shifter_operand_imm (str
, operand
, mode
);
3289 /* Return TRUE on success; return FALSE otherwise. */
3292 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3293 enum parse_shift_mode mode
)
3297 /* Determine if we have the sequence of characters #: or just :
3298 coming next. If we do, then we check for a :rello: relocation
3299 modifier. If we don't, punt the whole lot to
3300 parse_shifter_operand. */
3302 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3304 struct reloc_table_entry
*entry
;
3312 /* Try to parse a relocation. Anything else is an error. */
3313 if (!(entry
= find_reloc_table_entry (str
)))
3315 set_syntax_error (_("unknown relocation modifier"));
3319 if (entry
->add_type
== 0)
3322 (_("this relocation modifier is not allowed on this instruction"));
3326 /* Save str before we decompose it. */
3329 /* Next, we parse the expression. */
3330 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3333 /* Record the relocation type (use the ADD variant here). */
3334 inst
.reloc
.type
= entry
->add_type
;
3335 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3337 /* If str is empty, we've reached the end, stop here. */
3341 /* Otherwise, we have a shifted reloc modifier, so rewind to
3342 recover the variable name and continue parsing for the shifter. */
3344 return parse_shifter_operand_imm (str
, operand
, mode
);
3347 return parse_shifter_operand (str
, operand
, mode
);
3350 /* Parse all forms of an address expression. Information is written
3351 to *OPERAND and/or inst.reloc.
3353 The A64 instruction set has the following addressing modes:
3356 [base] // in SIMD ld/st structure
3357 [base{,#0}] // in ld/st exclusive
3359 [base,Xm{,LSL #imm}]
3360 [base,Xm,SXTX {#imm}]
3361 [base,Wm,(S|U)XTW {#imm}]
3366 [base],Xm // in SIMD ld/st structure
3367 PC-relative (literal)
3371 [base,Zm.D{,LSL #imm}]
3372 [base,Zm.S,(S|U)XTW {#imm}]
3373 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3376 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3377 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3378 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3380 (As a convenience, the notation "=immediate" is permitted in conjunction
3381 with the pc-relative literal load instructions to automatically place an
3382 immediate value or symbolic address in a nearby literal pool and generate
3383 a hidden label which references it.)
3385 Upon a successful parsing, the address structure in *OPERAND will be
3386 filled in the following way:
3388 .base_regno = <base>
3389 .offset.is_reg // 1 if the offset is a register
3391 .offset.regno = <Rm>
3393 For different addressing modes defined in the A64 ISA:
3396 .pcrel=0; .preind=1; .postind=0; .writeback=0
3398 .pcrel=0; .preind=1; .postind=0; .writeback=1
3400 .pcrel=0; .preind=0; .postind=1; .writeback=1
3401 PC-relative (literal)
3402 .pcrel=1; .preind=1; .postind=0; .writeback=0
3404 The shift/extension information, if any, will be stored in .shifter.
3405 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3406 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3407 corresponding register.
3409 BASE_TYPE says which types of base register should be accepted and
3410 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3411 is the type of shifter that is allowed for immediate offsets,
3412 or SHIFTED_NONE if none.
3414 In all other respects, it is the caller's responsibility to check
3415 for addressing modes not supported by the instruction, and to set
3419 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3420 aarch64_opnd_qualifier_t
*base_qualifier
,
3421 aarch64_opnd_qualifier_t
*offset_qualifier
,
3422 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3423 enum parse_shift_mode imm_shift_mode
)
3426 const reg_entry
*reg
;
3427 expressionS
*exp
= &inst
.reloc
.exp
;
3429 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3430 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3431 if (! skip_past_char (&p
, '['))
3433 /* =immediate or label. */
3434 operand
->addr
.pcrel
= 1;
3435 operand
->addr
.preind
= 1;
3437 /* #:<reloc_op>:<symbol> */
3438 skip_past_char (&p
, '#');
3439 if (skip_past_char (&p
, ':'))
3441 bfd_reloc_code_real_type ty
;
3442 struct reloc_table_entry
*entry
;
3444 /* Try to parse a relocation modifier. Anything else is
3446 entry
= find_reloc_table_entry (&p
);
3449 set_syntax_error (_("unknown relocation modifier"));
3453 switch (operand
->type
)
3455 case AARCH64_OPND_ADDR_PCREL21
:
3457 ty
= entry
->adr_type
;
3461 ty
= entry
->ld_literal_type
;
3468 (_("this relocation modifier is not allowed on this "
3474 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3476 set_syntax_error (_("invalid relocation expression"));
3480 /* #:<reloc_op>:<expr> */
3481 /* Record the relocation type. */
3482 inst
.reloc
.type
= ty
;
3483 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3488 if (skip_past_char (&p
, '='))
3489 /* =immediate; need to generate the literal in the literal pool. */
3490 inst
.gen_lit_pool
= 1;
3492 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3494 set_syntax_error (_("invalid address"));
3505 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3506 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3508 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3511 operand
->addr
.base_regno
= reg
->number
;
3514 if (skip_past_comma (&p
))
3517 operand
->addr
.preind
= 1;
3519 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3522 if (!aarch64_check_reg_type (reg
, offset_type
))
3524 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3529 operand
->addr
.offset
.regno
= reg
->number
;
3530 operand
->addr
.offset
.is_reg
= 1;
3531 /* Shifted index. */
3532 if (skip_past_comma (&p
))
3535 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3536 /* Use the diagnostics set in parse_shift, so not set new
3537 error message here. */
3541 [base,Xm{,LSL #imm}]
3542 [base,Xm,SXTX {#imm}]
3543 [base,Wm,(S|U)XTW {#imm}] */
3544 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3545 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3546 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3548 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3550 set_syntax_error (_("invalid use of 32-bit register offset"));
3553 if (aarch64_get_qualifier_esize (*base_qualifier
)
3554 != aarch64_get_qualifier_esize (*offset_qualifier
))
3556 set_syntax_error (_("offset has different size from base"));
3560 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3562 set_syntax_error (_("invalid use of 64-bit register offset"));
3568 /* [Xn,#:<reloc_op>:<symbol> */
3569 skip_past_char (&p
, '#');
3570 if (skip_past_char (&p
, ':'))
3572 struct reloc_table_entry
*entry
;
3574 /* Try to parse a relocation modifier. Anything else is
3576 if (!(entry
= find_reloc_table_entry (&p
)))
3578 set_syntax_error (_("unknown relocation modifier"));
3582 if (entry
->ldst_type
== 0)
3585 (_("this relocation modifier is not allowed on this "
3590 /* [Xn,#:<reloc_op>: */
3591 /* We now have the group relocation table entry corresponding to
3592 the name in the assembler source. Next, we parse the
3594 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3596 set_syntax_error (_("invalid relocation expression"));
3600 /* [Xn,#:<reloc_op>:<expr> */
3601 /* Record the load/store relocation type. */
3602 inst
.reloc
.type
= entry
->ldst_type
;
3603 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3607 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3609 set_syntax_error (_("invalid expression in the address"));
3613 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3614 /* [Xn,<expr>,<shifter> */
3615 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3621 if (! skip_past_char (&p
, ']'))
3623 set_syntax_error (_("']' expected"));
3627 if (skip_past_char (&p
, '!'))
3629 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3631 set_syntax_error (_("register offset not allowed in pre-indexed "
3632 "addressing mode"));
3636 operand
->addr
.writeback
= 1;
3638 else if (skip_past_comma (&p
))
3641 operand
->addr
.postind
= 1;
3642 operand
->addr
.writeback
= 1;
3644 if (operand
->addr
.preind
)
3646 set_syntax_error (_("cannot combine pre- and post-indexing"));
3650 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3654 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3656 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3660 operand
->addr
.offset
.regno
= reg
->number
;
3661 operand
->addr
.offset
.is_reg
= 1;
3663 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3666 set_syntax_error (_("invalid expression in the address"));
3671 /* If at this point neither .preind nor .postind is set, we have a
3672 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3673 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3675 if (operand
->addr
.writeback
)
3678 set_syntax_error (_("missing offset in the pre-indexed address"));
3682 operand
->addr
.preind
= 1;
3683 inst
.reloc
.exp
.X_op
= O_constant
;
3684 inst
.reloc
.exp
.X_add_number
= 0;
3691 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3694 parse_address (char **str
, aarch64_opnd_info
*operand
)
3696 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3697 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3698 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3701 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3702 The arguments have the same meaning as for parse_address_main.
3703 Return TRUE on success. */
3705 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3706 aarch64_opnd_qualifier_t
*base_qualifier
,
3707 aarch64_opnd_qualifier_t
*offset_qualifier
)
3709 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3710 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3714 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3715 Return TRUE on success; otherwise return FALSE. */
3717 parse_half (char **str
, int *internal_fixup_p
)
3721 skip_past_char (&p
, '#');
3723 gas_assert (internal_fixup_p
);
3724 *internal_fixup_p
= 0;
3728 struct reloc_table_entry
*entry
;
3730 /* Try to parse a relocation. Anything else is an error. */
3732 if (!(entry
= find_reloc_table_entry (&p
)))
3734 set_syntax_error (_("unknown relocation modifier"));
3738 if (entry
->movw_type
== 0)
3741 (_("this relocation modifier is not allowed on this instruction"));
3745 inst
.reloc
.type
= entry
->movw_type
;
3748 *internal_fixup_p
= 1;
3750 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3757 /* Parse an operand for an ADRP instruction:
3759 Return TRUE on success; otherwise return FALSE. */
3762 parse_adrp (char **str
)
3769 struct reloc_table_entry
*entry
;
3771 /* Try to parse a relocation. Anything else is an error. */
3773 if (!(entry
= find_reloc_table_entry (&p
)))
3775 set_syntax_error (_("unknown relocation modifier"));
3779 if (entry
->adrp_type
== 0)
3782 (_("this relocation modifier is not allowed on this instruction"));
3786 inst
.reloc
.type
= entry
->adrp_type
;
3789 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3791 inst
.reloc
.pc_rel
= 1;
3793 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3800 /* Miscellaneous. */
3802 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3803 of SIZE tokens in which index I gives the token for field value I,
3804 or is null if field value I is invalid. REG_TYPE says which register
3805 names should be treated as registers rather than as symbolic immediates.
3807 Return true on success, moving *STR past the operand and storing the
3808 field value in *VAL. */
3811 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3812 size_t size
, aarch64_reg_type reg_type
)
3818 /* Match C-like tokens. */
3820 while (ISALNUM (*q
))
3823 for (i
= 0; i
< size
; ++i
)
3825 && strncasecmp (array
[i
], p
, q
- p
) == 0
3826 && array
[i
][q
- p
] == 0)
3833 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3836 if (exp
.X_op
== O_constant
3837 && (uint64_t) exp
.X_add_number
< size
)
3839 *val
= exp
.X_add_number
;
3844 /* Use the default error for this operand. */
3848 /* Parse an option for a preload instruction. Returns the encoding for the
3849 option, or PARSE_FAIL. */
3852 parse_pldop (char **str
)
3855 const struct aarch64_name_value_pair
*o
;
3858 while (ISALNUM (*q
))
3861 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3869 /* Parse an option for a barrier instruction. Returns the encoding for the
3870 option, or PARSE_FAIL. */
3873 parse_barrier (char **str
)
3876 const asm_barrier_opt
*o
;
3879 while (ISALPHA (*q
))
3882 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3890 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3891 return 0 if successful. Otherwise return PARSE_FAIL. */
3894 parse_barrier_psb (char **str
,
3895 const struct aarch64_name_value_pair
** hint_opt
)
3898 const struct aarch64_name_value_pair
*o
;
3901 while (ISALPHA (*q
))
3904 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3907 set_fatal_syntax_error
3908 ( _("unknown or missing option to PSB"));
3912 if (o
->value
!= 0x11)
3914 /* PSB only accepts option name 'CSYNC'. */
3916 (_("the specified option is not accepted for PSB"));
3925 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3926 Returns the encoding for the option, or PARSE_FAIL.
3928 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3929 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3931 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3932 field, otherwise as a system register.
3936 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3937 int imple_defined_p
, int pstatefield_p
,
3942 const aarch64_sys_reg
*o
;
3946 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3948 *p
++ = TOLOWER (*q
);
3950 /* Assert that BUF be large enough. */
3951 gas_assert (p
- buf
== q
- *str
);
3953 o
= hash_find (sys_regs
, buf
);
3956 if (!imple_defined_p
)
3960 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3961 unsigned int op0
, op1
, cn
, cm
, op2
;
3963 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3966 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3968 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3975 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3976 as_bad (_("selected processor does not support PSTATE field "
3978 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3979 as_bad (_("selected processor does not support system register "
3981 if (aarch64_sys_reg_deprecated_p (o
))
3982 as_warn (_("system register name '%s' is deprecated and may be "
3983 "removed in a future release"), buf
);
3993 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3994 for the option, or NULL. */
3996 static const aarch64_sys_ins_reg
*
3997 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4001 const aarch64_sys_ins_reg
*o
;
4004 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4006 *p
++ = TOLOWER (*q
);
4009 o
= hash_find (sys_ins_regs
, buf
);
4013 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4014 as_bad (_("selected processor does not support system register "
4021 #define po_char_or_fail(chr) do { \
4022 if (! skip_past_char (&str, chr)) \
4026 #define po_reg_or_fail(regtype) do { \
4027 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4028 if (val == PARSE_FAIL) \
4030 set_default_error (); \
4035 #define po_int_reg_or_fail(reg_type) do { \
4036 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4037 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4039 set_default_error (); \
4042 info->reg.regno = reg->number; \
4043 info->qualifier = qualifier; \
4046 #define po_imm_nc_or_fail() do { \
4047 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4051 #define po_imm_or_fail(min, max) do { \
4052 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4054 if (val < min || val > max) \
4056 set_fatal_syntax_error (_("immediate value out of range "\
4057 #min " to "#max)); \
4062 #define po_enum_or_fail(array) do { \
4063 if (!parse_enum_string (&str, &val, array, \
4064 ARRAY_SIZE (array), imm_reg_type)) \
4068 #define po_misc_or_fail(expr) do { \
4073 /* encode the 12-bit imm field of Add/sub immediate */
4074 static inline uint32_t
4075 encode_addsub_imm (uint32_t imm
)
4080 /* encode the shift amount field of Add/sub immediate */
4081 static inline uint32_t
4082 encode_addsub_imm_shift_amount (uint32_t cnt
)
4088 /* encode the imm field of Adr instruction */
4089 static inline uint32_t
4090 encode_adr_imm (uint32_t imm
)
4092 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4093 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4096 /* encode the immediate field of Move wide immediate */
4097 static inline uint32_t
4098 encode_movw_imm (uint32_t imm
)
4103 /* encode the 26-bit offset of unconditional branch */
4104 static inline uint32_t
4105 encode_branch_ofs_26 (uint32_t ofs
)
4107 return ofs
& ((1 << 26) - 1);
4110 /* encode the 19-bit offset of conditional branch and compare & branch */
4111 static inline uint32_t
4112 encode_cond_branch_ofs_19 (uint32_t ofs
)
4114 return (ofs
& ((1 << 19) - 1)) << 5;
4117 /* encode the 19-bit offset of ld literal */
4118 static inline uint32_t
4119 encode_ld_lit_ofs_19 (uint32_t ofs
)
4121 return (ofs
& ((1 << 19) - 1)) << 5;
4124 /* Encode the 14-bit offset of test & branch. */
4125 static inline uint32_t
4126 encode_tst_branch_ofs_14 (uint32_t ofs
)
4128 return (ofs
& ((1 << 14) - 1)) << 5;
4131 /* Encode the 16-bit imm field of svc/hvc/smc. */
4132 static inline uint32_t
4133 encode_svc_imm (uint32_t imm
)
4138 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4139 static inline uint32_t
4140 reencode_addsub_switch_add_sub (uint32_t opcode
)
4142 return opcode
^ (1 << 30);
4145 static inline uint32_t
4146 reencode_movzn_to_movz (uint32_t opcode
)
4148 return opcode
| (1 << 30);
4151 static inline uint32_t
4152 reencode_movzn_to_movn (uint32_t opcode
)
4154 return opcode
& ~(1 << 30);
4157 /* Overall per-instruction processing. */
4159 /* We need to be able to fix up arbitrary expressions in some statements.
4160 This is so that we can handle symbols that are an arbitrary distance from
4161 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4162 which returns part of an address in a form which will be valid for
4163 a data instruction. We do this by pushing the expression into a symbol
4164 in the expr_section, and creating a fix for that. */
4167 fix_new_aarch64 (fragS
* frag
,
4169 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4179 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4183 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4190 /* Diagnostics on operands errors. */
4192 /* By default, output verbose error message.
4193 Disable the verbose error message by -mno-verbose-error. */
4194 static int verbose_error_p
= 1;
4196 #ifdef DEBUG_AARCH64
4197 /* N.B. this is only for the purpose of debugging. */
4198 const char* operand_mismatch_kind_names
[] =
4201 "AARCH64_OPDE_RECOVERABLE",
4202 "AARCH64_OPDE_SYNTAX_ERROR",
4203 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4204 "AARCH64_OPDE_INVALID_VARIANT",
4205 "AARCH64_OPDE_OUT_OF_RANGE",
4206 "AARCH64_OPDE_UNALIGNED",
4207 "AARCH64_OPDE_REG_LIST",
4208 "AARCH64_OPDE_OTHER_ERROR",
4210 #endif /* DEBUG_AARCH64 */
4212 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4214 When multiple errors of different kinds are found in the same assembly
4215 line, only the error of the highest severity will be picked up for
4216 issuing the diagnostics. */
4218 static inline bfd_boolean
4219 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4220 enum aarch64_operand_error_kind rhs
)
4222 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4223 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4224 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4225 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4226 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4227 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4228 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4229 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4233 /* Helper routine to get the mnemonic name from the assembly instruction
4234 line; should only be called for the diagnosis purpose, as there is
4235 string copy operation involved, which may affect the runtime
4236 performance if used in elsewhere. */
4239 get_mnemonic_name (const char *str
)
4241 static char mnemonic
[32];
4244 /* Get the first 15 bytes and assume that the full name is included. */
4245 strncpy (mnemonic
, str
, 31);
4246 mnemonic
[31] = '\0';
4248 /* Scan up to the end of the mnemonic, which must end in white space,
4249 '.', or end of string. */
4250 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4255 /* Append '...' to the truncated long name. */
4256 if (ptr
- mnemonic
== 31)
4257 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4263 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4265 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4266 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4269 /* Data structures storing one user error in the assembly code related to
4272 struct operand_error_record
4274 const aarch64_opcode
*opcode
;
4275 aarch64_operand_error detail
;
4276 struct operand_error_record
*next
;
4279 typedef struct operand_error_record operand_error_record
;
4281 struct operand_errors
4283 operand_error_record
*head
;
4284 operand_error_record
*tail
;
4287 typedef struct operand_errors operand_errors
;
4289 /* Top-level data structure reporting user errors for the current line of
4291 The way md_assemble works is that all opcodes sharing the same mnemonic
4292 name are iterated to find a match to the assembly line. In this data
4293 structure, each of the such opcodes will have one operand_error_record
4294 allocated and inserted. In other words, excessive errors related with
4295 a single opcode are disregarded. */
4296 operand_errors operand_error_report
;
4298 /* Free record nodes. */
4299 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4301 /* Initialize the data structure that stores the operand mismatch
4302 information on assembling one line of the assembly code. */
4304 init_operand_error_report (void)
4306 if (operand_error_report
.head
!= NULL
)
4308 gas_assert (operand_error_report
.tail
!= NULL
);
4309 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4310 free_opnd_error_record_nodes
= operand_error_report
.head
;
4311 operand_error_report
.head
= NULL
;
4312 operand_error_report
.tail
= NULL
;
4315 gas_assert (operand_error_report
.tail
== NULL
);
4318 /* Return TRUE if some operand error has been recorded during the
4319 parsing of the current assembly line using the opcode *OPCODE;
4320 otherwise return FALSE. */
4321 static inline bfd_boolean
4322 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4324 operand_error_record
*record
= operand_error_report
.head
;
4325 return record
&& record
->opcode
== opcode
;
4328 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4329 OPCODE field is initialized with OPCODE.
4330 N.B. only one record for each opcode, i.e. the maximum of one error is
4331 recorded for each instruction template. */
4334 add_operand_error_record (const operand_error_record
* new_record
)
4336 const aarch64_opcode
*opcode
= new_record
->opcode
;
4337 operand_error_record
* record
= operand_error_report
.head
;
4339 /* The record may have been created for this opcode. If not, we need
4341 if (! opcode_has_operand_error_p (opcode
))
4343 /* Get one empty record. */
4344 if (free_opnd_error_record_nodes
== NULL
)
4346 record
= XNEW (operand_error_record
);
4350 record
= free_opnd_error_record_nodes
;
4351 free_opnd_error_record_nodes
= record
->next
;
4353 record
->opcode
= opcode
;
4354 /* Insert at the head. */
4355 record
->next
= operand_error_report
.head
;
4356 operand_error_report
.head
= record
;
4357 if (operand_error_report
.tail
== NULL
)
4358 operand_error_report
.tail
= record
;
4360 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4361 && record
->detail
.index
<= new_record
->detail
.index
4362 && operand_error_higher_severity_p (record
->detail
.kind
,
4363 new_record
->detail
.kind
))
4365 /* In the case of multiple errors found on operands related with a
4366 single opcode, only record the error of the leftmost operand and
4367 only if the error is of higher severity. */
4368 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4369 " the existing error %s on operand %d",
4370 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4371 new_record
->detail
.index
,
4372 operand_mismatch_kind_names
[record
->detail
.kind
],
4373 record
->detail
.index
);
4377 record
->detail
= new_record
->detail
;
4381 record_operand_error_info (const aarch64_opcode
*opcode
,
4382 aarch64_operand_error
*error_info
)
4384 operand_error_record record
;
4385 record
.opcode
= opcode
;
4386 record
.detail
= *error_info
;
4387 add_operand_error_record (&record
);
4390 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4391 error message *ERROR, for operand IDX (count from 0). */
4394 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4395 enum aarch64_operand_error_kind kind
,
4398 aarch64_operand_error info
;
4399 memset(&info
, 0, sizeof (info
));
4403 record_operand_error_info (opcode
, &info
);
4407 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4408 enum aarch64_operand_error_kind kind
,
4409 const char* error
, const int *extra_data
)
4411 aarch64_operand_error info
;
4415 info
.data
[0] = extra_data
[0];
4416 info
.data
[1] = extra_data
[1];
4417 info
.data
[2] = extra_data
[2];
4418 record_operand_error_info (opcode
, &info
);
4422 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4423 const char* error
, int lower_bound
,
4426 int data
[3] = {lower_bound
, upper_bound
, 0};
4427 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4431 /* Remove the operand error record for *OPCODE. */
4432 static void ATTRIBUTE_UNUSED
4433 remove_operand_error_record (const aarch64_opcode
*opcode
)
4435 if (opcode_has_operand_error_p (opcode
))
4437 operand_error_record
* record
= operand_error_report
.head
;
4438 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4439 operand_error_report
.head
= record
->next
;
4440 record
->next
= free_opnd_error_record_nodes
;
4441 free_opnd_error_record_nodes
= record
;
4442 if (operand_error_report
.head
== NULL
)
4444 gas_assert (operand_error_report
.tail
== record
);
4445 operand_error_report
.tail
= NULL
;
4450 /* Given the instruction in *INSTR, return the index of the best matched
4451 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4453 Return -1 if there is no qualifier sequence; return the first match
4454 if there is multiple matches found. */
4457 find_best_match (const aarch64_inst
*instr
,
4458 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4460 int i
, num_opnds
, max_num_matched
, idx
;
4462 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4465 DEBUG_TRACE ("no operand");
4469 max_num_matched
= 0;
4472 /* For each pattern. */
4473 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4476 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4478 /* Most opcodes has much fewer patterns in the list. */
4479 if (empty_qualifier_sequence_p (qualifiers
))
4481 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4485 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4486 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4489 if (num_matched
> max_num_matched
)
4491 max_num_matched
= num_matched
;
4496 DEBUG_TRACE ("return with %d", idx
);
4500 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4501 corresponding operands in *INSTR. */
4504 assign_qualifier_sequence (aarch64_inst
*instr
,
4505 const aarch64_opnd_qualifier_t
*qualifiers
)
4508 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4509 gas_assert (num_opnds
);
4510 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4511 instr
->operands
[i
].qualifier
= *qualifiers
;
4514 /* Print operands for the diagnosis purpose. */
4517 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4518 const aarch64_opnd_info
*opnds
)
4522 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4526 /* We regard the opcode operand info more, however we also look into
4527 the inst->operands to support the disassembling of the optional
4529 The two operand code should be the same in all cases, apart from
4530 when the operand can be optional. */
4531 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4532 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4535 /* Generate the operand string in STR. */
4536 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4540 strcat (buf
, i
== 0 ? " " : ", ");
4542 /* Append the operand string. */
4547 /* Send to stderr a string as information. */
4550 output_info (const char *format
, ...)
4556 file
= as_where (&line
);
4560 fprintf (stderr
, "%s:%u: ", file
, line
);
4562 fprintf (stderr
, "%s: ", file
);
4564 fprintf (stderr
, _("Info: "));
4565 va_start (args
, format
);
4566 vfprintf (stderr
, format
, args
);
4568 (void) putc ('\n', stderr
);
4571 /* Output one operand error record. */
4574 output_operand_error_record (const operand_error_record
*record
, char *str
)
4576 const aarch64_operand_error
*detail
= &record
->detail
;
4577 int idx
= detail
->index
;
4578 const aarch64_opcode
*opcode
= record
->opcode
;
4579 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4580 : AARCH64_OPND_NIL
);
4582 switch (detail
->kind
)
4584 case AARCH64_OPDE_NIL
:
4588 case AARCH64_OPDE_SYNTAX_ERROR
:
4589 case AARCH64_OPDE_RECOVERABLE
:
4590 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4591 case AARCH64_OPDE_OTHER_ERROR
:
4592 /* Use the prepared error message if there is, otherwise use the
4593 operand description string to describe the error. */
4594 if (detail
->error
!= NULL
)
4597 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4599 as_bad (_("%s at operand %d -- `%s'"),
4600 detail
->error
, idx
+ 1, str
);
4604 gas_assert (idx
>= 0);
4605 as_bad (_("operand %d must be %s -- `%s'"), idx
+ 1,
4606 aarch64_get_operand_desc (opd_code
), str
);
4610 case AARCH64_OPDE_INVALID_VARIANT
:
4611 as_bad (_("operand mismatch -- `%s'"), str
);
4612 if (verbose_error_p
)
4614 /* We will try to correct the erroneous instruction and also provide
4615 more information e.g. all other valid variants.
4617 The string representation of the corrected instruction and other
4618 valid variants are generated by
4620 1) obtaining the intermediate representation of the erroneous
4622 2) manipulating the IR, e.g. replacing the operand qualifier;
4623 3) printing out the instruction by calling the printer functions
4624 shared with the disassembler.
4626 The limitation of this method is that the exact input assembly
4627 line cannot be accurately reproduced in some cases, for example an
4628 optional operand present in the actual assembly line will be
4629 omitted in the output; likewise for the optional syntax rules,
4630 e.g. the # before the immediate. Another limitation is that the
4631 assembly symbols and relocation operations in the assembly line
4632 currently cannot be printed out in the error report. Last but not
4633 least, when there is other error(s) co-exist with this error, the
4634 'corrected' instruction may be still incorrect, e.g. given
4635 'ldnp h0,h1,[x0,#6]!'
4636 this diagnosis will provide the version:
4637 'ldnp s0,s1,[x0,#6]!'
4638 which is still not right. */
4639 size_t len
= strlen (get_mnemonic_name (str
));
4643 aarch64_inst
*inst_base
= &inst
.base
;
4644 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4647 reset_aarch64_instruction (&inst
);
4648 inst_base
->opcode
= opcode
;
4650 /* Reset the error report so that there is no side effect on the
4651 following operand parsing. */
4652 init_operand_error_report ();
4655 result
= parse_operands (str
+ len
, opcode
)
4656 && programmer_friendly_fixup (&inst
);
4657 gas_assert (result
);
4658 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4660 gas_assert (!result
);
4662 /* Find the most matched qualifier sequence. */
4663 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4664 gas_assert (qlf_idx
> -1);
4666 /* Assign the qualifiers. */
4667 assign_qualifier_sequence (inst_base
,
4668 opcode
->qualifiers_list
[qlf_idx
]);
4670 /* Print the hint. */
4671 output_info (_(" did you mean this?"));
4672 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4673 print_operands (buf
, opcode
, inst_base
->operands
);
4674 output_info (_(" %s"), buf
);
4676 /* Print out other variant(s) if there is any. */
4678 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4679 output_info (_(" other valid variant(s):"));
4681 /* For each pattern. */
4682 qualifiers_list
= opcode
->qualifiers_list
;
4683 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4685 /* Most opcodes has much fewer patterns in the list.
4686 First NIL qualifier indicates the end in the list. */
4687 if (empty_qualifier_sequence_p (*qualifiers_list
))
4692 /* Mnemonics name. */
4693 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4695 /* Assign the qualifiers. */
4696 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4698 /* Print instruction. */
4699 print_operands (buf
, opcode
, inst_base
->operands
);
4701 output_info (_(" %s"), buf
);
4707 case AARCH64_OPDE_UNTIED_OPERAND
:
4708 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4709 detail
->index
+ 1, str
);
4712 case AARCH64_OPDE_OUT_OF_RANGE
:
4713 if (detail
->data
[0] != detail
->data
[1])
4714 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4715 detail
->error
? detail
->error
: _("immediate value"),
4716 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4718 as_bad (_("%s must be %d at operand %d -- `%s'"),
4719 detail
->error
? detail
->error
: _("immediate value"),
4720 detail
->data
[0], idx
+ 1, str
);
4723 case AARCH64_OPDE_REG_LIST
:
4724 if (detail
->data
[0] == 1)
4725 as_bad (_("invalid number of registers in the list; "
4726 "only 1 register is expected at operand %d -- `%s'"),
4729 as_bad (_("invalid number of registers in the list; "
4730 "%d registers are expected at operand %d -- `%s'"),
4731 detail
->data
[0], idx
+ 1, str
);
4734 case AARCH64_OPDE_UNALIGNED
:
4735 as_bad (_("immediate value must be a multiple of "
4736 "%d at operand %d -- `%s'"),
4737 detail
->data
[0], idx
+ 1, str
);
4746 /* Process and output the error message about the operand mismatching.
4748 When this function is called, the operand error information had
4749 been collected for an assembly line and there will be multiple
4750 errors in the case of multiple instruction templates; output the
4751 error message that most closely describes the problem. */
4754 output_operand_error_report (char *str
)
4756 int largest_error_pos
;
4757 const char *msg
= NULL
;
4758 enum aarch64_operand_error_kind kind
;
4759 operand_error_record
*curr
;
4760 operand_error_record
*head
= operand_error_report
.head
;
4761 operand_error_record
*record
= NULL
;
4763 /* No error to report. */
4767 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4769 /* Only one error. */
4770 if (head
== operand_error_report
.tail
)
4772 DEBUG_TRACE ("single opcode entry with error kind: %s",
4773 operand_mismatch_kind_names
[head
->detail
.kind
]);
4774 output_operand_error_record (head
, str
);
4778 /* Find the error kind of the highest severity. */
4779 DEBUG_TRACE ("multiple opcode entries with error kind");
4780 kind
= AARCH64_OPDE_NIL
;
4781 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4783 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4784 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4785 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4786 kind
= curr
->detail
.kind
;
4788 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4790 /* Pick up one of errors of KIND to report. */
4791 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4792 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4794 if (curr
->detail
.kind
!= kind
)
4796 /* If there are multiple errors, pick up the one with the highest
4797 mismatching operand index. In the case of multiple errors with
4798 the equally highest operand index, pick up the first one or the
4799 first one with non-NULL error message. */
4800 if (curr
->detail
.index
> largest_error_pos
4801 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4802 && curr
->detail
.error
!= NULL
))
4804 largest_error_pos
= curr
->detail
.index
;
4806 msg
= record
->detail
.error
;
4810 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4811 DEBUG_TRACE ("Pick up error kind %s to report",
4812 operand_mismatch_kind_names
[record
->detail
.kind
]);
4815 output_operand_error_record (record
, str
);
4818 /* Write an AARCH64 instruction to buf - always little-endian. */
4820 put_aarch64_insn (char *buf
, uint32_t insn
)
4822 unsigned char *where
= (unsigned char *) buf
;
4824 where
[1] = insn
>> 8;
4825 where
[2] = insn
>> 16;
4826 where
[3] = insn
>> 24;
4830 get_aarch64_insn (char *buf
)
4832 unsigned char *where
= (unsigned char *) buf
;
4834 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4839 output_inst (struct aarch64_inst
*new_inst
)
4843 to
= frag_more (INSN_SIZE
);
4845 frag_now
->tc_frag_data
.recorded
= 1;
4847 put_aarch64_insn (to
, inst
.base
.value
);
4849 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4851 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4852 INSN_SIZE
, &inst
.reloc
.exp
,
4855 DEBUG_TRACE ("Prepared relocation fix up");
4856 /* Don't check the addend value against the instruction size,
4857 that's the job of our code in md_apply_fix(). */
4858 fixp
->fx_no_overflow
= 1;
4859 if (new_inst
!= NULL
)
4860 fixp
->tc_fix_data
.inst
= new_inst
;
4861 if (aarch64_gas_internal_fixup_p ())
4863 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4864 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4865 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4869 dwarf2_emit_insn (INSN_SIZE
);
4872 /* Link together opcodes of the same name. */
4876 aarch64_opcode
*opcode
;
4877 struct templates
*next
;
4880 typedef struct templates templates
;
4883 lookup_mnemonic (const char *start
, int len
)
4885 templates
*templ
= NULL
;
4887 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4891 /* Subroutine of md_assemble, responsible for looking up the primary
4892 opcode from the mnemonic the user wrote. STR points to the
4893 beginning of the mnemonic. */
4896 opcode_lookup (char **str
)
4898 char *end
, *base
, *dot
;
4899 const aarch64_cond
*cond
;
4903 /* Scan up to the end of the mnemonic, which must end in white space,
4904 '.', or end of string. */
4906 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4907 if (*end
== '.' && !dot
)
4910 if (end
== base
|| dot
== base
)
4913 inst
.cond
= COND_ALWAYS
;
4915 /* Handle a possible condition. */
4918 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
4921 inst
.cond
= cond
->value
;
4937 if (inst
.cond
== COND_ALWAYS
)
4939 /* Look for unaffixed mnemonic. */
4940 return lookup_mnemonic (base
, len
);
4944 /* append ".c" to mnemonic if conditional */
4945 memcpy (condname
, base
, len
);
4946 memcpy (condname
+ len
, ".c", 2);
4949 return lookup_mnemonic (base
, len
);
4955 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4956 to a corresponding operand qualifier. */
4958 static inline aarch64_opnd_qualifier_t
4959 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4961 /* Element size in bytes indexed by vector_el_type. */
4962 const unsigned char ele_size
[5]
4964 const unsigned int ele_base
[5] =
4966 AARCH64_OPND_QLF_V_4B
,
4967 AARCH64_OPND_QLF_V_2H
,
4968 AARCH64_OPND_QLF_V_2S
,
4969 AARCH64_OPND_QLF_V_1D
,
4970 AARCH64_OPND_QLF_V_1Q
4973 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4974 goto vectype_conversion_fail
;
4976 if (vectype
->type
== NT_zero
)
4977 return AARCH64_OPND_QLF_P_Z
;
4978 if (vectype
->type
== NT_merge
)
4979 return AARCH64_OPND_QLF_P_M
;
4981 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4983 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4985 /* Special case S_4B. */
4986 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
4987 return AARCH64_OPND_QLF_S_4B
;
4989 /* Vector element register. */
4990 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4994 /* Vector register. */
4995 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4998 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4999 goto vectype_conversion_fail
;
5001 /* The conversion is by calculating the offset from the base operand
5002 qualifier for the vector type. The operand qualifiers are regular
5003 enough that the offset can established by shifting the vector width by
5004 a vector-type dependent amount. */
5006 if (vectype
->type
== NT_b
)
5008 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5010 else if (vectype
->type
>= NT_d
)
5015 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5016 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5017 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5021 vectype_conversion_fail
:
5022 first_error (_("bad vector arrangement type"));
5023 return AARCH64_OPND_QLF_NIL
;
5026 /* Process an optional operand that is found omitted from the assembly line.
5027 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5028 instruction's opcode entry while IDX is the index of this omitted operand.
5032 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5033 int idx
, aarch64_opnd_info
*operand
)
5035 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5036 gas_assert (optional_operand_p (opcode
, idx
));
5037 gas_assert (!operand
->present
);
5041 case AARCH64_OPND_Rd
:
5042 case AARCH64_OPND_Rn
:
5043 case AARCH64_OPND_Rm
:
5044 case AARCH64_OPND_Rt
:
5045 case AARCH64_OPND_Rt2
:
5046 case AARCH64_OPND_Rs
:
5047 case AARCH64_OPND_Ra
:
5048 case AARCH64_OPND_Rt_SYS
:
5049 case AARCH64_OPND_Rd_SP
:
5050 case AARCH64_OPND_Rn_SP
:
5051 case AARCH64_OPND_Rm_SP
:
5052 case AARCH64_OPND_Fd
:
5053 case AARCH64_OPND_Fn
:
5054 case AARCH64_OPND_Fm
:
5055 case AARCH64_OPND_Fa
:
5056 case AARCH64_OPND_Ft
:
5057 case AARCH64_OPND_Ft2
:
5058 case AARCH64_OPND_Sd
:
5059 case AARCH64_OPND_Sn
:
5060 case AARCH64_OPND_Sm
:
5061 case AARCH64_OPND_Va
:
5062 case AARCH64_OPND_Vd
:
5063 case AARCH64_OPND_Vn
:
5064 case AARCH64_OPND_Vm
:
5065 case AARCH64_OPND_VdD1
:
5066 case AARCH64_OPND_VnD1
:
5067 operand
->reg
.regno
= default_value
;
5070 case AARCH64_OPND_Ed
:
5071 case AARCH64_OPND_En
:
5072 case AARCH64_OPND_Em
:
5073 case AARCH64_OPND_SM3_IMM2
:
5074 operand
->reglane
.regno
= default_value
;
5077 case AARCH64_OPND_IDX
:
5078 case AARCH64_OPND_BIT_NUM
:
5079 case AARCH64_OPND_IMMR
:
5080 case AARCH64_OPND_IMMS
:
5081 case AARCH64_OPND_SHLL_IMM
:
5082 case AARCH64_OPND_IMM_VLSL
:
5083 case AARCH64_OPND_IMM_VLSR
:
5084 case AARCH64_OPND_CCMP_IMM
:
5085 case AARCH64_OPND_FBITS
:
5086 case AARCH64_OPND_UIMM4
:
5087 case AARCH64_OPND_UIMM3_OP1
:
5088 case AARCH64_OPND_UIMM3_OP2
:
5089 case AARCH64_OPND_IMM
:
5090 case AARCH64_OPND_IMM_2
:
5091 case AARCH64_OPND_WIDTH
:
5092 case AARCH64_OPND_UIMM7
:
5093 case AARCH64_OPND_NZCV
:
5094 case AARCH64_OPND_SVE_PATTERN
:
5095 case AARCH64_OPND_SVE_PRFOP
:
5096 operand
->imm
.value
= default_value
;
5099 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5100 operand
->imm
.value
= default_value
;
5101 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5102 operand
->shifter
.amount
= 1;
5105 case AARCH64_OPND_EXCEPTION
:
5106 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5109 case AARCH64_OPND_BARRIER_ISB
:
5110 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5117 /* Process the relocation type for move wide instructions.
5118 Return TRUE on success; otherwise return FALSE. */
5121 process_movw_reloc_info (void)
5126 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5128 if (inst
.base
.opcode
->op
== OP_MOVK
)
5129 switch (inst
.reloc
.type
)
5131 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5132 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5133 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5134 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5135 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5136 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5137 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5138 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5139 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5140 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5141 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5143 (_("the specified relocation type is not allowed for MOVK"));
5149 switch (inst
.reloc
.type
)
5151 case BFD_RELOC_AARCH64_MOVW_G0
:
5152 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5153 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5154 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5155 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5156 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5157 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5158 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5159 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5160 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5161 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5162 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5163 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5166 case BFD_RELOC_AARCH64_MOVW_G1
:
5167 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5168 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5169 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5170 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5171 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5172 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5173 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5174 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5175 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5176 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5177 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5178 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5181 case BFD_RELOC_AARCH64_MOVW_G2
:
5182 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5183 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5184 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5185 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5186 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5187 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5190 set_fatal_syntax_error
5191 (_("the specified relocation type is not allowed for 32-bit "
5197 case BFD_RELOC_AARCH64_MOVW_G3
:
5198 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5201 set_fatal_syntax_error
5202 (_("the specified relocation type is not allowed for 32-bit "
5209 /* More cases should be added when more MOVW-related relocation types
5210 are supported in GAS. */
5211 gas_assert (aarch64_gas_internal_fixup_p ());
5212 /* The shift amount should have already been set by the parser. */
5215 inst
.base
.operands
[1].shifter
.amount
= shift
;
5219 /* A primitive log calculator. */
5221 static inline unsigned int
5222 get_logsz (unsigned int size
)
5224 const unsigned char ls
[16] =
5225 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5231 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5232 return ls
[size
- 1];
5235 /* Determine and return the real reloc type code for an instruction
5236 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5238 static inline bfd_reloc_code_real_type
5239 ldst_lo12_determine_real_reloc_type (void)
5242 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5243 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5245 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5247 BFD_RELOC_AARCH64_LDST8_LO12
,
5248 BFD_RELOC_AARCH64_LDST16_LO12
,
5249 BFD_RELOC_AARCH64_LDST32_LO12
,
5250 BFD_RELOC_AARCH64_LDST64_LO12
,
5251 BFD_RELOC_AARCH64_LDST128_LO12
5254 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5255 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5256 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5257 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5258 BFD_RELOC_AARCH64_NONE
5261 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5262 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5263 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5264 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5265 BFD_RELOC_AARCH64_NONE
5268 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5269 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5270 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5271 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5272 BFD_RELOC_AARCH64_NONE
5275 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5276 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5277 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5278 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5279 BFD_RELOC_AARCH64_NONE
5283 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5284 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5286 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5288 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5290 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5291 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5293 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5295 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5297 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5299 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5300 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5301 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5302 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5303 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5304 gas_assert (logsz
<= 3);
5306 gas_assert (logsz
<= 4);
5308 /* In reloc.c, these pseudo relocation types should be defined in similar
5309 order as above reloc_ldst_lo12 array. Because the array index calculation
5310 below relies on this. */
5311 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5314 /* Check whether a register list REGINFO is valid. The registers must be
5315 numbered in increasing order (modulo 32), in increments of one or two.
5317 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5320 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5323 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5325 uint32_t i
, nb_regs
, prev_regno
, incr
;
5327 nb_regs
= 1 + (reginfo
& 0x3);
5329 prev_regno
= reginfo
& 0x1f;
5330 incr
= accept_alternate
? 2 : 1;
5332 for (i
= 1; i
< nb_regs
; ++i
)
5334 uint32_t curr_regno
;
5336 curr_regno
= reginfo
& 0x1f;
5337 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5339 prev_regno
= curr_regno
;
5345 /* Generic instruction operand parser. This does no encoding and no
5346 semantic validation; it merely squirrels values away in the inst
5347 structure. Returns TRUE or FALSE depending on whether the
5348 specified grammar matched. */
5351 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5354 char *backtrack_pos
= 0;
5355 const enum aarch64_opnd
*operands
= opcode
->operands
;
5356 aarch64_reg_type imm_reg_type
;
5359 skip_whitespace (str
);
5361 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5362 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5364 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5366 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5369 const reg_entry
*reg
;
5370 int comma_skipped_p
= 0;
5371 aarch64_reg_type rtype
;
5372 struct vector_type_el vectype
;
5373 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5374 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5375 aarch64_reg_type reg_type
;
5377 DEBUG_TRACE ("parse operand %d", i
);
5379 /* Assign the operand code. */
5380 info
->type
= operands
[i
];
5382 if (optional_operand_p (opcode
, i
))
5384 /* Remember where we are in case we need to backtrack. */
5385 gas_assert (!backtrack_pos
);
5386 backtrack_pos
= str
;
5389 /* Expect comma between operands; the backtrack mechanism will take
5390 care of cases of omitted optional operand. */
5391 if (i
> 0 && ! skip_past_char (&str
, ','))
5393 set_syntax_error (_("comma expected between operands"));
5397 comma_skipped_p
= 1;
5399 switch (operands
[i
])
5401 case AARCH64_OPND_Rd
:
5402 case AARCH64_OPND_Rn
:
5403 case AARCH64_OPND_Rm
:
5404 case AARCH64_OPND_Rt
:
5405 case AARCH64_OPND_Rt2
:
5406 case AARCH64_OPND_Rs
:
5407 case AARCH64_OPND_Ra
:
5408 case AARCH64_OPND_Rt_SYS
:
5409 case AARCH64_OPND_PAIRREG
:
5410 case AARCH64_OPND_SVE_Rm
:
5411 po_int_reg_or_fail (REG_TYPE_R_Z
);
5414 case AARCH64_OPND_Rd_SP
:
5415 case AARCH64_OPND_Rn_SP
:
5416 case AARCH64_OPND_SVE_Rn_SP
:
5417 case AARCH64_OPND_Rm_SP
:
5418 po_int_reg_or_fail (REG_TYPE_R_SP
);
5421 case AARCH64_OPND_Rm_EXT
:
5422 case AARCH64_OPND_Rm_SFT
:
5423 po_misc_or_fail (parse_shifter_operand
5424 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5426 : SHIFTED_LOGIC_IMM
)));
5427 if (!info
->shifter
.operator_present
)
5429 /* Default to LSL if not present. Libopcodes prefers shifter
5430 kind to be explicit. */
5431 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5432 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5433 /* For Rm_EXT, libopcodes will carry out further check on whether
5434 or not stack pointer is used in the instruction (Recall that
5435 "the extend operator is not optional unless at least one of
5436 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5440 case AARCH64_OPND_Fd
:
5441 case AARCH64_OPND_Fn
:
5442 case AARCH64_OPND_Fm
:
5443 case AARCH64_OPND_Fa
:
5444 case AARCH64_OPND_Ft
:
5445 case AARCH64_OPND_Ft2
:
5446 case AARCH64_OPND_Sd
:
5447 case AARCH64_OPND_Sn
:
5448 case AARCH64_OPND_Sm
:
5449 case AARCH64_OPND_SVE_VZn
:
5450 case AARCH64_OPND_SVE_Vd
:
5451 case AARCH64_OPND_SVE_Vm
:
5452 case AARCH64_OPND_SVE_Vn
:
5453 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5454 if (val
== PARSE_FAIL
)
5456 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5459 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5461 info
->reg
.regno
= val
;
5462 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5465 case AARCH64_OPND_SVE_Pd
:
5466 case AARCH64_OPND_SVE_Pg3
:
5467 case AARCH64_OPND_SVE_Pg4_5
:
5468 case AARCH64_OPND_SVE_Pg4_10
:
5469 case AARCH64_OPND_SVE_Pg4_16
:
5470 case AARCH64_OPND_SVE_Pm
:
5471 case AARCH64_OPND_SVE_Pn
:
5472 case AARCH64_OPND_SVE_Pt
:
5473 reg_type
= REG_TYPE_PN
;
5476 case AARCH64_OPND_SVE_Za_5
:
5477 case AARCH64_OPND_SVE_Za_16
:
5478 case AARCH64_OPND_SVE_Zd
:
5479 case AARCH64_OPND_SVE_Zm_5
:
5480 case AARCH64_OPND_SVE_Zm_16
:
5481 case AARCH64_OPND_SVE_Zn
:
5482 case AARCH64_OPND_SVE_Zt
:
5483 reg_type
= REG_TYPE_ZN
;
5486 case AARCH64_OPND_Va
:
5487 case AARCH64_OPND_Vd
:
5488 case AARCH64_OPND_Vn
:
5489 case AARCH64_OPND_Vm
:
5490 reg_type
= REG_TYPE_VN
;
5492 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5493 if (val
== PARSE_FAIL
)
5495 first_error (_(get_reg_expected_msg (reg_type
)));
5498 if (vectype
.defined
& NTA_HASINDEX
)
5501 info
->reg
.regno
= val
;
5502 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5503 && vectype
.type
== NT_invtype
)
5504 /* Unqualified Pn and Zn registers are allowed in certain
5505 contexts. Rely on F_STRICT qualifier checking to catch
5507 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5510 info
->qualifier
= vectype_to_qualifier (&vectype
);
5511 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5516 case AARCH64_OPND_VdD1
:
5517 case AARCH64_OPND_VnD1
:
5518 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5519 if (val
== PARSE_FAIL
)
5521 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5524 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5526 set_fatal_syntax_error
5527 (_("the top half of a 128-bit FP/SIMD register is expected"));
5530 info
->reg
.regno
= val
;
5531 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5532 here; it is correct for the purpose of encoding/decoding since
5533 only the register number is explicitly encoded in the related
5534 instructions, although this appears a bit hacky. */
5535 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5538 case AARCH64_OPND_SVE_Zm3_INDEX
:
5539 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5540 case AARCH64_OPND_SVE_Zm4_INDEX
:
5541 case AARCH64_OPND_SVE_Zn_INDEX
:
5542 reg_type
= REG_TYPE_ZN
;
5543 goto vector_reg_index
;
5545 case AARCH64_OPND_Ed
:
5546 case AARCH64_OPND_En
:
5547 case AARCH64_OPND_Em
:
5548 case AARCH64_OPND_SM3_IMM2
:
5549 reg_type
= REG_TYPE_VN
;
5551 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5552 if (val
== PARSE_FAIL
)
5554 first_error (_(get_reg_expected_msg (reg_type
)));
5557 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5560 info
->reglane
.regno
= val
;
5561 info
->reglane
.index
= vectype
.index
;
5562 info
->qualifier
= vectype_to_qualifier (&vectype
);
5563 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5567 case AARCH64_OPND_SVE_ZnxN
:
5568 case AARCH64_OPND_SVE_ZtxN
:
5569 reg_type
= REG_TYPE_ZN
;
5570 goto vector_reg_list
;
5572 case AARCH64_OPND_LVn
:
5573 case AARCH64_OPND_LVt
:
5574 case AARCH64_OPND_LVt_AL
:
5575 case AARCH64_OPND_LEt
:
5576 reg_type
= REG_TYPE_VN
;
5578 if (reg_type
== REG_TYPE_ZN
5579 && get_opcode_dependent_value (opcode
) == 1
5582 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5583 if (val
== PARSE_FAIL
)
5585 first_error (_(get_reg_expected_msg (reg_type
)));
5588 info
->reglist
.first_regno
= val
;
5589 info
->reglist
.num_regs
= 1;
5593 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5594 if (val
== PARSE_FAIL
)
5596 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5598 set_fatal_syntax_error (_("invalid register list"));
5601 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5602 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5604 if (operands
[i
] == AARCH64_OPND_LEt
)
5606 if (!(vectype
.defined
& NTA_HASINDEX
))
5608 info
->reglist
.has_index
= 1;
5609 info
->reglist
.index
= vectype
.index
;
5613 if (vectype
.defined
& NTA_HASINDEX
)
5615 if (!(vectype
.defined
& NTA_HASTYPE
))
5617 if (reg_type
== REG_TYPE_ZN
)
5618 set_fatal_syntax_error (_("missing type suffix"));
5622 info
->qualifier
= vectype_to_qualifier (&vectype
);
5623 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5627 case AARCH64_OPND_CRn
:
5628 case AARCH64_OPND_CRm
:
5630 char prefix
= *(str
++);
5631 if (prefix
!= 'c' && prefix
!= 'C')
5634 po_imm_nc_or_fail ();
5637 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5640 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5641 info
->imm
.value
= val
;
5645 case AARCH64_OPND_SHLL_IMM
:
5646 case AARCH64_OPND_IMM_VLSR
:
5647 po_imm_or_fail (1, 64);
5648 info
->imm
.value
= val
;
5651 case AARCH64_OPND_CCMP_IMM
:
5652 case AARCH64_OPND_SIMM5
:
5653 case AARCH64_OPND_FBITS
:
5654 case AARCH64_OPND_UIMM4
:
5655 case AARCH64_OPND_UIMM3_OP1
:
5656 case AARCH64_OPND_UIMM3_OP2
:
5657 case AARCH64_OPND_IMM_VLSL
:
5658 case AARCH64_OPND_IMM
:
5659 case AARCH64_OPND_IMM_2
:
5660 case AARCH64_OPND_WIDTH
:
5661 case AARCH64_OPND_SVE_INV_LIMM
:
5662 case AARCH64_OPND_SVE_LIMM
:
5663 case AARCH64_OPND_SVE_LIMM_MOV
:
5664 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5665 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5666 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5667 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5668 case AARCH64_OPND_SVE_SIMM5
:
5669 case AARCH64_OPND_SVE_SIMM5B
:
5670 case AARCH64_OPND_SVE_SIMM6
:
5671 case AARCH64_OPND_SVE_SIMM8
:
5672 case AARCH64_OPND_SVE_UIMM3
:
5673 case AARCH64_OPND_SVE_UIMM7
:
5674 case AARCH64_OPND_SVE_UIMM8
:
5675 case AARCH64_OPND_SVE_UIMM8_53
:
5676 case AARCH64_OPND_IMM_ROT1
:
5677 case AARCH64_OPND_IMM_ROT2
:
5678 case AARCH64_OPND_IMM_ROT3
:
5679 case AARCH64_OPND_SVE_IMM_ROT1
:
5680 case AARCH64_OPND_SVE_IMM_ROT2
:
5681 po_imm_nc_or_fail ();
5682 info
->imm
.value
= val
;
5685 case AARCH64_OPND_SVE_AIMM
:
5686 case AARCH64_OPND_SVE_ASIMM
:
5687 po_imm_nc_or_fail ();
5688 info
->imm
.value
= val
;
5689 skip_whitespace (str
);
5690 if (skip_past_comma (&str
))
5691 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5693 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5696 case AARCH64_OPND_SVE_PATTERN
:
5697 po_enum_or_fail (aarch64_sve_pattern_array
);
5698 info
->imm
.value
= val
;
5701 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5702 po_enum_or_fail (aarch64_sve_pattern_array
);
5703 info
->imm
.value
= val
;
5704 if (skip_past_comma (&str
)
5705 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5707 if (!info
->shifter
.operator_present
)
5709 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5710 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5711 info
->shifter
.amount
= 1;
5715 case AARCH64_OPND_SVE_PRFOP
:
5716 po_enum_or_fail (aarch64_sve_prfop_array
);
5717 info
->imm
.value
= val
;
5720 case AARCH64_OPND_UIMM7
:
5721 po_imm_or_fail (0, 127);
5722 info
->imm
.value
= val
;
5725 case AARCH64_OPND_IDX
:
5726 case AARCH64_OPND_MASK
:
5727 case AARCH64_OPND_BIT_NUM
:
5728 case AARCH64_OPND_IMMR
:
5729 case AARCH64_OPND_IMMS
:
5730 po_imm_or_fail (0, 63);
5731 info
->imm
.value
= val
;
5734 case AARCH64_OPND_IMM0
:
5735 po_imm_nc_or_fail ();
5738 set_fatal_syntax_error (_("immediate zero expected"));
5741 info
->imm
.value
= 0;
5744 case AARCH64_OPND_FPIMM0
:
5747 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5748 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5749 it is probably not worth the effort to support it. */
5750 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5753 || !(res2
= parse_constant_immediate (&str
, &val
,
5756 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5758 info
->imm
.value
= 0;
5759 info
->imm
.is_fp
= 1;
5762 set_fatal_syntax_error (_("immediate zero expected"));
5766 case AARCH64_OPND_IMM_MOV
:
5769 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5770 reg_name_p (str
, REG_TYPE_VN
))
5773 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5775 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5776 later. fix_mov_imm_insn will try to determine a machine
5777 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5778 message if the immediate cannot be moved by a single
5780 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5781 inst
.base
.operands
[i
].skip
= 1;
5785 case AARCH64_OPND_SIMD_IMM
:
5786 case AARCH64_OPND_SIMD_IMM_SFT
:
5787 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5789 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5791 /* need_libopcodes_p */ 1,
5794 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5795 shift, we don't check it here; we leave the checking to
5796 the libopcodes (operand_general_constraint_met_p). By
5797 doing this, we achieve better diagnostics. */
5798 if (skip_past_comma (&str
)
5799 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5801 if (!info
->shifter
.operator_present
5802 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5804 /* Default to LSL if not present. Libopcodes prefers shifter
5805 kind to be explicit. */
5806 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5807 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5811 case AARCH64_OPND_FPIMM
:
5812 case AARCH64_OPND_SIMD_FPIMM
:
5813 case AARCH64_OPND_SVE_FPIMM8
:
5818 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5819 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5820 || !aarch64_imm_float_p (qfloat
))
5823 set_fatal_syntax_error (_("invalid floating-point"
5827 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5828 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5832 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5833 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5834 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5839 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5840 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5843 set_fatal_syntax_error (_("invalid floating-point"
5847 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5848 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5852 case AARCH64_OPND_LIMM
:
5853 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5854 SHIFTED_LOGIC_IMM
));
5855 if (info
->shifter
.operator_present
)
5857 set_fatal_syntax_error
5858 (_("shift not allowed for bitmask immediate"));
5861 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5863 /* need_libopcodes_p */ 1,
5867 case AARCH64_OPND_AIMM
:
5868 if (opcode
->op
== OP_ADD
)
5869 /* ADD may have relocation types. */
5870 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5871 SHIFTED_ARITH_IMM
));
5873 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5874 SHIFTED_ARITH_IMM
));
5875 switch (inst
.reloc
.type
)
5877 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5878 info
->shifter
.amount
= 12;
5880 case BFD_RELOC_UNUSED
:
5881 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5882 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5883 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5884 inst
.reloc
.pc_rel
= 0;
5889 info
->imm
.value
= 0;
5890 if (!info
->shifter
.operator_present
)
5892 /* Default to LSL if not present. Libopcodes prefers shifter
5893 kind to be explicit. */
5894 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5895 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5899 case AARCH64_OPND_HALF
:
5901 /* #<imm16> or relocation. */
5902 int internal_fixup_p
;
5903 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5904 if (internal_fixup_p
)
5905 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5906 skip_whitespace (str
);
5907 if (skip_past_comma (&str
))
5909 /* {, LSL #<shift>} */
5910 if (! aarch64_gas_internal_fixup_p ())
5912 set_fatal_syntax_error (_("can't mix relocation modifier "
5913 "with explicit shift"));
5916 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5919 inst
.base
.operands
[i
].shifter
.amount
= 0;
5920 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5921 inst
.base
.operands
[i
].imm
.value
= 0;
5922 if (! process_movw_reloc_info ())
5927 case AARCH64_OPND_EXCEPTION
:
5928 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5930 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5932 /* need_libopcodes_p */ 0,
5936 case AARCH64_OPND_NZCV
:
5938 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5942 info
->imm
.value
= nzcv
->value
;
5945 po_imm_or_fail (0, 15);
5946 info
->imm
.value
= val
;
5950 case AARCH64_OPND_COND
:
5951 case AARCH64_OPND_COND1
:
5956 while (ISALPHA (*str
));
5957 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
5958 if (info
->cond
== NULL
)
5960 set_syntax_error (_("invalid condition"));
5963 else if (operands
[i
] == AARCH64_OPND_COND1
5964 && (info
->cond
->value
& 0xe) == 0xe)
5966 /* Do not allow AL or NV. */
5967 set_default_error ();
5973 case AARCH64_OPND_ADDR_ADRP
:
5974 po_misc_or_fail (parse_adrp (&str
));
5975 /* Clear the value as operand needs to be relocated. */
5976 info
->imm
.value
= 0;
5979 case AARCH64_OPND_ADDR_PCREL14
:
5980 case AARCH64_OPND_ADDR_PCREL19
:
5981 case AARCH64_OPND_ADDR_PCREL21
:
5982 case AARCH64_OPND_ADDR_PCREL26
:
5983 po_misc_or_fail (parse_address (&str
, info
));
5984 if (!info
->addr
.pcrel
)
5986 set_syntax_error (_("invalid pc-relative address"));
5989 if (inst
.gen_lit_pool
5990 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5992 /* Only permit "=value" in the literal load instructions.
5993 The literal will be generated by programmer_friendly_fixup. */
5994 set_syntax_error (_("invalid use of \"=immediate\""));
5997 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5999 set_syntax_error (_("unrecognized relocation suffix"));
6002 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6004 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6005 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6009 info
->imm
.value
= 0;
6010 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6011 switch (opcode
->iclass
)
6015 /* e.g. CBZ or B.COND */
6016 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6017 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6021 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6022 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6026 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6028 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6029 : BFD_RELOC_AARCH64_JUMP26
;
6032 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6033 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6036 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6037 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6043 inst
.reloc
.pc_rel
= 1;
6047 case AARCH64_OPND_ADDR_SIMPLE
:
6048 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6050 /* [<Xn|SP>{, #<simm>}] */
6052 /* First use the normal address-parsing routines, to get
6053 the usual syntax errors. */
6054 po_misc_or_fail (parse_address (&str
, info
));
6055 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6056 || !info
->addr
.preind
|| info
->addr
.postind
6057 || info
->addr
.writeback
)
6059 set_syntax_error (_("invalid addressing mode"));
6063 /* Then retry, matching the specific syntax of these addresses. */
6065 po_char_or_fail ('[');
6066 po_reg_or_fail (REG_TYPE_R64_SP
);
6067 /* Accept optional ", #0". */
6068 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6069 && skip_past_char (&str
, ','))
6071 skip_past_char (&str
, '#');
6072 if (! skip_past_char (&str
, '0'))
6074 set_fatal_syntax_error
6075 (_("the optional immediate offset can only be 0"));
6079 po_char_or_fail (']');
6083 case AARCH64_OPND_ADDR_REGOFF
:
6084 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6085 po_misc_or_fail (parse_address (&str
, info
));
6087 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6088 || !info
->addr
.preind
|| info
->addr
.postind
6089 || info
->addr
.writeback
)
6091 set_syntax_error (_("invalid addressing mode"));
6094 if (!info
->shifter
.operator_present
)
6096 /* Default to LSL if not present. Libopcodes prefers shifter
6097 kind to be explicit. */
6098 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6099 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6101 /* Qualifier to be deduced by libopcodes. */
6104 case AARCH64_OPND_ADDR_SIMM7
:
6105 po_misc_or_fail (parse_address (&str
, info
));
6106 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6107 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6109 set_syntax_error (_("invalid addressing mode"));
6112 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6114 set_syntax_error (_("relocation not allowed"));
6117 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6119 /* need_libopcodes_p */ 1,
6123 case AARCH64_OPND_ADDR_SIMM9
:
6124 case AARCH64_OPND_ADDR_SIMM9_2
:
6125 po_misc_or_fail (parse_address (&str
, info
));
6126 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6127 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6128 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6129 && info
->addr
.writeback
))
6131 set_syntax_error (_("invalid addressing mode"));
6134 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6136 set_syntax_error (_("relocation not allowed"));
6139 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6141 /* need_libopcodes_p */ 1,
6145 case AARCH64_OPND_ADDR_SIMM10
:
6146 case AARCH64_OPND_ADDR_OFFSET
:
6147 po_misc_or_fail (parse_address (&str
, info
));
6148 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6149 || !info
->addr
.preind
|| info
->addr
.postind
)
6151 set_syntax_error (_("invalid addressing mode"));
6154 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6156 set_syntax_error (_("relocation not allowed"));
6159 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6161 /* need_libopcodes_p */ 1,
6165 case AARCH64_OPND_ADDR_UIMM12
:
6166 po_misc_or_fail (parse_address (&str
, info
));
6167 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6168 || !info
->addr
.preind
|| info
->addr
.writeback
)
6170 set_syntax_error (_("invalid addressing mode"));
6173 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6174 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6175 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6177 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6179 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6181 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6183 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6184 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6185 /* Leave qualifier to be determined by libopcodes. */
6188 case AARCH64_OPND_SIMD_ADDR_POST
:
6189 /* [<Xn|SP>], <Xm|#<amount>> */
6190 po_misc_or_fail (parse_address (&str
, info
));
6191 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6193 set_syntax_error (_("invalid addressing mode"));
6196 if (!info
->addr
.offset
.is_reg
)
6198 if (inst
.reloc
.exp
.X_op
== O_constant
)
6199 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6202 set_fatal_syntax_error
6203 (_("writeback value must be an immediate constant"));
6210 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6211 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6212 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6213 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6214 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6215 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6216 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6217 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6218 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6219 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6220 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6221 /* [X<n>{, #imm, MUL VL}]
6223 but recognizing SVE registers. */
6224 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6225 &offset_qualifier
));
6226 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6228 set_syntax_error (_("invalid addressing mode"));
6232 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6233 || !info
->addr
.preind
|| info
->addr
.writeback
)
6235 set_syntax_error (_("invalid addressing mode"));
6238 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6239 || inst
.reloc
.exp
.X_op
!= O_constant
)
6241 /* Make sure this has priority over
6242 "invalid addressing mode". */
6243 set_fatal_syntax_error (_("constant offset required"));
6246 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6249 case AARCH64_OPND_SVE_ADDR_R
:
6250 /* [<Xn|SP>{, <R><m>}]
6251 but recognizing SVE registers. */
6252 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6253 &offset_qualifier
));
6254 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6256 offset_qualifier
= AARCH64_OPND_QLF_X
;
6257 info
->addr
.offset
.is_reg
= 1;
6258 info
->addr
.offset
.regno
= 31;
6260 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6261 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6263 set_syntax_error (_("invalid addressing mode"));
6268 case AARCH64_OPND_SVE_ADDR_RR
:
6269 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6270 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6271 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6272 case AARCH64_OPND_SVE_ADDR_RX
:
6273 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6274 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6275 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6276 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6277 but recognizing SVE registers. */
6278 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6279 &offset_qualifier
));
6280 if (base_qualifier
!= AARCH64_OPND_QLF_X
6281 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6283 set_syntax_error (_("invalid addressing mode"));
6288 case AARCH64_OPND_SVE_ADDR_RZ
:
6289 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6290 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6291 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6292 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6293 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6294 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6295 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6296 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6297 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6298 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6299 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6300 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6301 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6302 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6303 &offset_qualifier
));
6304 if (base_qualifier
!= AARCH64_OPND_QLF_X
6305 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6306 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6308 set_syntax_error (_("invalid addressing mode"));
6311 info
->qualifier
= offset_qualifier
;
6314 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6315 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6316 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6317 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6318 /* [Z<n>.<T>{, #imm}] */
6319 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6320 &offset_qualifier
));
6321 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6322 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6324 set_syntax_error (_("invalid addressing mode"));
6327 info
->qualifier
= base_qualifier
;
6330 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6331 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6332 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6333 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6334 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6338 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6340 here since we get better error messages by leaving it to
6341 the qualifier checking routines. */
6342 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6343 &offset_qualifier
));
6344 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6345 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6346 || offset_qualifier
!= base_qualifier
)
6348 set_syntax_error (_("invalid addressing mode"));
6351 info
->qualifier
= base_qualifier
;
6354 case AARCH64_OPND_SYSREG
:
6356 uint32_t sysreg_flags
;
6357 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6358 &sysreg_flags
)) == PARSE_FAIL
)
6360 set_syntax_error (_("unknown or missing system register name"));
6363 inst
.base
.operands
[i
].sysreg
.value
= val
;
6364 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6368 case AARCH64_OPND_PSTATEFIELD
:
6369 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6372 set_syntax_error (_("unknown or missing PSTATE field name"));
6375 inst
.base
.operands
[i
].pstatefield
= val
;
6378 case AARCH64_OPND_SYSREG_IC
:
6379 inst
.base
.operands
[i
].sysins_op
=
6380 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6382 case AARCH64_OPND_SYSREG_DC
:
6383 inst
.base
.operands
[i
].sysins_op
=
6384 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6386 case AARCH64_OPND_SYSREG_AT
:
6387 inst
.base
.operands
[i
].sysins_op
=
6388 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6390 case AARCH64_OPND_SYSREG_TLBI
:
6391 inst
.base
.operands
[i
].sysins_op
=
6392 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6394 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6396 set_fatal_syntax_error ( _("unknown or missing operation name"));
6401 case AARCH64_OPND_BARRIER
:
6402 case AARCH64_OPND_BARRIER_ISB
:
6403 val
= parse_barrier (&str
);
6404 if (val
!= PARSE_FAIL
6405 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6407 /* ISB only accepts options name 'sy'. */
6409 (_("the specified option is not accepted in ISB"));
6410 /* Turn off backtrack as this optional operand is present. */
6414 /* This is an extension to accept a 0..15 immediate. */
6415 if (val
== PARSE_FAIL
)
6416 po_imm_or_fail (0, 15);
6417 info
->barrier
= aarch64_barrier_options
+ val
;
6420 case AARCH64_OPND_PRFOP
:
6421 val
= parse_pldop (&str
);
6422 /* This is an extension to accept a 0..31 immediate. */
6423 if (val
== PARSE_FAIL
)
6424 po_imm_or_fail (0, 31);
6425 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6428 case AARCH64_OPND_BARRIER_PSB
:
6429 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6430 if (val
== PARSE_FAIL
)
6435 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6438 /* If we get here, this operand was successfully parsed. */
6439 inst
.base
.operands
[i
].present
= 1;
6443 /* The parse routine should already have set the error, but in case
6444 not, set a default one here. */
6446 set_default_error ();
6448 if (! backtrack_pos
)
6449 goto parse_operands_return
;
6452 /* We reach here because this operand is marked as optional, and
6453 either no operand was supplied or the operand was supplied but it
6454 was syntactically incorrect. In the latter case we report an
6455 error. In the former case we perform a few more checks before
6456 dropping through to the code to insert the default operand. */
6458 char *tmp
= backtrack_pos
;
6459 char endchar
= END_OF_INSN
;
6461 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6463 skip_past_char (&tmp
, ',');
6465 if (*tmp
!= endchar
)
6466 /* The user has supplied an operand in the wrong format. */
6467 goto parse_operands_return
;
6469 /* Make sure there is not a comma before the optional operand.
6470 For example the fifth operand of 'sys' is optional:
6472 sys #0,c0,c0,#0, <--- wrong
6473 sys #0,c0,c0,#0 <--- correct. */
6474 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6476 set_fatal_syntax_error
6477 (_("unexpected comma before the omitted optional operand"));
6478 goto parse_operands_return
;
6482 /* Reaching here means we are dealing with an optional operand that is
6483 omitted from the assembly line. */
6484 gas_assert (optional_operand_p (opcode
, i
));
6486 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6488 /* Try again, skipping the optional operand at backtrack_pos. */
6489 str
= backtrack_pos
;
6492 /* Clear any error record after the omitted optional operand has been
6493 successfully handled. */
6497 /* Check if we have parsed all the operands. */
6498 if (*str
!= '\0' && ! error_p ())
6500 /* Set I to the index of the last present operand; this is
6501 for the purpose of diagnostics. */
6502 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6504 set_fatal_syntax_error
6505 (_("unexpected characters following instruction"));
6508 parse_operands_return
:
6512 DEBUG_TRACE ("parsing FAIL: %s - %s",
6513 operand_mismatch_kind_names
[get_error_kind ()],
6514 get_error_message ());
6515 /* Record the operand error properly; this is useful when there
6516 are multiple instruction templates for a mnemonic name, so that
6517 later on, we can select the error that most closely describes
6519 record_operand_error (opcode
, i
, get_error_kind (),
6520 get_error_message ());
6525 DEBUG_TRACE ("parsing SUCCESS");
6530 /* It does some fix-up to provide some programmer friendly feature while
6531 keeping the libopcodes happy, i.e. libopcodes only accepts
6532 the preferred architectural syntax.
6533 Return FALSE if there is any failure; otherwise return TRUE. */
6536 programmer_friendly_fixup (aarch64_instruction
*instr
)
6538 aarch64_inst
*base
= &instr
->base
;
6539 const aarch64_opcode
*opcode
= base
->opcode
;
6540 enum aarch64_op op
= opcode
->op
;
6541 aarch64_opnd_info
*operands
= base
->operands
;
6543 DEBUG_TRACE ("enter");
6545 switch (opcode
->iclass
)
6548 /* TBNZ Xn|Wn, #uimm6, label
6549 Test and Branch Not Zero: conditionally jumps to label if bit number
6550 uimm6 in register Xn is not zero. The bit number implies the width of
6551 the register, which may be written and should be disassembled as Wn if
6552 uimm is less than 32. */
6553 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6555 if (operands
[1].imm
.value
>= 32)
6557 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6561 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6565 /* LDR Wt, label | =value
6566 As a convenience assemblers will typically permit the notation
6567 "=value" in conjunction with the pc-relative literal load instructions
6568 to automatically place an immediate value or symbolic address in a
6569 nearby literal pool and generate a hidden label which references it.
6570 ISREG has been set to 0 in the case of =value. */
6571 if (instr
->gen_lit_pool
6572 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6574 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6575 if (op
== OP_LDRSW_LIT
)
6577 if (instr
->reloc
.exp
.X_op
!= O_constant
6578 && instr
->reloc
.exp
.X_op
!= O_big
6579 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6581 record_operand_error (opcode
, 1,
6582 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6583 _("constant expression expected"));
6586 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6588 record_operand_error (opcode
, 1,
6589 AARCH64_OPDE_OTHER_ERROR
,
6590 _("literal pool insertion failed"));
6598 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6599 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6600 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6601 A programmer-friendly assembler should accept a destination Xd in
6602 place of Wd, however that is not the preferred form for disassembly.
6604 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6605 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6606 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6607 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6612 /* In the 64-bit form, the final register operand is written as Wm
6613 for all but the (possibly omitted) UXTX/LSL and SXTX
6615 As a programmer-friendly assembler, we accept e.g.
6616 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6617 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6618 int idx
= aarch64_operand_index (opcode
->operands
,
6619 AARCH64_OPND_Rm_EXT
);
6620 gas_assert (idx
== 1 || idx
== 2);
6621 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6622 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6623 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6624 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6625 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6626 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6634 DEBUG_TRACE ("exit with SUCCESS");
6638 /* Check for loads and stores that will cause unpredictable behavior. */
6641 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6643 aarch64_inst
*base
= &instr
->base
;
6644 const aarch64_opcode
*opcode
= base
->opcode
;
6645 const aarch64_opnd_info
*opnds
= base
->operands
;
6646 switch (opcode
->iclass
)
6653 /* Loading/storing the base register is unpredictable if writeback. */
6654 if ((aarch64_get_operand_class (opnds
[0].type
)
6655 == AARCH64_OPND_CLASS_INT_REG
)
6656 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6657 && opnds
[1].addr
.base_regno
!= REG_SP
6658 && opnds
[1].addr
.writeback
)
6659 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6662 case ldstnapair_offs
:
6663 case ldstpair_indexed
:
6664 /* Loading/storing the base register is unpredictable if writeback. */
6665 if ((aarch64_get_operand_class (opnds
[0].type
)
6666 == AARCH64_OPND_CLASS_INT_REG
)
6667 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6668 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6669 && opnds
[2].addr
.base_regno
!= REG_SP
6670 && opnds
[2].addr
.writeback
)
6671 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6672 /* Load operations must load different registers. */
6673 if ((opcode
->opcode
& (1 << 22))
6674 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6675 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6682 /* A wrapper function to interface with libopcodes on encoding and
6683 record the error message if there is any.
6685 Return TRUE on success; otherwise return FALSE. */
6688 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6691 aarch64_operand_error error_info
;
6692 error_info
.kind
= AARCH64_OPDE_NIL
;
6693 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6697 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6698 record_operand_error_info (opcode
, &error_info
);
6703 #ifdef DEBUG_AARCH64
6705 dump_opcode_operands (const aarch64_opcode
*opcode
)
6708 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6710 aarch64_verbose ("\t\t opnd%d: %s", i
,
6711 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6712 ? aarch64_get_operand_name (opcode
->operands
[i
])
6713 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6717 #endif /* DEBUG_AARCH64 */
6719 /* This is the guts of the machine-dependent assembler. STR points to a
6720 machine dependent instruction. This function is supposed to emit
6721 the frags/bytes it assembles to. */
6724 md_assemble (char *str
)
6727 templates
*template;
6728 aarch64_opcode
*opcode
;
6729 aarch64_inst
*inst_base
;
6730 unsigned saved_cond
;
6732 /* Align the previous label if needed. */
6733 if (last_label_seen
!= NULL
)
6735 symbol_set_frag (last_label_seen
, frag_now
);
6736 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6737 S_SET_SEGMENT (last_label_seen
, now_seg
);
6740 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6742 DEBUG_TRACE ("\n\n");
6743 DEBUG_TRACE ("==============================");
6744 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6746 template = opcode_lookup (&p
);
6749 /* It wasn't an instruction, but it might be a register alias of
6750 the form alias .req reg directive. */
6751 if (!create_register_alias (str
, p
))
6752 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6757 skip_whitespace (p
);
6760 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6761 get_mnemonic_name (str
), str
);
6765 init_operand_error_report ();
6767 /* Sections are assumed to start aligned. In executable section, there is no
6768 MAP_DATA symbol pending. So we only align the address during
6769 MAP_DATA --> MAP_INSN transition.
6770 For other sections, this is not guaranteed. */
6771 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6772 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6773 frag_align_code (2, 0);
6775 saved_cond
= inst
.cond
;
6776 reset_aarch64_instruction (&inst
);
6777 inst
.cond
= saved_cond
;
6779 /* Iterate through all opcode entries with the same mnemonic name. */
6782 opcode
= template->opcode
;
6784 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6785 #ifdef DEBUG_AARCH64
6787 dump_opcode_operands (opcode
);
6788 #endif /* DEBUG_AARCH64 */
6790 mapping_state (MAP_INSN
);
6792 inst_base
= &inst
.base
;
6793 inst_base
->opcode
= opcode
;
6795 /* Truly conditionally executed instructions, e.g. b.cond. */
6796 if (opcode
->flags
& F_COND
)
6798 gas_assert (inst
.cond
!= COND_ALWAYS
);
6799 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6800 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6802 else if (inst
.cond
!= COND_ALWAYS
)
6804 /* It shouldn't arrive here, where the assembly looks like a
6805 conditional instruction but the found opcode is unconditional. */
6810 if (parse_operands (p
, opcode
)
6811 && programmer_friendly_fixup (&inst
)
6812 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6814 /* Check that this instruction is supported for this CPU. */
6815 if (!opcode
->avariant
6816 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6818 as_bad (_("selected processor does not support `%s'"), str
);
6822 warn_unpredictable_ldst (&inst
, str
);
6824 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6825 || !inst
.reloc
.need_libopcodes_p
)
6829 /* If there is relocation generated for the instruction,
6830 store the instruction information for the future fix-up. */
6831 struct aarch64_inst
*copy
;
6832 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6833 copy
= XNEW (struct aarch64_inst
);
6834 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6840 template = template->next
;
6841 if (template != NULL
)
6843 reset_aarch64_instruction (&inst
);
6844 inst
.cond
= saved_cond
;
6847 while (template != NULL
);
6849 /* Issue the error messages if any. */
6850 output_operand_error_report (str
);
6853 /* Various frobbings of labels and their addresses. */
6856 aarch64_start_line_hook (void)
6858 last_label_seen
= NULL
;
6862 aarch64_frob_label (symbolS
* sym
)
6864 last_label_seen
= sym
;
6866 dwarf2_emit_label (sym
);
6870 aarch64_data_in_code (void)
6872 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6874 *input_line_pointer
= '/';
6875 input_line_pointer
+= 5;
6876 *input_line_pointer
= 0;
6884 aarch64_canonicalize_symbol_name (char *name
)
6888 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6889 *(name
+ len
- 5) = 0;
6894 /* Table of all register names defined by default. The user can
6895 define additional names with .req. Note that all register names
6896 should appear in both upper and lowercase variants. Some registers
6897 also have mixed-case names. */
6899 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6900 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
6901 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6902 #define REGSET16(p,t) \
6903 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6904 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6905 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6906 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6907 #define REGSET31(p,t) \
6909 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6910 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6911 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6912 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6913 #define REGSET(p,t) \
6914 REGSET31(p,t), REGNUM(p,31,t)
6916 /* These go into aarch64_reg_hsh hash-table. */
6917 static const reg_entry reg_names
[] = {
6918 /* Integer registers. */
6919 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6920 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6922 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
6923 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
6924 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
6925 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
6926 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6927 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6929 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6930 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6932 /* Floating-point single precision registers. */
6933 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6935 /* Floating-point double precision registers. */
6936 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6938 /* Floating-point half precision registers. */
6939 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6941 /* Floating-point byte precision registers. */
6942 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6944 /* Floating-point quad precision registers. */
6945 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6947 /* FP/SIMD registers. */
6948 REGSET (v
, VN
), REGSET (V
, VN
),
6950 /* SVE vector registers. */
6951 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6953 /* SVE predicate registers. */
6954 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6972 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6973 static const asm_nzcv nzcv_names
[] = {
6974 {"nzcv", B (n
, z
, c
, v
)},
6975 {"nzcV", B (n
, z
, c
, V
)},
6976 {"nzCv", B (n
, z
, C
, v
)},
6977 {"nzCV", B (n
, z
, C
, V
)},
6978 {"nZcv", B (n
, Z
, c
, v
)},
6979 {"nZcV", B (n
, Z
, c
, V
)},
6980 {"nZCv", B (n
, Z
, C
, v
)},
6981 {"nZCV", B (n
, Z
, C
, V
)},
6982 {"Nzcv", B (N
, z
, c
, v
)},
6983 {"NzcV", B (N
, z
, c
, V
)},
6984 {"NzCv", B (N
, z
, C
, v
)},
6985 {"NzCV", B (N
, z
, C
, V
)},
6986 {"NZcv", B (N
, Z
, c
, v
)},
6987 {"NZcV", B (N
, Z
, c
, V
)},
6988 {"NZCv", B (N
, Z
, C
, v
)},
6989 {"NZCV", B (N
, Z
, C
, V
)}
7002 /* MD interface: bits in the object file. */
7004 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7005 for use in the a.out file, and stores them in the array pointed to by buf.
7006 This knows about the endian-ness of the target machine and does
7007 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7008 2 (short) and 4 (long) Floating numbers are put out as a series of
7009 LITTLENUMS (shorts, here at least). */
7012 md_number_to_chars (char *buf
, valueT val
, int n
)
7014 if (target_big_endian
)
7015 number_to_chars_bigendian (buf
, val
, n
);
7017 number_to_chars_littleendian (buf
, val
, n
);
7020 /* MD interface: Sections. */
7022 /* Estimate the size of a frag before relaxing. Assume everything fits in
7026 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7032 /* Round up a section size to the appropriate boundary. */
7035 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7040 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7041 of an rs_align_code fragment.
7043 Here we fill the frag with the appropriate info for padding the
7044 output stream. The resulting frag will consist of a fixed (fr_fix)
7045 and of a repeating (fr_var) part.
7047 The fixed content is always emitted before the repeating content and
7048 these two parts are used as follows in constructing the output:
7049 - the fixed part will be used to align to a valid instruction word
7050 boundary, in case that we start at a misaligned address; as no
7051 executable instruction can live at the misaligned location, we
7052 simply fill with zeros;
7053 - the variable part will be used to cover the remaining padding and
7054 we fill using the AArch64 NOP instruction.
7056 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7057 enough storage space for up to 3 bytes for padding the back to a valid
7058 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7061 aarch64_handle_align (fragS
* fragP
)
7063 /* NOP = d503201f */
7064 /* AArch64 instructions are always little-endian. */
7065 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7067 int bytes
, fix
, noop_size
;
7070 if (fragP
->fr_type
!= rs_align_code
)
7073 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7074 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7077 gas_assert (fragP
->tc_frag_data
.recorded
);
7080 noop_size
= sizeof (aarch64_noop
);
7082 fix
= bytes
& (noop_size
- 1);
7086 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7090 fragP
->fr_fix
+= fix
;
7094 memcpy (p
, aarch64_noop
, noop_size
);
7095 fragP
->fr_var
= noop_size
;
7098 /* Perform target specific initialisation of a frag.
7099 Note - despite the name this initialisation is not done when the frag
7100 is created, but only when its type is assigned. A frag can be created
7101 and used a long time before its type is set, so beware of assuming that
7102 this initialisation is performed first. */
7106 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7107 int max_chars ATTRIBUTE_UNUSED
)
7111 #else /* OBJ_ELF is defined. */
7113 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7115 /* Record a mapping symbol for alignment frags. We will delete this
7116 later if the alignment ends up empty. */
7117 if (!fragP
->tc_frag_data
.recorded
)
7118 fragP
->tc_frag_data
.recorded
= 1;
7120 /* PR 21809: Do not set a mapping state for debug sections
7121 - it just confuses other tools. */
7122 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7125 switch (fragP
->fr_type
)
7129 mapping_state_2 (MAP_DATA
, max_chars
);
7132 /* PR 20364: We can get alignment frags in code sections,
7133 so do not just assume that we should use the MAP_DATA state. */
7134 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7137 mapping_state_2 (MAP_INSN
, max_chars
);
7144 /* Initialize the DWARF-2 unwind information for this procedure. */
7147 tc_aarch64_frame_initial_instructions (void)
7149 cfi_add_CFA_def_cfa (REG_SP
, 0);
7151 #endif /* OBJ_ELF */
7153 /* Convert REGNAME to a DWARF-2 register number. */
7156 tc_aarch64_regname_to_dw2regnum (char *regname
)
7158 const reg_entry
*reg
= parse_reg (®name
);
7164 case REG_TYPE_SP_32
:
7165 case REG_TYPE_SP_64
:
7175 return reg
->number
+ 64;
7183 /* Implement DWARF2_ADDR_SIZE. */
7186 aarch64_dwarf2_addr_size (void)
7188 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7192 return bfd_arch_bits_per_address (stdoutput
) / 8;
7195 /* MD interface: Symbol and relocation handling. */
7197 /* Return the address within the segment that a PC-relative fixup is
7198 relative to. For AArch64 PC-relative fixups applied to instructions
7199 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7202 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7204 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7206 /* If this is pc-relative and we are going to emit a relocation
7207 then we just want to put out any pipeline compensation that the linker
7208 will need. Otherwise we want to use the calculated base. */
7210 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7211 || aarch64_force_relocation (fixP
)))
7214 /* AArch64 should be consistent for all pc-relative relocations. */
7215 return base
+ AARCH64_PCREL_OFFSET
;
7218 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7219 Otherwise we have no need to default values of symbols. */
7222 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7225 if (name
[0] == '_' && name
[1] == 'G'
7226 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7230 if (symbol_find (name
))
7231 as_bad (_("GOT already in the symbol table"));
7233 GOT_symbol
= symbol_new (name
, undefined_section
,
7234 (valueT
) 0, &zero_address_frag
);
7244 /* Return non-zero if the indicated VALUE has overflowed the maximum
7245 range expressible by a unsigned number with the indicated number of
7249 unsigned_overflow (valueT value
, unsigned bits
)
7252 if (bits
>= sizeof (valueT
) * 8)
7254 lim
= (valueT
) 1 << bits
;
7255 return (value
>= lim
);
7259 /* Return non-zero if the indicated VALUE has overflowed the maximum
7260 range expressible by an signed number with the indicated number of
7264 signed_overflow (offsetT value
, unsigned bits
)
7267 if (bits
>= sizeof (offsetT
) * 8)
7269 lim
= (offsetT
) 1 << (bits
- 1);
7270 return (value
< -lim
|| value
>= lim
);
7273 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7274 unsigned immediate offset load/store instruction, try to encode it as
7275 an unscaled, 9-bit, signed immediate offset load/store instruction.
7276 Return TRUE if it is successful; otherwise return FALSE.
7278 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7279 in response to the standard LDR/STR mnemonics when the immediate offset is
7280 unambiguous, i.e. when it is negative or unaligned. */
7283 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7286 enum aarch64_op new_op
;
7287 const aarch64_opcode
*new_opcode
;
7289 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7291 switch (instr
->opcode
->op
)
7293 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7294 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7295 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7296 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7297 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7298 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7299 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7300 case OP_STR_POS
: new_op
= OP_STUR
; break;
7301 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7302 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7303 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7304 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7305 default: new_op
= OP_NIL
; break;
7308 if (new_op
== OP_NIL
)
7311 new_opcode
= aarch64_get_opcode (new_op
);
7312 gas_assert (new_opcode
!= NULL
);
7314 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7315 instr
->opcode
->op
, new_opcode
->op
);
7317 aarch64_replace_opcode (instr
, new_opcode
);
7319 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7320 qualifier matching may fail because the out-of-date qualifier will
7321 prevent the operand being updated with a new and correct qualifier. */
7322 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7323 AARCH64_OPND_ADDR_SIMM9
);
7324 gas_assert (idx
== 1);
7325 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7327 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7329 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
7335 /* Called by fix_insn to fix a MOV immediate alias instruction.
7337 Operand for a generic move immediate instruction, which is an alias
7338 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7339 a 32-bit/64-bit immediate value into general register. An assembler error
7340 shall result if the immediate cannot be created by a single one of these
7341 instructions. If there is a choice, then to ensure reversability an
7342 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7345 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7347 const aarch64_opcode
*opcode
;
7349 /* Need to check if the destination is SP/ZR. The check has to be done
7350 before any aarch64_replace_opcode. */
7351 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7352 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7354 instr
->operands
[1].imm
.value
= value
;
7355 instr
->operands
[1].skip
= 0;
7359 /* Try the MOVZ alias. */
7360 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7361 aarch64_replace_opcode (instr
, opcode
);
7362 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7363 &instr
->value
, NULL
, NULL
))
7365 put_aarch64_insn (buf
, instr
->value
);
7368 /* Try the MOVK alias. */
7369 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7370 aarch64_replace_opcode (instr
, opcode
);
7371 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7372 &instr
->value
, NULL
, NULL
))
7374 put_aarch64_insn (buf
, instr
->value
);
7379 if (try_mov_bitmask_p
)
7381 /* Try the ORR alias. */
7382 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7383 aarch64_replace_opcode (instr
, opcode
);
7384 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7385 &instr
->value
, NULL
, NULL
))
7387 put_aarch64_insn (buf
, instr
->value
);
7392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7393 _("immediate cannot be moved by a single instruction"));
7396 /* An instruction operand which is immediate related may have symbol used
7397 in the assembly, e.g.
7400 .set u32, 0x00ffff00
7402 At the time when the assembly instruction is parsed, a referenced symbol,
7403 like 'u32' in the above example may not have been seen; a fixS is created
7404 in such a case and is handled here after symbols have been resolved.
7405 Instruction is fixed up with VALUE using the information in *FIXP plus
7406 extra information in FLAGS.
7408 This function is called by md_apply_fix to fix up instructions that need
7409 a fix-up described above but does not involve any linker-time relocation. */
7412 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7416 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7417 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7418 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7422 /* Now the instruction is about to be fixed-up, so the operand that
7423 was previously marked as 'ignored' needs to be unmarked in order
7424 to get the encoding done properly. */
7425 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7426 new_inst
->operands
[idx
].skip
= 0;
7429 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7433 case AARCH64_OPND_EXCEPTION
:
7434 if (unsigned_overflow (value
, 16))
7435 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7436 _("immediate out of range"));
7437 insn
= get_aarch64_insn (buf
);
7438 insn
|= encode_svc_imm (value
);
7439 put_aarch64_insn (buf
, insn
);
7442 case AARCH64_OPND_AIMM
:
7443 /* ADD or SUB with immediate.
7444 NOTE this assumes we come here with a add/sub shifted reg encoding
7445 3 322|2222|2 2 2 21111 111111
7446 1 098|7654|3 2 1 09876 543210 98765 43210
7447 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7448 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7449 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7450 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7452 3 322|2222|2 2 221111111111
7453 1 098|7654|3 2 109876543210 98765 43210
7454 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7455 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7456 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7457 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7458 Fields sf Rn Rd are already set. */
7459 insn
= get_aarch64_insn (buf
);
7463 insn
= reencode_addsub_switch_add_sub (insn
);
7467 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7468 && unsigned_overflow (value
, 12))
7470 /* Try to shift the value by 12 to make it fit. */
7471 if (((value
>> 12) << 12) == value
7472 && ! unsigned_overflow (value
, 12 + 12))
7475 insn
|= encode_addsub_imm_shift_amount (1);
7479 if (unsigned_overflow (value
, 12))
7480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7481 _("immediate out of range"));
7483 insn
|= encode_addsub_imm (value
);
7485 put_aarch64_insn (buf
, insn
);
7488 case AARCH64_OPND_SIMD_IMM
:
7489 case AARCH64_OPND_SIMD_IMM_SFT
:
7490 case AARCH64_OPND_LIMM
:
7491 /* Bit mask immediate. */
7492 gas_assert (new_inst
!= NULL
);
7493 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7494 new_inst
->operands
[idx
].imm
.value
= value
;
7495 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7496 &new_inst
->value
, NULL
, NULL
))
7497 put_aarch64_insn (buf
, new_inst
->value
);
7499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7500 _("invalid immediate"));
7503 case AARCH64_OPND_HALF
:
7504 /* 16-bit unsigned immediate. */
7505 if (unsigned_overflow (value
, 16))
7506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7507 _("immediate out of range"));
7508 insn
= get_aarch64_insn (buf
);
7509 insn
|= encode_movw_imm (value
& 0xffff);
7510 put_aarch64_insn (buf
, insn
);
7513 case AARCH64_OPND_IMM_MOV
:
7514 /* Operand for a generic move immediate instruction, which is
7515 an alias instruction that generates a single MOVZ, MOVN or ORR
7516 instruction to loads a 32-bit/64-bit immediate value into general
7517 register. An assembler error shall result if the immediate cannot be
7518 created by a single one of these instructions. If there is a choice,
7519 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7520 and MOVZ or MOVN to ORR. */
7521 gas_assert (new_inst
!= NULL
);
7522 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7525 case AARCH64_OPND_ADDR_SIMM7
:
7526 case AARCH64_OPND_ADDR_SIMM9
:
7527 case AARCH64_OPND_ADDR_SIMM9_2
:
7528 case AARCH64_OPND_ADDR_SIMM10
:
7529 case AARCH64_OPND_ADDR_UIMM12
:
7530 /* Immediate offset in an address. */
7531 insn
= get_aarch64_insn (buf
);
7533 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7534 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7535 || new_inst
->opcode
->operands
[2] == opnd
);
7537 /* Get the index of the address operand. */
7538 if (new_inst
->opcode
->operands
[1] == opnd
)
7539 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7542 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7545 /* Update the resolved offset value. */
7546 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7548 /* Encode/fix-up. */
7549 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7550 &new_inst
->value
, NULL
, NULL
))
7552 put_aarch64_insn (buf
, new_inst
->value
);
7555 else if (new_inst
->opcode
->iclass
== ldst_pos
7556 && try_to_encode_as_unscaled_ldst (new_inst
))
7558 put_aarch64_insn (buf
, new_inst
->value
);
7562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7563 _("immediate offset out of range"));
7568 as_fatal (_("unhandled operand code %d"), opnd
);
7572 /* Apply a fixup (fixP) to segment data, once it has been determined
7573 by our caller that we have all the info we need to fix it up.
7575 Parameter valP is the pointer to the value of the bits. */
7578 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7580 offsetT value
= *valP
;
7582 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7584 unsigned flags
= fixP
->fx_addnumber
;
7586 DEBUG_TRACE ("\n\n");
7587 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7588 DEBUG_TRACE ("Enter md_apply_fix");
7590 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7592 /* Note whether this will delete the relocation. */
7594 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7597 /* Process the relocations. */
7598 switch (fixP
->fx_r_type
)
7600 case BFD_RELOC_NONE
:
7601 /* This will need to go in the object file. */
7606 case BFD_RELOC_8_PCREL
:
7607 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7608 md_number_to_chars (buf
, value
, 1);
7612 case BFD_RELOC_16_PCREL
:
7613 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7614 md_number_to_chars (buf
, value
, 2);
7618 case BFD_RELOC_32_PCREL
:
7619 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7620 md_number_to_chars (buf
, value
, 4);
7624 case BFD_RELOC_64_PCREL
:
7625 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7626 md_number_to_chars (buf
, value
, 8);
7629 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7630 /* We claim that these fixups have been processed here, even if
7631 in fact we generate an error because we do not have a reloc
7632 for them, so tc_gen_reloc() will reject them. */
7634 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7637 _("undefined symbol %s used as an immediate value"),
7638 S_GET_NAME (fixP
->fx_addsy
));
7639 goto apply_fix_return
;
7641 fix_insn (fixP
, flags
, value
);
7644 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7645 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7649 _("pc-relative load offset not word aligned"));
7650 if (signed_overflow (value
, 21))
7651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7652 _("pc-relative load offset out of range"));
7653 insn
= get_aarch64_insn (buf
);
7654 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7655 put_aarch64_insn (buf
, insn
);
7659 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7660 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7662 if (signed_overflow (value
, 21))
7663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7664 _("pc-relative address offset out of range"));
7665 insn
= get_aarch64_insn (buf
);
7666 insn
|= encode_adr_imm (value
);
7667 put_aarch64_insn (buf
, insn
);
7671 case BFD_RELOC_AARCH64_BRANCH19
:
7672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7676 _("conditional branch target not word aligned"));
7677 if (signed_overflow (value
, 21))
7678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7679 _("conditional branch out of range"));
7680 insn
= get_aarch64_insn (buf
);
7681 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7682 put_aarch64_insn (buf
, insn
);
7686 case BFD_RELOC_AARCH64_TSTBR14
:
7687 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7691 _("conditional branch target not word aligned"));
7692 if (signed_overflow (value
, 16))
7693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7694 _("conditional branch out of range"));
7695 insn
= get_aarch64_insn (buf
);
7696 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7697 put_aarch64_insn (buf
, insn
);
7701 case BFD_RELOC_AARCH64_CALL26
:
7702 case BFD_RELOC_AARCH64_JUMP26
:
7703 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7707 _("branch target not word aligned"));
7708 if (signed_overflow (value
, 28))
7709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7710 _("branch out of range"));
7711 insn
= get_aarch64_insn (buf
);
7712 insn
|= encode_branch_ofs_26 (value
>> 2);
7713 put_aarch64_insn (buf
, insn
);
7717 case BFD_RELOC_AARCH64_MOVW_G0
:
7718 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7719 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7720 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7721 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7722 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7725 case BFD_RELOC_AARCH64_MOVW_G1
:
7726 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7727 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7728 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7729 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7730 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7733 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7735 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7736 /* Should always be exported to object file, see
7737 aarch64_force_relocation(). */
7738 gas_assert (!fixP
->fx_done
);
7739 gas_assert (seg
->use_rela_p
);
7741 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7743 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7744 /* Should always be exported to object file, see
7745 aarch64_force_relocation(). */
7746 gas_assert (!fixP
->fx_done
);
7747 gas_assert (seg
->use_rela_p
);
7749 case BFD_RELOC_AARCH64_MOVW_G2
:
7750 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7751 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7752 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7753 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7756 case BFD_RELOC_AARCH64_MOVW_G3
:
7757 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7760 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7762 insn
= get_aarch64_insn (buf
);
7766 /* REL signed addend must fit in 16 bits */
7767 if (signed_overflow (value
, 16))
7768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7769 _("offset out of range"));
7773 /* Check for overflow and scale. */
7774 switch (fixP
->fx_r_type
)
7776 case BFD_RELOC_AARCH64_MOVW_G0
:
7777 case BFD_RELOC_AARCH64_MOVW_G1
:
7778 case BFD_RELOC_AARCH64_MOVW_G2
:
7779 case BFD_RELOC_AARCH64_MOVW_G3
:
7780 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7781 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7782 if (unsigned_overflow (value
, scale
+ 16))
7783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7784 _("unsigned value out of range"));
7786 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7787 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7788 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7789 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7790 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7791 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7792 /* NOTE: We can only come here with movz or movn. */
7793 if (signed_overflow (value
, scale
+ 16))
7794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7795 _("signed value out of range"));
7798 /* Force use of MOVN. */
7800 insn
= reencode_movzn_to_movn (insn
);
7804 /* Force use of MOVZ. */
7805 insn
= reencode_movzn_to_movz (insn
);
7809 /* Unchecked relocations. */
7815 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7816 insn
|= encode_movw_imm (value
& 0xffff);
7818 put_aarch64_insn (buf
, insn
);
7822 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7823 fixP
->fx_r_type
= (ilp32_p
7824 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7825 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7826 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7827 /* Should always be exported to object file, see
7828 aarch64_force_relocation(). */
7829 gas_assert (!fixP
->fx_done
);
7830 gas_assert (seg
->use_rela_p
);
7833 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7834 fixP
->fx_r_type
= (ilp32_p
7835 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7836 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
7837 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7838 /* Should always be exported to object file, see
7839 aarch64_force_relocation(). */
7840 gas_assert (!fixP
->fx_done
);
7841 gas_assert (seg
->use_rela_p
);
7844 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
7845 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7846 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7847 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7848 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
7849 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7850 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7851 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7852 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7853 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7854 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7855 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7856 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7857 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7858 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7859 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7860 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7861 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7862 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7863 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7864 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7865 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7866 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7867 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7868 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7869 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7870 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7871 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7872 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7873 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7874 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7875 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7876 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7877 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7878 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7879 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7880 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
7881 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
7882 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
7883 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
7884 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
7885 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
7886 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
7887 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
7888 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7889 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7890 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7891 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7892 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7893 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7894 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7895 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7896 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7897 /* Should always be exported to object file, see
7898 aarch64_force_relocation(). */
7899 gas_assert (!fixP
->fx_done
);
7900 gas_assert (seg
->use_rela_p
);
7903 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7904 /* Should always be exported to object file, see
7905 aarch64_force_relocation(). */
7906 fixP
->fx_r_type
= (ilp32_p
7907 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7908 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7909 gas_assert (!fixP
->fx_done
);
7910 gas_assert (seg
->use_rela_p
);
7913 case BFD_RELOC_AARCH64_ADD_LO12
:
7914 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7915 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7916 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7917 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7918 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7919 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7920 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7921 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7922 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7923 case BFD_RELOC_AARCH64_LDST128_LO12
:
7924 case BFD_RELOC_AARCH64_LDST16_LO12
:
7925 case BFD_RELOC_AARCH64_LDST32_LO12
:
7926 case BFD_RELOC_AARCH64_LDST64_LO12
:
7927 case BFD_RELOC_AARCH64_LDST8_LO12
:
7928 /* Should always be exported to object file, see
7929 aarch64_force_relocation(). */
7930 gas_assert (!fixP
->fx_done
);
7931 gas_assert (seg
->use_rela_p
);
7934 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7935 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7936 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7939 case BFD_RELOC_UNUSED
:
7940 /* An error will already have been reported. */
7944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7945 _("unexpected %s fixup"),
7946 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7951 /* Free the allocated the struct aarch64_inst.
7952 N.B. currently there are very limited number of fix-up types actually use
7953 this field, so the impact on the performance should be minimal . */
7954 if (fixP
->tc_fix_data
.inst
!= NULL
)
7955 free (fixP
->tc_fix_data
.inst
);
7960 /* Translate internal representation of relocation info to BFD target
7964 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7967 bfd_reloc_code_real_type code
;
7969 reloc
= XNEW (arelent
);
7971 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7972 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7973 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7977 if (section
->use_rela_p
)
7978 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7980 fixp
->fx_offset
= reloc
->address
;
7982 reloc
->addend
= fixp
->fx_offset
;
7984 code
= fixp
->fx_r_type
;
7989 code
= BFD_RELOC_16_PCREL
;
7994 code
= BFD_RELOC_32_PCREL
;
7999 code
= BFD_RELOC_64_PCREL
;
8006 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8007 if (reloc
->howto
== NULL
)
8009 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8011 ("cannot represent %s relocation in this object file format"),
8012 bfd_get_reloc_code_name (code
));
8019 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8022 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8024 bfd_reloc_code_real_type type
;
8028 FIXME: @@ Should look at CPU word size. */
8035 type
= BFD_RELOC_16
;
8038 type
= BFD_RELOC_32
;
8041 type
= BFD_RELOC_64
;
8044 as_bad (_("cannot do %u-byte relocation"), size
);
8045 type
= BFD_RELOC_UNUSED
;
8049 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8053 aarch64_force_relocation (struct fix
*fixp
)
8055 switch (fixp
->fx_r_type
)
8057 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8058 /* Perform these "immediate" internal relocations
8059 even if the symbol is extern or weak. */
8062 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8063 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8064 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8065 /* Pseudo relocs that need to be fixed up according to
8069 case BFD_RELOC_AARCH64_ADD_LO12
:
8070 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8071 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8072 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8073 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8074 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8075 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8076 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8077 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8078 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8079 case BFD_RELOC_AARCH64_LDST128_LO12
:
8080 case BFD_RELOC_AARCH64_LDST16_LO12
:
8081 case BFD_RELOC_AARCH64_LDST32_LO12
:
8082 case BFD_RELOC_AARCH64_LDST64_LO12
:
8083 case BFD_RELOC_AARCH64_LDST8_LO12
:
8084 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8085 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8086 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8087 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8088 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8089 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8090 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8091 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8092 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8093 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8094 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8095 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8096 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8097 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8098 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8099 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8100 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8101 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8102 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8103 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8104 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8105 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8106 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8107 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8108 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8109 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8110 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8111 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8112 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8113 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8114 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8115 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8116 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8117 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8118 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8119 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8120 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8121 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8122 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8123 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8124 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8125 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8126 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8127 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8128 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8129 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8130 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8131 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8132 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8133 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8134 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8135 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8136 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8137 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8138 /* Always leave these relocations for the linker. */
8145 return generic_force_reloc (fixp
);
8150 /* Implement md_after_parse_args. This is the earliest time we need to decide
8151 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8154 aarch64_after_parse_args (void)
8156 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8159 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8160 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8161 aarch64_abi
= AARCH64_ABI_ILP32
;
8163 aarch64_abi
= AARCH64_ABI_LP64
;
8167 elf64_aarch64_target_format (void)
8169 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8171 /* FIXME: What to do for ilp32_p ? */
8172 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8174 if (target_big_endian
)
8175 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8177 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8181 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8183 elf_frob_symbol (symp
, puntp
);
8187 /* MD interface: Finalization. */
8189 /* A good place to do this, although this was probably not intended
8190 for this kind of use. We need to dump the literal pool before
8191 references are made to a null symbol pointer. */
8194 aarch64_cleanup (void)
8198 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8200 /* Put it at the end of the relevant section. */
8201 subseg_set (pool
->section
, pool
->sub_section
);
8207 /* Remove any excess mapping symbols generated for alignment frags in
8208 SEC. We may have created a mapping symbol before a zero byte
8209 alignment; remove it if there's a mapping symbol after the
8212 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8213 void *dummy ATTRIBUTE_UNUSED
)
8215 segment_info_type
*seginfo
= seg_info (sec
);
8218 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8221 for (fragp
= seginfo
->frchainP
->frch_root
;
8222 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8224 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8225 fragS
*next
= fragp
->fr_next
;
8227 /* Variable-sized frags have been converted to fixed size by
8228 this point. But if this was variable-sized to start with,
8229 there will be a fixed-size frag after it. So don't handle
8231 if (sym
== NULL
|| next
== NULL
)
8234 if (S_GET_VALUE (sym
) < next
->fr_address
)
8235 /* Not at the end of this frag. */
8237 know (S_GET_VALUE (sym
) == next
->fr_address
);
8241 if (next
->tc_frag_data
.first_map
!= NULL
)
8243 /* Next frag starts with a mapping symbol. Discard this
8245 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8249 if (next
->fr_next
== NULL
)
8251 /* This mapping symbol is at the end of the section. Discard
8253 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8254 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8258 /* As long as we have empty frags without any mapping symbols,
8260 /* If the next frag is non-empty and does not start with a
8261 mapping symbol, then this mapping symbol is required. */
8262 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8265 next
= next
->fr_next
;
8267 while (next
!= NULL
);
8272 /* Adjust the symbol table. */
8275 aarch64_adjust_symtab (void)
8278 /* Remove any overlapping mapping symbols generated by alignment frags. */
8279 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8280 /* Now do generic ELF adjustments. */
8281 elf_adjust_symtab ();
8286 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8288 const char *hash_err
;
8290 hash_err
= hash_insert (table
, key
, value
);
8292 printf ("Internal Error: Can't hash %s\n", key
);
8296 fill_instruction_hash_table (void)
8298 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8300 while (opcode
->name
!= NULL
)
8302 templates
*templ
, *new_templ
;
8303 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8305 new_templ
= XNEW (templates
);
8306 new_templ
->opcode
= opcode
;
8307 new_templ
->next
= NULL
;
8310 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8313 new_templ
->next
= templ
->next
;
8314 templ
->next
= new_templ
;
8321 convert_to_upper (char *dst
, const char *src
, size_t num
)
8324 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8325 *dst
= TOUPPER (*src
);
8329 /* Assume STR point to a lower-case string, allocate, convert and return
8330 the corresponding upper-case string. */
8331 static inline const char*
8332 get_upper_str (const char *str
)
8335 size_t len
= strlen (str
);
8336 ret
= XNEWVEC (char, len
+ 1);
8337 convert_to_upper (ret
, str
, len
);
8341 /* MD interface: Initialization. */
8349 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8350 || (aarch64_cond_hsh
= hash_new ()) == NULL
8351 || (aarch64_shift_hsh
= hash_new ()) == NULL
8352 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8353 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8354 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8355 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8356 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8357 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8358 || (aarch64_reg_hsh
= hash_new ()) == NULL
8359 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8360 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8361 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8362 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8363 as_fatal (_("virtual memory exhausted"));
8365 fill_instruction_hash_table ();
8367 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8368 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8369 (void *) (aarch64_sys_regs
+ i
));
8371 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8372 checked_hash_insert (aarch64_pstatefield_hsh
,
8373 aarch64_pstatefields
[i
].name
,
8374 (void *) (aarch64_pstatefields
+ i
));
8376 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8377 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8378 aarch64_sys_regs_ic
[i
].name
,
8379 (void *) (aarch64_sys_regs_ic
+ i
));
8381 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8382 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8383 aarch64_sys_regs_dc
[i
].name
,
8384 (void *) (aarch64_sys_regs_dc
+ i
));
8386 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8387 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8388 aarch64_sys_regs_at
[i
].name
,
8389 (void *) (aarch64_sys_regs_at
+ i
));
8391 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8392 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8393 aarch64_sys_regs_tlbi
[i
].name
,
8394 (void *) (aarch64_sys_regs_tlbi
+ i
));
8396 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8397 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8398 (void *) (reg_names
+ i
));
8400 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8401 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8402 (void *) (nzcv_names
+ i
));
8404 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8406 const char *name
= aarch64_operand_modifiers
[i
].name
;
8407 checked_hash_insert (aarch64_shift_hsh
, name
,
8408 (void *) (aarch64_operand_modifiers
+ i
));
8409 /* Also hash the name in the upper case. */
8410 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8411 (void *) (aarch64_operand_modifiers
+ i
));
8414 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8417 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8418 the same condition code. */
8419 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8421 const char *name
= aarch64_conds
[i
].names
[j
];
8424 checked_hash_insert (aarch64_cond_hsh
, name
,
8425 (void *) (aarch64_conds
+ i
));
8426 /* Also hash the name in the upper case. */
8427 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8428 (void *) (aarch64_conds
+ i
));
8432 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8434 const char *name
= aarch64_barrier_options
[i
].name
;
8435 /* Skip xx00 - the unallocated values of option. */
8438 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8439 (void *) (aarch64_barrier_options
+ i
));
8440 /* Also hash the name in the upper case. */
8441 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8442 (void *) (aarch64_barrier_options
+ i
));
8445 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8447 const char* name
= aarch64_prfops
[i
].name
;
8448 /* Skip the unallocated hint encodings. */
8451 checked_hash_insert (aarch64_pldop_hsh
, name
,
8452 (void *) (aarch64_prfops
+ i
));
8453 /* Also hash the name in the upper case. */
8454 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8455 (void *) (aarch64_prfops
+ i
));
8458 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8460 const char* name
= aarch64_hint_options
[i
].name
;
8462 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8463 (void *) (aarch64_hint_options
+ i
));
8464 /* Also hash the name in the upper case. */
8465 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8466 (void *) (aarch64_hint_options
+ i
));
8469 /* Set the cpu variant based on the command-line options. */
8471 mcpu_cpu_opt
= march_cpu_opt
;
8474 mcpu_cpu_opt
= &cpu_default
;
8476 cpu_variant
= *mcpu_cpu_opt
;
8478 /* Record the CPU type. */
8479 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8481 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8484 /* Command line processing. */
8486 const char *md_shortopts
= "m:";
8488 #ifdef AARCH64_BI_ENDIAN
8489 #define OPTION_EB (OPTION_MD_BASE + 0)
8490 #define OPTION_EL (OPTION_MD_BASE + 1)
8492 #if TARGET_BYTES_BIG_ENDIAN
8493 #define OPTION_EB (OPTION_MD_BASE + 0)
8495 #define OPTION_EL (OPTION_MD_BASE + 1)
8499 struct option md_longopts
[] = {
8501 {"EB", no_argument
, NULL
, OPTION_EB
},
8504 {"EL", no_argument
, NULL
, OPTION_EL
},
8506 {NULL
, no_argument
, NULL
, 0}
8509 size_t md_longopts_size
= sizeof (md_longopts
);
8511 struct aarch64_option_table
8513 const char *option
; /* Option name to match. */
8514 const char *help
; /* Help information. */
8515 int *var
; /* Variable to change. */
8516 int value
; /* What to change it to. */
8517 char *deprecated
; /* If non-null, print this message. */
8520 static struct aarch64_option_table aarch64_opts
[] = {
8521 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8522 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8524 #ifdef DEBUG_AARCH64
8525 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8526 #endif /* DEBUG_AARCH64 */
8527 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8529 {"mno-verbose-error", N_("do not output verbose error messages"),
8530 &verbose_error_p
, 0, NULL
},
8531 {NULL
, NULL
, NULL
, 0, NULL
}
8534 struct aarch64_cpu_option_table
8537 const aarch64_feature_set value
;
8538 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8540 const char *canonical_name
;
8543 /* This list should, at a minimum, contain all the cpu names
8544 recognized by GCC. */
8545 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8546 {"all", AARCH64_ANY
, NULL
},
8547 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8548 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8549 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8550 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8551 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8552 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8553 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8554 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8555 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8556 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8557 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8558 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8560 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8561 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8563 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8564 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8565 "Samsung Exynos M1"},
8566 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8567 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8568 | AARCH64_FEATURE_RDMA
),
8570 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8571 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8572 | AARCH64_FEATURE_RDMA
),
8573 "Qualcomm QDF24XX"},
8574 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_3
,
8575 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8576 "Qualcomm Saphira"},
8577 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8578 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8580 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8581 AARCH64_FEATURE_CRYPTO
),
8583 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8584 in earlier releases and is superseded by 'xgene1' in all
8586 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8587 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8588 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8589 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8590 {"generic", AARCH64_ARCH_V8
, NULL
},
8592 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8595 struct aarch64_arch_option_table
8598 const aarch64_feature_set value
;
8601 /* This list should, at a minimum, contain all the architecture names
8602 recognized by GCC. */
8603 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8604 {"all", AARCH64_ANY
},
8605 {"armv8-a", AARCH64_ARCH_V8
},
8606 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8607 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8608 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8609 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8610 {NULL
, AARCH64_ARCH_NONE
}
8613 /* ISA extensions. */
8614 struct aarch64_option_cpu_value_table
8617 const aarch64_feature_set value
;
8618 const aarch64_feature_set require
; /* Feature dependencies. */
8621 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8622 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8624 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8625 | AARCH64_FEATURE_AES
8626 | AARCH64_FEATURE_SHA2
, 0),
8627 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8628 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8630 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8632 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8633 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8634 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8636 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8638 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8640 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8641 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8642 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8643 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8644 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8645 AARCH64_FEATURE (AARCH64_FEATURE_FP
8646 | AARCH64_FEATURE_F16
, 0)},
8647 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8649 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8650 AARCH64_FEATURE (AARCH64_FEATURE_F16
8651 | AARCH64_FEATURE_SIMD
8652 | AARCH64_FEATURE_COMPNUM
, 0)},
8653 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8654 AARCH64_FEATURE (AARCH64_FEATURE_F16
8655 | AARCH64_FEATURE_SIMD
, 0)},
8656 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8658 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8660 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8662 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8664 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8666 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8667 | AARCH64_FEATURE_SHA3
, 0),
8669 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8672 struct aarch64_long_option_table
8674 const char *option
; /* Substring to match. */
8675 const char *help
; /* Help information. */
8676 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8677 char *deprecated
; /* If non-null, print this message. */
8680 /* Transitive closure of features depending on set. */
8681 static aarch64_feature_set
8682 aarch64_feature_disable_set (aarch64_feature_set set
)
8684 const struct aarch64_option_cpu_value_table
*opt
;
8685 aarch64_feature_set prev
= 0;
8687 while (prev
!= set
) {
8689 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8690 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8691 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8696 /* Transitive closure of dependencies of set. */
8697 static aarch64_feature_set
8698 aarch64_feature_enable_set (aarch64_feature_set set
)
8700 const struct aarch64_option_cpu_value_table
*opt
;
8701 aarch64_feature_set prev
= 0;
8703 while (prev
!= set
) {
8705 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8706 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8707 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8713 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8714 bfd_boolean ext_only
)
8716 /* We insist on extensions being added before being removed. We achieve
8717 this by using the ADDING_VALUE variable to indicate whether we are
8718 adding an extension (1) or removing it (0) and only allowing it to
8719 change in the order -1 -> 1 -> 0. */
8720 int adding_value
= -1;
8721 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8723 /* Copy the feature set, so that we can modify it. */
8727 while (str
!= NULL
&& *str
!= 0)
8729 const struct aarch64_option_cpu_value_table
*opt
;
8730 const char *ext
= NULL
;
8737 as_bad (_("invalid architectural extension"));
8741 ext
= strchr (++str
, '+');
8747 optlen
= strlen (str
);
8749 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8751 if (adding_value
!= 0)
8756 else if (optlen
> 0)
8758 if (adding_value
== -1)
8760 else if (adding_value
!= 1)
8762 as_bad (_("must specify extensions to add before specifying "
8763 "those to remove"));
8770 as_bad (_("missing architectural extension"));
8774 gas_assert (adding_value
!= -1);
8776 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8777 if (strncmp (opt
->name
, str
, optlen
) == 0)
8779 aarch64_feature_set set
;
8781 /* Add or remove the extension. */
8784 set
= aarch64_feature_enable_set (opt
->value
);
8785 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8789 set
= aarch64_feature_disable_set (opt
->value
);
8790 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8795 if (opt
->name
== NULL
)
8797 as_bad (_("unknown architectural extension `%s'"), str
);
8808 aarch64_parse_cpu (const char *str
)
8810 const struct aarch64_cpu_option_table
*opt
;
8811 const char *ext
= strchr (str
, '+');
8817 optlen
= strlen (str
);
8821 as_bad (_("missing cpu name `%s'"), str
);
8825 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8826 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8828 mcpu_cpu_opt
= &opt
->value
;
8830 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8835 as_bad (_("unknown cpu `%s'"), str
);
8840 aarch64_parse_arch (const char *str
)
8842 const struct aarch64_arch_option_table
*opt
;
8843 const char *ext
= strchr (str
, '+');
8849 optlen
= strlen (str
);
8853 as_bad (_("missing architecture name `%s'"), str
);
8857 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8858 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8860 march_cpu_opt
= &opt
->value
;
8862 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8867 as_bad (_("unknown architecture `%s'\n"), str
);
8872 struct aarch64_option_abi_value_table
8875 enum aarch64_abi_type value
;
8878 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8879 {"ilp32", AARCH64_ABI_ILP32
},
8880 {"lp64", AARCH64_ABI_LP64
},
8884 aarch64_parse_abi (const char *str
)
8890 as_bad (_("missing abi name `%s'"), str
);
8894 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8895 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8897 aarch64_abi
= aarch64_abis
[i
].value
;
8901 as_bad (_("unknown abi `%s'\n"), str
);
8905 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8907 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8908 aarch64_parse_abi
, NULL
},
8909 #endif /* OBJ_ELF */
8910 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8911 aarch64_parse_cpu
, NULL
},
8912 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8913 aarch64_parse_arch
, NULL
},
8914 {NULL
, NULL
, 0, NULL
}
8918 md_parse_option (int c
, const char *arg
)
8920 struct aarch64_option_table
*opt
;
8921 struct aarch64_long_option_table
*lopt
;
8927 target_big_endian
= 1;
8933 target_big_endian
= 0;
8938 /* Listing option. Just ignore these, we don't support additional
8943 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8945 if (c
== opt
->option
[0]
8946 && ((arg
== NULL
&& opt
->option
[1] == 0)
8947 || streq (arg
, opt
->option
+ 1)))
8949 /* If the option is deprecated, tell the user. */
8950 if (opt
->deprecated
!= NULL
)
8951 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8952 arg
? arg
: "", _(opt
->deprecated
));
8954 if (opt
->var
!= NULL
)
8955 *opt
->var
= opt
->value
;
8961 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8963 /* These options are expected to have an argument. */
8964 if (c
== lopt
->option
[0]
8966 && strncmp (arg
, lopt
->option
+ 1,
8967 strlen (lopt
->option
+ 1)) == 0)
8969 /* If the option is deprecated, tell the user. */
8970 if (lopt
->deprecated
!= NULL
)
8971 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8972 _(lopt
->deprecated
));
8974 /* Call the sup-option parser. */
8975 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8986 md_show_usage (FILE * fp
)
8988 struct aarch64_option_table
*opt
;
8989 struct aarch64_long_option_table
*lopt
;
8991 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8993 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8994 if (opt
->help
!= NULL
)
8995 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8997 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8998 if (lopt
->help
!= NULL
)
8999 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9003 -EB assemble code for a big-endian cpu\n"));
9008 -EL assemble code for a little-endian cpu\n"));
9012 /* Parse a .cpu directive. */
9015 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9017 const struct aarch64_cpu_option_table
*opt
;
9023 name
= input_line_pointer
;
9024 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9025 input_line_pointer
++;
9026 saved_char
= *input_line_pointer
;
9027 *input_line_pointer
= 0;
9029 ext
= strchr (name
, '+');
9032 optlen
= ext
- name
;
9034 optlen
= strlen (name
);
9036 /* Skip the first "all" entry. */
9037 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9038 if (strlen (opt
->name
) == optlen
9039 && strncmp (name
, opt
->name
, optlen
) == 0)
9041 mcpu_cpu_opt
= &opt
->value
;
9043 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9046 cpu_variant
= *mcpu_cpu_opt
;
9048 *input_line_pointer
= saved_char
;
9049 demand_empty_rest_of_line ();
9052 as_bad (_("unknown cpu `%s'"), name
);
9053 *input_line_pointer
= saved_char
;
9054 ignore_rest_of_line ();
9058 /* Parse a .arch directive. */
9061 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9063 const struct aarch64_arch_option_table
*opt
;
9069 name
= input_line_pointer
;
9070 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9071 input_line_pointer
++;
9072 saved_char
= *input_line_pointer
;
9073 *input_line_pointer
= 0;
9075 ext
= strchr (name
, '+');
9078 optlen
= ext
- name
;
9080 optlen
= strlen (name
);
9082 /* Skip the first "all" entry. */
9083 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9084 if (strlen (opt
->name
) == optlen
9085 && strncmp (name
, opt
->name
, optlen
) == 0)
9087 mcpu_cpu_opt
= &opt
->value
;
9089 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9092 cpu_variant
= *mcpu_cpu_opt
;
9094 *input_line_pointer
= saved_char
;
9095 demand_empty_rest_of_line ();
9099 as_bad (_("unknown architecture `%s'\n"), name
);
9100 *input_line_pointer
= saved_char
;
9101 ignore_rest_of_line ();
9104 /* Parse a .arch_extension directive. */
9107 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9110 char *ext
= input_line_pointer
;;
9112 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9113 input_line_pointer
++;
9114 saved_char
= *input_line_pointer
;
9115 *input_line_pointer
= 0;
9117 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9120 cpu_variant
= *mcpu_cpu_opt
;
9122 *input_line_pointer
= saved_char
;
9123 demand_empty_rest_of_line ();
9126 /* Copy symbol information. */
9129 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9131 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);