1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Number of littlenums required to hold an extended precision number. */
242 #define MAX_LITTLENUMS 6
244 /* Return value for certain parsers when the parsing fails; those parsers
245 return the information of the parsed result, e.g. register number, on
247 #define PARSE_FAIL -1
249 /* This is an invalid condition code that means no conditional field is
251 #define COND_ALWAYS 0x10
255 const char *template;
261 const char *template;
268 bfd_reloc_code_real_type reloc
;
271 /* Macros to define the register types and masks for the purpose
274 #undef AARCH64_REG_TYPES
275 #define AARCH64_REG_TYPES \
276 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
277 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
278 BASIC_REG_TYPE(SP_32) /* wsp */ \
279 BASIC_REG_TYPE(SP_64) /* sp */ \
280 BASIC_REG_TYPE(Z_32) /* wzr */ \
281 BASIC_REG_TYPE(Z_64) /* xzr */ \
282 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
283 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
284 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
285 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
286 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
287 BASIC_REG_TYPE(VN) /* v[0-31] */ \
288 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
289 BASIC_REG_TYPE(PN) /* p[0-15] */ \
290 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
291 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
292 /* Typecheck: same, plus SVE registers. */ \
293 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
295 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
296 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
302 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
303 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
305 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
306 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Typecheck: any [BHSDQ]P FP. */ \
310 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
311 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
312 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
313 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
315 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
318 be used for SVE instructions, since Zn and Pn are valid symbols \
319 in other contexts. */ \
320 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
322 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
323 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
325 | REG_TYPE(ZN) | REG_TYPE(PN)) \
326 /* Any integer register; used for error messages only. */ \
327 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
329 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
330 /* Pseudo type to mark the end of the enumerator sequence. */ \
333 #undef BASIC_REG_TYPE
334 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
335 #undef MULTI_REG_TYPE
336 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
338 /* Register type enumerators. */
339 typedef enum aarch64_reg_type_
341 /* A list of REG_TYPE_*. */
345 #undef BASIC_REG_TYPE
346 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
348 #define REG_TYPE(T) (1 << REG_TYPE_##T)
349 #undef MULTI_REG_TYPE
350 #define MULTI_REG_TYPE(T,V) V,
352 /* Structure for a hash table entry for a register. */
356 unsigned char number
;
357 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
358 unsigned char builtin
;
361 /* Values indexed by aarch64_reg_type to assist the type checking. */
362 static const unsigned reg_type_masks
[] =
367 #undef BASIC_REG_TYPE
369 #undef MULTI_REG_TYPE
370 #undef AARCH64_REG_TYPES
372 /* Diagnostics used when we don't get a register of the expected type.
373 Note: this has to synchronized with aarch64_reg_type definitions
376 get_reg_expected_msg (aarch64_reg_type reg_type
)
383 msg
= N_("integer 32-bit register expected");
386 msg
= N_("integer 64-bit register expected");
389 msg
= N_("integer register expected");
391 case REG_TYPE_R64_SP
:
392 msg
= N_("64-bit integer or SP register expected");
394 case REG_TYPE_SVE_BASE
:
395 msg
= N_("base register expected");
398 msg
= N_("integer or zero register expected");
400 case REG_TYPE_SVE_OFFSET
:
401 msg
= N_("offset register expected");
404 msg
= N_("integer or SP register expected");
406 case REG_TYPE_R_Z_SP
:
407 msg
= N_("integer, zero or SP register expected");
410 msg
= N_("8-bit SIMD scalar register expected");
413 msg
= N_("16-bit SIMD scalar or floating-point half precision "
414 "register expected");
417 msg
= N_("32-bit SIMD scalar or floating-point single precision "
418 "register expected");
421 msg
= N_("64-bit SIMD scalar or floating-point double precision "
422 "register expected");
425 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
426 "register expected");
428 case REG_TYPE_R_Z_BHSDQ_V
:
429 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
430 msg
= N_("register expected");
432 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
433 msg
= N_("SIMD scalar or floating-point register expected");
435 case REG_TYPE_VN
: /* any V reg */
436 msg
= N_("vector register expected");
439 msg
= N_("SVE vector register expected");
442 msg
= N_("SVE predicate register expected");
445 as_fatal (_("invalid register type %d"), reg_type
);
450 /* Some well known registers that we refer to directly elsewhere. */
453 /* Instructions take 4 bytes in the object file. */
456 static struct hash_control
*aarch64_ops_hsh
;
457 static struct hash_control
*aarch64_cond_hsh
;
458 static struct hash_control
*aarch64_shift_hsh
;
459 static struct hash_control
*aarch64_sys_regs_hsh
;
460 static struct hash_control
*aarch64_pstatefield_hsh
;
461 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
462 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
463 static struct hash_control
*aarch64_sys_regs_at_hsh
;
464 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
465 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
466 static struct hash_control
*aarch64_reg_hsh
;
467 static struct hash_control
*aarch64_barrier_opt_hsh
;
468 static struct hash_control
*aarch64_nzcv_hsh
;
469 static struct hash_control
*aarch64_pldop_hsh
;
470 static struct hash_control
*aarch64_hint_opt_hsh
;
472 /* Stuff needed to resolve the label ambiguity
481 static symbolS
*last_label_seen
;
483 /* Literal pool structure. Held on a per-section
484 and per-sub-section basis. */
486 #define MAX_LITERAL_POOL_SIZE 1024
487 typedef struct literal_expression
490 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
491 LITTLENUM_TYPE
* bignum
;
492 } literal_expression
;
494 typedef struct literal_pool
496 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
497 unsigned int next_free_entry
;
503 struct literal_pool
*next
;
506 /* Pointer to a linked list of literal pools. */
507 static literal_pool
*list_of_pools
= NULL
;
511 /* This array holds the chars that always start a comment. If the
512 pre-processor is disabled, these aren't very useful. */
513 const char comment_chars
[] = "";
515 /* This array holds the chars that only start a comment at the beginning of
516 a line. If the line seems to have the form '# 123 filename'
517 .line and .file directives will appear in the pre-processed output. */
518 /* Note that input_file.c hand checks for '#' at the beginning of the
519 first line of the input file. This is because the compiler outputs
520 #NO_APP at the beginning of its output. */
521 /* Also note that comments like this one will always work. */
522 const char line_comment_chars
[] = "#";
524 const char line_separator_chars
[] = ";";
526 /* Chars that can be used to separate mant
527 from exp in floating point numbers. */
528 const char EXP_CHARS
[] = "eE";
530 /* Chars that mean this number is a floating point constant. */
534 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
536 /* Prefix character that indicates the start of an immediate value. */
537 #define is_immediate_prefix(C) ((C) == '#')
539 /* Separator character handling. */
541 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543 static inline bfd_boolean
544 skip_past_char (char **str
, char c
)
555 #define skip_past_comma(str) skip_past_char (str, ',')
557 /* Arithmetic expressions (possibly involving symbols). */
559 static bfd_boolean in_my_get_expression_p
= FALSE
;
561 /* Third argument to my_get_expression. */
562 #define GE_NO_PREFIX 0
563 #define GE_OPT_PREFIX 1
565 /* Return TRUE if the string pointed by *STR is successfully parsed
566 as an valid expression; *EP will be filled with the information of
567 such an expression. Otherwise return FALSE. */
570 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
575 int prefix_present_p
= 0;
582 if (is_immediate_prefix (**str
))
585 prefix_present_p
= 1;
592 memset (ep
, 0, sizeof (expressionS
));
594 save_in
= input_line_pointer
;
595 input_line_pointer
= *str
;
596 in_my_get_expression_p
= TRUE
;
597 seg
= expression (ep
);
598 in_my_get_expression_p
= FALSE
;
600 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
602 /* We found a bad expression in md_operand(). */
603 *str
= input_line_pointer
;
604 input_line_pointer
= save_in
;
605 if (prefix_present_p
&& ! error_p ())
606 set_fatal_syntax_error (_("bad expression"));
608 set_first_syntax_error (_("bad expression"));
613 if (seg
!= absolute_section
614 && seg
!= text_section
615 && seg
!= data_section
616 && seg
!= bss_section
&& seg
!= undefined_section
)
618 set_syntax_error (_("bad segment"));
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
627 *str
= input_line_pointer
;
628 input_line_pointer
= save_in
;
632 /* Turn a string in input_line_pointer into a floating point constant
633 of type TYPE, and store the appropriate bytes in *LITP. The number
634 of LITTLENUMS emitted is stored in *SIZEP. An error message is
635 returned, or NULL on OK. */
638 md_atof (int type
, char *litP
, int *sizeP
)
640 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
643 /* We handle all bad expressions here, so that we can report the faulty
644 instruction in the error message. */
646 md_operand (expressionS
* exp
)
648 if (in_my_get_expression_p
)
649 exp
->X_op
= O_illegal
;
652 /* Immediate values. */
654 /* Errors may be set multiple times during parsing or bit encoding
655 (particularly in the Neon bits), but usually the earliest error which is set
656 will be the most meaningful. Avoid overwriting it with later (cascading)
657 errors by calling this function. */
660 first_error (const char *error
)
663 set_syntax_error (error
);
666 /* Similar to first_error, but this function accepts formatted error
669 first_error_fmt (const char *format
, ...)
674 /* N.B. this single buffer will not cause error messages for different
675 instructions to pollute each other; this is because at the end of
676 processing of each assembly line, error message if any will be
677 collected by as_bad. */
678 static char buffer
[size
];
682 int ret ATTRIBUTE_UNUSED
;
683 va_start (args
, format
);
684 ret
= vsnprintf (buffer
, size
, format
, args
);
685 know (ret
<= size
- 1 && ret
>= 0);
687 set_syntax_error (buffer
);
691 /* Register parsing. */
693 /* Generic register parser which is called by other specialized
695 CCP points to what should be the beginning of a register name.
696 If it is indeed a valid register name, advance CCP over it and
697 return the reg_entry structure; otherwise return NULL.
698 It does not issue diagnostics. */
701 parse_reg (char **ccp
)
707 #ifdef REGISTER_PREFIX
708 if (*start
!= REGISTER_PREFIX
)
714 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
719 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
721 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
730 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
733 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
735 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
738 /* Try to parse a base or offset register. Allow SVE base and offset
739 registers if REG_TYPE includes SVE registers. Return the register
740 entry on success, setting *QUALIFIER to the register qualifier.
741 Return null otherwise.
743 Note that this function does not issue any diagnostics. */
745 static const reg_entry
*
746 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
747 aarch64_opnd_qualifier_t
*qualifier
)
750 const reg_entry
*reg
= parse_reg (&str
);
760 *qualifier
= AARCH64_OPND_QLF_W
;
766 *qualifier
= AARCH64_OPND_QLF_X
;
770 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
773 switch (TOLOWER (str
[1]))
776 *qualifier
= AARCH64_OPND_QLF_S_S
;
779 *qualifier
= AARCH64_OPND_QLF_S_D
;
796 /* Try to parse a base or offset register. Return the register entry
797 on success, setting *QUALIFIER to the register qualifier. Return null
800 Note that this function does not issue any diagnostics. */
802 static const reg_entry
*
803 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
805 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
808 /* Parse the qualifier of a vector register or vector element of type
809 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
810 succeeds; otherwise return FALSE.
812 Accept only one occurrence of:
813 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
816 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
817 struct vector_type_el
*parsed_type
, char **str
)
821 unsigned element_size
;
822 enum vector_el_type type
;
825 gas_assert (*ptr
== '.');
828 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
833 width
= strtoul (ptr
, &ptr
, 10);
834 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
836 first_error_fmt (_("bad size %d in vector width specifier"), width
);
841 switch (TOLOWER (*ptr
))
860 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
869 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
871 first_error (_("missing element size"));
874 if (width
!= 0 && width
* element_size
!= 64
875 && width
* element_size
!= 128
876 && !(width
== 2 && element_size
== 16)
877 && !(width
== 4 && element_size
== 8))
880 ("invalid element size %d and vector size combination %c"),
886 parsed_type
->type
= type
;
887 parsed_type
->width
= width
;
894 /* *STR contains an SVE zero/merge predication suffix. Parse it into
895 *PARSED_TYPE and point *STR at the end of the suffix. */
898 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
903 gas_assert (*ptr
== '/');
905 switch (TOLOWER (*ptr
))
908 parsed_type
->type
= NT_zero
;
911 parsed_type
->type
= NT_merge
;
914 if (*ptr
!= '\0' && *ptr
!= ',')
915 first_error_fmt (_("unexpected character `%c' in predication type"),
918 first_error (_("missing predication type"));
921 parsed_type
->width
= 0;
926 /* Parse a register of the type TYPE.
928 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
929 name or the parsed register is not of TYPE.
931 Otherwise return the register number, and optionally fill in the actual
932 type of the register in *RTYPE when multiple alternatives were given, and
933 return the register shape and element index information in *TYPEINFO.
935 IN_REG_LIST should be set with TRUE if the caller is parsing a register
939 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
940 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
943 const reg_entry
*reg
= parse_reg (&str
);
944 struct vector_type_el atype
;
945 struct vector_type_el parsetype
;
946 bfd_boolean is_typed_vecreg
= FALSE
;
949 atype
.type
= NT_invtype
;
957 set_default_error ();
961 if (! aarch64_check_reg_type (reg
, type
))
963 DEBUG_TRACE ("reg type check failed");
964 set_default_error ();
969 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
970 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
974 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
979 if (!parse_predication_for_operand (&parsetype
, &str
))
983 /* Register if of the form Vn.[bhsdq]. */
984 is_typed_vecreg
= TRUE
;
986 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
988 /* The width is always variable; we don't allow an integer width
990 gas_assert (parsetype
.width
== 0);
991 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
993 else if (parsetype
.width
== 0)
994 /* Expect index. In the new scheme we cannot have
995 Vn.[bhsdq] represent a scalar. Therefore any
996 Vn.[bhsdq] should have an index following it.
997 Except in reglists of course. */
998 atype
.defined
|= NTA_HASINDEX
;
1000 atype
.defined
|= NTA_HASTYPE
;
1002 atype
.type
= parsetype
.type
;
1003 atype
.width
= parsetype
.width
;
1006 if (skip_past_char (&str
, '['))
1010 /* Reject Sn[index] syntax. */
1011 if (!is_typed_vecreg
)
1013 first_error (_("this type of register can't be indexed"));
1019 first_error (_("index not allowed inside register list"));
1023 atype
.defined
|= NTA_HASINDEX
;
1025 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1027 if (exp
.X_op
!= O_constant
)
1029 first_error (_("constant expression required"));
1033 if (! skip_past_char (&str
, ']'))
1036 atype
.index
= exp
.X_add_number
;
1038 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1040 /* Indexed vector register expected. */
1041 first_error (_("indexed vector register expected"));
1045 /* A vector reg Vn should be typed or indexed. */
1046 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1048 first_error (_("invalid use of vector register"));
1064 Return the register number on success; return PARSE_FAIL otherwise.
1066 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1067 the register (e.g. NEON double or quad reg when either has been requested).
1069 If this is a NEON vector register with additional type information, fill
1070 in the struct pointed to by VECTYPE (if non-NULL).
1072 This parser does not handle register list. */
1075 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1076 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1078 struct vector_type_el atype
;
1080 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1081 /*in_reg_list= */ FALSE
);
1083 if (reg
== PARSE_FAIL
)
1094 static inline bfd_boolean
1095 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1099 && e1
.defined
== e2
.defined
1100 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1103 /* This function parses a list of vector registers of type TYPE.
1104 On success, it returns the parsed register list information in the
1105 following encoded format:
1107 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1108 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1110 The information of the register shape and/or index is returned in
1113 It returns PARSE_FAIL if the register list is invalid.
1115 The list contains one to four registers.
1116 Each register can be one of:
1119 All <T> should be identical.
1120 All <index> should be identical.
1121 There are restrictions on <Vt> numbers which are checked later
1122 (by reg_list_valid_p). */
1125 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1126 struct vector_type_el
*vectype
)
1130 struct vector_type_el typeinfo
, typeinfo_first
;
1135 bfd_boolean error
= FALSE
;
1136 bfd_boolean expect_index
= FALSE
;
1140 set_syntax_error (_("expecting {"));
1146 typeinfo_first
.defined
= 0;
1147 typeinfo_first
.type
= NT_invtype
;
1148 typeinfo_first
.width
= -1;
1149 typeinfo_first
.index
= 0;
1158 str
++; /* skip over '-' */
1161 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1162 /*in_reg_list= */ TRUE
);
1163 if (val
== PARSE_FAIL
)
1165 set_first_syntax_error (_("invalid vector register in list"));
1169 /* reject [bhsd]n */
1170 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1172 set_first_syntax_error (_("invalid scalar register in list"));
1177 if (typeinfo
.defined
& NTA_HASINDEX
)
1178 expect_index
= TRUE
;
1182 if (val
< val_range
)
1184 set_first_syntax_error
1185 (_("invalid range in vector register list"));
1194 typeinfo_first
= typeinfo
;
1195 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1197 set_first_syntax_error
1198 (_("type mismatch in vector register list"));
1203 for (i
= val_range
; i
<= val
; i
++)
1205 ret_val
|= i
<< (5 * nb_regs
);
1210 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1212 skip_whitespace (str
);
1215 set_first_syntax_error (_("end of vector register list not found"));
1220 skip_whitespace (str
);
1224 if (skip_past_char (&str
, '['))
1228 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1229 if (exp
.X_op
!= O_constant
)
1231 set_first_syntax_error (_("constant expression required."));
1234 if (! skip_past_char (&str
, ']'))
1237 typeinfo_first
.index
= exp
.X_add_number
;
1241 set_first_syntax_error (_("expected index"));
1248 set_first_syntax_error (_("too many registers in vector register list"));
1251 else if (nb_regs
== 0)
1253 set_first_syntax_error (_("empty vector register list"));
1259 *vectype
= typeinfo_first
;
1261 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1264 /* Directives: register aliases. */
1267 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1272 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1275 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1278 /* Only warn about a redefinition if it's not defined as the
1280 else if (new->number
!= number
|| new->type
!= type
)
1281 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1286 name
= xstrdup (str
);
1287 new = XNEW (reg_entry
);
1290 new->number
= number
;
1292 new->builtin
= FALSE
;
1294 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1300 /* Look for the .req directive. This is of the form:
1302 new_register_name .req existing_register_name
1304 If we find one, or if it looks sufficiently like one that we want to
1305 handle any error here, return TRUE. Otherwise return FALSE. */
1308 create_register_alias (char *newname
, char *p
)
1310 const reg_entry
*old
;
1311 char *oldname
, *nbuf
;
1314 /* The input scrubber ensures that whitespace after the mnemonic is
1315 collapsed to single spaces. */
1317 if (strncmp (oldname
, " .req ", 6) != 0)
1321 if (*oldname
== '\0')
1324 old
= hash_find (aarch64_reg_hsh
, oldname
);
1327 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1331 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1332 the desired alias name, and p points to its end. If not, then
1333 the desired alias name is in the global original_case_string. */
1334 #ifdef TC_CASE_SENSITIVE
1337 newname
= original_case_string
;
1338 nlen
= strlen (newname
);
1341 nbuf
= xmemdup0 (newname
, nlen
);
1343 /* Create aliases under the new name as stated; an all-lowercase
1344 version of the new name; and an all-uppercase version of the new
1346 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1348 for (p
= nbuf
; *p
; p
++)
1351 if (strncmp (nbuf
, newname
, nlen
))
1353 /* If this attempt to create an additional alias fails, do not bother
1354 trying to create the all-lower case alias. We will fail and issue
1355 a second, duplicate error message. This situation arises when the
1356 programmer does something like:
1359 The second .req creates the "Foo" alias but then fails to create
1360 the artificial FOO alias because it has already been created by the
1362 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1369 for (p
= nbuf
; *p
; p
++)
1372 if (strncmp (nbuf
, newname
, nlen
))
1373 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1380 /* Should never be called, as .req goes between the alias and the
1381 register name, not at the beginning of the line. */
1383 s_req (int a ATTRIBUTE_UNUSED
)
1385 as_bad (_("invalid syntax for .req directive"));
1388 /* The .unreq directive deletes an alias which was previously defined
1389 by .req. For example:
1395 s_unreq (int a ATTRIBUTE_UNUSED
)
1400 name
= input_line_pointer
;
1402 while (*input_line_pointer
!= 0
1403 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1404 ++input_line_pointer
;
1406 saved_char
= *input_line_pointer
;
1407 *input_line_pointer
= 0;
1410 as_bad (_("invalid syntax for .unreq directive"));
1413 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1416 as_bad (_("unknown register alias '%s'"), name
);
1417 else if (reg
->builtin
)
1418 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1425 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1426 free ((char *) reg
->name
);
1429 /* Also locate the all upper case and all lower case versions.
1430 Do not complain if we cannot find one or the other as it
1431 was probably deleted above. */
1433 nbuf
= strdup (name
);
1434 for (p
= nbuf
; *p
; p
++)
1436 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1439 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1440 free ((char *) reg
->name
);
1444 for (p
= nbuf
; *p
; p
++)
1446 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1449 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1450 free ((char *) reg
->name
);
1458 *input_line_pointer
= saved_char
;
1459 demand_empty_rest_of_line ();
1462 /* Directives: Instruction set selection. */
1465 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1466 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1467 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1468 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1470 /* Create a new mapping symbol for the transition to STATE. */
1473 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1476 const char *symname
;
1483 type
= BSF_NO_FLAGS
;
1487 type
= BSF_NO_FLAGS
;
1493 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1494 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1496 /* Save the mapping symbols for future reference. Also check that
1497 we do not place two mapping symbols at the same offset within a
1498 frag. We'll handle overlap between frags in
1499 check_mapping_symbols.
1501 If .fill or other data filling directive generates zero sized data,
1502 the mapping symbol for the following code will have the same value
1503 as the one generated for the data filling directive. In this case,
1504 we replace the old symbol with the new one at the same address. */
1507 if (frag
->tc_frag_data
.first_map
!= NULL
)
1509 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1510 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1513 frag
->tc_frag_data
.first_map
= symbolP
;
1515 if (frag
->tc_frag_data
.last_map
!= NULL
)
1517 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1518 S_GET_VALUE (symbolP
));
1519 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1520 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1523 frag
->tc_frag_data
.last_map
= symbolP
;
1526 /* We must sometimes convert a region marked as code to data during
1527 code alignment, if an odd number of bytes have to be padded. The
1528 code mapping symbol is pushed to an aligned address. */
1531 insert_data_mapping_symbol (enum mstate state
,
1532 valueT value
, fragS
* frag
, offsetT bytes
)
1534 /* If there was already a mapping symbol, remove it. */
1535 if (frag
->tc_frag_data
.last_map
!= NULL
1536 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1537 frag
->fr_address
+ value
)
1539 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1543 know (frag
->tc_frag_data
.first_map
== symp
);
1544 frag
->tc_frag_data
.first_map
= NULL
;
1546 frag
->tc_frag_data
.last_map
= NULL
;
1547 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1550 make_mapping_symbol (MAP_DATA
, value
, frag
);
1551 make_mapping_symbol (state
, value
+ bytes
, frag
);
1554 static void mapping_state_2 (enum mstate state
, int max_chars
);
1556 /* Set the mapping state to STATE. Only call this when about to
1557 emit some STATE bytes to the file. */
1560 mapping_state (enum mstate state
)
1562 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1564 if (state
== MAP_INSN
)
1565 /* AArch64 instructions require 4-byte alignment. When emitting
1566 instructions into any section, record the appropriate section
1568 record_alignment (now_seg
, 2);
1570 if (mapstate
== state
)
1571 /* The mapping symbol has already been emitted.
1572 There is nothing else to do. */
1575 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1576 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1577 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1578 evaluated later in the next else. */
1580 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1582 /* Only add the symbol if the offset is > 0:
1583 if we're at the first frag, check it's size > 0;
1584 if we're not at the first frag, then for sure
1585 the offset is > 0. */
1586 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1587 const int add_symbol
= (frag_now
!= frag_first
)
1588 || (frag_now_fix () > 0);
1591 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1595 mapping_state_2 (state
, 0);
1598 /* Same as mapping_state, but MAX_CHARS bytes have already been
1599 allocated. Put the mapping symbol that far back. */
1602 mapping_state_2 (enum mstate state
, int max_chars
)
1604 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1606 if (!SEG_NORMAL (now_seg
))
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1615 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1618 #define mapping_state(x) /* nothing */
1619 #define mapping_state_2(x, y) /* nothing */
1622 /* Directives: sectioning and alignment. */
1625 s_bss (int ignore ATTRIBUTE_UNUSED
)
1627 /* We don't support putting frags in the BSS segment, we fake it by
1628 marking in_bss, then looking at s_skip for clues. */
1629 subseg_set (bss_section
, 0);
1630 demand_empty_rest_of_line ();
1631 mapping_state (MAP_DATA
);
1635 s_even (int ignore ATTRIBUTE_UNUSED
)
1637 /* Never make frag if expect extra pass. */
1639 frag_align (1, 0, 0);
1641 record_alignment (now_seg
, 1);
1643 demand_empty_rest_of_line ();
1646 /* Directives: Literal pools. */
1648 static literal_pool
*
1649 find_literal_pool (int size
)
1653 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1655 if (pool
->section
== now_seg
1656 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1663 static literal_pool
*
1664 find_or_make_literal_pool (int size
)
1666 /* Next literal pool ID number. */
1667 static unsigned int latest_pool_num
= 1;
1670 pool
= find_literal_pool (size
);
1674 /* Create a new pool. */
1675 pool
= XNEW (literal_pool
);
1679 /* Currently we always put the literal pool in the current text
1680 section. If we were generating "small" model code where we
1681 knew that all code and initialised data was within 1MB then
1682 we could output literals to mergeable, read-only data
1685 pool
->next_free_entry
= 0;
1686 pool
->section
= now_seg
;
1687 pool
->sub_section
= now_subseg
;
1689 pool
->next
= list_of_pools
;
1690 pool
->symbol
= NULL
;
1692 /* Add it to the list. */
1693 list_of_pools
= pool
;
1696 /* New pools, and emptied pools, will have a NULL symbol. */
1697 if (pool
->symbol
== NULL
)
1699 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1700 (valueT
) 0, &zero_address_frag
);
1701 pool
->id
= latest_pool_num
++;
1708 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1709 Return TRUE on success, otherwise return FALSE. */
1711 add_to_lit_pool (expressionS
*exp
, int size
)
1716 pool
= find_or_make_literal_pool (size
);
1718 /* Check if this literal value is already in the pool. */
1719 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1721 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1723 if ((litexp
->X_op
== exp
->X_op
)
1724 && (exp
->X_op
== O_constant
)
1725 && (litexp
->X_add_number
== exp
->X_add_number
)
1726 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1729 if ((litexp
->X_op
== exp
->X_op
)
1730 && (exp
->X_op
== O_symbol
)
1731 && (litexp
->X_add_number
== exp
->X_add_number
)
1732 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1733 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1737 /* Do we need to create a new entry? */
1738 if (entry
== pool
->next_free_entry
)
1740 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1742 set_syntax_error (_("literal pool overflow"));
1746 pool
->literals
[entry
].exp
= *exp
;
1747 pool
->next_free_entry
+= 1;
1748 if (exp
->X_op
== O_big
)
1750 /* PR 16688: Bignums are held in a single global array. We must
1751 copy and preserve that value now, before it is overwritten. */
1752 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1754 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1755 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1758 pool
->literals
[entry
].bignum
= NULL
;
1761 exp
->X_op
= O_symbol
;
1762 exp
->X_add_number
= ((int) entry
) * size
;
1763 exp
->X_add_symbol
= pool
->symbol
;
1768 /* Can't use symbol_new here, so have to create a symbol and then at
1769 a later date assign it a value. That's what these functions do. */
1772 symbol_locate (symbolS
* symbolP
,
1773 const char *name
,/* It is copied, the caller can modify. */
1774 segT segment
, /* Segment identifier (SEG_<something>). */
1775 valueT valu
, /* Symbol value. */
1776 fragS
* frag
) /* Associated fragment. */
1779 char *preserved_copy_of_name
;
1781 name_length
= strlen (name
) + 1; /* +1 for \0. */
1782 obstack_grow (¬es
, name
, name_length
);
1783 preserved_copy_of_name
= obstack_finish (¬es
);
1785 #ifdef tc_canonicalize_symbol_name
1786 preserved_copy_of_name
=
1787 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1790 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1792 S_SET_SEGMENT (symbolP
, segment
);
1793 S_SET_VALUE (symbolP
, valu
);
1794 symbol_clear_list_pointers (symbolP
);
1796 symbol_set_frag (symbolP
, frag
);
1798 /* Link to end of symbol chain. */
1800 extern int symbol_table_frozen
;
1802 if (symbol_table_frozen
)
1806 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1808 obj_symbol_new_hook (symbolP
);
1810 #ifdef tc_symbol_new_hook
1811 tc_symbol_new_hook (symbolP
);
1815 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1816 #endif /* DEBUG_SYMS */
1821 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1828 for (align
= 2; align
<= 4; align
++)
1830 int size
= 1 << align
;
1832 pool
= find_literal_pool (size
);
1833 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1836 /* Align pool as you have word accesses.
1837 Only make a frag if we have to. */
1839 frag_align (align
, 0, 0);
1841 mapping_state (MAP_DATA
);
1843 record_alignment (now_seg
, align
);
1845 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1847 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1848 (valueT
) frag_now_fix (), frag_now
);
1849 symbol_table_insert (pool
->symbol
);
1851 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1853 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1855 if (exp
->X_op
== O_big
)
1857 /* PR 16688: Restore the global bignum value. */
1858 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1859 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1860 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1863 /* First output the expression in the instruction to the pool. */
1864 emit_expr (exp
, size
); /* .word|.xword */
1866 if (exp
->X_op
== O_big
)
1868 free (pool
->literals
[entry
].bignum
);
1869 pool
->literals
[entry
].bignum
= NULL
;
1873 /* Mark the pool as empty. */
1874 pool
->next_free_entry
= 0;
1875 pool
->symbol
= NULL
;
1880 /* Forward declarations for functions below, in the MD interface
1882 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1883 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1885 /* Directives: Data. */
1886 /* N.B. the support for relocation suffix in this directive needs to be
1887 implemented properly. */
1890 s_aarch64_elf_cons (int nbytes
)
1894 #ifdef md_flush_pending_output
1895 md_flush_pending_output ();
1898 if (is_it_end_of_statement ())
1900 demand_empty_rest_of_line ();
1904 #ifdef md_cons_align
1905 md_cons_align (nbytes
);
1908 mapping_state (MAP_DATA
);
1911 struct reloc_table_entry
*reloc
;
1915 if (exp
.X_op
!= O_symbol
)
1916 emit_expr (&exp
, (unsigned int) nbytes
);
1919 skip_past_char (&input_line_pointer
, '#');
1920 if (skip_past_char (&input_line_pointer
, ':'))
1922 reloc
= find_reloc_table_entry (&input_line_pointer
);
1924 as_bad (_("unrecognized relocation suffix"));
1926 as_bad (_("unimplemented relocation suffix"));
1927 ignore_rest_of_line ();
1931 emit_expr (&exp
, (unsigned int) nbytes
);
1934 while (*input_line_pointer
++ == ',');
1936 /* Put terminator back into stream. */
1937 input_line_pointer
--;
1938 demand_empty_rest_of_line ();
1941 #endif /* OBJ_ELF */
1943 /* Output a 32-bit word, but mark as an instruction. */
1946 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1950 #ifdef md_flush_pending_output
1951 md_flush_pending_output ();
1954 if (is_it_end_of_statement ())
1956 demand_empty_rest_of_line ();
1960 /* Sections are assumed to start aligned. In executable section, there is no
1961 MAP_DATA symbol pending. So we only align the address during
1962 MAP_DATA --> MAP_INSN transition.
1963 For other sections, this is not guaranteed. */
1964 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1965 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1966 frag_align_code (2, 0);
1969 mapping_state (MAP_INSN
);
1975 if (exp
.X_op
!= O_constant
)
1977 as_bad (_("constant expression required"));
1978 ignore_rest_of_line ();
1982 if (target_big_endian
)
1984 unsigned int val
= exp
.X_add_number
;
1985 exp
.X_add_number
= SWAP_32 (val
);
1987 emit_expr (&exp
, 4);
1989 while (*input_line_pointer
++ == ',');
1991 /* Put terminator back into stream. */
1992 input_line_pointer
--;
1993 demand_empty_rest_of_line ();
1997 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2000 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2006 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2007 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2009 demand_empty_rest_of_line ();
2012 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2015 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2019 /* Since we're just labelling the code, there's no need to define a
2022 /* Make sure there is enough room in this frag for the following
2023 blr. This trick only works if the blr follows immediately after
2024 the .tlsdesc directive. */
2026 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2027 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2029 demand_empty_rest_of_line ();
2032 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2035 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2041 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2042 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2044 demand_empty_rest_of_line ();
2046 #endif /* OBJ_ELF */
2048 static void s_aarch64_arch (int);
2049 static void s_aarch64_cpu (int);
2050 static void s_aarch64_arch_extension (int);
2052 /* This table describes all the machine specific pseudo-ops the assembler
2053 has to support. The fields are:
2054 pseudo-op name without dot
2055 function to call to execute this pseudo-op
2056 Integer arg to pass to the function. */
2058 const pseudo_typeS md_pseudo_table
[] = {
2059 /* Never called because '.req' does not start a line. */
2061 {"unreq", s_unreq
, 0},
2063 {"even", s_even
, 0},
2064 {"ltorg", s_ltorg
, 0},
2065 {"pool", s_ltorg
, 0},
2066 {"cpu", s_aarch64_cpu
, 0},
2067 {"arch", s_aarch64_arch
, 0},
2068 {"arch_extension", s_aarch64_arch_extension
, 0},
2069 {"inst", s_aarch64_inst
, 0},
2071 {"tlsdescadd", s_tlsdescadd
, 0},
2072 {"tlsdesccall", s_tlsdesccall
, 0},
2073 {"tlsdescldr", s_tlsdescldr
, 0},
2074 {"word", s_aarch64_elf_cons
, 4},
2075 {"long", s_aarch64_elf_cons
, 4},
2076 {"xword", s_aarch64_elf_cons
, 8},
2077 {"dword", s_aarch64_elf_cons
, 8},
2083 /* Check whether STR points to a register name followed by a comma or the
2084 end of line; REG_TYPE indicates which register types are checked
2085 against. Return TRUE if STR is such a register name; otherwise return
2086 FALSE. The function does not intend to produce any diagnostics, but since
2087 the register parser aarch64_reg_parse, which is called by this function,
2088 does produce diagnostics, we call clear_error to clear any diagnostics
2089 that may be generated by aarch64_reg_parse.
2090 Also, the function returns FALSE directly if there is any user error
2091 present at the function entry. This prevents the existing diagnostics
2092 state from being spoiled.
2093 The function currently serves parse_constant_immediate and
2094 parse_big_immediate only. */
2096 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2100 /* Prevent the diagnostics state from being spoiled. */
2104 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2106 /* Clear the parsing error that may be set by the reg parser. */
2109 if (reg
== PARSE_FAIL
)
2112 skip_whitespace (str
);
2113 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2119 /* Parser functions used exclusively in instruction operands. */
2121 /* Parse an immediate expression which may not be constant.
2123 To prevent the expression parser from pushing a register name
2124 into the symbol table as an undefined symbol, firstly a check is
2125 done to find out whether STR is a register of type REG_TYPE followed
2126 by a comma or the end of line. Return FALSE if STR is such a string. */
2129 parse_immediate_expression (char **str
, expressionS
*exp
,
2130 aarch64_reg_type reg_type
)
2132 if (reg_name_p (*str
, reg_type
))
2134 set_recoverable_error (_("immediate operand required"));
2138 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2140 if (exp
->X_op
== O_absent
)
2142 set_fatal_syntax_error (_("missing immediate expression"));
2149 /* Constant immediate-value read function for use in insn parsing.
2150 STR points to the beginning of the immediate (with the optional
2151 leading #); *VAL receives the value. REG_TYPE says which register
2152 names should be treated as registers rather than as symbolic immediates.
2154 Return TRUE on success; otherwise return FALSE. */
2157 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2161 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2164 if (exp
.X_op
!= O_constant
)
2166 set_syntax_error (_("constant expression required"));
2170 *val
= exp
.X_add_number
;
2175 encode_imm_float_bits (uint32_t imm
)
2177 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2178 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2181 /* Return TRUE if the single-precision floating-point value encoded in IMM
2182 can be expressed in the AArch64 8-bit signed floating-point format with
2183 3-bit exponent and normalized 4 bits of precision; in other words, the
2184 floating-point value must be expressable as
2185 (+/-) n / 16 * power (2, r)
2186 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2189 aarch64_imm_float_p (uint32_t imm
)
2191 /* If a single-precision floating-point value has the following bit
2192 pattern, it can be expressed in the AArch64 8-bit floating-point
2195 3 32222222 2221111111111
2196 1 09876543 21098765432109876543210
2197 n Eeeeeexx xxxx0000000000000000000
2199 where n, e and each x are either 0 or 1 independently, with
2204 /* Prepare the pattern for 'Eeeeee'. */
2205 if (((imm
>> 30) & 0x1) == 0)
2206 pattern
= 0x3e000000;
2208 pattern
= 0x40000000;
2210 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2211 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2214 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2215 as an IEEE float without any loss of precision. Store the value in
2219 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2221 /* If a double-precision floating-point value has the following bit
2222 pattern, it can be expressed in a float:
2224 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2225 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2226 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2228 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2229 if Eeee_eeee != 1111_1111
2231 where n, e, s and S are either 0 or 1 independently and where ~ is the
2235 uint32_t high32
= imm
>> 32;
2236 uint32_t low32
= imm
;
2238 /* Lower 29 bits need to be 0s. */
2239 if ((imm
& 0x1fffffff) != 0)
2242 /* Prepare the pattern for 'Eeeeeeeee'. */
2243 if (((high32
>> 30) & 0x1) == 0)
2244 pattern
= 0x38000000;
2246 pattern
= 0x40000000;
2249 if ((high32
& 0x78000000) != pattern
)
2252 /* Check Eeee_eeee != 1111_1111. */
2253 if ((high32
& 0x7ff00000) == 0x47f00000)
2256 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2257 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2258 | (low32
>> 29)); /* 3 S bits. */
2262 /* Return true if we should treat OPERAND as a double-precision
2263 floating-point operand rather than a single-precision one. */
2265 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2267 /* Check for unsuffixed SVE registers, which are allowed
2268 for LDR and STR but not in instructions that require an
2269 immediate. We get better error messages if we arbitrarily
2270 pick one size, parse the immediate normally, and then
2271 report the match failure in the normal way. */
2272 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2273 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2276 /* Parse a floating-point immediate. Return TRUE on success and return the
2277 value in *IMMED in the format of IEEE754 single-precision encoding.
2278 *CCP points to the start of the string; DP_P is TRUE when the immediate
2279 is expected to be in double-precision (N.B. this only matters when
2280 hexadecimal representation is involved). REG_TYPE says which register
2281 names should be treated as registers rather than as symbolic immediates.
2283 This routine accepts any IEEE float; it is up to the callers to reject
2287 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2288 aarch64_reg_type reg_type
)
2292 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2294 unsigned fpword
= 0;
2295 bfd_boolean hex_p
= FALSE
;
2297 skip_past_char (&str
, '#');
2300 skip_whitespace (fpnum
);
2302 if (strncmp (fpnum
, "0x", 2) == 0)
2304 /* Support the hexadecimal representation of the IEEE754 encoding.
2305 Double-precision is expected when DP_P is TRUE, otherwise the
2306 representation should be in single-precision. */
2307 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2312 if (!can_convert_double_to_float (val
, &fpword
))
2315 else if ((uint64_t) val
> 0xffffffff)
2322 else if (reg_name_p (str
, reg_type
))
2324 set_recoverable_error (_("immediate operand required"));
2332 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2335 /* Our FP word must be 32 bits (single-precision FP). */
2336 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2338 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2348 set_fatal_syntax_error (_("invalid floating-point constant"));
2352 /* Less-generic immediate-value read function with the possibility of loading
2353 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2356 To prevent the expression parser from pushing a register name into the
2357 symbol table as an undefined symbol, a check is firstly done to find
2358 out whether STR is a register of type REG_TYPE followed by a comma or
2359 the end of line. Return FALSE if STR is such a register. */
2362 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2366 if (reg_name_p (ptr
, reg_type
))
2368 set_syntax_error (_("immediate operand required"));
2372 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2374 if (inst
.reloc
.exp
.X_op
== O_constant
)
2375 *imm
= inst
.reloc
.exp
.X_add_number
;
2382 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2383 if NEED_LIBOPCODES is non-zero, the fixup will need
2384 assistance from the libopcodes. */
2387 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2388 const aarch64_opnd_info
*operand
,
2389 int need_libopcodes_p
)
2391 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2392 reloc
->opnd
= operand
->type
;
2393 if (need_libopcodes_p
)
2394 reloc
->need_libopcodes_p
= 1;
2397 /* Return TRUE if the instruction needs to be fixed up later internally by
2398 the GAS; otherwise return FALSE. */
2400 static inline bfd_boolean
2401 aarch64_gas_internal_fixup_p (void)
2403 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2406 /* Assign the immediate value to the relevant field in *OPERAND if
2407 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2408 needs an internal fixup in a later stage.
2409 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2410 IMM.VALUE that may get assigned with the constant. */
2412 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2413 aarch64_opnd_info
*operand
,
2415 int need_libopcodes_p
,
2418 if (reloc
->exp
.X_op
== O_constant
)
2421 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2423 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2424 reloc
->type
= BFD_RELOC_UNUSED
;
2428 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2429 /* Tell libopcodes to ignore this operand or not. This is helpful
2430 when one of the operands needs to be fixed up later but we need
2431 libopcodes to check the other operands. */
2432 operand
->skip
= skip_p
;
2436 /* Relocation modifiers. Each entry in the table contains the textual
2437 name for the relocation which may be placed before a symbol used as
2438 a load/store offset, or add immediate. It must be surrounded by a
2439 leading and trailing colon, for example:
2441 ldr x0, [x1, #:rello:varsym]
2442 add x0, x1, #:rello:varsym */
2444 struct reloc_table_entry
2448 bfd_reloc_code_real_type adr_type
;
2449 bfd_reloc_code_real_type adrp_type
;
2450 bfd_reloc_code_real_type movw_type
;
2451 bfd_reloc_code_real_type add_type
;
2452 bfd_reloc_code_real_type ldst_type
;
2453 bfd_reloc_code_real_type ld_literal_type
;
2456 static struct reloc_table_entry reloc_table
[] = {
2457 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2462 BFD_RELOC_AARCH64_ADD_LO12
,
2463 BFD_RELOC_AARCH64_LDST_LO12
,
2466 /* Higher 21 bits of pc-relative page offset: ADRP */
2469 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2475 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2478 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2484 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2488 BFD_RELOC_AARCH64_MOVW_G0
,
2493 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2497 BFD_RELOC_AARCH64_MOVW_G0_S
,
2502 /* Less significant bits 0-15 of address/value: MOVK, no check */
2506 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2511 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2515 BFD_RELOC_AARCH64_MOVW_G1
,
2520 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2524 BFD_RELOC_AARCH64_MOVW_G1_S
,
2529 /* Less significant bits 16-31 of address/value: MOVK, no check */
2533 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2538 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2542 BFD_RELOC_AARCH64_MOVW_G2
,
2547 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2551 BFD_RELOC_AARCH64_MOVW_G2_S
,
2556 /* Less significant bits 32-47 of address/value: MOVK, no check */
2560 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2565 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2569 BFD_RELOC_AARCH64_MOVW_G3
,
2574 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2578 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2583 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2587 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2592 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2596 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2601 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2605 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2610 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2614 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2619 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2623 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2628 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2632 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2637 /* Get to the page containing GOT entry for a symbol. */
2640 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2644 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2646 /* 12 bit offset into the page containing GOT entry for that symbol. */
2652 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2655 /* 0-15 bits of address/value: MOVk, no check. */
2659 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2664 /* Most significant bits 16-31 of address/value: MOVZ. */
2668 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2673 /* 15 bit offset into the page containing GOT entry for that symbol. */
2679 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2682 /* Get to the page containing GOT TLS entry for a symbol */
2683 {"gottprel_g0_nc", 0,
2686 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2691 /* Get to the page containing GOT TLS entry for a symbol */
2695 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2700 /* Get to the page containing GOT TLS entry for a symbol */
2702 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2703 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2709 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2714 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2718 /* Lower 16 bits address/value: MOVk. */
2722 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2727 /* Most significant bits 16-31 of address/value: MOVZ. */
2731 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2736 /* Get to the page containing GOT TLS entry for a symbol */
2738 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2739 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2743 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2745 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2750 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2751 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2754 /* Get to the page containing GOT TLS entry for a symbol.
2755 The same as GD, we allocate two consecutive GOT slots
2756 for module index and module offset, the only difference
2757 with GD is the module offset should be initialized to
2758 zero without any outstanding runtime relocation. */
2760 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2761 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2767 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2768 {"tlsldm_lo12_nc", 0,
2772 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2776 /* 12 bit offset into the module TLS base address. */
2781 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2782 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2785 /* Same as dtprel_lo12, no overflow check. */
2786 {"dtprel_lo12_nc", 0,
2790 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2791 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2794 /* bits[23:12] of offset to the module TLS base address. */
2799 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2803 /* bits[15:0] of offset to the module TLS base address. */
2807 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2812 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2816 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2821 /* bits[31:16] of offset to the module TLS base address. */
2825 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2830 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2834 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2839 /* bits[47:32] of offset to the module TLS base address. */
2843 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2848 /* Lower 16 bit offset into GOT entry for a symbol */
2849 {"tlsdesc_off_g0_nc", 0,
2852 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2857 /* Higher 16 bit offset into GOT entry for a symbol */
2858 {"tlsdesc_off_g1", 0,
2861 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2866 /* Get to the page containing GOT TLS entry for a symbol */
2869 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2873 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2875 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2876 {"gottprel_lo12", 0,
2881 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2884 /* Get tp offset for a symbol. */
2889 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2893 /* Get tp offset for a symbol. */
2898 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2899 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2902 /* Get tp offset for a symbol. */
2907 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2911 /* Get tp offset for a symbol. */
2912 {"tprel_lo12_nc", 0,
2916 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2917 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2920 /* Most significant bits 32-47 of address/value: MOVZ. */
2924 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2929 /* Most significant bits 16-31 of address/value: MOVZ. */
2933 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2938 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2942 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2947 /* Most significant bits 0-15 of address/value: MOVZ. */
2951 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2956 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2960 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2965 /* 15bit offset from got entry to base address of GOT table. */
2971 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2974 /* 14bit offset from got entry to base address of GOT table. */
2980 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2984 /* Given the address of a pointer pointing to the textual name of a
2985 relocation as may appear in assembler source, attempt to find its
2986 details in reloc_table. The pointer will be updated to the character
2987 after the trailing colon. On failure, NULL will be returned;
2988 otherwise return the reloc_table_entry. */
2990 static struct reloc_table_entry
*
2991 find_reloc_table_entry (char **str
)
2994 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2996 int length
= strlen (reloc_table
[i
].name
);
2998 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2999 && (*str
)[length
] == ':')
3001 *str
+= (length
+ 1);
3002 return &reloc_table
[i
];
3009 /* Mode argument to parse_shift and parser_shifter_operand. */
3010 enum parse_shift_mode
3012 SHIFTED_NONE
, /* no shifter allowed */
3013 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3015 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3017 SHIFTED_LSL
, /* bare "lsl #n" */
3018 SHIFTED_MUL
, /* bare "mul #n" */
3019 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3020 SHIFTED_MUL_VL
, /* "mul vl" */
3021 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3024 /* Parse a <shift> operator on an AArch64 data processing instruction.
3025 Return TRUE on success; otherwise return FALSE. */
3027 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3029 const struct aarch64_name_value_pair
*shift_op
;
3030 enum aarch64_modifier_kind kind
;
3036 for (p
= *str
; ISALPHA (*p
); p
++)
3041 set_syntax_error (_("shift expression expected"));
3045 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3047 if (shift_op
== NULL
)
3049 set_syntax_error (_("shift operator expected"));
3053 kind
= aarch64_get_operand_modifier (shift_op
);
3055 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3057 set_syntax_error (_("invalid use of 'MSL'"));
3061 if (kind
== AARCH64_MOD_MUL
3062 && mode
!= SHIFTED_MUL
3063 && mode
!= SHIFTED_MUL_VL
)
3065 set_syntax_error (_("invalid use of 'MUL'"));
3071 case SHIFTED_LOGIC_IMM
:
3072 if (aarch64_extend_operator_p (kind
))
3074 set_syntax_error (_("extending shift is not permitted"));
3079 case SHIFTED_ARITH_IMM
:
3080 if (kind
== AARCH64_MOD_ROR
)
3082 set_syntax_error (_("'ROR' shift is not permitted"));
3088 if (kind
!= AARCH64_MOD_LSL
)
3090 set_syntax_error (_("only 'LSL' shift is permitted"));
3096 if (kind
!= AARCH64_MOD_MUL
)
3098 set_syntax_error (_("only 'MUL' is permitted"));
3103 case SHIFTED_MUL_VL
:
3104 /* "MUL VL" consists of two separate tokens. Require the first
3105 token to be "MUL" and look for a following "VL". */
3106 if (kind
== AARCH64_MOD_MUL
)
3108 skip_whitespace (p
);
3109 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3112 kind
= AARCH64_MOD_MUL_VL
;
3116 set_syntax_error (_("only 'MUL VL' is permitted"));
3119 case SHIFTED_REG_OFFSET
:
3120 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3121 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3123 set_fatal_syntax_error
3124 (_("invalid shift for the register offset addressing mode"));
3129 case SHIFTED_LSL_MSL
:
3130 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3132 set_syntax_error (_("invalid shift operator"));
3141 /* Whitespace can appear here if the next thing is a bare digit. */
3142 skip_whitespace (p
);
3144 /* Parse shift amount. */
3146 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3147 exp
.X_op
= O_absent
;
3150 if (is_immediate_prefix (*p
))
3155 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3157 if (kind
== AARCH64_MOD_MUL_VL
)
3158 /* For consistency, give MUL VL the same shift amount as an implicit
3160 operand
->shifter
.amount
= 1;
3161 else if (exp
.X_op
== O_absent
)
3163 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3165 set_syntax_error (_("missing shift amount"));
3168 operand
->shifter
.amount
= 0;
3170 else if (exp
.X_op
!= O_constant
)
3172 set_syntax_error (_("constant shift amount required"));
3175 /* For parsing purposes, MUL #n has no inherent range. The range
3176 depends on the operand and will be checked by operand-specific
3178 else if (kind
!= AARCH64_MOD_MUL
3179 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3181 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3186 operand
->shifter
.amount
= exp
.X_add_number
;
3187 operand
->shifter
.amount_present
= 1;
3190 operand
->shifter
.operator_present
= 1;
3191 operand
->shifter
.kind
= kind
;
3197 /* Parse a <shifter_operand> for a data processing instruction:
3200 #<immediate>, LSL #imm
3202 Validation of immediate operands is deferred to md_apply_fix.
3204 Return TRUE on success; otherwise return FALSE. */
3207 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3208 enum parse_shift_mode mode
)
3212 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3217 /* Accept an immediate expression. */
3218 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3221 /* Accept optional LSL for arithmetic immediate values. */
3222 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3223 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3226 /* Not accept any shifter for logical immediate values. */
3227 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3228 && parse_shift (&p
, operand
, mode
))
3230 set_syntax_error (_("unexpected shift operator"));
3238 /* Parse a <shifter_operand> for a data processing instruction:
3243 #<immediate>, LSL #imm
3245 where <shift> is handled by parse_shift above, and the last two
3246 cases are handled by the function above.
3248 Validation of immediate operands is deferred to md_apply_fix.
3250 Return TRUE on success; otherwise return FALSE. */
3253 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3254 enum parse_shift_mode mode
)
3256 const reg_entry
*reg
;
3257 aarch64_opnd_qualifier_t qualifier
;
3258 enum aarch64_operand_class opd_class
3259 = aarch64_get_operand_class (operand
->type
);
3261 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3264 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3266 set_syntax_error (_("unexpected register in the immediate operand"));
3270 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3272 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3276 operand
->reg
.regno
= reg
->number
;
3277 operand
->qualifier
= qualifier
;
3279 /* Accept optional shift operation on register. */
3280 if (! skip_past_comma (str
))
3283 if (! parse_shift (str
, operand
, mode
))
3288 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3291 (_("integer register expected in the extended/shifted operand "
3296 /* We have a shifted immediate variable. */
3297 return parse_shifter_operand_imm (str
, operand
, mode
);
3300 /* Return TRUE on success; return FALSE otherwise. */
3303 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3304 enum parse_shift_mode mode
)
3308 /* Determine if we have the sequence of characters #: or just :
3309 coming next. If we do, then we check for a :rello: relocation
3310 modifier. If we don't, punt the whole lot to
3311 parse_shifter_operand. */
3313 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3315 struct reloc_table_entry
*entry
;
3323 /* Try to parse a relocation. Anything else is an error. */
3324 if (!(entry
= find_reloc_table_entry (str
)))
3326 set_syntax_error (_("unknown relocation modifier"));
3330 if (entry
->add_type
== 0)
3333 (_("this relocation modifier is not allowed on this instruction"));
3337 /* Save str before we decompose it. */
3340 /* Next, we parse the expression. */
3341 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3344 /* Record the relocation type (use the ADD variant here). */
3345 inst
.reloc
.type
= entry
->add_type
;
3346 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3348 /* If str is empty, we've reached the end, stop here. */
3352 /* Otherwise, we have a shifted reloc modifier, so rewind to
3353 recover the variable name and continue parsing for the shifter. */
3355 return parse_shifter_operand_imm (str
, operand
, mode
);
3358 return parse_shifter_operand (str
, operand
, mode
);
3361 /* Parse all forms of an address expression. Information is written
3362 to *OPERAND and/or inst.reloc.
3364 The A64 instruction set has the following addressing modes:
3367 [base] // in SIMD ld/st structure
3368 [base{,#0}] // in ld/st exclusive
3370 [base,Xm{,LSL #imm}]
3371 [base,Xm,SXTX {#imm}]
3372 [base,Wm,(S|U)XTW {#imm}]
3377 [base],Xm // in SIMD ld/st structure
3378 PC-relative (literal)
3382 [base,Zm.D{,LSL #imm}]
3383 [base,Zm.S,(S|U)XTW {#imm}]
3384 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3387 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3388 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3389 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3391 (As a convenience, the notation "=immediate" is permitted in conjunction
3392 with the pc-relative literal load instructions to automatically place an
3393 immediate value or symbolic address in a nearby literal pool and generate
3394 a hidden label which references it.)
3396 Upon a successful parsing, the address structure in *OPERAND will be
3397 filled in the following way:
3399 .base_regno = <base>
3400 .offset.is_reg // 1 if the offset is a register
3402 .offset.regno = <Rm>
3404 For different addressing modes defined in the A64 ISA:
3407 .pcrel=0; .preind=1; .postind=0; .writeback=0
3409 .pcrel=0; .preind=1; .postind=0; .writeback=1
3411 .pcrel=0; .preind=0; .postind=1; .writeback=1
3412 PC-relative (literal)
3413 .pcrel=1; .preind=1; .postind=0; .writeback=0
3415 The shift/extension information, if any, will be stored in .shifter.
3416 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3417 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3418 corresponding register.
3420 BASE_TYPE says which types of base register should be accepted and
3421 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3422 is the type of shifter that is allowed for immediate offsets,
3423 or SHIFTED_NONE if none.
3425 In all other respects, it is the caller's responsibility to check
3426 for addressing modes not supported by the instruction, and to set
3430 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3431 aarch64_opnd_qualifier_t
*base_qualifier
,
3432 aarch64_opnd_qualifier_t
*offset_qualifier
,
3433 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3434 enum parse_shift_mode imm_shift_mode
)
3437 const reg_entry
*reg
;
3438 expressionS
*exp
= &inst
.reloc
.exp
;
3440 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3441 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3442 if (! skip_past_char (&p
, '['))
3444 /* =immediate or label. */
3445 operand
->addr
.pcrel
= 1;
3446 operand
->addr
.preind
= 1;
3448 /* #:<reloc_op>:<symbol> */
3449 skip_past_char (&p
, '#');
3450 if (skip_past_char (&p
, ':'))
3452 bfd_reloc_code_real_type ty
;
3453 struct reloc_table_entry
*entry
;
3455 /* Try to parse a relocation modifier. Anything else is
3457 entry
= find_reloc_table_entry (&p
);
3460 set_syntax_error (_("unknown relocation modifier"));
3464 switch (operand
->type
)
3466 case AARCH64_OPND_ADDR_PCREL21
:
3468 ty
= entry
->adr_type
;
3472 ty
= entry
->ld_literal_type
;
3479 (_("this relocation modifier is not allowed on this "
3485 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3487 set_syntax_error (_("invalid relocation expression"));
3491 /* #:<reloc_op>:<expr> */
3492 /* Record the relocation type. */
3493 inst
.reloc
.type
= ty
;
3494 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3499 if (skip_past_char (&p
, '='))
3500 /* =immediate; need to generate the literal in the literal pool. */
3501 inst
.gen_lit_pool
= 1;
3503 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3505 set_syntax_error (_("invalid address"));
3516 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3517 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3519 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3522 operand
->addr
.base_regno
= reg
->number
;
3525 if (skip_past_comma (&p
))
3528 operand
->addr
.preind
= 1;
3530 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3533 if (!aarch64_check_reg_type (reg
, offset_type
))
3535 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3540 operand
->addr
.offset
.regno
= reg
->number
;
3541 operand
->addr
.offset
.is_reg
= 1;
3542 /* Shifted index. */
3543 if (skip_past_comma (&p
))
3546 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3547 /* Use the diagnostics set in parse_shift, so not set new
3548 error message here. */
3552 [base,Xm{,LSL #imm}]
3553 [base,Xm,SXTX {#imm}]
3554 [base,Wm,(S|U)XTW {#imm}] */
3555 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3556 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3557 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3559 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3561 set_syntax_error (_("invalid use of 32-bit register offset"));
3564 if (aarch64_get_qualifier_esize (*base_qualifier
)
3565 != aarch64_get_qualifier_esize (*offset_qualifier
))
3567 set_syntax_error (_("offset has different size from base"));
3571 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3573 set_syntax_error (_("invalid use of 64-bit register offset"));
3579 /* [Xn,#:<reloc_op>:<symbol> */
3580 skip_past_char (&p
, '#');
3581 if (skip_past_char (&p
, ':'))
3583 struct reloc_table_entry
*entry
;
3585 /* Try to parse a relocation modifier. Anything else is
3587 if (!(entry
= find_reloc_table_entry (&p
)))
3589 set_syntax_error (_("unknown relocation modifier"));
3593 if (entry
->ldst_type
== 0)
3596 (_("this relocation modifier is not allowed on this "
3601 /* [Xn,#:<reloc_op>: */
3602 /* We now have the group relocation table entry corresponding to
3603 the name in the assembler source. Next, we parse the
3605 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3607 set_syntax_error (_("invalid relocation expression"));
3611 /* [Xn,#:<reloc_op>:<expr> */
3612 /* Record the load/store relocation type. */
3613 inst
.reloc
.type
= entry
->ldst_type
;
3614 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3618 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3620 set_syntax_error (_("invalid expression in the address"));
3624 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3625 /* [Xn,<expr>,<shifter> */
3626 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3632 if (! skip_past_char (&p
, ']'))
3634 set_syntax_error (_("']' expected"));
3638 if (skip_past_char (&p
, '!'))
3640 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3642 set_syntax_error (_("register offset not allowed in pre-indexed "
3643 "addressing mode"));
3647 operand
->addr
.writeback
= 1;
3649 else if (skip_past_comma (&p
))
3652 operand
->addr
.postind
= 1;
3653 operand
->addr
.writeback
= 1;
3655 if (operand
->addr
.preind
)
3657 set_syntax_error (_("cannot combine pre- and post-indexing"));
3661 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3665 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3667 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3671 operand
->addr
.offset
.regno
= reg
->number
;
3672 operand
->addr
.offset
.is_reg
= 1;
3674 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3677 set_syntax_error (_("invalid expression in the address"));
3682 /* If at this point neither .preind nor .postind is set, we have a
3683 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3684 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3686 if (operand
->addr
.writeback
)
3689 set_syntax_error (_("missing offset in the pre-indexed address"));
3693 operand
->addr
.preind
= 1;
3694 inst
.reloc
.exp
.X_op
= O_constant
;
3695 inst
.reloc
.exp
.X_add_number
= 0;
3702 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3705 parse_address (char **str
, aarch64_opnd_info
*operand
)
3707 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3708 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3709 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3712 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3713 The arguments have the same meaning as for parse_address_main.
3714 Return TRUE on success. */
3716 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3717 aarch64_opnd_qualifier_t
*base_qualifier
,
3718 aarch64_opnd_qualifier_t
*offset_qualifier
)
3720 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3721 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3725 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3726 Return TRUE on success; otherwise return FALSE. */
3728 parse_half (char **str
, int *internal_fixup_p
)
3732 skip_past_char (&p
, '#');
3734 gas_assert (internal_fixup_p
);
3735 *internal_fixup_p
= 0;
3739 struct reloc_table_entry
*entry
;
3741 /* Try to parse a relocation. Anything else is an error. */
3743 if (!(entry
= find_reloc_table_entry (&p
)))
3745 set_syntax_error (_("unknown relocation modifier"));
3749 if (entry
->movw_type
== 0)
3752 (_("this relocation modifier is not allowed on this instruction"));
3756 inst
.reloc
.type
= entry
->movw_type
;
3759 *internal_fixup_p
= 1;
3761 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3768 /* Parse an operand for an ADRP instruction:
3770 Return TRUE on success; otherwise return FALSE. */
3773 parse_adrp (char **str
)
3780 struct reloc_table_entry
*entry
;
3782 /* Try to parse a relocation. Anything else is an error. */
3784 if (!(entry
= find_reloc_table_entry (&p
)))
3786 set_syntax_error (_("unknown relocation modifier"));
3790 if (entry
->adrp_type
== 0)
3793 (_("this relocation modifier is not allowed on this instruction"));
3797 inst
.reloc
.type
= entry
->adrp_type
;
3800 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3802 inst
.reloc
.pc_rel
= 1;
3804 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3811 /* Miscellaneous. */
3813 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3814 of SIZE tokens in which index I gives the token for field value I,
3815 or is null if field value I is invalid. REG_TYPE says which register
3816 names should be treated as registers rather than as symbolic immediates.
3818 Return true on success, moving *STR past the operand and storing the
3819 field value in *VAL. */
3822 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3823 size_t size
, aarch64_reg_type reg_type
)
3829 /* Match C-like tokens. */
3831 while (ISALNUM (*q
))
3834 for (i
= 0; i
< size
; ++i
)
3836 && strncasecmp (array
[i
], p
, q
- p
) == 0
3837 && array
[i
][q
- p
] == 0)
3844 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3847 if (exp
.X_op
== O_constant
3848 && (uint64_t) exp
.X_add_number
< size
)
3850 *val
= exp
.X_add_number
;
3855 /* Use the default error for this operand. */
3859 /* Parse an option for a preload instruction. Returns the encoding for the
3860 option, or PARSE_FAIL. */
3863 parse_pldop (char **str
)
3866 const struct aarch64_name_value_pair
*o
;
3869 while (ISALNUM (*q
))
3872 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3880 /* Parse an option for a barrier instruction. Returns the encoding for the
3881 option, or PARSE_FAIL. */
3884 parse_barrier (char **str
)
3887 const asm_barrier_opt
*o
;
3890 while (ISALPHA (*q
))
3893 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3901 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3902 return 0 if successful. Otherwise return PARSE_FAIL. */
3905 parse_barrier_psb (char **str
,
3906 const struct aarch64_name_value_pair
** hint_opt
)
3909 const struct aarch64_name_value_pair
*o
;
3912 while (ISALPHA (*q
))
3915 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3918 set_fatal_syntax_error
3919 ( _("unknown or missing option to PSB"));
3923 if (o
->value
!= 0x11)
3925 /* PSB only accepts option name 'CSYNC'. */
3927 (_("the specified option is not accepted for PSB"));
3936 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3937 return 0 if successful. Otherwise return PARSE_FAIL. */
3940 parse_bti_operand (char **str
,
3941 const struct aarch64_name_value_pair
** hint_opt
)
3944 const struct aarch64_name_value_pair
*o
;
3947 while (ISALPHA (*q
))
3950 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3953 set_fatal_syntax_error
3954 ( _("unknown option to BTI"));
3960 /* Valid BTI operands. */
3968 (_("unknown option to BTI"));
3977 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3978 Returns the encoding for the option, or PARSE_FAIL.
3980 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3981 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3983 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3984 field, otherwise as a system register.
3988 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3989 int imple_defined_p
, int pstatefield_p
,
3994 const aarch64_sys_reg
*o
;
3998 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4000 *p
++ = TOLOWER (*q
);
4002 /* Assert that BUF be large enough. */
4003 gas_assert (p
- buf
== q
- *str
);
4005 o
= hash_find (sys_regs
, buf
);
4008 if (!imple_defined_p
)
4012 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4013 unsigned int op0
, op1
, cn
, cm
, op2
;
4015 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4018 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4020 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4027 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4028 as_bad (_("selected processor does not support PSTATE field "
4030 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4031 as_bad (_("selected processor does not support system register "
4033 if (aarch64_sys_reg_deprecated_p (o
))
4034 as_warn (_("system register name '%s' is deprecated and may be "
4035 "removed in a future release"), buf
);
4045 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4046 for the option, or NULL. */
4048 static const aarch64_sys_ins_reg
*
4049 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4053 const aarch64_sys_ins_reg
*o
;
4056 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4058 *p
++ = TOLOWER (*q
);
4061 o
= hash_find (sys_ins_regs
, buf
);
4065 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4066 as_bad (_("selected processor does not support system register "
4073 #define po_char_or_fail(chr) do { \
4074 if (! skip_past_char (&str, chr)) \
4078 #define po_reg_or_fail(regtype) do { \
4079 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4080 if (val == PARSE_FAIL) \
4082 set_default_error (); \
4087 #define po_int_reg_or_fail(reg_type) do { \
4088 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4089 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4091 set_default_error (); \
4094 info->reg.regno = reg->number; \
4095 info->qualifier = qualifier; \
4098 #define po_imm_nc_or_fail() do { \
4099 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4103 #define po_imm_or_fail(min, max) do { \
4104 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4106 if (val < min || val > max) \
4108 set_fatal_syntax_error (_("immediate value out of range "\
4109 #min " to "#max)); \
4114 #define po_enum_or_fail(array) do { \
4115 if (!parse_enum_string (&str, &val, array, \
4116 ARRAY_SIZE (array), imm_reg_type)) \
4120 #define po_misc_or_fail(expr) do { \
4125 /* encode the 12-bit imm field of Add/sub immediate */
4126 static inline uint32_t
4127 encode_addsub_imm (uint32_t imm
)
4132 /* encode the shift amount field of Add/sub immediate */
4133 static inline uint32_t
4134 encode_addsub_imm_shift_amount (uint32_t cnt
)
4140 /* encode the imm field of Adr instruction */
4141 static inline uint32_t
4142 encode_adr_imm (uint32_t imm
)
4144 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4145 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4148 /* encode the immediate field of Move wide immediate */
4149 static inline uint32_t
4150 encode_movw_imm (uint32_t imm
)
4155 /* encode the 26-bit offset of unconditional branch */
4156 static inline uint32_t
4157 encode_branch_ofs_26 (uint32_t ofs
)
4159 return ofs
& ((1 << 26) - 1);
4162 /* encode the 19-bit offset of conditional branch and compare & branch */
4163 static inline uint32_t
4164 encode_cond_branch_ofs_19 (uint32_t ofs
)
4166 return (ofs
& ((1 << 19) - 1)) << 5;
4169 /* encode the 19-bit offset of ld literal */
4170 static inline uint32_t
4171 encode_ld_lit_ofs_19 (uint32_t ofs
)
4173 return (ofs
& ((1 << 19) - 1)) << 5;
4176 /* Encode the 14-bit offset of test & branch. */
4177 static inline uint32_t
4178 encode_tst_branch_ofs_14 (uint32_t ofs
)
4180 return (ofs
& ((1 << 14) - 1)) << 5;
4183 /* Encode the 16-bit imm field of svc/hvc/smc. */
4184 static inline uint32_t
4185 encode_svc_imm (uint32_t imm
)
4190 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4191 static inline uint32_t
4192 reencode_addsub_switch_add_sub (uint32_t opcode
)
4194 return opcode
^ (1 << 30);
4197 static inline uint32_t
4198 reencode_movzn_to_movz (uint32_t opcode
)
4200 return opcode
| (1 << 30);
4203 static inline uint32_t
4204 reencode_movzn_to_movn (uint32_t opcode
)
4206 return opcode
& ~(1 << 30);
4209 /* Overall per-instruction processing. */
4211 /* We need to be able to fix up arbitrary expressions in some statements.
4212 This is so that we can handle symbols that are an arbitrary distance from
4213 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4214 which returns part of an address in a form which will be valid for
4215 a data instruction. We do this by pushing the expression into a symbol
4216 in the expr_section, and creating a fix for that. */
4219 fix_new_aarch64 (fragS
* frag
,
4221 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4231 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4235 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4242 /* Diagnostics on operands errors. */
4244 /* By default, output verbose error message.
4245 Disable the verbose error message by -mno-verbose-error. */
4246 static int verbose_error_p
= 1;
4248 #ifdef DEBUG_AARCH64
4249 /* N.B. this is only for the purpose of debugging. */
4250 const char* operand_mismatch_kind_names
[] =
4253 "AARCH64_OPDE_RECOVERABLE",
4254 "AARCH64_OPDE_SYNTAX_ERROR",
4255 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4256 "AARCH64_OPDE_INVALID_VARIANT",
4257 "AARCH64_OPDE_OUT_OF_RANGE",
4258 "AARCH64_OPDE_UNALIGNED",
4259 "AARCH64_OPDE_REG_LIST",
4260 "AARCH64_OPDE_OTHER_ERROR",
4262 #endif /* DEBUG_AARCH64 */
4264 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4266 When multiple errors of different kinds are found in the same assembly
4267 line, only the error of the highest severity will be picked up for
4268 issuing the diagnostics. */
4270 static inline bfd_boolean
4271 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4272 enum aarch64_operand_error_kind rhs
)
4274 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4275 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4276 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4277 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4278 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4279 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4280 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4281 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4285 /* Helper routine to get the mnemonic name from the assembly instruction
4286 line; should only be called for the diagnosis purpose, as there is
4287 string copy operation involved, which may affect the runtime
4288 performance if used in elsewhere. */
4291 get_mnemonic_name (const char *str
)
4293 static char mnemonic
[32];
4296 /* Get the first 15 bytes and assume that the full name is included. */
4297 strncpy (mnemonic
, str
, 31);
4298 mnemonic
[31] = '\0';
4300 /* Scan up to the end of the mnemonic, which must end in white space,
4301 '.', or end of string. */
4302 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4307 /* Append '...' to the truncated long name. */
4308 if (ptr
- mnemonic
== 31)
4309 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4315 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4317 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4318 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4321 /* Data structures storing one user error in the assembly code related to
4324 struct operand_error_record
4326 const aarch64_opcode
*opcode
;
4327 aarch64_operand_error detail
;
4328 struct operand_error_record
*next
;
4331 typedef struct operand_error_record operand_error_record
;
4333 struct operand_errors
4335 operand_error_record
*head
;
4336 operand_error_record
*tail
;
4339 typedef struct operand_errors operand_errors
;
4341 /* Top-level data structure reporting user errors for the current line of
4343 The way md_assemble works is that all opcodes sharing the same mnemonic
4344 name are iterated to find a match to the assembly line. In this data
4345 structure, each of the such opcodes will have one operand_error_record
4346 allocated and inserted. In other words, excessive errors related with
4347 a single opcode are disregarded. */
4348 operand_errors operand_error_report
;
4350 /* Free record nodes. */
4351 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4353 /* Initialize the data structure that stores the operand mismatch
4354 information on assembling one line of the assembly code. */
4356 init_operand_error_report (void)
4358 if (operand_error_report
.head
!= NULL
)
4360 gas_assert (operand_error_report
.tail
!= NULL
);
4361 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4362 free_opnd_error_record_nodes
= operand_error_report
.head
;
4363 operand_error_report
.head
= NULL
;
4364 operand_error_report
.tail
= NULL
;
4367 gas_assert (operand_error_report
.tail
== NULL
);
4370 /* Return TRUE if some operand error has been recorded during the
4371 parsing of the current assembly line using the opcode *OPCODE;
4372 otherwise return FALSE. */
4373 static inline bfd_boolean
4374 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4376 operand_error_record
*record
= operand_error_report
.head
;
4377 return record
&& record
->opcode
== opcode
;
4380 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4381 OPCODE field is initialized with OPCODE.
4382 N.B. only one record for each opcode, i.e. the maximum of one error is
4383 recorded for each instruction template. */
4386 add_operand_error_record (const operand_error_record
* new_record
)
4388 const aarch64_opcode
*opcode
= new_record
->opcode
;
4389 operand_error_record
* record
= operand_error_report
.head
;
4391 /* The record may have been created for this opcode. If not, we need
4393 if (! opcode_has_operand_error_p (opcode
))
4395 /* Get one empty record. */
4396 if (free_opnd_error_record_nodes
== NULL
)
4398 record
= XNEW (operand_error_record
);
4402 record
= free_opnd_error_record_nodes
;
4403 free_opnd_error_record_nodes
= record
->next
;
4405 record
->opcode
= opcode
;
4406 /* Insert at the head. */
4407 record
->next
= operand_error_report
.head
;
4408 operand_error_report
.head
= record
;
4409 if (operand_error_report
.tail
== NULL
)
4410 operand_error_report
.tail
= record
;
4412 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4413 && record
->detail
.index
<= new_record
->detail
.index
4414 && operand_error_higher_severity_p (record
->detail
.kind
,
4415 new_record
->detail
.kind
))
4417 /* In the case of multiple errors found on operands related with a
4418 single opcode, only record the error of the leftmost operand and
4419 only if the error is of higher severity. */
4420 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4421 " the existing error %s on operand %d",
4422 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4423 new_record
->detail
.index
,
4424 operand_mismatch_kind_names
[record
->detail
.kind
],
4425 record
->detail
.index
);
4429 record
->detail
= new_record
->detail
;
4433 record_operand_error_info (const aarch64_opcode
*opcode
,
4434 aarch64_operand_error
*error_info
)
4436 operand_error_record record
;
4437 record
.opcode
= opcode
;
4438 record
.detail
= *error_info
;
4439 add_operand_error_record (&record
);
4442 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4443 error message *ERROR, for operand IDX (count from 0). */
4446 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4447 enum aarch64_operand_error_kind kind
,
4450 aarch64_operand_error info
;
4451 memset(&info
, 0, sizeof (info
));
4455 info
.non_fatal
= FALSE
;
4456 record_operand_error_info (opcode
, &info
);
4460 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4461 enum aarch64_operand_error_kind kind
,
4462 const char* error
, const int *extra_data
)
4464 aarch64_operand_error info
;
4468 info
.data
[0] = extra_data
[0];
4469 info
.data
[1] = extra_data
[1];
4470 info
.data
[2] = extra_data
[2];
4471 info
.non_fatal
= FALSE
;
4472 record_operand_error_info (opcode
, &info
);
4476 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4477 const char* error
, int lower_bound
,
4480 int data
[3] = {lower_bound
, upper_bound
, 0};
4481 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4485 /* Remove the operand error record for *OPCODE. */
4486 static void ATTRIBUTE_UNUSED
4487 remove_operand_error_record (const aarch64_opcode
*opcode
)
4489 if (opcode_has_operand_error_p (opcode
))
4491 operand_error_record
* record
= operand_error_report
.head
;
4492 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4493 operand_error_report
.head
= record
->next
;
4494 record
->next
= free_opnd_error_record_nodes
;
4495 free_opnd_error_record_nodes
= record
;
4496 if (operand_error_report
.head
== NULL
)
4498 gas_assert (operand_error_report
.tail
== record
);
4499 operand_error_report
.tail
= NULL
;
4504 /* Given the instruction in *INSTR, return the index of the best matched
4505 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4507 Return -1 if there is no qualifier sequence; return the first match
4508 if there is multiple matches found. */
4511 find_best_match (const aarch64_inst
*instr
,
4512 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4514 int i
, num_opnds
, max_num_matched
, idx
;
4516 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4519 DEBUG_TRACE ("no operand");
4523 max_num_matched
= 0;
4526 /* For each pattern. */
4527 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4530 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4532 /* Most opcodes has much fewer patterns in the list. */
4533 if (empty_qualifier_sequence_p (qualifiers
))
4535 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4539 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4540 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4543 if (num_matched
> max_num_matched
)
4545 max_num_matched
= num_matched
;
4550 DEBUG_TRACE ("return with %d", idx
);
4554 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4555 corresponding operands in *INSTR. */
4558 assign_qualifier_sequence (aarch64_inst
*instr
,
4559 const aarch64_opnd_qualifier_t
*qualifiers
)
4562 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4563 gas_assert (num_opnds
);
4564 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4565 instr
->operands
[i
].qualifier
= *qualifiers
;
4568 /* Print operands for the diagnosis purpose. */
4571 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4572 const aarch64_opnd_info
*opnds
)
4576 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4580 /* We regard the opcode operand info more, however we also look into
4581 the inst->operands to support the disassembling of the optional
4583 The two operand code should be the same in all cases, apart from
4584 when the operand can be optional. */
4585 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4586 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4589 /* Generate the operand string in STR. */
4590 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4595 strcat (buf
, i
== 0 ? " " : ", ");
4597 /* Append the operand string. */
4602 /* Send to stderr a string as information. */
4605 output_info (const char *format
, ...)
4611 file
= as_where (&line
);
4615 fprintf (stderr
, "%s:%u: ", file
, line
);
4617 fprintf (stderr
, "%s: ", file
);
4619 fprintf (stderr
, _("Info: "));
4620 va_start (args
, format
);
4621 vfprintf (stderr
, format
, args
);
4623 (void) putc ('\n', stderr
);
4626 /* Output one operand error record. */
4629 output_operand_error_record (const operand_error_record
*record
, char *str
)
4631 const aarch64_operand_error
*detail
= &record
->detail
;
4632 int idx
= detail
->index
;
4633 const aarch64_opcode
*opcode
= record
->opcode
;
4634 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4635 : AARCH64_OPND_NIL
);
4637 typedef void (*handler_t
)(const char *format
, ...);
4638 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4640 switch (detail
->kind
)
4642 case AARCH64_OPDE_NIL
:
4645 case AARCH64_OPDE_SYNTAX_ERROR
:
4646 case AARCH64_OPDE_RECOVERABLE
:
4647 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4648 case AARCH64_OPDE_OTHER_ERROR
:
4649 /* Use the prepared error message if there is, otherwise use the
4650 operand description string to describe the error. */
4651 if (detail
->error
!= NULL
)
4654 handler (_("%s -- `%s'"), detail
->error
, str
);
4656 handler (_("%s at operand %d -- `%s'"),
4657 detail
->error
, idx
+ 1, str
);
4661 gas_assert (idx
>= 0);
4662 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4663 aarch64_get_operand_desc (opd_code
), str
);
4667 case AARCH64_OPDE_INVALID_VARIANT
:
4668 handler (_("operand mismatch -- `%s'"), str
);
4669 if (verbose_error_p
)
4671 /* We will try to correct the erroneous instruction and also provide
4672 more information e.g. all other valid variants.
4674 The string representation of the corrected instruction and other
4675 valid variants are generated by
4677 1) obtaining the intermediate representation of the erroneous
4679 2) manipulating the IR, e.g. replacing the operand qualifier;
4680 3) printing out the instruction by calling the printer functions
4681 shared with the disassembler.
4683 The limitation of this method is that the exact input assembly
4684 line cannot be accurately reproduced in some cases, for example an
4685 optional operand present in the actual assembly line will be
4686 omitted in the output; likewise for the optional syntax rules,
4687 e.g. the # before the immediate. Another limitation is that the
4688 assembly symbols and relocation operations in the assembly line
4689 currently cannot be printed out in the error report. Last but not
4690 least, when there is other error(s) co-exist with this error, the
4691 'corrected' instruction may be still incorrect, e.g. given
4692 'ldnp h0,h1,[x0,#6]!'
4693 this diagnosis will provide the version:
4694 'ldnp s0,s1,[x0,#6]!'
4695 which is still not right. */
4696 size_t len
= strlen (get_mnemonic_name (str
));
4700 aarch64_inst
*inst_base
= &inst
.base
;
4701 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4704 reset_aarch64_instruction (&inst
);
4705 inst_base
->opcode
= opcode
;
4707 /* Reset the error report so that there is no side effect on the
4708 following operand parsing. */
4709 init_operand_error_report ();
4712 result
= parse_operands (str
+ len
, opcode
)
4713 && programmer_friendly_fixup (&inst
);
4714 gas_assert (result
);
4715 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4716 NULL
, NULL
, insn_sequence
);
4717 gas_assert (!result
);
4719 /* Find the most matched qualifier sequence. */
4720 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4721 gas_assert (qlf_idx
> -1);
4723 /* Assign the qualifiers. */
4724 assign_qualifier_sequence (inst_base
,
4725 opcode
->qualifiers_list
[qlf_idx
]);
4727 /* Print the hint. */
4728 output_info (_(" did you mean this?"));
4729 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4730 print_operands (buf
, opcode
, inst_base
->operands
);
4731 output_info (_(" %s"), buf
);
4733 /* Print out other variant(s) if there is any. */
4735 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4736 output_info (_(" other valid variant(s):"));
4738 /* For each pattern. */
4739 qualifiers_list
= opcode
->qualifiers_list
;
4740 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4742 /* Most opcodes has much fewer patterns in the list.
4743 First NIL qualifier indicates the end in the list. */
4744 if (empty_qualifier_sequence_p (*qualifiers_list
))
4749 /* Mnemonics name. */
4750 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4752 /* Assign the qualifiers. */
4753 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4755 /* Print instruction. */
4756 print_operands (buf
, opcode
, inst_base
->operands
);
4758 output_info (_(" %s"), buf
);
4764 case AARCH64_OPDE_UNTIED_OPERAND
:
4765 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4766 detail
->index
+ 1, str
);
4769 case AARCH64_OPDE_OUT_OF_RANGE
:
4770 if (detail
->data
[0] != detail
->data
[1])
4771 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4772 detail
->error
? detail
->error
: _("immediate value"),
4773 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4775 handler (_("%s must be %d at operand %d -- `%s'"),
4776 detail
->error
? detail
->error
: _("immediate value"),
4777 detail
->data
[0], idx
+ 1, str
);
4780 case AARCH64_OPDE_REG_LIST
:
4781 if (detail
->data
[0] == 1)
4782 handler (_("invalid number of registers in the list; "
4783 "only 1 register is expected at operand %d -- `%s'"),
4786 handler (_("invalid number of registers in the list; "
4787 "%d registers are expected at operand %d -- `%s'"),
4788 detail
->data
[0], idx
+ 1, str
);
4791 case AARCH64_OPDE_UNALIGNED
:
4792 handler (_("immediate value must be a multiple of "
4793 "%d at operand %d -- `%s'"),
4794 detail
->data
[0], idx
+ 1, str
);
4803 /* Process and output the error message about the operand mismatching.
4805 When this function is called, the operand error information had
4806 been collected for an assembly line and there will be multiple
4807 errors in the case of multiple instruction templates; output the
4808 error message that most closely describes the problem.
4810 The errors to be printed can be filtered on printing all errors
4811 or only non-fatal errors. This distinction has to be made because
4812 the error buffer may already be filled with fatal errors we don't want to
4813 print due to the different instruction templates. */
4816 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4818 int largest_error_pos
;
4819 const char *msg
= NULL
;
4820 enum aarch64_operand_error_kind kind
;
4821 operand_error_record
*curr
;
4822 operand_error_record
*head
= operand_error_report
.head
;
4823 operand_error_record
*record
= NULL
;
4825 /* No error to report. */
4829 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4831 /* Only one error. */
4832 if (head
== operand_error_report
.tail
)
4834 /* If the only error is a non-fatal one and we don't want to print it,
4836 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4838 DEBUG_TRACE ("single opcode entry with error kind: %s",
4839 operand_mismatch_kind_names
[head
->detail
.kind
]);
4840 output_operand_error_record (head
, str
);
4845 /* Find the error kind of the highest severity. */
4846 DEBUG_TRACE ("multiple opcode entries with error kind");
4847 kind
= AARCH64_OPDE_NIL
;
4848 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4850 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4851 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4852 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4853 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4854 kind
= curr
->detail
.kind
;
4857 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4859 /* Pick up one of errors of KIND to report. */
4860 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4861 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4863 /* If we don't want to print non-fatal errors then don't consider them
4865 if (curr
->detail
.kind
!= kind
4866 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4868 /* If there are multiple errors, pick up the one with the highest
4869 mismatching operand index. In the case of multiple errors with
4870 the equally highest operand index, pick up the first one or the
4871 first one with non-NULL error message. */
4872 if (curr
->detail
.index
> largest_error_pos
4873 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4874 && curr
->detail
.error
!= NULL
))
4876 largest_error_pos
= curr
->detail
.index
;
4878 msg
= record
->detail
.error
;
4882 /* The way errors are collected in the back-end is a bit non-intuitive. But
4883 essentially, because each operand template is tried recursively you may
4884 always have errors collected from the previous tried OPND. These are
4885 usually skipped if there is one successful match. However now with the
4886 non-fatal errors we have to ignore those previously collected hard errors
4887 when we're only interested in printing the non-fatal ones. This condition
4888 prevents us from printing errors that are not appropriate, since we did
4889 match a condition, but it also has warnings that it wants to print. */
4890 if (non_fatal_only
&& !record
)
4893 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4894 DEBUG_TRACE ("Pick up error kind %s to report",
4895 operand_mismatch_kind_names
[record
->detail
.kind
]);
4898 output_operand_error_record (record
, str
);
4901 /* Write an AARCH64 instruction to buf - always little-endian. */
4903 put_aarch64_insn (char *buf
, uint32_t insn
)
4905 unsigned char *where
= (unsigned char *) buf
;
4907 where
[1] = insn
>> 8;
4908 where
[2] = insn
>> 16;
4909 where
[3] = insn
>> 24;
4913 get_aarch64_insn (char *buf
)
4915 unsigned char *where
= (unsigned char *) buf
;
4917 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4922 output_inst (struct aarch64_inst
*new_inst
)
4926 to
= frag_more (INSN_SIZE
);
4928 frag_now
->tc_frag_data
.recorded
= 1;
4930 put_aarch64_insn (to
, inst
.base
.value
);
4932 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4934 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4935 INSN_SIZE
, &inst
.reloc
.exp
,
4938 DEBUG_TRACE ("Prepared relocation fix up");
4939 /* Don't check the addend value against the instruction size,
4940 that's the job of our code in md_apply_fix(). */
4941 fixp
->fx_no_overflow
= 1;
4942 if (new_inst
!= NULL
)
4943 fixp
->tc_fix_data
.inst
= new_inst
;
4944 if (aarch64_gas_internal_fixup_p ())
4946 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4947 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4948 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4952 dwarf2_emit_insn (INSN_SIZE
);
4955 /* Link together opcodes of the same name. */
4959 aarch64_opcode
*opcode
;
4960 struct templates
*next
;
4963 typedef struct templates templates
;
4966 lookup_mnemonic (const char *start
, int len
)
4968 templates
*templ
= NULL
;
4970 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4974 /* Subroutine of md_assemble, responsible for looking up the primary
4975 opcode from the mnemonic the user wrote. STR points to the
4976 beginning of the mnemonic. */
4979 opcode_lookup (char **str
)
4981 char *end
, *base
, *dot
;
4982 const aarch64_cond
*cond
;
4986 /* Scan up to the end of the mnemonic, which must end in white space,
4987 '.', or end of string. */
4989 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4990 if (*end
== '.' && !dot
)
4993 if (end
== base
|| dot
== base
)
4996 inst
.cond
= COND_ALWAYS
;
4998 /* Handle a possible condition. */
5001 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5004 inst
.cond
= cond
->value
;
5020 if (inst
.cond
== COND_ALWAYS
)
5022 /* Look for unaffixed mnemonic. */
5023 return lookup_mnemonic (base
, len
);
5027 /* append ".c" to mnemonic if conditional */
5028 memcpy (condname
, base
, len
);
5029 memcpy (condname
+ len
, ".c", 2);
5032 return lookup_mnemonic (base
, len
);
5038 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5039 to a corresponding operand qualifier. */
5041 static inline aarch64_opnd_qualifier_t
5042 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5044 /* Element size in bytes indexed by vector_el_type. */
5045 const unsigned char ele_size
[5]
5047 const unsigned int ele_base
[5] =
5049 AARCH64_OPND_QLF_V_4B
,
5050 AARCH64_OPND_QLF_V_2H
,
5051 AARCH64_OPND_QLF_V_2S
,
5052 AARCH64_OPND_QLF_V_1D
,
5053 AARCH64_OPND_QLF_V_1Q
5056 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5057 goto vectype_conversion_fail
;
5059 if (vectype
->type
== NT_zero
)
5060 return AARCH64_OPND_QLF_P_Z
;
5061 if (vectype
->type
== NT_merge
)
5062 return AARCH64_OPND_QLF_P_M
;
5064 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5066 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5068 /* Special case S_4B. */
5069 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5070 return AARCH64_OPND_QLF_S_4B
;
5072 /* Vector element register. */
5073 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5077 /* Vector register. */
5078 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5081 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5082 goto vectype_conversion_fail
;
5084 /* The conversion is by calculating the offset from the base operand
5085 qualifier for the vector type. The operand qualifiers are regular
5086 enough that the offset can established by shifting the vector width by
5087 a vector-type dependent amount. */
5089 if (vectype
->type
== NT_b
)
5091 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5093 else if (vectype
->type
>= NT_d
)
5098 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5099 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5100 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5104 vectype_conversion_fail
:
5105 first_error (_("bad vector arrangement type"));
5106 return AARCH64_OPND_QLF_NIL
;
5109 /* Process an optional operand that is found omitted from the assembly line.
5110 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5111 instruction's opcode entry while IDX is the index of this omitted operand.
5115 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5116 int idx
, aarch64_opnd_info
*operand
)
5118 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5119 gas_assert (optional_operand_p (opcode
, idx
));
5120 gas_assert (!operand
->present
);
5124 case AARCH64_OPND_Rd
:
5125 case AARCH64_OPND_Rn
:
5126 case AARCH64_OPND_Rm
:
5127 case AARCH64_OPND_Rt
:
5128 case AARCH64_OPND_Rt2
:
5129 case AARCH64_OPND_Rs
:
5130 case AARCH64_OPND_Ra
:
5131 case AARCH64_OPND_Rt_SYS
:
5132 case AARCH64_OPND_Rd_SP
:
5133 case AARCH64_OPND_Rn_SP
:
5134 case AARCH64_OPND_Rm_SP
:
5135 case AARCH64_OPND_Fd
:
5136 case AARCH64_OPND_Fn
:
5137 case AARCH64_OPND_Fm
:
5138 case AARCH64_OPND_Fa
:
5139 case AARCH64_OPND_Ft
:
5140 case AARCH64_OPND_Ft2
:
5141 case AARCH64_OPND_Sd
:
5142 case AARCH64_OPND_Sn
:
5143 case AARCH64_OPND_Sm
:
5144 case AARCH64_OPND_Va
:
5145 case AARCH64_OPND_Vd
:
5146 case AARCH64_OPND_Vn
:
5147 case AARCH64_OPND_Vm
:
5148 case AARCH64_OPND_VdD1
:
5149 case AARCH64_OPND_VnD1
:
5150 operand
->reg
.regno
= default_value
;
5153 case AARCH64_OPND_Ed
:
5154 case AARCH64_OPND_En
:
5155 case AARCH64_OPND_Em
:
5156 case AARCH64_OPND_Em16
:
5157 case AARCH64_OPND_SM3_IMM2
:
5158 operand
->reglane
.regno
= default_value
;
5161 case AARCH64_OPND_IDX
:
5162 case AARCH64_OPND_BIT_NUM
:
5163 case AARCH64_OPND_IMMR
:
5164 case AARCH64_OPND_IMMS
:
5165 case AARCH64_OPND_SHLL_IMM
:
5166 case AARCH64_OPND_IMM_VLSL
:
5167 case AARCH64_OPND_IMM_VLSR
:
5168 case AARCH64_OPND_CCMP_IMM
:
5169 case AARCH64_OPND_FBITS
:
5170 case AARCH64_OPND_UIMM4
:
5171 case AARCH64_OPND_UIMM3_OP1
:
5172 case AARCH64_OPND_UIMM3_OP2
:
5173 case AARCH64_OPND_IMM
:
5174 case AARCH64_OPND_IMM_2
:
5175 case AARCH64_OPND_WIDTH
:
5176 case AARCH64_OPND_UIMM7
:
5177 case AARCH64_OPND_NZCV
:
5178 case AARCH64_OPND_SVE_PATTERN
:
5179 case AARCH64_OPND_SVE_PRFOP
:
5180 operand
->imm
.value
= default_value
;
5183 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5184 operand
->imm
.value
= default_value
;
5185 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5186 operand
->shifter
.amount
= 1;
5189 case AARCH64_OPND_EXCEPTION
:
5190 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5193 case AARCH64_OPND_BARRIER_ISB
:
5194 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5197 case AARCH64_OPND_BTI_TARGET
:
5198 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5206 /* Process the relocation type for move wide instructions.
5207 Return TRUE on success; otherwise return FALSE. */
5210 process_movw_reloc_info (void)
5215 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5217 if (inst
.base
.opcode
->op
== OP_MOVK
)
5218 switch (inst
.reloc
.type
)
5220 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5221 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5222 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5223 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5224 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5225 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5226 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5227 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5228 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5229 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5230 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5232 (_("the specified relocation type is not allowed for MOVK"));
5238 switch (inst
.reloc
.type
)
5240 case BFD_RELOC_AARCH64_MOVW_G0
:
5241 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5242 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5243 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5244 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5245 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5246 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5247 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5248 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5249 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5250 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5251 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5252 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5255 case BFD_RELOC_AARCH64_MOVW_G1
:
5256 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5257 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5258 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5259 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5260 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5261 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5262 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5263 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5264 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5265 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5266 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5267 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5270 case BFD_RELOC_AARCH64_MOVW_G2
:
5271 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5272 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5273 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5274 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5275 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5276 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5279 set_fatal_syntax_error
5280 (_("the specified relocation type is not allowed for 32-bit "
5286 case BFD_RELOC_AARCH64_MOVW_G3
:
5287 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5290 set_fatal_syntax_error
5291 (_("the specified relocation type is not allowed for 32-bit "
5298 /* More cases should be added when more MOVW-related relocation types
5299 are supported in GAS. */
5300 gas_assert (aarch64_gas_internal_fixup_p ());
5301 /* The shift amount should have already been set by the parser. */
5304 inst
.base
.operands
[1].shifter
.amount
= shift
;
5308 /* A primitive log calculator. */
5310 static inline unsigned int
5311 get_logsz (unsigned int size
)
5313 const unsigned char ls
[16] =
5314 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5320 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5321 return ls
[size
- 1];
5324 /* Determine and return the real reloc type code for an instruction
5325 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5327 static inline bfd_reloc_code_real_type
5328 ldst_lo12_determine_real_reloc_type (void)
5331 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5332 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5334 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5336 BFD_RELOC_AARCH64_LDST8_LO12
,
5337 BFD_RELOC_AARCH64_LDST16_LO12
,
5338 BFD_RELOC_AARCH64_LDST32_LO12
,
5339 BFD_RELOC_AARCH64_LDST64_LO12
,
5340 BFD_RELOC_AARCH64_LDST128_LO12
5343 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5344 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5345 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5346 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5347 BFD_RELOC_AARCH64_NONE
5350 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5351 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5352 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5353 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5354 BFD_RELOC_AARCH64_NONE
5357 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5358 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5359 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5360 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5361 BFD_RELOC_AARCH64_NONE
5364 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5365 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5366 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5367 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5368 BFD_RELOC_AARCH64_NONE
5372 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5373 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5375 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5377 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5379 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5380 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5382 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5384 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5386 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5388 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5389 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5390 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5391 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5392 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5393 gas_assert (logsz
<= 3);
5395 gas_assert (logsz
<= 4);
5397 /* In reloc.c, these pseudo relocation types should be defined in similar
5398 order as above reloc_ldst_lo12 array. Because the array index calculation
5399 below relies on this. */
5400 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5403 /* Check whether a register list REGINFO is valid. The registers must be
5404 numbered in increasing order (modulo 32), in increments of one or two.
5406 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5409 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5412 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5414 uint32_t i
, nb_regs
, prev_regno
, incr
;
5416 nb_regs
= 1 + (reginfo
& 0x3);
5418 prev_regno
= reginfo
& 0x1f;
5419 incr
= accept_alternate
? 2 : 1;
5421 for (i
= 1; i
< nb_regs
; ++i
)
5423 uint32_t curr_regno
;
5425 curr_regno
= reginfo
& 0x1f;
5426 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5428 prev_regno
= curr_regno
;
5434 /* Generic instruction operand parser. This does no encoding and no
5435 semantic validation; it merely squirrels values away in the inst
5436 structure. Returns TRUE or FALSE depending on whether the
5437 specified grammar matched. */
5440 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5443 char *backtrack_pos
= 0;
5444 const enum aarch64_opnd
*operands
= opcode
->operands
;
5445 aarch64_reg_type imm_reg_type
;
5448 skip_whitespace (str
);
5450 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5451 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5453 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5455 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5458 const reg_entry
*reg
;
5459 int comma_skipped_p
= 0;
5460 aarch64_reg_type rtype
;
5461 struct vector_type_el vectype
;
5462 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5463 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5464 aarch64_reg_type reg_type
;
5466 DEBUG_TRACE ("parse operand %d", i
);
5468 /* Assign the operand code. */
5469 info
->type
= operands
[i
];
5471 if (optional_operand_p (opcode
, i
))
5473 /* Remember where we are in case we need to backtrack. */
5474 gas_assert (!backtrack_pos
);
5475 backtrack_pos
= str
;
5478 /* Expect comma between operands; the backtrack mechanism will take
5479 care of cases of omitted optional operand. */
5480 if (i
> 0 && ! skip_past_char (&str
, ','))
5482 set_syntax_error (_("comma expected between operands"));
5486 comma_skipped_p
= 1;
5488 switch (operands
[i
])
5490 case AARCH64_OPND_Rd
:
5491 case AARCH64_OPND_Rn
:
5492 case AARCH64_OPND_Rm
:
5493 case AARCH64_OPND_Rt
:
5494 case AARCH64_OPND_Rt2
:
5495 case AARCH64_OPND_Rs
:
5496 case AARCH64_OPND_Ra
:
5497 case AARCH64_OPND_Rt_SYS
:
5498 case AARCH64_OPND_PAIRREG
:
5499 case AARCH64_OPND_SVE_Rm
:
5500 po_int_reg_or_fail (REG_TYPE_R_Z
);
5503 case AARCH64_OPND_Rd_SP
:
5504 case AARCH64_OPND_Rn_SP
:
5505 case AARCH64_OPND_SVE_Rn_SP
:
5506 case AARCH64_OPND_Rm_SP
:
5507 po_int_reg_or_fail (REG_TYPE_R_SP
);
5510 case AARCH64_OPND_Rm_EXT
:
5511 case AARCH64_OPND_Rm_SFT
:
5512 po_misc_or_fail (parse_shifter_operand
5513 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5515 : SHIFTED_LOGIC_IMM
)));
5516 if (!info
->shifter
.operator_present
)
5518 /* Default to LSL if not present. Libopcodes prefers shifter
5519 kind to be explicit. */
5520 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5521 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5522 /* For Rm_EXT, libopcodes will carry out further check on whether
5523 or not stack pointer is used in the instruction (Recall that
5524 "the extend operator is not optional unless at least one of
5525 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5529 case AARCH64_OPND_Fd
:
5530 case AARCH64_OPND_Fn
:
5531 case AARCH64_OPND_Fm
:
5532 case AARCH64_OPND_Fa
:
5533 case AARCH64_OPND_Ft
:
5534 case AARCH64_OPND_Ft2
:
5535 case AARCH64_OPND_Sd
:
5536 case AARCH64_OPND_Sn
:
5537 case AARCH64_OPND_Sm
:
5538 case AARCH64_OPND_SVE_VZn
:
5539 case AARCH64_OPND_SVE_Vd
:
5540 case AARCH64_OPND_SVE_Vm
:
5541 case AARCH64_OPND_SVE_Vn
:
5542 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5543 if (val
== PARSE_FAIL
)
5545 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5548 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5550 info
->reg
.regno
= val
;
5551 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5554 case AARCH64_OPND_SVE_Pd
:
5555 case AARCH64_OPND_SVE_Pg3
:
5556 case AARCH64_OPND_SVE_Pg4_5
:
5557 case AARCH64_OPND_SVE_Pg4_10
:
5558 case AARCH64_OPND_SVE_Pg4_16
:
5559 case AARCH64_OPND_SVE_Pm
:
5560 case AARCH64_OPND_SVE_Pn
:
5561 case AARCH64_OPND_SVE_Pt
:
5562 reg_type
= REG_TYPE_PN
;
5565 case AARCH64_OPND_SVE_Za_5
:
5566 case AARCH64_OPND_SVE_Za_16
:
5567 case AARCH64_OPND_SVE_Zd
:
5568 case AARCH64_OPND_SVE_Zm_5
:
5569 case AARCH64_OPND_SVE_Zm_16
:
5570 case AARCH64_OPND_SVE_Zn
:
5571 case AARCH64_OPND_SVE_Zt
:
5572 reg_type
= REG_TYPE_ZN
;
5575 case AARCH64_OPND_Va
:
5576 case AARCH64_OPND_Vd
:
5577 case AARCH64_OPND_Vn
:
5578 case AARCH64_OPND_Vm
:
5579 reg_type
= REG_TYPE_VN
;
5581 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5582 if (val
== PARSE_FAIL
)
5584 first_error (_(get_reg_expected_msg (reg_type
)));
5587 if (vectype
.defined
& NTA_HASINDEX
)
5590 info
->reg
.regno
= val
;
5591 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5592 && vectype
.type
== NT_invtype
)
5593 /* Unqualified Pn and Zn registers are allowed in certain
5594 contexts. Rely on F_STRICT qualifier checking to catch
5596 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5599 info
->qualifier
= vectype_to_qualifier (&vectype
);
5600 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5605 case AARCH64_OPND_VdD1
:
5606 case AARCH64_OPND_VnD1
:
5607 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5608 if (val
== PARSE_FAIL
)
5610 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5613 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5615 set_fatal_syntax_error
5616 (_("the top half of a 128-bit FP/SIMD register is expected"));
5619 info
->reg
.regno
= val
;
5620 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5621 here; it is correct for the purpose of encoding/decoding since
5622 only the register number is explicitly encoded in the related
5623 instructions, although this appears a bit hacky. */
5624 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5627 case AARCH64_OPND_SVE_Zm3_INDEX
:
5628 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5629 case AARCH64_OPND_SVE_Zm4_INDEX
:
5630 case AARCH64_OPND_SVE_Zn_INDEX
:
5631 reg_type
= REG_TYPE_ZN
;
5632 goto vector_reg_index
;
5634 case AARCH64_OPND_Ed
:
5635 case AARCH64_OPND_En
:
5636 case AARCH64_OPND_Em
:
5637 case AARCH64_OPND_Em16
:
5638 case AARCH64_OPND_SM3_IMM2
:
5639 reg_type
= REG_TYPE_VN
;
5641 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5642 if (val
== PARSE_FAIL
)
5644 first_error (_(get_reg_expected_msg (reg_type
)));
5647 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5650 info
->reglane
.regno
= val
;
5651 info
->reglane
.index
= vectype
.index
;
5652 info
->qualifier
= vectype_to_qualifier (&vectype
);
5653 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5657 case AARCH64_OPND_SVE_ZnxN
:
5658 case AARCH64_OPND_SVE_ZtxN
:
5659 reg_type
= REG_TYPE_ZN
;
5660 goto vector_reg_list
;
5662 case AARCH64_OPND_LVn
:
5663 case AARCH64_OPND_LVt
:
5664 case AARCH64_OPND_LVt_AL
:
5665 case AARCH64_OPND_LEt
:
5666 reg_type
= REG_TYPE_VN
;
5668 if (reg_type
== REG_TYPE_ZN
5669 && get_opcode_dependent_value (opcode
) == 1
5672 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5673 if (val
== PARSE_FAIL
)
5675 first_error (_(get_reg_expected_msg (reg_type
)));
5678 info
->reglist
.first_regno
= val
;
5679 info
->reglist
.num_regs
= 1;
5683 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5684 if (val
== PARSE_FAIL
)
5686 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5688 set_fatal_syntax_error (_("invalid register list"));
5691 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5692 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5694 if (operands
[i
] == AARCH64_OPND_LEt
)
5696 if (!(vectype
.defined
& NTA_HASINDEX
))
5698 info
->reglist
.has_index
= 1;
5699 info
->reglist
.index
= vectype
.index
;
5703 if (vectype
.defined
& NTA_HASINDEX
)
5705 if (!(vectype
.defined
& NTA_HASTYPE
))
5707 if (reg_type
== REG_TYPE_ZN
)
5708 set_fatal_syntax_error (_("missing type suffix"));
5712 info
->qualifier
= vectype_to_qualifier (&vectype
);
5713 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5717 case AARCH64_OPND_CRn
:
5718 case AARCH64_OPND_CRm
:
5720 char prefix
= *(str
++);
5721 if (prefix
!= 'c' && prefix
!= 'C')
5724 po_imm_nc_or_fail ();
5727 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5730 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5731 info
->imm
.value
= val
;
5735 case AARCH64_OPND_SHLL_IMM
:
5736 case AARCH64_OPND_IMM_VLSR
:
5737 po_imm_or_fail (1, 64);
5738 info
->imm
.value
= val
;
5741 case AARCH64_OPND_CCMP_IMM
:
5742 case AARCH64_OPND_SIMM5
:
5743 case AARCH64_OPND_FBITS
:
5744 case AARCH64_OPND_UIMM4
:
5745 case AARCH64_OPND_UIMM3_OP1
:
5746 case AARCH64_OPND_UIMM3_OP2
:
5747 case AARCH64_OPND_IMM_VLSL
:
5748 case AARCH64_OPND_IMM
:
5749 case AARCH64_OPND_IMM_2
:
5750 case AARCH64_OPND_WIDTH
:
5751 case AARCH64_OPND_SVE_INV_LIMM
:
5752 case AARCH64_OPND_SVE_LIMM
:
5753 case AARCH64_OPND_SVE_LIMM_MOV
:
5754 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5755 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5756 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5757 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5758 case AARCH64_OPND_SVE_SIMM5
:
5759 case AARCH64_OPND_SVE_SIMM5B
:
5760 case AARCH64_OPND_SVE_SIMM6
:
5761 case AARCH64_OPND_SVE_SIMM8
:
5762 case AARCH64_OPND_SVE_UIMM3
:
5763 case AARCH64_OPND_SVE_UIMM7
:
5764 case AARCH64_OPND_SVE_UIMM8
:
5765 case AARCH64_OPND_SVE_UIMM8_53
:
5766 case AARCH64_OPND_IMM_ROT1
:
5767 case AARCH64_OPND_IMM_ROT2
:
5768 case AARCH64_OPND_IMM_ROT3
:
5769 case AARCH64_OPND_SVE_IMM_ROT1
:
5770 case AARCH64_OPND_SVE_IMM_ROT2
:
5771 po_imm_nc_or_fail ();
5772 info
->imm
.value
= val
;
5775 case AARCH64_OPND_SVE_AIMM
:
5776 case AARCH64_OPND_SVE_ASIMM
:
5777 po_imm_nc_or_fail ();
5778 info
->imm
.value
= val
;
5779 skip_whitespace (str
);
5780 if (skip_past_comma (&str
))
5781 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5783 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5786 case AARCH64_OPND_SVE_PATTERN
:
5787 po_enum_or_fail (aarch64_sve_pattern_array
);
5788 info
->imm
.value
= val
;
5791 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5792 po_enum_or_fail (aarch64_sve_pattern_array
);
5793 info
->imm
.value
= val
;
5794 if (skip_past_comma (&str
)
5795 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5797 if (!info
->shifter
.operator_present
)
5799 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5800 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5801 info
->shifter
.amount
= 1;
5805 case AARCH64_OPND_SVE_PRFOP
:
5806 po_enum_or_fail (aarch64_sve_prfop_array
);
5807 info
->imm
.value
= val
;
5810 case AARCH64_OPND_UIMM7
:
5811 po_imm_or_fail (0, 127);
5812 info
->imm
.value
= val
;
5815 case AARCH64_OPND_IDX
:
5816 case AARCH64_OPND_MASK
:
5817 case AARCH64_OPND_BIT_NUM
:
5818 case AARCH64_OPND_IMMR
:
5819 case AARCH64_OPND_IMMS
:
5820 po_imm_or_fail (0, 63);
5821 info
->imm
.value
= val
;
5824 case AARCH64_OPND_IMM0
:
5825 po_imm_nc_or_fail ();
5828 set_fatal_syntax_error (_("immediate zero expected"));
5831 info
->imm
.value
= 0;
5834 case AARCH64_OPND_FPIMM0
:
5837 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5838 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5839 it is probably not worth the effort to support it. */
5840 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5843 || !(res2
= parse_constant_immediate (&str
, &val
,
5846 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5848 info
->imm
.value
= 0;
5849 info
->imm
.is_fp
= 1;
5852 set_fatal_syntax_error (_("immediate zero expected"));
5856 case AARCH64_OPND_IMM_MOV
:
5859 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5860 reg_name_p (str
, REG_TYPE_VN
))
5863 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5865 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5866 later. fix_mov_imm_insn will try to determine a machine
5867 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5868 message if the immediate cannot be moved by a single
5870 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5871 inst
.base
.operands
[i
].skip
= 1;
5875 case AARCH64_OPND_SIMD_IMM
:
5876 case AARCH64_OPND_SIMD_IMM_SFT
:
5877 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5879 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5881 /* need_libopcodes_p */ 1,
5884 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5885 shift, we don't check it here; we leave the checking to
5886 the libopcodes (operand_general_constraint_met_p). By
5887 doing this, we achieve better diagnostics. */
5888 if (skip_past_comma (&str
)
5889 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5891 if (!info
->shifter
.operator_present
5892 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5894 /* Default to LSL if not present. Libopcodes prefers shifter
5895 kind to be explicit. */
5896 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5897 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5901 case AARCH64_OPND_FPIMM
:
5902 case AARCH64_OPND_SIMD_FPIMM
:
5903 case AARCH64_OPND_SVE_FPIMM8
:
5908 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5909 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5910 || !aarch64_imm_float_p (qfloat
))
5913 set_fatal_syntax_error (_("invalid floating-point"
5917 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5918 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5922 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5923 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5924 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5929 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5930 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5933 set_fatal_syntax_error (_("invalid floating-point"
5937 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5938 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5942 case AARCH64_OPND_LIMM
:
5943 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5944 SHIFTED_LOGIC_IMM
));
5945 if (info
->shifter
.operator_present
)
5947 set_fatal_syntax_error
5948 (_("shift not allowed for bitmask immediate"));
5951 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5953 /* need_libopcodes_p */ 1,
5957 case AARCH64_OPND_AIMM
:
5958 if (opcode
->op
== OP_ADD
)
5959 /* ADD may have relocation types. */
5960 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5961 SHIFTED_ARITH_IMM
));
5963 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5964 SHIFTED_ARITH_IMM
));
5965 switch (inst
.reloc
.type
)
5967 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5968 info
->shifter
.amount
= 12;
5970 case BFD_RELOC_UNUSED
:
5971 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5972 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5973 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5974 inst
.reloc
.pc_rel
= 0;
5979 info
->imm
.value
= 0;
5980 if (!info
->shifter
.operator_present
)
5982 /* Default to LSL if not present. Libopcodes prefers shifter
5983 kind to be explicit. */
5984 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5985 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5989 case AARCH64_OPND_HALF
:
5991 /* #<imm16> or relocation. */
5992 int internal_fixup_p
;
5993 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5994 if (internal_fixup_p
)
5995 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5996 skip_whitespace (str
);
5997 if (skip_past_comma (&str
))
5999 /* {, LSL #<shift>} */
6000 if (! aarch64_gas_internal_fixup_p ())
6002 set_fatal_syntax_error (_("can't mix relocation modifier "
6003 "with explicit shift"));
6006 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6009 inst
.base
.operands
[i
].shifter
.amount
= 0;
6010 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6011 inst
.base
.operands
[i
].imm
.value
= 0;
6012 if (! process_movw_reloc_info ())
6017 case AARCH64_OPND_EXCEPTION
:
6018 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6020 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6022 /* need_libopcodes_p */ 0,
6026 case AARCH64_OPND_NZCV
:
6028 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6032 info
->imm
.value
= nzcv
->value
;
6035 po_imm_or_fail (0, 15);
6036 info
->imm
.value
= val
;
6040 case AARCH64_OPND_COND
:
6041 case AARCH64_OPND_COND1
:
6046 while (ISALPHA (*str
));
6047 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6048 if (info
->cond
== NULL
)
6050 set_syntax_error (_("invalid condition"));
6053 else if (operands
[i
] == AARCH64_OPND_COND1
6054 && (info
->cond
->value
& 0xe) == 0xe)
6056 /* Do not allow AL or NV. */
6057 set_default_error ();
6063 case AARCH64_OPND_ADDR_ADRP
:
6064 po_misc_or_fail (parse_adrp (&str
));
6065 /* Clear the value as operand needs to be relocated. */
6066 info
->imm
.value
= 0;
6069 case AARCH64_OPND_ADDR_PCREL14
:
6070 case AARCH64_OPND_ADDR_PCREL19
:
6071 case AARCH64_OPND_ADDR_PCREL21
:
6072 case AARCH64_OPND_ADDR_PCREL26
:
6073 po_misc_or_fail (parse_address (&str
, info
));
6074 if (!info
->addr
.pcrel
)
6076 set_syntax_error (_("invalid pc-relative address"));
6079 if (inst
.gen_lit_pool
6080 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6082 /* Only permit "=value" in the literal load instructions.
6083 The literal will be generated by programmer_friendly_fixup. */
6084 set_syntax_error (_("invalid use of \"=immediate\""));
6087 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6089 set_syntax_error (_("unrecognized relocation suffix"));
6092 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6094 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6095 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6099 info
->imm
.value
= 0;
6100 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6101 switch (opcode
->iclass
)
6105 /* e.g. CBZ or B.COND */
6106 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6107 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6111 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6112 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6116 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6118 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6119 : BFD_RELOC_AARCH64_JUMP26
;
6122 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6123 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6126 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6127 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6133 inst
.reloc
.pc_rel
= 1;
6137 case AARCH64_OPND_ADDR_SIMPLE
:
6138 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6140 /* [<Xn|SP>{, #<simm>}] */
6142 /* First use the normal address-parsing routines, to get
6143 the usual syntax errors. */
6144 po_misc_or_fail (parse_address (&str
, info
));
6145 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6146 || !info
->addr
.preind
|| info
->addr
.postind
6147 || info
->addr
.writeback
)
6149 set_syntax_error (_("invalid addressing mode"));
6153 /* Then retry, matching the specific syntax of these addresses. */
6155 po_char_or_fail ('[');
6156 po_reg_or_fail (REG_TYPE_R64_SP
);
6157 /* Accept optional ", #0". */
6158 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6159 && skip_past_char (&str
, ','))
6161 skip_past_char (&str
, '#');
6162 if (! skip_past_char (&str
, '0'))
6164 set_fatal_syntax_error
6165 (_("the optional immediate offset can only be 0"));
6169 po_char_or_fail (']');
6173 case AARCH64_OPND_ADDR_REGOFF
:
6174 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6175 po_misc_or_fail (parse_address (&str
, info
));
6177 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6178 || !info
->addr
.preind
|| info
->addr
.postind
6179 || info
->addr
.writeback
)
6181 set_syntax_error (_("invalid addressing mode"));
6184 if (!info
->shifter
.operator_present
)
6186 /* Default to LSL if not present. Libopcodes prefers shifter
6187 kind to be explicit. */
6188 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6189 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6191 /* Qualifier to be deduced by libopcodes. */
6194 case AARCH64_OPND_ADDR_SIMM7
:
6195 po_misc_or_fail (parse_address (&str
, info
));
6196 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6197 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6199 set_syntax_error (_("invalid addressing mode"));
6202 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6204 set_syntax_error (_("relocation not allowed"));
6207 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6209 /* need_libopcodes_p */ 1,
6213 case AARCH64_OPND_ADDR_SIMM9
:
6214 case AARCH64_OPND_ADDR_SIMM9_2
:
6215 po_misc_or_fail (parse_address (&str
, info
));
6216 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6217 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6218 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6219 && info
->addr
.writeback
))
6221 set_syntax_error (_("invalid addressing mode"));
6224 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6226 set_syntax_error (_("relocation not allowed"));
6229 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6231 /* need_libopcodes_p */ 1,
6235 case AARCH64_OPND_ADDR_SIMM10
:
6236 case AARCH64_OPND_ADDR_OFFSET
:
6237 po_misc_or_fail (parse_address (&str
, info
));
6238 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6239 || !info
->addr
.preind
|| info
->addr
.postind
)
6241 set_syntax_error (_("invalid addressing mode"));
6244 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6246 set_syntax_error (_("relocation not allowed"));
6249 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6251 /* need_libopcodes_p */ 1,
6255 case AARCH64_OPND_ADDR_UIMM12
:
6256 po_misc_or_fail (parse_address (&str
, info
));
6257 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6258 || !info
->addr
.preind
|| info
->addr
.writeback
)
6260 set_syntax_error (_("invalid addressing mode"));
6263 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6264 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6265 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6267 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6269 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6271 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6273 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6274 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6275 /* Leave qualifier to be determined by libopcodes. */
6278 case AARCH64_OPND_SIMD_ADDR_POST
:
6279 /* [<Xn|SP>], <Xm|#<amount>> */
6280 po_misc_or_fail (parse_address (&str
, info
));
6281 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6283 set_syntax_error (_("invalid addressing mode"));
6286 if (!info
->addr
.offset
.is_reg
)
6288 if (inst
.reloc
.exp
.X_op
== O_constant
)
6289 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6292 set_fatal_syntax_error
6293 (_("writeback value must be an immediate constant"));
6300 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6301 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6302 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6303 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6304 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6305 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6306 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6307 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6308 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6309 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6310 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6311 /* [X<n>{, #imm, MUL VL}]
6313 but recognizing SVE registers. */
6314 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6315 &offset_qualifier
));
6316 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6318 set_syntax_error (_("invalid addressing mode"));
6322 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6323 || !info
->addr
.preind
|| info
->addr
.writeback
)
6325 set_syntax_error (_("invalid addressing mode"));
6328 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6329 || inst
.reloc
.exp
.X_op
!= O_constant
)
6331 /* Make sure this has priority over
6332 "invalid addressing mode". */
6333 set_fatal_syntax_error (_("constant offset required"));
6336 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6339 case AARCH64_OPND_SVE_ADDR_R
:
6340 /* [<Xn|SP>{, <R><m>}]
6341 but recognizing SVE registers. */
6342 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6343 &offset_qualifier
));
6344 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6346 offset_qualifier
= AARCH64_OPND_QLF_X
;
6347 info
->addr
.offset
.is_reg
= 1;
6348 info
->addr
.offset
.regno
= 31;
6350 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6351 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6353 set_syntax_error (_("invalid addressing mode"));
6358 case AARCH64_OPND_SVE_ADDR_RR
:
6359 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6360 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6361 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6362 case AARCH64_OPND_SVE_ADDR_RX
:
6363 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6364 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6365 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6366 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6367 but recognizing SVE registers. */
6368 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6369 &offset_qualifier
));
6370 if (base_qualifier
!= AARCH64_OPND_QLF_X
6371 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6373 set_syntax_error (_("invalid addressing mode"));
6378 case AARCH64_OPND_SVE_ADDR_RZ
:
6379 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6380 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6381 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6382 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6383 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6384 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6385 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6386 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6387 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6388 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6389 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6390 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6391 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6392 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6393 &offset_qualifier
));
6394 if (base_qualifier
!= AARCH64_OPND_QLF_X
6395 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6396 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6398 set_syntax_error (_("invalid addressing mode"));
6401 info
->qualifier
= offset_qualifier
;
6404 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6405 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6406 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6407 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6408 /* [Z<n>.<T>{, #imm}] */
6409 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6410 &offset_qualifier
));
6411 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6412 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6414 set_syntax_error (_("invalid addressing mode"));
6417 info
->qualifier
= base_qualifier
;
6420 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6421 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6422 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6423 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6424 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6428 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6430 here since we get better error messages by leaving it to
6431 the qualifier checking routines. */
6432 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6433 &offset_qualifier
));
6434 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6435 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6436 || offset_qualifier
!= base_qualifier
)
6438 set_syntax_error (_("invalid addressing mode"));
6441 info
->qualifier
= base_qualifier
;
6444 case AARCH64_OPND_SYSREG
:
6446 uint32_t sysreg_flags
;
6447 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6448 &sysreg_flags
)) == PARSE_FAIL
)
6450 set_syntax_error (_("unknown or missing system register name"));
6453 inst
.base
.operands
[i
].sysreg
.value
= val
;
6454 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6458 case AARCH64_OPND_PSTATEFIELD
:
6459 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6462 set_syntax_error (_("unknown or missing PSTATE field name"));
6465 inst
.base
.operands
[i
].pstatefield
= val
;
6468 case AARCH64_OPND_SYSREG_IC
:
6469 inst
.base
.operands
[i
].sysins_op
=
6470 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6473 case AARCH64_OPND_SYSREG_DC
:
6474 inst
.base
.operands
[i
].sysins_op
=
6475 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6478 case AARCH64_OPND_SYSREG_AT
:
6479 inst
.base
.operands
[i
].sysins_op
=
6480 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6483 case AARCH64_OPND_SYSREG_SR
:
6484 inst
.base
.operands
[i
].sysins_op
=
6485 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6488 case AARCH64_OPND_SYSREG_TLBI
:
6489 inst
.base
.operands
[i
].sysins_op
=
6490 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6492 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6494 set_fatal_syntax_error ( _("unknown or missing operation name"));
6499 case AARCH64_OPND_BARRIER
:
6500 case AARCH64_OPND_BARRIER_ISB
:
6501 val
= parse_barrier (&str
);
6502 if (val
!= PARSE_FAIL
6503 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6505 /* ISB only accepts options name 'sy'. */
6507 (_("the specified option is not accepted in ISB"));
6508 /* Turn off backtrack as this optional operand is present. */
6512 /* This is an extension to accept a 0..15 immediate. */
6513 if (val
== PARSE_FAIL
)
6514 po_imm_or_fail (0, 15);
6515 info
->barrier
= aarch64_barrier_options
+ val
;
6518 case AARCH64_OPND_PRFOP
:
6519 val
= parse_pldop (&str
);
6520 /* This is an extension to accept a 0..31 immediate. */
6521 if (val
== PARSE_FAIL
)
6522 po_imm_or_fail (0, 31);
6523 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6526 case AARCH64_OPND_BARRIER_PSB
:
6527 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6528 if (val
== PARSE_FAIL
)
6532 case AARCH64_OPND_BTI_TARGET
:
6533 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6534 if (val
== PARSE_FAIL
)
6539 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6542 /* If we get here, this operand was successfully parsed. */
6543 inst
.base
.operands
[i
].present
= 1;
6547 /* The parse routine should already have set the error, but in case
6548 not, set a default one here. */
6550 set_default_error ();
6552 if (! backtrack_pos
)
6553 goto parse_operands_return
;
6556 /* We reach here because this operand is marked as optional, and
6557 either no operand was supplied or the operand was supplied but it
6558 was syntactically incorrect. In the latter case we report an
6559 error. In the former case we perform a few more checks before
6560 dropping through to the code to insert the default operand. */
6562 char *tmp
= backtrack_pos
;
6563 char endchar
= END_OF_INSN
;
6565 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6567 skip_past_char (&tmp
, ',');
6569 if (*tmp
!= endchar
)
6570 /* The user has supplied an operand in the wrong format. */
6571 goto parse_operands_return
;
6573 /* Make sure there is not a comma before the optional operand.
6574 For example the fifth operand of 'sys' is optional:
6576 sys #0,c0,c0,#0, <--- wrong
6577 sys #0,c0,c0,#0 <--- correct. */
6578 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6580 set_fatal_syntax_error
6581 (_("unexpected comma before the omitted optional operand"));
6582 goto parse_operands_return
;
6586 /* Reaching here means we are dealing with an optional operand that is
6587 omitted from the assembly line. */
6588 gas_assert (optional_operand_p (opcode
, i
));
6590 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6592 /* Try again, skipping the optional operand at backtrack_pos. */
6593 str
= backtrack_pos
;
6596 /* Clear any error record after the omitted optional operand has been
6597 successfully handled. */
6601 /* Check if we have parsed all the operands. */
6602 if (*str
!= '\0' && ! error_p ())
6604 /* Set I to the index of the last present operand; this is
6605 for the purpose of diagnostics. */
6606 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6608 set_fatal_syntax_error
6609 (_("unexpected characters following instruction"));
6612 parse_operands_return
:
6616 DEBUG_TRACE ("parsing FAIL: %s - %s",
6617 operand_mismatch_kind_names
[get_error_kind ()],
6618 get_error_message ());
6619 /* Record the operand error properly; this is useful when there
6620 are multiple instruction templates for a mnemonic name, so that
6621 later on, we can select the error that most closely describes
6623 record_operand_error (opcode
, i
, get_error_kind (),
6624 get_error_message ());
6629 DEBUG_TRACE ("parsing SUCCESS");
6634 /* It does some fix-up to provide some programmer friendly feature while
6635 keeping the libopcodes happy, i.e. libopcodes only accepts
6636 the preferred architectural syntax.
6637 Return FALSE if there is any failure; otherwise return TRUE. */
6640 programmer_friendly_fixup (aarch64_instruction
*instr
)
6642 aarch64_inst
*base
= &instr
->base
;
6643 const aarch64_opcode
*opcode
= base
->opcode
;
6644 enum aarch64_op op
= opcode
->op
;
6645 aarch64_opnd_info
*operands
= base
->operands
;
6647 DEBUG_TRACE ("enter");
6649 switch (opcode
->iclass
)
6652 /* TBNZ Xn|Wn, #uimm6, label
6653 Test and Branch Not Zero: conditionally jumps to label if bit number
6654 uimm6 in register Xn is not zero. The bit number implies the width of
6655 the register, which may be written and should be disassembled as Wn if
6656 uimm is less than 32. */
6657 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6659 if (operands
[1].imm
.value
>= 32)
6661 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6665 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6669 /* LDR Wt, label | =value
6670 As a convenience assemblers will typically permit the notation
6671 "=value" in conjunction with the pc-relative literal load instructions
6672 to automatically place an immediate value or symbolic address in a
6673 nearby literal pool and generate a hidden label which references it.
6674 ISREG has been set to 0 in the case of =value. */
6675 if (instr
->gen_lit_pool
6676 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6678 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6679 if (op
== OP_LDRSW_LIT
)
6681 if (instr
->reloc
.exp
.X_op
!= O_constant
6682 && instr
->reloc
.exp
.X_op
!= O_big
6683 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6685 record_operand_error (opcode
, 1,
6686 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6687 _("constant expression expected"));
6690 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6692 record_operand_error (opcode
, 1,
6693 AARCH64_OPDE_OTHER_ERROR
,
6694 _("literal pool insertion failed"));
6702 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6703 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6704 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6705 A programmer-friendly assembler should accept a destination Xd in
6706 place of Wd, however that is not the preferred form for disassembly.
6708 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6709 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6710 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6711 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6716 /* In the 64-bit form, the final register operand is written as Wm
6717 for all but the (possibly omitted) UXTX/LSL and SXTX
6719 As a programmer-friendly assembler, we accept e.g.
6720 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6721 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6722 int idx
= aarch64_operand_index (opcode
->operands
,
6723 AARCH64_OPND_Rm_EXT
);
6724 gas_assert (idx
== 1 || idx
== 2);
6725 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6726 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6727 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6728 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6729 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6730 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6738 DEBUG_TRACE ("exit with SUCCESS");
6742 /* Check for loads and stores that will cause unpredictable behavior. */
6745 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6747 aarch64_inst
*base
= &instr
->base
;
6748 const aarch64_opcode
*opcode
= base
->opcode
;
6749 const aarch64_opnd_info
*opnds
= base
->operands
;
6750 switch (opcode
->iclass
)
6757 /* Loading/storing the base register is unpredictable if writeback. */
6758 if ((aarch64_get_operand_class (opnds
[0].type
)
6759 == AARCH64_OPND_CLASS_INT_REG
)
6760 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6761 && opnds
[1].addr
.base_regno
!= REG_SP
6762 && opnds
[1].addr
.writeback
)
6763 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6766 case ldstnapair_offs
:
6767 case ldstpair_indexed
:
6768 /* Loading/storing the base register is unpredictable if writeback. */
6769 if ((aarch64_get_operand_class (opnds
[0].type
)
6770 == AARCH64_OPND_CLASS_INT_REG
)
6771 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6772 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6773 && opnds
[2].addr
.base_regno
!= REG_SP
6774 && opnds
[2].addr
.writeback
)
6775 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6776 /* Load operations must load different registers. */
6777 if ((opcode
->opcode
& (1 << 22))
6778 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6779 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6783 /* It is unpredictable if the destination and status registers are the
6785 if ((aarch64_get_operand_class (opnds
[0].type
)
6786 == AARCH64_OPND_CLASS_INT_REG
)
6787 && (aarch64_get_operand_class (opnds
[1].type
)
6788 == AARCH64_OPND_CLASS_INT_REG
)
6789 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6790 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6791 as_warn (_("unpredictable: identical transfer and status registers"
6803 force_automatic_sequence_close (void)
6805 if (now_instr_sequence
.instr
)
6807 as_warn (_("previous `%s' sequence has not been closed"),
6808 now_instr_sequence
.instr
->opcode
->name
);
6809 init_insn_sequence (NULL
, &now_instr_sequence
);
6813 /* A wrapper function to interface with libopcodes on encoding and
6814 record the error message if there is any.
6816 Return TRUE on success; otherwise return FALSE. */
6819 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6822 aarch64_operand_error error_info
;
6823 memset (&error_info
, '\0', sizeof (error_info
));
6824 error_info
.kind
= AARCH64_OPDE_NIL
;
6825 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6826 && !error_info
.non_fatal
)
6829 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6830 record_operand_error_info (opcode
, &error_info
);
6831 return error_info
.non_fatal
;
6834 #ifdef DEBUG_AARCH64
6836 dump_opcode_operands (const aarch64_opcode
*opcode
)
6839 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6841 aarch64_verbose ("\t\t opnd%d: %s", i
,
6842 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6843 ? aarch64_get_operand_name (opcode
->operands
[i
])
6844 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6848 #endif /* DEBUG_AARCH64 */
6850 /* This is the guts of the machine-dependent assembler. STR points to a
6851 machine dependent instruction. This function is supposed to emit
6852 the frags/bytes it assembles to. */
6855 md_assemble (char *str
)
6858 templates
*template;
6859 aarch64_opcode
*opcode
;
6860 aarch64_inst
*inst_base
;
6861 unsigned saved_cond
;
6863 /* Align the previous label if needed. */
6864 if (last_label_seen
!= NULL
)
6866 symbol_set_frag (last_label_seen
, frag_now
);
6867 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6868 S_SET_SEGMENT (last_label_seen
, now_seg
);
6871 /* Update the current insn_sequence from the segment. */
6872 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6874 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6876 DEBUG_TRACE ("\n\n");
6877 DEBUG_TRACE ("==============================");
6878 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6880 template = opcode_lookup (&p
);
6883 /* It wasn't an instruction, but it might be a register alias of
6884 the form alias .req reg directive. */
6885 if (!create_register_alias (str
, p
))
6886 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6891 skip_whitespace (p
);
6894 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6895 get_mnemonic_name (str
), str
);
6899 init_operand_error_report ();
6901 /* Sections are assumed to start aligned. In executable section, there is no
6902 MAP_DATA symbol pending. So we only align the address during
6903 MAP_DATA --> MAP_INSN transition.
6904 For other sections, this is not guaranteed. */
6905 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6906 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6907 frag_align_code (2, 0);
6909 saved_cond
= inst
.cond
;
6910 reset_aarch64_instruction (&inst
);
6911 inst
.cond
= saved_cond
;
6913 /* Iterate through all opcode entries with the same mnemonic name. */
6916 opcode
= template->opcode
;
6918 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6919 #ifdef DEBUG_AARCH64
6921 dump_opcode_operands (opcode
);
6922 #endif /* DEBUG_AARCH64 */
6924 mapping_state (MAP_INSN
);
6926 inst_base
= &inst
.base
;
6927 inst_base
->opcode
= opcode
;
6929 /* Truly conditionally executed instructions, e.g. b.cond. */
6930 if (opcode
->flags
& F_COND
)
6932 gas_assert (inst
.cond
!= COND_ALWAYS
);
6933 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6934 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6936 else if (inst
.cond
!= COND_ALWAYS
)
6938 /* It shouldn't arrive here, where the assembly looks like a
6939 conditional instruction but the found opcode is unconditional. */
6944 if (parse_operands (p
, opcode
)
6945 && programmer_friendly_fixup (&inst
)
6946 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6948 /* Check that this instruction is supported for this CPU. */
6949 if (!opcode
->avariant
6950 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6952 as_bad (_("selected processor does not support `%s'"), str
);
6956 warn_unpredictable_ldst (&inst
, str
);
6958 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6959 || !inst
.reloc
.need_libopcodes_p
)
6963 /* If there is relocation generated for the instruction,
6964 store the instruction information for the future fix-up. */
6965 struct aarch64_inst
*copy
;
6966 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6967 copy
= XNEW (struct aarch64_inst
);
6968 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6972 /* Issue non-fatal messages if any. */
6973 output_operand_error_report (str
, TRUE
);
6977 template = template->next
;
6978 if (template != NULL
)
6980 reset_aarch64_instruction (&inst
);
6981 inst
.cond
= saved_cond
;
6984 while (template != NULL
);
6986 /* Issue the error messages if any. */
6987 output_operand_error_report (str
, FALSE
);
6990 /* Various frobbings of labels and their addresses. */
6993 aarch64_start_line_hook (void)
6995 last_label_seen
= NULL
;
6999 aarch64_frob_label (symbolS
* sym
)
7001 last_label_seen
= sym
;
7003 dwarf2_emit_label (sym
);
7007 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7009 /* Check to see if we have a block to close. */
7010 force_automatic_sequence_close ();
7014 aarch64_data_in_code (void)
7016 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7018 *input_line_pointer
= '/';
7019 input_line_pointer
+= 5;
7020 *input_line_pointer
= 0;
7028 aarch64_canonicalize_symbol_name (char *name
)
7032 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7033 *(name
+ len
- 5) = 0;
7038 /* Table of all register names defined by default. The user can
7039 define additional names with .req. Note that all register names
7040 should appear in both upper and lowercase variants. Some registers
7041 also have mixed-case names. */
7043 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7044 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7045 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7046 #define REGSET16(p,t) \
7047 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7048 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7049 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7050 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7051 #define REGSET31(p,t) \
7053 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7054 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7055 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7056 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7057 #define REGSET(p,t) \
7058 REGSET31(p,t), REGNUM(p,31,t)
7060 /* These go into aarch64_reg_hsh hash-table. */
7061 static const reg_entry reg_names
[] = {
7062 /* Integer registers. */
7063 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7064 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7066 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7067 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7068 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7069 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7070 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7071 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7073 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7074 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7076 /* Floating-point single precision registers. */
7077 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7079 /* Floating-point double precision registers. */
7080 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7082 /* Floating-point half precision registers. */
7083 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7085 /* Floating-point byte precision registers. */
7086 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7088 /* Floating-point quad precision registers. */
7089 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7091 /* FP/SIMD registers. */
7092 REGSET (v
, VN
), REGSET (V
, VN
),
7094 /* SVE vector registers. */
7095 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7097 /* SVE predicate registers. */
7098 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7116 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7117 static const asm_nzcv nzcv_names
[] = {
7118 {"nzcv", B (n
, z
, c
, v
)},
7119 {"nzcV", B (n
, z
, c
, V
)},
7120 {"nzCv", B (n
, z
, C
, v
)},
7121 {"nzCV", B (n
, z
, C
, V
)},
7122 {"nZcv", B (n
, Z
, c
, v
)},
7123 {"nZcV", B (n
, Z
, c
, V
)},
7124 {"nZCv", B (n
, Z
, C
, v
)},
7125 {"nZCV", B (n
, Z
, C
, V
)},
7126 {"Nzcv", B (N
, z
, c
, v
)},
7127 {"NzcV", B (N
, z
, c
, V
)},
7128 {"NzCv", B (N
, z
, C
, v
)},
7129 {"NzCV", B (N
, z
, C
, V
)},
7130 {"NZcv", B (N
, Z
, c
, v
)},
7131 {"NZcV", B (N
, Z
, c
, V
)},
7132 {"NZCv", B (N
, Z
, C
, v
)},
7133 {"NZCV", B (N
, Z
, C
, V
)}
7146 /* MD interface: bits in the object file. */
7148 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7149 for use in the a.out file, and stores them in the array pointed to by buf.
7150 This knows about the endian-ness of the target machine and does
7151 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7152 2 (short) and 4 (long) Floating numbers are put out as a series of
7153 LITTLENUMS (shorts, here at least). */
7156 md_number_to_chars (char *buf
, valueT val
, int n
)
7158 if (target_big_endian
)
7159 number_to_chars_bigendian (buf
, val
, n
);
7161 number_to_chars_littleendian (buf
, val
, n
);
7164 /* MD interface: Sections. */
7166 /* Estimate the size of a frag before relaxing. Assume everything fits in
7170 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7176 /* Round up a section size to the appropriate boundary. */
7179 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7184 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7185 of an rs_align_code fragment.
7187 Here we fill the frag with the appropriate info for padding the
7188 output stream. The resulting frag will consist of a fixed (fr_fix)
7189 and of a repeating (fr_var) part.
7191 The fixed content is always emitted before the repeating content and
7192 these two parts are used as follows in constructing the output:
7193 - the fixed part will be used to align to a valid instruction word
7194 boundary, in case that we start at a misaligned address; as no
7195 executable instruction can live at the misaligned location, we
7196 simply fill with zeros;
7197 - the variable part will be used to cover the remaining padding and
7198 we fill using the AArch64 NOP instruction.
7200 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7201 enough storage space for up to 3 bytes for padding the back to a valid
7202 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7205 aarch64_handle_align (fragS
* fragP
)
7207 /* NOP = d503201f */
7208 /* AArch64 instructions are always little-endian. */
7209 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7211 int bytes
, fix
, noop_size
;
7214 if (fragP
->fr_type
!= rs_align_code
)
7217 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7218 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7221 gas_assert (fragP
->tc_frag_data
.recorded
);
7224 noop_size
= sizeof (aarch64_noop
);
7226 fix
= bytes
& (noop_size
- 1);
7230 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7234 fragP
->fr_fix
+= fix
;
7238 memcpy (p
, aarch64_noop
, noop_size
);
7239 fragP
->fr_var
= noop_size
;
7242 /* Perform target specific initialisation of a frag.
7243 Note - despite the name this initialisation is not done when the frag
7244 is created, but only when its type is assigned. A frag can be created
7245 and used a long time before its type is set, so beware of assuming that
7246 this initialisation is performed first. */
7250 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7251 int max_chars ATTRIBUTE_UNUSED
)
7255 #else /* OBJ_ELF is defined. */
7257 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7259 /* Record a mapping symbol for alignment frags. We will delete this
7260 later if the alignment ends up empty. */
7261 if (!fragP
->tc_frag_data
.recorded
)
7262 fragP
->tc_frag_data
.recorded
= 1;
7264 /* PR 21809: Do not set a mapping state for debug sections
7265 - it just confuses other tools. */
7266 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7269 switch (fragP
->fr_type
)
7273 mapping_state_2 (MAP_DATA
, max_chars
);
7276 /* PR 20364: We can get alignment frags in code sections,
7277 so do not just assume that we should use the MAP_DATA state. */
7278 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7281 mapping_state_2 (MAP_INSN
, max_chars
);
7288 /* Initialize the DWARF-2 unwind information for this procedure. */
7291 tc_aarch64_frame_initial_instructions (void)
7293 cfi_add_CFA_def_cfa (REG_SP
, 0);
7295 #endif /* OBJ_ELF */
7297 /* Convert REGNAME to a DWARF-2 register number. */
7300 tc_aarch64_regname_to_dw2regnum (char *regname
)
7302 const reg_entry
*reg
= parse_reg (®name
);
7308 case REG_TYPE_SP_32
:
7309 case REG_TYPE_SP_64
:
7319 return reg
->number
+ 64;
7327 /* Implement DWARF2_ADDR_SIZE. */
7330 aarch64_dwarf2_addr_size (void)
7332 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7336 return bfd_arch_bits_per_address (stdoutput
) / 8;
7339 /* MD interface: Symbol and relocation handling. */
7341 /* Return the address within the segment that a PC-relative fixup is
7342 relative to. For AArch64 PC-relative fixups applied to instructions
7343 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7346 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7348 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7350 /* If this is pc-relative and we are going to emit a relocation
7351 then we just want to put out any pipeline compensation that the linker
7352 will need. Otherwise we want to use the calculated base. */
7354 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7355 || aarch64_force_relocation (fixP
)))
7358 /* AArch64 should be consistent for all pc-relative relocations. */
7359 return base
+ AARCH64_PCREL_OFFSET
;
7362 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7363 Otherwise we have no need to default values of symbols. */
7366 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7369 if (name
[0] == '_' && name
[1] == 'G'
7370 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7374 if (symbol_find (name
))
7375 as_bad (_("GOT already in the symbol table"));
7377 GOT_symbol
= symbol_new (name
, undefined_section
,
7378 (valueT
) 0, &zero_address_frag
);
7388 /* Return non-zero if the indicated VALUE has overflowed the maximum
7389 range expressible by a unsigned number with the indicated number of
7393 unsigned_overflow (valueT value
, unsigned bits
)
7396 if (bits
>= sizeof (valueT
) * 8)
7398 lim
= (valueT
) 1 << bits
;
7399 return (value
>= lim
);
7403 /* Return non-zero if the indicated VALUE has overflowed the maximum
7404 range expressible by an signed number with the indicated number of
7408 signed_overflow (offsetT value
, unsigned bits
)
7411 if (bits
>= sizeof (offsetT
) * 8)
7413 lim
= (offsetT
) 1 << (bits
- 1);
7414 return (value
< -lim
|| value
>= lim
);
7417 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7418 unsigned immediate offset load/store instruction, try to encode it as
7419 an unscaled, 9-bit, signed immediate offset load/store instruction.
7420 Return TRUE if it is successful; otherwise return FALSE.
7422 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7423 in response to the standard LDR/STR mnemonics when the immediate offset is
7424 unambiguous, i.e. when it is negative or unaligned. */
7427 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7430 enum aarch64_op new_op
;
7431 const aarch64_opcode
*new_opcode
;
7433 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7435 switch (instr
->opcode
->op
)
7437 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7438 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7439 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7440 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7441 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7442 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7443 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7444 case OP_STR_POS
: new_op
= OP_STUR
; break;
7445 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7446 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7447 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7448 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7449 default: new_op
= OP_NIL
; break;
7452 if (new_op
== OP_NIL
)
7455 new_opcode
= aarch64_get_opcode (new_op
);
7456 gas_assert (new_opcode
!= NULL
);
7458 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7459 instr
->opcode
->op
, new_opcode
->op
);
7461 aarch64_replace_opcode (instr
, new_opcode
);
7463 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7464 qualifier matching may fail because the out-of-date qualifier will
7465 prevent the operand being updated with a new and correct qualifier. */
7466 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7467 AARCH64_OPND_ADDR_SIMM9
);
7468 gas_assert (idx
== 1);
7469 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7471 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7473 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7480 /* Called by fix_insn to fix a MOV immediate alias instruction.
7482 Operand for a generic move immediate instruction, which is an alias
7483 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7484 a 32-bit/64-bit immediate value into general register. An assembler error
7485 shall result if the immediate cannot be created by a single one of these
7486 instructions. If there is a choice, then to ensure reversability an
7487 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7490 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7492 const aarch64_opcode
*opcode
;
7494 /* Need to check if the destination is SP/ZR. The check has to be done
7495 before any aarch64_replace_opcode. */
7496 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7497 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7499 instr
->operands
[1].imm
.value
= value
;
7500 instr
->operands
[1].skip
= 0;
7504 /* Try the MOVZ alias. */
7505 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7506 aarch64_replace_opcode (instr
, opcode
);
7507 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7508 &instr
->value
, NULL
, NULL
, insn_sequence
))
7510 put_aarch64_insn (buf
, instr
->value
);
7513 /* Try the MOVK alias. */
7514 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7515 aarch64_replace_opcode (instr
, opcode
);
7516 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7517 &instr
->value
, NULL
, NULL
, insn_sequence
))
7519 put_aarch64_insn (buf
, instr
->value
);
7524 if (try_mov_bitmask_p
)
7526 /* Try the ORR alias. */
7527 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7528 aarch64_replace_opcode (instr
, opcode
);
7529 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7530 &instr
->value
, NULL
, NULL
, insn_sequence
))
7532 put_aarch64_insn (buf
, instr
->value
);
7537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7538 _("immediate cannot be moved by a single instruction"));
7541 /* An instruction operand which is immediate related may have symbol used
7542 in the assembly, e.g.
7545 .set u32, 0x00ffff00
7547 At the time when the assembly instruction is parsed, a referenced symbol,
7548 like 'u32' in the above example may not have been seen; a fixS is created
7549 in such a case and is handled here after symbols have been resolved.
7550 Instruction is fixed up with VALUE using the information in *FIXP plus
7551 extra information in FLAGS.
7553 This function is called by md_apply_fix to fix up instructions that need
7554 a fix-up described above but does not involve any linker-time relocation. */
7557 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7561 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7562 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7563 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7567 /* Now the instruction is about to be fixed-up, so the operand that
7568 was previously marked as 'ignored' needs to be unmarked in order
7569 to get the encoding done properly. */
7570 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7571 new_inst
->operands
[idx
].skip
= 0;
7574 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7578 case AARCH64_OPND_EXCEPTION
:
7579 if (unsigned_overflow (value
, 16))
7580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7581 _("immediate out of range"));
7582 insn
= get_aarch64_insn (buf
);
7583 insn
|= encode_svc_imm (value
);
7584 put_aarch64_insn (buf
, insn
);
7587 case AARCH64_OPND_AIMM
:
7588 /* ADD or SUB with immediate.
7589 NOTE this assumes we come here with a add/sub shifted reg encoding
7590 3 322|2222|2 2 2 21111 111111
7591 1 098|7654|3 2 1 09876 543210 98765 43210
7592 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7593 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7594 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7595 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7597 3 322|2222|2 2 221111111111
7598 1 098|7654|3 2 109876543210 98765 43210
7599 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7600 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7601 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7602 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7603 Fields sf Rn Rd are already set. */
7604 insn
= get_aarch64_insn (buf
);
7608 insn
= reencode_addsub_switch_add_sub (insn
);
7612 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7613 && unsigned_overflow (value
, 12))
7615 /* Try to shift the value by 12 to make it fit. */
7616 if (((value
>> 12) << 12) == value
7617 && ! unsigned_overflow (value
, 12 + 12))
7620 insn
|= encode_addsub_imm_shift_amount (1);
7624 if (unsigned_overflow (value
, 12))
7625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7626 _("immediate out of range"));
7628 insn
|= encode_addsub_imm (value
);
7630 put_aarch64_insn (buf
, insn
);
7633 case AARCH64_OPND_SIMD_IMM
:
7634 case AARCH64_OPND_SIMD_IMM_SFT
:
7635 case AARCH64_OPND_LIMM
:
7636 /* Bit mask immediate. */
7637 gas_assert (new_inst
!= NULL
);
7638 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7639 new_inst
->operands
[idx
].imm
.value
= value
;
7640 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7641 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7642 put_aarch64_insn (buf
, new_inst
->value
);
7644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7645 _("invalid immediate"));
7648 case AARCH64_OPND_HALF
:
7649 /* 16-bit unsigned immediate. */
7650 if (unsigned_overflow (value
, 16))
7651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7652 _("immediate out of range"));
7653 insn
= get_aarch64_insn (buf
);
7654 insn
|= encode_movw_imm (value
& 0xffff);
7655 put_aarch64_insn (buf
, insn
);
7658 case AARCH64_OPND_IMM_MOV
:
7659 /* Operand for a generic move immediate instruction, which is
7660 an alias instruction that generates a single MOVZ, MOVN or ORR
7661 instruction to loads a 32-bit/64-bit immediate value into general
7662 register. An assembler error shall result if the immediate cannot be
7663 created by a single one of these instructions. If there is a choice,
7664 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7665 and MOVZ or MOVN to ORR. */
7666 gas_assert (new_inst
!= NULL
);
7667 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7670 case AARCH64_OPND_ADDR_SIMM7
:
7671 case AARCH64_OPND_ADDR_SIMM9
:
7672 case AARCH64_OPND_ADDR_SIMM9_2
:
7673 case AARCH64_OPND_ADDR_SIMM10
:
7674 case AARCH64_OPND_ADDR_UIMM12
:
7675 /* Immediate offset in an address. */
7676 insn
= get_aarch64_insn (buf
);
7678 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7679 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7680 || new_inst
->opcode
->operands
[2] == opnd
);
7682 /* Get the index of the address operand. */
7683 if (new_inst
->opcode
->operands
[1] == opnd
)
7684 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7687 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7690 /* Update the resolved offset value. */
7691 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7693 /* Encode/fix-up. */
7694 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7695 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7697 put_aarch64_insn (buf
, new_inst
->value
);
7700 else if (new_inst
->opcode
->iclass
== ldst_pos
7701 && try_to_encode_as_unscaled_ldst (new_inst
))
7703 put_aarch64_insn (buf
, new_inst
->value
);
7707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7708 _("immediate offset out of range"));
7713 as_fatal (_("unhandled operand code %d"), opnd
);
7717 /* Apply a fixup (fixP) to segment data, once it has been determined
7718 by our caller that we have all the info we need to fix it up.
7720 Parameter valP is the pointer to the value of the bits. */
7723 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7725 offsetT value
= *valP
;
7727 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7729 unsigned flags
= fixP
->fx_addnumber
;
7731 DEBUG_TRACE ("\n\n");
7732 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7733 DEBUG_TRACE ("Enter md_apply_fix");
7735 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7737 /* Note whether this will delete the relocation. */
7739 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7742 /* Process the relocations. */
7743 switch (fixP
->fx_r_type
)
7745 case BFD_RELOC_NONE
:
7746 /* This will need to go in the object file. */
7751 case BFD_RELOC_8_PCREL
:
7752 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7753 md_number_to_chars (buf
, value
, 1);
7757 case BFD_RELOC_16_PCREL
:
7758 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7759 md_number_to_chars (buf
, value
, 2);
7763 case BFD_RELOC_32_PCREL
:
7764 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7765 md_number_to_chars (buf
, value
, 4);
7769 case BFD_RELOC_64_PCREL
:
7770 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7771 md_number_to_chars (buf
, value
, 8);
7774 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7775 /* We claim that these fixups have been processed here, even if
7776 in fact we generate an error because we do not have a reloc
7777 for them, so tc_gen_reloc() will reject them. */
7779 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7782 _("undefined symbol %s used as an immediate value"),
7783 S_GET_NAME (fixP
->fx_addsy
));
7784 goto apply_fix_return
;
7786 fix_insn (fixP
, flags
, value
);
7789 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7790 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7794 _("pc-relative load offset not word aligned"));
7795 if (signed_overflow (value
, 21))
7796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7797 _("pc-relative load offset out of range"));
7798 insn
= get_aarch64_insn (buf
);
7799 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7800 put_aarch64_insn (buf
, insn
);
7804 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7805 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7807 if (signed_overflow (value
, 21))
7808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7809 _("pc-relative address offset out of range"));
7810 insn
= get_aarch64_insn (buf
);
7811 insn
|= encode_adr_imm (value
);
7812 put_aarch64_insn (buf
, insn
);
7816 case BFD_RELOC_AARCH64_BRANCH19
:
7817 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7821 _("conditional branch target not word aligned"));
7822 if (signed_overflow (value
, 21))
7823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7824 _("conditional branch out of range"));
7825 insn
= get_aarch64_insn (buf
);
7826 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7827 put_aarch64_insn (buf
, insn
);
7831 case BFD_RELOC_AARCH64_TSTBR14
:
7832 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7836 _("conditional branch target not word aligned"));
7837 if (signed_overflow (value
, 16))
7838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7839 _("conditional branch out of range"));
7840 insn
= get_aarch64_insn (buf
);
7841 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7842 put_aarch64_insn (buf
, insn
);
7846 case BFD_RELOC_AARCH64_CALL26
:
7847 case BFD_RELOC_AARCH64_JUMP26
:
7848 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7852 _("branch target not word aligned"));
7853 if (signed_overflow (value
, 28))
7854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7855 _("branch out of range"));
7856 insn
= get_aarch64_insn (buf
);
7857 insn
|= encode_branch_ofs_26 (value
>> 2);
7858 put_aarch64_insn (buf
, insn
);
7862 case BFD_RELOC_AARCH64_MOVW_G0
:
7863 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7864 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7865 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7866 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7867 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7870 case BFD_RELOC_AARCH64_MOVW_G1
:
7871 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7872 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7873 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7874 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7875 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7878 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7880 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7881 /* Should always be exported to object file, see
7882 aarch64_force_relocation(). */
7883 gas_assert (!fixP
->fx_done
);
7884 gas_assert (seg
->use_rela_p
);
7886 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7888 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7889 /* Should always be exported to object file, see
7890 aarch64_force_relocation(). */
7891 gas_assert (!fixP
->fx_done
);
7892 gas_assert (seg
->use_rela_p
);
7894 case BFD_RELOC_AARCH64_MOVW_G2
:
7895 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7896 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7897 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7898 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7901 case BFD_RELOC_AARCH64_MOVW_G3
:
7902 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7905 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7907 insn
= get_aarch64_insn (buf
);
7911 /* REL signed addend must fit in 16 bits */
7912 if (signed_overflow (value
, 16))
7913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7914 _("offset out of range"));
7918 /* Check for overflow and scale. */
7919 switch (fixP
->fx_r_type
)
7921 case BFD_RELOC_AARCH64_MOVW_G0
:
7922 case BFD_RELOC_AARCH64_MOVW_G1
:
7923 case BFD_RELOC_AARCH64_MOVW_G2
:
7924 case BFD_RELOC_AARCH64_MOVW_G3
:
7925 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7926 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7927 if (unsigned_overflow (value
, scale
+ 16))
7928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7929 _("unsigned value out of range"));
7931 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7932 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7933 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7934 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7935 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7936 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7937 /* NOTE: We can only come here with movz or movn. */
7938 if (signed_overflow (value
, scale
+ 16))
7939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7940 _("signed value out of range"));
7943 /* Force use of MOVN. */
7945 insn
= reencode_movzn_to_movn (insn
);
7949 /* Force use of MOVZ. */
7950 insn
= reencode_movzn_to_movz (insn
);
7954 /* Unchecked relocations. */
7960 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7961 insn
|= encode_movw_imm (value
& 0xffff);
7963 put_aarch64_insn (buf
, insn
);
7967 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7968 fixP
->fx_r_type
= (ilp32_p
7969 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7970 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7971 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7972 /* Should always be exported to object file, see
7973 aarch64_force_relocation(). */
7974 gas_assert (!fixP
->fx_done
);
7975 gas_assert (seg
->use_rela_p
);
7978 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7979 fixP
->fx_r_type
= (ilp32_p
7980 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7981 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
7982 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7983 /* Should always be exported to object file, see
7984 aarch64_force_relocation(). */
7985 gas_assert (!fixP
->fx_done
);
7986 gas_assert (seg
->use_rela_p
);
7989 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
7990 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7991 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7992 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7993 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
7994 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7995 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7996 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7997 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7998 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7999 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8000 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8001 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8002 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8003 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8004 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8005 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8006 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8007 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8008 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8009 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8010 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8011 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8012 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8013 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8014 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8015 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8016 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8017 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8018 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8019 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8020 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8021 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8022 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8023 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8024 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8025 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8026 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8027 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8028 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8029 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8030 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8031 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8032 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8033 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8034 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8035 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8036 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8037 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8038 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8039 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8040 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8041 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8042 /* Should always be exported to object file, see
8043 aarch64_force_relocation(). */
8044 gas_assert (!fixP
->fx_done
);
8045 gas_assert (seg
->use_rela_p
);
8048 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8049 /* Should always be exported to object file, see
8050 aarch64_force_relocation(). */
8051 fixP
->fx_r_type
= (ilp32_p
8052 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8053 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8054 gas_assert (!fixP
->fx_done
);
8055 gas_assert (seg
->use_rela_p
);
8058 case BFD_RELOC_AARCH64_ADD_LO12
:
8059 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8060 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8061 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8062 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8063 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8064 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8065 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8066 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8067 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8068 case BFD_RELOC_AARCH64_LDST128_LO12
:
8069 case BFD_RELOC_AARCH64_LDST16_LO12
:
8070 case BFD_RELOC_AARCH64_LDST32_LO12
:
8071 case BFD_RELOC_AARCH64_LDST64_LO12
:
8072 case BFD_RELOC_AARCH64_LDST8_LO12
:
8073 /* Should always be exported to object file, see
8074 aarch64_force_relocation(). */
8075 gas_assert (!fixP
->fx_done
);
8076 gas_assert (seg
->use_rela_p
);
8079 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8080 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8081 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8084 case BFD_RELOC_UNUSED
:
8085 /* An error will already have been reported. */
8089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8090 _("unexpected %s fixup"),
8091 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8096 /* Free the allocated the struct aarch64_inst.
8097 N.B. currently there are very limited number of fix-up types actually use
8098 this field, so the impact on the performance should be minimal . */
8099 if (fixP
->tc_fix_data
.inst
!= NULL
)
8100 free (fixP
->tc_fix_data
.inst
);
8105 /* Translate internal representation of relocation info to BFD target
8109 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8112 bfd_reloc_code_real_type code
;
8114 reloc
= XNEW (arelent
);
8116 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8117 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8118 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8122 if (section
->use_rela_p
)
8123 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8125 fixp
->fx_offset
= reloc
->address
;
8127 reloc
->addend
= fixp
->fx_offset
;
8129 code
= fixp
->fx_r_type
;
8134 code
= BFD_RELOC_16_PCREL
;
8139 code
= BFD_RELOC_32_PCREL
;
8144 code
= BFD_RELOC_64_PCREL
;
8151 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8152 if (reloc
->howto
== NULL
)
8154 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8156 ("cannot represent %s relocation in this object file format"),
8157 bfd_get_reloc_code_name (code
));
8164 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8167 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8169 bfd_reloc_code_real_type type
;
8173 FIXME: @@ Should look at CPU word size. */
8180 type
= BFD_RELOC_16
;
8183 type
= BFD_RELOC_32
;
8186 type
= BFD_RELOC_64
;
8189 as_bad (_("cannot do %u-byte relocation"), size
);
8190 type
= BFD_RELOC_UNUSED
;
8194 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8198 aarch64_force_relocation (struct fix
*fixp
)
8200 switch (fixp
->fx_r_type
)
8202 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8203 /* Perform these "immediate" internal relocations
8204 even if the symbol is extern or weak. */
8207 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8208 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8209 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8210 /* Pseudo relocs that need to be fixed up according to
8214 case BFD_RELOC_AARCH64_ADD_LO12
:
8215 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8216 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8217 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8218 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8219 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8220 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8221 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8222 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8223 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8224 case BFD_RELOC_AARCH64_LDST128_LO12
:
8225 case BFD_RELOC_AARCH64_LDST16_LO12
:
8226 case BFD_RELOC_AARCH64_LDST32_LO12
:
8227 case BFD_RELOC_AARCH64_LDST64_LO12
:
8228 case BFD_RELOC_AARCH64_LDST8_LO12
:
8229 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8230 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8231 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8232 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8233 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8234 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8235 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8236 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8237 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8238 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8239 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8240 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8241 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8242 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8243 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8244 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8245 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8246 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8247 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8248 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8249 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8250 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8251 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8252 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8253 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8254 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8255 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8256 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8257 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8258 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8259 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8260 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8261 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8262 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8263 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8264 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8265 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8266 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8267 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8268 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8269 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8270 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8271 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8272 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8273 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8274 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8275 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8276 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8277 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8278 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8279 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8280 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8281 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8282 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8283 /* Always leave these relocations for the linker. */
8290 return generic_force_reloc (fixp
);
8295 /* Implement md_after_parse_args. This is the earliest time we need to decide
8296 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8299 aarch64_after_parse_args (void)
8301 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8304 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8305 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8306 aarch64_abi
= AARCH64_ABI_ILP32
;
8308 aarch64_abi
= AARCH64_ABI_LP64
;
8312 elf64_aarch64_target_format (void)
8314 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8316 /* FIXME: What to do for ilp32_p ? */
8317 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8319 if (target_big_endian
)
8320 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8322 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8326 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8328 elf_frob_symbol (symp
, puntp
);
8332 /* MD interface: Finalization. */
8334 /* A good place to do this, although this was probably not intended
8335 for this kind of use. We need to dump the literal pool before
8336 references are made to a null symbol pointer. */
8339 aarch64_cleanup (void)
8343 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8345 /* Put it at the end of the relevant section. */
8346 subseg_set (pool
->section
, pool
->sub_section
);
8352 /* Remove any excess mapping symbols generated for alignment frags in
8353 SEC. We may have created a mapping symbol before a zero byte
8354 alignment; remove it if there's a mapping symbol after the
8357 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8358 void *dummy ATTRIBUTE_UNUSED
)
8360 segment_info_type
*seginfo
= seg_info (sec
);
8363 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8366 for (fragp
= seginfo
->frchainP
->frch_root
;
8367 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8369 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8370 fragS
*next
= fragp
->fr_next
;
8372 /* Variable-sized frags have been converted to fixed size by
8373 this point. But if this was variable-sized to start with,
8374 there will be a fixed-size frag after it. So don't handle
8376 if (sym
== NULL
|| next
== NULL
)
8379 if (S_GET_VALUE (sym
) < next
->fr_address
)
8380 /* Not at the end of this frag. */
8382 know (S_GET_VALUE (sym
) == next
->fr_address
);
8386 if (next
->tc_frag_data
.first_map
!= NULL
)
8388 /* Next frag starts with a mapping symbol. Discard this
8390 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8394 if (next
->fr_next
== NULL
)
8396 /* This mapping symbol is at the end of the section. Discard
8398 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8399 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8403 /* As long as we have empty frags without any mapping symbols,
8405 /* If the next frag is non-empty and does not start with a
8406 mapping symbol, then this mapping symbol is required. */
8407 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8410 next
= next
->fr_next
;
8412 while (next
!= NULL
);
8417 /* Adjust the symbol table. */
8420 aarch64_adjust_symtab (void)
8423 /* Remove any overlapping mapping symbols generated by alignment frags. */
8424 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8425 /* Now do generic ELF adjustments. */
8426 elf_adjust_symtab ();
8431 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8433 const char *hash_err
;
8435 hash_err
= hash_insert (table
, key
, value
);
8437 printf ("Internal Error: Can't hash %s\n", key
);
8441 fill_instruction_hash_table (void)
8443 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8445 while (opcode
->name
!= NULL
)
8447 templates
*templ
, *new_templ
;
8448 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8450 new_templ
= XNEW (templates
);
8451 new_templ
->opcode
= opcode
;
8452 new_templ
->next
= NULL
;
8455 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8458 new_templ
->next
= templ
->next
;
8459 templ
->next
= new_templ
;
8466 convert_to_upper (char *dst
, const char *src
, size_t num
)
8469 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8470 *dst
= TOUPPER (*src
);
8474 /* Assume STR point to a lower-case string, allocate, convert and return
8475 the corresponding upper-case string. */
8476 static inline const char*
8477 get_upper_str (const char *str
)
8480 size_t len
= strlen (str
);
8481 ret
= XNEWVEC (char, len
+ 1);
8482 convert_to_upper (ret
, str
, len
);
8486 /* MD interface: Initialization. */
8494 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8495 || (aarch64_cond_hsh
= hash_new ()) == NULL
8496 || (aarch64_shift_hsh
= hash_new ()) == NULL
8497 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8498 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8499 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8500 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8501 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8502 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8503 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8504 || (aarch64_reg_hsh
= hash_new ()) == NULL
8505 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8506 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8507 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8508 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8509 as_fatal (_("virtual memory exhausted"));
8511 fill_instruction_hash_table ();
8513 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8514 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8515 (void *) (aarch64_sys_regs
+ i
));
8517 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8518 checked_hash_insert (aarch64_pstatefield_hsh
,
8519 aarch64_pstatefields
[i
].name
,
8520 (void *) (aarch64_pstatefields
+ i
));
8522 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8523 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8524 aarch64_sys_regs_ic
[i
].name
,
8525 (void *) (aarch64_sys_regs_ic
+ i
));
8527 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8528 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8529 aarch64_sys_regs_dc
[i
].name
,
8530 (void *) (aarch64_sys_regs_dc
+ i
));
8532 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8533 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8534 aarch64_sys_regs_at
[i
].name
,
8535 (void *) (aarch64_sys_regs_at
+ i
));
8537 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8538 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8539 aarch64_sys_regs_tlbi
[i
].name
,
8540 (void *) (aarch64_sys_regs_tlbi
+ i
));
8542 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8543 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8544 aarch64_sys_regs_sr
[i
].name
,
8545 (void *) (aarch64_sys_regs_sr
+ i
));
8547 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8548 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8549 (void *) (reg_names
+ i
));
8551 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8552 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8553 (void *) (nzcv_names
+ i
));
8555 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8557 const char *name
= aarch64_operand_modifiers
[i
].name
;
8558 checked_hash_insert (aarch64_shift_hsh
, name
,
8559 (void *) (aarch64_operand_modifiers
+ i
));
8560 /* Also hash the name in the upper case. */
8561 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8562 (void *) (aarch64_operand_modifiers
+ i
));
8565 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8568 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8569 the same condition code. */
8570 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8572 const char *name
= aarch64_conds
[i
].names
[j
];
8575 checked_hash_insert (aarch64_cond_hsh
, name
,
8576 (void *) (aarch64_conds
+ i
));
8577 /* Also hash the name in the upper case. */
8578 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8579 (void *) (aarch64_conds
+ i
));
8583 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8585 const char *name
= aarch64_barrier_options
[i
].name
;
8586 /* Skip xx00 - the unallocated values of option. */
8589 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8590 (void *) (aarch64_barrier_options
+ i
));
8591 /* Also hash the name in the upper case. */
8592 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8593 (void *) (aarch64_barrier_options
+ i
));
8596 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8598 const char* name
= aarch64_prfops
[i
].name
;
8599 /* Skip the unallocated hint encodings. */
8602 checked_hash_insert (aarch64_pldop_hsh
, name
,
8603 (void *) (aarch64_prfops
+ i
));
8604 /* Also hash the name in the upper case. */
8605 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8606 (void *) (aarch64_prfops
+ i
));
8609 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8611 const char* name
= aarch64_hint_options
[i
].name
;
8613 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8614 (void *) (aarch64_hint_options
+ i
));
8615 /* Also hash the name in the upper case. */
8616 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8617 (void *) (aarch64_hint_options
+ i
));
8620 /* Set the cpu variant based on the command-line options. */
8622 mcpu_cpu_opt
= march_cpu_opt
;
8625 mcpu_cpu_opt
= &cpu_default
;
8627 cpu_variant
= *mcpu_cpu_opt
;
8629 /* Record the CPU type. */
8630 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8632 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8635 /* Command line processing. */
8637 const char *md_shortopts
= "m:";
8639 #ifdef AARCH64_BI_ENDIAN
8640 #define OPTION_EB (OPTION_MD_BASE + 0)
8641 #define OPTION_EL (OPTION_MD_BASE + 1)
8643 #if TARGET_BYTES_BIG_ENDIAN
8644 #define OPTION_EB (OPTION_MD_BASE + 0)
8646 #define OPTION_EL (OPTION_MD_BASE + 1)
8650 struct option md_longopts
[] = {
8652 {"EB", no_argument
, NULL
, OPTION_EB
},
8655 {"EL", no_argument
, NULL
, OPTION_EL
},
8657 {NULL
, no_argument
, NULL
, 0}
8660 size_t md_longopts_size
= sizeof (md_longopts
);
8662 struct aarch64_option_table
8664 const char *option
; /* Option name to match. */
8665 const char *help
; /* Help information. */
8666 int *var
; /* Variable to change. */
8667 int value
; /* What to change it to. */
8668 char *deprecated
; /* If non-null, print this message. */
8671 static struct aarch64_option_table aarch64_opts
[] = {
8672 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8673 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8675 #ifdef DEBUG_AARCH64
8676 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8677 #endif /* DEBUG_AARCH64 */
8678 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8680 {"mno-verbose-error", N_("do not output verbose error messages"),
8681 &verbose_error_p
, 0, NULL
},
8682 {NULL
, NULL
, NULL
, 0, NULL
}
8685 struct aarch64_cpu_option_table
8688 const aarch64_feature_set value
;
8689 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8691 const char *canonical_name
;
8694 /* This list should, at a minimum, contain all the cpu names
8695 recognized by GCC. */
8696 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8697 {"all", AARCH64_ANY
, NULL
},
8698 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8699 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8700 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8701 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8702 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8703 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8704 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8705 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8706 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8707 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8708 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8709 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8711 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8712 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8714 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8715 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8717 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8718 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8719 "Samsung Exynos M1"},
8720 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8721 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8722 | AARCH64_FEATURE_RDMA
),
8724 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8725 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8726 | AARCH64_FEATURE_RDMA
),
8727 "Qualcomm QDF24XX"},
8728 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8729 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8730 "Qualcomm Saphira"},
8731 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8732 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8734 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8735 AARCH64_FEATURE_CRYPTO
),
8737 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8738 in earlier releases and is superseded by 'xgene1' in all
8740 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8741 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8742 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8743 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8744 {"generic", AARCH64_ARCH_V8
, NULL
},
8746 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8749 struct aarch64_arch_option_table
8752 const aarch64_feature_set value
;
8755 /* This list should, at a minimum, contain all the architecture names
8756 recognized by GCC. */
8757 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8758 {"all", AARCH64_ANY
},
8759 {"armv8-a", AARCH64_ARCH_V8
},
8760 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8761 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8762 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8763 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8764 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8765 {NULL
, AARCH64_ARCH_NONE
}
8768 /* ISA extensions. */
8769 struct aarch64_option_cpu_value_table
8772 const aarch64_feature_set value
;
8773 const aarch64_feature_set require
; /* Feature dependencies. */
8776 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8777 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8779 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8780 | AARCH64_FEATURE_AES
8781 | AARCH64_FEATURE_SHA2
, 0),
8782 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8783 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8785 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8787 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8788 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8789 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8791 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8793 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8795 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8796 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8797 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8798 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8799 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8800 AARCH64_FEATURE (AARCH64_FEATURE_FP
8801 | AARCH64_FEATURE_F16
, 0)},
8802 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8804 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8805 AARCH64_FEATURE (AARCH64_FEATURE_F16
8806 | AARCH64_FEATURE_SIMD
8807 | AARCH64_FEATURE_COMPNUM
, 0)},
8808 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8809 AARCH64_FEATURE (AARCH64_FEATURE_F16
8810 | AARCH64_FEATURE_SIMD
, 0)},
8811 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8813 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8815 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8817 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8819 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8821 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8823 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8825 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8826 | AARCH64_FEATURE_SHA3
, 0),
8828 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8830 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
8832 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
8834 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8837 struct aarch64_long_option_table
8839 const char *option
; /* Substring to match. */
8840 const char *help
; /* Help information. */
8841 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8842 char *deprecated
; /* If non-null, print this message. */
8845 /* Transitive closure of features depending on set. */
8846 static aarch64_feature_set
8847 aarch64_feature_disable_set (aarch64_feature_set set
)
8849 const struct aarch64_option_cpu_value_table
*opt
;
8850 aarch64_feature_set prev
= 0;
8852 while (prev
!= set
) {
8854 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8855 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8856 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8861 /* Transitive closure of dependencies of set. */
8862 static aarch64_feature_set
8863 aarch64_feature_enable_set (aarch64_feature_set set
)
8865 const struct aarch64_option_cpu_value_table
*opt
;
8866 aarch64_feature_set prev
= 0;
8868 while (prev
!= set
) {
8870 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8871 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8872 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8878 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8879 bfd_boolean ext_only
)
8881 /* We insist on extensions being added before being removed. We achieve
8882 this by using the ADDING_VALUE variable to indicate whether we are
8883 adding an extension (1) or removing it (0) and only allowing it to
8884 change in the order -1 -> 1 -> 0. */
8885 int adding_value
= -1;
8886 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8888 /* Copy the feature set, so that we can modify it. */
8892 while (str
!= NULL
&& *str
!= 0)
8894 const struct aarch64_option_cpu_value_table
*opt
;
8895 const char *ext
= NULL
;
8902 as_bad (_("invalid architectural extension"));
8906 ext
= strchr (++str
, '+');
8912 optlen
= strlen (str
);
8914 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8916 if (adding_value
!= 0)
8921 else if (optlen
> 0)
8923 if (adding_value
== -1)
8925 else if (adding_value
!= 1)
8927 as_bad (_("must specify extensions to add before specifying "
8928 "those to remove"));
8935 as_bad (_("missing architectural extension"));
8939 gas_assert (adding_value
!= -1);
8941 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8942 if (strncmp (opt
->name
, str
, optlen
) == 0)
8944 aarch64_feature_set set
;
8946 /* Add or remove the extension. */
8949 set
= aarch64_feature_enable_set (opt
->value
);
8950 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8954 set
= aarch64_feature_disable_set (opt
->value
);
8955 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8960 if (opt
->name
== NULL
)
8962 as_bad (_("unknown architectural extension `%s'"), str
);
8973 aarch64_parse_cpu (const char *str
)
8975 const struct aarch64_cpu_option_table
*opt
;
8976 const char *ext
= strchr (str
, '+');
8982 optlen
= strlen (str
);
8986 as_bad (_("missing cpu name `%s'"), str
);
8990 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8991 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8993 mcpu_cpu_opt
= &opt
->value
;
8995 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9000 as_bad (_("unknown cpu `%s'"), str
);
9005 aarch64_parse_arch (const char *str
)
9007 const struct aarch64_arch_option_table
*opt
;
9008 const char *ext
= strchr (str
, '+');
9014 optlen
= strlen (str
);
9018 as_bad (_("missing architecture name `%s'"), str
);
9022 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9023 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9025 march_cpu_opt
= &opt
->value
;
9027 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9032 as_bad (_("unknown architecture `%s'\n"), str
);
9037 struct aarch64_option_abi_value_table
9040 enum aarch64_abi_type value
;
9043 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9044 {"ilp32", AARCH64_ABI_ILP32
},
9045 {"lp64", AARCH64_ABI_LP64
},
9049 aarch64_parse_abi (const char *str
)
9055 as_bad (_("missing abi name `%s'"), str
);
9059 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9060 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9062 aarch64_abi
= aarch64_abis
[i
].value
;
9066 as_bad (_("unknown abi `%s'\n"), str
);
9070 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9072 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9073 aarch64_parse_abi
, NULL
},
9074 #endif /* OBJ_ELF */
9075 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9076 aarch64_parse_cpu
, NULL
},
9077 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9078 aarch64_parse_arch
, NULL
},
9079 {NULL
, NULL
, 0, NULL
}
9083 md_parse_option (int c
, const char *arg
)
9085 struct aarch64_option_table
*opt
;
9086 struct aarch64_long_option_table
*lopt
;
9092 target_big_endian
= 1;
9098 target_big_endian
= 0;
9103 /* Listing option. Just ignore these, we don't support additional
9108 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9110 if (c
== opt
->option
[0]
9111 && ((arg
== NULL
&& opt
->option
[1] == 0)
9112 || streq (arg
, opt
->option
+ 1)))
9114 /* If the option is deprecated, tell the user. */
9115 if (opt
->deprecated
!= NULL
)
9116 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9117 arg
? arg
: "", _(opt
->deprecated
));
9119 if (opt
->var
!= NULL
)
9120 *opt
->var
= opt
->value
;
9126 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9128 /* These options are expected to have an argument. */
9129 if (c
== lopt
->option
[0]
9131 && strncmp (arg
, lopt
->option
+ 1,
9132 strlen (lopt
->option
+ 1)) == 0)
9134 /* If the option is deprecated, tell the user. */
9135 if (lopt
->deprecated
!= NULL
)
9136 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9137 _(lopt
->deprecated
));
9139 /* Call the sup-option parser. */
9140 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9151 md_show_usage (FILE * fp
)
9153 struct aarch64_option_table
*opt
;
9154 struct aarch64_long_option_table
*lopt
;
9156 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9158 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9159 if (opt
->help
!= NULL
)
9160 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9162 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9163 if (lopt
->help
!= NULL
)
9164 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9168 -EB assemble code for a big-endian cpu\n"));
9173 -EL assemble code for a little-endian cpu\n"));
9177 /* Parse a .cpu directive. */
9180 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9182 const struct aarch64_cpu_option_table
*opt
;
9188 name
= input_line_pointer
;
9189 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9190 input_line_pointer
++;
9191 saved_char
= *input_line_pointer
;
9192 *input_line_pointer
= 0;
9194 ext
= strchr (name
, '+');
9197 optlen
= ext
- name
;
9199 optlen
= strlen (name
);
9201 /* Skip the first "all" entry. */
9202 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9203 if (strlen (opt
->name
) == optlen
9204 && strncmp (name
, opt
->name
, optlen
) == 0)
9206 mcpu_cpu_opt
= &opt
->value
;
9208 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9211 cpu_variant
= *mcpu_cpu_opt
;
9213 *input_line_pointer
= saved_char
;
9214 demand_empty_rest_of_line ();
9217 as_bad (_("unknown cpu `%s'"), name
);
9218 *input_line_pointer
= saved_char
;
9219 ignore_rest_of_line ();
9223 /* Parse a .arch directive. */
9226 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9228 const struct aarch64_arch_option_table
*opt
;
9234 name
= input_line_pointer
;
9235 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9236 input_line_pointer
++;
9237 saved_char
= *input_line_pointer
;
9238 *input_line_pointer
= 0;
9240 ext
= strchr (name
, '+');
9243 optlen
= ext
- name
;
9245 optlen
= strlen (name
);
9247 /* Skip the first "all" entry. */
9248 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9249 if (strlen (opt
->name
) == optlen
9250 && strncmp (name
, opt
->name
, optlen
) == 0)
9252 mcpu_cpu_opt
= &opt
->value
;
9254 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9257 cpu_variant
= *mcpu_cpu_opt
;
9259 *input_line_pointer
= saved_char
;
9260 demand_empty_rest_of_line ();
9264 as_bad (_("unknown architecture `%s'\n"), name
);
9265 *input_line_pointer
= saved_char
;
9266 ignore_rest_of_line ();
9269 /* Parse a .arch_extension directive. */
9272 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9275 char *ext
= input_line_pointer
;;
9277 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9278 input_line_pointer
++;
9279 saved_char
= *input_line_pointer
;
9280 *input_line_pointer
= 0;
9282 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9285 cpu_variant
= *mcpu_cpu_opt
;
9287 *input_line_pointer
= saved_char
;
9288 demand_empty_rest_of_line ();
9291 /* Copy symbol information. */
9294 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9296 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);