1 /* tc-alpha.c - Processor-specific code for the DEC Alpha CPU.
2 Copyright (C) 1989, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Carnegie Mellon University, 1993.
4 Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
5 Modified by Ken Raeburn for gas-2.x and ECOFF support.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 * Mach Operating System
25 * Copyright (c) 1993 Carnegie Mellon University
26 * All Rights Reserved.
28 * Permission to use, copy, modify and distribute this software and its
29 * documentation is hereby granted, provided that both the copyright
30 * notice and this permission notice appear in all copies of the
31 * software, derivative works or modified versions, and any portions
32 * thereof, and that both notices appear in supporting documentation.
34 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
35 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
36 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
38 * Carnegie Mellon requests users of this software to return to
40 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
41 * School of Computer Science
42 * Carnegie Mellon University
43 * Pittsburgh PA 15213-3890
45 * any improvements or extensions that they make and grant Carnegie the
46 * rights to redistribute these changes.
50 * 5-Oct-93 Alessandro Forin (af) at Carnegie-Mellon University
53 * Author: Alessandro Forin, Carnegie Mellon University
58 #include "alpha-opcode.h"
61 /* These are exported to relaxing code, even though we don't do any
62 relaxing on this processor currently. */
63 const relax_typeS md_relax_table
[1];
64 int md_short_jump_size
= 4;
65 int md_long_jump_size
= 4;
67 /* handle of the OPCODE hash table */
68 static struct hash_control
*op_hash
;
70 /* sections we'll want to keep track of */
71 static segT lita_sec
, rdata
, sdata
;
73 /* setting for ".set [no]{at,macro}" */
74 static int at_ok
= 1, macro_ok
= 1;
76 /* Keep track of global pointer. */
77 valueT alpha_gp_value
;
80 /* We'll probably be using this relocation frequently, and we
81 will want to compare for it. */
82 static reloc_howto_type
*gpdisp_hi16_howto
;
84 /* These are exported to ECOFF code. */
85 unsigned long alpha_gprmask
, alpha_fprmask
;
87 /* Used for LITUSE relocations. */
88 static expressionS lituse_basereg
, lituse_byteoff
, lituse_jsr
;
90 /* Imported functions -- they should be defined in header files somewhere. */
91 extern segT
subseg_get ();
92 extern PTR
bfd_alloc_by_size_t ();
93 extern void s_globl (), s_long (), s_short (), s_space (), cons (), s_text (),
94 s_data (), float_cons ();
96 /* Static functions, needing forward declarations. */
97 static void s_mask (), s_base (), s_proc (), s_alpha_set ();
98 static void s_gprel32 (), s_rdata (), s_sdata (), s_alpha_comm ();
99 static int alpha_ip ();
101 const pseudo_typeS md_pseudo_table
[] =
103 {"common", s_comm
, 0}, /* is this used? */
104 {"comm", s_alpha_comm
, 0}, /* osf1 compiler does this */
105 {"rdata", s_rdata
, 0},
106 {"sdata", s_sdata
, 0},
107 {"gprel32", s_gprel32
, 0},
108 {"t_floating", float_cons
, 'd'},
109 {"s_floating", float_cons
, 'f'},
110 {"f_floating", float_cons
, 'F'},
111 {"g_floating", float_cons
, 'G'},
112 {"d_floating", float_cons
, 'D'},
115 {"aproc", s_proc
, 1},
116 {"set", s_alpha_set
, 0},
117 {"reguse", s_ignore
, 0},
118 {"livereg", s_ignore
, 0},
119 {"extern", s_ignore
, 0}, /*??*/
120 {"base", s_base
, 0}, /*??*/
121 {"option", s_ignore
, 0},
122 {"prologue", s_ignore
, 0},
123 {"aent", s_ignore
, 0},
124 {"ugen", s_ignore
, 0},
126 /* We don't do any optimizing, so we can safely ignore these. */
127 {"noalias", s_ignore
, 0},
128 {"alias", s_ignore
, 0},
133 #define SA 21 /* shift for register Ra */
134 #define SB 16 /* shift for register Rb */
135 #define SC 0 /* shift for register Rc */
136 #define SN 13 /* shift for 8 bit immediate # */
148 #define OPCODE(X) (((X) >> 26) & 0x3f)
149 #define OP_FCN(X) (((X) >> 5) & 0x7f)
151 #ifndef FIRST_32BIT_QUADRANT
152 #define FIRST_32BIT_QUADRANT 0
155 int first_32bit_quadrant
= FIRST_32BIT_QUADRANT
;
156 int base_register
= FIRST_32BIT_QUADRANT
? ZERO
: GP
;
158 int no_mixed_code
= 0;
161 /* This array holds the chars that always start a comment. If the
162 pre-processor is disabled, these aren't very useful */
163 const char comment_chars
[] = "#";
165 /* This array holds the chars that only start a comment at the beginning of
166 a line. If the line seems to have the form '# 123 filename'
167 .line and .file directives will appear in the pre-processed output */
168 /* Note that input_file.c hand checks for '#' at the beginning of the
169 first line of the input file. This is because the compiler outputs
170 #NO_APP at the beginning of its output. */
171 /* Also note that '/*' will always start a comment */
172 const char line_comment_chars
[] = "#";
174 /* Chars that can be used to separate mant from exp in floating point nums */
175 const char EXP_CHARS
[] = "eE";
177 const char line_separator_chars
[1];
179 /* Chars that mean this number is a floating point constant, as in
180 "0f12.456" or "0d1.2345e12". */
181 char FLT_CHARS
[] = "rRsSfFdDxXpP";
183 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
184 changed in read.c. Ideally it shouldn't have to know about it at all,
185 but nothing is ideal around here. */
190 bfd_reloc_code_real_type code
;
193 /* Occasionally, two relocations will be desired for one address.
194 Mainly only in cases like "jsr $r,foo" where we want both a LITUSE
199 unsigned long opcode
; /* need at least 32 bits */
200 struct reloc_data reloc
[MAX_RELOCS
];
203 static void getExpression (char *str
, struct alpha_it
*insn
);
204 static char *expr_end
;
206 #define note_gpreg(R) (alpha_gprmask |= (1 << (R)))
207 #define note_fpreg(R) (alpha_fprmask |= (1 << (R)))
210 tc_get_register (frame
)
217 if (*input_line_pointer
== '$')
219 input_line_pointer
++;
220 if (input_line_pointer
[0] == 's'
221 && input_line_pointer
[1] == 'p')
223 input_line_pointer
+= 2;
227 framereg
= get_absolute_expression ();
228 framereg
&= 31; /* ? */
231 as_warn ("frame reg expected, using $%d.", framereg
);
233 note_gpreg (framereg
);
243 temp
= get_absolute_expression ();
246 rdata
= subseg_get (".rdata", 0);
247 subseg_set (rdata
, (subsegT
) temp
);
249 rdata
= subseg_new (".rdata", 0);
251 demand_empty_rest_of_line ();
260 temp
= get_absolute_expression ();
263 sdata
= subseg_get (".sdata", 0);
264 subseg_set (sdata
, (subsegT
) temp
);
266 sdata
= subseg_new (".sdata", 0);
268 demand_empty_rest_of_line ();
272 s_alpha_comm (ignore
)
279 register symbolS
*symbolP
;
281 name
= input_line_pointer
;
282 c
= get_symbol_end ();
283 /* just after name is now '\0' */
284 p
= input_line_pointer
;
287 /* Alpha OSF/1 compiler doesn't provide the comma, gcc does. */
288 if (*input_line_pointer
== ',')
290 input_line_pointer
++;
293 if ((temp
= get_absolute_expression ()) < 0)
295 as_warn (".COMMon length (%ld.) <0! Ignored.", (long) temp
);
296 ignore_rest_of_line ();
300 symbolP
= symbol_find_or_make (name
);
302 if (S_IS_DEFINED (symbolP
))
304 as_bad ("Ignoring attempt to re-define symbol");
305 ignore_rest_of_line ();
308 if (S_GET_VALUE (symbolP
))
310 if (S_GET_VALUE (symbolP
) != (valueT
) temp
)
311 as_bad ("Length of .comm \"%s\" is already %ld. Not changed to %ld.",
312 S_GET_NAME (symbolP
),
313 (long) S_GET_VALUE (symbolP
),
318 S_SET_VALUE (symbolP
, (valueT
) temp
);
319 S_SET_EXTERNAL (symbolP
);
322 know (symbolP
->sy_frag
== &zero_address_frag
);
323 demand_empty_rest_of_line ();
327 tc_gen_reloc (sec
, fixp
)
332 bfd_reloc_code_real_type code
;
334 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
335 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
336 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
338 if (fixp
->fx_r_type
> BFD_RELOC_UNUSED
|| fixp
->fx_r_type
< 0)
341 if (fixp
->fx_r_type
== BFD_RELOC_ALPHA_GPDISP_HI16
)
343 if (!gpdisp_hi16_howto
)
344 gpdisp_hi16_howto
= bfd_reloc_type_lookup (stdoutput
,
346 reloc
->howto
= gpdisp_hi16_howto
;
349 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
350 assert (reloc
->howto
!= 0);
351 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
353 as_fatal ("bug in handling type-%d relocs", fixp
->fx_r_type
);
356 assert (!fixp
->fx_pcrel
== !reloc
->howto
->pc_relative
);
358 if (reloc
->howto
->pc_relative
359 && reloc
->howto
->pcrel_offset
361 && code
!= BFD_RELOC_ALPHA_GPDISP_HI16
362 && code
!= BFD_RELOC_ALPHA_GPDISP_LO16
366 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
369 reloc
->addend
= fixp
->fx_offset
;
376 if (first_32bit_quadrant
)
378 /* not fatal, but it might not work in the end */
379 as_warn ("File overrides no-base-register option.");
380 first_32bit_quadrant
= 0;
384 if (*input_line_pointer
== '$')
386 input_line_pointer
++;
387 if (*input_line_pointer
== 'r')
388 input_line_pointer
++;
391 base_register
= get_absolute_expression ();
392 if (base_register
< 0 || base_register
> 31)
395 as_warn ("Bad base register, using $r.", base_register
);
397 demand_empty_rest_of_line ();
411 e
.X_add_symbol
= section_symbol (absolute_section
);
422 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &e
, 0,
427 create_lita_section ()
429 segT current_section
= now_seg
;
430 int current_subsec
= now_subseg
;
432 lita_sec
= subseg_new (".lita", 0);
433 subseg_set (current_section
, current_subsec
);
434 bfd_set_section_flags (stdoutput
, lita_sec
,
435 SEC_RELOC
| SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
437 bfd_set_section_alignment (stdoutput
, lita_sec
, 3);
440 /* This function is called once, at assembler startup time. It should
441 set up all the tables, etc. that the MD part of the assembler will need. */
449 op_hash
= hash_new ();
451 for (i
= 0; i
< NUMOPCODES
; )
453 const char *name
= alpha_opcodes
[i
].name
;
454 retval
= hash_insert (op_hash
, name
, (PTR
) & alpha_opcodes
[i
]);
457 as_bad ("internal error: can't hash opcode `%s': %s",
458 alpha_opcodes
[i
].name
, retval
);
463 while (i
< NUMOPCODES
464 && (alpha_opcodes
[i
].name
== name
465 || !strcmp (alpha_opcodes
[i
].name
, name
)));
467 /* Some opcodes include modifiers of various sorts with a "/mod"
468 syntax, like the architecture documentation suggests. However,
469 for use with gcc at least, we also need to access those same
470 opcodes without the "/". */
471 for (i
= 0; i
< NUMOPCODES
; )
473 const char *name
= alpha_opcodes
[i
].name
;
474 if (strchr (name
, '/'))
476 char *p
= xmalloc (strlen (name
));
477 const char *q
= name
;
485 retval
= hash_insert (op_hash
, p
, (PTR
) & alpha_opcodes
[i
]);
488 /* Ignore failures -- the opcode table does duplicate
489 some variants in different forms, like "hw_st/q" and
492 as_bad ("internal error: can't hash opcode variant `%s': %s",
500 while (i
< NUMOPCODES
501 && (alpha_opcodes
[i
].name
== name
502 || !strcmp (alpha_opcodes
[i
].name
, name
)));
508 as_fatal ("Broken assembler. No assembly attempted.");
510 lituse_basereg
.X_op
= O_constant
;
511 lituse_basereg
.X_add_number
= 1;
512 lituse_byteoff
.X_op
= O_constant
;
513 lituse_byteoff
.X_add_number
= 2;
514 lituse_jsr
.X_op
= O_constant
;
515 lituse_jsr
.X_add_number
= 3;
517 /* So .sbss will get used for tiny objects. */
518 bfd_set_gp_size (stdoutput
, 8);
519 create_lita_section ();
520 /* For handling the GP, create a symbol that won't be output in the
521 symbol table. We'll edit it out of relocs later. */
522 gp
= symbol_new ("<GP value>", lita_sec
, 0x8000, &zero_address_frag
);
523 symbol_remove (gp
, &symbol_rootP
, &symbol_lastP
);
535 struct alpha_it insns
[MAX_INSNS
];
537 count
= alpha_ip (str
, insns
);
541 for (i
= 0; i
< count
; i
++)
545 /* put out the opcode */
546 md_number_to_chars (toP
, insns
[i
].opcode
, 4);
548 /* put out the symbol-dependent stuff */
549 for (j
= 0; j
< MAX_RELOCS
; j
++)
551 struct reloc_data
*r
= &insns
[i
].reloc
[j
];
554 if (r
->code
!= BFD_RELOC_NONE
)
556 if (r
->exp
.X_op
== O_constant
)
558 r
->exp
.X_add_symbol
= section_symbol (absolute_section
);
559 r
->exp
.X_op
= O_symbol
;
561 f
= fix_new_exp (frag_now
, (toP
- frag_now
->fr_literal
), 4,
562 &r
->exp
, r
->pcrel
, r
->code
);
564 if (r
->code
== BFD_RELOC_ALPHA_GPDISP_LO16
)
566 static bit_fixS cookie
;
567 /* This'll make the range checking in write.c shut up. */
568 f
->fx_bit_fixP
= &cookie
;
574 /* @@ Will a simple 0x8000 work here? If not, why not? */
575 #define GP_ADJUSTMENT (0x8000 - 0x10)
580 bfd_vma lita_vma
, sdata_vma
;
582 if (alpha_gp_value
!= 0)
586 lita_vma
= bfd_get_section_vma (abfd
, lita_sec
);
591 sdata_vma
= bfd_get_section_vma (abfd
, sdata
);
597 /* Who knows which order they'll get laid out in? */
598 || (sdata_vma
!= 0 && sdata_vma
< lita_vma
))
599 alpha_gp_value
= sdata_vma
;
601 alpha_gp_value
= lita_vma
;
603 alpha_gp_value
+= GP_ADJUSTMENT
;
605 S_SET_VALUE (gp
, alpha_gp_value
);
608 printf ("Chose GP value of %lx\n", alpha_gp_value
);
613 alpha_force_relocation (f
)
616 switch (f
->fx_r_type
)
618 case BFD_RELOC_ALPHA_GPDISP_HI16
:
619 case BFD_RELOC_ALPHA_GPDISP_LO16
:
620 case BFD_RELOC_ALPHA_LITERAL
:
621 case BFD_RELOC_ALPHA_LITUSE
:
622 case BFD_RELOC_GPREL32
:
624 case BFD_RELOC_ALPHA_HINT
:
629 case BFD_RELOC_23_PCREL_S2
:
639 alpha_fix_adjustable (f
)
642 /* Are there any relocation types for which we must generate a reloc
643 but we can adjust the values contained within it? */
644 switch (f
->fx_r_type
)
646 case BFD_RELOC_ALPHA_GPDISP_HI16
:
647 case BFD_RELOC_ALPHA_GPDISP_LO16
:
649 case BFD_RELOC_GPREL32
:
652 return !alpha_force_relocation (f
);
656 md_section_align (seg
, size
)
661 /* This should probably be handled within BFD, or by pulling the
662 number from BFD at least. */
670 /* Add this thing to the .lita section and produce a LITERAL reloc referring
675 Set GP value properly, and have values in LITERAL references set
680 load_symbol_address (reg
, insn
)
682 struct alpha_it
*insn
;
684 static symbolS
*lita_sym
;
695 lita_sym
= section_symbol (lita_sec
);
696 S_CLEAR_EXTERNAL (lita_sym
);
699 retval
= add_to_literal_pool (insn
->reloc
[0].exp
.X_add_symbol
,
700 insn
->reloc
[0].exp
.X_add_number
,
703 /* @@ Get these numbers from GP setting. */
704 retval
-= GP_ADJUSTMENT
;
706 /* Now emit a LITERAL relocation for the original section. */
707 insn
->reloc
[0].exp
.X_op
= O_symbol
;
708 insn
->reloc
[0].exp
.X_add_symbol
= lita_sym
;
709 insn
->reloc
[0].exp
.X_add_number
= retval
;
710 insn
->reloc
[0].code
= BFD_RELOC_ALPHA_LITERAL
;
712 if (retval
== 0x8000)
714 as_fatal ("overflow in literal (.lita) table");
716 insn
->opcode
= (0xa4000000 /* ldq */
718 | (base_register
<< SB
)
720 note_gpreg (base_register
);
723 /* To load an address with a single instruction,
724 emit a LITERAL reloc in this section, and a REFQUAD
725 for the .lita section, so that we'll be able to access
727 lda REG, xx -> ldq REG, -32752(gp)
728 lda REG, xx+4 -> ldq REG, -32752(gp)
731 The offsets need to start near -0x8000, and the generated LITERAL
732 relocations should negate the offset. I don't completely grok the
736 load_expression (reg
, insn
)
738 struct alpha_it
*insn
;
743 addend
= insn
->reloc
[0].exp
.X_add_number
;
744 insn
->reloc
[0].exp
.X_add_number
= 0;
745 load_symbol_address (reg
, insn
);
752 && (x
& ~0x7fff) + 0x8000 != 0)
754 as_bad ("assembler not prepared to handle constants >16 bits yet");
758 insn
[1].opcode
= (0x20000000 /* lda */
761 | (addend
& 0xffff));
762 insn
[1].reloc
[0].code
= BFD_RELOC_ALPHA_LITUSE
;
763 insn
[1].reloc
[0].exp
= lituse_basereg
;
769 getExpression (str
, this_insn
)
771 struct alpha_it
*this_insn
;
776 #if 0 /* Not converted to bfd yet, and I don't think we need them
777 for ECOFF. Re-adding a.out support will probably require
779 static const struct am
{
781 bfd_reloc_code_real_type reloc
;
783 { "hi", RELOC_48_63
},
784 { "lo", RELOC_0_15
},
785 { "ml", RELOC_16_31
},
786 { "mh", RELOC_32_47
},
787 { "uhi", RELOC_U_48_63
},
788 { "uml", RELOC_U_16_31
},
789 { "umh", RELOC_U_32_47
},
793 /* Handle macros: "%macroname(expr)" */
804 while (*q
&& *p
== *q
)
812 str
= p
; /* keep the '(' */
813 this_insn
->reloc
= m
->reloc
;
818 save_in
= input_line_pointer
;
819 input_line_pointer
= str
;
821 seg
= expression (&this_insn
->reloc
[0].exp
);
822 /* XXX validate seg and exp, make sure they're reasonable */
823 expr_end
= input_line_pointer
;
824 input_line_pointer
= save_in
;
827 /* Note that for now, this function is called recursively (by way of
828 calling md_assemble again). Some of the macros defined as part of
829 the assembly language are currently rewritten as sequences of
830 strings to be assembled. See, for example, the handling of "divq".
832 For efficiency, this should be fixed someday. */
834 alpha_ip (str
, insns
)
836 struct alpha_it insns
[];
842 struct alpha_opcode
*pattern
;
846 int match
= 0, num_gen
= 1;
850 islower (*s
) || *s
== '_' || *s
== '/' || *s
== '4' || *s
== '8';
869 as_warn ("Unknown opcode: `%s'", str
);
872 if ((pattern
= (struct alpha_opcode
*) hash_find (op_hash
, str
)) == NULL
)
874 as_warn ("Unknown opcode: `%s'", str
);
883 opcode
= pattern
->match
;
885 memset (insns
, 0, sizeof (*insns
));
886 for (i
= 0; i
< MAX_RELOCS
; i
++)
887 insns
[0].reloc
[i
].code
= BFD_RELOC_NONE
;
888 for (i
= 1; i
< MAX_INSNS
; i
++)
891 /* Build the opcode, checking as we go to make sure that the
893 for (args
= pattern
->args
;; ++args
)
898 case '\0': /* end of args */
917 case '(': /* these must match exactly */
926 case '1': /* next operand must be a register */
936 case 'a': /* $at: as temporary */
942 case 'g': /* $gp: base register */
945 mask
= base_register
;
948 case 's': /* $sp: stack pointer */
955 case 'r': /* any register */
956 if (!isdigit (c
= *s
++))
973 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
982 if ((c
== GP
) && first_32bit_quadrant
)
992 /* Got the register, now figure out where it goes in
1000 opcode
|= mask
<< SA
;
1005 opcode
|= mask
<< SB
;
1014 opcode
|= (mask
<< SA
) | mask
;
1017 case 'R': /* ra and rb are the same */
1018 opcode
|= (mask
<< SA
) | (mask
<< SB
);
1022 opcode
|= (mask
<< SA
) | (mask
<< SB
) | (mask
);
1028 case 'e': /* next operand is a floating point register */
1032 if (*s
++ == '$' && *s
++ == 'f' && isdigit (*s
))
1037 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1048 /* same encoding as gp registers */
1054 case 'h': /* bits 16..31 */
1055 insns
[0].reloc
= RELOC_16_31
;
1059 case 'l': /* bits 0..15 */
1060 insns
[0].reloc
[0].code
= BFD_RELOC_16
;
1063 case 'L': /* 21 bit PC relative immediate */
1064 insns
[0].reloc
[0].code
= BFD_RELOC_23_PCREL_S2
;
1065 insns
[0].reloc
[0].pcrel
= 1;
1068 case 'i': /* 14 bit immediate */
1069 if (OPCODE (opcode
) != 0x1a)
1070 /* Not a jmp variant?? */
1072 else if (opcode
& 0x8000)
1073 /* ret or jsr_coroutine */
1075 insns
[0].reloc
[0].code
= BFD_RELOC_14
;
1076 insns
[0].reloc
[0].pcrel
= 0;
1081 insns
[0].reloc
[0].code
= BFD_RELOC_ALPHA_HINT
;
1082 insns
[0].reloc
[0].pcrel
= 1;
1086 case 'b': /* 8 bit immediate */
1087 insns
[0].reloc
[0].code
= BFD_RELOC_8
;
1091 case 't': /* 12 bit 0...11 */
1092 insns
[0].reloc
= RELOC_0_12
;
1095 case '8': /* 8 bit 0...7 */
1096 insns
[0].reloc
= RELOC_0_8
;
1099 case 'I': /* 26 bit immediate */
1100 insns
[0].reloc
= RELOC_0_25
;
1112 getExpression (s
, &insns
[0]);
1114 /* Handle overflow in certain instructions by converting
1115 to other instructions. */
1116 if (insns
[0].reloc
[0].code
== BFD_RELOC_8
1117 && insns
[0].reloc
[0].exp
.X_op
== O_constant
1118 && (insns
[0].reloc
[0].exp
.X_add_number
< 0
1119 || insns
[0].reloc
[0].exp
.X_add_number
> 0xff))
1121 if (OPCODE (opcode
) == 0x10
1122 && (OP_FCN (opcode
) == 0x00 /* addl */
1123 || OP_FCN (opcode
) == 0x40 /* addl/v */
1124 || OP_FCN (opcode
) == 0x20 /* addq */
1125 || OP_FCN (opcode
) == 0x60 /* addq/v */
1126 || OP_FCN (opcode
) == 0x09 /* subl */
1127 || OP_FCN (opcode
) == 0x49 /* subl/v */
1128 || OP_FCN (opcode
) == 0x29 /* subq */
1129 || OP_FCN (opcode
) == 0x69 /* subq/v */
1130 || OP_FCN (opcode
) == 0x02 /* s4addl */
1131 || OP_FCN (opcode
) == 0x22 /* s4addq */
1132 || OP_FCN (opcode
) == 0x0b /* s4subl */
1133 || OP_FCN (opcode
) == 0x2b /* s4subq */
1134 || OP_FCN (opcode
) == 0x12 /* s8addl */
1135 || OP_FCN (opcode
) == 0x32 /* s8addq */
1136 || OP_FCN (opcode
) == 0x1b /* s8subl */
1137 || OP_FCN (opcode
) == 0x3b /* s8subq */
1139 /* Can we make it fit by negating? */
1140 && -insns
[0].reloc
[0].exp
.X_add_number
< 0xff
1141 && -insns
[0].reloc
[0].exp
.X_add_number
> 0)
1143 opcode
^= 0x120; /* convert add<=>sub */
1144 insns
[0].reloc
[0].exp
.X_add_number
*= -1;
1146 else if (at_ok
&& macro_ok
)
1148 /* Constant value supplied, but it's too large. */
1150 sprintf (expansion
, "lda $%d,%d($%d)", AT
,
1151 insns
[0].reloc
[0].exp
.X_add_number
, ZERO
);
1152 md_assemble (expansion
);
1153 opcode
|= 0x1000 /* use reg */ | (AT
<< SB
);
1154 insns
[0].reloc
[0].code
= BFD_RELOC_NONE
;
1157 as_bad ("overflow in 8-bit literal field in `operate' format insn");
1161 /* The following two.. take advantage of the fact that
1162 opcode already contains most of what we need to know.
1163 We just prepend to the instr an "ldah
1164 $r,%ml(expr)($base)" and turn this one (done later
1165 after we return) into something like "stq
1166 $r,%lo(expr)(at)" or "ldq $r,%lo(expr)($r)".
1168 NOTE: This can fail later on at link time if the
1169 offset from $base actually turns out to be more than
1170 2**31 or 2**47 if use_large_offsets is set. */
1171 case 'P': /* Addressing macros: PUT */
1172 mask
= AT
; /* register 'at' */
1175 case 'G': /* Addressing macros: GET */
1177 /* All it is missing is the expression, which is what we
1182 getExpression (s
, &insns
[0]);
1185 /* Must check for "lda ..,number" too */
1186 if (insns
[0].reloc
[0].exp
.X_op
== O_big
)
1188 as_warn ("Sorry, not yet. Put bignums in .data section yourself.");
1191 if (insns
[0].reloc
[0].exp
.X_op
== O_constant
)
1193 /* This only handles 32bit numbers */
1194 register int val
= insns
[0].reloc
[0].exp
.X_add_number
;
1195 register short sval
;
1197 insns
[0].reloc
[0].code
= BFD_RELOC_NONE
;
1198 insns
[1].reloc
[0].code
= BFD_RELOC_NONE
;
1201 if ((sval
!= val
) && (val
& 0x8000))
1207 if (optnum
&& (sval
== val
))
1209 /* optimize away the ldah */
1211 opcode
|= (ZERO
<< SB
) | (val
& 0xffff);
1216 insns
[1].opcode
= opcode
| (mask
<< SB
) | (val
& 0xffff);
1217 opcode
= 0x24000000 /*ldah*/ |
1218 mask
<< SA
| (ZERO
<< SB
) |
1219 ((val
>> 16) & 0xffff);
1222 else if (insns
[0].reloc
[0].exp
.X_op
== O_symbol
)
1224 unsigned long old_opcode
= opcode
;
1228 as_bad ("insn requires expansion but `nomacro' specified");
1229 else if (*args
== 'G')
1232 as_bad ("insn expansion requires AT use, but `noat' specified");
1235 num_gen
= load_expression (tmp_reg
, insns
);
1236 opcode
= insns
[0].opcode
;
1237 /* lda is opcode 8, 0x20000000 */
1238 if (OPCODE (old_opcode
) != 0x08)
1241 i
= &insns
[num_gen
++];
1242 i
->reloc
[0].code
= BFD_RELOC_NONE
;
1243 i
->opcode
= old_opcode
| (tmp_reg
<< SB
);
1250 insns
[1].reloc
[0].exp
= insns
[0].reloc
[0].exp
;
1252 /* Generate: ldah REG,x1(GP); OP ?,x0(REG) */
1254 abort (); /* relocs need fixing */
1256 insns
[1].reloc
= RELOC_0_15
;
1257 insns
[1].opcode
= opcode
| mask
<< SB
;
1259 insns
[0].reloc
= RELOC_16_31
;
1260 opcode
= 0x24000000 /*ldah*/ | mask
<< SA
| (base_register
<< SB
);
1266 /* Same failure modes as above, actually most of the
1267 same code shared. */
1268 case 'B': /* Builtins */
1273 case 'a': /* ldgp */
1275 if (first_32bit_quadrant
|| no_mixed_code
)
1277 switch (OUTPUT_FLAVOR
)
1279 case bfd_target_aout_flavour
:
1280 /* this is cmu's a.out version */
1281 insns
[0].reloc
[0].code
= BFD_RELOC_NONE
;
1282 /* generate "zap %r,0xf,%r" to take high 32 bits */
1283 opcode
|= 0x48001600 /* zap ?,#,?*/ | (0xf << SN
);
1285 case bfd_target_ecoff_flavour
:
1286 /* Given "ldgp R1,N(R2)", turn it into something
1287 like "ldah R1,###(R2) ; lda R1,###(R1)" with
1288 appropriate constants and relocations. */
1290 unsigned long r1
, r2
;
1291 unsigned long addend
= 0;
1296 insns
[0].reloc
[0].code
= BFD_RELOC_ALPHA_GPDISP_HI16
;
1297 insns
[0].reloc
[0].pcrel
= 1;
1298 insns
[0].reloc
[0].exp
.X_op
= O_symbol
;
1299 insns
[0].reloc
[0].exp
.X_add_symbol
= gp
;
1300 insns
[0].reloc
[0].exp
.X_add_number
= 0;
1301 insns
[0].opcode
= (0x24000000 /* ldah */
1304 insns
[1].reloc
[0].code
= BFD_RELOC_ALPHA_GPDISP_LO16
;
1305 insns
[1].reloc
[0].exp
.X_op
= O_symbol
;
1306 insns
[1].reloc
[0].exp
.X_add_symbol
= gp
;
1307 insns
[1].reloc
[0].exp
.X_add_number
= 4;
1308 insns
[1].reloc
[0].pcrel
= 1;
1309 insns
[1].opcode
= 0x20000000 | (r1
<< SA
) | (r1
<< SB
);
1310 opcode
= insns
[0].opcode
;
1311 /* merge in addend */
1312 insns
[1].opcode
|= addend
& 0xffff;
1313 insns
[0].opcode
|= ((addend
>> 16)
1314 + (addend
& 0x8000 ? 1 : 0));
1315 ecoff_set_gp_prolog_size (0);
1324 case 'b': /* setgp */
1325 switch (OUTPUT_FLAVOR
)
1327 case bfd_target_aout_flavour
:
1328 /* generate "zap %r,0xf,$gp" to take high 32 bits */
1329 opcode
|= 0x48001600 /* zap ?,#,?*/
1330 | (0xf << SN
) | (base_register
);
1337 case 'c': /* jsr $r,foo becomes
1340 Register 27, t12, is used by convention
1343 struct alpha_it
*jsr
;
1345 struct reloc_data
*r
;
1347 /* We still have to parse the function name */
1350 getExpression (s
, &insns
[0]);
1351 etmp
= insns
[0].reloc
[0].exp
;
1353 num_gen
= load_expression (PV
, &insns
[0]);
1356 jsr
= &insns
[num_gen
++];
1357 jsr
->opcode
= (0x68004000 /* jsr */
1363 /* LITUSE wasn't emitted yet */
1364 jsr
->reloc
[0].code
= BFD_RELOC_ALPHA_LITUSE
;
1365 jsr
->reloc
[0].exp
= lituse_jsr
;
1371 r
->code
= BFD_RELOC_ALPHA_HINT
;
1373 opcode
= insns
[0].opcode
;
1377 /* DIVISION and MODULUS. Yech.
1378 Convert OP x,y,result
1384 with appropriate optimizations if t10,t11,t12
1385 are the registers specified by the compiler.
1386 We are missing an obvious optimization
1387 opportunity here; if the ldq generated by the
1388 jsr assembly requires a cycle or two to make
1389 the value available, initiating it before one
1390 or two of the mov instructions would result in
1391 faster execution. */
1392 case '0': /* reml */
1393 case '1': /* divl */
1394 case '2': /* remq */
1395 case '3': /* divq */
1396 case '4': /* remlu */
1397 case '5': /* divlu */
1398 case '6': /* remqu */
1399 case '7': /* divqu */
1401 static char func
[8][6] = {
1402 "reml", "divl", "remq", "divq",
1403 "remlu", "divlu", "remqu", "divqu"
1408 /* All regs parsed, in opcode */
1410 /* Do the expansions, one instr at a time */
1412 reg
= (opcode
>> SA
) & 31;
1416 sprintf (expansion
, "mov $%d,$%d", reg
, T10
);
1417 md_assemble (expansion
);
1419 reg
= (opcode
>> SB
) & 31;
1421 /* we already overwrote it! */
1423 else if (reg
!= T11
)
1426 sprintf (expansion
, "mov $%d,$%d", reg
, T11
);
1427 md_assemble (expansion
);
1429 sprintf (expansion
, "lda $%d,__%s", PV
, func
[*args
- '0']);
1430 md_assemble (expansion
);
1431 sprintf (expansion
, "jsr $%d,($%d),__%s", T9
, PV
,
1433 md_assemble (expansion
);
1435 if (!first_32bit_quadrant
)
1440 md_assemble (expansion
);
1443 sprintf (expansion
, "ldgp $%d,0($%d)",
1445 md_assemble (expansion
);
1447 /* Use insns[0] to get at the result */
1448 if ((reg
= (opcode
& 31)) != PV
)
1449 opcode
= (0x47e00400 /* or zero,zero,zero */
1451 | reg
/* Rc */ ); /* pv->z */
1467 /* Args don't match. */
1468 if (&pattern
[1] - alpha_opcodes
< NUMOPCODES
1469 && !strcmp (pattern
->name
, pattern
[1].name
))
1477 as_warn ("Illegal operands");
1483 /* Args match, see if a float instructions and -nofloats */
1484 if (nofloats
&& pattern
->isa_float
)
1490 insns
[0].opcode
= opcode
;
1494 /* Turn a string in input_line_pointer into a floating point constant
1495 of type type, and store the appropriate bytes in *litP. The number
1496 of LITTLENUMS emitted is stored in *sizeP. An error message is
1497 returned, or NULL on OK. */
1499 /* Equal to MAX_PRECISION in atof-ieee.c */
1500 #define MAX_LITTLENUMS 6
1503 md_atof (type
, litP
, sizeP
)
1509 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1510 LITTLENUM_TYPE
*wordP
;
1512 char *atof_ieee (), *vax_md_atof ();
1518 /* VAX md_atof doesn't like "G" for some reason. */
1522 return vax_md_atof (type
, litP
, sizeP
);
1545 return "Bad call to MD_ATOF()";
1547 t
= atof_ieee (input_line_pointer
, type
, words
);
1549 input_line_pointer
= t
;
1550 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1552 for (wordP
= words
+ prec
- 1; prec
--;)
1554 md_number_to_chars (litP
, (long) (*wordP
--), sizeof (LITTLENUM_TYPE
));
1555 litP
+= sizeof (LITTLENUM_TYPE
);
1562 md_bignum_to_chars (buf
, bignum
, nchars
)
1564 LITTLENUM_TYPE
*bignum
;
1569 LITTLENUM_TYPE work
= *bignum
++;
1570 int nb
= CHARS_PER_LITTLENUM
;
1574 *buf
++ = work
& ((1 << BITS_PER_CHAR
) - 1);
1577 work
>>= BITS_PER_CHAR
;
1584 md_parse_option (argP
, cntP
, vecP
)
1594 #if 0 /* I have no idea if this stuff would work any more. And it's
1595 probably not right for ECOFF anyways. */
1596 /* Use base-register addressing, e.g. PIC code */
1599 if (first_32bit_quadrant
)
1601 first_32bit_quadrant
= 0;
1606 first_32bit_quadrant
= 1;
1607 base_register
= ZERO
;
1609 if (argP
[0][1] == 'k')
1615 if (!strcmp (*argP
, "nocpp"))
1626 /* XXXX Align to cache linesize XXXXX */
1633 /* Takes ".proc name,nargs" */
1634 name
= input_line_pointer
;
1635 c
= get_symbol_end ();
1636 p
= input_line_pointer
;
1637 symbolP
= symbol_find_or_make (name
);
1640 if (*input_line_pointer
!= ',')
1643 as_warn ("Expected comma after name \"%s\"", name
);
1646 ignore_rest_of_line ();
1650 input_line_pointer
++;
1651 temp
= get_absolute_expression ();
1653 /* symbolP->sy_other = (signed char) temp; */
1654 as_warn ("unhandled: .proc %s,%d", name
, temp
);
1655 demand_empty_rest_of_line ();
1662 char *name
= input_line_pointer
, ch
, *s
;
1665 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1666 input_line_pointer
++;
1667 ch
= *input_line_pointer
;
1668 *input_line_pointer
= '\0';
1671 if (s
[0] == 'n' && s
[1] == 'o')
1676 if (!strcmp ("reorder", s
))
1678 else if (!strcmp ("at", s
))
1680 else if (!strcmp ("macro", s
))
1683 as_warn ("Tried to set unrecognized symbol: %s", name
);
1684 *input_line_pointer
= ch
;
1685 demand_empty_rest_of_line ();
1688 /* @@ Is this right?? */
1690 md_pcrel_from (fixP
)
1693 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1694 switch (fixP
->fx_r_type
)
1696 case BFD_RELOC_ALPHA_GPDISP_HI16
:
1697 case BFD_RELOC_ALPHA_GPDISP_LO16
:
1700 return fixP
->fx_size
+ addr
;
1705 alpha_do_align (n
, fill
)
1710 && (now_seg
== text_section
1711 || !strcmp (now_seg
->name
, ".init")
1712 || !strcmp (now_seg
->name
, ".fini")))
1714 static const char nop_pattern
[] = { 0x1f, 0x04, 0xff, 0x47 };
1715 frag_align_pattern (n
, nop_pattern
, sizeof (nop_pattern
));
1722 md_apply_fix (fixP
, valueP
)
1729 char *p
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1733 switch (fixP
->fx_r_type
)
1735 /* The GPDISP relocations are processed internally with a symbol
1736 referring to the current function; we need to drop in a value
1737 which, when added to the address of the start of the function,
1738 gives the desired GP. */
1739 case BFD_RELOC_ALPHA_GPDISP_HI16
:
1740 case BFD_RELOC_ALPHA_GPDISP_LO16
:
1742 if (fixP
->fx_r_type
== BFD_RELOC_ALPHA_GPDISP_HI16
)
1744 assert (fixP
->fx_next
->fx_r_type
== BFD_RELOC_ALPHA_GPDISP_LO16
);
1747 fprintf_vma (stdout
, addend
);
1750 if (addend
& 0x8000)
1753 fixP
->fx_offset
= 4; /* @@ Compute this using fx_next. */
1759 fprintf_vma (stdout
, addend
);
1763 fixP
->fx_offset
= 0;
1765 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
1767 fixP
->fx_addsy
= section_symbol (absolute_section
);
1768 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
1772 /* Write 8 bits, shifted left 13 bit positions. */
1776 *p
|= (value
<< 5) & 0xe0;
1785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1786 "overflow in type-%d reloc", (int) fixP
->fx_r_type
);
1793 /* Don't want overflow checking. */
1796 if (fixP
->fx_pcrel
== 0
1797 && fixP
->fx_addsy
== 0)
1799 md_number_to_chars (p
, value
, size
);
1800 /* @@ Overflow checks?? */
1806 if (fixP
->fx_addsy
!= 0
1807 && fixP
->fx_addsy
->bsym
->section
!= absolute_section
)
1808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1809 "ret/jsr_coroutine requires constant in displacement field");
1810 else if (value
>> 14 != 0)
1811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1812 "overflow in 14-bit operand field of ret or jsr_coroutine");
1813 *p
++ = value
& 0xff;
1815 *p
= (*p
& 0xc0) | (value
& 0x3f);
1818 case BFD_RELOC_23_PCREL_S2
:
1819 /* Write 21 bits only. */
1821 *p
++ = value
& 0xff;
1823 *p
++ = value
& 0xff;
1826 *p
|= (value
& 0x1f);
1829 case BFD_RELOC_ALPHA_LITERAL
:
1830 case BFD_RELOC_ALPHA_LITUSE
:
1833 case BFD_RELOC_GPREL32
:
1834 assert (fixP
->fx_subsy
== gp
);
1835 value
= - alpha_gp_value
; /* huh? this works... */
1837 md_number_to_chars (p
, value
, 4);
1840 case BFD_RELOC_ALPHA_HINT
:
1841 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
1849 as_fatal ("unknown relocation type %d?", fixP
->fx_r_type
);
1853 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
1855 printf ("type %d reloc done?\n", fixP
->fx_r_type
);
1867 /* This bit only works because tc_frob_file gets called before
1868 obj_frob_file does. Sigh. */
1870 /* $zero and $f31 are read-only */
1871 alpha_gprmask
&= ~1;
1872 alpha_fprmask
&= ~1;
1875 /* The Alpha has support for some VAX floating point types, as well as for
1876 IEEE floating point. We consider IEEE to be the primary floating point
1877 format, and sneak in the VAX floating point support here. */
1878 #define md_atof vax_md_atof
1879 #include "config/atof-vax.c"