1 /* tc-alpha.c - Processor-specific code for the DEC Alpha CPU.
2 Copyright (C) 1989, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Carnegie Mellon University, 1993.
4 Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
5 Modified by Ken Raeburn for gas-2.x and ECOFF support.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 * Mach Operating System
25 * Copyright (c) 1993 Carnegie Mellon University
26 * All Rights Reserved.
28 * Permission to use, copy, modify and distribute this software and its
29 * documentation is hereby granted, provided that both the copyright
30 * notice and this permission notice appear in all copies of the
31 * software, derivative works or modified versions, and any portions
32 * thereof, and that both notices appear in supporting documentation.
34 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
35 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
36 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
38 * Carnegie Mellon requests users of this software to return to
40 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
41 * School of Computer Science
42 * Carnegie Mellon University
43 * Pittsburgh PA 15213-3890
45 * any improvements or extensions that they make and grant Carnegie the
46 * rights to redistribute these changes.
50 * 5-Oct-93 Alessandro Forin (af) at Carnegie-Mellon University
53 * Author: Alessandro Forin, Carnegie Mellon University
58 #include "alpha-opcode.h"
61 /* @@ Will a simple 0x8000 work here? If not, why not? */
62 #define GP_ADJUSTMENT (0x8000 - 0x10)
64 /* Which machine type is this? Currently stores an integer for the
65 model, one of: 21064, 21066, 21164. */
66 static unsigned long machine
;
68 /* These are exported to relaxing code, even though we don't do any
69 relaxing on this processor currently. */
70 const relax_typeS md_relax_table
[1];
71 int md_short_jump_size
= 4;
72 int md_long_jump_size
= 4;
74 /* handle of the OPCODE hash table */
75 static struct hash_control
*op_hash
;
77 /* Sections and symbols we'll want to keep track of. */
78 static segT lita_sec
, rdata
, sdata
, lit8_sec
, lit4_sec
;
79 static symbolS
*lit8_sym
, *lit4_sym
;
81 /* Setting for ".set [no]{at,macro}". */
82 static int at_ok
= 1, macro_ok
= 1;
84 /* Keep track of global pointer. */
85 valueT alpha_gp_value
;
88 /* We'll probably be using this relocation frequently, and we
89 will want to compare for it. */
90 static reloc_howto_type
*gpdisp_hi16_howto
;
92 /* These are exported to ECOFF code. */
93 unsigned long alpha_gprmask
, alpha_fprmask
;
95 /* Used for LITUSE relocations. */
96 static expressionS lituse_basereg
, lituse_byteoff
, lituse_jsr
;
98 /* Address size: In OSF/1 1.3, an undocumented "-32addr" option will
99 cause all addresses to be treated as 32-bit values in memory. (The
100 in-register versions are all sign-extended to 64 bits, of course.)
101 Some other systems may want this option too. */
104 /* Imported functions -- they should be defined in header files somewhere. */
105 extern segT
subseg_get ();
106 extern PTR
bfd_alloc_by_size_t ();
107 extern void s_globl (), s_long (), s_short (), s_space (), cons (), s_text (),
108 s_data (), float_cons ();
110 /* Static functions, needing forward declarations. */
111 static void s_mask (), s_base (), s_proc (), s_alpha_set ();
112 static void s_gprel32 (), s_rdata (), s_sdata (), s_alpha_comm ();
113 static int alpha_ip ();
115 const pseudo_typeS md_pseudo_table
[] =
117 {"common", s_comm
, 0}, /* is this used? */
118 {"comm", s_alpha_comm
, 0}, /* osf1 compiler does this */
119 {"rdata", s_rdata
, 0},
120 {"sdata", s_sdata
, 0},
121 {"gprel32", s_gprel32
, 0},
122 {"t_floating", float_cons
, 'd'},
123 {"s_floating", float_cons
, 'f'},
124 {"f_floating", float_cons
, 'F'},
125 {"g_floating", float_cons
, 'G'},
126 {"d_floating", float_cons
, 'D'},
129 {"aproc", s_proc
, 1},
130 {"set", s_alpha_set
, 0},
131 {"reguse", s_ignore
, 0},
132 {"livereg", s_ignore
, 0},
133 {"extern", s_ignore
, 0}, /*??*/
134 {"base", s_base
, 0}, /*??*/
135 {"option", s_ignore
, 0},
136 {"prologue", s_ignore
, 0},
137 {"aent", s_ignore
, 0},
138 {"ugen", s_ignore
, 0},
140 /* We don't do any optimizing, so we can safely ignore these. */
141 {"noalias", s_ignore
, 0},
142 {"alias", s_ignore
, 0},
147 #define SA 21 /* shift for register Ra */
148 #define SB 16 /* shift for register Rb */
149 #define SC 0 /* shift for register Rc */
150 #define SN 13 /* shift for 8 bit immediate # */
156 #define RA 26 /* note: same as T12 */
163 #define OPCODE(X) (((X) >> 26) & 0x3f)
164 #define OP_FCN(X) (((X) >> 5) & 0x7f)
166 #ifndef FIRST_32BIT_QUADRANT
167 #define FIRST_32BIT_QUADRANT 0
170 int first_32bit_quadrant
= FIRST_32BIT_QUADRANT
;
171 int base_register
= FIRST_32BIT_QUADRANT
? ZERO
: GP
;
173 int no_mixed_code
= 0;
176 /* This array holds the chars that always start a comment. If the
177 pre-processor is disabled, these aren't very useful */
178 const char comment_chars
[] = "#";
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that '/*' will always start a comment */
187 const char line_comment_chars
[] = "#!";
189 /* Chars that can be used to separate mant from exp in floating point nums */
190 const char EXP_CHARS
[] = "eE";
192 const char line_separator_chars
[1];
194 /* Chars that mean this number is a floating point constant, as in
195 "0f12.456" or "0d1.2345e12". */
196 /* @@ Do all of these really get used on the alpha?? */
197 char FLT_CHARS
[] = "rRsSfFdDxXpP";
199 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
200 changed in read.c. Ideally it shouldn't have to know about it at all,
201 but nothing is ideal around here. */
206 bfd_reloc_code_real_type code
;
209 /* Occasionally, two relocations will be desired for one address.
210 Mainly only in cases like "jsr $r,foo" where we want both a LITUSE
215 unsigned long opcode
; /* need at least 32 bits */
216 struct reloc_data reloc
[MAX_RELOCS
];
219 static void getExpression (char *str
, struct alpha_it
*insn
);
220 static char *expr_end
;
222 #define note_gpreg(R) (alpha_gprmask |= (1 << (R)))
223 #define note_fpreg(R) (alpha_fprmask |= (1 << (R)))
226 tc_get_register (frame
)
233 if (*input_line_pointer
== '$')
235 input_line_pointer
++;
236 if (input_line_pointer
[0] == 's'
237 && input_line_pointer
[1] == 'p')
239 input_line_pointer
+= 2;
243 framereg
= get_absolute_expression ();
244 framereg
&= 31; /* ? */
247 as_warn ("frame reg expected, using $%d.", framereg
);
249 note_gpreg (framereg
);
259 temp
= get_absolute_expression ();
262 rdata
= subseg_get (".rdata", 0);
263 subseg_set (rdata
, (subsegT
) temp
);
265 rdata
= subseg_new (".rdata", 0);
267 demand_empty_rest_of_line ();
276 temp
= get_absolute_expression ();
279 sdata
= subseg_get (".sdata", 0);
280 subseg_set (sdata
, (subsegT
) temp
);
282 sdata
= subseg_new (".sdata", 0);
284 demand_empty_rest_of_line ();
288 s_alpha_comm (ignore
)
295 register symbolS
*symbolP
;
297 name
= input_line_pointer
;
298 c
= get_symbol_end ();
299 /* just after name is now '\0' */
300 p
= input_line_pointer
;
303 /* Alpha OSF/1 compiler doesn't provide the comma, gcc does. */
304 if (*input_line_pointer
== ',')
306 input_line_pointer
++;
309 if ((temp
= get_absolute_expression ()) < 0)
311 as_warn (".COMMon length (%ld.) <0! Ignored.", (long) temp
);
312 ignore_rest_of_line ();
316 symbolP
= symbol_find_or_make (name
);
318 if (S_IS_DEFINED (symbolP
))
320 as_bad ("Ignoring attempt to re-define symbol");
321 ignore_rest_of_line ();
324 if (S_GET_VALUE (symbolP
))
326 if (S_GET_VALUE (symbolP
) != (valueT
) temp
)
327 as_bad ("Length of .comm \"%s\" is already %ld. Not changed to %ld.",
328 S_GET_NAME (symbolP
),
329 (long) S_GET_VALUE (symbolP
),
334 S_SET_VALUE (symbolP
, (valueT
) temp
);
335 S_SET_EXTERNAL (symbolP
);
338 know (symbolP
->sy_frag
== &zero_address_frag
);
339 demand_empty_rest_of_line ();
343 tc_gen_reloc (sec
, fixp
)
349 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
350 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
351 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
353 if (fixp
->fx_r_type
> BFD_RELOC_UNUSED
|| fixp
->fx_r_type
< 0)
356 if (fixp
->fx_r_type
== BFD_RELOC_ALPHA_GPDISP_HI16
)
358 if (!gpdisp_hi16_howto
)
359 gpdisp_hi16_howto
= bfd_reloc_type_lookup (stdoutput
,
361 reloc
->howto
= gpdisp_hi16_howto
;
364 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
365 assert (reloc
->howto
!= 0);
366 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
368 as_fatal ("bug in handling type-%d relocs", fixp
->fx_r_type
);
371 assert (!fixp
->fx_pcrel
== !reloc
->howto
->pc_relative
);
373 if (fixp
->fx_r_type
== BFD_RELOC_ALPHA_LITERAL
)
375 /* fake out bfd_perform_relocation. sigh */
376 reloc
->addend
= -alpha_gp_value
;
378 else if (reloc
->howto
->pc_relative
&& reloc
->howto
->pcrel_offset
)
380 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
383 reloc
->addend
= fixp
->fx_offset
;
390 if (first_32bit_quadrant
)
392 /* not fatal, but it might not work in the end */
393 as_warn ("File overrides no-base-register option.");
394 first_32bit_quadrant
= 0;
398 if (*input_line_pointer
== '$')
400 input_line_pointer
++;
401 if (*input_line_pointer
== 'r')
402 input_line_pointer
++;
405 base_register
= get_absolute_expression ();
406 if (base_register
< 0 || base_register
> 31)
409 as_warn ("Bad base register, using $r.", base_register
);
411 demand_empty_rest_of_line ();
425 e
.X_add_symbol
= section_symbol (absolute_section
);
436 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &e
, 0,
441 create_literal_section (secp
, name
)
445 segT current_section
= now_seg
;
446 int current_subsec
= now_subseg
;
449 *secp
= new_sec
= subseg_new (name
, 0);
450 subseg_set (current_section
, current_subsec
);
451 bfd_set_section_alignment (stdoutput
, new_sec
, 3);
452 bfd_set_section_flags (stdoutput
, new_sec
,
453 SEC_RELOC
| SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
457 #define create_lita_section() create_literal_section (&lita_sec, ".lita")
460 get_lit8_offset (val
)
466 create_literal_section (&lit8_sec
, ".lit8");
467 lit8_sym
= section_symbol (lit8_sec
);
469 retval
= add_to_literal_pool ((symbolS
*) 0, val
, lit8_sec
, 8);
470 if (retval
>= 0xfff0)
471 as_fatal ("overflow in fp literal (.lit8) table");
476 get_lit4_offset (val
)
482 create_literal_section (&lit4_sec
, ".lit4");
483 lit4_sym
= section_symbol (lit4_sec
);
485 retval
= add_to_literal_pool ((symbolS
*) 0, val
, lit4_sec
, 4);
486 if (retval
>= 0xfff0)
487 as_fatal ("overflow in fp literal (.lit4) table");
491 #define load_insn(NAME, OP) (hash_insert (op_hash, (NAME), (PTR) (OP)))
494 load_insn_table (ops
, size
)
495 struct alpha_opcode
*ops
;
498 struct alpha_opcode
*end
= ops
+ size
;
499 struct alpha_opcode
*op
;
502 for (op
= ops
; op
< end
; )
508 retval
= load_insn (op
->name
, op
);
510 as_fatal ("internal error: can't hash opcode `%s': %s",
517 || !strcmp (op
->name
, name
)));
519 /* Some opcodes include modifiers of various sorts with a "/mod"
520 syntax, like the architecture documentation suggests. However,
521 for use with gcc at least, we also need to access those same
522 opcodes without the "/". */
523 for (op
= ops
; op
< end
; )
527 if (strchr (name
, '/'))
529 const char *name2
, *p
, *q
;
531 name2
= xmalloc (strlen (name
));
541 /* Ignore failures -- the opcode table does duplicate some
542 variants in different forms, like "hw_stq" and "hw_st/q".
543 Maybe the variants can be eliminated, and this error checking
545 load_insn (name2
, op
);
552 || !strcmp (op
->name
, name
)));
556 /* This function is called once, at assembler startup time. It should
557 set up all the tables, etc. that the MD part of the assembler will
558 need, that can be determined before arguments are parsed. */
566 op_hash
= hash_new ();
567 load_insn_table (alpha_opcodes
, NUMOPCODES
);
569 /* Default to 21064 PAL instructions. */
577 load_insn_table (alpha_pal21064_opcodes
, NUM21064OPCODES
);
580 load_insn_table (alpha_pal21164_opcodes
, NUM21164OPCODES
);
583 as_fatal ("palcode set unknown (internal error)");
586 lituse_basereg
.X_op
= O_constant
;
587 lituse_basereg
.X_add_number
= 1;
588 lituse_byteoff
.X_op
= O_constant
;
589 lituse_byteoff
.X_add_number
= 2;
590 lituse_jsr
.X_op
= O_constant
;
591 lituse_jsr
.X_add_number
= 3;
593 /* So .sbss will get used for tiny objects. */
594 bfd_set_gp_size (stdoutput
, 8);
595 create_lita_section ();
596 /* For handling the GP, create a symbol that won't be output in the
597 symbol table. We'll edit it out of relocs later. */
598 gp
= symbol_new ("<GP value>", lita_sec
, 0x8000, &zero_address_frag
);
599 symbol_remove (gp
, &symbol_rootP
, &symbol_lastP
);
606 struct alpha_it
*insn
;
613 /* put out the opcode */
614 md_number_to_chars (toP
, insn
->opcode
, 4);
616 /* put out the symbol-dependent stuff */
617 for (j
= 0; j
< MAX_RELOCS
; j
++)
619 struct reloc_data
*r
= &insn
->reloc
[j
];
622 if (r
->code
!= BFD_RELOC_NONE
)
624 if (r
->exp
.X_op
== O_constant
)
626 r
->exp
.X_add_symbol
= section_symbol (absolute_section
);
627 r
->exp
.X_op
= O_symbol
;
629 f
= fix_new_exp (frag_now
, (toP
- frag_now
->fr_literal
), 4,
630 &r
->exp
, r
->pcrel
, r
->code
);
632 if (r
->code
== BFD_RELOC_ALPHA_GPDISP_LO16
)
634 static bit_fixS cookie
;
635 /* @@ This'll make the range checking in write.c shut up. */
636 f
->fx_bit_fixP
= &cookie
;
647 struct alpha_it insns
[MAX_INSNS
];
649 count
= alpha_ip (str
, insns
);
653 for (i
= 0; i
< count
; i
++)
654 emit_insn (&insns
[i
]);
664 vma
= bfd_get_section_vma (foo
, sec
);
665 if (vma
&& vma
< alpha_gp_value
)
666 alpha_gp_value
= vma
;
672 if (alpha_gp_value
!= 0)
675 /* Get minus-one in whatever width... */
676 alpha_gp_value
= 0; alpha_gp_value
--;
678 /* Select the smallest VMA of these existing sections. */
679 maybe_set_gp (lita_sec
);
680 /* maybe_set_gp (sdata); Was disabled before -- should we use it? */
682 maybe_set_gp (lit8_sec
);
683 maybe_set_gp (lit4_sec
);
686 alpha_gp_value
+= GP_ADJUSTMENT
;
688 S_SET_VALUE (gp
, alpha_gp_value
);
691 printf ("Chose GP value of %lx\n", alpha_gp_value
);
696 alpha_force_relocation (f
)
699 switch (f
->fx_r_type
)
701 case BFD_RELOC_ALPHA_GPDISP_HI16
:
702 case BFD_RELOC_ALPHA_GPDISP_LO16
:
703 case BFD_RELOC_ALPHA_LITERAL
:
704 case BFD_RELOC_ALPHA_LITUSE
:
705 case BFD_RELOC_GPREL32
:
707 case BFD_RELOC_ALPHA_HINT
:
712 case BFD_RELOC_23_PCREL_S2
:
723 alpha_fix_adjustable (f
)
726 /* Are there any relocation types for which we must generate a reloc
727 but we can adjust the values contained within it? */
728 switch (f
->fx_r_type
)
730 case BFD_RELOC_ALPHA_GPDISP_HI16
:
731 case BFD_RELOC_ALPHA_GPDISP_LO16
:
733 case BFD_RELOC_GPREL32
:
736 return !alpha_force_relocation (f
);
740 md_section_align (seg
, size
)
745 /* This should probably be handled within BFD, or by pulling the
746 number from BFD at least. */
754 /* Add this thing to the .lita section and produce a LITERAL reloc referring
757 /* Are we currently eligible to emit a LITUSE reloc for the literal
758 references just generated? */
759 static int lituse_pending
;
762 load_symbol_address (reg
, insn
)
764 struct alpha_it
*insn
;
766 static symbolS
*lita_sym
;
777 lita_sym
= section_symbol (lita_sec
);
778 S_CLEAR_EXTERNAL (lita_sym
);
781 retval
= add_to_literal_pool (insn
->reloc
[0].exp
.X_add_symbol
,
782 insn
->reloc
[0].exp
.X_add_number
,
785 /* Now emit a LITERAL relocation for the original section. */
786 insn
->reloc
[0].exp
.X_op
= O_symbol
;
787 insn
->reloc
[0].exp
.X_add_symbol
= lita_sym
;
788 insn
->reloc
[0].exp
.X_add_number
= retval
;
789 insn
->reloc
[0].code
= BFD_RELOC_ALPHA_LITERAL
;
792 if (retval
== 0x8000)
794 as_fatal ("overflow in literal (.lita) table");
797 insn
->opcode
= (0xa0000000 /* ldl */
799 | (base_register
<< SB
)
802 insn
->opcode
= (0xa4000000 /* ldq */
804 | (base_register
<< SB
)
806 note_gpreg (base_register
);
809 /* To load an address with a single instruction,
810 emit a LITERAL reloc in this section, and a REFQUAD
811 for the .lita section, so that we'll be able to access
813 lda REG, xx -> ldq REG, -32752(gp)
814 lda REG, xx+4 -> ldq REG, -32752(gp)
817 The offsets need to start near -0x8000, and the generated LITERAL
818 relocations should negate the offset. I don't completely grok the
822 load_expression (reg
, insn
)
824 struct alpha_it
*insn
;
829 if (insn
->reloc
[0].exp
.X_add_symbol
->bsym
->flags
& BSF_SECTION_SYM
)
835 addend
= insn
->reloc
[0].exp
.X_add_number
;
836 insn
->reloc
[0].exp
.X_add_number
= 0;
838 load_symbol_address (reg
, insn
);
844 if ((x
& ~0x7fff) != 0
845 && (x
& ~0x7fff) + 0x8000 != 0)
847 as_bad ("assembler not prepared to handle constants >16 bits yet");
851 insn
[1].opcode
= (0x20000000 /* lda */
854 | (addend
& 0xffff));
855 insn
[1].reloc
[0].code
= BFD_RELOC_ALPHA_LITUSE
;
856 insn
[1].reloc
[0].exp
= lituse_basereg
;
863 getExpression (str
, this_insn
)
865 struct alpha_it
*this_insn
;
870 #if 0 /* Not converted to bfd yet, and I don't think we need them
871 for ECOFF. Re-adding a.out support will probably require
873 static const struct am
{
875 bfd_reloc_code_real_type reloc
;
877 { "hi", RELOC_48_63
},
878 { "lo", RELOC_0_15
},
879 { "ml", RELOC_16_31
},
880 { "mh", RELOC_32_47
},
881 { "uhi", RELOC_U_48_63
},
882 { "uml", RELOC_U_16_31
},
883 { "umh", RELOC_U_32_47
},
887 /* Handle macros: "%macroname(expr)" */
898 while (*q
&& *p
== *q
)
906 str
= p
; /* keep the '(' */
907 this_insn
->reloc
= m
->reloc
;
912 save_in
= input_line_pointer
;
913 input_line_pointer
= str
;
915 seg
= expression (&this_insn
->reloc
[0].exp
);
916 /* XXX validate seg and exp, make sure they're reasonable */
917 expr_end
= input_line_pointer
;
918 input_line_pointer
= save_in
;
921 /* All of these should soon be changed to just emit words to the
924 emit_unaligned_io (dir
, addr_reg
, addr_offset
, reg
)
930 sprintf (buf
, "%sq_u $%d,%ld($%d)", dir
, reg
, (long) addr_offset
, addr_reg
);
935 emit_load_unal (addr_reg
, addr_offset
, reg
)
939 emit_unaligned_io ("ld", addr_reg
, addr_offset
, reg
);
943 emit_store_unal (addr_reg
, addr_offset
, reg
)
947 emit_unaligned_io ("st", addr_reg
, addr_offset
, reg
);
951 emit_byte_manip_r (op
, in
, mask
, out
, mode
, which
)
955 sprintf (buf
, "%s%c%c $%d,$%d,$%d", op
, mode
, which
, in
, mask
, out
);
960 emit_extract_r (in
, mask
, out
, mode
, which
)
962 emit_byte_manip_r ("ext", in
, mask
, out
, mode
, which
);
966 emit_insert_r (in
, mask
, out
, mode
, which
)
968 emit_byte_manip_r ("ins", in
, mask
, out
, mode
, which
);
972 emit_mask_r (in
, mask
, out
, mode
, which
)
974 emit_byte_manip_r ("msk", in
, mask
, out
, mode
, which
);
978 emit_sign_extend (reg
, size
)
981 sprintf (buf
, "sll $%d,0x%x,$%d", reg
, 64 - size
, reg
);
983 sprintf (buf
, "sra $%d,0x%x,$%d", reg
, 64 - size
, reg
);
988 emit_bis_r (in1
, in2
, out
)
991 sprintf (buf
, "bis $%d,$%d,$%d", in1
, in2
, out
);
995 /* Note that for now, this function is called recursively (by way of
996 calling md_assemble again). Some of the macros defined as part of
997 the assembly language are currently rewritten as sequences of
998 strings to be assembled. See, for example, the handling of "divq".
1000 For efficiency, this should be fixed someday. */
1002 alpha_ip (str
, insns
)
1004 struct alpha_it insns
[];
1010 struct alpha_opcode
*pattern
;
1012 unsigned int opcode
;
1014 int match
= 0, num_gen
= 1;
1018 islower (*s
) || *s
== '_' || *s
== '/' || *s
== '4' || *s
== '8';
1037 as_warn ("Unknown opcode: `%s'", str
);
1040 if ((pattern
= (struct alpha_opcode
*) hash_find (op_hash
, str
)) == NULL
)
1042 as_warn ("Unknown opcode: `%s'", str
);
1051 opcode
= pattern
->match
;
1053 memset (insns
, 0, sizeof (*insns
));
1054 for (i
= 0; i
< MAX_RELOCS
; i
++)
1055 insns
[0].reloc
[i
].code
= BFD_RELOC_NONE
;
1056 for (i
= 1; i
< MAX_INSNS
; i
++)
1057 insns
[i
] = insns
[0];
1059 /* Build the opcode, checking as we go to make sure that the
1061 for (args
= pattern
->args
;; ++args
)
1066 case '\0': /* end of args */
1085 case '(': /* these must match exactly */
1094 case '1': /* next operand must be a register */
1104 case 'a': /* $at: as temporary */
1110 case 'g': /* $gp: base register */
1113 mask
= base_register
;
1116 case 's': /* $sp: stack pointer */
1123 case 'r': /* any register */
1124 if (!isdigit (c
= *s
++))
1141 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1150 if ((c
== GP
) && first_32bit_quadrant
)
1160 /* Got the register, now figure out where it goes in
1168 opcode
|= mask
<< SA
;
1173 opcode
|= mask
<< SB
;
1182 opcode
|= (mask
<< SA
) | mask
;
1185 case 'R': /* ra and rb are the same */
1186 opcode
|= (mask
<< SA
) | (mask
<< SB
);
1190 opcode
|= (mask
<< SA
) | (mask
<< SB
) | (mask
);
1196 case 'e': /* next operand is a floating point register */
1200 if (*s
++ == '$' && *s
++ == 'f' && isdigit (*s
))
1205 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1216 /* same encoding as gp registers */
1222 case 'h': /* bits 16..31 */
1223 insns
[0].reloc
= RELOC_16_31
;
1227 case 'l': /* bits 0..15 */
1228 insns
[0].reloc
[0].code
= BFD_RELOC_16
;
1231 case 'L': /* 21 bit PC relative immediate */
1232 insns
[0].reloc
[0].code
= BFD_RELOC_23_PCREL_S2
;
1233 insns
[0].reloc
[0].pcrel
= 1;
1236 case 'i': /* 14 bit immediate */
1237 if (OPCODE (opcode
) != 0x1a)
1238 /* Not a jmp variant?? */
1240 else if (opcode
& 0x8000)
1241 /* ret or jsr_coroutine */
1243 insns
[0].reloc
[0].code
= BFD_RELOC_14
;
1244 insns
[0].reloc
[0].pcrel
= 0;
1249 insns
[0].reloc
[0].code
= BFD_RELOC_ALPHA_HINT
;
1250 insns
[0].reloc
[0].pcrel
= 1;
1254 case 'b': /* 8 bit immediate */
1255 insns
[0].reloc
[0].code
= BFD_RELOC_8
;
1258 case 'I': /* 26 bit immediate, for PALcode */
1259 insns
[0].reloc
[0].code
= BFD_RELOC_26
;
1263 case 't': /* 12 bit 0...11 */
1264 insns
[0].reloc
= RELOC_0_12
;
1267 case '8': /* 8 bit 0...7 */
1268 insns
[0].reloc
= RELOC_0_8
;
1271 case 'I': /* 26 bit immediate */
1272 insns
[0].reloc
= RELOC_0_25
;
1283 getExpression (s
, &insns
[0]);
1285 /* Handle overflow in certain instructions by converting
1286 to other instructions. */
1287 if (insns
[0].reloc
[0].code
== BFD_RELOC_8
1288 && insns
[0].reloc
[0].exp
.X_op
== O_constant
1289 && (insns
[0].reloc
[0].exp
.X_add_number
< 0
1290 || insns
[0].reloc
[0].exp
.X_add_number
> 0xff))
1292 if (OPCODE (opcode
) == 0x10
1293 && (OP_FCN (opcode
) == 0x00 /* addl */
1294 || OP_FCN (opcode
) == 0x40 /* addl/v */
1295 || OP_FCN (opcode
) == 0x20 /* addq */
1296 || OP_FCN (opcode
) == 0x60 /* addq/v */
1297 || OP_FCN (opcode
) == 0x09 /* subl */
1298 || OP_FCN (opcode
) == 0x49 /* subl/v */
1299 || OP_FCN (opcode
) == 0x29 /* subq */
1300 || OP_FCN (opcode
) == 0x69 /* subq/v */
1301 || OP_FCN (opcode
) == 0x02 /* s4addl */
1302 || OP_FCN (opcode
) == 0x22 /* s4addq */
1303 || OP_FCN (opcode
) == 0x0b /* s4subl */
1304 || OP_FCN (opcode
) == 0x2b /* s4subq */
1305 || OP_FCN (opcode
) == 0x12 /* s8addl */
1306 || OP_FCN (opcode
) == 0x32 /* s8addq */
1307 || OP_FCN (opcode
) == 0x1b /* s8subl */
1308 || OP_FCN (opcode
) == 0x3b /* s8subq */
1310 /* Can we make it fit by negating? */
1311 && -insns
[0].reloc
[0].exp
.X_add_number
< 0xff
1312 && -insns
[0].reloc
[0].exp
.X_add_number
> 0)
1314 opcode
^= 0x120; /* convert add<=>sub */
1315 insns
[0].reloc
[0].exp
.X_add_number
*= -1;
1317 else if (at_ok
&& macro_ok
)
1319 /* Constant value supplied, but it's too large. */
1321 sprintf (expansion
, "lda $%d,%d($%d)", AT
,
1322 insns
[0].reloc
[0].exp
.X_add_number
, ZERO
);
1323 md_assemble (expansion
);
1324 opcode
|= 0x1000 /* use reg */ | (AT
<< SB
);
1325 insns
[0].reloc
[0].code
= BFD_RELOC_NONE
;
1328 as_bad ("overflow in 8-bit literal field in `operate' format insn");
1334 int format
, length
, mode
, i
, size
;
1335 char temp
[20 /*MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT*/];
1337 static const char formats
[4] = "FGfd";
1338 bfd_vma bits
, offset
;
1339 char *old_input_line_pointer
= input_line_pointer
;
1341 input_line_pointer
= s
;
1343 memset (temp
, 0, sizeof (temp
));
1344 mode
= (opcode
>> 26) & 3;
1345 format
= formats
[mode
];
1346 err
= md_atof (format
, temp
, &length
);
1349 as_bad ("Bad floating literal: %s", err
);
1354 /* Generate little-endian number from byte sequence. */
1356 for (i
= length
- 1; i
>= 0; i
--)
1357 bits
+= ((bfd_vma
)(temp
[i
] & 0xff)) << (i
* 8);
1362 offset
= get_lit8_offset (bits
) - 0x8000;
1363 insns
[0].reloc
[0].exp
.X_add_symbol
= lit8_sym
;
1364 insns
[0].reloc
[0].exp
.X_add_number
= 0x8000;
1367 offset
= get_lit4_offset (bits
) - 0x8000;
1368 insns
[0].reloc
[0].exp
.X_add_symbol
= lit4_sym
;
1369 insns
[0].reloc
[0].exp
.X_add_number
= 0x8000;
1374 insns
[0].reloc
[0].exp
.X_op
= O_symbol
;
1376 num_gen
= load_expression (AT
, &insns
[0]);
1379 insns
[num_gen
].reloc
[0].code
= BFD_RELOC_ALPHA_LITUSE
;
1380 insns
[num_gen
].reloc
[0].exp
= lituse_basereg
;
1383 insns
[num_gen
++].opcode
= opcode
| (AT
<< SB
) | offset
;
1384 opcode
= insns
[0].opcode
;
1385 s
= input_line_pointer
;
1386 input_line_pointer
= old_input_line_pointer
;
1390 /* The following two.. take advantage of the fact that
1391 opcode already contains most of what we need to know.
1392 We just prepend to the instr an "ldah
1393 $r,%ml(expr)($base)" and turn this one (done later
1394 after we return) into something like "stq
1395 $r,%lo(expr)(at)" or "ldq $r,%lo(expr)($r)".
1397 NOTE: This can fail later on at link time if the
1398 offset from $base actually turns out to be more than
1399 2**31 or 2**47 if use_large_offsets is set. */
1400 case 'P': /* Addressing macros: PUT */
1401 mask
= AT
; /* register 'at' */
1404 case 'G': /* Addressing macros: GET */
1406 /* All it is missing is the expression, which is what we
1411 getExpression (s
, &insns
[0]);
1414 /* Must check for "lda ..,number" too */
1415 if (insns
[0].reloc
[0].exp
.X_op
== O_big
)
1417 as_warn ("Sorry, not yet. Put bignums in .data section yourself.");
1420 if (insns
[0].reloc
[0].exp
.X_op
== O_constant
)
1422 /* This only handles 32bit numbers */
1423 register int val
= insns
[0].reloc
[0].exp
.X_add_number
;
1424 register short sval
;
1426 insns
[0].reloc
[0].code
= BFD_RELOC_NONE
;
1427 insns
[1].reloc
[0].code
= BFD_RELOC_NONE
;
1430 if ((sval
!= val
) && (val
& 0x8000))
1436 if (optnum
&& (sval
== val
))
1438 /* optimize away the ldah */
1440 opcode
|= (ZERO
<< SB
) | (val
& 0xffff);
1445 insns
[1].opcode
= opcode
| (mask
<< SB
) | (val
& 0xffff);
1446 opcode
= 0x24000000 /*ldah*/ |
1447 mask
<< SA
| (ZERO
<< SB
) |
1448 ((val
>> 16) & 0xffff);
1451 else if (insns
[0].reloc
[0].exp
.X_op
== O_symbol
)
1453 unsigned long old_opcode
= opcode
;
1457 as_bad ("insn requires expansion but `nomacro' specified");
1458 else if (*args
== 'G')
1461 as_bad ("insn expansion requires AT use, but `noat' specified");
1464 num_gen
= load_expression (tmp_reg
, insns
);
1465 opcode
= insns
[0].opcode
;
1466 /* lda is opcode 8, 0x20000000, and the macros that use
1467 this code have an opcode field of 0. The latter
1468 require further processing, and we don't have the
1469 true opcode here. */
1470 if (OPCODE (old_opcode
) != 0
1471 && OPCODE (old_opcode
) != 0x08)
1474 i
= &insns
[num_gen
++];
1475 i
->opcode
= old_opcode
| (tmp_reg
<< SB
);
1479 i
->reloc
[0].code
= BFD_RELOC_ALPHA_LITUSE
;
1480 i
->reloc
[0].exp
= lituse_basereg
;
1489 insns
[1].reloc
[0].exp
= insns
[0].reloc
[0].exp
;
1491 /* Generate: ldah REG,x1(GP); OP ?,x0(REG) */
1493 abort (); /* relocs need fixing */
1495 insns
[1].reloc
= RELOC_0_15
;
1496 insns
[1].opcode
= opcode
| mask
<< SB
;
1498 insns
[0].reloc
= RELOC_16_31
;
1499 opcode
= 0x24000000 /*ldah*/ | mask
<< SA
| (base_register
<< SB
);
1505 /* Same failure modes as above, actually most of the
1506 same code shared. */
1507 case 'B': /* Builtins */
1512 case 'a': /* ldgp */
1514 if (first_32bit_quadrant
|| no_mixed_code
)
1516 switch (OUTPUT_FLAVOR
)
1518 case bfd_target_aout_flavour
:
1519 /* this is cmu's a.out version */
1520 insns
[0].reloc
[0].code
= BFD_RELOC_NONE
;
1521 /* generate "zap %r,0xf,%r" to take high 32 bits */
1522 opcode
|= 0x48001600 /* zap ?,#,?*/ | (0xf << SN
);
1524 case bfd_target_ecoff_flavour
:
1525 /* Given "ldgp R1,N(R2)", turn it into something
1526 like "ldah R1,###(R2) ; lda R1,###(R1)" with
1527 appropriate constants and relocations. */
1529 unsigned long r1
, r2
;
1530 unsigned long addend
= 0;
1535 insns
[0].reloc
[0].code
= BFD_RELOC_ALPHA_GPDISP_HI16
;
1536 insns
[0].reloc
[0].pcrel
= 1;
1537 insns
[0].reloc
[0].exp
.X_op
= O_symbol
;
1538 insns
[0].reloc
[0].exp
.X_add_symbol
= gp
;
1539 insns
[0].reloc
[0].exp
.X_add_number
= 0;
1540 insns
[0].opcode
= (0x24000000 /* ldah */
1543 insns
[1].reloc
[0].code
= BFD_RELOC_ALPHA_GPDISP_LO16
;
1544 insns
[1].reloc
[0].exp
.X_op
= O_symbol
;
1545 insns
[1].reloc
[0].exp
.X_add_symbol
= gp
;
1546 insns
[1].reloc
[0].exp
.X_add_number
= 4;
1547 insns
[1].reloc
[0].pcrel
= 1;
1548 insns
[1].opcode
= 0x20000000 | (r1
<< SA
) | (r1
<< SB
);
1549 opcode
= insns
[0].opcode
;
1550 /* merge in addend */
1551 insns
[1].opcode
|= addend
& 0xffff;
1552 insns
[0].opcode
|= ((addend
>> 16)
1553 + (addend
& 0x8000 ? 1 : 0));
1555 ecoff_set_gp_prolog_size (0);
1564 case 'b': /* setgp */
1565 switch (OUTPUT_FLAVOR
)
1567 case bfd_target_aout_flavour
:
1568 /* generate "zap %r,0xf,$gp" to take high 32 bits */
1569 opcode
|= 0x48001600 /* zap ?,#,?*/
1570 | (0xf << SN
) | (base_register
);
1577 case 'c': /* jsr $r,foo becomes
1580 Register 27, t12, is used by convention
1583 struct alpha_it
*jsr
;
1585 struct reloc_data
*r
;
1587 /* We still have to parse the function name */
1590 getExpression (s
, &insns
[0]);
1591 etmp
= insns
[0].reloc
[0].exp
;
1593 num_gen
= load_expression (PV
, &insns
[0]);
1596 jsr
= &insns
[num_gen
++];
1597 jsr
->opcode
= (0x68004000 /* jsr */
1603 /* LITUSE wasn't emitted yet */
1604 jsr
->reloc
[0].code
= BFD_RELOC_ALPHA_LITUSE
;
1605 jsr
->reloc
[0].exp
= lituse_jsr
;
1612 r
->code
= BFD_RELOC_ALPHA_HINT
;
1614 opcode
= insns
[0].opcode
;
1619 /* Sub-word loads and stores. We load the address into
1620 $at, which might involve using the `P' parameter
1621 processing too, then emit a sequence to get the job
1622 done, using unaligned memory accesses and byte
1623 manipulation, with t9 and t10 as temporaries. */
1625 /* Characteristics of access. */
1626 int is_load
, is_unsigned
= 0, is_unaligned
= 0;
1627 int mode_size
, mode
;
1628 /* Register operand. */
1630 /* Addend for loads and stores. */
1632 /* Which register do we use for the address? */
1636 /* Pick apart name and set flags. */
1637 char *s
= pattern
->name
;
1645 if (s
[0] == 'l' && s
[1] == 'd')
1647 else if (s
[0] == 's' && s
[1] == 't')
1650 as_fatal ("unrecognized sub-word access insn `%s'",
1655 if (mode
== 'b') mode_size
= 1;
1656 else if (mode
== 'w') mode_size
= 2;
1657 else if (mode
== 'l') mode_size
= 4;
1658 else if (mode
== 'q') mode_size
= 8;
1669 /* Longwords are always kept sign-extended. */
1670 if (mode
== 'l' && is_unsigned
)
1672 /* There's no special unaligned byte handling. */
1673 if (mode
== 'b' && is_unaligned
)
1675 /* Stores don't care about signedness. */
1676 if (!is_load
&& is_unsigned
)
1680 if (args
[-2] == 'P')
1689 r1 -> (opcode >> SA) & 31
1690 num -> insns->reloc[0].*
1692 We want to emit "lda at,num(r2)", since these
1693 operations require the use of a single register
1694 with the starting address of the memory operand
1697 We could probably get away without doing this
1698 (and use r2 below, with the addend for the
1699 actual reads and writes) in cases where the
1700 addend is known to be a multiple of 8. */
1702 int r1
= (opcode
>> SA
) & 31;
1704 if (insns
[0].reloc
[0].code
== BFD_RELOC_NONE
)
1706 else if (insns
[0].reloc
[0].code
== BFD_RELOC_16
)
1708 if (insns
[0].reloc
[0].exp
.X_op
!= O_constant
)
1710 addend
= insns
[0].reloc
[0].exp
.X_add_number
;
1715 if (addend
+ mode_size
- 1 < 0x7fff
1716 && (addend
% 8) == 0
1717 && (r2
< T9
|| r2
> T12
))
1724 /* Let later relocation processing deal
1725 with the addend field. */
1726 insns
[num_gen
-1].opcode
= (0x20000000 /* lda */
1735 /* Because the emit_* routines append directly to
1736 the current frag, we now need to flush any
1740 for (i
= 0; i
< num_gen
; i
++)
1741 emit_insn (&insns
[i
]);
1750 reg2
= T9
, reg3
= T10
;
1754 emit_load_unal (addr
, addend
, T9
);
1756 emit_load_unal (addr
, addend
+ mode_size
- 1, T10
);
1757 emit_extract_r (T9
, addr
, reg2
, mode
, 'l');
1760 emit_extract_r (T10
, addr
, reg3
, mode
, 'h');
1761 emit_bis_r (T9
, T10
, reg
);
1764 emit_sign_extend (reg
, mode_size
* 8);
1768 /* The second word gets processed first
1769 because if the address does turn out to be
1770 aligned, the processing for the second word
1771 will be pushing around all-zeros, and the
1772 entire value will be handled as the `first'
1773 word. So we want to store the `first' word
1775 /* Pair these up so that the memory loads get
1776 separated from each other, as well as being
1777 well in advance of the uses of the values
1781 emit_load_unal (addr
, addend
+ mode_size
- 1, T11
);
1782 emit_insert_r (reg
, addr
, T12
, mode
, 'h');
1784 emit_load_unal (addr
, addend
, T9
);
1785 emit_insert_r (reg
, addr
, T10
, mode
, 'l');
1787 emit_mask_r (T12
, addr
, T12
, mode
, 'h');
1788 emit_mask_r (T10
, addr
, T10
, mode
, 'l');
1790 emit_bis_r (T11
, T12
, T11
);
1791 emit_bis_r (T9
, T10
, T9
);
1793 emit_store_unal (addr
, addend
+ mode_size
- 1, T11
);
1794 emit_store_unal (addr
, addend
, T9
);
1799 /* DIVISION and MODULUS. Yech.
1800 Convert OP x,y,result
1806 with appropriate optimizations if t10,t11,t12
1807 are the registers specified by the compiler.
1808 We are missing an obvious optimization
1809 opportunity here; if the ldq generated by the
1810 jsr assembly requires a cycle or two to make
1811 the value available, initiating it before one
1812 or two of the mov instructions would result in
1813 faster execution. */
1814 case '0': /* reml */
1815 case '1': /* divl */
1816 case '2': /* remq */
1817 case '3': /* divq */
1818 case '4': /* remlu */
1819 case '5': /* divlu */
1820 case '6': /* remqu */
1821 case '7': /* divqu */
1823 static char func
[8][6] = {
1824 "reml", "divl", "remq", "divq",
1825 "remlu", "divlu", "remqu", "divqu"
1830 /* All regs parsed, in opcode */
1832 /* Do the expansions, one instr at a time */
1834 reg
= (opcode
>> SA
) & 31;
1838 sprintf (expansion
, "mov $%d,$%d", reg
, T10
);
1839 md_assemble (expansion
);
1841 reg
= (opcode
>> SB
) & 31;
1843 /* we already overwrote it! */
1845 else if (reg
!= T11
)
1848 sprintf (expansion
, "mov $%d,$%d", reg
, T11
);
1849 md_assemble (expansion
);
1851 sprintf (expansion
, "lda $%d,__%s", PV
, func
[*args
- '0']);
1852 md_assemble (expansion
);
1853 sprintf (expansion
, "jsr $%d,($%d),__%s", T9
, PV
,
1855 md_assemble (expansion
);
1857 if (!first_32bit_quadrant
)
1862 md_assemble (expansion
);
1865 sprintf (expansion
, "ldgp $%d,0($%d)",
1867 md_assemble (expansion
);
1869 /* Use insns[0] to get at the result */
1870 if ((reg
= (opcode
& 31)) != PV
)
1871 opcode
= (0x47e00400 /* or zero,zero,zero */
1873 | reg
/* Rc */ ); /* pv->z */
1889 /* Args don't match. */
1890 if (&pattern
[1] - alpha_opcodes
< NUMOPCODES
1891 && !strcmp (pattern
->name
, pattern
[1].name
))
1899 as_warn ("Illegal operands");
1905 /* Args match, see if a float instructions and -nofloats */
1906 if (nofloats
&& pattern
->isa_float
)
1912 insns
[0].opcode
= opcode
;
1916 /* Turn a string in input_line_pointer into a floating point constant
1917 of type type, and store the appropriate bytes in *litP. The number
1918 of LITTLENUMS emitted is stored in *sizeP. An error message is
1919 returned, or NULL on OK. */
1921 /* Equal to MAX_PRECISION in atof-ieee.c */
1922 #define MAX_LITTLENUMS 6
1925 md_atof (type
, litP
, sizeP
)
1931 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1932 LITTLENUM_TYPE
*wordP
;
1934 char *atof_ieee (), *vax_md_atof ();
1940 /* VAX md_atof doesn't like "G" for some reason. */
1944 return vax_md_atof (type
, litP
, sizeP
);
1967 return "Bad call to MD_ATOF()";
1969 t
= atof_ieee (input_line_pointer
, type
, words
);
1971 input_line_pointer
= t
;
1972 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1974 for (wordP
= words
+ prec
- 1; prec
--;)
1976 md_number_to_chars (litP
, (long) (*wordP
--), sizeof (LITTLENUM_TYPE
));
1977 litP
+= sizeof (LITTLENUM_TYPE
);
1984 md_bignum_to_chars (buf
, bignum
, nchars
)
1986 LITTLENUM_TYPE
*bignum
;
1991 LITTLENUM_TYPE work
= *bignum
++;
1992 int nb
= CHARS_PER_LITTLENUM
;
1996 *buf
++ = work
& ((1 << BITS_PER_CHAR
) - 1);
1999 work
>>= BITS_PER_CHAR
;
2005 CONST
char *md_shortopts
= "Fm:";
2006 struct option md_longopts
[] = {
2007 #define OPTION_32ADDR (OPTION_MD_BASE)
2008 {"32addr", no_argument
, NULL
, OPTION_32ADDR
},
2009 {NULL
, no_argument
, NULL
, 0}
2011 size_t md_longopts_size
= sizeof(md_longopts
);
2014 md_parse_option (c
, arg
)
2032 if (!strcmp (arg
, "21064"))
2034 else if (!strcmp (arg
, "21066"))
2036 else if (!strcmp (arg
, "21164"))
2040 as_bad ("invalid architecture %s", arg
);
2044 if (machine
!= 0 && machine
!= mach
)
2046 as_warn ("machine type %lu already chosen, overriding with %lu",
2061 md_show_usage (stream
)
2066 -32addr treat addresses as 32-bit values\n\
2067 -F lack floating point instructions support\n\
2068 -m21064 | -m21066 | -m21164\n\
2069 specify variant of Alpha architecture\n\
2076 /* XXXX Align to cache linesize XXXXX */
2083 /* Takes ".proc name,nargs" */
2084 name
= input_line_pointer
;
2085 c
= get_symbol_end ();
2086 p
= input_line_pointer
;
2087 symbolP
= symbol_find_or_make (name
);
2090 if (*input_line_pointer
!= ',')
2093 as_warn ("Expected comma after name \"%s\"", name
);
2096 ignore_rest_of_line ();
2100 input_line_pointer
++;
2101 temp
= get_absolute_expression ();
2103 /* symbolP->sy_other = (signed char) temp; */
2104 as_warn ("unhandled: .proc %s,%d", name
, temp
);
2105 demand_empty_rest_of_line ();
2112 char *name
= input_line_pointer
, ch
, *s
;
2115 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2116 input_line_pointer
++;
2117 ch
= *input_line_pointer
;
2118 *input_line_pointer
= '\0';
2121 if (s
[0] == 'n' && s
[1] == 'o')
2126 if (!strcmp ("reorder", s
))
2128 else if (!strcmp ("at", s
))
2130 else if (!strcmp ("macro", s
))
2133 as_warn ("Tried to set unrecognized symbol: %s", name
);
2134 *input_line_pointer
= ch
;
2135 demand_empty_rest_of_line ();
2138 /* @@ Is this right?? */
2140 md_pcrel_from (fixP
)
2143 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2144 switch (fixP
->fx_r_type
)
2146 case BFD_RELOC_ALPHA_GPDISP_HI16
:
2147 case BFD_RELOC_ALPHA_GPDISP_LO16
:
2150 return fixP
->fx_size
+ addr
;
2155 alpha_do_align (n
, fill
)
2160 && (now_seg
== text_section
2161 || !strcmp (now_seg
->name
, ".init")
2162 || !strcmp (now_seg
->name
, ".fini")))
2164 static const unsigned char nop_pattern
[] = { 0x1f, 0x04, 0xff, 0x47 };
2165 frag_align_pattern (n
, nop_pattern
, sizeof (nop_pattern
));
2172 md_apply_fix (fixP
, valueP
)
2179 char *p
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2183 switch (fixP
->fx_r_type
)
2185 /* The GPDISP relocations are processed internally with a symbol
2186 referring to the current function; we need to drop in a value
2187 which, when added to the address of the start of the function,
2188 gives the desired GP. */
2189 case BFD_RELOC_ALPHA_GPDISP_HI16
:
2190 case BFD_RELOC_ALPHA_GPDISP_LO16
:
2192 if (fixP
->fx_r_type
== BFD_RELOC_ALPHA_GPDISP_HI16
)
2194 assert (fixP
->fx_next
->fx_r_type
== BFD_RELOC_ALPHA_GPDISP_LO16
);
2197 fprintf_vma (stdout
, addend
);
2200 if (addend
& 0x8000)
2203 fixP
->fx_offset
= 4; /* @@ Compute this using fx_next. */
2209 fprintf_vma (stdout
, addend
);
2213 fixP
->fx_offset
= 0;
2215 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
2217 fixP
->fx_addsy
= section_symbol (absolute_section
);
2218 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2222 /* Write 8 bits, shifted left 13 bit positions. */
2226 *p
|= (value
<< 5) & 0xe0;
2235 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2236 "overflow in type-%d reloc", (int) fixP
->fx_r_type
);
2246 /* Don't want overflow checking. */
2249 if (fixP
->fx_pcrel
== 0
2250 && fixP
->fx_addsy
== 0)
2252 md_number_to_chars (p
, value
, size
);
2253 /* @@ Overflow checks?? */
2259 if (fixP
->fx_addsy
!= 0
2260 && fixP
->fx_addsy
->bsym
->section
!= absolute_section
)
2261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2262 "PALcode instructions require immediate constant function code");
2263 else if (value
>> 26 != 0)
2264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2265 "overflow in 26-bit PALcode function field");
2266 *p
++ = value
& 0xff;
2268 *p
++ = value
& 0xff;
2270 *p
++ = value
& 0xff;
2281 if (fixP
->fx_addsy
!= 0
2282 && fixP
->fx_addsy
->bsym
->section
!= absolute_section
)
2283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2284 "ret/jsr_coroutine requires constant in displacement field");
2285 else if (value
>> 14 != 0)
2286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2287 "overflow in 14-bit operand field of ret or jsr_coroutine");
2288 *p
++ = value
& 0xff;
2290 *p
= (*p
& 0xc0) | (value
& 0x3f);
2293 case BFD_RELOC_23_PCREL_S2
:
2294 /* Write 21 bits only. */
2296 *p
++ = value
& 0xff;
2298 *p
++ = value
& 0xff;
2301 *p
|= (value
& 0x1f);
2304 case BFD_RELOC_ALPHA_LITERAL
:
2305 case BFD_RELOC_ALPHA_LITUSE
:
2308 case BFD_RELOC_GPREL32
:
2309 assert (fixP
->fx_subsy
== gp
);
2310 value
= - alpha_gp_value
; /* huh? this works... */
2312 md_number_to_chars (p
, value
, 4);
2315 case BFD_RELOC_ALPHA_HINT
:
2316 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
2324 as_fatal ("unknown relocation type %d?", fixP
->fx_r_type
);
2328 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
2330 printf ("type %d reloc done?\n", fixP
->fx_r_type
);
2340 alpha_frob_ecoff_data ()
2343 /* $zero and $f31 are read-only */
2344 alpha_gprmask
&= ~1;
2345 alpha_fprmask
&= ~1;
2348 /* The Alpha has support for some VAX floating point types, as well as for
2349 IEEE floating point. We consider IEEE to be the primary floating point
2350 format, and sneak in the VAX floating point support here. */
2351 #define md_atof vax_md_atof
2352 #include "config/atof-vax.c"