1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
49 (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 /* Enum used to enumerate the relaxable ins operands. */
59 REGISTER_S
, /* Register for short instruction(s). */
60 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
61 REGISTER_DUP
, /* Duplication of previous operand of type register. */
95 #define regno(x) ((x) & 0x3F)
96 #define is_ir_num(x) (((x) & ~0x3F) == 0)
97 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98 #define is_spfp_p(op) (((sc) == SPX))
99 #define is_dpfp_p(op) (((sc) == DPX))
100 #define is_fpuda_p(op) (((sc) == DPA))
101 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
102 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
104 /* Generic assembler global variables which must be defined by all
107 /* Characters which always start a comment. */
108 const char comment_chars
[] = "#;";
110 /* Characters which start a comment at the beginning of a line. */
111 const char line_comment_chars
[] = "#";
113 /* Characters which may be used to separate multiple commands on a
115 const char line_separator_chars
[] = "`";
117 /* Characters which are used to indicate an exponent in a floating
119 const char EXP_CHARS
[] = "eE";
121 /* Chars that mean this number is a floating point constant
122 As in 0f12.456 or 0d1.2345e12. */
123 const char FLT_CHARS
[] = "rRsSfFdD";
126 extern int target_big_endian
;
127 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
128 static int byte_order
= DEFAULT_BYTE_ORDER
;
130 /* Arc extension section. */
131 static segT arcext_section
;
133 /* By default relaxation is disabled. */
134 static int relaxation_state
= 0;
136 extern int arc_get_mach (char *);
138 /* Forward declarations. */
139 static void arc_lcomm (int);
140 static void arc_option (int);
141 static void arc_extra_reloc (int);
142 static void arc_extinsn (int);
144 const pseudo_typeS md_pseudo_table
[] =
146 /* Make sure that .word is 32 bits. */
149 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
150 { "lcomm", arc_lcomm
, 0 },
151 { "lcommon", arc_lcomm
, 0 },
152 { "cpu", arc_option
, 0 },
154 { "extinstruction", arc_extinsn
, 0 },
156 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
157 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
162 const char *md_shortopts
= "";
166 OPTION_EB
= OPTION_MD_BASE
,
179 /* The following options are deprecated and provided here only for
180 compatibility reasons. */
206 struct option md_longopts
[] =
208 { "EB", no_argument
, NULL
, OPTION_EB
},
209 { "EL", no_argument
, NULL
, OPTION_EL
},
210 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
211 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
212 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
213 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
214 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
215 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
216 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
217 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
218 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
219 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
221 /* The following options are deprecated and provided here only for
222 compatibility reasons. */
223 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
224 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
225 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
226 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
227 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
228 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
229 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
230 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
231 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
232 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
233 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
234 { "mea", no_argument
, NULL
, OPTION_EA
},
235 { "mEA", no_argument
, NULL
, OPTION_EA
},
236 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
237 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
238 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
239 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
240 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
241 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
242 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
243 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
244 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
245 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
246 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
247 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
248 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
249 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
250 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
251 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
252 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
253 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
254 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
255 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
256 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
257 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
258 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
259 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
260 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
261 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
263 { NULL
, no_argument
, NULL
, 0 }
266 size_t md_longopts_size
= sizeof (md_longopts
);
268 /* Local data and data types. */
270 /* Used since new relocation types are introduced in this
271 file (DUMMY_RELOC_LITUSE_*). */
272 typedef int extended_bfd_reloc_code_real_type
;
278 extended_bfd_reloc_code_real_type reloc
;
280 /* index into arc_operands. */
281 unsigned int opindex
;
283 /* PC-relative, used by internals fixups. */
286 /* TRUE if this fixup is for LIMM operand. */
294 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
296 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
298 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
300 bfd_boolean relax
; /* Boolean value: TRUE if needs
304 /* Structure to hold any last two instructions. */
305 static struct arc_last_insn
307 /* Saved instruction opcode. */
308 const struct arc_opcode
*opcode
;
310 /* Boolean value: TRUE if current insn is short. */
311 bfd_boolean has_limm
;
313 /* Boolean value: TRUE if current insn has delay slot. */
314 bfd_boolean has_delay_slot
;
317 /* Extension instruction suffix classes. */
325 static const attributes_t suffixclass
[] =
327 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
328 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
329 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
332 /* Extension instruction syntax classes. */
333 static const attributes_t syntaxclass
[] =
335 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
336 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
}
339 /* Extension instruction syntax classes modifiers. */
340 static const attributes_t syntaxclassmod
[] =
342 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
343 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
346 /* Structure to hold an entry in ARC_OPCODE_HASH. */
347 struct arc_opcode_hash_entry
349 /* The number of pointers in the OPCODE list. */
352 /* Points to a list of opcode pointers. */
353 const struct arc_opcode
**opcode
;
356 /* Structure used for iterating through an arc_opcode_hash_entry. */
357 struct arc_opcode_hash_entry_iterator
359 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
362 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
363 returned by this iterator. */
364 const struct arc_opcode
*opcode
;
367 /* Forward declaration. */
368 static void assemble_insn
369 (const struct arc_opcode
*, const expressionS
*, int,
370 const struct arc_flags
*, int, struct arc_insn
*);
372 /* The cpu for which we are generating code. */
373 static unsigned arc_target
;
374 static const char *arc_target_name
;
375 static unsigned arc_features
;
377 /* The default architecture. */
378 static int arc_mach_type
;
380 /* Non-zero if the cpu type has been explicitly specified. */
381 static int mach_type_specified_p
= 0;
383 /* The hash table of instruction opcodes. */
384 static struct hash_control
*arc_opcode_hash
;
386 /* The hash table of register symbols. */
387 static struct hash_control
*arc_reg_hash
;
389 /* A table of CPU names and opcode sets. */
390 static const struct cpu_type
400 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
401 E_ARC_MACH_ARC600
, 0x00},
402 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
403 E_ARC_MACH_ARC700
, 0x00},
404 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
405 E_ARC_MACH_NPS400
, 0x00},
406 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
407 EF_ARC_CPU_ARCV2EM
, ARC_CD
},
408 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
409 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
413 /* Used by the arc_reloc_op table. Order is important. */
414 #define O_gotoff O_md1 /* @gotoff relocation. */
415 #define O_gotpc O_md2 /* @gotpc relocation. */
416 #define O_plt O_md3 /* @plt relocation. */
417 #define O_sda O_md4 /* @sda relocation. */
418 #define O_pcl O_md5 /* @pcl relocation. */
419 #define O_tlsgd O_md6 /* @tlsgd relocation. */
420 #define O_tlsie O_md7 /* @tlsie relocation. */
421 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
422 #define O_tpoff O_md9 /* @tpoff relocation. */
423 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
424 #define O_dtpoff O_md11 /* @dtpoff relocation. */
425 #define O_last O_dtpoff
427 /* Used to define a bracket as operand in tokens. */
428 #define O_bracket O_md32
430 /* Dummy relocation, to be sorted out. */
431 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
433 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
435 /* A table to map the spelling of a relocation operand into an appropriate
436 bfd_reloc_code_real_type type. The table is assumed to be ordered such
437 that op-O_literal indexes into it. */
438 #define ARC_RELOC_TABLE(op) \
439 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
441 : (int) (op) - (int) O_gotoff) ])
443 #define DEF(NAME, RELOC, REQ) \
444 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
446 static const struct arc_reloc_op_tag
448 /* String to lookup. */
450 /* Size of the string. */
452 /* Which operator to use. */
454 extended_bfd_reloc_code_real_type reloc
;
455 /* Allows complex relocation expression like identifier@reloc +
457 unsigned int complex_expr
: 1;
461 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
462 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
463 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
464 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
465 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
466 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
467 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
468 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
469 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
470 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
471 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
474 static const int arc_num_reloc_op
475 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
477 /* Structure for relaxable instruction that have to be swapped with a
478 smaller alternative instruction. */
479 struct arc_relaxable_ins
481 /* Mnemonic that should be checked. */
482 const char *mnemonic_r
;
484 /* Operands that should be checked.
485 Indexes of operands from operand array. */
486 enum rlx_operand_type operands
[6];
488 /* Flags that should be checked. */
489 unsigned flag_classes
[5];
491 /* Mnemonic (smaller) alternative to be used later for relaxation. */
492 const char *mnemonic_alt
;
494 /* Index of operand that generic relaxation has to check. */
497 /* Base subtype index used. */
498 enum arc_rlx_types subtype
;
501 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
502 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
503 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
507 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
508 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
509 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
514 /* ARC relaxation table. */
515 const relax_typeS md_relax_table
[] =
522 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
523 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
527 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
528 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
533 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
534 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
535 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
537 /* LD_S a, [b, u7] ->
538 LD<zz><.x><.aa><.di> a, [b, s9] ->
539 LD<zz><.x><.aa><.di> a, [b, limm] */
540 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
541 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
542 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
547 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
548 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
549 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
553 SUB<.f> a, b, limm. */
554 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
555 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
556 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
558 /* MPY<.f> a, b, u6 ->
559 MPY<.f> a, b, limm. */
560 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
561 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
563 /* MOV<.f><.cc> b, u6 ->
564 MOV<.f><.cc> b, limm. */
565 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
566 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
568 /* ADD<.f><.cc> b, b, u6 ->
569 ADD<.f><.cc> b, b, limm. */
570 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
571 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
574 /* Order of this table's entries matters! */
575 const struct arc_relaxable_ins arc_relaxable_insns
[] =
577 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
578 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
579 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
580 2, ARC_RLX_ADD_RRU6
},
581 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
583 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
585 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
586 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
587 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
588 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
589 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
590 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
591 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
592 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
594 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
596 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
600 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
602 /* Flags to set in the elf header. */
603 static flagword arc_eflag
= 0x00;
605 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
606 symbolS
* GOT_symbol
= 0;
608 /* Set to TRUE when we assemble instructions. */
609 static bfd_boolean assembling_insn
= FALSE
;
611 /* Functions implementation. */
613 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
614 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
615 are no matching entries in ARC_OPCODE_HASH. */
617 static const struct arc_opcode_hash_entry
*
618 arc_find_opcode (const char *name
)
620 const struct arc_opcode_hash_entry
*entry
;
622 entry
= hash_find (arc_opcode_hash
, name
);
626 /* Initialise the iterator ITER. */
629 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
635 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
636 calls to this function. Return NULL when all ARC_OPCODE entries have
639 static const struct arc_opcode
*
640 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
641 struct arc_opcode_hash_entry_iterator
*iter
)
643 if (iter
->opcode
== NULL
&& iter
->index
== 0)
645 gas_assert (entry
->count
> 0);
646 iter
->opcode
= entry
->opcode
[iter
->index
];
648 else if (iter
->opcode
!= NULL
)
650 const char *old_name
= iter
->opcode
->name
;
653 if (iter
->opcode
->name
654 && (strcmp (old_name
, iter
->opcode
->name
) != 0))
657 if (iter
->index
== entry
->count
)
660 iter
->opcode
= entry
->opcode
[iter
->index
];
667 /* Insert an opcode into opcode hash structure. */
670 arc_insert_opcode (const struct arc_opcode
*opcode
)
672 const char *name
, *retval
;
673 struct arc_opcode_hash_entry
*entry
;
676 entry
= hash_find (arc_opcode_hash
, name
);
679 entry
= xmalloc (sizeof (*entry
));
681 entry
->opcode
= NULL
;
683 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
685 as_fatal (_("internal error: can't hash opcode '%s': %s"),
689 entry
->opcode
= xrealloc (entry
->opcode
,
690 sizeof (const struct arc_opcode
*)
691 * (entry
->count
+ 1));
693 if (entry
->opcode
== NULL
)
694 as_fatal (_("Virtual memory exhausted"));
696 entry
->opcode
[entry
->count
] = opcode
;
701 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
702 is encoded as 'middle-endian' for a little-endian target. FIXME!
703 this function is used for regular 4 byte instructions as well. */
706 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
710 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
711 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
715 md_number_to_chars (buf
, val
, n
);
719 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
720 the relevant static global variables. */
723 arc_select_cpu (const char *arg
)
728 for (i
= 0; cpu_types
[i
].name
; ++i
)
730 if (!strcasecmp (cpu_types
[i
].name
, arg
))
732 arc_target
= cpu_types
[i
].flags
;
733 arc_target_name
= cpu_types
[i
].name
;
734 arc_features
= cpu_types
[i
].features
;
735 arc_mach_type
= cpu_types
[i
].mach
;
736 cpu_flags
= cpu_types
[i
].eflags
;
741 if (!cpu_types
[i
].name
)
742 as_fatal (_("unknown architecture: %s\n"), arg
);
743 gas_assert (cpu_flags
!= 0);
744 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
747 /* Here ends all the ARCompact extension instruction assembling
751 arc_extra_reloc (int r_type
)
754 symbolS
*sym
, *lab
= NULL
;
756 if (*input_line_pointer
== '@')
757 input_line_pointer
++;
758 c
= get_symbol_name (&sym_name
);
759 sym
= symbol_find_or_make (sym_name
);
760 restore_line_pointer (c
);
761 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
763 ++input_line_pointer
;
765 c
= get_symbol_name (&lab_name
);
766 lab
= symbol_find_or_make (lab_name
);
767 restore_line_pointer (c
);
770 /* These relocations exist as a mechanism for the compiler to tell the
771 linker how to patch the code if the tls model is optimised. However,
772 the relocation itself does not require any space within the assembler
773 fragment, and so we pass a size of 0.
775 The lines that generate these relocations look like this:
777 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
779 The '.tls_gd_ld @.tdata' is processed first and generates the
780 additional relocation, while the 'bl __tls_get_addr@plt' is processed
781 second and generates the additional branch.
783 It is possible that the additional relocation generated by the
784 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
785 while the 'bl __tls_get_addr@plt' will be generated as the first thing
786 in the next fragment. This will be fine; both relocations will still
787 appear to be at the same address in the generated object file.
788 However, this only works as the additional relocation is generated
789 with size of 0 bytes. */
791 = fix_new (frag_now
, /* Which frag? */
792 frag_now_fix (), /* Where in that frag? */
793 0, /* size: 1, 2, or 4 usually. */
794 sym
, /* X_add_symbol. */
795 0, /* X_add_number. */
796 FALSE
, /* TRUE if PC-relative relocation. */
797 r_type
/* Relocation type. */);
798 fixP
->fx_subsy
= lab
;
802 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
803 symbolS
*symbolP
, addressT size
)
808 if (*input_line_pointer
== ',')
810 align
= parse_align (1);
812 if (align
== (addressT
) -1)
827 bss_alloc (symbolP
, size
, align
);
828 S_CLEAR_EXTERNAL (symbolP
);
834 arc_lcomm (int ignore
)
836 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
839 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
842 /* Select the cpu we're assembling for. */
845 arc_option (int ignore ATTRIBUTE_UNUSED
)
851 c
= get_symbol_name (&cpu
);
852 mach
= arc_get_mach (cpu
);
857 if (!mach_type_specified_p
)
859 if ((!strcmp ("ARC600", cpu
))
860 || (!strcmp ("ARC601", cpu
))
861 || (!strcmp ("A6", cpu
)))
863 md_parse_option (OPTION_MCPU
, "arc600");
865 else if ((!strcmp ("ARC700", cpu
))
866 || (!strcmp ("A7", cpu
)))
868 md_parse_option (OPTION_MCPU
, "arc700");
870 else if (!strcmp ("EM", cpu
))
872 md_parse_option (OPTION_MCPU
, "arcem");
874 else if (!strcmp ("HS", cpu
))
876 md_parse_option (OPTION_MCPU
, "archs");
879 as_fatal (_("could not find the architecture"));
881 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
882 as_fatal (_("could not set architecture and machine"));
885 if (arc_mach_type
!= mach
)
886 as_warn (_("Command-line value overrides \".cpu\" directive"));
888 restore_line_pointer (c
);
889 demand_empty_rest_of_line ();
893 restore_line_pointer (c
);
894 as_bad (_("invalid identifier for \".cpu\""));
895 ignore_rest_of_line ();
898 /* Smartly print an expression. */
901 debug_exp (expressionS
*t
)
903 const char *name ATTRIBUTE_UNUSED
;
904 const char *namemd ATTRIBUTE_UNUSED
;
906 pr_debug ("debug_exp: ");
910 default: name
= "unknown"; break;
911 case O_illegal
: name
= "O_illegal"; break;
912 case O_absent
: name
= "O_absent"; break;
913 case O_constant
: name
= "O_constant"; break;
914 case O_symbol
: name
= "O_symbol"; break;
915 case O_symbol_rva
: name
= "O_symbol_rva"; break;
916 case O_register
: name
= "O_register"; break;
917 case O_big
: name
= "O_big"; break;
918 case O_uminus
: name
= "O_uminus"; break;
919 case O_bit_not
: name
= "O_bit_not"; break;
920 case O_logical_not
: name
= "O_logical_not"; break;
921 case O_multiply
: name
= "O_multiply"; break;
922 case O_divide
: name
= "O_divide"; break;
923 case O_modulus
: name
= "O_modulus"; break;
924 case O_left_shift
: name
= "O_left_shift"; break;
925 case O_right_shift
: name
= "O_right_shift"; break;
926 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
927 case O_bit_or_not
: name
= "O_bit_or_not"; break;
928 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
929 case O_bit_and
: name
= "O_bit_and"; break;
930 case O_add
: name
= "O_add"; break;
931 case O_subtract
: name
= "O_subtract"; break;
932 case O_eq
: name
= "O_eq"; break;
933 case O_ne
: name
= "O_ne"; break;
934 case O_lt
: name
= "O_lt"; break;
935 case O_le
: name
= "O_le"; break;
936 case O_ge
: name
= "O_ge"; break;
937 case O_gt
: name
= "O_gt"; break;
938 case O_logical_and
: name
= "O_logical_and"; break;
939 case O_logical_or
: name
= "O_logical_or"; break;
940 case O_index
: name
= "O_index"; break;
941 case O_bracket
: name
= "O_bracket"; break;
946 default: namemd
= "unknown"; break;
947 case O_gotoff
: namemd
= "O_gotoff"; break;
948 case O_gotpc
: namemd
= "O_gotpc"; break;
949 case O_plt
: namemd
= "O_plt"; break;
950 case O_sda
: namemd
= "O_sda"; break;
951 case O_pcl
: namemd
= "O_pcl"; break;
952 case O_tlsgd
: namemd
= "O_tlsgd"; break;
953 case O_tlsie
: namemd
= "O_tlsie"; break;
954 case O_tpoff9
: namemd
= "O_tpoff9"; break;
955 case O_tpoff
: namemd
= "O_tpoff"; break;
956 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
957 case O_dtpoff
: namemd
= "O_dtpoff"; break;
960 pr_debug ("%s (%s, %s, %d, %s)", name
,
961 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
962 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
963 (int) t
->X_add_number
,
964 (t
->X_md
) ? namemd
: "--");
969 /* Parse the arguments to an opcode. */
972 tokenize_arguments (char *str
,
976 char *old_input_line_pointer
;
977 bfd_boolean saw_comma
= FALSE
;
978 bfd_boolean saw_arg
= FALSE
;
983 const struct arc_reloc_op_tag
*r
;
987 memset (tok
, 0, sizeof (*tok
) * ntok
);
989 /* Save and restore input_line_pointer around this function. */
990 old_input_line_pointer
= input_line_pointer
;
991 input_line_pointer
= str
;
993 while (*input_line_pointer
)
996 switch (*input_line_pointer
)
1002 input_line_pointer
++;
1003 if (saw_comma
|| !saw_arg
)
1010 ++input_line_pointer
;
1014 tok
->X_op
= O_bracket
;
1021 input_line_pointer
++;
1025 tok
->X_op
= O_bracket
;
1031 /* We have labels, function names and relocations, all
1032 starting with @ symbol. Sort them out. */
1033 if (saw_arg
&& !saw_comma
)
1037 tok
->X_op
= O_symbol
;
1038 tok
->X_md
= O_absent
;
1040 if (*input_line_pointer
!= '@')
1041 goto normalsymbol
; /* This is not a relocation. */
1045 /* A relocation opernad has the following form
1046 @identifier@relocation_type. The identifier is already
1048 if (tok
->X_op
!= O_symbol
)
1050 as_bad (_("No valid label relocation operand"));
1054 /* Parse @relocation_type. */
1055 input_line_pointer
++;
1056 c
= get_symbol_name (&reloc_name
);
1057 len
= input_line_pointer
- reloc_name
;
1060 as_bad (_("No relocation operand"));
1064 /* Go through known relocation and try to find a match. */
1065 r
= &arc_reloc_op
[0];
1066 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1067 if (len
== r
->length
1068 && memcmp (reloc_name
, r
->name
, len
) == 0)
1072 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1076 *input_line_pointer
= c
;
1077 SKIP_WHITESPACE_AFTER_NAME ();
1078 /* Extra check for TLS: base. */
1079 if (*input_line_pointer
== '@')
1082 if (tok
->X_op_symbol
!= NULL
1083 || tok
->X_op
!= O_symbol
)
1085 as_bad (_("Unable to parse TLS base: %s"),
1086 input_line_pointer
);
1089 input_line_pointer
++;
1091 c
= get_symbol_name (&sym_name
);
1092 base
= symbol_find_or_make (sym_name
);
1093 tok
->X_op
= O_subtract
;
1094 tok
->X_op_symbol
= base
;
1095 restore_line_pointer (c
);
1096 tmpE
.X_add_number
= 0;
1098 else if ((*input_line_pointer
!= '+')
1099 && (*input_line_pointer
!= '-'))
1101 tmpE
.X_add_number
= 0;
1105 /* Parse the constant of a complex relocation expression
1106 like @identifier@reloc +/- const. */
1107 if (! r
->complex_expr
)
1109 as_bad (_("@%s is not a complex relocation."), r
->name
);
1113 if (tmpE
.X_op
!= O_constant
)
1115 as_bad (_("Bad expression: @%s + %s."),
1116 r
->name
, input_line_pointer
);
1122 tok
->X_add_number
= tmpE
.X_add_number
;
1133 /* Can be a register. */
1134 ++input_line_pointer
;
1138 if (saw_arg
&& !saw_comma
)
1141 tok
->X_op
= O_absent
;
1142 tok
->X_md
= O_absent
;
1145 /* Legacy: There are cases when we have
1146 identifier@relocation_type, if it is the case parse the
1147 relocation type as well. */
1148 if (*input_line_pointer
== '@')
1154 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1166 if (saw_comma
|| brk_lvl
)
1168 input_line_pointer
= old_input_line_pointer
;
1174 as_bad (_("Brackets in operand field incorrect"));
1176 as_bad (_("extra comma"));
1178 as_bad (_("missing argument"));
1180 as_bad (_("missing comma or colon"));
1181 input_line_pointer
= old_input_line_pointer
;
1185 /* Parse the flags to a structure. */
1188 tokenize_flags (const char *str
,
1189 struct arc_flags flags
[],
1192 char *old_input_line_pointer
;
1193 bfd_boolean saw_flg
= FALSE
;
1194 bfd_boolean saw_dot
= FALSE
;
1198 memset (flags
, 0, sizeof (*flags
) * nflg
);
1200 /* Save and restore input_line_pointer around this function. */
1201 old_input_line_pointer
= input_line_pointer
;
1202 input_line_pointer
= (char *) str
;
1204 while (*input_line_pointer
)
1206 switch (*input_line_pointer
)
1213 input_line_pointer
++;
1221 if (saw_flg
&& !saw_dot
)
1224 if (num_flags
>= nflg
)
1227 flgnamelen
= strspn (input_line_pointer
,
1228 "abcdefghijklmnopqrstuvwxyz0123456789");
1229 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1232 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1234 input_line_pointer
+= flgnamelen
;
1244 input_line_pointer
= old_input_line_pointer
;
1249 as_bad (_("extra dot"));
1251 as_bad (_("unrecognized flag"));
1253 as_bad (_("failed to parse flags"));
1254 input_line_pointer
= old_input_line_pointer
;
1258 /* Apply the fixups in order. */
1261 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1265 for (i
= 0; i
< insn
->nfixups
; i
++)
1267 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1268 int size
, pcrel
, offset
= 0;
1270 /* FIXME! the reloc size is wrong in the BFD file.
1271 When it is fixed please delete me. */
1272 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1275 offset
= (insn
->short_insn
) ? 2 : 4;
1277 /* Some fixups are only used internally, thus no howto. */
1278 if ((int) fixup
->reloc
== 0)
1279 as_fatal (_("Unhandled reloc type"));
1281 if ((int) fixup
->reloc
< 0)
1283 /* FIXME! the reloc size is wrong in the BFD file.
1284 When it is fixed please enable me.
1285 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1286 pcrel
= fixup
->pcrel
;
1290 reloc_howto_type
*reloc_howto
=
1291 bfd_reloc_type_lookup (stdoutput
,
1292 (bfd_reloc_code_real_type
) fixup
->reloc
);
1293 gas_assert (reloc_howto
);
1295 /* FIXME! the reloc size is wrong in the BFD file.
1296 When it is fixed please enable me.
1297 size = bfd_get_reloc_size (reloc_howto); */
1298 pcrel
= reloc_howto
->pc_relative
;
1301 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1303 fragP
->fr_file
, fragP
->fr_line
,
1304 (fixup
->reloc
< 0) ? "Internal" :
1305 bfd_get_reloc_code_name (fixup
->reloc
),
1308 fix_new_exp (fragP
, fix
+ offset
,
1309 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1311 /* Check for ZOLs, and update symbol info if any. */
1312 if (LP_INSN (insn
->insn
))
1314 gas_assert (fixup
->exp
.X_add_symbol
);
1315 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1320 /* Actually output an instruction with its fixup. */
1323 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1327 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1328 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1329 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1331 /* Write out the instruction. */
1332 if (insn
->short_insn
)
1338 md_number_to_chars (f
, insn
->insn
, 2);
1339 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1340 dwarf2_emit_insn (6);
1346 md_number_to_chars (f
, insn
->insn
, 2);
1347 dwarf2_emit_insn (2);
1356 md_number_to_chars_midend (f
, insn
->insn
, 4);
1357 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1358 dwarf2_emit_insn (8);
1364 md_number_to_chars_midend (f
, insn
->insn
, 4);
1365 dwarf2_emit_insn (4);
1370 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1374 emit_insn1 (struct arc_insn
*insn
)
1376 /* How frag_var's args are currently configured:
1377 - rs_machine_dependent, to dictate it's a relaxation frag.
1378 - FRAG_MAX_GROWTH, maximum size of instruction
1379 - 0, variable size that might grow...unused by generic relaxation.
1380 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1381 - s, opand expression.
1382 - 0, offset but it's unused.
1383 - 0, opcode but it's unused. */
1384 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1385 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1387 if (frag_room () < FRAG_MAX_GROWTH
)
1389 /* Handle differently when frag literal memory is exhausted.
1390 This is used because when there's not enough memory left in
1391 the current frag, a new frag is created and the information
1392 we put into frag_now->tc_frag_data is disregarded. */
1394 struct arc_relax_type relax_info_copy
;
1395 relax_substateT subtype
= frag_now
->fr_subtype
;
1397 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1398 sizeof (struct arc_relax_type
));
1400 frag_wane (frag_now
);
1401 frag_grow (FRAG_MAX_GROWTH
);
1403 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1404 sizeof (struct arc_relax_type
));
1406 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1410 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1411 frag_now
->fr_subtype
, s
, 0, 0);
1415 emit_insn (struct arc_insn
*insn
)
1420 emit_insn0 (insn
, NULL
, FALSE
);
1423 /* Check whether a symbol involves a register. */
1426 contains_register (symbolS
*sym
)
1430 expressionS
*ex
= symbol_get_value_expression (sym
);
1432 return ((O_register
== ex
->X_op
)
1433 && !contains_register (ex
->X_add_symbol
)
1434 && !contains_register (ex
->X_op_symbol
));
1440 /* Returns the register number within a symbol. */
1443 get_register (symbolS
*sym
)
1445 if (!contains_register (sym
))
1448 expressionS
*ex
= symbol_get_value_expression (sym
);
1449 return regno (ex
->X_add_number
);
1452 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1453 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1456 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1463 case BFD_RELOC_ARC_SDA_LDST
:
1464 case BFD_RELOC_ARC_SDA_LDST1
:
1465 case BFD_RELOC_ARC_SDA_LDST2
:
1466 case BFD_RELOC_ARC_SDA16_LD
:
1467 case BFD_RELOC_ARC_SDA16_LD1
:
1468 case BFD_RELOC_ARC_SDA16_LD2
:
1469 case BFD_RELOC_ARC_SDA16_ST2
:
1470 case BFD_RELOC_ARC_SDA32_ME
:
1477 /* Allocates a tok entry. */
1480 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1482 if (ntok
> MAX_INSN_ARGS
- 2)
1483 return 0; /* No space left. */
1486 return 0; /* Incorect args. */
1488 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1491 return 1; /* Success. */
1492 return allocate_tok (tok
, ntok
- 1, cidx
);
1495 /* Check if an particular ARC feature is enabled. */
1498 check_cpu_feature (insn_subclass_t sc
)
1500 if (!(arc_features
& ARC_CD
)
1501 && is_code_density_p (sc
))
1504 if (!(arc_features
& ARC_SPFP
)
1508 if (!(arc_features
& ARC_DPFP
)
1512 if (!(arc_features
& ARC_FPUDA
)
1519 /* Search forward through all variants of an opcode looking for a
1522 static const struct arc_opcode
*
1523 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1526 struct arc_flags
*first_pflag
,
1530 const struct arc_opcode
*opcode
;
1531 struct arc_opcode_hash_entry_iterator iter
;
1533 int got_cpu_match
= 0;
1534 expressionS bktok
[MAX_INSN_ARGS
];
1538 arc_opcode_hash_entry_iterator_init (&iter
);
1539 memset (&emptyE
, 0, sizeof (emptyE
));
1540 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1543 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1545 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1547 const unsigned char *opidx
;
1548 const unsigned char *flgidx
;
1549 int tokidx
= 0, lnflg
, i
;
1550 const expressionS
*t
= &emptyE
;
1552 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1553 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1555 /* Don't match opcodes that don't exist on this
1557 if (!(opcode
->cpu
& arc_target
))
1560 if (!check_cpu_feature (opcode
->subclass
))
1566 /* Check the operands. */
1567 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1569 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1571 /* Only take input from real operands. */
1572 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1573 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1576 /* When we expect input, make sure we have it. */
1580 /* Match operand type with expression type. */
1581 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1583 case ARC_OPERAND_IR
:
1584 /* Check to be a register. */
1585 if ((tok
[tokidx
].X_op
!= O_register
1586 || !is_ir_num (tok
[tokidx
].X_add_number
))
1587 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1590 /* If expect duplicate, make sure it is duplicate. */
1591 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1593 /* Check for duplicate. */
1594 if (t
->X_op
!= O_register
1595 || !is_ir_num (t
->X_add_number
)
1596 || (regno (t
->X_add_number
) !=
1597 regno (tok
[tokidx
].X_add_number
)))
1601 /* Special handling? */
1602 if (operand
->insert
)
1604 const char *errmsg
= NULL
;
1605 (*operand
->insert
)(0,
1606 regno (tok
[tokidx
].X_add_number
),
1610 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1612 /* Missing argument, create one. */
1613 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1616 tok
[tokidx
].X_op
= O_absent
;
1627 case ARC_OPERAND_BRAKET
:
1628 /* Check if bracket is also in opcode table as
1630 if (tok
[tokidx
].X_op
!= O_bracket
)
1634 case ARC_OPERAND_LIMM
:
1635 case ARC_OPERAND_SIGNED
:
1636 case ARC_OPERAND_UNSIGNED
:
1637 switch (tok
[tokidx
].X_op
)
1645 /* Got an (too) early bracket, check if it is an
1646 ignored operand. N.B. This procedure works only
1647 when bracket is the last operand! */
1648 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1650 /* Insert the missing operand. */
1651 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1654 tok
[tokidx
].X_op
= O_absent
;
1662 const struct arc_aux_reg
*auxr
;
1665 if (opcode
->class != AUXREG
)
1667 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1670 auxr
= &arc_aux_regs
[0];
1671 for (j
= 0; j
< arc_num_aux_regs
; j
++, auxr
++)
1672 if (len
== auxr
->length
1673 && strcasecmp (auxr
->name
, p
) == 0
1674 && ((auxr
->subclass
== NONE
)
1675 || check_cpu_feature (auxr
->subclass
)))
1677 /* We modify the token array here, safe in the
1678 knowledge, that if this was the wrong choice
1679 then the original contents will be restored
1681 tok
[tokidx
].X_op
= O_constant
;
1682 tok
[tokidx
].X_add_number
= auxr
->address
;
1683 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1687 if (tok
[tokidx
].X_op
!= O_constant
)
1692 /* Check the range. */
1693 if (operand
->bits
!= 32
1694 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1696 offsetT min
, max
, val
;
1697 val
= tok
[tokidx
].X_add_number
;
1699 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1701 max
= (1 << (operand
->bits
- 1)) - 1;
1702 min
= -(1 << (operand
->bits
- 1));
1706 max
= (1 << operand
->bits
) - 1;
1710 if (val
< min
|| val
> max
)
1713 /* Check alignmets. */
1714 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1718 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1722 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1724 if (operand
->insert
)
1726 const char *errmsg
= NULL
;
1727 (*operand
->insert
)(0,
1728 tok
[tokidx
].X_add_number
,
1739 /* Check if it is register range. */
1740 if ((tok
[tokidx
].X_add_number
== 0)
1741 && contains_register (tok
[tokidx
].X_add_symbol
)
1742 && contains_register (tok
[tokidx
].X_op_symbol
))
1746 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1748 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1749 if (operand
->insert
)
1751 const char *errmsg
= NULL
;
1752 (*operand
->insert
)(0,
1764 if (operand
->default_reloc
== 0)
1765 goto match_failed
; /* The operand needs relocation. */
1767 /* Relocs requiring long immediate. FIXME! make it
1768 generic and move it to a function. */
1769 switch (tok
[tokidx
].X_md
)
1778 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1781 if (!generic_reloc_p (operand
->default_reloc
))
1788 /* If expect duplicate, make sure it is duplicate. */
1789 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1791 if (t
->X_op
== O_illegal
1792 || t
->X_op
== O_absent
1793 || t
->X_op
== O_register
1794 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1801 /* Everything else should have been fake. */
1809 /* Setup ready for flag parsing. */
1811 for (i
= 0; i
< nflgs
; i
++)
1812 first_pflag
[i
].code
= 0;
1814 /* Check the flags. Iterate over the valid flag classes. */
1815 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1817 /* Get a valid flag class. */
1818 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1819 const unsigned *flgopridx
;
1822 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1824 const struct arc_flag_operand
*flg_operand
;
1825 struct arc_flags
*pflag
= first_pflag
;
1827 flg_operand
= &arc_flag_operands
[*flgopridx
];
1828 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1830 /* Match against the parsed flags. */
1831 if (!strcmp (flg_operand
->name
, pflag
->name
))
1833 if (pflag
->code
!= 0)
1836 pflag
->code
= *flgopridx
;
1838 break; /* goto next flag class and parsed flag. */
1843 if (cl_flags
->class == F_CLASS_REQUIRED
&& cl_matches
== 0)
1845 if (cl_flags
->class == F_CLASS_OPTIONAL
&& cl_matches
> 1)
1848 /* Did I check all the parsed flags? */
1853 /* Possible match -- did we use all of our input? */
1863 /* Restore the original parameters. */
1864 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1869 *pcpumatch
= got_cpu_match
;
1874 /* Swap operand tokens. */
1877 swap_operand (expressionS
*operand_array
,
1879 unsigned destination
)
1881 expressionS cpy_operand
;
1882 expressionS
*src_operand
;
1883 expressionS
*dst_operand
;
1886 if (source
== destination
)
1889 src_operand
= &operand_array
[source
];
1890 dst_operand
= &operand_array
[destination
];
1891 size
= sizeof (expressionS
);
1893 /* Make copy of operand to swap with and swap. */
1894 memcpy (&cpy_operand
, dst_operand
, size
);
1895 memcpy (dst_operand
, src_operand
, size
);
1896 memcpy (src_operand
, &cpy_operand
, size
);
1899 /* Check if *op matches *tok type.
1900 Returns FALSE if they don't match, TRUE if they match. */
1903 pseudo_operand_match (const expressionS
*tok
,
1904 const struct arc_operand_operation
*op
)
1906 offsetT min
, max
, val
;
1908 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1914 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1916 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1918 val
= tok
->X_add_number
+ op
->count
;
1919 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1921 max
= (1 << (operand_real
->bits
- 1)) - 1;
1922 min
= -(1 << (operand_real
->bits
- 1));
1926 max
= (1 << operand_real
->bits
) - 1;
1929 if (min
<= val
&& val
<= max
)
1935 /* Handle all symbols as long immediates or signed 9. */
1936 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
1937 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
1942 if (operand_real
->flags
& ARC_OPERAND_IR
)
1947 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
1958 /* Find pseudo instruction in array. */
1960 static const struct arc_pseudo_insn
*
1961 find_pseudo_insn (const char *opname
,
1963 const expressionS
*tok
)
1965 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
1966 const struct arc_operand_operation
*op
;
1970 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
1972 pseudo_insn
= &arc_pseudo_insns
[i
];
1973 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
1975 op
= pseudo_insn
->operand
;
1976 for (j
= 0; j
< ntok
; ++j
)
1977 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
1980 /* Found the right instruction. */
1988 /* Assumes the expressionS *tok is of sufficient size. */
1990 static const struct arc_opcode_hash_entry
*
1991 find_special_case_pseudo (const char *opname
,
1995 struct arc_flags
*pflags
)
1997 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
1998 const struct arc_operand_operation
*operand_pseudo
;
1999 const struct arc_operand
*operand_real
;
2001 char construct_operand
[MAX_CONSTR_STR
];
2003 /* Find whether opname is in pseudo instruction array. */
2004 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2006 if (pseudo_insn
== NULL
)
2009 /* Handle flag, Limited to one flag at the moment. */
2010 if (pseudo_insn
->flag_r
!= NULL
)
2011 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2012 MAX_INSN_FLGS
- *nflgs
);
2014 /* Handle operand operations. */
2015 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2017 operand_pseudo
= &pseudo_insn
->operand
[i
];
2018 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2020 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
2021 !operand_pseudo
->needs_insert
)
2024 /* Has to be inserted (i.e. this token does not exist yet). */
2025 if (operand_pseudo
->needs_insert
)
2027 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2029 tok
[i
].X_op
= O_bracket
;
2034 /* Check if operand is a register or constant and handle it
2036 if (operand_real
->flags
& ARC_OPERAND_IR
)
2037 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2038 operand_pseudo
->count
);
2040 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2041 operand_pseudo
->count
);
2043 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2047 else if (operand_pseudo
->count
)
2049 /* Operand number has to be adjusted accordingly (by operand
2051 switch (tok
[i
].X_op
)
2054 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2067 /* Swap operands if necessary. Only supports one swap at the
2069 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2071 operand_pseudo
= &pseudo_insn
->operand
[i
];
2073 if (operand_pseudo
->swap_operand_idx
== i
)
2076 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2078 /* Prevent a swap back later by breaking out. */
2082 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2085 static const struct arc_opcode_hash_entry
*
2086 find_special_case_flag (const char *opname
,
2088 struct arc_flags
*pflags
)
2092 unsigned flag_idx
, flag_arr_idx
;
2093 size_t flaglen
, oplen
;
2094 const struct arc_flag_special
*arc_flag_special_opcode
;
2095 const struct arc_opcode_hash_entry
*entry
;
2097 /* Search for special case instruction. */
2098 for (i
= 0; i
< arc_num_flag_special
; i
++)
2100 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2101 oplen
= strlen (arc_flag_special_opcode
->name
);
2103 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2106 /* Found a potential special case instruction, now test for
2108 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2110 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2112 break; /* End of array, nothing found. */
2114 flagnm
= arc_flag_operands
[flag_idx
].name
;
2115 flaglen
= strlen (flagnm
);
2116 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2118 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2120 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2122 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2123 pflags
[*nflgs
].name
[flaglen
] = '\0';
2132 /* Used to find special case opcode. */
2134 static const struct arc_opcode_hash_entry
*
2135 find_special_case (const char *opname
,
2137 struct arc_flags
*pflags
,
2141 const struct arc_opcode_hash_entry
*entry
;
2143 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2146 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2151 /* Given an opcode name, pre-tockenized set of argumenst and the
2152 opcode flags, take it all the way through emission. */
2155 assemble_tokens (const char *opname
,
2158 struct arc_flags
*pflags
,
2161 bfd_boolean found_something
= FALSE
;
2162 const struct arc_opcode_hash_entry
*entry
;
2165 /* Search opcodes. */
2166 entry
= arc_find_opcode (opname
);
2168 /* Couldn't find opcode conventional way, try special cases. */
2170 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2174 const struct arc_opcode
*opcode
;
2176 pr_debug ("%s:%d: assemble_tokens: %s\n",
2177 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2178 found_something
= TRUE
;
2179 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2183 struct arc_insn insn
;
2185 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2191 if (found_something
)
2194 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2196 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2200 as_bad (_("unknown opcode '%s'"), opname
);
2203 /* The public interface to the instruction assembler. */
2206 md_assemble (char *str
)
2209 expressionS tok
[MAX_INSN_ARGS
];
2212 struct arc_flags flags
[MAX_INSN_FLGS
];
2214 /* Split off the opcode. */
2215 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2216 opname
= xmalloc (opnamelen
+ 1);
2217 memcpy (opname
, str
, opnamelen
);
2218 opname
[opnamelen
] = '\0';
2220 /* Signalize we are assmbling the instructions. */
2221 assembling_insn
= TRUE
;
2223 /* Tokenize the flags. */
2224 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2226 as_bad (_("syntax error"));
2230 /* Scan up to the end of the mnemonic which must end in space or end
2233 for (; *str
!= '\0'; str
++)
2237 /* Tokenize the rest of the line. */
2238 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2240 as_bad (_("syntax error"));
2244 /* Finish it off. */
2245 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2246 assembling_insn
= FALSE
;
2249 /* Callback to insert a register into the hash table. */
2252 declare_register (const char *name
, int number
)
2255 symbolS
*regS
= symbol_create (name
, reg_section
,
2256 number
, &zero_address_frag
);
2258 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2260 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2264 /* Construct symbols for each of the general registers. */
2267 declare_register_set (void)
2270 for (i
= 0; i
< 64; ++i
)
2274 sprintf (name
, "r%d", i
);
2275 declare_register (name
, i
);
2276 if ((i
& 0x01) == 0)
2278 sprintf (name
, "r%dr%d", i
, i
+1);
2279 declare_register (name
, i
);
2284 /* Port-specific assembler initialization. This function is called
2285 once, at assembler startup time. */
2290 const struct arc_opcode
*opcode
= arc_opcodes
;
2292 if (!mach_type_specified_p
)
2293 arc_select_cpu ("arc700");
2295 /* The endianness can be chosen "at the factory". */
2296 target_big_endian
= byte_order
== BIG_ENDIAN
;
2298 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2299 as_warn (_("could not set architecture and machine"));
2301 /* Set elf header flags. */
2302 bfd_set_private_flags (stdoutput
, arc_eflag
);
2304 /* Set up a hash table for the instructions. */
2305 arc_opcode_hash
= hash_new ();
2306 if (arc_opcode_hash
== NULL
)
2307 as_fatal (_("Virtual memory exhausted"));
2309 /* Initialize the hash table with the insns. */
2312 const char *name
= opcode
->name
;
2314 arc_insert_opcode (opcode
);
2316 while (++opcode
&& opcode
->name
2317 && (opcode
->name
== name
2318 || !strcmp (opcode
->name
, name
)))
2320 }while (opcode
->name
);
2322 /* Register declaration. */
2323 arc_reg_hash
= hash_new ();
2324 if (arc_reg_hash
== NULL
)
2325 as_fatal (_("Virtual memory exhausted"));
2327 declare_register_set ();
2328 declare_register ("gp", 26);
2329 declare_register ("fp", 27);
2330 declare_register ("sp", 28);
2331 declare_register ("ilink", 29);
2332 declare_register ("ilink1", 29);
2333 declare_register ("ilink2", 30);
2334 declare_register ("blink", 31);
2336 declare_register ("mlo", 57);
2337 declare_register ("mmid", 58);
2338 declare_register ("mhi", 59);
2340 declare_register ("acc1", 56);
2341 declare_register ("acc2", 57);
2343 declare_register ("lp_count", 60);
2344 declare_register ("pcl", 63);
2346 /* Initialize the last instructions. */
2347 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2350 /* Write a value out to the object file, using the appropriate
2354 md_number_to_chars (char *buf
,
2358 if (target_big_endian
)
2359 number_to_chars_bigendian (buf
, val
, n
);
2361 number_to_chars_littleendian (buf
, val
, n
);
2364 /* Round up a section size to the appropriate boundary. */
2367 md_section_align (segT segment
,
2370 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2372 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2375 /* The location from which a PC relative jump should be calculated,
2376 given a PC relative reloc. */
2379 md_pcrel_from_section (fixS
*fixP
,
2382 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2384 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2386 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2387 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2388 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2390 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2392 /* The symbol is undefined (or is defined but not in this section).
2393 Let the linker figure it out. */
2397 if ((int) fixP
->fx_r_type
< 0)
2399 /* These are the "internal" relocations. Align them to
2400 32 bit boundary (PCL), for the moment. */
2405 switch (fixP
->fx_r_type
)
2407 case BFD_RELOC_ARC_PC32
:
2408 /* The hardware calculates relative to the start of the
2409 insn, but this relocation is relative to location of the
2410 LIMM, compensate. The base always needs to be
2411 substracted by 4 as we do not support this type of PCrel
2412 relocation for short instructions. */
2415 case BFD_RELOC_ARC_PLT32
:
2416 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2417 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2418 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2419 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2421 case BFD_RELOC_ARC_S21H_PCREL
:
2422 case BFD_RELOC_ARC_S25H_PCREL
:
2423 case BFD_RELOC_ARC_S13_PCREL
:
2424 case BFD_RELOC_ARC_S21W_PCREL
:
2425 case BFD_RELOC_ARC_S25W_PCREL
:
2429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2430 _("unhandled reloc %s in md_pcrel_from_section"),
2431 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2436 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2437 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2438 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2439 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2444 /* Given a BFD relocation find the coresponding operand. */
2446 static const struct arc_operand
*
2447 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2451 for (i
= 0; i
< arc_num_operands
; i
++)
2452 if (arc_operands
[i
].default_reloc
== reloc
)
2453 return &arc_operands
[i
];
2457 /* Insert an operand value into an instruction. */
2460 insert_operand (unsigned insn
,
2461 const struct arc_operand
*operand
,
2466 offsetT min
= 0, max
= 0;
2468 if (operand
->bits
!= 32
2469 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2470 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2472 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2474 max
= (1 << (operand
->bits
- 1)) - 1;
2475 min
= -(1 << (operand
->bits
- 1));
2479 max
= (1 << operand
->bits
) - 1;
2483 if (val
< min
|| val
> max
)
2484 as_bad_value_out_of_range (_("operand"),
2485 val
, min
, max
, file
, line
);
2488 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2489 min
, val
, max
, insn
);
2491 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2493 as_bad_where (file
, line
,
2494 _("Unaligned operand. Needs to be 32bit aligned"));
2496 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2498 as_bad_where (file
, line
,
2499 _("Unaligned operand. Needs to be 16bit aligned"));
2501 if (operand
->insert
)
2503 const char *errmsg
= NULL
;
2505 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2507 as_warn_where (file
, line
, "%s", errmsg
);
2511 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2513 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2515 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2518 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2523 /* Apply a fixup to the object code. At this point all symbol values
2524 should be fully resolved, and we attempt to completely resolve the
2525 reloc. If we can not do that, we determine the correct reloc code
2526 and put it back in the fixup. To indicate that a fixup has been
2527 eliminated, set fixP->fx_done. */
2530 md_apply_fix (fixS
*fixP
,
2534 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2535 valueT value
= *valP
;
2537 symbolS
*fx_addsy
, *fx_subsy
;
2539 segT add_symbol_segment
= absolute_section
;
2540 segT sub_symbol_segment
= absolute_section
;
2541 const struct arc_operand
*operand
= NULL
;
2542 extended_bfd_reloc_code_real_type reloc
;
2544 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2545 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2546 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2547 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2550 fx_addsy
= fixP
->fx_addsy
;
2551 fx_subsy
= fixP
->fx_subsy
;
2556 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2560 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2561 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2562 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2564 resolve_symbol_value (fx_subsy
);
2565 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2567 if (sub_symbol_segment
== absolute_section
)
2569 /* The symbol is really a constant. */
2570 fx_offset
-= S_GET_VALUE (fx_subsy
);
2575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2576 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2577 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2578 segment_name (add_symbol_segment
),
2579 S_GET_NAME (fx_subsy
),
2580 segment_name (sub_symbol_segment
));
2586 && !S_IS_WEAK (fx_addsy
))
2588 if (add_symbol_segment
== seg
2591 value
+= S_GET_VALUE (fx_addsy
);
2592 value
-= md_pcrel_from_section (fixP
, seg
);
2594 fixP
->fx_pcrel
= FALSE
;
2596 else if (add_symbol_segment
== absolute_section
)
2598 value
= fixP
->fx_offset
;
2599 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2601 fixP
->fx_pcrel
= FALSE
;
2606 fixP
->fx_done
= TRUE
;
2611 && ((S_IS_DEFINED (fx_addsy
)
2612 && S_GET_SEGMENT (fx_addsy
) != seg
)
2613 || S_IS_WEAK (fx_addsy
)))
2614 value
+= md_pcrel_from_section (fixP
, seg
);
2616 switch (fixP
->fx_r_type
)
2618 case BFD_RELOC_ARC_32_ME
:
2619 /* This is a pc-relative value in a LIMM. Adjust it to the
2620 address of the instruction not to the address of the
2621 LIMM. Note: it is not anylonger valid this afirmation as
2622 the linker consider ARC_PC32 a fixup to entire 64 bit
2624 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2627 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2629 case BFD_RELOC_ARC_PC32
:
2630 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2633 if ((int) fixP
->fx_r_type
< 0)
2634 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2640 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2641 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2642 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2643 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2647 /* Now check for TLS relocations. */
2648 reloc
= fixP
->fx_r_type
;
2651 case BFD_RELOC_ARC_TLS_DTPOFF
:
2652 case BFD_RELOC_ARC_TLS_LE_32
:
2656 case BFD_RELOC_ARC_TLS_GD_GOT
:
2657 case BFD_RELOC_ARC_TLS_IE_GOT
:
2658 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2661 case BFD_RELOC_ARC_TLS_GD_LD
:
2662 gas_assert (!fixP
->fx_offset
);
2665 = (S_GET_VALUE (fixP
->fx_subsy
)
2666 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2667 fixP
->fx_subsy
= NULL
;
2669 case BFD_RELOC_ARC_TLS_GD_CALL
:
2670 /* These two relocs are there just to allow ld to change the tls
2671 model for this symbol, by patching the code. The offset -
2672 and scale, if any - will be installed by the linker. */
2673 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2676 case BFD_RELOC_ARC_TLS_LE_S9
:
2677 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2678 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2690 /* Addjust the value if we have a constant. */
2693 /* For hosts with longs bigger than 32-bits make sure that the top
2694 bits of a 32-bit negative value read in by the parser are set,
2695 so that the correct comparisons are made. */
2696 if (value
& 0x80000000)
2697 value
|= (-1L << 31);
2699 reloc
= fixP
->fx_r_type
;
2707 case BFD_RELOC_ARC_32_PCREL
:
2708 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2711 case BFD_RELOC_ARC_GOTPC32
:
2712 /* I cannot fix an GOTPC relocation because I need to relax it
2713 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2714 as_bad (_("Unsupported operation on reloc"));
2717 case BFD_RELOC_ARC_TLS_DTPOFF
:
2718 case BFD_RELOC_ARC_TLS_LE_32
:
2719 gas_assert (!fixP
->fx_addsy
);
2720 gas_assert (!fixP
->fx_subsy
);
2722 case BFD_RELOC_ARC_GOTOFF
:
2723 case BFD_RELOC_ARC_32_ME
:
2724 case BFD_RELOC_ARC_PC32
:
2725 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2728 case BFD_RELOC_ARC_PLT32
:
2729 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2732 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2733 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2736 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2737 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2740 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2741 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2744 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2745 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2747 case BFD_RELOC_ARC_S25W_PCREL
:
2748 case BFD_RELOC_ARC_S21W_PCREL
:
2749 case BFD_RELOC_ARC_S21H_PCREL
:
2750 case BFD_RELOC_ARC_S25H_PCREL
:
2751 case BFD_RELOC_ARC_S13_PCREL
:
2753 operand
= find_operand_for_reloc (reloc
);
2754 gas_assert (operand
);
2759 if ((int) fixP
->fx_r_type
>= 0)
2760 as_fatal (_("unhandled relocation type %s"),
2761 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2763 /* The rest of these fixups needs to be completely resolved as
2765 if (fixP
->fx_addsy
!= 0
2766 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2767 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2768 _("non-absolute expression in constant field"));
2770 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2771 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2776 if (target_big_endian
)
2778 switch (fixP
->fx_size
)
2781 insn
= bfd_getb32 (fixpos
);
2784 insn
= bfd_getb16 (fixpos
);
2787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2788 _("unknown fixup size"));
2794 switch (fixP
->fx_size
)
2797 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2800 insn
= bfd_getl16 (fixpos
);
2803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2804 _("unknown fixup size"));
2808 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
2809 fixP
->fx_file
, fixP
->fx_line
);
2811 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
2814 /* Prepare machine-dependent frags for relaxation.
2816 Called just before relaxation starts. Any symbol that is now undefined
2817 will not become defined.
2819 Return the correct fr_subtype in the frag.
2821 Return the initial "guess for fr_var" to caller. The guess for fr_var
2822 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2823 or fr_var contributes to our returned value.
2825 Although it may not be explicit in the frag, pretend
2826 fr_var starts with a value. */
2829 md_estimate_size_before_relax (fragS
*fragP
,
2834 /* If the symbol is not located within the same section AND it's not
2835 an absolute section, use the maximum. OR if the symbol is a
2836 constant AND the insn is by nature not pc-rel, use the maximum.
2837 OR if the symbol is being equated against another symbol, use the
2838 maximum. OR if the symbol is weak use the maximum. */
2839 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2840 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2841 || (symbol_constant_p (fragP
->fr_symbol
)
2842 && !fragP
->tc_frag_data
.pcrel
)
2843 || symbol_equated_p (fragP
->fr_symbol
)
2844 || S_IS_WEAK (fragP
->fr_symbol
))
2846 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
2847 ++fragP
->fr_subtype
;
2850 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2851 fragP
->fr_var
= growth
;
2853 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2854 fragP
->fr_file
, fragP
->fr_line
, growth
);
2859 /* Translate internal representation of relocation info to BFD target
2863 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
2867 bfd_reloc_code_real_type code
;
2869 reloc
= (arelent
*) xmalloc (sizeof (* reloc
));
2870 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2871 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2872 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2874 /* Make sure none of our internal relocations make it this far.
2875 They'd better have been fully resolved by this point. */
2876 gas_assert ((int) fixP
->fx_r_type
> 0);
2878 code
= fixP
->fx_r_type
;
2880 /* if we have something like add gp, pcl,
2881 _GLOBAL_OFFSET_TABLE_@gotpc. */
2882 if (code
== BFD_RELOC_ARC_GOTPC32
2884 && fixP
->fx_addsy
== GOT_symbol
)
2885 code
= BFD_RELOC_ARC_GOTPC
;
2887 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2888 if (reloc
->howto
== NULL
)
2890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2891 _("cannot represent `%s' relocation in object file"),
2892 bfd_get_reloc_code_name (code
));
2896 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
2897 as_fatal (_("internal error? cannot generate `%s' relocation"),
2898 bfd_get_reloc_code_name (code
));
2900 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
2902 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
2903 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
2906 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
2907 /* We just want to store a 24 bit index, but we have to wait
2908 till after write_contents has been called via
2909 bfd_map_over_sections before we can get the index from
2910 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2911 function is elf32-arc.c has to pick up the slack.
2912 Unfortunately, this leads to problems with hosts that have
2913 pointers wider than long (bfd_vma). There would be various
2914 ways to handle this, all error-prone :-( */
2915 reloc
->addend
= (bfd_vma
) sym
;
2916 if ((asymbol
*) reloc
->addend
!= sym
)
2918 as_bad ("Can't store pointer\n");
2923 reloc
->addend
= fixP
->fx_offset
;
2928 /* Perform post-processing of machine-dependent frags after relaxation.
2929 Called after relaxation is finished.
2930 In: Address of frag.
2931 fr_type == rs_machine_dependent.
2932 fr_subtype is what the address relaxed to.
2934 Out: Any fixS:s and constants are set up. */
2937 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
2938 segT segment ATTRIBUTE_UNUSED
,
2941 const relax_typeS
*table_entry
;
2943 const struct arc_opcode
*opcode
;
2944 struct arc_insn insn
;
2946 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
2948 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
2949 dest
= fragP
->fr_literal
+ fix
;
2950 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
2952 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
2953 fragP
->fr_file
, fragP
->fr_line
,
2954 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
2956 if (fragP
->fr_subtype
<= 0
2957 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
2958 as_fatal (_("no relaxation found for this instruction."));
2960 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
2962 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
2963 relax_arg
->nflg
, &insn
);
2965 apply_fixups (&insn
, fragP
, fix
);
2967 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
2968 gas_assert (table_entry
->rlx_length
== size
);
2969 emit_insn0 (&insn
, dest
, TRUE
);
2971 fragP
->fr_fix
+= table_entry
->rlx_length
;
2975 /* We have no need to default values of symbols. We could catch
2976 register names here, but that is handled by inserting them all in
2977 the symbol table to begin with. */
2980 md_undefined_symbol (char *name
)
2982 /* The arc abi demands that a GOT[0] should be referencible as
2983 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
2984 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
2986 && (*(name
+1) == 'G')
2987 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
2989 && (*(name
+1) == 'D')
2990 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
2994 if (symbol_find (name
))
2995 as_bad ("GOT already in symbol table");
2997 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
2998 (valueT
) 0, &zero_address_frag
);
3005 /* Turn a string in input_line_pointer into a floating point constant
3006 of type type, and store the appropriate bytes in *litP. The number
3007 of LITTLENUMS emitted is stored in *sizeP. An error message is
3008 returned, or NULL on OK. */
3011 md_atof (int type
, char *litP
, int *sizeP
)
3013 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3016 /* Called for any expression that can not be recognized. When the
3017 function is called, `input_line_pointer' will point to the start of
3021 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3023 char *p
= input_line_pointer
;
3026 input_line_pointer
++;
3027 expressionP
->X_op
= O_symbol
;
3028 expression (expressionP
);
3032 /* This function is called from the function 'expression', it attempts
3033 to parse special names (in our case register names). It fills in
3034 the expression with the identified register. It returns TRUE if
3035 it is a register and FALSE otherwise. */
3038 arc_parse_name (const char *name
,
3039 struct expressionS
*e
)
3043 if (!assembling_insn
)
3046 /* Handle only registers. */
3047 if (e
->X_op
!= O_absent
)
3050 sym
= hash_find (arc_reg_hash
, name
);
3053 e
->X_op
= O_register
;
3054 e
->X_add_number
= S_GET_VALUE (sym
);
3061 Invocation line includes a switch not recognized by the base assembler.
3062 See if it's a processor-specific option.
3064 New options (supported) are:
3066 -mcpu=<cpu name> Assemble for selected processor
3067 -EB/-mbig-endian Big-endian
3068 -EL/-mlittle-endian Little-endian
3069 -mrelax Enable relaxation
3071 The following CPU names are recognized:
3072 arc700, av2em, av2hs. */
3075 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3081 return md_parse_option (OPTION_MCPU
, "arc600");
3084 return md_parse_option (OPTION_MCPU
, "arc700");
3087 return md_parse_option (OPTION_MCPU
, "arcem");
3090 return md_parse_option (OPTION_MCPU
, "archs");
3094 arc_select_cpu (arg
);
3095 mach_type_specified_p
= 1;
3100 arc_target_format
= "elf32-bigarc";
3101 byte_order
= BIG_ENDIAN
;
3105 arc_target_format
= "elf32-littlearc";
3106 byte_order
= LITTLE_ENDIAN
;
3110 /* This option has an effect only on ARC EM. */
3111 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3112 arc_features
|= ARC_CD
;
3114 as_warn (_("Code density option invalid for selected CPU"));
3118 relaxation_state
= 1;
3121 case OPTION_USER_MODE
:
3122 case OPTION_LD_EXT_MASK
:
3125 case OPTION_BARREL_SHIFT
:
3126 case OPTION_MIN_MAX
:
3131 /* Dummy options are accepted but have no effect. */
3135 arc_features
|= ARC_SPFP
;
3139 arc_features
|= ARC_DPFP
;
3142 case OPTION_XMAC_D16
:
3143 case OPTION_XMAC_24
:
3144 case OPTION_DSP_PACKA
:
3147 case OPTION_TELEPHONY
:
3148 case OPTION_XYMEMORY
:
3152 /* Dummy options are accepted but have no effect. */
3156 /* This option has an effect only on ARC EM. */
3157 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3158 arc_features
|= ARC_FPUDA
;
3160 as_warn (_("FPUDA invalid for selected CPU"));
3171 md_show_usage (FILE *stream
)
3173 fprintf (stream
, _("ARC-specific assembler options:\n"));
3175 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3177 " -mcode-density\t enable code density option for ARC EM\n");
3179 fprintf (stream
, _("\
3180 -EB assemble code for a big-endian cpu\n"));
3181 fprintf (stream
, _("\
3182 -EL assemble code for a little-endian cpu\n"));
3183 fprintf (stream
, _("\
3184 -mrelax Enable relaxation\n"));
3188 /* Find the proper relocation for the given opcode. */
3190 static extended_bfd_reloc_code_real_type
3191 find_reloc (const char *name
,
3192 const char *opcodename
,
3193 const struct arc_flags
*pflags
,
3195 extended_bfd_reloc_code_real_type reloc
)
3199 bfd_boolean found_flag
, tmp
;
3200 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3202 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3204 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3206 /* Find the entry. */
3207 if (strcmp (name
, r
->name
))
3209 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3216 unsigned * psflg
= (unsigned *)r
->flags
;
3220 for (j
= 0; j
< nflg
; j
++)
3221 if (!strcmp (pflags
[j
].name
,
3222 arc_flag_operands
[*psflg
].name
))
3243 if (reloc
!= r
->oldreloc
)
3250 if (ret
== BFD_RELOC_UNUSED
)
3251 as_bad (_("Unable to find %s relocation for instruction %s"),
3256 /* All the symbol types that are allowed to be used for
3260 may_relax_expr (expressionS tok
)
3262 /* Check if we have unrelaxable relocs. */
3287 /* Checks if flags are in line with relaxable insn. */
3290 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3291 const struct arc_flags
*pflags
,
3294 unsigned flag_class
,
3299 const struct arc_flag_operand
*flag_opand
;
3300 int i
, counttrue
= 0;
3302 /* Iterate through flags classes. */
3303 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3305 /* Iterate through flags in flag class. */
3306 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3309 flag_opand
= &arc_flag_operands
[flag
];
3310 /* Iterate through flags in ins to compare. */
3311 for (i
= 0; i
< nflgs
; ++i
)
3313 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3324 /* If counttrue == nflgs, then all flags have been found. */
3325 return (counttrue
== nflgs
? TRUE
: FALSE
);
3328 /* Checks if operands are in line with relaxable insn. */
3331 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3332 const expressionS
*tok
,
3335 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3338 while (*operand
!= EMPTY
)
3340 const expressionS
*epr
= &tok
[i
];
3342 if (i
!= 0 && i
>= ntok
)
3348 if (!(epr
->X_op
== O_multiply
3349 || epr
->X_op
== O_divide
3350 || epr
->X_op
== O_modulus
3351 || epr
->X_op
== O_add
3352 || epr
->X_op
== O_subtract
3353 || epr
->X_op
== O_symbol
))
3359 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3363 if (epr
->X_op
!= O_register
)
3368 if (epr
->X_op
!= O_register
)
3371 switch (epr
->X_add_number
)
3373 case 0: case 1: case 2: case 3:
3374 case 12: case 13: case 14: case 15:
3381 case REGISTER_NO_GP
:
3382 if ((epr
->X_op
!= O_register
)
3383 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3388 if (epr
->X_op
!= O_bracket
)
3393 /* Don't understand, bail out. */
3399 operand
= &ins
->operands
[i
];
3402 return (i
== ntok
? TRUE
: FALSE
);
3405 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3408 relax_insn_p (const struct arc_opcode
*opcode
,
3409 const expressionS
*tok
,
3411 const struct arc_flags
*pflags
,
3415 bfd_boolean rv
= FALSE
;
3417 /* Check the relaxation table. */
3418 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3420 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3422 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3423 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3424 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3425 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3428 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3429 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3430 sizeof (expressionS
) * ntok
);
3431 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3432 sizeof (struct arc_flags
) * nflg
);
3433 frag_now
->tc_frag_data
.nflg
= nflg
;
3434 frag_now
->tc_frag_data
.ntok
= ntok
;
3442 /* Turn an opcode description and a set of arguments into
3443 an instruction and a fixup. */
3446 assemble_insn (const struct arc_opcode
*opcode
,
3447 const expressionS
*tok
,
3449 const struct arc_flags
*pflags
,
3451 struct arc_insn
*insn
)
3453 const expressionS
*reloc_exp
= NULL
;
3455 const unsigned char *argidx
;
3458 unsigned char pcrel
= 0;
3459 bfd_boolean needGOTSymbol
;
3460 bfd_boolean has_delay_slot
= FALSE
;
3461 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3463 memset (insn
, 0, sizeof (*insn
));
3464 image
= opcode
->opcode
;
3466 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3467 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3470 /* Handle operands. */
3471 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3473 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3474 const expressionS
*t
= (const expressionS
*) 0;
3476 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3477 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3480 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3482 /* Duplicate operand, already inserted. */
3494 /* Regardless if we have a reloc or not mark the instruction
3495 limm if it is the case. */
3496 if (operand
->flags
& ARC_OPERAND_LIMM
)
3497 insn
->has_limm
= TRUE
;
3502 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3507 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3509 if (operand
->flags
& ARC_OPERAND_LIMM
)
3510 insn
->limm
= t
->X_add_number
;
3514 /* Ignore brackets. */
3518 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3522 /* Maybe register range. */
3523 if ((t
->X_add_number
== 0)
3524 && contains_register (t
->X_add_symbol
)
3525 && contains_register (t
->X_op_symbol
))
3529 regs
= get_register (t
->X_add_symbol
);
3531 regs
|= get_register (t
->X_op_symbol
);
3532 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3537 /* This operand needs a relocation. */
3538 needGOTSymbol
= FALSE
;
3543 if (opcode
->class == JUMP
)
3544 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3545 _("Unable to use @plt relocatio for insn %s"),
3547 needGOTSymbol
= TRUE
;
3548 reloc
= find_reloc ("plt", opcode
->name
,
3550 operand
->default_reloc
);
3555 needGOTSymbol
= TRUE
;
3556 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3559 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3560 if (ARC_SHORT (opcode
->mask
) || opcode
->class == JUMP
)
3561 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3562 _("Unable to use @pcl relocation for insn %s"),
3566 reloc
= find_reloc ("sda", opcode
->name
,
3568 operand
->default_reloc
);
3572 needGOTSymbol
= TRUE
;
3577 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3580 case O_tpoff9
: /*FIXME! Check for the conditionality of
3582 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3584 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3588 /* Just consider the default relocation. */
3589 reloc
= operand
->default_reloc
;
3593 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3594 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3601 /* sanity checks. */
3602 reloc_howto_type
*reloc_howto
3603 = bfd_reloc_type_lookup (stdoutput
,
3604 (bfd_reloc_code_real_type
) reloc
);
3605 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3606 if (reloc_howto
->rightshift
)
3607 reloc_bitsize
-= reloc_howto
->rightshift
;
3608 if (reloc_bitsize
!= operand
->bits
)
3610 as_bad (_("invalid relocation %s for field"),
3611 bfd_get_reloc_code_name (reloc
));
3616 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3617 as_fatal (_("too many fixups"));
3619 struct arc_fixup
*fixup
;
3620 fixup
= &insn
->fixups
[insn
->nfixups
++];
3622 fixup
->reloc
= reloc
;
3623 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3624 fixup
->pcrel
= pcrel
;
3625 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3632 for (i
= 0; i
< nflg
; i
++)
3634 const struct arc_flag_operand
*flg_operand
=
3635 &arc_flag_operands
[pflags
[i
].code
];
3637 /* Check if the instruction has a delay slot. */
3638 if (!strcmp (flg_operand
->name
, "d"))
3639 has_delay_slot
= TRUE
;
3641 /* There is an exceptional case when we cannot insert a flag
3642 just as it is. The .T flag must be handled in relation with
3643 the relative address. */
3644 if (!strcmp (flg_operand
->name
, "t")
3645 || !strcmp (flg_operand
->name
, "nt"))
3647 unsigned bitYoperand
= 0;
3648 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3649 if (!strcmp (flg_operand
->name
, "t"))
3650 if (!strcmp (opcode
->name
, "bbit0")
3651 || !strcmp (opcode
->name
, "bbit1"))
3652 bitYoperand
= arc_NToperand
;
3654 bitYoperand
= arc_Toperand
;
3656 if (!strcmp (opcode
->name
, "bbit0")
3657 || !strcmp (opcode
->name
, "bbit1"))
3658 bitYoperand
= arc_Toperand
;
3660 bitYoperand
= arc_NToperand
;
3662 gas_assert (reloc_exp
!= NULL
);
3663 if (reloc_exp
->X_op
== O_constant
)
3665 /* Check if we have a constant and solved it
3667 offsetT val
= reloc_exp
->X_add_number
;
3668 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3673 struct arc_fixup
*fixup
;
3675 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3676 as_fatal (_("too many fixups"));
3678 fixup
= &insn
->fixups
[insn
->nfixups
++];
3679 fixup
->exp
= *reloc_exp
;
3680 fixup
->reloc
= -bitYoperand
;
3681 fixup
->pcrel
= pcrel
;
3682 fixup
->islong
= FALSE
;
3686 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3687 << flg_operand
->shift
;
3690 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3692 /* Short instruction? */
3693 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3697 /* Update last insn status. */
3698 arc_last_insns
[1] = arc_last_insns
[0];
3699 arc_last_insns
[0].opcode
= opcode
;
3700 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3701 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3703 /* Check if the current instruction is legally used. */
3704 if (arc_last_insns
[1].has_delay_slot
3705 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3706 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3707 _("A jump/branch instruction in delay slot."));
3711 arc_handle_align (fragS
* fragP
)
3713 if ((fragP
)->fr_type
== rs_align_code
)
3715 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3716 valueT count
= ((fragP
)->fr_next
->fr_address
3717 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3719 (fragP
)->fr_var
= 2;
3721 if (count
& 1)/* Padding in the gap till the next 2-byte
3722 boundary with 0s. */
3727 /* Writing nop_s. */
3728 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3732 /* Here we decide which fixups can be adjusted to make them relative
3733 to the beginning of the section instead of the symbol. Basically
3734 we need to make sure that the dynamic relocations are done
3735 correctly, so in some cases we force the original symbol to be
3739 tc_arc_fix_adjustable (fixS
*fixP
)
3742 /* Prevent all adjustments to global symbols. */
3743 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3745 if (S_IS_WEAK (fixP
->fx_addsy
))
3748 /* Adjust_reloc_syms doesn't know about the GOT. */
3749 switch (fixP
->fx_r_type
)
3751 case BFD_RELOC_ARC_GOTPC32
:
3752 case BFD_RELOC_ARC_PLT32
:
3753 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3754 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3755 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3756 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3766 /* Compute the reloc type of an expression EXP. */
3769 arc_check_reloc (expressionS
*exp
,
3770 bfd_reloc_code_real_type
*r_type_p
)
3772 if (*r_type_p
== BFD_RELOC_32
3773 && exp
->X_op
== O_subtract
3774 && exp
->X_op_symbol
!= NULL
3775 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3776 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
3780 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3783 arc_cons_fix_new (fragS
*frag
,
3787 bfd_reloc_code_real_type r_type
)
3789 r_type
= BFD_RELOC_UNUSED
;
3794 r_type
= BFD_RELOC_8
;
3798 r_type
= BFD_RELOC_16
;
3802 r_type
= BFD_RELOC_24
;
3806 r_type
= BFD_RELOC_32
;
3807 arc_check_reloc (exp
, &r_type
);
3811 r_type
= BFD_RELOC_64
;
3815 as_bad (_("unsupported BFD relocation size %u"), size
);
3816 r_type
= BFD_RELOC_UNUSED
;
3819 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
3822 /* The actual routine that checks the ZOL conditions. */
3825 check_zol (symbolS
*s
)
3827 switch (arc_mach_type
)
3829 case bfd_mach_arc_arcv2
:
3830 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3833 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
3834 || arc_last_insns
[1].has_delay_slot
)
3835 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3839 case bfd_mach_arc_arc600
:
3841 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
3842 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3845 if (arc_last_insns
[0].has_limm
3846 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3847 as_bad (_("A jump instruction with long immediate detected at the \
3848 end of the ZOL label @%s"), S_GET_NAME (s
));
3851 case bfd_mach_arc_nps400
:
3852 case bfd_mach_arc_arc700
:
3853 if (arc_last_insns
[0].has_delay_slot
)
3854 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3863 /* If ZOL end check the last two instruction for illegals. */
3865 arc_frob_label (symbolS
* sym
)
3867 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
3870 dwarf2_emit_label (sym
);
3873 /* Used because generic relaxation assumes a pc-rel value whilst we
3874 also relax instructions that use an absolute value resolved out of
3875 relative values (if that makes any sense). An example: 'add r1,
3876 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3877 but if they're in the same section we can subtract the section
3878 offset relocation which ends up in a resolved value. So if @.L2 is
3879 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3880 .text + 0x40 = 0x10. */
3882 arc_pcrel_adjust (fragS
*fragP
)
3884 if (!fragP
->tc_frag_data
.pcrel
)
3885 return fragP
->fr_address
+ fragP
->fr_fix
;
3890 /* Initialize the DWARF-2 unwind information for this procedure. */
3893 tc_arc_frame_initial_instructions (void)
3895 /* Stack pointer is register 28. */
3896 cfi_add_CFA_def_cfa_register (28);
3900 tc_arc_regname_to_dw2regnum (char *regname
)
3904 sym
= hash_find (arc_reg_hash
, regname
);
3906 return S_GET_VALUE (sym
);
3911 /* Adjust the symbol table. Delete found AUX register symbols. */
3914 arc_adjust_symtab (void)
3918 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3920 /* I've created a symbol during parsing process. Now, remove
3921 the symbol as it is found to be an AUX register. */
3922 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
3923 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
3926 /* Now do generic ELF adjustments. */
3927 elf_adjust_symtab ();
3931 tokenize_extinsn (extInstruction_t
*einsn
)
3935 unsigned char major_opcode
;
3936 unsigned char sub_opcode
;
3937 unsigned char syntax_class
= 0;
3938 unsigned char syntax_class_modifiers
= 0;
3939 unsigned char suffix_class
= 0;
3944 /* 1st: get instruction name. */
3945 p
= input_line_pointer
;
3946 c
= get_symbol_name (&p
);
3948 insn_name
= xstrdup (p
);
3949 restore_line_pointer (c
);
3951 /* 2nd: get major opcode. */
3952 if (*input_line_pointer
!= ',')
3954 as_bad (_("expected comma after instruction name"));
3955 ignore_rest_of_line ();
3958 input_line_pointer
++;
3959 major_opcode
= get_absolute_expression ();
3961 /* 3rd: get sub-opcode. */
3964 if (*input_line_pointer
!= ',')
3966 as_bad (_("expected comma after major opcode"));
3967 ignore_rest_of_line ();
3970 input_line_pointer
++;
3971 sub_opcode
= get_absolute_expression ();
3973 /* 4th: get suffix class. */
3976 if (*input_line_pointer
!= ',')
3978 as_bad ("expected comma after sub opcode");
3979 ignore_rest_of_line ();
3982 input_line_pointer
++;
3988 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
3990 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
3991 suffixclass
[i
].len
))
3993 suffix_class
|= suffixclass
[i
].class;
3994 input_line_pointer
+= suffixclass
[i
].len
;
3999 if (i
== ARRAY_SIZE (suffixclass
))
4001 as_bad ("invalid suffix class");
4002 ignore_rest_of_line ();
4008 if (*input_line_pointer
== '|')
4009 input_line_pointer
++;
4014 /* 5th: get syntax class and syntax class modifiers. */
4015 if (*input_line_pointer
!= ',')
4017 as_bad ("expected comma after suffix class");
4018 ignore_rest_of_line ();
4021 input_line_pointer
++;
4027 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4029 if (!strncmp (syntaxclassmod
[i
].name
,
4031 syntaxclassmod
[i
].len
))
4033 syntax_class_modifiers
|= syntaxclassmod
[i
].class;
4034 input_line_pointer
+= syntaxclassmod
[i
].len
;
4039 if (i
== ARRAY_SIZE (syntaxclassmod
))
4041 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4043 if (!strncmp (syntaxclass
[i
].name
,
4045 syntaxclass
[i
].len
))
4047 syntax_class
|= syntaxclass
[i
].class;
4048 input_line_pointer
+= syntaxclass
[i
].len
;
4053 if (i
== ARRAY_SIZE (syntaxclass
))
4055 as_bad ("missing syntax class");
4056 ignore_rest_of_line ();
4063 if (*input_line_pointer
== '|')
4064 input_line_pointer
++;
4069 demand_empty_rest_of_line ();
4071 einsn
->name
= insn_name
;
4072 einsn
->major
= major_opcode
;
4073 einsn
->minor
= sub_opcode
;
4074 einsn
->syntax
= syntax_class
;
4075 einsn
->modsyn
= syntax_class_modifiers
;
4076 einsn
->suffix
= suffix_class
;
4077 einsn
->flags
= syntax_class
4078 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4081 /* Generate an extension section. */
4084 arc_set_ext_seg (void)
4086 if (!arcext_section
)
4088 arcext_section
= subseg_new (".arcextmap", 0);
4089 bfd_set_section_flags (stdoutput
, arcext_section
,
4090 SEC_READONLY
| SEC_HAS_CONTENTS
);
4093 subseg_set (arcext_section
, 0);
4097 /* Create an extension instruction description in the arc extension
4098 section of the output file.
4099 The structure for an instruction is like this:
4100 [0]: Length of the record.
4101 [1]: Type of the record.
4105 [4]: Syntax (flags).
4106 [5]+ Name instruction.
4108 The sequence is terminated by an empty entry. */
4111 create_extinst_section (extInstruction_t
*einsn
)
4114 segT old_sec
= now_seg
;
4115 int old_subsec
= now_subseg
;
4117 int name_len
= strlen (einsn
->name
);
4122 *p
= 5 + name_len
+ 1;
4124 *p
= EXT_INSTRUCTION
;
4131 p
= frag_more (name_len
+ 1);
4132 strcpy (p
, einsn
->name
);
4134 subseg_set (old_sec
, old_subsec
);
4137 /* Handler .extinstruction pseudo-op. */
4140 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4142 extInstruction_t einsn
;
4143 struct arc_opcode
*arc_ext_opcodes
;
4144 const char *errmsg
= NULL
;
4145 unsigned char moplow
, mophigh
;
4147 memset (&einsn
, 0, sizeof (einsn
));
4148 tokenize_extinsn (&einsn
);
4150 /* Check if the name is already used. */
4151 if (arc_find_opcode (einsn
.name
))
4152 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4154 /* Check the opcode ranges. */
4156 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4157 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4159 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4160 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4162 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4163 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4164 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4166 switch (einsn
.syntax
& (ARC_SYNTAX_3OP
| ARC_SYNTAX_2OP
))
4168 case ARC_SYNTAX_3OP
:
4169 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4170 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4172 case ARC_SYNTAX_2OP
:
4173 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4174 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4180 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4181 if (arc_ext_opcodes
== NULL
)
4184 as_fatal ("%s", errmsg
);
4186 as_fatal (_("Couldn't generate extension instruction opcodes"));
4189 as_warn ("%s", errmsg
);
4191 /* Insert the extension instruction. */
4192 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4194 create_extinst_section (&einsn
);
4198 eval: (c-set-style "gnu")