1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
31 #include "opcode/arc-attrs.h"
33 #include "../opcodes/arc-ext.h"
35 /* Defines section. */
37 #define MAX_INSN_FIXUPS 2
38 #define MAX_CONSTR_STR 20
39 #define FRAG_MAX_GROWTH 8
42 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
44 # define pr_debug(fmt, args...)
47 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
49 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
52 /* Equal to MAX_PRECISION in atof-ieee.c. */
53 #define MAX_LITTLENUMS 6
55 #ifndef TARGET_WITH_CPU
56 #define TARGET_WITH_CPU "arc700"
57 #endif /* TARGET_WITH_CPU */
59 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61 #define streq(a, b) (strcmp (a, b) == 0)
63 /* Enum used to enumerate the relaxable ins operands. */
68 REGISTER_S
, /* Register for short instruction(s). */
69 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
70 REGISTER_DUP
, /* Duplication of previous operand of type register. */
102 /* Macros section. */
104 #define regno(x) ((x) & 0x3F)
105 #define is_ir_num(x) (((x) & ~0x3F) == 0)
106 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107 #define is_spfp_p(op) (((sc) == SPX))
108 #define is_dpfp_p(op) (((sc) == DPX))
109 #define is_fpuda_p(op) (((sc) == DPA))
110 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP \
112 || (op)->insn_class == BRCC \
113 || (op)->insn_class == BBIT0 \
114 || (op)->insn_class == BBIT1 \
115 || (op)->insn_class == BI \
116 || (op)->insn_class == EI \
117 || (op)->insn_class == ENTER \
118 || (op)->insn_class == JLI \
119 || (op)->insn_class == LOOP \
120 || (op)->insn_class == LEAVE \
122 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
123 #define is_nps400_p(op) (((sc) == NPS400))
125 /* Generic assembler global variables which must be defined by all
128 /* Characters which always start a comment. */
129 const char comment_chars
[] = "#;";
131 /* Characters which start a comment at the beginning of a line. */
132 const char line_comment_chars
[] = "#";
134 /* Characters which may be used to separate multiple commands on a
136 const char line_separator_chars
[] = "`";
138 /* Characters which are used to indicate an exponent in a floating
140 const char EXP_CHARS
[] = "eE";
142 /* Chars that mean this number is a floating point constant
143 As in 0f12.456 or 0d1.2345e12. */
144 const char FLT_CHARS
[] = "rRsSfFdD";
147 extern int target_big_endian
;
148 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
149 static int byte_order
= DEFAULT_BYTE_ORDER
;
151 /* Arc extension section. */
152 static segT arcext_section
;
154 /* By default relaxation is disabled. */
155 static int relaxation_state
= 0;
157 extern int arc_get_mach (char *);
159 /* Forward declarations. */
160 static void arc_lcomm (int);
161 static void arc_option (int);
162 static void arc_extra_reloc (int);
163 static void arc_extinsn (int);
164 static void arc_extcorereg (int);
165 static void arc_attribute (int);
167 const pseudo_typeS md_pseudo_table
[] =
169 /* Make sure that .word is 32 bits. */
172 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
173 { "lcomm", arc_lcomm
, 0 },
174 { "lcommon", arc_lcomm
, 0 },
175 { "cpu", arc_option
, 0 },
177 { "arc_attribute", arc_attribute
, 0 },
178 { "extinstruction", arc_extinsn
, 0 },
179 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
180 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
181 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
183 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
184 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
189 const char *md_shortopts
= "";
193 OPTION_EB
= OPTION_MD_BASE
,
211 /* The following options are deprecated and provided here only for
212 compatibility reasons. */
235 struct option md_longopts
[] =
237 { "EB", no_argument
, NULL
, OPTION_EB
},
238 { "EL", no_argument
, NULL
, OPTION_EL
},
239 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
240 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
241 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
242 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
243 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
244 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
245 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
246 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
247 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
248 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
249 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
251 /* Floating point options */
252 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
253 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
254 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
255 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
256 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
257 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
258 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
259 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
260 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
261 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
262 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
264 /* The following options are deprecated and provided here only for
265 compatibility reasons. */
266 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
267 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
268 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
269 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
270 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
271 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
272 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
273 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
274 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
275 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
276 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
277 { "mea", no_argument
, NULL
, OPTION_EA
},
278 { "mEA", no_argument
, NULL
, OPTION_EA
},
279 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
280 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
281 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
282 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
283 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
284 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
285 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
286 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
287 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
288 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
289 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
290 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
291 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
292 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
293 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
295 { NULL
, no_argument
, NULL
, 0 }
298 size_t md_longopts_size
= sizeof (md_longopts
);
300 /* Local data and data types. */
302 /* Used since new relocation types are introduced in this
303 file (DUMMY_RELOC_LITUSE_*). */
304 typedef int extended_bfd_reloc_code_real_type
;
310 extended_bfd_reloc_code_real_type reloc
;
312 /* index into arc_operands. */
313 unsigned int opindex
;
315 /* PC-relative, used by internals fixups. */
318 /* TRUE if this fixup is for LIMM operand. */
324 unsigned long long int insn
;
326 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
328 unsigned int len
; /* Length of instruction in bytes. */
329 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
331 bfd_boolean relax
; /* Boolean value: TRUE if needs
335 /* Structure to hold any last two instructions. */
336 static struct arc_last_insn
338 /* Saved instruction opcode. */
339 const struct arc_opcode
*opcode
;
341 /* Boolean value: TRUE if current insn is short. */
342 bfd_boolean has_limm
;
344 /* Boolean value: TRUE if current insn has delay slot. */
345 bfd_boolean has_delay_slot
;
348 /* Extension instruction suffix classes. */
356 static const attributes_t suffixclass
[] =
358 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
359 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
360 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
363 /* Extension instruction syntax classes. */
364 static const attributes_t syntaxclass
[] =
366 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
367 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
368 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
369 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
372 /* Extension instruction syntax classes modifiers. */
373 static const attributes_t syntaxclassmod
[] =
375 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
376 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
379 /* Extension register type. */
387 /* A structure to hold the additional conditional codes. */
390 struct arc_flag_operand
*arc_ext_condcode
;
392 } ext_condcode
= { NULL
, 0 };
394 /* Structure to hold an entry in ARC_OPCODE_HASH. */
395 struct arc_opcode_hash_entry
397 /* The number of pointers in the OPCODE list. */
400 /* Points to a list of opcode pointers. */
401 const struct arc_opcode
**opcode
;
404 /* Structure used for iterating through an arc_opcode_hash_entry. */
405 struct arc_opcode_hash_entry_iterator
407 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
410 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
411 returned by this iterator. */
412 const struct arc_opcode
*opcode
;
415 /* Forward declaration. */
416 static void assemble_insn
417 (const struct arc_opcode
*, const expressionS
*, int,
418 const struct arc_flags
*, int, struct arc_insn
*);
420 /* The selection of the machine type can come from different sources. This
421 enum is used to track how the selection was made in order to perform
423 enum mach_selection_type
426 MACH_SELECTION_FROM_DEFAULT
,
427 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
428 MACH_SELECTION_FROM_COMMAND_LINE
431 /* How the current machine type was selected. */
432 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
434 /* The hash table of instruction opcodes. */
435 static struct hash_control
*arc_opcode_hash
;
437 /* The hash table of register symbols. */
438 static struct hash_control
*arc_reg_hash
;
440 /* The hash table of aux register symbols. */
441 static struct hash_control
*arc_aux_hash
;
443 /* The hash table of address types. */
444 static struct hash_control
*arc_addrtype_hash
;
446 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
448 E_ARC_MACH_ARC600, EXTRA}
449 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
451 E_ARC_MACH_ARC700, EXTRA}
452 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
453 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
454 EF_ARC_CPU_ARCV2EM, EXTRA}
455 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
456 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
457 EF_ARC_CPU_ARCV2HS, EXTRA}
458 #define ARC_CPU_TYPE_NONE \
461 /* A table of CPU names and opcode sets. */
462 static const struct cpu_type
472 #include "elf/arc-cpu.def"
475 /* Information about the cpu/variant we're assembling for. */
476 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
479 static unsigned mpy_option
= 0;
482 static unsigned pic_option
= 0;
484 /* Use small data. */
485 static unsigned sda_option
= 0;
488 static unsigned tls_option
= 0;
490 /* Command line given features. */
491 static unsigned cl_features
= 0;
493 /* Used by the arc_reloc_op table. Order is important. */
494 #define O_gotoff O_md1 /* @gotoff relocation. */
495 #define O_gotpc O_md2 /* @gotpc relocation. */
496 #define O_plt O_md3 /* @plt relocation. */
497 #define O_sda O_md4 /* @sda relocation. */
498 #define O_pcl O_md5 /* @pcl relocation. */
499 #define O_tlsgd O_md6 /* @tlsgd relocation. */
500 #define O_tlsie O_md7 /* @tlsie relocation. */
501 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
502 #define O_tpoff O_md9 /* @tpoff relocation. */
503 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
504 #define O_dtpoff O_md11 /* @dtpoff relocation. */
505 #define O_last O_dtpoff
507 /* Used to define a bracket as operand in tokens. */
508 #define O_bracket O_md32
510 /* Used to define a colon as an operand in tokens. */
511 #define O_colon O_md31
513 /* Used to define address types in nps400. */
514 #define O_addrtype O_md30
516 /* Dummy relocation, to be sorted out. */
517 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
519 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
521 /* A table to map the spelling of a relocation operand into an appropriate
522 bfd_reloc_code_real_type type. The table is assumed to be ordered such
523 that op-O_literal indexes into it. */
524 #define ARC_RELOC_TABLE(op) \
525 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
527 : (int) (op) - (int) O_gotoff) ])
529 #define DEF(NAME, RELOC, REQ) \
530 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
532 static const struct arc_reloc_op_tag
534 /* String to lookup. */
536 /* Size of the string. */
538 /* Which operator to use. */
540 extended_bfd_reloc_code_real_type reloc
;
541 /* Allows complex relocation expression like identifier@reloc +
543 unsigned int complex_expr
: 1;
547 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
548 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
549 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
550 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
551 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
552 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
553 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
554 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
555 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
556 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
557 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
560 static const int arc_num_reloc_op
561 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
563 /* Structure for relaxable instruction that have to be swapped with a
564 smaller alternative instruction. */
565 struct arc_relaxable_ins
567 /* Mnemonic that should be checked. */
568 const char *mnemonic_r
;
570 /* Operands that should be checked.
571 Indexes of operands from operand array. */
572 enum rlx_operand_type operands
[6];
574 /* Flags that should be checked. */
575 unsigned flag_classes
[5];
577 /* Mnemonic (smaller) alternative to be used later for relaxation. */
578 const char *mnemonic_alt
;
580 /* Index of operand that generic relaxation has to check. */
583 /* Base subtype index used. */
584 enum arc_rlx_types subtype
;
587 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
588 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
589 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
593 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
594 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
595 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
600 /* ARC relaxation table. */
601 const relax_typeS md_relax_table
[] =
608 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
609 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
613 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
614 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
619 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
620 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
621 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
623 /* LD_S a, [b, u7] ->
624 LD<zz><.x><.aa><.di> a, [b, s9] ->
625 LD<zz><.x><.aa><.di> a, [b, limm] */
626 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
627 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
628 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
633 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
634 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
635 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
639 SUB<.f> a, b, limm. */
640 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
641 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
642 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
644 /* MPY<.f> a, b, u6 ->
645 MPY<.f> a, b, limm. */
646 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
647 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
649 /* MOV<.f><.cc> b, u6 ->
650 MOV<.f><.cc> b, limm. */
651 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
652 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
654 /* ADD<.f><.cc> b, b, u6 ->
655 ADD<.f><.cc> b, b, limm. */
656 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
657 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
660 /* Order of this table's entries matters! */
661 const struct arc_relaxable_ins arc_relaxable_insns
[] =
663 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
664 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
665 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
666 2, ARC_RLX_ADD_RRU6
},
667 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
669 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
671 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
672 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
673 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
674 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
675 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
676 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
677 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
678 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
680 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
682 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
686 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
688 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
689 symbolS
* GOT_symbol
= 0;
691 /* Set to TRUE when we assemble instructions. */
692 static bfd_boolean assembling_insn
= FALSE
;
694 /* List with attributes set explicitly. */
695 static bfd_boolean attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
697 /* Functions implementation. */
699 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
700 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
701 are no matching entries in ARC_OPCODE_HASH. */
703 static const struct arc_opcode_hash_entry
*
704 arc_find_opcode (const char *name
)
706 const struct arc_opcode_hash_entry
*entry
;
708 entry
= hash_find (arc_opcode_hash
, name
);
712 /* Initialise the iterator ITER. */
715 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
721 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
722 calls to this function. Return NULL when all ARC_OPCODE entries have
725 static const struct arc_opcode
*
726 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
727 struct arc_opcode_hash_entry_iterator
*iter
)
729 if (iter
->opcode
== NULL
&& iter
->index
== 0)
731 gas_assert (entry
->count
> 0);
732 iter
->opcode
= entry
->opcode
[iter
->index
];
734 else if (iter
->opcode
!= NULL
)
736 const char *old_name
= iter
->opcode
->name
;
739 if (iter
->opcode
->name
== NULL
740 || strcmp (old_name
, iter
->opcode
->name
) != 0)
743 if (iter
->index
== entry
->count
)
746 iter
->opcode
= entry
->opcode
[iter
->index
];
753 /* Insert an opcode into opcode hash structure. */
756 arc_insert_opcode (const struct arc_opcode
*opcode
)
758 const char *name
, *retval
;
759 struct arc_opcode_hash_entry
*entry
;
762 entry
= hash_find (arc_opcode_hash
, name
);
765 entry
= XNEW (struct arc_opcode_hash_entry
);
767 entry
->opcode
= NULL
;
769 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
771 as_fatal (_("internal error: can't hash opcode '%s': %s"),
775 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
778 if (entry
->opcode
== NULL
)
779 as_fatal (_("Virtual memory exhausted"));
781 entry
->opcode
[entry
->count
] = opcode
;
786 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
787 value, is encoded as 'middle-endian' for a little-endian target. This
788 function is used for regular 4, 6, and 8 byte instructions as well. */
791 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
796 md_number_to_chars (buf
, val
, n
);
799 md_number_to_chars (buf
, (val
& 0xffff00000000) >> 32, 2);
800 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
803 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
804 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
807 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000) >> 32, 4);
808 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
815 /* Check if a feature is allowed for a specific CPU. */
818 arc_check_feature (void)
822 if (!selected_cpu
.features
823 || !selected_cpu
.name
)
826 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
827 if ((selected_cpu
.features
& feature_list
[i
].feature
)
828 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
829 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
832 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
833 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
834 as_bad(_("conflicting ISA extension attributes."));
837 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
838 the relevant static global variables. Parameter SEL describes where
839 this selection originated from. */
842 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
846 /* We should only set a default if we've not made a selection from some
848 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
849 || mach_selection_mode
== MACH_SELECTION_NONE
);
851 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
852 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
853 as_bad (_("Multiple .cpu directives found"));
855 /* Look for a matching entry in CPU_TYPES array. */
856 for (i
= 0; cpu_types
[i
].name
; ++i
)
858 if (!strcasecmp (cpu_types
[i
].name
, arg
))
860 /* If a previous selection was made on the command line, then we
861 allow later selections on the command line to override earlier
862 ones. However, a selection from a '.cpu NAME' directive must
863 match the command line selection, or we give a warning. */
864 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
866 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
867 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
868 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
869 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
871 as_warn (_("Command-line value overrides \".cpu\" directive"));
876 /* Initialise static global data about selected machine type. */
877 selected_cpu
.flags
= cpu_types
[i
].flags
;
878 selected_cpu
.name
= cpu_types
[i
].name
;
879 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
880 selected_cpu
.mach
= cpu_types
[i
].mach
;
881 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
882 | cpu_types
[i
].eflags
);
887 if (!cpu_types
[i
].name
)
888 as_fatal (_("unknown architecture: %s\n"), arg
);
890 /* Check if set features are compatible with the chosen CPU. */
891 arc_check_feature ();
893 mach_selection_mode
= sel
;
896 /* Here ends all the ARCompact extension instruction assembling
900 arc_extra_reloc (int r_type
)
903 symbolS
*sym
, *lab
= NULL
;
905 if (*input_line_pointer
== '@')
906 input_line_pointer
++;
907 c
= get_symbol_name (&sym_name
);
908 sym
= symbol_find_or_make (sym_name
);
909 restore_line_pointer (c
);
910 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
912 ++input_line_pointer
;
914 c
= get_symbol_name (&lab_name
);
915 lab
= symbol_find_or_make (lab_name
);
916 restore_line_pointer (c
);
919 /* These relocations exist as a mechanism for the compiler to tell the
920 linker how to patch the code if the tls model is optimised. However,
921 the relocation itself does not require any space within the assembler
922 fragment, and so we pass a size of 0.
924 The lines that generate these relocations look like this:
926 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
928 The '.tls_gd_ld @.tdata' is processed first and generates the
929 additional relocation, while the 'bl __tls_get_addr@plt' is processed
930 second and generates the additional branch.
932 It is possible that the additional relocation generated by the
933 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
934 while the 'bl __tls_get_addr@plt' will be generated as the first thing
935 in the next fragment. This will be fine; both relocations will still
936 appear to be at the same address in the generated object file.
937 However, this only works as the additional relocation is generated
938 with size of 0 bytes. */
940 = fix_new (frag_now
, /* Which frag? */
941 frag_now_fix (), /* Where in that frag? */
942 0, /* size: 1, 2, or 4 usually. */
943 sym
, /* X_add_symbol. */
944 0, /* X_add_number. */
945 FALSE
, /* TRUE if PC-relative relocation. */
946 r_type
/* Relocation type. */);
947 fixP
->fx_subsy
= lab
;
951 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
952 symbolS
*symbolP
, addressT size
)
957 if (*input_line_pointer
== ',')
959 align
= parse_align (1);
961 if (align
== (addressT
) -1)
976 bss_alloc (symbolP
, size
, align
);
977 S_CLEAR_EXTERNAL (symbolP
);
983 arc_lcomm (int ignore
)
985 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
988 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
991 /* Select the cpu we're assembling for. */
994 arc_option (int ignore ATTRIBUTE_UNUSED
)
998 const char *cpu_name
;
1000 c
= get_symbol_name (&cpu
);
1003 if ((!strcmp ("ARC600", cpu
))
1004 || (!strcmp ("ARC601", cpu
))
1005 || (!strcmp ("A6", cpu
)))
1006 cpu_name
= "arc600";
1007 else if ((!strcmp ("ARC700", cpu
))
1008 || (!strcmp ("A7", cpu
)))
1009 cpu_name
= "arc700";
1010 else if (!strcmp ("EM", cpu
))
1012 else if (!strcmp ("HS", cpu
))
1014 else if (!strcmp ("NPS400", cpu
))
1015 cpu_name
= "nps400";
1017 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1019 restore_line_pointer (c
);
1020 demand_empty_rest_of_line ();
1023 /* Smartly print an expression. */
1026 debug_exp (expressionS
*t
)
1028 const char *name ATTRIBUTE_UNUSED
;
1029 const char *namemd ATTRIBUTE_UNUSED
;
1031 pr_debug ("debug_exp: ");
1035 default: name
= "unknown"; break;
1036 case O_illegal
: name
= "O_illegal"; break;
1037 case O_absent
: name
= "O_absent"; break;
1038 case O_constant
: name
= "O_constant"; break;
1039 case O_symbol
: name
= "O_symbol"; break;
1040 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1041 case O_register
: name
= "O_register"; break;
1042 case O_big
: name
= "O_big"; break;
1043 case O_uminus
: name
= "O_uminus"; break;
1044 case O_bit_not
: name
= "O_bit_not"; break;
1045 case O_logical_not
: name
= "O_logical_not"; break;
1046 case O_multiply
: name
= "O_multiply"; break;
1047 case O_divide
: name
= "O_divide"; break;
1048 case O_modulus
: name
= "O_modulus"; break;
1049 case O_left_shift
: name
= "O_left_shift"; break;
1050 case O_right_shift
: name
= "O_right_shift"; break;
1051 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1052 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1053 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1054 case O_bit_and
: name
= "O_bit_and"; break;
1055 case O_add
: name
= "O_add"; break;
1056 case O_subtract
: name
= "O_subtract"; break;
1057 case O_eq
: name
= "O_eq"; break;
1058 case O_ne
: name
= "O_ne"; break;
1059 case O_lt
: name
= "O_lt"; break;
1060 case O_le
: name
= "O_le"; break;
1061 case O_ge
: name
= "O_ge"; break;
1062 case O_gt
: name
= "O_gt"; break;
1063 case O_logical_and
: name
= "O_logical_and"; break;
1064 case O_logical_or
: name
= "O_logical_or"; break;
1065 case O_index
: name
= "O_index"; break;
1066 case O_bracket
: name
= "O_bracket"; break;
1067 case O_colon
: name
= "O_colon"; break;
1068 case O_addrtype
: name
= "O_addrtype"; break;
1073 default: namemd
= "unknown"; break;
1074 case O_gotoff
: namemd
= "O_gotoff"; break;
1075 case O_gotpc
: namemd
= "O_gotpc"; break;
1076 case O_plt
: namemd
= "O_plt"; break;
1077 case O_sda
: namemd
= "O_sda"; break;
1078 case O_pcl
: namemd
= "O_pcl"; break;
1079 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1080 case O_tlsie
: namemd
= "O_tlsie"; break;
1081 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1082 case O_tpoff
: namemd
= "O_tpoff"; break;
1083 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1084 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1087 pr_debug ("%s (%s, %s, %d, %s)", name
,
1088 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1089 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1090 (int) t
->X_add_number
,
1091 (t
->X_md
) ? namemd
: "--");
1096 /* Parse the arguments to an opcode. */
1099 tokenize_arguments (char *str
,
1103 char *old_input_line_pointer
;
1104 bfd_boolean saw_comma
= FALSE
;
1105 bfd_boolean saw_arg
= FALSE
;
1110 const struct arc_reloc_op_tag
*r
;
1112 char *reloc_name
, c
;
1114 memset (tok
, 0, sizeof (*tok
) * ntok
);
1116 /* Save and restore input_line_pointer around this function. */
1117 old_input_line_pointer
= input_line_pointer
;
1118 input_line_pointer
= str
;
1120 while (*input_line_pointer
)
1123 switch (*input_line_pointer
)
1129 input_line_pointer
++;
1130 if (saw_comma
|| !saw_arg
)
1137 ++input_line_pointer
;
1139 if (!saw_arg
|| num_args
== ntok
)
1141 tok
->X_op
= O_bracket
;
1148 input_line_pointer
++;
1149 if (brk_lvl
|| num_args
== ntok
)
1152 tok
->X_op
= O_bracket
;
1158 input_line_pointer
++;
1159 if (!saw_arg
|| num_args
== ntok
)
1161 tok
->X_op
= O_colon
;
1168 /* We have labels, function names and relocations, all
1169 starting with @ symbol. Sort them out. */
1170 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1174 tok
->X_op
= O_symbol
;
1175 tok
->X_md
= O_absent
;
1177 if (*input_line_pointer
!= '@')
1178 goto normalsymbol
; /* This is not a relocation. */
1182 /* A relocation operand has the following form
1183 @identifier@relocation_type. The identifier is already
1185 if (tok
->X_op
!= O_symbol
)
1187 as_bad (_("No valid label relocation operand"));
1191 /* Parse @relocation_type. */
1192 input_line_pointer
++;
1193 c
= get_symbol_name (&reloc_name
);
1194 len
= input_line_pointer
- reloc_name
;
1197 as_bad (_("No relocation operand"));
1201 /* Go through known relocation and try to find a match. */
1202 r
= &arc_reloc_op
[0];
1203 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1204 if (len
== r
->length
1205 && memcmp (reloc_name
, r
->name
, len
) == 0)
1209 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1213 *input_line_pointer
= c
;
1214 SKIP_WHITESPACE_AFTER_NAME ();
1215 /* Extra check for TLS: base. */
1216 if (*input_line_pointer
== '@')
1219 if (tok
->X_op_symbol
!= NULL
1220 || tok
->X_op
!= O_symbol
)
1222 as_bad (_("Unable to parse TLS base: %s"),
1223 input_line_pointer
);
1226 input_line_pointer
++;
1228 c
= get_symbol_name (&sym_name
);
1229 base
= symbol_find_or_make (sym_name
);
1230 tok
->X_op
= O_subtract
;
1231 tok
->X_op_symbol
= base
;
1232 restore_line_pointer (c
);
1233 tmpE
.X_add_number
= 0;
1235 if ((*input_line_pointer
!= '+')
1236 && (*input_line_pointer
!= '-'))
1238 tmpE
.X_add_number
= 0;
1242 /* Parse the constant of a complex relocation expression
1243 like @identifier@reloc +/- const. */
1244 if (! r
->complex_expr
)
1246 as_bad (_("@%s is not a complex relocation."), r
->name
);
1250 if (tmpE
.X_op
!= O_constant
)
1252 as_bad (_("Bad expression: @%s + %s."),
1253 r
->name
, input_line_pointer
);
1259 tok
->X_add_number
= tmpE
.X_add_number
;
1270 /* Can be a register. */
1271 ++input_line_pointer
;
1275 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1278 tok
->X_op
= O_absent
;
1279 tok
->X_md
= O_absent
;
1282 /* Legacy: There are cases when we have
1283 identifier@relocation_type, if it is the case parse the
1284 relocation type as well. */
1285 if (*input_line_pointer
== '@')
1291 if (tok
->X_op
== O_illegal
1292 || tok
->X_op
== O_absent
1293 || num_args
== ntok
)
1305 if (saw_comma
|| brk_lvl
)
1307 input_line_pointer
= old_input_line_pointer
;
1313 as_bad (_("Brackets in operand field incorrect"));
1315 as_bad (_("extra comma"));
1317 as_bad (_("missing argument"));
1319 as_bad (_("missing comma or colon"));
1320 input_line_pointer
= old_input_line_pointer
;
1324 /* Parse the flags to a structure. */
1327 tokenize_flags (const char *str
,
1328 struct arc_flags flags
[],
1331 char *old_input_line_pointer
;
1332 bfd_boolean saw_flg
= FALSE
;
1333 bfd_boolean saw_dot
= FALSE
;
1337 memset (flags
, 0, sizeof (*flags
) * nflg
);
1339 /* Save and restore input_line_pointer around this function. */
1340 old_input_line_pointer
= input_line_pointer
;
1341 input_line_pointer
= (char *) str
;
1343 while (*input_line_pointer
)
1345 switch (*input_line_pointer
)
1352 input_line_pointer
++;
1360 if (saw_flg
&& !saw_dot
)
1363 if (num_flags
>= nflg
)
1366 flgnamelen
= strspn (input_line_pointer
,
1367 "abcdefghijklmnopqrstuvwxyz0123456789");
1368 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1371 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1373 input_line_pointer
+= flgnamelen
;
1383 input_line_pointer
= old_input_line_pointer
;
1388 as_bad (_("extra dot"));
1390 as_bad (_("unrecognized flag"));
1392 as_bad (_("failed to parse flags"));
1393 input_line_pointer
= old_input_line_pointer
;
1397 /* Apply the fixups in order. */
1400 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1404 for (i
= 0; i
< insn
->nfixups
; i
++)
1406 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1407 int size
, pcrel
, offset
= 0;
1409 /* FIXME! the reloc size is wrong in the BFD file.
1410 When it is fixed please delete me. */
1411 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1416 /* Some fixups are only used internally, thus no howto. */
1417 if ((int) fixup
->reloc
== 0)
1418 as_fatal (_("Unhandled reloc type"));
1420 if ((int) fixup
->reloc
< 0)
1422 /* FIXME! the reloc size is wrong in the BFD file.
1423 When it is fixed please enable me.
1424 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1425 pcrel
= fixup
->pcrel
;
1429 reloc_howto_type
*reloc_howto
=
1430 bfd_reloc_type_lookup (stdoutput
,
1431 (bfd_reloc_code_real_type
) fixup
->reloc
);
1432 gas_assert (reloc_howto
);
1434 /* FIXME! the reloc size is wrong in the BFD file.
1435 When it is fixed please enable me.
1436 size = bfd_get_reloc_size (reloc_howto); */
1437 pcrel
= reloc_howto
->pc_relative
;
1440 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1442 fragP
->fr_file
, fragP
->fr_line
,
1443 (fixup
->reloc
< 0) ? "Internal" :
1444 bfd_get_reloc_code_name (fixup
->reloc
),
1447 fix_new_exp (fragP
, fix
+ offset
,
1448 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1450 /* Check for ZOLs, and update symbol info if any. */
1451 if (LP_INSN (insn
->insn
))
1453 gas_assert (fixup
->exp
.X_add_symbol
);
1454 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1459 /* Actually output an instruction with its fixup. */
1462 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1467 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1468 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1469 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1471 /* Write out the instruction. */
1472 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1474 f
= frag_more (total_len
);
1476 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1479 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1480 dwarf2_emit_insn (total_len
);
1483 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1487 emit_insn1 (struct arc_insn
*insn
)
1489 /* How frag_var's args are currently configured:
1490 - rs_machine_dependent, to dictate it's a relaxation frag.
1491 - FRAG_MAX_GROWTH, maximum size of instruction
1492 - 0, variable size that might grow...unused by generic relaxation.
1493 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1494 - s, opand expression.
1495 - 0, offset but it's unused.
1496 - 0, opcode but it's unused. */
1497 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1498 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1500 if (frag_room () < FRAG_MAX_GROWTH
)
1502 /* Handle differently when frag literal memory is exhausted.
1503 This is used because when there's not enough memory left in
1504 the current frag, a new frag is created and the information
1505 we put into frag_now->tc_frag_data is disregarded. */
1507 struct arc_relax_type relax_info_copy
;
1508 relax_substateT subtype
= frag_now
->fr_subtype
;
1510 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1511 sizeof (struct arc_relax_type
));
1513 frag_wane (frag_now
);
1514 frag_grow (FRAG_MAX_GROWTH
);
1516 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1517 sizeof (struct arc_relax_type
));
1519 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1523 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1524 frag_now
->fr_subtype
, s
, 0, 0);
1528 emit_insn (struct arc_insn
*insn
)
1533 emit_insn0 (insn
, NULL
, FALSE
);
1536 /* Check whether a symbol involves a register. */
1539 contains_register (symbolS
*sym
)
1543 expressionS
*ex
= symbol_get_value_expression (sym
);
1545 return ((O_register
== ex
->X_op
)
1546 && !contains_register (ex
->X_add_symbol
)
1547 && !contains_register (ex
->X_op_symbol
));
1553 /* Returns the register number within a symbol. */
1556 get_register (symbolS
*sym
)
1558 if (!contains_register (sym
))
1561 expressionS
*ex
= symbol_get_value_expression (sym
);
1562 return regno (ex
->X_add_number
);
1565 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1566 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1569 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1576 case BFD_RELOC_ARC_SDA_LDST
:
1577 case BFD_RELOC_ARC_SDA_LDST1
:
1578 case BFD_RELOC_ARC_SDA_LDST2
:
1579 case BFD_RELOC_ARC_SDA16_LD
:
1580 case BFD_RELOC_ARC_SDA16_LD1
:
1581 case BFD_RELOC_ARC_SDA16_LD2
:
1582 case BFD_RELOC_ARC_SDA16_ST2
:
1583 case BFD_RELOC_ARC_SDA32_ME
:
1590 /* Allocates a tok entry. */
1593 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1595 if (ntok
> MAX_INSN_ARGS
- 2)
1596 return 0; /* No space left. */
1599 return 0; /* Incorrect args. */
1601 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1604 return 1; /* Success. */
1605 return allocate_tok (tok
, ntok
- 1, cidx
);
1608 /* Check if an particular ARC feature is enabled. */
1611 check_cpu_feature (insn_subclass_t sc
)
1613 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1616 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1619 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1622 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1625 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1631 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1632 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1633 array and returns TRUE if the flag operands all match, otherwise,
1634 returns FALSE, in which case the FIRST_PFLAG array may have been
1638 parse_opcode_flags (const struct arc_opcode
*opcode
,
1640 struct arc_flags
*first_pflag
)
1643 const unsigned char *flgidx
;
1646 for (i
= 0; i
< nflgs
; i
++)
1647 first_pflag
[i
].flgp
= NULL
;
1649 /* Check the flags. Iterate over the valid flag classes. */
1650 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1652 /* Get a valid flag class. */
1653 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1654 const unsigned *flgopridx
;
1656 struct arc_flags
*pflag
= NULL
;
1658 /* Check if opcode has implicit flag classes. */
1659 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1662 /* Check for extension conditional codes. */
1663 if (ext_condcode
.arc_ext_condcode
1664 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1666 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1669 pflag
= first_pflag
;
1670 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1672 if (!strcmp (pf
->name
, pflag
->name
))
1674 if (pflag
->flgp
!= NULL
)
1687 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1689 const struct arc_flag_operand
*flg_operand
;
1691 pflag
= first_pflag
;
1692 flg_operand
= &arc_flag_operands
[*flgopridx
];
1693 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1695 /* Match against the parsed flags. */
1696 if (!strcmp (flg_operand
->name
, pflag
->name
))
1698 if (pflag
->flgp
!= NULL
)
1701 pflag
->flgp
= flg_operand
;
1703 break; /* goto next flag class and parsed flag. */
1708 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1710 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1714 /* Did I check all the parsed flags? */
1715 return lnflg
? FALSE
: TRUE
;
1719 /* Search forward through all variants of an opcode looking for a
1722 static const struct arc_opcode
*
1723 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1726 struct arc_flags
*first_pflag
,
1729 const char **errmsg
)
1731 const struct arc_opcode
*opcode
;
1732 struct arc_opcode_hash_entry_iterator iter
;
1734 int got_cpu_match
= 0;
1735 expressionS bktok
[MAX_INSN_ARGS
];
1739 arc_opcode_hash_entry_iterator_init (&iter
);
1740 memset (&emptyE
, 0, sizeof (emptyE
));
1741 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1744 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1746 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1748 const unsigned char *opidx
;
1750 const expressionS
*t
= &emptyE
;
1752 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1753 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1755 /* Don't match opcodes that don't exist on this
1757 if (!(opcode
->cpu
& selected_cpu
.flags
))
1760 if (!check_cpu_feature (opcode
->subclass
))
1766 /* Check the operands. */
1767 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1769 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1771 /* Only take input from real operands. */
1772 if (ARC_OPERAND_IS_FAKE (operand
))
1775 /* When we expect input, make sure we have it. */
1779 /* Match operand type with expression type. */
1780 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1782 case ARC_OPERAND_ADDRTYPE
:
1786 /* Check to be an address type. */
1787 if (tok
[tokidx
].X_op
!= O_addrtype
)
1790 /* All address type operands need to have an insert
1791 method in order to check that we have the correct
1793 gas_assert (operand
->insert
!= NULL
);
1794 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1796 if (*errmsg
!= NULL
)
1801 case ARC_OPERAND_IR
:
1802 /* Check to be a register. */
1803 if ((tok
[tokidx
].X_op
!= O_register
1804 || !is_ir_num (tok
[tokidx
].X_add_number
))
1805 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1808 /* If expect duplicate, make sure it is duplicate. */
1809 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1811 /* Check for duplicate. */
1812 if (t
->X_op
!= O_register
1813 || !is_ir_num (t
->X_add_number
)
1814 || (regno (t
->X_add_number
) !=
1815 regno (tok
[tokidx
].X_add_number
)))
1819 /* Special handling? */
1820 if (operand
->insert
)
1823 (*operand
->insert
)(0,
1824 regno (tok
[tokidx
].X_add_number
),
1828 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1830 /* Missing argument, create one. */
1831 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1834 tok
[tokidx
].X_op
= O_absent
;
1845 case ARC_OPERAND_BRAKET
:
1846 /* Check if bracket is also in opcode table as
1848 if (tok
[tokidx
].X_op
!= O_bracket
)
1852 case ARC_OPERAND_COLON
:
1853 /* Check if colon is also in opcode table as operand. */
1854 if (tok
[tokidx
].X_op
!= O_colon
)
1858 case ARC_OPERAND_LIMM
:
1859 case ARC_OPERAND_SIGNED
:
1860 case ARC_OPERAND_UNSIGNED
:
1861 switch (tok
[tokidx
].X_op
)
1869 /* Got an (too) early bracket, check if it is an
1870 ignored operand. N.B. This procedure works only
1871 when bracket is the last operand! */
1872 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1874 /* Insert the missing operand. */
1875 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1878 tok
[tokidx
].X_op
= O_absent
;
1885 const struct arc_aux_reg
*auxr
;
1887 if (opcode
->insn_class
!= AUXREG
)
1889 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1891 auxr
= hash_find (arc_aux_hash
, p
);
1894 /* We modify the token array here, safe in the
1895 knowledge, that if this was the wrong
1896 choice then the original contents will be
1897 restored from BKTOK. */
1898 tok
[tokidx
].X_op
= O_constant
;
1899 tok
[tokidx
].X_add_number
= auxr
->address
;
1900 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1903 if (tok
[tokidx
].X_op
!= O_constant
)
1908 /* Check the range. */
1909 if (operand
->bits
!= 32
1910 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1912 offsetT min
, max
, val
;
1913 val
= tok
[tokidx
].X_add_number
;
1915 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1917 max
= (1 << (operand
->bits
- 1)) - 1;
1918 min
= -(1 << (operand
->bits
- 1));
1922 max
= (1 << operand
->bits
) - 1;
1926 if (val
< min
|| val
> max
)
1929 /* Check alignments. */
1930 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1934 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1938 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1940 if (operand
->insert
)
1943 (*operand
->insert
)(0,
1944 tok
[tokidx
].X_add_number
,
1949 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1955 /* Check if it is register range. */
1956 if ((tok
[tokidx
].X_add_number
== 0)
1957 && contains_register (tok
[tokidx
].X_add_symbol
)
1958 && contains_register (tok
[tokidx
].X_op_symbol
))
1962 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1964 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1965 if (operand
->insert
)
1968 (*operand
->insert
)(0,
1981 if (operand
->default_reloc
== 0)
1982 goto match_failed
; /* The operand needs relocation. */
1984 /* Relocs requiring long immediate. FIXME! make it
1985 generic and move it to a function. */
1986 switch (tok
[tokidx
].X_md
)
1995 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1999 if (!generic_reloc_p (operand
->default_reloc
))
2007 /* If expect duplicate, make sure it is duplicate. */
2008 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2010 if (t
->X_op
== O_illegal
2011 || t
->X_op
== O_absent
2012 || t
->X_op
== O_register
2013 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2020 /* Everything else should have been fake. */
2028 /* Setup ready for flag parsing. */
2029 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2033 /* Possible match -- did we use all of our input? */
2043 /* Restore the original parameters. */
2044 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2049 *pcpumatch
= got_cpu_match
;
2054 /* Swap operand tokens. */
2057 swap_operand (expressionS
*operand_array
,
2059 unsigned destination
)
2061 expressionS cpy_operand
;
2062 expressionS
*src_operand
;
2063 expressionS
*dst_operand
;
2066 if (source
== destination
)
2069 src_operand
= &operand_array
[source
];
2070 dst_operand
= &operand_array
[destination
];
2071 size
= sizeof (expressionS
);
2073 /* Make copy of operand to swap with and swap. */
2074 memcpy (&cpy_operand
, dst_operand
, size
);
2075 memcpy (dst_operand
, src_operand
, size
);
2076 memcpy (src_operand
, &cpy_operand
, size
);
2079 /* Check if *op matches *tok type.
2080 Returns FALSE if they don't match, TRUE if they match. */
2083 pseudo_operand_match (const expressionS
*tok
,
2084 const struct arc_operand_operation
*op
)
2086 offsetT min
, max
, val
;
2088 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2094 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2096 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2098 val
= tok
->X_add_number
+ op
->count
;
2099 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2101 max
= (1 << (operand_real
->bits
- 1)) - 1;
2102 min
= -(1 << (operand_real
->bits
- 1));
2106 max
= (1 << operand_real
->bits
) - 1;
2109 if (min
<= val
&& val
<= max
)
2115 /* Handle all symbols as long immediates or signed 9. */
2116 if (operand_real
->flags
& ARC_OPERAND_LIMM
2117 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2118 && operand_real
->bits
== 9))
2123 if (operand_real
->flags
& ARC_OPERAND_IR
)
2128 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2139 /* Find pseudo instruction in array. */
2141 static const struct arc_pseudo_insn
*
2142 find_pseudo_insn (const char *opname
,
2144 const expressionS
*tok
)
2146 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2147 const struct arc_operand_operation
*op
;
2151 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2153 pseudo_insn
= &arc_pseudo_insns
[i
];
2154 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2156 op
= pseudo_insn
->operand
;
2157 for (j
= 0; j
< ntok
; ++j
)
2158 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2161 /* Found the right instruction. */
2169 /* Assumes the expressionS *tok is of sufficient size. */
2171 static const struct arc_opcode_hash_entry
*
2172 find_special_case_pseudo (const char *opname
,
2176 struct arc_flags
*pflags
)
2178 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2179 const struct arc_operand_operation
*operand_pseudo
;
2180 const struct arc_operand
*operand_real
;
2182 char construct_operand
[MAX_CONSTR_STR
];
2184 /* Find whether opname is in pseudo instruction array. */
2185 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2187 if (pseudo_insn
== NULL
)
2190 /* Handle flag, Limited to one flag at the moment. */
2191 if (pseudo_insn
->flag_r
!= NULL
)
2192 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2193 MAX_INSN_FLGS
- *nflgs
);
2195 /* Handle operand operations. */
2196 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2198 operand_pseudo
= &pseudo_insn
->operand
[i
];
2199 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2201 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2202 && !operand_pseudo
->needs_insert
)
2205 /* Has to be inserted (i.e. this token does not exist yet). */
2206 if (operand_pseudo
->needs_insert
)
2208 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2210 tok
[i
].X_op
= O_bracket
;
2215 /* Check if operand is a register or constant and handle it
2217 if (operand_real
->flags
& ARC_OPERAND_IR
)
2218 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2219 operand_pseudo
->count
);
2221 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2222 operand_pseudo
->count
);
2224 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2228 else if (operand_pseudo
->count
)
2230 /* Operand number has to be adjusted accordingly (by operand
2232 switch (tok
[i
].X_op
)
2235 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2248 /* Swap operands if necessary. Only supports one swap at the
2250 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2252 operand_pseudo
= &pseudo_insn
->operand
[i
];
2254 if (operand_pseudo
->swap_operand_idx
== i
)
2257 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2259 /* Prevent a swap back later by breaking out. */
2263 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2266 static const struct arc_opcode_hash_entry
*
2267 find_special_case_flag (const char *opname
,
2269 struct arc_flags
*pflags
)
2273 unsigned flag_idx
, flag_arr_idx
;
2274 size_t flaglen
, oplen
;
2275 const struct arc_flag_special
*arc_flag_special_opcode
;
2276 const struct arc_opcode_hash_entry
*entry
;
2278 /* Search for special case instruction. */
2279 for (i
= 0; i
< arc_num_flag_special
; i
++)
2281 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2282 oplen
= strlen (arc_flag_special_opcode
->name
);
2284 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2287 /* Found a potential special case instruction, now test for
2289 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2291 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2293 break; /* End of array, nothing found. */
2295 flagnm
= arc_flag_operands
[flag_idx
].name
;
2296 flaglen
= strlen (flagnm
);
2297 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2299 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2301 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2303 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2304 pflags
[*nflgs
].name
[flaglen
] = '\0';
2313 /* Used to find special case opcode. */
2315 static const struct arc_opcode_hash_entry
*
2316 find_special_case (const char *opname
,
2318 struct arc_flags
*pflags
,
2322 const struct arc_opcode_hash_entry
*entry
;
2324 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2327 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2332 /* Autodetect cpu attribute list. */
2335 autodetect_attributes (const struct arc_opcode
*opcode
,
2336 const expressionS
*tok
,
2344 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2347 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2348 if (opcode
->subclass
== feature_list
[i
].feature
)
2349 selected_cpu
.features
|= feature_list
[i
].feature
;
2351 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2352 if (opcode
->subclass
== mpy_list
[i
].feature
)
2353 mpy_option
= mpy_list
[i
].encoding
;
2355 for (i
= 0; i
< (unsigned) ntok
; i
++)
2357 switch (tok
[i
].X_md
)
2381 /* Given an opcode name, pre-tockenized set of argumenst and the
2382 opcode flags, take it all the way through emission. */
2385 assemble_tokens (const char *opname
,
2388 struct arc_flags
*pflags
,
2391 bfd_boolean found_something
= FALSE
;
2392 const struct arc_opcode_hash_entry
*entry
;
2394 const char *errmsg
= NULL
;
2396 /* Search opcodes. */
2397 entry
= arc_find_opcode (opname
);
2399 /* Couldn't find opcode conventional way, try special cases. */
2401 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2405 const struct arc_opcode
*opcode
;
2407 pr_debug ("%s:%d: assemble_tokens: %s\n",
2408 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2409 found_something
= TRUE
;
2410 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2411 nflgs
, &cpumatch
, &errmsg
);
2414 struct arc_insn insn
;
2416 autodetect_attributes (opcode
, tok
, ntok
);
2417 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2423 if (found_something
)
2427 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2429 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2431 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2435 as_bad (_("unknown opcode '%s'"), opname
);
2438 /* The public interface to the instruction assembler. */
2441 md_assemble (char *str
)
2444 expressionS tok
[MAX_INSN_ARGS
];
2447 struct arc_flags flags
[MAX_INSN_FLGS
];
2449 /* Split off the opcode. */
2450 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2451 opname
= xmemdup0 (str
, opnamelen
);
2453 /* Signalize we are assembling the instructions. */
2454 assembling_insn
= TRUE
;
2456 /* Tokenize the flags. */
2457 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2459 as_bad (_("syntax error"));
2463 /* Scan up to the end of the mnemonic which must end in space or end
2466 for (; *str
!= '\0'; str
++)
2470 /* Tokenize the rest of the line. */
2471 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2473 as_bad (_("syntax error"));
2477 /* Finish it off. */
2478 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2479 assembling_insn
= FALSE
;
2482 /* Callback to insert a register into the hash table. */
2485 declare_register (const char *name
, int number
)
2488 symbolS
*regS
= symbol_create (name
, reg_section
,
2489 number
, &zero_address_frag
);
2491 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2493 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2497 /* Construct symbols for each of the general registers. */
2500 declare_register_set (void)
2503 for (i
= 0; i
< 64; ++i
)
2507 sprintf (name
, "r%d", i
);
2508 declare_register (name
, i
);
2509 if ((i
& 0x01) == 0)
2511 sprintf (name
, "r%dr%d", i
, i
+1);
2512 declare_register (name
, i
);
2517 /* Construct a symbol for an address type. */
2520 declare_addrtype (const char *name
, int number
)
2523 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2524 number
, &zero_address_frag
);
2526 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2527 (void *) addrtypeS
);
2529 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2533 /* Port-specific assembler initialization. This function is called
2534 once, at assembler startup time. */
2539 const struct arc_opcode
*opcode
= arc_opcodes
;
2541 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2542 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2544 /* The endianness can be chosen "at the factory". */
2545 target_big_endian
= byte_order
== BIG_ENDIAN
;
2547 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2548 as_warn (_("could not set architecture and machine"));
2550 /* Set elf header flags. */
2551 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2553 /* Set up a hash table for the instructions. */
2554 arc_opcode_hash
= hash_new ();
2555 if (arc_opcode_hash
== NULL
)
2556 as_fatal (_("Virtual memory exhausted"));
2558 /* Initialize the hash table with the insns. */
2561 const char *name
= opcode
->name
;
2563 arc_insert_opcode (opcode
);
2565 while (++opcode
&& opcode
->name
2566 && (opcode
->name
== name
2567 || !strcmp (opcode
->name
, name
)))
2569 }while (opcode
->name
);
2571 /* Register declaration. */
2572 arc_reg_hash
= hash_new ();
2573 if (arc_reg_hash
== NULL
)
2574 as_fatal (_("Virtual memory exhausted"));
2576 declare_register_set ();
2577 declare_register ("gp", 26);
2578 declare_register ("fp", 27);
2579 declare_register ("sp", 28);
2580 declare_register ("ilink", 29);
2581 declare_register ("ilink1", 29);
2582 declare_register ("ilink2", 30);
2583 declare_register ("blink", 31);
2585 /* XY memory registers. */
2586 declare_register ("x0_u0", 32);
2587 declare_register ("x0_u1", 33);
2588 declare_register ("x1_u0", 34);
2589 declare_register ("x1_u1", 35);
2590 declare_register ("x2_u0", 36);
2591 declare_register ("x2_u1", 37);
2592 declare_register ("x3_u0", 38);
2593 declare_register ("x3_u1", 39);
2594 declare_register ("y0_u0", 40);
2595 declare_register ("y0_u1", 41);
2596 declare_register ("y1_u0", 42);
2597 declare_register ("y1_u1", 43);
2598 declare_register ("y2_u0", 44);
2599 declare_register ("y2_u1", 45);
2600 declare_register ("y3_u0", 46);
2601 declare_register ("y3_u1", 47);
2602 declare_register ("x0_nu", 48);
2603 declare_register ("x1_nu", 49);
2604 declare_register ("x2_nu", 50);
2605 declare_register ("x3_nu", 51);
2606 declare_register ("y0_nu", 52);
2607 declare_register ("y1_nu", 53);
2608 declare_register ("y2_nu", 54);
2609 declare_register ("y3_nu", 55);
2611 declare_register ("mlo", 57);
2612 declare_register ("mmid", 58);
2613 declare_register ("mhi", 59);
2615 declare_register ("acc1", 56);
2616 declare_register ("acc2", 57);
2618 declare_register ("lp_count", 60);
2619 declare_register ("pcl", 63);
2621 /* Initialize the last instructions. */
2622 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2624 /* Aux register declaration. */
2625 arc_aux_hash
= hash_new ();
2626 if (arc_aux_hash
== NULL
)
2627 as_fatal (_("Virtual memory exhausted"));
2629 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2631 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2635 if (!(auxr
->cpu
& selected_cpu
.flags
))
2638 if ((auxr
->subclass
!= NONE
)
2639 && !check_cpu_feature (auxr
->subclass
))
2642 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2644 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2645 auxr
->name
, retval
);
2648 /* Address type declaration. */
2649 arc_addrtype_hash
= hash_new ();
2650 if (arc_addrtype_hash
== NULL
)
2651 as_fatal (_("Virtual memory exhausted"));
2653 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2654 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2655 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2656 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2657 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2658 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2659 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2660 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2661 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2662 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2663 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2664 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2665 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2666 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2667 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2668 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2671 /* Write a value out to the object file, using the appropriate
2675 md_number_to_chars (char *buf
,
2679 if (target_big_endian
)
2680 number_to_chars_bigendian (buf
, val
, n
);
2682 number_to_chars_littleendian (buf
, val
, n
);
2685 /* Round up a section size to the appropriate boundary. */
2688 md_section_align (segT segment
,
2691 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2693 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2696 /* The location from which a PC relative jump should be calculated,
2697 given a PC relative reloc. */
2700 md_pcrel_from_section (fixS
*fixP
,
2703 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2705 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2707 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2708 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2709 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2711 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2713 /* The symbol is undefined (or is defined but not in this section).
2714 Let the linker figure it out. */
2718 if ((int) fixP
->fx_r_type
< 0)
2720 /* These are the "internal" relocations. Align them to
2721 32 bit boundary (PCL), for the moment. */
2726 switch (fixP
->fx_r_type
)
2728 case BFD_RELOC_ARC_PC32
:
2729 /* The hardware calculates relative to the start of the
2730 insn, but this relocation is relative to location of the
2731 LIMM, compensate. The base always needs to be
2732 subtracted by 4 as we do not support this type of PCrel
2733 relocation for short instructions. */
2736 case BFD_RELOC_ARC_PLT32
:
2737 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2738 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2739 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2740 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2742 case BFD_RELOC_ARC_S21H_PCREL
:
2743 case BFD_RELOC_ARC_S25H_PCREL
:
2744 case BFD_RELOC_ARC_S13_PCREL
:
2745 case BFD_RELOC_ARC_S21W_PCREL
:
2746 case BFD_RELOC_ARC_S25W_PCREL
:
2750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2751 _("unhandled reloc %s in md_pcrel_from_section"),
2752 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2757 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2758 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2759 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2760 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2761 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2766 /* Given a BFD relocation find the corresponding operand. */
2768 static const struct arc_operand
*
2769 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2773 for (i
= 0; i
< arc_num_operands
; i
++)
2774 if (arc_operands
[i
].default_reloc
== reloc
)
2775 return &arc_operands
[i
];
2779 /* Insert an operand value into an instruction. */
2781 static unsigned long long
2782 insert_operand (unsigned long long insn
,
2783 const struct arc_operand
*operand
,
2788 offsetT min
= 0, max
= 0;
2790 if (operand
->bits
!= 32
2791 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2792 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2794 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2796 max
= (1 << (operand
->bits
- 1)) - 1;
2797 min
= -(1 << (operand
->bits
- 1));
2801 max
= (1 << operand
->bits
) - 1;
2805 if (val
< min
|| val
> max
)
2806 as_bad_value_out_of_range (_("operand"),
2807 val
, min
, max
, file
, line
);
2810 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2811 min
, val
, max
, insn
);
2813 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2815 as_bad_where (file
, line
,
2816 _("Unaligned operand. Needs to be 32bit aligned"));
2818 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2820 as_bad_where (file
, line
,
2821 _("Unaligned operand. Needs to be 16bit aligned"));
2823 if (operand
->insert
)
2825 const char *errmsg
= NULL
;
2827 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2829 as_warn_where (file
, line
, "%s", errmsg
);
2833 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2835 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2837 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2840 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2845 /* Apply a fixup to the object code. At this point all symbol values
2846 should be fully resolved, and we attempt to completely resolve the
2847 reloc. If we can not do that, we determine the correct reloc code
2848 and put it back in the fixup. To indicate that a fixup has been
2849 eliminated, set fixP->fx_done. */
2852 md_apply_fix (fixS
*fixP
,
2856 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2857 valueT value
= *valP
;
2859 symbolS
*fx_addsy
, *fx_subsy
;
2861 segT add_symbol_segment
= absolute_section
;
2862 segT sub_symbol_segment
= absolute_section
;
2863 const struct arc_operand
*operand
= NULL
;
2864 extended_bfd_reloc_code_real_type reloc
;
2866 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2867 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2868 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2869 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2872 fx_addsy
= fixP
->fx_addsy
;
2873 fx_subsy
= fixP
->fx_subsy
;
2878 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2882 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2883 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2884 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2886 resolve_symbol_value (fx_subsy
);
2887 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2889 if (sub_symbol_segment
== absolute_section
)
2891 /* The symbol is really a constant. */
2892 fx_offset
-= S_GET_VALUE (fx_subsy
);
2897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2898 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2899 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2900 segment_name (add_symbol_segment
),
2901 S_GET_NAME (fx_subsy
),
2902 segment_name (sub_symbol_segment
));
2908 && !S_IS_WEAK (fx_addsy
))
2910 if (add_symbol_segment
== seg
2913 value
+= S_GET_VALUE (fx_addsy
);
2914 value
-= md_pcrel_from_section (fixP
, seg
);
2916 fixP
->fx_pcrel
= FALSE
;
2918 else if (add_symbol_segment
== absolute_section
)
2920 value
= fixP
->fx_offset
;
2921 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2923 fixP
->fx_pcrel
= FALSE
;
2928 fixP
->fx_done
= TRUE
;
2933 && ((S_IS_DEFINED (fx_addsy
)
2934 && S_GET_SEGMENT (fx_addsy
) != seg
)
2935 || S_IS_WEAK (fx_addsy
)))
2936 value
+= md_pcrel_from_section (fixP
, seg
);
2938 switch (fixP
->fx_r_type
)
2940 case BFD_RELOC_ARC_32_ME
:
2941 /* This is a pc-relative value in a LIMM. Adjust it to the
2942 address of the instruction not to the address of the
2943 LIMM. Note: it is not any longer valid this affirmation as
2944 the linker consider ARC_PC32 a fixup to entire 64 bit
2946 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2949 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2951 case BFD_RELOC_ARC_PC32
:
2952 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2955 if ((int) fixP
->fx_r_type
< 0)
2956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2957 _("PC relative relocation not allowed for (internal)"
2964 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2965 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2966 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2967 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2971 /* Now check for TLS relocations. */
2972 reloc
= fixP
->fx_r_type
;
2975 case BFD_RELOC_ARC_TLS_DTPOFF
:
2976 case BFD_RELOC_ARC_TLS_LE_32
:
2980 case BFD_RELOC_ARC_TLS_GD_GOT
:
2981 case BFD_RELOC_ARC_TLS_IE_GOT
:
2982 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2985 case BFD_RELOC_ARC_TLS_GD_LD
:
2986 gas_assert (!fixP
->fx_offset
);
2989 = (S_GET_VALUE (fixP
->fx_subsy
)
2990 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2991 fixP
->fx_subsy
= NULL
;
2993 case BFD_RELOC_ARC_TLS_GD_CALL
:
2994 /* These two relocs are there just to allow ld to change the tls
2995 model for this symbol, by patching the code. The offset -
2996 and scale, if any - will be installed by the linker. */
2997 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3000 case BFD_RELOC_ARC_TLS_LE_S9
:
3001 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3002 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3014 /* Adjust the value if we have a constant. */
3017 /* For hosts with longs bigger than 32-bits make sure that the top
3018 bits of a 32-bit negative value read in by the parser are set,
3019 so that the correct comparisons are made. */
3020 if (value
& 0x80000000)
3021 value
|= (-1UL << 31);
3023 reloc
= fixP
->fx_r_type
;
3031 case BFD_RELOC_ARC_32_PCREL
:
3032 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3035 case BFD_RELOC_ARC_GOTPC32
:
3036 /* I cannot fix an GOTPC relocation because I need to relax it
3037 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3038 as_bad (_("Unsupported operation on reloc"));
3041 case BFD_RELOC_ARC_TLS_DTPOFF
:
3042 case BFD_RELOC_ARC_TLS_LE_32
:
3043 gas_assert (!fixP
->fx_addsy
);
3044 gas_assert (!fixP
->fx_subsy
);
3047 case BFD_RELOC_ARC_GOTOFF
:
3048 case BFD_RELOC_ARC_32_ME
:
3049 case BFD_RELOC_ARC_PC32
:
3050 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3053 case BFD_RELOC_ARC_PLT32
:
3054 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3057 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3058 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3061 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3062 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3065 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3066 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3069 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3070 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3073 case BFD_RELOC_ARC_S25W_PCREL
:
3074 case BFD_RELOC_ARC_S21W_PCREL
:
3075 case BFD_RELOC_ARC_S21H_PCREL
:
3076 case BFD_RELOC_ARC_S25H_PCREL
:
3077 case BFD_RELOC_ARC_S13_PCREL
:
3079 operand
= find_operand_for_reloc (reloc
);
3080 gas_assert (operand
);
3085 if ((int) fixP
->fx_r_type
>= 0)
3086 as_fatal (_("unhandled relocation type %s"),
3087 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3089 /* The rest of these fixups needs to be completely resolved as
3091 if (fixP
->fx_addsy
!= 0
3092 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3094 _("non-absolute expression in constant field"));
3096 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3097 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3102 if (target_big_endian
)
3104 switch (fixP
->fx_size
)
3107 insn
= bfd_getb32 (fixpos
);
3110 insn
= bfd_getb16 (fixpos
);
3113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3114 _("unknown fixup size"));
3120 switch (fixP
->fx_size
)
3123 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3126 insn
= bfd_getl16 (fixpos
);
3129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3130 _("unknown fixup size"));
3134 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3135 fixP
->fx_file
, fixP
->fx_line
);
3137 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3140 /* Prepare machine-dependent frags for relaxation.
3142 Called just before relaxation starts. Any symbol that is now undefined
3143 will not become defined.
3145 Return the correct fr_subtype in the frag.
3147 Return the initial "guess for fr_var" to caller. The guess for fr_var
3148 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3149 or fr_var contributes to our returned value.
3151 Although it may not be explicit in the frag, pretend
3152 fr_var starts with a value. */
3155 md_estimate_size_before_relax (fragS
*fragP
,
3160 /* If the symbol is not located within the same section AND it's not
3161 an absolute section, use the maximum. OR if the symbol is a
3162 constant AND the insn is by nature not pc-rel, use the maximum.
3163 OR if the symbol is being equated against another symbol, use the
3164 maximum. OR if the symbol is weak use the maximum. */
3165 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3166 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3167 || (symbol_constant_p (fragP
->fr_symbol
)
3168 && !fragP
->tc_frag_data
.pcrel
)
3169 || symbol_equated_p (fragP
->fr_symbol
)
3170 || S_IS_WEAK (fragP
->fr_symbol
))
3172 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3173 ++fragP
->fr_subtype
;
3176 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3177 fragP
->fr_var
= growth
;
3179 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3180 fragP
->fr_file
, fragP
->fr_line
, growth
);
3185 /* Translate internal representation of relocation info to BFD target
3189 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3193 bfd_reloc_code_real_type code
;
3195 reloc
= XNEW (arelent
);
3196 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3197 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3198 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3200 /* Make sure none of our internal relocations make it this far.
3201 They'd better have been fully resolved by this point. */
3202 gas_assert ((int) fixP
->fx_r_type
> 0);
3204 code
= fixP
->fx_r_type
;
3206 /* if we have something like add gp, pcl,
3207 _GLOBAL_OFFSET_TABLE_@gotpc. */
3208 if (code
== BFD_RELOC_ARC_GOTPC32
3210 && fixP
->fx_addsy
== GOT_symbol
)
3211 code
= BFD_RELOC_ARC_GOTPC
;
3213 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3214 if (reloc
->howto
== NULL
)
3216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3217 _("cannot represent `%s' relocation in object file"),
3218 bfd_get_reloc_code_name (code
));
3222 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3223 as_fatal (_("internal error? cannot generate `%s' relocation"),
3224 bfd_get_reloc_code_name (code
));
3226 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3228 reloc
->addend
= fixP
->fx_offset
;
3233 /* Perform post-processing of machine-dependent frags after relaxation.
3234 Called after relaxation is finished.
3235 In: Address of frag.
3236 fr_type == rs_machine_dependent.
3237 fr_subtype is what the address relaxed to.
3239 Out: Any fixS:s and constants are set up. */
3242 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3243 segT segment ATTRIBUTE_UNUSED
,
3246 const relax_typeS
*table_entry
;
3248 const struct arc_opcode
*opcode
;
3249 struct arc_insn insn
;
3251 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3253 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3254 dest
= fragP
->fr_literal
+ fix
;
3255 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3257 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3258 "var: %"BFD_VMA_FMT
"d\n",
3259 fragP
->fr_file
, fragP
->fr_line
,
3260 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3262 if (fragP
->fr_subtype
<= 0
3263 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3264 as_fatal (_("no relaxation found for this instruction."));
3266 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3268 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3269 relax_arg
->nflg
, &insn
);
3271 apply_fixups (&insn
, fragP
, fix
);
3273 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3274 gas_assert (table_entry
->rlx_length
== size
);
3275 emit_insn0 (&insn
, dest
, TRUE
);
3277 fragP
->fr_fix
+= table_entry
->rlx_length
;
3281 /* We have no need to default values of symbols. We could catch
3282 register names here, but that is handled by inserting them all in
3283 the symbol table to begin with. */
3286 md_undefined_symbol (char *name
)
3288 /* The arc abi demands that a GOT[0] should be referencible as
3289 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3290 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3292 && (*(name
+1) == 'G')
3293 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)))
3297 if (symbol_find (name
))
3298 as_bad ("GOT already in symbol table");
3300 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3301 (valueT
) 0, &zero_address_frag
);
3308 /* Turn a string in input_line_pointer into a floating point constant
3309 of type type, and store the appropriate bytes in *litP. The number
3310 of LITTLENUMS emitted is stored in *sizeP. An error message is
3311 returned, or NULL on OK. */
3314 md_atof (int type
, char *litP
, int *sizeP
)
3316 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3319 /* Called for any expression that can not be recognized. When the
3320 function is called, `input_line_pointer' will point to the start of
3324 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3326 char *p
= input_line_pointer
;
3329 input_line_pointer
++;
3330 expressionP
->X_op
= O_symbol
;
3331 expression (expressionP
);
3335 /* This function is called from the function 'expression', it attempts
3336 to parse special names (in our case register names). It fills in
3337 the expression with the identified register. It returns TRUE if
3338 it is a register and FALSE otherwise. */
3341 arc_parse_name (const char *name
,
3342 struct expressionS
*e
)
3346 if (!assembling_insn
)
3349 if (e
->X_op
== O_symbol
)
3352 sym
= hash_find (arc_reg_hash
, name
);
3355 e
->X_op
= O_register
;
3356 e
->X_add_number
= S_GET_VALUE (sym
);
3360 sym
= hash_find (arc_addrtype_hash
, name
);
3363 e
->X_op
= O_addrtype
;
3364 e
->X_add_number
= S_GET_VALUE (sym
);
3372 Invocation line includes a switch not recognized by the base assembler.
3373 See if it's a processor-specific option.
3375 New options (supported) are:
3377 -mcpu=<cpu name> Assemble for selected processor
3378 -EB/-mbig-endian Big-endian
3379 -EL/-mlittle-endian Little-endian
3380 -mrelax Enable relaxation
3382 The following CPU names are recognized:
3383 arc600, arc700, arcem, archs, nps400. */
3386 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3392 return md_parse_option (OPTION_MCPU
, "arc600");
3395 return md_parse_option (OPTION_MCPU
, "arc700");
3398 return md_parse_option (OPTION_MCPU
, "arcem");
3401 return md_parse_option (OPTION_MCPU
, "archs");
3405 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3410 arc_target_format
= "elf32-bigarc";
3411 byte_order
= BIG_ENDIAN
;
3415 arc_target_format
= "elf32-littlearc";
3416 byte_order
= LITTLE_ENDIAN
;
3420 selected_cpu
.features
|= CD
;
3422 arc_check_feature ();
3426 relaxation_state
= 1;
3430 selected_cpu
.features
|= NPS400
;
3431 cl_features
|= NPS400
;
3432 arc_check_feature ();
3436 selected_cpu
.features
|= SPX
;
3438 arc_check_feature ();
3442 selected_cpu
.features
|= DPX
;
3444 arc_check_feature ();
3448 selected_cpu
.features
|= DPA
;
3450 arc_check_feature ();
3453 /* Dummy options are accepted but have no effect. */
3454 case OPTION_USER_MODE
:
3455 case OPTION_LD_EXT_MASK
:
3458 case OPTION_BARREL_SHIFT
:
3459 case OPTION_MIN_MAX
:
3464 case OPTION_XMAC_D16
:
3465 case OPTION_XMAC_24
:
3466 case OPTION_DSP_PACKA
:
3469 case OPTION_TELEPHONY
:
3470 case OPTION_XYMEMORY
:
3483 /* Display the list of cpu names for use in the help text. */
3486 arc_show_cpu_list (FILE *stream
)
3489 static const char *space_buf
= " ";
3491 fprintf (stream
, "%s", space_buf
);
3492 offset
= strlen (space_buf
);
3493 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3495 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3497 /* If displaying the new cpu name string, and the ', ' (for all
3498 but the last one) will take us past a target width of 80
3499 characters, then it's time for a new line. */
3500 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3502 fprintf (stream
, "\n%s", space_buf
);
3503 offset
= strlen (space_buf
);
3506 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3507 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3512 md_show_usage (FILE *stream
)
3514 fprintf (stream
, _("ARC-specific assembler options:\n"));
3516 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3517 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3518 arc_show_cpu_list (stream
);
3519 fprintf (stream
, "\n");
3520 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3521 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3522 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3523 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3525 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3526 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3528 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3530 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3531 "point\n\t\t\t instructions for ARC EM\n");
3534 " -mcode-density\t enable code density option for ARC EM\n");
3536 fprintf (stream
, _("\
3537 -EB assemble code for a big-endian cpu\n"));
3538 fprintf (stream
, _("\
3539 -EL assemble code for a little-endian cpu\n"));
3540 fprintf (stream
, _("\
3541 -mrelax enable relaxation\n"));
3543 fprintf (stream
, _("The following ARC-specific assembler options are "
3544 "deprecated and are accepted\nfor compatibility only:\n"));
3546 fprintf (stream
, _(" -mEA\n"
3547 " -mbarrel-shifter\n"
3548 " -mbarrel_shifter\n"
3553 " -mld-extension-reg-mask\n"
3569 " -muser-mode-only\n"
3573 /* Find the proper relocation for the given opcode. */
3575 static extended_bfd_reloc_code_real_type
3576 find_reloc (const char *name
,
3577 const char *opcodename
,
3578 const struct arc_flags
*pflags
,
3580 extended_bfd_reloc_code_real_type reloc
)
3584 bfd_boolean found_flag
, tmp
;
3585 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3587 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3589 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3591 /* Find the entry. */
3592 if (strcmp (name
, r
->name
))
3594 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3601 unsigned * psflg
= (unsigned *)r
->flags
;
3605 for (j
= 0; j
< nflg
; j
++)
3606 if (!strcmp (pflags
[j
].name
,
3607 arc_flag_operands
[*psflg
].name
))
3628 if (reloc
!= r
->oldreloc
)
3635 if (ret
== BFD_RELOC_UNUSED
)
3636 as_bad (_("Unable to find %s relocation for instruction %s"),
3641 /* All the symbol types that are allowed to be used for
3645 may_relax_expr (expressionS tok
)
3647 /* Check if we have unrelaxable relocs. */
3672 /* Checks if flags are in line with relaxable insn. */
3675 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3676 const struct arc_flags
*pflags
,
3679 unsigned flag_class
,
3684 const struct arc_flag_operand
*flag_opand
;
3685 int i
, counttrue
= 0;
3687 /* Iterate through flags classes. */
3688 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3690 /* Iterate through flags in flag class. */
3691 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3694 flag_opand
= &arc_flag_operands
[flag
];
3695 /* Iterate through flags in ins to compare. */
3696 for (i
= 0; i
< nflgs
; ++i
)
3698 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3709 /* If counttrue == nflgs, then all flags have been found. */
3710 return (counttrue
== nflgs
? TRUE
: FALSE
);
3713 /* Checks if operands are in line with relaxable insn. */
3716 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3717 const expressionS
*tok
,
3720 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3723 while (*operand
!= EMPTY
)
3725 const expressionS
*epr
= &tok
[i
];
3727 if (i
!= 0 && i
>= ntok
)
3733 if (!(epr
->X_op
== O_multiply
3734 || epr
->X_op
== O_divide
3735 || epr
->X_op
== O_modulus
3736 || epr
->X_op
== O_add
3737 || epr
->X_op
== O_subtract
3738 || epr
->X_op
== O_symbol
))
3744 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3748 if (epr
->X_op
!= O_register
)
3753 if (epr
->X_op
!= O_register
)
3756 switch (epr
->X_add_number
)
3758 case 0: case 1: case 2: case 3:
3759 case 12: case 13: case 14: case 15:
3766 case REGISTER_NO_GP
:
3767 if ((epr
->X_op
!= O_register
)
3768 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3773 if (epr
->X_op
!= O_bracket
)
3778 /* Don't understand, bail out. */
3784 operand
= &ins
->operands
[i
];
3787 return (i
== ntok
? TRUE
: FALSE
);
3790 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3793 relax_insn_p (const struct arc_opcode
*opcode
,
3794 const expressionS
*tok
,
3796 const struct arc_flags
*pflags
,
3800 bfd_boolean rv
= FALSE
;
3802 /* Check the relaxation table. */
3803 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3805 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3807 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3808 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3809 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3810 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3813 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3814 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3815 sizeof (expressionS
) * ntok
);
3816 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3817 sizeof (struct arc_flags
) * nflg
);
3818 frag_now
->tc_frag_data
.nflg
= nflg
;
3819 frag_now
->tc_frag_data
.ntok
= ntok
;
3827 /* Turn an opcode description and a set of arguments into
3828 an instruction and a fixup. */
3831 assemble_insn (const struct arc_opcode
*opcode
,
3832 const expressionS
*tok
,
3834 const struct arc_flags
*pflags
,
3836 struct arc_insn
*insn
)
3838 const expressionS
*reloc_exp
= NULL
;
3839 unsigned long long image
;
3840 const unsigned char *argidx
;
3843 unsigned char pcrel
= 0;
3844 bfd_boolean needGOTSymbol
;
3845 bfd_boolean has_delay_slot
= FALSE
;
3846 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3848 memset (insn
, 0, sizeof (*insn
));
3849 image
= opcode
->opcode
;
3851 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3852 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3855 /* Handle operands. */
3856 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3858 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3859 const expressionS
*t
= (const expressionS
*) 0;
3861 if (ARC_OPERAND_IS_FAKE (operand
))
3864 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3866 /* Duplicate operand, already inserted. */
3878 /* Regardless if we have a reloc or not mark the instruction
3879 limm if it is the case. */
3880 if (operand
->flags
& ARC_OPERAND_LIMM
)
3881 insn
->has_limm
= TRUE
;
3886 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3891 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3893 if (operand
->flags
& ARC_OPERAND_LIMM
)
3894 insn
->limm
= t
->X_add_number
;
3900 /* Ignore brackets, colons, and address types. */
3904 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3908 /* Maybe register range. */
3909 if ((t
->X_add_number
== 0)
3910 && contains_register (t
->X_add_symbol
)
3911 && contains_register (t
->X_op_symbol
))
3915 regs
= get_register (t
->X_add_symbol
);
3917 regs
|= get_register (t
->X_op_symbol
);
3918 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3924 /* This operand needs a relocation. */
3925 needGOTSymbol
= FALSE
;
3930 if (opcode
->insn_class
== JUMP
)
3931 as_bad (_("Unable to use @plt relocation for insn %s"),
3933 needGOTSymbol
= TRUE
;
3934 reloc
= find_reloc ("plt", opcode
->name
,
3936 operand
->default_reloc
);
3941 needGOTSymbol
= TRUE
;
3942 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3945 if (operand
->flags
& ARC_OPERAND_LIMM
)
3947 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3948 if (arc_opcode_len (opcode
) == 2
3949 || opcode
->insn_class
== JUMP
)
3950 as_bad (_("Unable to use @pcl relocation for insn %s"),
3955 /* This is a relaxed operand which initially was
3956 limm, choose whatever we have defined in the
3958 reloc
= operand
->default_reloc
;
3962 reloc
= find_reloc ("sda", opcode
->name
,
3964 operand
->default_reloc
);
3968 needGOTSymbol
= TRUE
;
3973 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3976 case O_tpoff9
: /*FIXME! Check for the conditionality of
3978 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3980 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3984 /* Just consider the default relocation. */
3985 reloc
= operand
->default_reloc
;
3989 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3990 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3997 /* sanity checks. */
3998 reloc_howto_type
*reloc_howto
3999 = bfd_reloc_type_lookup (stdoutput
,
4000 (bfd_reloc_code_real_type
) reloc
);
4001 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4002 if (reloc_howto
->rightshift
)
4003 reloc_bitsize
-= reloc_howto
->rightshift
;
4004 if (reloc_bitsize
!= operand
->bits
)
4006 as_bad (_("invalid relocation %s for field"),
4007 bfd_get_reloc_code_name (reloc
));
4012 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4013 as_fatal (_("too many fixups"));
4015 struct arc_fixup
*fixup
;
4016 fixup
= &insn
->fixups
[insn
->nfixups
++];
4018 fixup
->reloc
= reloc
;
4019 if ((int) reloc
< 0)
4020 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4023 reloc_howto_type
*reloc_howto
=
4024 bfd_reloc_type_lookup (stdoutput
,
4025 (bfd_reloc_code_real_type
) fixup
->reloc
);
4026 pcrel
= reloc_howto
->pc_relative
;
4028 fixup
->pcrel
= pcrel
;
4029 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4036 for (i
= 0; i
< nflg
; i
++)
4038 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4040 /* Check if the instruction has a delay slot. */
4041 if (!strcmp (flg_operand
->name
, "d"))
4042 has_delay_slot
= TRUE
;
4044 /* There is an exceptional case when we cannot insert a flag just as
4045 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4046 relation with the relative address. Unfortunately, some of the
4047 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4048 handled in the normal way.
4050 Flag operands don't have an architecture field, so we can't
4051 directly validate that FLAG_OPERAND is valid for the current
4052 architecture, what we do instead is just validate that we're
4053 assembling for an ARCv2 architecture. */
4054 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4055 && (!strcmp (flg_operand
->name
, "t")
4056 || !strcmp (flg_operand
->name
, "nt")))
4058 unsigned bitYoperand
= 0;
4059 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4060 if (!strcmp (flg_operand
->name
, "t"))
4061 if (!strcmp (opcode
->name
, "bbit0")
4062 || !strcmp (opcode
->name
, "bbit1"))
4063 bitYoperand
= arc_NToperand
;
4065 bitYoperand
= arc_Toperand
;
4067 if (!strcmp (opcode
->name
, "bbit0")
4068 || !strcmp (opcode
->name
, "bbit1"))
4069 bitYoperand
= arc_Toperand
;
4071 bitYoperand
= arc_NToperand
;
4073 gas_assert (reloc_exp
!= NULL
);
4074 if (reloc_exp
->X_op
== O_constant
)
4076 /* Check if we have a constant and solved it
4078 offsetT val
= reloc_exp
->X_add_number
;
4079 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4084 struct arc_fixup
*fixup
;
4086 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4087 as_fatal (_("too many fixups"));
4089 fixup
= &insn
->fixups
[insn
->nfixups
++];
4090 fixup
->exp
= *reloc_exp
;
4091 fixup
->reloc
= -bitYoperand
;
4092 fixup
->pcrel
= pcrel
;
4093 fixup
->islong
= FALSE
;
4097 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4098 << flg_operand
->shift
;
4101 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4103 /* Instruction length. */
4104 insn
->len
= arc_opcode_len (opcode
);
4108 /* Update last insn status. */
4109 arc_last_insns
[1] = arc_last_insns
[0];
4110 arc_last_insns
[0].opcode
= opcode
;
4111 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4112 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4114 /* Check if the current instruction is legally used. */
4115 if (arc_last_insns
[1].has_delay_slot
4116 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4117 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4118 arc_last_insns
[1].opcode
->name
,
4119 arc_last_insns
[0].opcode
->name
);
4120 if (arc_last_insns
[1].has_delay_slot
4121 && arc_last_insns
[0].has_limm
)
4122 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4123 arc_last_insns
[1].opcode
->name
,
4124 arc_last_insns
[0].opcode
->name
);
4128 arc_handle_align (fragS
* fragP
)
4130 if ((fragP
)->fr_type
== rs_align_code
)
4132 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4133 valueT count
= ((fragP
)->fr_next
->fr_address
4134 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4136 (fragP
)->fr_var
= 2;
4138 if (count
& 1)/* Padding in the gap till the next 2-byte
4139 boundary with 0s. */
4144 /* Writing nop_s. */
4145 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4149 /* Here we decide which fixups can be adjusted to make them relative
4150 to the beginning of the section instead of the symbol. Basically
4151 we need to make sure that the dynamic relocations are done
4152 correctly, so in some cases we force the original symbol to be
4156 tc_arc_fix_adjustable (fixS
*fixP
)
4159 /* Prevent all adjustments to global symbols. */
4160 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4162 if (S_IS_WEAK (fixP
->fx_addsy
))
4165 /* Adjust_reloc_syms doesn't know about the GOT. */
4166 switch (fixP
->fx_r_type
)
4168 case BFD_RELOC_ARC_GOTPC32
:
4169 case BFD_RELOC_ARC_PLT32
:
4170 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4171 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4172 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4173 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4183 /* Compute the reloc type of an expression EXP. */
4186 arc_check_reloc (expressionS
*exp
,
4187 bfd_reloc_code_real_type
*r_type_p
)
4189 if (*r_type_p
== BFD_RELOC_32
4190 && exp
->X_op
== O_subtract
4191 && exp
->X_op_symbol
!= NULL
4192 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4193 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4197 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4200 arc_cons_fix_new (fragS
*frag
,
4204 bfd_reloc_code_real_type r_type
)
4206 r_type
= BFD_RELOC_UNUSED
;
4211 r_type
= BFD_RELOC_8
;
4215 r_type
= BFD_RELOC_16
;
4219 r_type
= BFD_RELOC_24
;
4223 r_type
= BFD_RELOC_32
;
4224 arc_check_reloc (exp
, &r_type
);
4228 r_type
= BFD_RELOC_64
;
4232 as_bad (_("unsupported BFD relocation size %u"), size
);
4233 r_type
= BFD_RELOC_UNUSED
;
4236 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4239 /* The actual routine that checks the ZOL conditions. */
4242 check_zol (symbolS
*s
)
4244 switch (selected_cpu
.mach
)
4246 case bfd_mach_arc_arcv2
:
4247 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4250 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4251 || arc_last_insns
[1].has_delay_slot
)
4252 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4256 case bfd_mach_arc_arc600
:
4258 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4259 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4262 if (arc_last_insns
[0].has_limm
4263 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4264 as_bad (_("A jump instruction with long immediate detected at the \
4265 end of the ZOL label @%s"), S_GET_NAME (s
));
4268 case bfd_mach_arc_arc700
:
4269 if (arc_last_insns
[0].has_delay_slot
)
4270 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4279 /* If ZOL end check the last two instruction for illegals. */
4281 arc_frob_label (symbolS
* sym
)
4283 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4286 dwarf2_emit_label (sym
);
4289 /* Used because generic relaxation assumes a pc-rel value whilst we
4290 also relax instructions that use an absolute value resolved out of
4291 relative values (if that makes any sense). An example: 'add r1,
4292 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4293 but if they're in the same section we can subtract the section
4294 offset relocation which ends up in a resolved value. So if @.L2 is
4295 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4296 .text + 0x40 = 0x10. */
4298 arc_pcrel_adjust (fragS
*fragP
)
4300 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4301 fragP
->fr_address
, fragP
->fr_fix
,
4302 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4304 if (!fragP
->tc_frag_data
.pcrel
)
4305 return fragP
->fr_address
+ fragP
->fr_fix
;
4307 /* Take into account the PCL rounding. */
4308 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4311 /* Initialize the DWARF-2 unwind information for this procedure. */
4314 tc_arc_frame_initial_instructions (void)
4316 /* Stack pointer is register 28. */
4317 cfi_add_CFA_def_cfa (28, 0);
4321 tc_arc_regname_to_dw2regnum (char *regname
)
4325 sym
= hash_find (arc_reg_hash
, regname
);
4327 return S_GET_VALUE (sym
);
4332 /* Adjust the symbol table. Delete found AUX register symbols. */
4335 arc_adjust_symtab (void)
4339 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4341 /* I've created a symbol during parsing process. Now, remove
4342 the symbol as it is found to be an AUX register. */
4343 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4344 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4347 /* Now do generic ELF adjustments. */
4348 elf_adjust_symtab ();
4352 tokenize_extinsn (extInstruction_t
*einsn
)
4356 unsigned char major_opcode
;
4357 unsigned char sub_opcode
;
4358 unsigned char syntax_class
= 0;
4359 unsigned char syntax_class_modifiers
= 0;
4360 unsigned char suffix_class
= 0;
4365 /* 1st: get instruction name. */
4366 p
= input_line_pointer
;
4367 c
= get_symbol_name (&p
);
4369 insn_name
= xstrdup (p
);
4370 restore_line_pointer (c
);
4372 /* 2nd: get major opcode. */
4373 if (*input_line_pointer
!= ',')
4375 as_bad (_("expected comma after instruction name"));
4376 ignore_rest_of_line ();
4379 input_line_pointer
++;
4380 major_opcode
= get_absolute_expression ();
4382 /* 3rd: get sub-opcode. */
4385 if (*input_line_pointer
!= ',')
4387 as_bad (_("expected comma after major opcode"));
4388 ignore_rest_of_line ();
4391 input_line_pointer
++;
4392 sub_opcode
= get_absolute_expression ();
4394 /* 4th: get suffix class. */
4397 if (*input_line_pointer
!= ',')
4399 as_bad ("expected comma after sub opcode");
4400 ignore_rest_of_line ();
4403 input_line_pointer
++;
4409 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4411 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4412 suffixclass
[i
].len
))
4414 suffix_class
|= suffixclass
[i
].attr_class
;
4415 input_line_pointer
+= suffixclass
[i
].len
;
4420 if (i
== ARRAY_SIZE (suffixclass
))
4422 as_bad ("invalid suffix class");
4423 ignore_rest_of_line ();
4429 if (*input_line_pointer
== '|')
4430 input_line_pointer
++;
4435 /* 5th: get syntax class and syntax class modifiers. */
4436 if (*input_line_pointer
!= ',')
4438 as_bad ("expected comma after suffix class");
4439 ignore_rest_of_line ();
4442 input_line_pointer
++;
4448 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4450 if (!strncmp (syntaxclassmod
[i
].name
,
4452 syntaxclassmod
[i
].len
))
4454 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4455 input_line_pointer
+= syntaxclassmod
[i
].len
;
4460 if (i
== ARRAY_SIZE (syntaxclassmod
))
4462 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4464 if (!strncmp (syntaxclass
[i
].name
,
4466 syntaxclass
[i
].len
))
4468 syntax_class
|= syntaxclass
[i
].attr_class
;
4469 input_line_pointer
+= syntaxclass
[i
].len
;
4474 if (i
== ARRAY_SIZE (syntaxclass
))
4476 as_bad ("missing syntax class");
4477 ignore_rest_of_line ();
4484 if (*input_line_pointer
== '|')
4485 input_line_pointer
++;
4490 demand_empty_rest_of_line ();
4492 einsn
->name
= insn_name
;
4493 einsn
->major
= major_opcode
;
4494 einsn
->minor
= sub_opcode
;
4495 einsn
->syntax
= syntax_class
;
4496 einsn
->modsyn
= syntax_class_modifiers
;
4497 einsn
->suffix
= suffix_class
;
4498 einsn
->flags
= syntax_class
4499 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4502 /* Generate an extension section. */
4505 arc_set_ext_seg (void)
4507 if (!arcext_section
)
4509 arcext_section
= subseg_new (".arcextmap", 0);
4510 bfd_set_section_flags (stdoutput
, arcext_section
,
4511 SEC_READONLY
| SEC_HAS_CONTENTS
);
4514 subseg_set (arcext_section
, 0);
4518 /* Create an extension instruction description in the arc extension
4519 section of the output file.
4520 The structure for an instruction is like this:
4521 [0]: Length of the record.
4522 [1]: Type of the record.
4526 [4]: Syntax (flags).
4527 [5]+ Name instruction.
4529 The sequence is terminated by an empty entry. */
4532 create_extinst_section (extInstruction_t
*einsn
)
4535 segT old_sec
= now_seg
;
4536 int old_subsec
= now_subseg
;
4538 int name_len
= strlen (einsn
->name
);
4543 *p
= 5 + name_len
+ 1;
4545 *p
= EXT_INSTRUCTION
;
4552 p
= frag_more (name_len
+ 1);
4553 strcpy (p
, einsn
->name
);
4555 subseg_set (old_sec
, old_subsec
);
4558 /* Handler .extinstruction pseudo-op. */
4561 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4563 extInstruction_t einsn
;
4564 struct arc_opcode
*arc_ext_opcodes
;
4565 const char *errmsg
= NULL
;
4566 unsigned char moplow
, mophigh
;
4568 memset (&einsn
, 0, sizeof (einsn
));
4569 tokenize_extinsn (&einsn
);
4571 /* Check if the name is already used. */
4572 if (arc_find_opcode (einsn
.name
))
4573 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4575 /* Check the opcode ranges. */
4577 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4578 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4580 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4581 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4583 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4584 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4585 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4587 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4589 case ARC_SYNTAX_3OP
:
4590 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4591 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4593 case ARC_SYNTAX_2OP
:
4594 case ARC_SYNTAX_1OP
:
4595 case ARC_SYNTAX_NOP
:
4596 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4597 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4603 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4604 if (arc_ext_opcodes
== NULL
)
4607 as_fatal ("%s", errmsg
);
4609 as_fatal (_("Couldn't generate extension instruction opcodes"));
4612 as_warn ("%s", errmsg
);
4614 /* Insert the extension instruction. */
4615 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4617 create_extinst_section (&einsn
);
4621 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4627 int number
, imode
= 0;
4628 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4629 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4630 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4632 /* 1st: get register name. */
4634 p
= input_line_pointer
;
4635 c
= get_symbol_name (&p
);
4638 restore_line_pointer (c
);
4640 /* 2nd: get register number. */
4643 if (*input_line_pointer
!= ',')
4645 as_bad (_("expected comma after name"));
4646 ignore_rest_of_line ();
4650 input_line_pointer
++;
4651 number
= get_absolute_expression ();
4654 && (opertype
!= EXT_AUX_REGISTER
))
4656 as_bad (_("%s second argument cannot be a negative number %d"),
4657 isCore_p
? "extCoreRegister's" : "extCondCode's",
4659 ignore_rest_of_line ();
4666 /* 3rd: get register mode. */
4669 if (*input_line_pointer
!= ',')
4671 as_bad (_("expected comma after register number"));
4672 ignore_rest_of_line ();
4677 input_line_pointer
++;
4678 mode
= input_line_pointer
;
4680 if (!strncmp (mode
, "r|w", 3))
4683 input_line_pointer
+= 3;
4685 else if (!strncmp (mode
, "r", 1))
4687 imode
= ARC_REGISTER_READONLY
;
4688 input_line_pointer
+= 1;
4690 else if (strncmp (mode
, "w", 1))
4692 as_bad (_("invalid mode"));
4693 ignore_rest_of_line ();
4699 imode
= ARC_REGISTER_WRITEONLY
;
4700 input_line_pointer
+= 1;
4706 /* 4th: get core register shortcut. */
4708 if (*input_line_pointer
!= ',')
4710 as_bad (_("expected comma after register mode"));
4711 ignore_rest_of_line ();
4716 input_line_pointer
++;
4718 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4720 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4721 input_line_pointer
+= 15;
4723 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4725 as_bad (_("shortcut designator invalid"));
4726 ignore_rest_of_line ();
4732 input_line_pointer
+= 12;
4735 demand_empty_rest_of_line ();
4738 ereg
->number
= number
;
4739 ereg
->imode
= imode
;
4743 /* Create an extension register/condition description in the arc
4744 extension section of the output file.
4746 The structure for an instruction is like this:
4747 [0]: Length of the record.
4748 [1]: Type of the record.
4750 For core regs and condition codes:
4754 For auxiliary registers:
4758 The sequence is terminated by an empty entry. */
4761 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4763 segT old_sec
= now_seg
;
4764 int old_subsec
= now_subseg
;
4766 int name_len
= strlen (ereg
->name
);
4773 case EXT_CORE_REGISTER
:
4775 *p
= 3 + name_len
+ 1;
4781 case EXT_AUX_REGISTER
:
4783 *p
= 6 + name_len
+ 1;
4785 *p
= EXT_AUX_REGISTER
;
4787 *p
= (ereg
->number
>> 24) & 0xff;
4789 *p
= (ereg
->number
>> 16) & 0xff;
4791 *p
= (ereg
->number
>> 8) & 0xff;
4793 *p
= (ereg
->number
) & 0xff;
4799 p
= frag_more (name_len
+ 1);
4800 strcpy (p
, ereg
->name
);
4802 subseg_set (old_sec
, old_subsec
);
4805 /* Handler .extCoreRegister pseudo-op. */
4808 arc_extcorereg (int opertype
)
4811 struct arc_aux_reg
*auxr
;
4813 struct arc_flag_operand
*ccode
;
4815 memset (&ereg
, 0, sizeof (ereg
));
4816 if (!tokenize_extregister (&ereg
, opertype
))
4821 case EXT_CORE_REGISTER
:
4822 /* Core register. */
4823 if (ereg
.number
> 60)
4824 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4826 declare_register (ereg
.name
, ereg
.number
);
4828 case EXT_AUX_REGISTER
:
4829 /* Auxiliary register. */
4830 auxr
= XNEW (struct arc_aux_reg
);
4831 auxr
->name
= ereg
.name
;
4832 auxr
->cpu
= selected_cpu
.flags
;
4833 auxr
->subclass
= NONE
;
4834 auxr
->address
= ereg
.number
;
4835 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4837 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4838 auxr
->name
, retval
);
4841 /* Condition code. */
4842 if (ereg
.number
> 31)
4843 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4845 ext_condcode
.size
++;
4846 ext_condcode
.arc_ext_condcode
=
4847 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4848 ext_condcode
.size
+ 1);
4849 if (ext_condcode
.arc_ext_condcode
== NULL
)
4850 as_fatal (_("Virtual memory exhausted"));
4852 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4853 ccode
->name
= ereg
.name
;
4854 ccode
->code
= ereg
.number
;
4857 ccode
->favail
= 0; /* not used. */
4859 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4862 as_bad (_("Unknown extension"));
4865 create_extcore_section (&ereg
, opertype
);
4868 /* Parse a .arc_attribute directive. */
4871 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4873 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4875 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4876 attributes_set_explicitly
[tag
] = TRUE
;
4879 /* Set an attribute if it has not already been set by the user. */
4882 arc_set_attribute_int (int tag
, int value
)
4885 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4886 || !attributes_set_explicitly
[tag
])
4887 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4891 arc_set_attribute_string (int tag
, const char *value
)
4894 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4895 || !attributes_set_explicitly
[tag
])
4896 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4899 /* Allocate and concatenate two strings. s1 can be NULL but not
4900 s2. s1 pointer is freed at end of this procedure. */
4903 arc_stralloc (char * s1
, const char * s2
)
4909 len
= strlen (s1
) + 1;
4911 /* Only s1 can be null. */
4913 len
+= strlen (s2
) + 1;
4915 p
= (char *) xmalloc (len
);
4917 as_fatal (_("Virtual memory exhausted"));
4932 /* Set the public ARC object attributes. */
4935 arc_set_public_attributes (void)
4941 /* Tag_ARC_CPU_name. */
4942 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4944 /* Tag_ARC_CPU_base. */
4945 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
4947 case E_ARC_MACH_ARC600
:
4948 case E_ARC_MACH_ARC601
:
4949 base
= TAG_CPU_ARC6xx
;
4951 case E_ARC_MACH_ARC700
:
4952 base
= TAG_CPU_ARC7xx
;
4954 case EF_ARC_CPU_ARCV2EM
:
4955 base
= TAG_CPU_ARCEM
;
4957 case EF_ARC_CPU_ARCV2HS
:
4958 base
= TAG_CPU_ARCHS
;
4964 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
4965 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
4967 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4968 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
4970 /* Tag_ARC_ABI_osver. */
4971 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
4973 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
4976 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
4977 | (val
& 0x0f << 8));
4981 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
4984 /* Tag_ARC_ISA_config. */
4985 arc_check_feature();
4987 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
4988 if (selected_cpu
.features
& feature_list
[i
].feature
)
4989 s
= arc_stralloc (s
, feature_list
[i
].attr
);
4992 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
4994 /* Tag_ARC_ISA_mpy_option. */
4995 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
4997 /* Tag_ARC_ABI_pic. */
4998 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5000 /* Tag_ARC_ABI_sda. */
5001 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5003 /* Tag_ARC_ABI_tls. */
5004 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5007 /* Add the default contents for the .ARC.attributes section. */
5012 arc_set_public_attributes ();
5014 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5015 as_fatal (_("could not set architecture and machine"));
5017 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5020 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5022 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5025 int arc_convert_symbolic_attribute (const char *name
)
5034 #define T(tag) {#tag, tag}
5035 T (Tag_ARC_PCS_config
),
5036 T (Tag_ARC_CPU_base
),
5037 T (Tag_ARC_CPU_variation
),
5038 T (Tag_ARC_CPU_name
),
5039 T (Tag_ARC_ABI_rf16
),
5040 T (Tag_ARC_ABI_osver
),
5041 T (Tag_ARC_ABI_sda
),
5042 T (Tag_ARC_ABI_pic
),
5043 T (Tag_ARC_ABI_tls
),
5044 T (Tag_ARC_ABI_enumsize
),
5045 T (Tag_ARC_ABI_exceptions
),
5046 T (Tag_ARC_ABI_double_size
),
5047 T (Tag_ARC_ISA_config
),
5048 T (Tag_ARC_ISA_apex
),
5049 T (Tag_ARC_ISA_mpy_option
)
5057 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5058 if (streq (name
, attribute_table
[i
].name
))
5059 return attribute_table
[i
].tag
;
5065 eval: (c-set-style "gnu")