1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
354 /* The maximum number of operands we need. */
355 #define ARM_IT_MAX_OPERANDS 6
360 unsigned long instruction
;
364 /* "uncond_value" is set to the value in place of the conditional field in
365 unconditional versions of the instruction, or -1 if nothing is
368 struct neon_type vectype
;
369 /* This does not indicate an actual NEON instruction, only that
370 the mnemonic accepts neon-style type suffixes. */
372 /* Set to the opcode if the instruction needs relaxation.
373 Zero if the instruction is not relaxed. */
377 bfd_reloc_code_real_type type
;
382 enum it_instruction_type it_insn_type
;
388 struct neon_type_el vectype
;
389 unsigned present
: 1; /* Operand present. */
390 unsigned isreg
: 1; /* Operand was a register. */
391 unsigned immisreg
: 1; /* .imm field is a second register. */
392 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
393 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
394 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
395 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
396 instructions. This allows us to disambiguate ARM <-> vector insns. */
397 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
398 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
399 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
400 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
401 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
402 unsigned writeback
: 1; /* Operand has trailing ! */
403 unsigned preind
: 1; /* Preindexed address. */
404 unsigned postind
: 1; /* Postindexed address. */
405 unsigned negative
: 1; /* Index register was negated. */
406 unsigned shifted
: 1; /* Shift applied to operation. */
407 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 } operands
[ARM_IT_MAX_OPERANDS
];
411 static struct arm_it inst
;
413 #define NUM_FLOAT_VALS 8
415 const char * fp_const
[] =
417 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
420 /* Number of littlenums required to hold an extended precision number. */
421 #define MAX_LITTLENUMS 6
423 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
433 #define CP_T_X 0x00008000
434 #define CP_T_Y 0x00400000
436 #define CONDS_BIT 0x00100000
437 #define LOAD_BIT 0x00100000
439 #define DOUBLE_LOAD_FLAG 0x00000001
443 const char * template_name
;
447 #define COND_ALWAYS 0xE
451 const char * template_name
;
455 struct asm_barrier_opt
457 const char * template_name
;
461 /* The bit that distinguishes CPSR and SPSR. */
462 #define SPSR_BIT (1 << 22)
464 /* The individual PSR flag bits. */
465 #define PSR_c (1 << 16)
466 #define PSR_x (1 << 17)
467 #define PSR_s (1 << 18)
468 #define PSR_f (1 << 19)
473 bfd_reloc_code_real_type reloc
;
478 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
479 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
484 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
487 /* Bits for DEFINED field in neon_typed_alias. */
488 #define NTA_HASTYPE 1
489 #define NTA_HASINDEX 2
491 struct neon_typed_alias
493 unsigned char defined
;
495 struct neon_type_el eltype
;
498 /* ARM register categories. This includes coprocessor numbers and various
499 architecture extensions' registers. */
526 /* Structure for a hash table entry for a register.
527 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
528 information which states whether a vector type or index is specified (for a
529 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
535 unsigned char builtin
;
536 struct neon_typed_alias
* neon
;
539 /* Diagnostics used when we don't get a register of the expected type. */
540 const char * const reg_expected_msgs
[] =
542 N_("ARM register expected"),
543 N_("bad or missing co-processor number"),
544 N_("co-processor register expected"),
545 N_("FPA register expected"),
546 N_("VFP single precision register expected"),
547 N_("VFP/Neon double precision register expected"),
548 N_("Neon quad precision register expected"),
549 N_("VFP single or double precision register expected"),
550 N_("Neon double or quad precision register expected"),
551 N_("VFP single, double or Neon quad precision register expected"),
552 N_("VFP system register expected"),
553 N_("Maverick MVF register expected"),
554 N_("Maverick MVD register expected"),
555 N_("Maverick MVFX register expected"),
556 N_("Maverick MVDX register expected"),
557 N_("Maverick MVAX register expected"),
558 N_("Maverick DSPSC register expected"),
559 N_("iWMMXt data register expected"),
560 N_("iWMMXt control register expected"),
561 N_("iWMMXt scalar register expected"),
562 N_("XScale accumulator register expected"),
565 /* Some well known registers that we refer to directly elsewhere. */
570 /* ARM instructions take 4bytes in the object file, Thumb instructions
576 /* Basic string to match. */
577 const char * template_name
;
579 /* Parameters to instruction. */
580 unsigned int operands
[8];
582 /* Conditional tag - see opcode_lookup. */
583 unsigned int tag
: 4;
585 /* Basic instruction code. */
586 unsigned int avalue
: 28;
588 /* Thumb-format instruction code. */
591 /* Which architecture variant provides this instruction. */
592 const arm_feature_set
* avariant
;
593 const arm_feature_set
* tvariant
;
595 /* Function to call to encode instruction in ARM format. */
596 void (* aencode
) (void);
598 /* Function to call to encode instruction in Thumb format. */
599 void (* tencode
) (void);
602 /* Defines for various bits that we will want to toggle. */
603 #define INST_IMMEDIATE 0x02000000
604 #define OFFSET_REG 0x02000000
605 #define HWOFFSET_IMM 0x00400000
606 #define SHIFT_BY_REG 0x00000010
607 #define PRE_INDEX 0x01000000
608 #define INDEX_UP 0x00800000
609 #define WRITE_BACK 0x00200000
610 #define LDM_TYPE_2_OR_3 0x00400000
611 #define CPSI_MMOD 0x00020000
613 #define LITERAL_MASK 0xf000f000
614 #define OPCODE_MASK 0xfe1fffff
615 #define V4_STR_BIT 0x00000020
617 #define T2_SUBS_PC_LR 0xf3de8f00
619 #define DATA_OP_SHIFT 21
621 #define T2_OPCODE_MASK 0xfe1fffff
622 #define T2_DATA_OP_SHIFT 21
624 /* Codes to distinguish the arithmetic instructions. */
635 #define OPCODE_CMP 10
636 #define OPCODE_CMN 11
637 #define OPCODE_ORR 12
638 #define OPCODE_MOV 13
639 #define OPCODE_BIC 14
640 #define OPCODE_MVN 15
642 #define T2_OPCODE_AND 0
643 #define T2_OPCODE_BIC 1
644 #define T2_OPCODE_ORR 2
645 #define T2_OPCODE_ORN 3
646 #define T2_OPCODE_EOR 4
647 #define T2_OPCODE_ADD 8
648 #define T2_OPCODE_ADC 10
649 #define T2_OPCODE_SBC 11
650 #define T2_OPCODE_SUB 13
651 #define T2_OPCODE_RSB 14
653 #define T_OPCODE_MUL 0x4340
654 #define T_OPCODE_TST 0x4200
655 #define T_OPCODE_CMN 0x42c0
656 #define T_OPCODE_NEG 0x4240
657 #define T_OPCODE_MVN 0x43c0
659 #define T_OPCODE_ADD_R3 0x1800
660 #define T_OPCODE_SUB_R3 0x1a00
661 #define T_OPCODE_ADD_HI 0x4400
662 #define T_OPCODE_ADD_ST 0xb000
663 #define T_OPCODE_SUB_ST 0xb080
664 #define T_OPCODE_ADD_SP 0xa800
665 #define T_OPCODE_ADD_PC 0xa000
666 #define T_OPCODE_ADD_I8 0x3000
667 #define T_OPCODE_SUB_I8 0x3800
668 #define T_OPCODE_ADD_I3 0x1c00
669 #define T_OPCODE_SUB_I3 0x1e00
671 #define T_OPCODE_ASR_R 0x4100
672 #define T_OPCODE_LSL_R 0x4080
673 #define T_OPCODE_LSR_R 0x40c0
674 #define T_OPCODE_ROR_R 0x41c0
675 #define T_OPCODE_ASR_I 0x1000
676 #define T_OPCODE_LSL_I 0x0000
677 #define T_OPCODE_LSR_I 0x0800
679 #define T_OPCODE_MOV_I8 0x2000
680 #define T_OPCODE_CMP_I8 0x2800
681 #define T_OPCODE_CMP_LR 0x4280
682 #define T_OPCODE_MOV_HR 0x4600
683 #define T_OPCODE_CMP_HR 0x4500
685 #define T_OPCODE_LDR_PC 0x4800
686 #define T_OPCODE_LDR_SP 0x9800
687 #define T_OPCODE_STR_SP 0x9000
688 #define T_OPCODE_LDR_IW 0x6800
689 #define T_OPCODE_STR_IW 0x6000
690 #define T_OPCODE_LDR_IH 0x8800
691 #define T_OPCODE_STR_IH 0x8000
692 #define T_OPCODE_LDR_IB 0x7800
693 #define T_OPCODE_STR_IB 0x7000
694 #define T_OPCODE_LDR_RW 0x5800
695 #define T_OPCODE_STR_RW 0x5000
696 #define T_OPCODE_LDR_RH 0x5a00
697 #define T_OPCODE_STR_RH 0x5200
698 #define T_OPCODE_LDR_RB 0x5c00
699 #define T_OPCODE_STR_RB 0x5400
701 #define T_OPCODE_PUSH 0xb400
702 #define T_OPCODE_POP 0xbc00
704 #define T_OPCODE_BRANCH 0xe000
706 #define THUMB_SIZE 2 /* Size of thumb instruction. */
707 #define THUMB_PP_PC_LR 0x0100
708 #define THUMB_LOAD_BIT 0x0800
709 #define THUMB2_LOAD_BIT 0x00100000
711 #define BAD_ARGS _("bad arguments to instruction")
712 #define BAD_SP _("r13 not allowed here")
713 #define BAD_PC _("r15 not allowed here")
714 #define BAD_COND _("instruction cannot be conditional")
715 #define BAD_OVERLAP _("registers may not be the same")
716 #define BAD_HIREG _("lo register required")
717 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
718 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
719 #define BAD_BRANCH _("branch must be last instruction in IT block")
720 #define BAD_NOT_IT _("instruction not allowed in IT block")
721 #define BAD_FPU _("selected FPU does not support instruction")
722 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
723 #define BAD_IT_COND _("incorrect condition in IT block")
724 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
725 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
726 #define BAD_PC_ADDRESSING \
727 _("cannot use register index with PC-relative addressing")
728 #define BAD_PC_WRITEBACK \
729 _("cannot use writeback with PC-relative addressing")
730 #define BAD_RANGE _("branch out of range")
732 static struct hash_control
* arm_ops_hsh
;
733 static struct hash_control
* arm_cond_hsh
;
734 static struct hash_control
* arm_shift_hsh
;
735 static struct hash_control
* arm_psr_hsh
;
736 static struct hash_control
* arm_v7m_psr_hsh
;
737 static struct hash_control
* arm_reg_hsh
;
738 static struct hash_control
* arm_reloc_hsh
;
739 static struct hash_control
* arm_barrier_opt_hsh
;
741 /* Stuff needed to resolve the label ambiguity
750 symbolS
* last_label_seen
;
751 static int label_is_thumb_function_name
= FALSE
;
753 /* Literal pool structure. Held on a per-section
754 and per-sub-section basis. */
756 #define MAX_LITERAL_POOL_SIZE 1024
757 typedef struct literal_pool
759 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
760 unsigned int next_free_entry
;
766 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
768 struct literal_pool
* next
;
771 /* Pointer to a linked list of literal pools. */
772 literal_pool
* list_of_pools
= NULL
;
775 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
777 static struct current_it now_it
;
781 now_it_compatible (int cond
)
783 return (cond
& ~1) == (now_it
.cc
& ~1);
787 conditional_insn (void)
789 return inst
.cond
!= COND_ALWAYS
;
792 static int in_it_block (void);
794 static int handle_it_state (void);
796 static void force_automatic_it_block_close (void);
798 static void it_fsm_post_encode (void);
800 #define set_it_insn_type(type) \
803 inst.it_insn_type = type; \
804 if (handle_it_state () == FAIL) \
809 #define set_it_insn_type_nonvoid(type, failret) \
812 inst.it_insn_type = type; \
813 if (handle_it_state () == FAIL) \
818 #define set_it_insn_type_last() \
821 if (inst.cond == COND_ALWAYS) \
822 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
824 set_it_insn_type (INSIDE_IT_LAST_INSN); \
830 /* This array holds the chars that always start a comment. If the
831 pre-processor is disabled, these aren't very useful. */
832 const char comment_chars
[] = "@";
834 /* This array holds the chars that only start a comment at the beginning of
835 a line. If the line seems to have the form '# 123 filename'
836 .line and .file directives will appear in the pre-processed output. */
837 /* Note that input_file.c hand checks for '#' at the beginning of the
838 first line of the input file. This is because the compiler outputs
839 #NO_APP at the beginning of its output. */
840 /* Also note that comments like this one will always work. */
841 const char line_comment_chars
[] = "#";
843 const char line_separator_chars
[] = ";";
845 /* Chars that can be used to separate mant
846 from exp in floating point numbers. */
847 const char EXP_CHARS
[] = "eE";
849 /* Chars that mean this number is a floating point constant. */
853 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
855 /* Prefix characters that indicate the start of an immediate
857 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
859 /* Separator character handling. */
861 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
864 skip_past_char (char ** str
, char c
)
875 #define skip_past_comma(str) skip_past_char (str, ',')
877 /* Arithmetic expressions (possibly involving symbols). */
879 /* Return TRUE if anything in the expression is a bignum. */
882 walk_no_bignums (symbolS
* sp
)
884 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
887 if (symbol_get_value_expression (sp
)->X_add_symbol
)
889 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
890 || (symbol_get_value_expression (sp
)->X_op_symbol
891 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
897 static int in_my_get_expression
= 0;
899 /* Third argument to my_get_expression. */
900 #define GE_NO_PREFIX 0
901 #define GE_IMM_PREFIX 1
902 #define GE_OPT_PREFIX 2
903 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
904 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
905 #define GE_OPT_PREFIX_BIG 3
908 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
913 /* In unified syntax, all prefixes are optional. */
915 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
920 case GE_NO_PREFIX
: break;
922 if (!is_immediate_prefix (**str
))
924 inst
.error
= _("immediate expression requires a # prefix");
930 case GE_OPT_PREFIX_BIG
:
931 if (is_immediate_prefix (**str
))
937 memset (ep
, 0, sizeof (expressionS
));
939 save_in
= input_line_pointer
;
940 input_line_pointer
= *str
;
941 in_my_get_expression
= 1;
942 seg
= expression (ep
);
943 in_my_get_expression
= 0;
945 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
947 /* We found a bad or missing expression in md_operand(). */
948 *str
= input_line_pointer
;
949 input_line_pointer
= save_in
;
950 if (inst
.error
== NULL
)
951 inst
.error
= (ep
->X_op
== O_absent
952 ? _("missing expression") :_("bad expression"));
957 if (seg
!= absolute_section
958 && seg
!= text_section
959 && seg
!= data_section
960 && seg
!= bss_section
961 && seg
!= undefined_section
)
963 inst
.error
= _("bad segment");
964 *str
= input_line_pointer
;
965 input_line_pointer
= save_in
;
972 /* Get rid of any bignums now, so that we don't generate an error for which
973 we can't establish a line number later on. Big numbers are never valid
974 in instructions, which is where this routine is always called. */
975 if (prefix_mode
!= GE_OPT_PREFIX_BIG
976 && (ep
->X_op
== O_big
978 && (walk_no_bignums (ep
->X_add_symbol
)
980 && walk_no_bignums (ep
->X_op_symbol
))))))
982 inst
.error
= _("invalid constant");
983 *str
= input_line_pointer
;
984 input_line_pointer
= save_in
;
988 *str
= input_line_pointer
;
989 input_line_pointer
= save_in
;
993 /* Turn a string in input_line_pointer into a floating point constant
994 of type TYPE, and store the appropriate bytes in *LITP. The number
995 of LITTLENUMS emitted is stored in *SIZEP. An error message is
996 returned, or NULL on OK.
998 Note that fp constants aren't represent in the normal way on the ARM.
999 In big endian mode, things are as expected. However, in little endian
1000 mode fp constants are big-endian word-wise, and little-endian byte-wise
1001 within the words. For example, (double) 1.1 in big endian mode is
1002 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1003 the byte sequence 99 99 f1 3f 9a 99 99 99.
1005 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1008 md_atof (int type
, char * litP
, int * sizeP
)
1011 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1043 return _("Unrecognized or unsupported floating point constant");
1046 t
= atof_ieee (input_line_pointer
, type
, words
);
1048 input_line_pointer
= t
;
1049 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1051 if (target_big_endian
)
1053 for (i
= 0; i
< prec
; i
++)
1055 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1056 litP
+= sizeof (LITTLENUM_TYPE
);
1061 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1062 for (i
= prec
- 1; i
>= 0; i
--)
1064 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1065 litP
+= sizeof (LITTLENUM_TYPE
);
1068 /* For a 4 byte float the order of elements in `words' is 1 0.
1069 For an 8 byte float the order is 1 0 3 2. */
1070 for (i
= 0; i
< prec
; i
+= 2)
1072 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1073 sizeof (LITTLENUM_TYPE
));
1074 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1075 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1076 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1083 /* We handle all bad expressions here, so that we can report the faulty
1084 instruction in the error message. */
1086 md_operand (expressionS
* exp
)
1088 if (in_my_get_expression
)
1089 exp
->X_op
= O_illegal
;
1092 /* Immediate values. */
1094 /* Generic immediate-value read function for use in directives.
1095 Accepts anything that 'expression' can fold to a constant.
1096 *val receives the number. */
1099 immediate_for_directive (int *val
)
1102 exp
.X_op
= O_illegal
;
1104 if (is_immediate_prefix (*input_line_pointer
))
1106 input_line_pointer
++;
1110 if (exp
.X_op
!= O_constant
)
1112 as_bad (_("expected #constant"));
1113 ignore_rest_of_line ();
1116 *val
= exp
.X_add_number
;
1121 /* Register parsing. */
1123 /* Generic register parser. CCP points to what should be the
1124 beginning of a register name. If it is indeed a valid register
1125 name, advance CCP over it and return the reg_entry structure;
1126 otherwise return NULL. Does not issue diagnostics. */
1128 static struct reg_entry
*
1129 arm_reg_parse_multi (char **ccp
)
1133 struct reg_entry
*reg
;
1135 #ifdef REGISTER_PREFIX
1136 if (*start
!= REGISTER_PREFIX
)
1140 #ifdef OPTIONAL_REGISTER_PREFIX
1141 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1146 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1151 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1153 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1163 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1164 enum arm_reg_type type
)
1166 /* Alternative syntaxes are accepted for a few register classes. */
1173 /* Generic coprocessor register names are allowed for these. */
1174 if (reg
&& reg
->type
== REG_TYPE_CN
)
1179 /* For backward compatibility, a bare number is valid here. */
1181 unsigned long processor
= strtoul (start
, ccp
, 10);
1182 if (*ccp
!= start
&& processor
<= 15)
1186 case REG_TYPE_MMXWC
:
1187 /* WC includes WCG. ??? I'm not sure this is true for all
1188 instructions that take WC registers. */
1189 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1200 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1201 return value is the register number or FAIL. */
1204 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1207 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1210 /* Do not allow a scalar (reg+index) to parse as a register. */
1211 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1214 if (reg
&& reg
->type
== type
)
1217 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1224 /* Parse a Neon type specifier. *STR should point at the leading '.'
1225 character. Does no verification at this stage that the type fits the opcode
1232 Can all be legally parsed by this function.
1234 Fills in neon_type struct pointer with parsed information, and updates STR
1235 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1236 type, FAIL if not. */
1239 parse_neon_type (struct neon_type
*type
, char **str
)
1246 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1248 enum neon_el_type thistype
= NT_untyped
;
1249 unsigned thissize
= -1u;
1256 /* Just a size without an explicit type. */
1260 switch (TOLOWER (*ptr
))
1262 case 'i': thistype
= NT_integer
; break;
1263 case 'f': thistype
= NT_float
; break;
1264 case 'p': thistype
= NT_poly
; break;
1265 case 's': thistype
= NT_signed
; break;
1266 case 'u': thistype
= NT_unsigned
; break;
1268 thistype
= NT_float
;
1273 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1279 /* .f is an abbreviation for .f32. */
1280 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1285 thissize
= strtoul (ptr
, &ptr
, 10);
1287 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1290 as_bad (_("bad size %d in type specifier"), thissize
);
1298 type
->el
[type
->elems
].type
= thistype
;
1299 type
->el
[type
->elems
].size
= thissize
;
1304 /* Empty/missing type is not a successful parse. */
1305 if (type
->elems
== 0)
1313 /* Errors may be set multiple times during parsing or bit encoding
1314 (particularly in the Neon bits), but usually the earliest error which is set
1315 will be the most meaningful. Avoid overwriting it with later (cascading)
1316 errors by calling this function. */
1319 first_error (const char *err
)
1325 /* Parse a single type, e.g. ".s32", leading period included. */
1327 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1330 struct neon_type optype
;
1334 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1336 if (optype
.elems
== 1)
1337 *vectype
= optype
.el
[0];
1340 first_error (_("only one type should be specified for operand"));
1346 first_error (_("vector type expected"));
1358 /* Special meanings for indices (which have a range of 0-7), which will fit into
1361 #define NEON_ALL_LANES 15
1362 #define NEON_INTERLEAVE_LANES 14
1364 /* Parse either a register or a scalar, with an optional type. Return the
1365 register number, and optionally fill in the actual type of the register
1366 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1367 type/index information in *TYPEINFO. */
1370 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1371 enum arm_reg_type
*rtype
,
1372 struct neon_typed_alias
*typeinfo
)
1375 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1376 struct neon_typed_alias atype
;
1377 struct neon_type_el parsetype
;
1381 atype
.eltype
.type
= NT_invtype
;
1382 atype
.eltype
.size
= -1;
1384 /* Try alternate syntax for some types of register. Note these are mutually
1385 exclusive with the Neon syntax extensions. */
1388 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1396 /* Undo polymorphism when a set of register types may be accepted. */
1397 if ((type
== REG_TYPE_NDQ
1398 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1399 || (type
== REG_TYPE_VFSD
1400 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1401 || (type
== REG_TYPE_NSDQ
1402 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1403 || reg
->type
== REG_TYPE_NQ
))
1404 || (type
== REG_TYPE_MMXWC
1405 && (reg
->type
== REG_TYPE_MMXWCG
)))
1406 type
= (enum arm_reg_type
) reg
->type
;
1408 if (type
!= reg
->type
)
1414 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1416 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1418 first_error (_("can't redefine type for operand"));
1421 atype
.defined
|= NTA_HASTYPE
;
1422 atype
.eltype
= parsetype
;
1425 if (skip_past_char (&str
, '[') == SUCCESS
)
1427 if (type
!= REG_TYPE_VFD
)
1429 first_error (_("only D registers may be indexed"));
1433 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1435 first_error (_("can't change index for operand"));
1439 atype
.defined
|= NTA_HASINDEX
;
1441 if (skip_past_char (&str
, ']') == SUCCESS
)
1442 atype
.index
= NEON_ALL_LANES
;
1447 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1449 if (exp
.X_op
!= O_constant
)
1451 first_error (_("constant expression required"));
1455 if (skip_past_char (&str
, ']') == FAIL
)
1458 atype
.index
= exp
.X_add_number
;
1473 /* Like arm_reg_parse, but allow allow the following extra features:
1474 - If RTYPE is non-zero, return the (possibly restricted) type of the
1475 register (e.g. Neon double or quad reg when either has been requested).
1476 - If this is a Neon vector type with additional type information, fill
1477 in the struct pointed to by VECTYPE (if non-NULL).
1478 This function will fault on encountering a scalar. */
1481 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1482 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1484 struct neon_typed_alias atype
;
1486 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1491 /* Do not allow regname(... to parse as a register. */
1495 /* Do not allow a scalar (reg+index) to parse as a register. */
1496 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1498 first_error (_("register operand expected, but got scalar"));
1503 *vectype
= atype
.eltype
;
1510 #define NEON_SCALAR_REG(X) ((X) >> 4)
1511 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1513 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1514 have enough information to be able to do a good job bounds-checking. So, we
1515 just do easy checks here, and do further checks later. */
1518 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1522 struct neon_typed_alias atype
;
1524 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1526 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1529 if (atype
.index
== NEON_ALL_LANES
)
1531 first_error (_("scalar must have an index"));
1534 else if (atype
.index
>= 64 / elsize
)
1536 first_error (_("scalar index out of range"));
1541 *type
= atype
.eltype
;
1545 return reg
* 16 + atype
.index
;
1548 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1551 parse_reg_list (char ** strp
)
1553 char * str
= * strp
;
1557 /* We come back here if we get ranges concatenated by '+' or '|'. */
1572 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1574 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1584 first_error (_("bad range in register list"));
1588 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1590 if (range
& (1 << i
))
1592 (_("Warning: duplicated register (r%d) in register list"),
1600 if (range
& (1 << reg
))
1601 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1603 else if (reg
<= cur_reg
)
1604 as_tsktsk (_("Warning: register range not in ascending order"));
1609 while (skip_past_comma (&str
) != FAIL
1610 || (in_range
= 1, *str
++ == '-'));
1615 first_error (_("missing `}'"));
1623 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1626 if (exp
.X_op
== O_constant
)
1628 if (exp
.X_add_number
1629 != (exp
.X_add_number
& 0x0000ffff))
1631 inst
.error
= _("invalid register mask");
1635 if ((range
& exp
.X_add_number
) != 0)
1637 int regno
= range
& exp
.X_add_number
;
1640 regno
= (1 << regno
) - 1;
1642 (_("Warning: duplicated register (r%d) in register list"),
1646 range
|= exp
.X_add_number
;
1650 if (inst
.reloc
.type
!= 0)
1652 inst
.error
= _("expression too complex");
1656 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1657 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1658 inst
.reloc
.pc_rel
= 0;
1662 if (*str
== '|' || *str
== '+')
1668 while (another_range
);
1674 /* Types of registers in a list. */
1683 /* Parse a VFP register list. If the string is invalid return FAIL.
1684 Otherwise return the number of registers, and set PBASE to the first
1685 register. Parses registers of type ETYPE.
1686 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1687 - Q registers can be used to specify pairs of D registers
1688 - { } can be omitted from around a singleton register list
1689 FIXME: This is not implemented, as it would require backtracking in
1692 This could be done (the meaning isn't really ambiguous), but doesn't
1693 fit in well with the current parsing framework.
1694 - 32 D registers may be used (also true for VFPv3).
1695 FIXME: Types are ignored in these register lists, which is probably a
1699 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1704 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1708 unsigned long mask
= 0;
1713 inst
.error
= _("expecting {");
1722 regtype
= REG_TYPE_VFS
;
1727 regtype
= REG_TYPE_VFD
;
1730 case REGLIST_NEON_D
:
1731 regtype
= REG_TYPE_NDQ
;
1735 if (etype
!= REGLIST_VFP_S
)
1737 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1738 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1742 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1745 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1752 base_reg
= max_regs
;
1756 int setmask
= 1, addregs
= 1;
1758 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1760 if (new_base
== FAIL
)
1762 first_error (_(reg_expected_msgs
[regtype
]));
1766 if (new_base
>= max_regs
)
1768 first_error (_("register out of range in list"));
1772 /* Note: a value of 2 * n is returned for the register Q<n>. */
1773 if (regtype
== REG_TYPE_NQ
)
1779 if (new_base
< base_reg
)
1780 base_reg
= new_base
;
1782 if (mask
& (setmask
<< new_base
))
1784 first_error (_("invalid register list"));
1788 if ((mask
>> new_base
) != 0 && ! warned
)
1790 as_tsktsk (_("register list not in ascending order"));
1794 mask
|= setmask
<< new_base
;
1797 if (*str
== '-') /* We have the start of a range expression */
1803 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1806 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1810 if (high_range
>= max_regs
)
1812 first_error (_("register out of range in list"));
1816 if (regtype
== REG_TYPE_NQ
)
1817 high_range
= high_range
+ 1;
1819 if (high_range
<= new_base
)
1821 inst
.error
= _("register range not in ascending order");
1825 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1827 if (mask
& (setmask
<< new_base
))
1829 inst
.error
= _("invalid register list");
1833 mask
|= setmask
<< new_base
;
1838 while (skip_past_comma (&str
) != FAIL
);
1842 /* Sanity check -- should have raised a parse error above. */
1843 if (count
== 0 || count
> max_regs
)
1848 /* Final test -- the registers must be consecutive. */
1850 for (i
= 0; i
< count
; i
++)
1852 if ((mask
& (1u << i
)) == 0)
1854 inst
.error
= _("non-contiguous register range");
1864 /* True if two alias types are the same. */
1867 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1875 if (a
->defined
!= b
->defined
)
1878 if ((a
->defined
& NTA_HASTYPE
) != 0
1879 && (a
->eltype
.type
!= b
->eltype
.type
1880 || a
->eltype
.size
!= b
->eltype
.size
))
1883 if ((a
->defined
& NTA_HASINDEX
) != 0
1884 && (a
->index
!= b
->index
))
1890 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1891 The base register is put in *PBASE.
1892 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1894 The register stride (minus one) is put in bit 4 of the return value.
1895 Bits [6:5] encode the list length (minus one).
1896 The type of the list elements is put in *ELTYPE, if non-NULL. */
1898 #define NEON_LANE(X) ((X) & 0xf)
1899 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1900 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1903 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1904 struct neon_type_el
*eltype
)
1911 int leading_brace
= 0;
1912 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1913 const char *const incr_error
= _("register stride must be 1 or 2");
1914 const char *const type_error
= _("mismatched element/structure types in list");
1915 struct neon_typed_alias firsttype
;
1917 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1922 struct neon_typed_alias atype
;
1923 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1927 first_error (_(reg_expected_msgs
[rtype
]));
1934 if (rtype
== REG_TYPE_NQ
)
1940 else if (reg_incr
== -1)
1942 reg_incr
= getreg
- base_reg
;
1943 if (reg_incr
< 1 || reg_incr
> 2)
1945 first_error (_(incr_error
));
1949 else if (getreg
!= base_reg
+ reg_incr
* count
)
1951 first_error (_(incr_error
));
1955 if (! neon_alias_types_same (&atype
, &firsttype
))
1957 first_error (_(type_error
));
1961 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1965 struct neon_typed_alias htype
;
1966 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1968 lane
= NEON_INTERLEAVE_LANES
;
1969 else if (lane
!= NEON_INTERLEAVE_LANES
)
1971 first_error (_(type_error
));
1976 else if (reg_incr
!= 1)
1978 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1982 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1985 first_error (_(reg_expected_msgs
[rtype
]));
1988 if (! neon_alias_types_same (&htype
, &firsttype
))
1990 first_error (_(type_error
));
1993 count
+= hireg
+ dregs
- getreg
;
1997 /* If we're using Q registers, we can't use [] or [n] syntax. */
1998 if (rtype
== REG_TYPE_NQ
)
2004 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2008 else if (lane
!= atype
.index
)
2010 first_error (_(type_error
));
2014 else if (lane
== -1)
2015 lane
= NEON_INTERLEAVE_LANES
;
2016 else if (lane
!= NEON_INTERLEAVE_LANES
)
2018 first_error (_(type_error
));
2023 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2025 /* No lane set by [x]. We must be interleaving structures. */
2027 lane
= NEON_INTERLEAVE_LANES
;
2030 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2031 || (count
> 1 && reg_incr
== -1))
2033 first_error (_("error parsing element/structure list"));
2037 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2039 first_error (_("expected }"));
2047 *eltype
= firsttype
.eltype
;
2052 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2055 /* Parse an explicit relocation suffix on an expression. This is
2056 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2057 arm_reloc_hsh contains no entries, so this function can only
2058 succeed if there is no () after the word. Returns -1 on error,
2059 BFD_RELOC_UNUSED if there wasn't any suffix. */
2062 parse_reloc (char **str
)
2064 struct reloc_entry
*r
;
2068 return BFD_RELOC_UNUSED
;
2073 while (*q
&& *q
!= ')' && *q
!= ',')
2078 if ((r
= (struct reloc_entry
*)
2079 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2086 /* Directives: register aliases. */
2088 static struct reg_entry
*
2089 insert_reg_alias (char *str
, unsigned number
, int type
)
2091 struct reg_entry
*new_reg
;
2094 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2096 if (new_reg
->builtin
)
2097 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2099 /* Only warn about a redefinition if it's not defined as the
2101 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2102 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2107 name
= xstrdup (str
);
2108 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2110 new_reg
->name
= name
;
2111 new_reg
->number
= number
;
2112 new_reg
->type
= type
;
2113 new_reg
->builtin
= FALSE
;
2114 new_reg
->neon
= NULL
;
2116 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2123 insert_neon_reg_alias (char *str
, int number
, int type
,
2124 struct neon_typed_alias
*atype
)
2126 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2130 first_error (_("attempt to redefine typed alias"));
2136 reg
->neon
= (struct neon_typed_alias
*)
2137 xmalloc (sizeof (struct neon_typed_alias
));
2138 *reg
->neon
= *atype
;
2142 /* Look for the .req directive. This is of the form:
2144 new_register_name .req existing_register_name
2146 If we find one, or if it looks sufficiently like one that we want to
2147 handle any error here, return TRUE. Otherwise return FALSE. */
2150 create_register_alias (char * newname
, char *p
)
2152 struct reg_entry
*old
;
2153 char *oldname
, *nbuf
;
2156 /* The input scrubber ensures that whitespace after the mnemonic is
2157 collapsed to single spaces. */
2159 if (strncmp (oldname
, " .req ", 6) != 0)
2163 if (*oldname
== '\0')
2166 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2169 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2173 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2174 the desired alias name, and p points to its end. If not, then
2175 the desired alias name is in the global original_case_string. */
2176 #ifdef TC_CASE_SENSITIVE
2179 newname
= original_case_string
;
2180 nlen
= strlen (newname
);
2183 nbuf
= (char *) alloca (nlen
+ 1);
2184 memcpy (nbuf
, newname
, nlen
);
2187 /* Create aliases under the new name as stated; an all-lowercase
2188 version of the new name; and an all-uppercase version of the new
2190 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2192 for (p
= nbuf
; *p
; p
++)
2195 if (strncmp (nbuf
, newname
, nlen
))
2197 /* If this attempt to create an additional alias fails, do not bother
2198 trying to create the all-lower case alias. We will fail and issue
2199 a second, duplicate error message. This situation arises when the
2200 programmer does something like:
2203 The second .req creates the "Foo" alias but then fails to create
2204 the artificial FOO alias because it has already been created by the
2206 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2210 for (p
= nbuf
; *p
; p
++)
2213 if (strncmp (nbuf
, newname
, nlen
))
2214 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2220 /* Create a Neon typed/indexed register alias using directives, e.g.:
2225 These typed registers can be used instead of the types specified after the
2226 Neon mnemonic, so long as all operands given have types. Types can also be
2227 specified directly, e.g.:
2228 vadd d0.s32, d1.s32, d2.s32 */
2231 create_neon_reg_alias (char *newname
, char *p
)
2233 enum arm_reg_type basetype
;
2234 struct reg_entry
*basereg
;
2235 struct reg_entry mybasereg
;
2236 struct neon_type ntype
;
2237 struct neon_typed_alias typeinfo
;
2238 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2241 typeinfo
.defined
= 0;
2242 typeinfo
.eltype
.type
= NT_invtype
;
2243 typeinfo
.eltype
.size
= -1;
2244 typeinfo
.index
= -1;
2248 if (strncmp (p
, " .dn ", 5) == 0)
2249 basetype
= REG_TYPE_VFD
;
2250 else if (strncmp (p
, " .qn ", 5) == 0)
2251 basetype
= REG_TYPE_NQ
;
2260 basereg
= arm_reg_parse_multi (&p
);
2262 if (basereg
&& basereg
->type
!= basetype
)
2264 as_bad (_("bad type for register"));
2268 if (basereg
== NULL
)
2271 /* Try parsing as an integer. */
2272 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2273 if (exp
.X_op
!= O_constant
)
2275 as_bad (_("expression must be constant"));
2278 basereg
= &mybasereg
;
2279 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2285 typeinfo
= *basereg
->neon
;
2287 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2289 /* We got a type. */
2290 if (typeinfo
.defined
& NTA_HASTYPE
)
2292 as_bad (_("can't redefine the type of a register alias"));
2296 typeinfo
.defined
|= NTA_HASTYPE
;
2297 if (ntype
.elems
!= 1)
2299 as_bad (_("you must specify a single type only"));
2302 typeinfo
.eltype
= ntype
.el
[0];
2305 if (skip_past_char (&p
, '[') == SUCCESS
)
2308 /* We got a scalar index. */
2310 if (typeinfo
.defined
& NTA_HASINDEX
)
2312 as_bad (_("can't redefine the index of a scalar alias"));
2316 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2318 if (exp
.X_op
!= O_constant
)
2320 as_bad (_("scalar index must be constant"));
2324 typeinfo
.defined
|= NTA_HASINDEX
;
2325 typeinfo
.index
= exp
.X_add_number
;
2327 if (skip_past_char (&p
, ']') == FAIL
)
2329 as_bad (_("expecting ]"));
2334 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2335 the desired alias name, and p points to its end. If not, then
2336 the desired alias name is in the global original_case_string. */
2337 #ifdef TC_CASE_SENSITIVE
2338 namelen
= nameend
- newname
;
2340 newname
= original_case_string
;
2341 namelen
= strlen (newname
);
2344 namebuf
= (char *) alloca (namelen
+ 1);
2345 strncpy (namebuf
, newname
, namelen
);
2346 namebuf
[namelen
] = '\0';
2348 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2349 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2351 /* Insert name in all uppercase. */
2352 for (p
= namebuf
; *p
; p
++)
2355 if (strncmp (namebuf
, newname
, namelen
))
2356 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2357 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2359 /* Insert name in all lowercase. */
2360 for (p
= namebuf
; *p
; p
++)
2363 if (strncmp (namebuf
, newname
, namelen
))
2364 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2365 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2370 /* Should never be called, as .req goes between the alias and the
2371 register name, not at the beginning of the line. */
2374 s_req (int a ATTRIBUTE_UNUSED
)
2376 as_bad (_("invalid syntax for .req directive"));
2380 s_dn (int a ATTRIBUTE_UNUSED
)
2382 as_bad (_("invalid syntax for .dn directive"));
2386 s_qn (int a ATTRIBUTE_UNUSED
)
2388 as_bad (_("invalid syntax for .qn directive"));
2391 /* The .unreq directive deletes an alias which was previously defined
2392 by .req. For example:
2398 s_unreq (int a ATTRIBUTE_UNUSED
)
2403 name
= input_line_pointer
;
2405 while (*input_line_pointer
!= 0
2406 && *input_line_pointer
!= ' '
2407 && *input_line_pointer
!= '\n')
2408 ++input_line_pointer
;
2410 saved_char
= *input_line_pointer
;
2411 *input_line_pointer
= 0;
2414 as_bad (_("invalid syntax for .unreq directive"));
2417 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2421 as_bad (_("unknown register alias '%s'"), name
);
2422 else if (reg
->builtin
)
2423 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2430 hash_delete (arm_reg_hsh
, name
, FALSE
);
2431 free ((char *) reg
->name
);
2436 /* Also locate the all upper case and all lower case versions.
2437 Do not complain if we cannot find one or the other as it
2438 was probably deleted above. */
2440 nbuf
= strdup (name
);
2441 for (p
= nbuf
; *p
; p
++)
2443 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2446 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2447 free ((char *) reg
->name
);
2453 for (p
= nbuf
; *p
; p
++)
2455 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2458 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2459 free ((char *) reg
->name
);
2469 *input_line_pointer
= saved_char
;
2470 demand_empty_rest_of_line ();
2473 /* Directives: Instruction set selection. */
2476 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2477 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2478 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2479 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2481 /* Create a new mapping symbol for the transition to STATE. */
2484 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2487 const char * symname
;
2494 type
= BSF_NO_FLAGS
;
2498 type
= BSF_NO_FLAGS
;
2502 type
= BSF_NO_FLAGS
;
2508 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2509 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2514 THUMB_SET_FUNC (symbolP
, 0);
2515 ARM_SET_THUMB (symbolP
, 0);
2516 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2520 THUMB_SET_FUNC (symbolP
, 1);
2521 ARM_SET_THUMB (symbolP
, 1);
2522 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2530 /* Save the mapping symbols for future reference. Also check that
2531 we do not place two mapping symbols at the same offset within a
2532 frag. We'll handle overlap between frags in
2533 check_mapping_symbols.
2535 If .fill or other data filling directive generates zero sized data,
2536 the mapping symbol for the following code will have the same value
2537 as the one generated for the data filling directive. In this case,
2538 we replace the old symbol with the new one at the same address. */
2541 if (frag
->tc_frag_data
.first_map
!= NULL
)
2543 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2544 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2546 frag
->tc_frag_data
.first_map
= symbolP
;
2548 if (frag
->tc_frag_data
.last_map
!= NULL
)
2550 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2551 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2552 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2554 frag
->tc_frag_data
.last_map
= symbolP
;
2557 /* We must sometimes convert a region marked as code to data during
2558 code alignment, if an odd number of bytes have to be padded. The
2559 code mapping symbol is pushed to an aligned address. */
2562 insert_data_mapping_symbol (enum mstate state
,
2563 valueT value
, fragS
*frag
, offsetT bytes
)
2565 /* If there was already a mapping symbol, remove it. */
2566 if (frag
->tc_frag_data
.last_map
!= NULL
2567 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2569 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2573 know (frag
->tc_frag_data
.first_map
== symp
);
2574 frag
->tc_frag_data
.first_map
= NULL
;
2576 frag
->tc_frag_data
.last_map
= NULL
;
2577 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2580 make_mapping_symbol (MAP_DATA
, value
, frag
);
2581 make_mapping_symbol (state
, value
+ bytes
, frag
);
2584 static void mapping_state_2 (enum mstate state
, int max_chars
);
2586 /* Set the mapping state to STATE. Only call this when about to
2587 emit some STATE bytes to the file. */
2590 mapping_state (enum mstate state
)
2592 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2594 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2596 if (mapstate
== state
)
2597 /* The mapping symbol has already been emitted.
2598 There is nothing else to do. */
2601 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2603 All ARM instructions require 4-byte alignment.
2604 (Almost) all Thumb instructions require 2-byte alignment.
2606 When emitting instructions into any section, mark the section
2609 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2610 but themselves require 2-byte alignment; this applies to some
2611 PC- relative forms. However, these cases will invovle implicit
2612 literal pool generation or an explicit .align >=2, both of
2613 which will cause the section to me marked with sufficient
2614 alignment. Thus, we don't handle those cases here. */
2615 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2617 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2618 /* This case will be evaluated later in the next else. */
2620 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2621 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2623 /* Only add the symbol if the offset is > 0:
2624 if we're at the first frag, check it's size > 0;
2625 if we're not at the first frag, then for sure
2626 the offset is > 0. */
2627 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2628 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2631 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2634 mapping_state_2 (state
, 0);
2638 /* Same as mapping_state, but MAX_CHARS bytes have already been
2639 allocated. Put the mapping symbol that far back. */
2642 mapping_state_2 (enum mstate state
, int max_chars
)
2644 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2646 if (!SEG_NORMAL (now_seg
))
2649 if (mapstate
== state
)
2650 /* The mapping symbol has already been emitted.
2651 There is nothing else to do. */
2654 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2655 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2658 #define mapping_state(x) ((void)0)
2659 #define mapping_state_2(x, y) ((void)0)
2662 /* Find the real, Thumb encoded start of a Thumb function. */
2666 find_real_start (symbolS
* symbolP
)
2669 const char * name
= S_GET_NAME (symbolP
);
2670 symbolS
* new_target
;
2672 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2673 #define STUB_NAME ".real_start_of"
2678 /* The compiler may generate BL instructions to local labels because
2679 it needs to perform a branch to a far away location. These labels
2680 do not have a corresponding ".real_start_of" label. We check
2681 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2682 the ".real_start_of" convention for nonlocal branches. */
2683 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2686 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2687 new_target
= symbol_find (real_start
);
2689 if (new_target
== NULL
)
2691 as_warn (_("Failed to find real start of function: %s\n"), name
);
2692 new_target
= symbolP
;
2700 opcode_select (int width
)
2707 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2708 as_bad (_("selected processor does not support THUMB opcodes"));
2711 /* No need to force the alignment, since we will have been
2712 coming from ARM mode, which is word-aligned. */
2713 record_alignment (now_seg
, 1);
2720 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2721 as_bad (_("selected processor does not support ARM opcodes"));
2726 frag_align (2, 0, 0);
2728 record_alignment (now_seg
, 1);
2733 as_bad (_("invalid instruction size selected (%d)"), width
);
2738 s_arm (int ignore ATTRIBUTE_UNUSED
)
2741 demand_empty_rest_of_line ();
2745 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2748 demand_empty_rest_of_line ();
2752 s_code (int unused ATTRIBUTE_UNUSED
)
2756 temp
= get_absolute_expression ();
2761 opcode_select (temp
);
2765 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2770 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2772 /* If we are not already in thumb mode go into it, EVEN if
2773 the target processor does not support thumb instructions.
2774 This is used by gcc/config/arm/lib1funcs.asm for example
2775 to compile interworking support functions even if the
2776 target processor should not support interworking. */
2780 record_alignment (now_seg
, 1);
2783 demand_empty_rest_of_line ();
2787 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2791 /* The following label is the name/address of the start of a Thumb function.
2792 We need to know this for the interworking support. */
2793 label_is_thumb_function_name
= TRUE
;
2796 /* Perform a .set directive, but also mark the alias as
2797 being a thumb function. */
2800 s_thumb_set (int equiv
)
2802 /* XXX the following is a duplicate of the code for s_set() in read.c
2803 We cannot just call that code as we need to get at the symbol that
2810 /* Especial apologies for the random logic:
2811 This just grew, and could be parsed much more simply!
2813 name
= input_line_pointer
;
2814 delim
= get_symbol_end ();
2815 end_name
= input_line_pointer
;
2818 if (*input_line_pointer
!= ',')
2821 as_bad (_("expected comma after name \"%s\""), name
);
2823 ignore_rest_of_line ();
2827 input_line_pointer
++;
2830 if (name
[0] == '.' && name
[1] == '\0')
2832 /* XXX - this should not happen to .thumb_set. */
2836 if ((symbolP
= symbol_find (name
)) == NULL
2837 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2840 /* When doing symbol listings, play games with dummy fragments living
2841 outside the normal fragment chain to record the file and line info
2843 if (listing
& LISTING_SYMBOLS
)
2845 extern struct list_info_struct
* listing_tail
;
2846 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2848 memset (dummy_frag
, 0, sizeof (fragS
));
2849 dummy_frag
->fr_type
= rs_fill
;
2850 dummy_frag
->line
= listing_tail
;
2851 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2852 dummy_frag
->fr_symbol
= symbolP
;
2856 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2859 /* "set" symbols are local unless otherwise specified. */
2860 SF_SET_LOCAL (symbolP
);
2861 #endif /* OBJ_COFF */
2862 } /* Make a new symbol. */
2864 symbol_table_insert (symbolP
);
2869 && S_IS_DEFINED (symbolP
)
2870 && S_GET_SEGMENT (symbolP
) != reg_section
)
2871 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2873 pseudo_set (symbolP
);
2875 demand_empty_rest_of_line ();
2877 /* XXX Now we come to the Thumb specific bit of code. */
2879 THUMB_SET_FUNC (symbolP
, 1);
2880 ARM_SET_THUMB (symbolP
, 1);
2881 #if defined OBJ_ELF || defined OBJ_COFF
2882 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2886 /* Directives: Mode selection. */
2888 /* .syntax [unified|divided] - choose the new unified syntax
2889 (same for Arm and Thumb encoding, modulo slight differences in what
2890 can be represented) or the old divergent syntax for each mode. */
2892 s_syntax (int unused ATTRIBUTE_UNUSED
)
2896 name
= input_line_pointer
;
2897 delim
= get_symbol_end ();
2899 if (!strcasecmp (name
, "unified"))
2900 unified_syntax
= TRUE
;
2901 else if (!strcasecmp (name
, "divided"))
2902 unified_syntax
= FALSE
;
2905 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2908 *input_line_pointer
= delim
;
2909 demand_empty_rest_of_line ();
2912 /* Directives: sectioning and alignment. */
2914 /* Same as s_align_ptwo but align 0 => align 2. */
2917 s_align (int unused ATTRIBUTE_UNUSED
)
2922 long max_alignment
= 15;
2924 temp
= get_absolute_expression ();
2925 if (temp
> max_alignment
)
2926 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2929 as_bad (_("alignment negative. 0 assumed."));
2933 if (*input_line_pointer
== ',')
2935 input_line_pointer
++;
2936 temp_fill
= get_absolute_expression ();
2948 /* Only make a frag if we HAVE to. */
2949 if (temp
&& !need_pass_2
)
2951 if (!fill_p
&& subseg_text_p (now_seg
))
2952 frag_align_code (temp
, 0);
2954 frag_align (temp
, (int) temp_fill
, 0);
2956 demand_empty_rest_of_line ();
2958 record_alignment (now_seg
, temp
);
2962 s_bss (int ignore ATTRIBUTE_UNUSED
)
2964 /* We don't support putting frags in the BSS segment, we fake it by
2965 marking in_bss, then looking at s_skip for clues. */
2966 subseg_set (bss_section
, 0);
2967 demand_empty_rest_of_line ();
2969 #ifdef md_elf_section_change_hook
2970 md_elf_section_change_hook ();
2975 s_even (int ignore ATTRIBUTE_UNUSED
)
2977 /* Never make frag if expect extra pass. */
2979 frag_align (1, 0, 0);
2981 record_alignment (now_seg
, 1);
2983 demand_empty_rest_of_line ();
2986 /* Directives: Literal pools. */
2988 static literal_pool
*
2989 find_literal_pool (void)
2991 literal_pool
* pool
;
2993 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2995 if (pool
->section
== now_seg
2996 && pool
->sub_section
== now_subseg
)
3003 static literal_pool
*
3004 find_or_make_literal_pool (void)
3006 /* Next literal pool ID number. */
3007 static unsigned int latest_pool_num
= 1;
3008 literal_pool
* pool
;
3010 pool
= find_literal_pool ();
3014 /* Create a new pool. */
3015 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3019 pool
->next_free_entry
= 0;
3020 pool
->section
= now_seg
;
3021 pool
->sub_section
= now_subseg
;
3022 pool
->next
= list_of_pools
;
3023 pool
->symbol
= NULL
;
3025 /* Add it to the list. */
3026 list_of_pools
= pool
;
3029 /* New pools, and emptied pools, will have a NULL symbol. */
3030 if (pool
->symbol
== NULL
)
3032 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3033 (valueT
) 0, &zero_address_frag
);
3034 pool
->id
= latest_pool_num
++;
3041 /* Add the literal in the global 'inst'
3042 structure to the relevant literal pool. */
3045 add_to_lit_pool (void)
3047 literal_pool
* pool
;
3050 pool
= find_or_make_literal_pool ();
3052 /* Check if this literal value is already in the pool. */
3053 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3055 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3056 && (inst
.reloc
.exp
.X_op
== O_constant
)
3057 && (pool
->literals
[entry
].X_add_number
3058 == inst
.reloc
.exp
.X_add_number
)
3059 && (pool
->literals
[entry
].X_unsigned
3060 == inst
.reloc
.exp
.X_unsigned
))
3063 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3064 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3065 && (pool
->literals
[entry
].X_add_number
3066 == inst
.reloc
.exp
.X_add_number
)
3067 && (pool
->literals
[entry
].X_add_symbol
3068 == inst
.reloc
.exp
.X_add_symbol
)
3069 && (pool
->literals
[entry
].X_op_symbol
3070 == inst
.reloc
.exp
.X_op_symbol
))
3074 /* Do we need to create a new entry? */
3075 if (entry
== pool
->next_free_entry
)
3077 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3079 inst
.error
= _("literal pool overflow");
3083 pool
->literals
[entry
] = inst
.reloc
.exp
;
3085 /* PR ld/12974: Record the location of the first source line to reference
3086 this entry in the literal pool. If it turns out during linking that the
3087 symbol does not exist we will be able to give an accurate line number for
3088 the (first use of the) missing reference. */
3089 if (debug_type
== DEBUG_DWARF2
)
3090 dwarf2_where (pool
->locs
+ entry
);
3092 pool
->next_free_entry
+= 1;
3095 inst
.reloc
.exp
.X_op
= O_symbol
;
3096 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3097 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3102 /* Can't use symbol_new here, so have to create a symbol and then at
3103 a later date assign it a value. Thats what these functions do. */
3106 symbol_locate (symbolS
* symbolP
,
3107 const char * name
, /* It is copied, the caller can modify. */
3108 segT segment
, /* Segment identifier (SEG_<something>). */
3109 valueT valu
, /* Symbol value. */
3110 fragS
* frag
) /* Associated fragment. */
3112 unsigned int name_length
;
3113 char * preserved_copy_of_name
;
3115 name_length
= strlen (name
) + 1; /* +1 for \0. */
3116 obstack_grow (¬es
, name
, name_length
);
3117 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3119 #ifdef tc_canonicalize_symbol_name
3120 preserved_copy_of_name
=
3121 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3124 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3126 S_SET_SEGMENT (symbolP
, segment
);
3127 S_SET_VALUE (symbolP
, valu
);
3128 symbol_clear_list_pointers (symbolP
);
3130 symbol_set_frag (symbolP
, frag
);
3132 /* Link to end of symbol chain. */
3134 extern int symbol_table_frozen
;
3136 if (symbol_table_frozen
)
3140 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3142 obj_symbol_new_hook (symbolP
);
3144 #ifdef tc_symbol_new_hook
3145 tc_symbol_new_hook (symbolP
);
3149 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3150 #endif /* DEBUG_SYMS */
3155 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3158 literal_pool
* pool
;
3161 pool
= find_literal_pool ();
3163 || pool
->symbol
== NULL
3164 || pool
->next_free_entry
== 0)
3167 mapping_state (MAP_DATA
);
3169 /* Align pool as you have word accesses.
3170 Only make a frag if we have to. */
3172 frag_align (2, 0, 0);
3174 record_alignment (now_seg
, 2);
3176 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3178 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3179 (valueT
) frag_now_fix (), frag_now
);
3180 symbol_table_insert (pool
->symbol
);
3182 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3184 #if defined OBJ_COFF || defined OBJ_ELF
3185 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3188 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3191 if (debug_type
== DEBUG_DWARF2
)
3192 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3194 /* First output the expression in the instruction to the pool. */
3195 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3198 /* Mark the pool as empty. */
3199 pool
->next_free_entry
= 0;
3200 pool
->symbol
= NULL
;
3204 /* Forward declarations for functions below, in the MD interface
3206 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3207 static valueT
create_unwind_entry (int);
3208 static void start_unwind_section (const segT
, int);
3209 static void add_unwind_opcode (valueT
, int);
3210 static void flush_pending_unwind (void);
3212 /* Directives: Data. */
3215 s_arm_elf_cons (int nbytes
)
3219 #ifdef md_flush_pending_output
3220 md_flush_pending_output ();
3223 if (is_it_end_of_statement ())
3225 demand_empty_rest_of_line ();
3229 #ifdef md_cons_align
3230 md_cons_align (nbytes
);
3233 mapping_state (MAP_DATA
);
3237 char *base
= input_line_pointer
;
3241 if (exp
.X_op
!= O_symbol
)
3242 emit_expr (&exp
, (unsigned int) nbytes
);
3245 char *before_reloc
= input_line_pointer
;
3246 reloc
= parse_reloc (&input_line_pointer
);
3249 as_bad (_("unrecognized relocation suffix"));
3250 ignore_rest_of_line ();
3253 else if (reloc
== BFD_RELOC_UNUSED
)
3254 emit_expr (&exp
, (unsigned int) nbytes
);
3257 reloc_howto_type
*howto
= (reloc_howto_type
*)
3258 bfd_reloc_type_lookup (stdoutput
,
3259 (bfd_reloc_code_real_type
) reloc
);
3260 int size
= bfd_get_reloc_size (howto
);
3262 if (reloc
== BFD_RELOC_ARM_PLT32
)
3264 as_bad (_("(plt) is only valid on branch targets"));
3265 reloc
= BFD_RELOC_UNUSED
;
3270 as_bad (_("%s relocations do not fit in %d bytes"),
3271 howto
->name
, nbytes
);
3274 /* We've parsed an expression stopping at O_symbol.
3275 But there may be more expression left now that we
3276 have parsed the relocation marker. Parse it again.
3277 XXX Surely there is a cleaner way to do this. */
3278 char *p
= input_line_pointer
;
3280 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3281 memcpy (save_buf
, base
, input_line_pointer
- base
);
3282 memmove (base
+ (input_line_pointer
- before_reloc
),
3283 base
, before_reloc
- base
);
3285 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3287 memcpy (base
, save_buf
, p
- base
);
3289 offset
= nbytes
- size
;
3290 p
= frag_more ((int) nbytes
);
3291 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3292 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3297 while (*input_line_pointer
++ == ',');
3299 /* Put terminator back into stream. */
3300 input_line_pointer
--;
3301 demand_empty_rest_of_line ();
3304 /* Emit an expression containing a 32-bit thumb instruction.
3305 Implementation based on put_thumb32_insn. */
3308 emit_thumb32_expr (expressionS
* exp
)
3310 expressionS exp_high
= *exp
;
3312 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3313 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3314 exp
->X_add_number
&= 0xffff;
3315 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3318 /* Guess the instruction size based on the opcode. */
3321 thumb_insn_size (int opcode
)
3323 if ((unsigned int) opcode
< 0xe800u
)
3325 else if ((unsigned int) opcode
>= 0xe8000000u
)
3332 emit_insn (expressionS
*exp
, int nbytes
)
3336 if (exp
->X_op
== O_constant
)
3341 size
= thumb_insn_size (exp
->X_add_number
);
3345 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3347 as_bad (_(".inst.n operand too big. "\
3348 "Use .inst.w instead"));
3353 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3354 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3356 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3358 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3359 emit_thumb32_expr (exp
);
3361 emit_expr (exp
, (unsigned int) size
);
3363 it_fsm_post_encode ();
3367 as_bad (_("cannot determine Thumb instruction size. " \
3368 "Use .inst.n/.inst.w instead"));
3371 as_bad (_("constant expression required"));
3376 /* Like s_arm_elf_cons but do not use md_cons_align and
3377 set the mapping state to MAP_ARM/MAP_THUMB. */
3380 s_arm_elf_inst (int nbytes
)
3382 if (is_it_end_of_statement ())
3384 demand_empty_rest_of_line ();
3388 /* Calling mapping_state () here will not change ARM/THUMB,
3389 but will ensure not to be in DATA state. */
3392 mapping_state (MAP_THUMB
);
3397 as_bad (_("width suffixes are invalid in ARM mode"));
3398 ignore_rest_of_line ();
3404 mapping_state (MAP_ARM
);
3413 if (! emit_insn (& exp
, nbytes
))
3415 ignore_rest_of_line ();
3419 while (*input_line_pointer
++ == ',');
3421 /* Put terminator back into stream. */
3422 input_line_pointer
--;
3423 demand_empty_rest_of_line ();
3426 /* Parse a .rel31 directive. */
3429 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3436 if (*input_line_pointer
== '1')
3437 highbit
= 0x80000000;
3438 else if (*input_line_pointer
!= '0')
3439 as_bad (_("expected 0 or 1"));
3441 input_line_pointer
++;
3442 if (*input_line_pointer
!= ',')
3443 as_bad (_("missing comma"));
3444 input_line_pointer
++;
3446 #ifdef md_flush_pending_output
3447 md_flush_pending_output ();
3450 #ifdef md_cons_align
3454 mapping_state (MAP_DATA
);
3459 md_number_to_chars (p
, highbit
, 4);
3460 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3461 BFD_RELOC_ARM_PREL31
);
3463 demand_empty_rest_of_line ();
3466 /* Directives: AEABI stack-unwind tables. */
3468 /* Parse an unwind_fnstart directive. Simply records the current location. */
3471 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3473 demand_empty_rest_of_line ();
3474 if (unwind
.proc_start
)
3476 as_bad (_("duplicate .fnstart directive"));
3480 /* Mark the start of the function. */
3481 unwind
.proc_start
= expr_build_dot ();
3483 /* Reset the rest of the unwind info. */
3484 unwind
.opcode_count
= 0;
3485 unwind
.table_entry
= NULL
;
3486 unwind
.personality_routine
= NULL
;
3487 unwind
.personality_index
= -1;
3488 unwind
.frame_size
= 0;
3489 unwind
.fp_offset
= 0;
3490 unwind
.fp_reg
= REG_SP
;
3492 unwind
.sp_restored
= 0;
3496 /* Parse a handlerdata directive. Creates the exception handling table entry
3497 for the function. */
3500 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3502 demand_empty_rest_of_line ();
3503 if (!unwind
.proc_start
)
3504 as_bad (MISSING_FNSTART
);
3506 if (unwind
.table_entry
)
3507 as_bad (_("duplicate .handlerdata directive"));
3509 create_unwind_entry (1);
3512 /* Parse an unwind_fnend directive. Generates the index table entry. */
3515 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3520 unsigned int marked_pr_dependency
;
3522 demand_empty_rest_of_line ();
3524 if (!unwind
.proc_start
)
3526 as_bad (_(".fnend directive without .fnstart"));
3530 /* Add eh table entry. */
3531 if (unwind
.table_entry
== NULL
)
3532 val
= create_unwind_entry (0);
3536 /* Add index table entry. This is two words. */
3537 start_unwind_section (unwind
.saved_seg
, 1);
3538 frag_align (2, 0, 0);
3539 record_alignment (now_seg
, 2);
3541 ptr
= frag_more (8);
3542 where
= frag_now_fix () - 8;
3544 /* Self relative offset of the function start. */
3545 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3546 BFD_RELOC_ARM_PREL31
);
3548 /* Indicate dependency on EHABI-defined personality routines to the
3549 linker, if it hasn't been done already. */
3550 marked_pr_dependency
3551 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3552 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3553 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3555 static const char *const name
[] =
3557 "__aeabi_unwind_cpp_pr0",
3558 "__aeabi_unwind_cpp_pr1",
3559 "__aeabi_unwind_cpp_pr2"
3561 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3562 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3563 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3564 |= 1 << unwind
.personality_index
;
3568 /* Inline exception table entry. */
3569 md_number_to_chars (ptr
+ 4, val
, 4);
3571 /* Self relative offset of the table entry. */
3572 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3573 BFD_RELOC_ARM_PREL31
);
3575 /* Restore the original section. */
3576 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3578 unwind
.proc_start
= NULL
;
3582 /* Parse an unwind_cantunwind directive. */
3585 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3587 demand_empty_rest_of_line ();
3588 if (!unwind
.proc_start
)
3589 as_bad (MISSING_FNSTART
);
3591 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3592 as_bad (_("personality routine specified for cantunwind frame"));
3594 unwind
.personality_index
= -2;
3598 /* Parse a personalityindex directive. */
3601 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3605 if (!unwind
.proc_start
)
3606 as_bad (MISSING_FNSTART
);
3608 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3609 as_bad (_("duplicate .personalityindex directive"));
3613 if (exp
.X_op
!= O_constant
3614 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3616 as_bad (_("bad personality routine number"));
3617 ignore_rest_of_line ();
3621 unwind
.personality_index
= exp
.X_add_number
;
3623 demand_empty_rest_of_line ();
3627 /* Parse a personality directive. */
3630 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3634 if (!unwind
.proc_start
)
3635 as_bad (MISSING_FNSTART
);
3637 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3638 as_bad (_("duplicate .personality directive"));
3640 name
= input_line_pointer
;
3641 c
= get_symbol_end ();
3642 p
= input_line_pointer
;
3643 unwind
.personality_routine
= symbol_find_or_make (name
);
3645 demand_empty_rest_of_line ();
3649 /* Parse a directive saving core registers. */
3652 s_arm_unwind_save_core (void)
3658 range
= parse_reg_list (&input_line_pointer
);
3661 as_bad (_("expected register list"));
3662 ignore_rest_of_line ();
3666 demand_empty_rest_of_line ();
3668 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3669 into .unwind_save {..., sp...}. We aren't bothered about the value of
3670 ip because it is clobbered by calls. */
3671 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3672 && (range
& 0x3000) == 0x1000)
3674 unwind
.opcode_count
--;
3675 unwind
.sp_restored
= 0;
3676 range
= (range
| 0x2000) & ~0x1000;
3677 unwind
.pending_offset
= 0;
3683 /* See if we can use the short opcodes. These pop a block of up to 8
3684 registers starting with r4, plus maybe r14. */
3685 for (n
= 0; n
< 8; n
++)
3687 /* Break at the first non-saved register. */
3688 if ((range
& (1 << (n
+ 4))) == 0)
3691 /* See if there are any other bits set. */
3692 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3694 /* Use the long form. */
3695 op
= 0x8000 | ((range
>> 4) & 0xfff);
3696 add_unwind_opcode (op
, 2);
3700 /* Use the short form. */
3702 op
= 0xa8; /* Pop r14. */
3704 op
= 0xa0; /* Do not pop r14. */
3706 add_unwind_opcode (op
, 1);
3713 op
= 0xb100 | (range
& 0xf);
3714 add_unwind_opcode (op
, 2);
3717 /* Record the number of bytes pushed. */
3718 for (n
= 0; n
< 16; n
++)
3720 if (range
& (1 << n
))
3721 unwind
.frame_size
+= 4;
3726 /* Parse a directive saving FPA registers. */
3729 s_arm_unwind_save_fpa (int reg
)
3735 /* Get Number of registers to transfer. */
3736 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3739 exp
.X_op
= O_illegal
;
3741 if (exp
.X_op
!= O_constant
)
3743 as_bad (_("expected , <constant>"));
3744 ignore_rest_of_line ();
3748 num_regs
= exp
.X_add_number
;
3750 if (num_regs
< 1 || num_regs
> 4)
3752 as_bad (_("number of registers must be in the range [1:4]"));
3753 ignore_rest_of_line ();
3757 demand_empty_rest_of_line ();
3762 op
= 0xb4 | (num_regs
- 1);
3763 add_unwind_opcode (op
, 1);
3768 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3769 add_unwind_opcode (op
, 2);
3771 unwind
.frame_size
+= num_regs
* 12;
3775 /* Parse a directive saving VFP registers for ARMv6 and above. */
3778 s_arm_unwind_save_vfp_armv6 (void)
3783 int num_vfpv3_regs
= 0;
3784 int num_regs_below_16
;
3786 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3789 as_bad (_("expected register list"));
3790 ignore_rest_of_line ();
3794 demand_empty_rest_of_line ();
3796 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3797 than FSTMX/FLDMX-style ones). */
3799 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3801 num_vfpv3_regs
= count
;
3802 else if (start
+ count
> 16)
3803 num_vfpv3_regs
= start
+ count
- 16;
3805 if (num_vfpv3_regs
> 0)
3807 int start_offset
= start
> 16 ? start
- 16 : 0;
3808 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3809 add_unwind_opcode (op
, 2);
3812 /* Generate opcode for registers numbered in the range 0 .. 15. */
3813 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3814 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3815 if (num_regs_below_16
> 0)
3817 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3818 add_unwind_opcode (op
, 2);
3821 unwind
.frame_size
+= count
* 8;
3825 /* Parse a directive saving VFP registers for pre-ARMv6. */
3828 s_arm_unwind_save_vfp (void)
3834 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3837 as_bad (_("expected register list"));
3838 ignore_rest_of_line ();
3842 demand_empty_rest_of_line ();
3847 op
= 0xb8 | (count
- 1);
3848 add_unwind_opcode (op
, 1);
3853 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3854 add_unwind_opcode (op
, 2);
3856 unwind
.frame_size
+= count
* 8 + 4;
3860 /* Parse a directive saving iWMMXt data registers. */
3863 s_arm_unwind_save_mmxwr (void)
3871 if (*input_line_pointer
== '{')
3872 input_line_pointer
++;
3876 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3880 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3885 as_tsktsk (_("register list not in ascending order"));
3888 if (*input_line_pointer
== '-')
3890 input_line_pointer
++;
3891 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3894 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3897 else if (reg
>= hi_reg
)
3899 as_bad (_("bad register range"));
3902 for (; reg
< hi_reg
; reg
++)
3906 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3908 if (*input_line_pointer
== '}')
3909 input_line_pointer
++;
3911 demand_empty_rest_of_line ();
3913 /* Generate any deferred opcodes because we're going to be looking at
3915 flush_pending_unwind ();
3917 for (i
= 0; i
< 16; i
++)
3919 if (mask
& (1 << i
))
3920 unwind
.frame_size
+= 8;
3923 /* Attempt to combine with a previous opcode. We do this because gcc
3924 likes to output separate unwind directives for a single block of
3926 if (unwind
.opcode_count
> 0)
3928 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3929 if ((i
& 0xf8) == 0xc0)
3932 /* Only merge if the blocks are contiguous. */
3935 if ((mask
& 0xfe00) == (1 << 9))
3937 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3938 unwind
.opcode_count
--;
3941 else if (i
== 6 && unwind
.opcode_count
>= 2)
3943 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3947 op
= 0xffff << (reg
- 1);
3949 && ((mask
& op
) == (1u << (reg
- 1))))
3951 op
= (1 << (reg
+ i
+ 1)) - 1;
3952 op
&= ~((1 << reg
) - 1);
3954 unwind
.opcode_count
-= 2;
3961 /* We want to generate opcodes in the order the registers have been
3962 saved, ie. descending order. */
3963 for (reg
= 15; reg
>= -1; reg
--)
3965 /* Save registers in blocks. */
3967 || !(mask
& (1 << reg
)))
3969 /* We found an unsaved reg. Generate opcodes to save the
3976 op
= 0xc0 | (hi_reg
- 10);
3977 add_unwind_opcode (op
, 1);
3982 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3983 add_unwind_opcode (op
, 2);
3992 ignore_rest_of_line ();
3996 s_arm_unwind_save_mmxwcg (void)
4003 if (*input_line_pointer
== '{')
4004 input_line_pointer
++;
4008 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4012 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4018 as_tsktsk (_("register list not in ascending order"));
4021 if (*input_line_pointer
== '-')
4023 input_line_pointer
++;
4024 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4027 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4030 else if (reg
>= hi_reg
)
4032 as_bad (_("bad register range"));
4035 for (; reg
< hi_reg
; reg
++)
4039 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4041 if (*input_line_pointer
== '}')
4042 input_line_pointer
++;
4044 demand_empty_rest_of_line ();
4046 /* Generate any deferred opcodes because we're going to be looking at
4048 flush_pending_unwind ();
4050 for (reg
= 0; reg
< 16; reg
++)
4052 if (mask
& (1 << reg
))
4053 unwind
.frame_size
+= 4;
4056 add_unwind_opcode (op
, 2);
4059 ignore_rest_of_line ();
4063 /* Parse an unwind_save directive.
4064 If the argument is non-zero, this is a .vsave directive. */
4067 s_arm_unwind_save (int arch_v6
)
4070 struct reg_entry
*reg
;
4071 bfd_boolean had_brace
= FALSE
;
4073 if (!unwind
.proc_start
)
4074 as_bad (MISSING_FNSTART
);
4076 /* Figure out what sort of save we have. */
4077 peek
= input_line_pointer
;
4085 reg
= arm_reg_parse_multi (&peek
);
4089 as_bad (_("register expected"));
4090 ignore_rest_of_line ();
4099 as_bad (_("FPA .unwind_save does not take a register list"));
4100 ignore_rest_of_line ();
4103 input_line_pointer
= peek
;
4104 s_arm_unwind_save_fpa (reg
->number
);
4107 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4110 s_arm_unwind_save_vfp_armv6 ();
4112 s_arm_unwind_save_vfp ();
4114 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4115 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4118 as_bad (_(".unwind_save does not support this kind of register"));
4119 ignore_rest_of_line ();
4124 /* Parse an unwind_movsp directive. */
4127 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4133 if (!unwind
.proc_start
)
4134 as_bad (MISSING_FNSTART
);
4136 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4139 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4140 ignore_rest_of_line ();
4144 /* Optional constant. */
4145 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4147 if (immediate_for_directive (&offset
) == FAIL
)
4153 demand_empty_rest_of_line ();
4155 if (reg
== REG_SP
|| reg
== REG_PC
)
4157 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4161 if (unwind
.fp_reg
!= REG_SP
)
4162 as_bad (_("unexpected .unwind_movsp directive"));
4164 /* Generate opcode to restore the value. */
4166 add_unwind_opcode (op
, 1);
4168 /* Record the information for later. */
4169 unwind
.fp_reg
= reg
;
4170 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4171 unwind
.sp_restored
= 1;
4174 /* Parse an unwind_pad directive. */
4177 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4181 if (!unwind
.proc_start
)
4182 as_bad (MISSING_FNSTART
);
4184 if (immediate_for_directive (&offset
) == FAIL
)
4189 as_bad (_("stack increment must be multiple of 4"));
4190 ignore_rest_of_line ();
4194 /* Don't generate any opcodes, just record the details for later. */
4195 unwind
.frame_size
+= offset
;
4196 unwind
.pending_offset
+= offset
;
4198 demand_empty_rest_of_line ();
4201 /* Parse an unwind_setfp directive. */
4204 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4210 if (!unwind
.proc_start
)
4211 as_bad (MISSING_FNSTART
);
4213 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4214 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4217 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4219 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4221 as_bad (_("expected <reg>, <reg>"));
4222 ignore_rest_of_line ();
4226 /* Optional constant. */
4227 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4229 if (immediate_for_directive (&offset
) == FAIL
)
4235 demand_empty_rest_of_line ();
4237 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4239 as_bad (_("register must be either sp or set by a previous"
4240 "unwind_movsp directive"));
4244 /* Don't generate any opcodes, just record the information for later. */
4245 unwind
.fp_reg
= fp_reg
;
4247 if (sp_reg
== REG_SP
)
4248 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4250 unwind
.fp_offset
-= offset
;
4253 /* Parse an unwind_raw directive. */
4256 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4259 /* This is an arbitrary limit. */
4260 unsigned char op
[16];
4263 if (!unwind
.proc_start
)
4264 as_bad (MISSING_FNSTART
);
4267 if (exp
.X_op
== O_constant
4268 && skip_past_comma (&input_line_pointer
) != FAIL
)
4270 unwind
.frame_size
+= exp
.X_add_number
;
4274 exp
.X_op
= O_illegal
;
4276 if (exp
.X_op
!= O_constant
)
4278 as_bad (_("expected <offset>, <opcode>"));
4279 ignore_rest_of_line ();
4285 /* Parse the opcode. */
4290 as_bad (_("unwind opcode too long"));
4291 ignore_rest_of_line ();
4293 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4295 as_bad (_("invalid unwind opcode"));
4296 ignore_rest_of_line ();
4299 op
[count
++] = exp
.X_add_number
;
4301 /* Parse the next byte. */
4302 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4308 /* Add the opcode bytes in reverse order. */
4310 add_unwind_opcode (op
[count
], 1);
4312 demand_empty_rest_of_line ();
4316 /* Parse a .eabi_attribute directive. */
4319 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4321 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4323 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4324 attributes_set_explicitly
[tag
] = 1;
4327 /* Emit a tls fix for the symbol. */
4330 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4334 #ifdef md_flush_pending_output
4335 md_flush_pending_output ();
4338 #ifdef md_cons_align
4342 /* Since we're just labelling the code, there's no need to define a
4345 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4346 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4347 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4348 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4350 #endif /* OBJ_ELF */
4352 static void s_arm_arch (int);
4353 static void s_arm_object_arch (int);
4354 static void s_arm_cpu (int);
4355 static void s_arm_fpu (int);
4356 static void s_arm_arch_extension (int);
4361 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4368 if (exp
.X_op
== O_symbol
)
4369 exp
.X_op
= O_secrel
;
4371 emit_expr (&exp
, 4);
4373 while (*input_line_pointer
++ == ',');
4375 input_line_pointer
--;
4376 demand_empty_rest_of_line ();
4380 /* This table describes all the machine specific pseudo-ops the assembler
4381 has to support. The fields are:
4382 pseudo-op name without dot
4383 function to call to execute this pseudo-op
4384 Integer arg to pass to the function. */
4386 const pseudo_typeS md_pseudo_table
[] =
4388 /* Never called because '.req' does not start a line. */
4389 { "req", s_req
, 0 },
4390 /* Following two are likewise never called. */
4393 { "unreq", s_unreq
, 0 },
4394 { "bss", s_bss
, 0 },
4395 { "align", s_align
, 0 },
4396 { "arm", s_arm
, 0 },
4397 { "thumb", s_thumb
, 0 },
4398 { "code", s_code
, 0 },
4399 { "force_thumb", s_force_thumb
, 0 },
4400 { "thumb_func", s_thumb_func
, 0 },
4401 { "thumb_set", s_thumb_set
, 0 },
4402 { "even", s_even
, 0 },
4403 { "ltorg", s_ltorg
, 0 },
4404 { "pool", s_ltorg
, 0 },
4405 { "syntax", s_syntax
, 0 },
4406 { "cpu", s_arm_cpu
, 0 },
4407 { "arch", s_arm_arch
, 0 },
4408 { "object_arch", s_arm_object_arch
, 0 },
4409 { "fpu", s_arm_fpu
, 0 },
4410 { "arch_extension", s_arm_arch_extension
, 0 },
4412 { "word", s_arm_elf_cons
, 4 },
4413 { "long", s_arm_elf_cons
, 4 },
4414 { "inst.n", s_arm_elf_inst
, 2 },
4415 { "inst.w", s_arm_elf_inst
, 4 },
4416 { "inst", s_arm_elf_inst
, 0 },
4417 { "rel31", s_arm_rel31
, 0 },
4418 { "fnstart", s_arm_unwind_fnstart
, 0 },
4419 { "fnend", s_arm_unwind_fnend
, 0 },
4420 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4421 { "personality", s_arm_unwind_personality
, 0 },
4422 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4423 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4424 { "save", s_arm_unwind_save
, 0 },
4425 { "vsave", s_arm_unwind_save
, 1 },
4426 { "movsp", s_arm_unwind_movsp
, 0 },
4427 { "pad", s_arm_unwind_pad
, 0 },
4428 { "setfp", s_arm_unwind_setfp
, 0 },
4429 { "unwind_raw", s_arm_unwind_raw
, 0 },
4430 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4431 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4435 /* These are used for dwarf. */
4439 /* These are used for dwarf2. */
4440 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4441 { "loc", dwarf2_directive_loc
, 0 },
4442 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4444 { "extend", float_cons
, 'x' },
4445 { "ldouble", float_cons
, 'x' },
4446 { "packed", float_cons
, 'p' },
4448 {"secrel32", pe_directive_secrel
, 0},
4453 /* Parser functions used exclusively in instruction operands. */
4455 /* Generic immediate-value read function for use in insn parsing.
4456 STR points to the beginning of the immediate (the leading #);
4457 VAL receives the value; if the value is outside [MIN, MAX]
4458 issue an error. PREFIX_OPT is true if the immediate prefix is
4462 parse_immediate (char **str
, int *val
, int min
, int max
,
4463 bfd_boolean prefix_opt
)
4466 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4467 if (exp
.X_op
!= O_constant
)
4469 inst
.error
= _("constant expression required");
4473 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4475 inst
.error
= _("immediate value out of range");
4479 *val
= exp
.X_add_number
;
4483 /* Less-generic immediate-value read function with the possibility of loading a
4484 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4485 instructions. Puts the result directly in inst.operands[i]. */
4488 parse_big_immediate (char **str
, int i
)
4493 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4495 if (exp
.X_op
== O_constant
)
4497 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4498 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4499 O_constant. We have to be careful not to break compilation for
4500 32-bit X_add_number, though. */
4501 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4503 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4504 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4505 inst
.operands
[i
].regisimm
= 1;
4508 else if (exp
.X_op
== O_big
4509 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4511 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4513 /* Bignums have their least significant bits in
4514 generic_bignum[0]. Make sure we put 32 bits in imm and
4515 32 bits in reg, in a (hopefully) portable way. */
4516 gas_assert (parts
!= 0);
4518 /* Make sure that the number is not too big.
4519 PR 11972: Bignums can now be sign-extended to the
4520 size of a .octa so check that the out of range bits
4521 are all zero or all one. */
4522 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4524 LITTLENUM_TYPE m
= -1;
4526 if (generic_bignum
[parts
* 2] != 0
4527 && generic_bignum
[parts
* 2] != m
)
4530 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4531 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4535 inst
.operands
[i
].imm
= 0;
4536 for (j
= 0; j
< parts
; j
++, idx
++)
4537 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4538 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4539 inst
.operands
[i
].reg
= 0;
4540 for (j
= 0; j
< parts
; j
++, idx
++)
4541 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4542 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4543 inst
.operands
[i
].regisimm
= 1;
4553 /* Returns the pseudo-register number of an FPA immediate constant,
4554 or FAIL if there isn't a valid constant here. */
4557 parse_fpa_immediate (char ** str
)
4559 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4565 /* First try and match exact strings, this is to guarantee
4566 that some formats will work even for cross assembly. */
4568 for (i
= 0; fp_const
[i
]; i
++)
4570 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4574 *str
+= strlen (fp_const
[i
]);
4575 if (is_end_of_line
[(unsigned char) **str
])
4581 /* Just because we didn't get a match doesn't mean that the constant
4582 isn't valid, just that it is in a format that we don't
4583 automatically recognize. Try parsing it with the standard
4584 expression routines. */
4586 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4588 /* Look for a raw floating point number. */
4589 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4590 && is_end_of_line
[(unsigned char) *save_in
])
4592 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4594 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4596 if (words
[j
] != fp_values
[i
][j
])
4600 if (j
== MAX_LITTLENUMS
)
4608 /* Try and parse a more complex expression, this will probably fail
4609 unless the code uses a floating point prefix (eg "0f"). */
4610 save_in
= input_line_pointer
;
4611 input_line_pointer
= *str
;
4612 if (expression (&exp
) == absolute_section
4613 && exp
.X_op
== O_big
4614 && exp
.X_add_number
< 0)
4616 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4618 if (gen_to_words (words
, 5, (long) 15) == 0)
4620 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4622 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4624 if (words
[j
] != fp_values
[i
][j
])
4628 if (j
== MAX_LITTLENUMS
)
4630 *str
= input_line_pointer
;
4631 input_line_pointer
= save_in
;
4638 *str
= input_line_pointer
;
4639 input_line_pointer
= save_in
;
4640 inst
.error
= _("invalid FPA immediate expression");
4644 /* Returns 1 if a number has "quarter-precision" float format
4645 0baBbbbbbc defgh000 00000000 00000000. */
4648 is_quarter_float (unsigned imm
)
4650 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4651 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4654 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4655 0baBbbbbbc defgh000 00000000 00000000.
4656 The zero and minus-zero cases need special handling, since they can't be
4657 encoded in the "quarter-precision" float format, but can nonetheless be
4658 loaded as integer constants. */
4661 parse_qfloat_immediate (char **ccp
, int *immed
)
4665 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4666 int found_fpchar
= 0;
4668 skip_past_char (&str
, '#');
4670 /* We must not accidentally parse an integer as a floating-point number. Make
4671 sure that the value we parse is not an integer by checking for special
4672 characters '.' or 'e'.
4673 FIXME: This is a horrible hack, but doing better is tricky because type
4674 information isn't in a very usable state at parse time. */
4676 skip_whitespace (fpnum
);
4678 if (strncmp (fpnum
, "0x", 2) == 0)
4682 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4683 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4693 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4695 unsigned fpword
= 0;
4698 /* Our FP word must be 32 bits (single-precision FP). */
4699 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4701 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4705 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4718 /* Shift operands. */
4721 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4724 struct asm_shift_name
4727 enum shift_kind kind
;
4730 /* Third argument to parse_shift. */
4731 enum parse_shift_mode
4733 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4734 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4735 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4736 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4737 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4740 /* Parse a <shift> specifier on an ARM data processing instruction.
4741 This has three forms:
4743 (LSL|LSR|ASL|ASR|ROR) Rs
4744 (LSL|LSR|ASL|ASR|ROR) #imm
4747 Note that ASL is assimilated to LSL in the instruction encoding, and
4748 RRX to ROR #0 (which cannot be written as such). */
4751 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4753 const struct asm_shift_name
*shift_name
;
4754 enum shift_kind shift
;
4759 for (p
= *str
; ISALPHA (*p
); p
++)
4764 inst
.error
= _("shift expression expected");
4768 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4771 if (shift_name
== NULL
)
4773 inst
.error
= _("shift expression expected");
4777 shift
= shift_name
->kind
;
4781 case NO_SHIFT_RESTRICT
:
4782 case SHIFT_IMMEDIATE
: break;
4784 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4785 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4787 inst
.error
= _("'LSL' or 'ASR' required");
4792 case SHIFT_LSL_IMMEDIATE
:
4793 if (shift
!= SHIFT_LSL
)
4795 inst
.error
= _("'LSL' required");
4800 case SHIFT_ASR_IMMEDIATE
:
4801 if (shift
!= SHIFT_ASR
)
4803 inst
.error
= _("'ASR' required");
4811 if (shift
!= SHIFT_RRX
)
4813 /* Whitespace can appear here if the next thing is a bare digit. */
4814 skip_whitespace (p
);
4816 if (mode
== NO_SHIFT_RESTRICT
4817 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4819 inst
.operands
[i
].imm
= reg
;
4820 inst
.operands
[i
].immisreg
= 1;
4822 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4825 inst
.operands
[i
].shift_kind
= shift
;
4826 inst
.operands
[i
].shifted
= 1;
4831 /* Parse a <shifter_operand> for an ARM data processing instruction:
4834 #<immediate>, <rotate>
4838 where <shift> is defined by parse_shift above, and <rotate> is a
4839 multiple of 2 between 0 and 30. Validation of immediate operands
4840 is deferred to md_apply_fix. */
4843 parse_shifter_operand (char **str
, int i
)
4848 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4850 inst
.operands
[i
].reg
= value
;
4851 inst
.operands
[i
].isreg
= 1;
4853 /* parse_shift will override this if appropriate */
4854 inst
.reloc
.exp
.X_op
= O_constant
;
4855 inst
.reloc
.exp
.X_add_number
= 0;
4857 if (skip_past_comma (str
) == FAIL
)
4860 /* Shift operation on register. */
4861 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4864 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4867 if (skip_past_comma (str
) == SUCCESS
)
4869 /* #x, y -- ie explicit rotation by Y. */
4870 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4873 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4875 inst
.error
= _("constant expression expected");
4879 value
= exp
.X_add_number
;
4880 if (value
< 0 || value
> 30 || value
% 2 != 0)
4882 inst
.error
= _("invalid rotation");
4885 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4887 inst
.error
= _("invalid constant");
4891 /* Encode as specified. */
4892 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
4896 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4897 inst
.reloc
.pc_rel
= 0;
4901 /* Group relocation information. Each entry in the table contains the
4902 textual name of the relocation as may appear in assembler source
4903 and must end with a colon.
4904 Along with this textual name are the relocation codes to be used if
4905 the corresponding instruction is an ALU instruction (ADD or SUB only),
4906 an LDR, an LDRS, or an LDC. */
4908 struct group_reloc_table_entry
4919 /* Varieties of non-ALU group relocation. */
4926 static struct group_reloc_table_entry group_reloc_table
[] =
4927 { /* Program counter relative: */
4929 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4934 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4935 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4936 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4937 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4939 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4944 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4945 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4946 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4947 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4949 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4950 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4951 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4952 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4953 /* Section base relative */
4955 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4960 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4961 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4962 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4963 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4965 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4970 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4971 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4972 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4973 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4975 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4976 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4977 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4978 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4980 /* Given the address of a pointer pointing to the textual name of a group
4981 relocation as may appear in assembler source, attempt to find its details
4982 in group_reloc_table. The pointer will be updated to the character after
4983 the trailing colon. On failure, FAIL will be returned; SUCCESS
4984 otherwise. On success, *entry will be updated to point at the relevant
4985 group_reloc_table entry. */
4988 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4991 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4993 int length
= strlen (group_reloc_table
[i
].name
);
4995 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4996 && (*str
)[length
] == ':')
4998 *out
= &group_reloc_table
[i
];
4999 *str
+= (length
+ 1);
5007 /* Parse a <shifter_operand> for an ARM data processing instruction
5008 (as for parse_shifter_operand) where group relocations are allowed:
5011 #<immediate>, <rotate>
5012 #:<group_reloc>:<expression>
5016 where <group_reloc> is one of the strings defined in group_reloc_table.
5017 The hashes are optional.
5019 Everything else is as for parse_shifter_operand. */
5021 static parse_operand_result
5022 parse_shifter_operand_group_reloc (char **str
, int i
)
5024 /* Determine if we have the sequence of characters #: or just :
5025 coming next. If we do, then we check for a group relocation.
5026 If we don't, punt the whole lot to parse_shifter_operand. */
5028 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5029 || (*str
)[0] == ':')
5031 struct group_reloc_table_entry
*entry
;
5033 if ((*str
)[0] == '#')
5038 /* Try to parse a group relocation. Anything else is an error. */
5039 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5041 inst
.error
= _("unknown group relocation");
5042 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5045 /* We now have the group relocation table entry corresponding to
5046 the name in the assembler source. Next, we parse the expression. */
5047 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5048 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5050 /* Record the relocation type (always the ALU variant here). */
5051 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5052 gas_assert (inst
.reloc
.type
!= 0);
5054 return PARSE_OPERAND_SUCCESS
;
5057 return parse_shifter_operand (str
, i
) == SUCCESS
5058 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5060 /* Never reached. */
5063 /* Parse a Neon alignment expression. Information is written to
5064 inst.operands[i]. We assume the initial ':' has been skipped.
5066 align .imm = align << 8, .immisalign=1, .preind=0 */
5067 static parse_operand_result
5068 parse_neon_alignment (char **str
, int i
)
5073 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5075 if (exp
.X_op
!= O_constant
)
5077 inst
.error
= _("alignment must be constant");
5078 return PARSE_OPERAND_FAIL
;
5081 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5082 inst
.operands
[i
].immisalign
= 1;
5083 /* Alignments are not pre-indexes. */
5084 inst
.operands
[i
].preind
= 0;
5087 return PARSE_OPERAND_SUCCESS
;
5090 /* Parse all forms of an ARM address expression. Information is written
5091 to inst.operands[i] and/or inst.reloc.
5093 Preindexed addressing (.preind=1):
5095 [Rn, #offset] .reg=Rn .reloc.exp=offset
5096 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5097 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5098 .shift_kind=shift .reloc.exp=shift_imm
5100 These three may have a trailing ! which causes .writeback to be set also.
5102 Postindexed addressing (.postind=1, .writeback=1):
5104 [Rn], #offset .reg=Rn .reloc.exp=offset
5105 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5106 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5107 .shift_kind=shift .reloc.exp=shift_imm
5109 Unindexed addressing (.preind=0, .postind=0):
5111 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5115 [Rn]{!} shorthand for [Rn,#0]{!}
5116 =immediate .isreg=0 .reloc.exp=immediate
5117 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5119 It is the caller's responsibility to check for addressing modes not
5120 supported by the instruction, and to set inst.reloc.type. */
5122 static parse_operand_result
5123 parse_address_main (char **str
, int i
, int group_relocations
,
5124 group_reloc_type group_type
)
5129 if (skip_past_char (&p
, '[') == FAIL
)
5131 if (skip_past_char (&p
, '=') == FAIL
)
5133 /* Bare address - translate to PC-relative offset. */
5134 inst
.reloc
.pc_rel
= 1;
5135 inst
.operands
[i
].reg
= REG_PC
;
5136 inst
.operands
[i
].isreg
= 1;
5137 inst
.operands
[i
].preind
= 1;
5139 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5141 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5142 return PARSE_OPERAND_FAIL
;
5145 return PARSE_OPERAND_SUCCESS
;
5148 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5150 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5151 return PARSE_OPERAND_FAIL
;
5153 inst
.operands
[i
].reg
= reg
;
5154 inst
.operands
[i
].isreg
= 1;
5156 if (skip_past_comma (&p
) == SUCCESS
)
5158 inst
.operands
[i
].preind
= 1;
5161 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5163 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5165 inst
.operands
[i
].imm
= reg
;
5166 inst
.operands
[i
].immisreg
= 1;
5168 if (skip_past_comma (&p
) == SUCCESS
)
5169 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5170 return PARSE_OPERAND_FAIL
;
5172 else if (skip_past_char (&p
, ':') == SUCCESS
)
5174 /* FIXME: '@' should be used here, but it's filtered out by generic
5175 code before we get to see it here. This may be subject to
5177 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5179 if (result
!= PARSE_OPERAND_SUCCESS
)
5184 if (inst
.operands
[i
].negative
)
5186 inst
.operands
[i
].negative
= 0;
5190 if (group_relocations
5191 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5193 struct group_reloc_table_entry
*entry
;
5195 /* Skip over the #: or : sequence. */
5201 /* Try to parse a group relocation. Anything else is an
5203 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5205 inst
.error
= _("unknown group relocation");
5206 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5209 /* We now have the group relocation table entry corresponding to
5210 the name in the assembler source. Next, we parse the
5212 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5213 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5215 /* Record the relocation type. */
5219 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5223 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5227 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5234 if (inst
.reloc
.type
== 0)
5236 inst
.error
= _("this group relocation is not allowed on this instruction");
5237 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5243 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5244 return PARSE_OPERAND_FAIL
;
5245 /* If the offset is 0, find out if it's a +0 or -0. */
5246 if (inst
.reloc
.exp
.X_op
== O_constant
5247 && inst
.reloc
.exp
.X_add_number
== 0)
5249 skip_whitespace (q
);
5253 skip_whitespace (q
);
5256 inst
.operands
[i
].negative
= 1;
5261 else if (skip_past_char (&p
, ':') == SUCCESS
)
5263 /* FIXME: '@' should be used here, but it's filtered out by generic code
5264 before we get to see it here. This may be subject to change. */
5265 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5267 if (result
!= PARSE_OPERAND_SUCCESS
)
5271 if (skip_past_char (&p
, ']') == FAIL
)
5273 inst
.error
= _("']' expected");
5274 return PARSE_OPERAND_FAIL
;
5277 if (skip_past_char (&p
, '!') == SUCCESS
)
5278 inst
.operands
[i
].writeback
= 1;
5280 else if (skip_past_comma (&p
) == SUCCESS
)
5282 if (skip_past_char (&p
, '{') == SUCCESS
)
5284 /* [Rn], {expr} - unindexed, with option */
5285 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5286 0, 255, TRUE
) == FAIL
)
5287 return PARSE_OPERAND_FAIL
;
5289 if (skip_past_char (&p
, '}') == FAIL
)
5291 inst
.error
= _("'}' expected at end of 'option' field");
5292 return PARSE_OPERAND_FAIL
;
5294 if (inst
.operands
[i
].preind
)
5296 inst
.error
= _("cannot combine index with option");
5297 return PARSE_OPERAND_FAIL
;
5300 return PARSE_OPERAND_SUCCESS
;
5304 inst
.operands
[i
].postind
= 1;
5305 inst
.operands
[i
].writeback
= 1;
5307 if (inst
.operands
[i
].preind
)
5309 inst
.error
= _("cannot combine pre- and post-indexing");
5310 return PARSE_OPERAND_FAIL
;
5314 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5316 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5318 /* We might be using the immediate for alignment already. If we
5319 are, OR the register number into the low-order bits. */
5320 if (inst
.operands
[i
].immisalign
)
5321 inst
.operands
[i
].imm
|= reg
;
5323 inst
.operands
[i
].imm
= reg
;
5324 inst
.operands
[i
].immisreg
= 1;
5326 if (skip_past_comma (&p
) == SUCCESS
)
5327 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5328 return PARSE_OPERAND_FAIL
;
5333 if (inst
.operands
[i
].negative
)
5335 inst
.operands
[i
].negative
= 0;
5338 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5339 return PARSE_OPERAND_FAIL
;
5340 /* If the offset is 0, find out if it's a +0 or -0. */
5341 if (inst
.reloc
.exp
.X_op
== O_constant
5342 && inst
.reloc
.exp
.X_add_number
== 0)
5344 skip_whitespace (q
);
5348 skip_whitespace (q
);
5351 inst
.operands
[i
].negative
= 1;
5357 /* If at this point neither .preind nor .postind is set, we have a
5358 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5359 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5361 inst
.operands
[i
].preind
= 1;
5362 inst
.reloc
.exp
.X_op
= O_constant
;
5363 inst
.reloc
.exp
.X_add_number
= 0;
5366 return PARSE_OPERAND_SUCCESS
;
5370 parse_address (char **str
, int i
)
5372 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5376 static parse_operand_result
5377 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5379 return parse_address_main (str
, i
, 1, type
);
5382 /* Parse an operand for a MOVW or MOVT instruction. */
5384 parse_half (char **str
)
5389 skip_past_char (&p
, '#');
5390 if (strncasecmp (p
, ":lower16:", 9) == 0)
5391 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5392 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5393 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5395 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5398 skip_whitespace (p
);
5401 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5404 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5406 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5408 inst
.error
= _("constant expression expected");
5411 if (inst
.reloc
.exp
.X_add_number
< 0
5412 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5414 inst
.error
= _("immediate value out of range");
5422 /* Miscellaneous. */
5424 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5425 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5427 parse_psr (char **str
, bfd_boolean lhs
)
5430 unsigned long psr_field
;
5431 const struct asm_psr
*psr
;
5433 bfd_boolean is_apsr
= FALSE
;
5434 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5436 /* PR gas/12698: If the user has specified -march=all then m_profile will
5437 be TRUE, but we want to ignore it in this case as we are building for any
5438 CPU type, including non-m variants. */
5439 if (selected_cpu
.core
== arm_arch_any
.core
)
5442 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5443 feature for ease of use and backwards compatibility. */
5445 if (strncasecmp (p
, "SPSR", 4) == 0)
5448 goto unsupported_psr
;
5450 psr_field
= SPSR_BIT
;
5452 else if (strncasecmp (p
, "CPSR", 4) == 0)
5455 goto unsupported_psr
;
5459 else if (strncasecmp (p
, "APSR", 4) == 0)
5461 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5462 and ARMv7-R architecture CPUs. */
5471 while (ISALNUM (*p
) || *p
== '_');
5473 if (strncasecmp (start
, "iapsr", 5) == 0
5474 || strncasecmp (start
, "eapsr", 5) == 0
5475 || strncasecmp (start
, "xpsr", 4) == 0
5476 || strncasecmp (start
, "psr", 3) == 0)
5477 p
= start
+ strcspn (start
, "rR") + 1;
5479 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5485 /* If APSR is being written, a bitfield may be specified. Note that
5486 APSR itself is handled above. */
5487 if (psr
->field
<= 3)
5489 psr_field
= psr
->field
;
5495 /* M-profile MSR instructions have the mask field set to "10", except
5496 *PSR variants which modify APSR, which may use a different mask (and
5497 have been handled already). Do that by setting the PSR_f field
5499 return psr
->field
| (lhs
? PSR_f
: 0);
5502 goto unsupported_psr
;
5508 /* A suffix follows. */
5514 while (ISALNUM (*p
) || *p
== '_');
5518 /* APSR uses a notation for bits, rather than fields. */
5519 unsigned int nzcvq_bits
= 0;
5520 unsigned int g_bit
= 0;
5523 for (bit
= start
; bit
!= p
; bit
++)
5525 switch (TOLOWER (*bit
))
5528 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5532 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5536 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5540 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5544 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5548 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5552 inst
.error
= _("unexpected bit specified after APSR");
5557 if (nzcvq_bits
== 0x1f)
5562 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5564 inst
.error
= _("selected processor does not "
5565 "support DSP extension");
5572 if ((nzcvq_bits
& 0x20) != 0
5573 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5574 || (g_bit
& 0x2) != 0)
5576 inst
.error
= _("bad bitmask specified after APSR");
5582 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5587 psr_field
|= psr
->field
;
5593 goto error
; /* Garbage after "[CS]PSR". */
5595 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5596 is deprecated, but allow it anyway. */
5600 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5603 else if (!m_profile
)
5604 /* These bits are never right for M-profile devices: don't set them
5605 (only code paths which read/write APSR reach here). */
5606 psr_field
|= (PSR_c
| PSR_f
);
5612 inst
.error
= _("selected processor does not support requested special "
5613 "purpose register");
5617 inst
.error
= _("flag for {c}psr instruction expected");
5621 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5622 value suitable for splatting into the AIF field of the instruction. */
5625 parse_cps_flags (char **str
)
5634 case '\0': case ',':
5637 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5638 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5639 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5642 inst
.error
= _("unrecognized CPS flag");
5647 if (saw_a_flag
== 0)
5649 inst
.error
= _("missing CPS flags");
5657 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5658 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5661 parse_endian_specifier (char **str
)
5666 if (strncasecmp (s
, "BE", 2))
5668 else if (strncasecmp (s
, "LE", 2))
5672 inst
.error
= _("valid endian specifiers are be or le");
5676 if (ISALNUM (s
[2]) || s
[2] == '_')
5678 inst
.error
= _("valid endian specifiers are be or le");
5683 return little_endian
;
5686 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5687 value suitable for poking into the rotate field of an sxt or sxta
5688 instruction, or FAIL on error. */
5691 parse_ror (char **str
)
5696 if (strncasecmp (s
, "ROR", 3) == 0)
5700 inst
.error
= _("missing rotation field after comma");
5704 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5709 case 0: *str
= s
; return 0x0;
5710 case 8: *str
= s
; return 0x1;
5711 case 16: *str
= s
; return 0x2;
5712 case 24: *str
= s
; return 0x3;
5715 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5720 /* Parse a conditional code (from conds[] below). The value returned is in the
5721 range 0 .. 14, or FAIL. */
5723 parse_cond (char **str
)
5726 const struct asm_cond
*c
;
5728 /* Condition codes are always 2 characters, so matching up to
5729 3 characters is sufficient. */
5734 while (ISALPHA (*q
) && n
< 3)
5736 cond
[n
] = TOLOWER (*q
);
5741 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5744 inst
.error
= _("condition required");
5752 /* Parse an option for a barrier instruction. Returns the encoding for the
5755 parse_barrier (char **str
)
5758 const struct asm_barrier_opt
*o
;
5761 while (ISALPHA (*q
))
5764 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5773 /* Parse the operands of a table branch instruction. Similar to a memory
5776 parse_tb (char **str
)
5781 if (skip_past_char (&p
, '[') == FAIL
)
5783 inst
.error
= _("'[' expected");
5787 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5789 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5792 inst
.operands
[0].reg
= reg
;
5794 if (skip_past_comma (&p
) == FAIL
)
5796 inst
.error
= _("',' expected");
5800 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5802 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5805 inst
.operands
[0].imm
= reg
;
5807 if (skip_past_comma (&p
) == SUCCESS
)
5809 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5811 if (inst
.reloc
.exp
.X_add_number
!= 1)
5813 inst
.error
= _("invalid shift");
5816 inst
.operands
[0].shifted
= 1;
5819 if (skip_past_char (&p
, ']') == FAIL
)
5821 inst
.error
= _("']' expected");
5828 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5829 information on the types the operands can take and how they are encoded.
5830 Up to four operands may be read; this function handles setting the
5831 ".present" field for each read operand itself.
5832 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5833 else returns FAIL. */
5836 parse_neon_mov (char **str
, int *which_operand
)
5838 int i
= *which_operand
, val
;
5839 enum arm_reg_type rtype
;
5841 struct neon_type_el optype
;
5843 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5845 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5846 inst
.operands
[i
].reg
= val
;
5847 inst
.operands
[i
].isscalar
= 1;
5848 inst
.operands
[i
].vectype
= optype
;
5849 inst
.operands
[i
++].present
= 1;
5851 if (skip_past_comma (&ptr
) == FAIL
)
5854 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5857 inst
.operands
[i
].reg
= val
;
5858 inst
.operands
[i
].isreg
= 1;
5859 inst
.operands
[i
].present
= 1;
5861 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5864 /* Cases 0, 1, 2, 3, 5 (D only). */
5865 if (skip_past_comma (&ptr
) == FAIL
)
5868 inst
.operands
[i
].reg
= val
;
5869 inst
.operands
[i
].isreg
= 1;
5870 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5871 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5872 inst
.operands
[i
].isvec
= 1;
5873 inst
.operands
[i
].vectype
= optype
;
5874 inst
.operands
[i
++].present
= 1;
5876 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5878 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5879 Case 13: VMOV <Sd>, <Rm> */
5880 inst
.operands
[i
].reg
= val
;
5881 inst
.operands
[i
].isreg
= 1;
5882 inst
.operands
[i
].present
= 1;
5884 if (rtype
== REG_TYPE_NQ
)
5886 first_error (_("can't use Neon quad register here"));
5889 else if (rtype
!= REG_TYPE_VFS
)
5892 if (skip_past_comma (&ptr
) == FAIL
)
5894 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5896 inst
.operands
[i
].reg
= val
;
5897 inst
.operands
[i
].isreg
= 1;
5898 inst
.operands
[i
].present
= 1;
5901 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5904 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5905 Case 1: VMOV<c><q> <Dd>, <Dm>
5906 Case 8: VMOV.F32 <Sd>, <Sm>
5907 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5909 inst
.operands
[i
].reg
= val
;
5910 inst
.operands
[i
].isreg
= 1;
5911 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5912 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5913 inst
.operands
[i
].isvec
= 1;
5914 inst
.operands
[i
].vectype
= optype
;
5915 inst
.operands
[i
].present
= 1;
5917 if (skip_past_comma (&ptr
) == SUCCESS
)
5922 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5925 inst
.operands
[i
].reg
= val
;
5926 inst
.operands
[i
].isreg
= 1;
5927 inst
.operands
[i
++].present
= 1;
5929 if (skip_past_comma (&ptr
) == FAIL
)
5932 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5935 inst
.operands
[i
].reg
= val
;
5936 inst
.operands
[i
].isreg
= 1;
5937 inst
.operands
[i
].present
= 1;
5940 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5941 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5942 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5943 Case 10: VMOV.F32 <Sd>, #<imm>
5944 Case 11: VMOV.F64 <Dd>, #<imm> */
5945 inst
.operands
[i
].immisfloat
= 1;
5946 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5947 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5948 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5952 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5956 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5959 inst
.operands
[i
].reg
= val
;
5960 inst
.operands
[i
].isreg
= 1;
5961 inst
.operands
[i
++].present
= 1;
5963 if (skip_past_comma (&ptr
) == FAIL
)
5966 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5968 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5969 inst
.operands
[i
].reg
= val
;
5970 inst
.operands
[i
].isscalar
= 1;
5971 inst
.operands
[i
].present
= 1;
5972 inst
.operands
[i
].vectype
= optype
;
5974 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5976 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5977 inst
.operands
[i
].reg
= val
;
5978 inst
.operands
[i
].isreg
= 1;
5979 inst
.operands
[i
++].present
= 1;
5981 if (skip_past_comma (&ptr
) == FAIL
)
5984 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5987 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5991 inst
.operands
[i
].reg
= val
;
5992 inst
.operands
[i
].isreg
= 1;
5993 inst
.operands
[i
].isvec
= 1;
5994 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5995 inst
.operands
[i
].vectype
= optype
;
5996 inst
.operands
[i
].present
= 1;
5998 if (rtype
== REG_TYPE_VFS
)
6002 if (skip_past_comma (&ptr
) == FAIL
)
6004 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6007 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6010 inst
.operands
[i
].reg
= val
;
6011 inst
.operands
[i
].isreg
= 1;
6012 inst
.operands
[i
].isvec
= 1;
6013 inst
.operands
[i
].issingle
= 1;
6014 inst
.operands
[i
].vectype
= optype
;
6015 inst
.operands
[i
].present
= 1;
6018 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6022 inst
.operands
[i
].reg
= val
;
6023 inst
.operands
[i
].isreg
= 1;
6024 inst
.operands
[i
].isvec
= 1;
6025 inst
.operands
[i
].issingle
= 1;
6026 inst
.operands
[i
].vectype
= optype
;
6027 inst
.operands
[i
].present
= 1;
6032 first_error (_("parse error"));
6036 /* Successfully parsed the operands. Update args. */
6042 first_error (_("expected comma"));
6046 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6050 /* Use this macro when the operand constraints are different
6051 for ARM and THUMB (e.g. ldrd). */
6052 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6053 ((arm_operand) | ((thumb_operand) << 16))
6055 /* Matcher codes for parse_operands. */
6056 enum operand_parse_code
6058 OP_stop
, /* end of line */
6060 OP_RR
, /* ARM register */
6061 OP_RRnpc
, /* ARM register, not r15 */
6062 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6063 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6064 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6065 optional trailing ! */
6066 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6067 OP_RCP
, /* Coprocessor number */
6068 OP_RCN
, /* Coprocessor register */
6069 OP_RF
, /* FPA register */
6070 OP_RVS
, /* VFP single precision register */
6071 OP_RVD
, /* VFP double precision register (0..15) */
6072 OP_RND
, /* Neon double precision register (0..31) */
6073 OP_RNQ
, /* Neon quad precision register */
6074 OP_RVSD
, /* VFP single or double precision register */
6075 OP_RNDQ
, /* Neon double or quad precision register */
6076 OP_RNSDQ
, /* Neon single, double or quad precision register */
6077 OP_RNSC
, /* Neon scalar D[X] */
6078 OP_RVC
, /* VFP control register */
6079 OP_RMF
, /* Maverick F register */
6080 OP_RMD
, /* Maverick D register */
6081 OP_RMFX
, /* Maverick FX register */
6082 OP_RMDX
, /* Maverick DX register */
6083 OP_RMAX
, /* Maverick AX register */
6084 OP_RMDS
, /* Maverick DSPSC register */
6085 OP_RIWR
, /* iWMMXt wR register */
6086 OP_RIWC
, /* iWMMXt wC register */
6087 OP_RIWG
, /* iWMMXt wCG register */
6088 OP_RXA
, /* XScale accumulator register */
6090 OP_REGLST
, /* ARM register list */
6091 OP_VRSLST
, /* VFP single-precision register list */
6092 OP_VRDLST
, /* VFP double-precision register list */
6093 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6094 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6095 OP_NSTRLST
, /* Neon element/structure list */
6097 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6098 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6099 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6100 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6101 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6102 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6103 OP_VMOV
, /* Neon VMOV operands. */
6104 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6105 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6106 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6108 OP_I0
, /* immediate zero */
6109 OP_I7
, /* immediate value 0 .. 7 */
6110 OP_I15
, /* 0 .. 15 */
6111 OP_I16
, /* 1 .. 16 */
6112 OP_I16z
, /* 0 .. 16 */
6113 OP_I31
, /* 0 .. 31 */
6114 OP_I31w
, /* 0 .. 31, optional trailing ! */
6115 OP_I32
, /* 1 .. 32 */
6116 OP_I32z
, /* 0 .. 32 */
6117 OP_I63
, /* 0 .. 63 */
6118 OP_I63s
, /* -64 .. 63 */
6119 OP_I64
, /* 1 .. 64 */
6120 OP_I64z
, /* 0 .. 64 */
6121 OP_I255
, /* 0 .. 255 */
6123 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6124 OP_I7b
, /* 0 .. 7 */
6125 OP_I15b
, /* 0 .. 15 */
6126 OP_I31b
, /* 0 .. 31 */
6128 OP_SH
, /* shifter operand */
6129 OP_SHG
, /* shifter operand with possible group relocation */
6130 OP_ADDR
, /* Memory address expression (any mode) */
6131 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6132 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6133 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6134 OP_EXP
, /* arbitrary expression */
6135 OP_EXPi
, /* same, with optional immediate prefix */
6136 OP_EXPr
, /* same, with optional relocation suffix */
6137 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6139 OP_CPSF
, /* CPS flags */
6140 OP_ENDI
, /* Endianness specifier */
6141 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6142 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6143 OP_COND
, /* conditional code */
6144 OP_TB
, /* Table branch. */
6146 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6148 OP_RRnpc_I0
, /* ARM register or literal 0 */
6149 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6150 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6151 OP_RF_IF
, /* FPA register or immediate */
6152 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6153 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6155 /* Optional operands. */
6156 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6157 OP_oI31b
, /* 0 .. 31 */
6158 OP_oI32b
, /* 1 .. 32 */
6159 OP_oI32z
, /* 0 .. 32 */
6160 OP_oIffffb
, /* 0 .. 65535 */
6161 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6163 OP_oRR
, /* ARM register */
6164 OP_oRRnpc
, /* ARM register, not the PC */
6165 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6166 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6167 OP_oRND
, /* Optional Neon double precision register */
6168 OP_oRNQ
, /* Optional Neon quad precision register */
6169 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6170 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6171 OP_oSHll
, /* LSL immediate */
6172 OP_oSHar
, /* ASR immediate */
6173 OP_oSHllar
, /* LSL or ASR immediate */
6174 OP_oROR
, /* ROR 0/8/16/24 */
6175 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6177 /* Some pre-defined mixed (ARM/THUMB) operands. */
6178 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6179 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6180 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6182 OP_FIRST_OPTIONAL
= OP_oI7b
6185 /* Generic instruction operand parser. This does no encoding and no
6186 semantic validation; it merely squirrels values away in the inst
6187 structure. Returns SUCCESS or FAIL depending on whether the
6188 specified grammar matched. */
6190 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6192 unsigned const int *upat
= pattern
;
6193 char *backtrack_pos
= 0;
6194 const char *backtrack_error
= 0;
6195 int i
, val
, backtrack_index
= 0;
6196 enum arm_reg_type rtype
;
6197 parse_operand_result result
;
6198 unsigned int op_parse_code
;
6200 #define po_char_or_fail(chr) \
6203 if (skip_past_char (&str, chr) == FAIL) \
6208 #define po_reg_or_fail(regtype) \
6211 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6212 & inst.operands[i].vectype); \
6215 first_error (_(reg_expected_msgs[regtype])); \
6218 inst.operands[i].reg = val; \
6219 inst.operands[i].isreg = 1; \
6220 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6221 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6222 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6223 || rtype == REG_TYPE_VFD \
6224 || rtype == REG_TYPE_NQ); \
6228 #define po_reg_or_goto(regtype, label) \
6231 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6232 & inst.operands[i].vectype); \
6236 inst.operands[i].reg = val; \
6237 inst.operands[i].isreg = 1; \
6238 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6239 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6240 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6241 || rtype == REG_TYPE_VFD \
6242 || rtype == REG_TYPE_NQ); \
6246 #define po_imm_or_fail(min, max, popt) \
6249 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6251 inst.operands[i].imm = val; \
6255 #define po_scalar_or_goto(elsz, label) \
6258 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6261 inst.operands[i].reg = val; \
6262 inst.operands[i].isscalar = 1; \
6266 #define po_misc_or_fail(expr) \
6274 #define po_misc_or_fail_no_backtrack(expr) \
6278 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6279 backtrack_pos = 0; \
6280 if (result != PARSE_OPERAND_SUCCESS) \
6285 #define po_barrier_or_imm(str) \
6288 val = parse_barrier (&str); \
6291 if (ISALPHA (*str)) \
6298 if ((inst.instruction & 0xf0) == 0x60 \
6301 /* ISB can only take SY as an option. */ \
6302 inst.error = _("invalid barrier type"); \
6309 skip_whitespace (str
);
6311 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6313 op_parse_code
= upat
[i
];
6314 if (op_parse_code
>= 1<<16)
6315 op_parse_code
= thumb
? (op_parse_code
>> 16)
6316 : (op_parse_code
& ((1<<16)-1));
6318 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6320 /* Remember where we are in case we need to backtrack. */
6321 gas_assert (!backtrack_pos
);
6322 backtrack_pos
= str
;
6323 backtrack_error
= inst
.error
;
6324 backtrack_index
= i
;
6327 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6328 po_char_or_fail (',');
6330 switch (op_parse_code
)
6338 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6339 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6340 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6341 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6342 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6343 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6345 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6347 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6349 /* Also accept generic coprocessor regs for unknown registers. */
6351 po_reg_or_fail (REG_TYPE_CN
);
6353 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6354 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6355 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6356 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6357 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6358 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6359 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6360 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6361 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6362 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6364 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6366 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6367 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6369 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6371 /* Neon scalar. Using an element size of 8 means that some invalid
6372 scalars are accepted here, so deal with those in later code. */
6373 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6377 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6380 po_imm_or_fail (0, 0, TRUE
);
6385 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6390 po_scalar_or_goto (8, try_rr
);
6393 po_reg_or_fail (REG_TYPE_RN
);
6399 po_scalar_or_goto (8, try_nsdq
);
6402 po_reg_or_fail (REG_TYPE_NSDQ
);
6408 po_scalar_or_goto (8, try_ndq
);
6411 po_reg_or_fail (REG_TYPE_NDQ
);
6417 po_scalar_or_goto (8, try_vfd
);
6420 po_reg_or_fail (REG_TYPE_VFD
);
6425 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6426 not careful then bad things might happen. */
6427 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6432 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6435 /* There's a possibility of getting a 64-bit immediate here, so
6436 we need special handling. */
6437 if (parse_big_immediate (&str
, i
) == FAIL
)
6439 inst
.error
= _("immediate value is out of range");
6447 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6450 po_imm_or_fail (0, 63, TRUE
);
6455 po_char_or_fail ('[');
6456 po_reg_or_fail (REG_TYPE_RN
);
6457 po_char_or_fail (']');
6463 po_reg_or_fail (REG_TYPE_RN
);
6464 if (skip_past_char (&str
, '!') == SUCCESS
)
6465 inst
.operands
[i
].writeback
= 1;
6469 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6470 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6471 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6472 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6473 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6474 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6475 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6476 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6477 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6478 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6479 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6480 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6482 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6484 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6485 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6487 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6488 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6489 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6490 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6492 /* Immediate variants */
6494 po_char_or_fail ('{');
6495 po_imm_or_fail (0, 255, TRUE
);
6496 po_char_or_fail ('}');
6500 /* The expression parser chokes on a trailing !, so we have
6501 to find it first and zap it. */
6504 while (*s
&& *s
!= ',')
6509 inst
.operands
[i
].writeback
= 1;
6511 po_imm_or_fail (0, 31, TRUE
);
6519 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6524 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6529 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6531 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6533 val
= parse_reloc (&str
);
6536 inst
.error
= _("unrecognized relocation suffix");
6539 else if (val
!= BFD_RELOC_UNUSED
)
6541 inst
.operands
[i
].imm
= val
;
6542 inst
.operands
[i
].hasreloc
= 1;
6547 /* Operand for MOVW or MOVT. */
6549 po_misc_or_fail (parse_half (&str
));
6552 /* Register or expression. */
6553 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6554 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6556 /* Register or immediate. */
6557 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6558 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6560 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6562 if (!is_immediate_prefix (*str
))
6565 val
= parse_fpa_immediate (&str
);
6568 /* FPA immediates are encoded as registers 8-15.
6569 parse_fpa_immediate has already applied the offset. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isreg
= 1;
6574 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6575 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6577 /* Two kinds of register. */
6580 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6582 || (rege
->type
!= REG_TYPE_MMXWR
6583 && rege
->type
!= REG_TYPE_MMXWC
6584 && rege
->type
!= REG_TYPE_MMXWCG
))
6586 inst
.error
= _("iWMMXt data or control register expected");
6589 inst
.operands
[i
].reg
= rege
->number
;
6590 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6596 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6598 || (rege
->type
!= REG_TYPE_MMXWC
6599 && rege
->type
!= REG_TYPE_MMXWCG
))
6601 inst
.error
= _("iWMMXt control register expected");
6604 inst
.operands
[i
].reg
= rege
->number
;
6605 inst
.operands
[i
].isreg
= 1;
6610 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6611 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6612 case OP_oROR
: val
= parse_ror (&str
); break;
6613 case OP_COND
: val
= parse_cond (&str
); break;
6614 case OP_oBARRIER_I15
:
6615 po_barrier_or_imm (str
); break;
6617 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6623 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6624 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6626 inst
.error
= _("Banked registers are not available with this "
6632 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6636 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6639 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6641 if (strncasecmp (str
, "APSR_", 5) == 0)
6648 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6649 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6650 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6651 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6652 default: found
= 16;
6656 inst
.operands
[i
].isvec
= 1;
6657 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6658 inst
.operands
[i
].reg
= REG_PC
;
6665 po_misc_or_fail (parse_tb (&str
));
6668 /* Register lists. */
6670 val
= parse_reg_list (&str
);
6673 inst
.operands
[1].writeback
= 1;
6679 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6683 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6687 /* Allow Q registers too. */
6688 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6693 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6695 inst
.operands
[i
].issingle
= 1;
6700 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6705 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6706 &inst
.operands
[i
].vectype
);
6709 /* Addressing modes */
6711 po_misc_or_fail (parse_address (&str
, i
));
6715 po_misc_or_fail_no_backtrack (
6716 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6720 po_misc_or_fail_no_backtrack (
6721 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6725 po_misc_or_fail_no_backtrack (
6726 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6730 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6734 po_misc_or_fail_no_backtrack (
6735 parse_shifter_operand_group_reloc (&str
, i
));
6739 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6743 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6747 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6751 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6754 /* Various value-based sanity checks and shared operations. We
6755 do not signal immediate failures for the register constraints;
6756 this allows a syntax error to take precedence. */
6757 switch (op_parse_code
)
6765 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6766 inst
.error
= BAD_PC
;
6771 if (inst
.operands
[i
].isreg
)
6773 if (inst
.operands
[i
].reg
== REG_PC
)
6774 inst
.error
= BAD_PC
;
6775 else if (inst
.operands
[i
].reg
== REG_SP
)
6776 inst
.error
= BAD_SP
;
6781 if (inst
.operands
[i
].isreg
6782 && inst
.operands
[i
].reg
== REG_PC
6783 && (inst
.operands
[i
].writeback
|| thumb
))
6784 inst
.error
= BAD_PC
;
6793 case OP_oBARRIER_I15
:
6802 inst
.operands
[i
].imm
= val
;
6809 /* If we get here, this operand was successfully parsed. */
6810 inst
.operands
[i
].present
= 1;
6814 inst
.error
= BAD_ARGS
;
6819 /* The parse routine should already have set inst.error, but set a
6820 default here just in case. */
6822 inst
.error
= _("syntax error");
6826 /* Do not backtrack over a trailing optional argument that
6827 absorbed some text. We will only fail again, with the
6828 'garbage following instruction' error message, which is
6829 probably less helpful than the current one. */
6830 if (backtrack_index
== i
&& backtrack_pos
!= str
6831 && upat
[i
+1] == OP_stop
)
6834 inst
.error
= _("syntax error");
6838 /* Try again, skipping the optional argument at backtrack_pos. */
6839 str
= backtrack_pos
;
6840 inst
.error
= backtrack_error
;
6841 inst
.operands
[backtrack_index
].present
= 0;
6842 i
= backtrack_index
;
6846 /* Check that we have parsed all the arguments. */
6847 if (*str
!= '\0' && !inst
.error
)
6848 inst
.error
= _("garbage following instruction");
6850 return inst
.error
? FAIL
: SUCCESS
;
6853 #undef po_char_or_fail
6854 #undef po_reg_or_fail
6855 #undef po_reg_or_goto
6856 #undef po_imm_or_fail
6857 #undef po_scalar_or_fail
6858 #undef po_barrier_or_imm
6860 /* Shorthand macro for instruction encoding functions issuing errors. */
6861 #define constraint(expr, err) \
6872 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6873 instructions are unpredictable if these registers are used. This
6874 is the BadReg predicate in ARM's Thumb-2 documentation. */
6875 #define reject_bad_reg(reg) \
6877 if (reg == REG_SP || reg == REG_PC) \
6879 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6884 /* If REG is R13 (the stack pointer), warn that its use is
6886 #define warn_deprecated_sp(reg) \
6888 if (warn_on_deprecated && reg == REG_SP) \
6889 as_warn (_("use of r13 is deprecated")); \
6892 /* Functions for operand encoding. ARM, then Thumb. */
6894 #define rotate_left(v, n) (v << n | v >> (32 - n))
6896 /* If VAL can be encoded in the immediate field of an ARM instruction,
6897 return the encoded form. Otherwise, return FAIL. */
6900 encode_arm_immediate (unsigned int val
)
6904 for (i
= 0; i
< 32; i
+= 2)
6905 if ((a
= rotate_left (val
, i
)) <= 0xff)
6906 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6911 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6912 return the encoded form. Otherwise, return FAIL. */
6914 encode_thumb32_immediate (unsigned int val
)
6921 for (i
= 1; i
<= 24; i
++)
6924 if ((val
& ~(0xff << i
)) == 0)
6925 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6929 if (val
== ((a
<< 16) | a
))
6931 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6935 if (val
== ((a
<< 16) | a
))
6936 return 0x200 | (a
>> 8);
6940 /* Encode a VFP SP or DP register number into inst.instruction. */
6943 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6945 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6948 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6951 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6954 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6959 first_error (_("D register out of range for selected VFP version"));
6967 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6971 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6975 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6979 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6983 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6987 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6995 /* Encode a <shift> in an ARM-format instruction. The immediate,
6996 if any, is handled by md_apply_fix. */
6998 encode_arm_shift (int i
)
7000 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7001 inst
.instruction
|= SHIFT_ROR
<< 5;
7004 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7005 if (inst
.operands
[i
].immisreg
)
7007 inst
.instruction
|= SHIFT_BY_REG
;
7008 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7011 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7016 encode_arm_shifter_operand (int i
)
7018 if (inst
.operands
[i
].isreg
)
7020 inst
.instruction
|= inst
.operands
[i
].reg
;
7021 encode_arm_shift (i
);
7025 inst
.instruction
|= INST_IMMEDIATE
;
7026 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7027 inst
.instruction
|= inst
.operands
[i
].imm
;
7031 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7033 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7035 gas_assert (inst
.operands
[i
].isreg
);
7036 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7038 if (inst
.operands
[i
].preind
)
7042 inst
.error
= _("instruction does not accept preindexed addressing");
7045 inst
.instruction
|= PRE_INDEX
;
7046 if (inst
.operands
[i
].writeback
)
7047 inst
.instruction
|= WRITE_BACK
;
7050 else if (inst
.operands
[i
].postind
)
7052 gas_assert (inst
.operands
[i
].writeback
);
7054 inst
.instruction
|= WRITE_BACK
;
7056 else /* unindexed - only for coprocessor */
7058 inst
.error
= _("instruction does not accept unindexed addressing");
7062 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7063 && (((inst
.instruction
& 0x000f0000) >> 16)
7064 == ((inst
.instruction
& 0x0000f000) >> 12)))
7065 as_warn ((inst
.instruction
& LOAD_BIT
)
7066 ? _("destination register same as write-back base")
7067 : _("source register same as write-back base"));
7070 /* inst.operands[i] was set up by parse_address. Encode it into an
7071 ARM-format mode 2 load or store instruction. If is_t is true,
7072 reject forms that cannot be used with a T instruction (i.e. not
7075 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7077 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7079 encode_arm_addr_mode_common (i
, is_t
);
7081 if (inst
.operands
[i
].immisreg
)
7083 constraint ((inst
.operands
[i
].imm
== REG_PC
7084 || (is_pc
&& inst
.operands
[i
].writeback
)),
7086 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7087 inst
.instruction
|= inst
.operands
[i
].imm
;
7088 if (!inst
.operands
[i
].negative
)
7089 inst
.instruction
|= INDEX_UP
;
7090 if (inst
.operands
[i
].shifted
)
7092 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7093 inst
.instruction
|= SHIFT_ROR
<< 5;
7096 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7097 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7101 else /* immediate offset in inst.reloc */
7103 if (is_pc
&& !inst
.reloc
.pc_rel
)
7105 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7107 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7108 cannot use PC in addressing.
7109 PC cannot be used in writeback addressing, either. */
7110 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7113 /* Use of PC in str is deprecated for ARMv7. */
7114 if (warn_on_deprecated
7116 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7117 as_warn (_("use of PC in this instruction is deprecated"));
7120 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7122 /* Prefer + for zero encoded value. */
7123 if (!inst
.operands
[i
].negative
)
7124 inst
.instruction
|= INDEX_UP
;
7125 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7130 /* inst.operands[i] was set up by parse_address. Encode it into an
7131 ARM-format mode 3 load or store instruction. Reject forms that
7132 cannot be used with such instructions. If is_t is true, reject
7133 forms that cannot be used with a T instruction (i.e. not
7136 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7138 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7140 inst
.error
= _("instruction does not accept scaled register index");
7144 encode_arm_addr_mode_common (i
, is_t
);
7146 if (inst
.operands
[i
].immisreg
)
7148 constraint ((inst
.operands
[i
].imm
== REG_PC
7149 || inst
.operands
[i
].reg
== REG_PC
),
7151 inst
.instruction
|= inst
.operands
[i
].imm
;
7152 if (!inst
.operands
[i
].negative
)
7153 inst
.instruction
|= INDEX_UP
;
7155 else /* immediate offset in inst.reloc */
7157 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7158 && inst
.operands
[i
].writeback
),
7160 inst
.instruction
|= HWOFFSET_IMM
;
7161 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7163 /* Prefer + for zero encoded value. */
7164 if (!inst
.operands
[i
].negative
)
7165 inst
.instruction
|= INDEX_UP
;
7167 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7172 /* inst.operands[i] was set up by parse_address. Encode it into an
7173 ARM-format instruction. Reject all forms which cannot be encoded
7174 into a coprocessor load/store instruction. If wb_ok is false,
7175 reject use of writeback; if unind_ok is false, reject use of
7176 unindexed addressing. If reloc_override is not 0, use it instead
7177 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7178 (in which case it is preserved). */
7181 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7183 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7185 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7187 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7189 gas_assert (!inst
.operands
[i
].writeback
);
7192 inst
.error
= _("instruction does not support unindexed addressing");
7195 inst
.instruction
|= inst
.operands
[i
].imm
;
7196 inst
.instruction
|= INDEX_UP
;
7200 if (inst
.operands
[i
].preind
)
7201 inst
.instruction
|= PRE_INDEX
;
7203 if (inst
.operands
[i
].writeback
)
7205 if (inst
.operands
[i
].reg
== REG_PC
)
7207 inst
.error
= _("pc may not be used with write-back");
7212 inst
.error
= _("instruction does not support writeback");
7215 inst
.instruction
|= WRITE_BACK
;
7219 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7220 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7221 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7222 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7225 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7227 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7230 /* Prefer + for zero encoded value. */
7231 if (!inst
.operands
[i
].negative
)
7232 inst
.instruction
|= INDEX_UP
;
7237 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7238 Determine whether it can be performed with a move instruction; if
7239 it can, convert inst.instruction to that move instruction and
7240 return TRUE; if it can't, convert inst.instruction to a literal-pool
7241 load and return FALSE. If this is not a valid thing to do in the
7242 current context, set inst.error and return TRUE.
7244 inst.operands[i] describes the destination register. */
7247 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7252 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7256 if ((inst
.instruction
& tbit
) == 0)
7258 inst
.error
= _("invalid pseudo operation");
7261 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7263 inst
.error
= _("constant expression expected");
7266 if (inst
.reloc
.exp
.X_op
== O_constant
)
7270 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7272 /* This can be done with a mov(1) instruction. */
7273 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7274 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7280 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7283 /* This can be done with a mov instruction. */
7284 inst
.instruction
&= LITERAL_MASK
;
7285 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7286 inst
.instruction
|= value
& 0xfff;
7290 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7293 /* This can be done with a mvn instruction. */
7294 inst
.instruction
&= LITERAL_MASK
;
7295 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7296 inst
.instruction
|= value
& 0xfff;
7302 if (add_to_lit_pool () == FAIL
)
7304 inst
.error
= _("literal pool insertion failed");
7307 inst
.operands
[1].reg
= REG_PC
;
7308 inst
.operands
[1].isreg
= 1;
7309 inst
.operands
[1].preind
= 1;
7310 inst
.reloc
.pc_rel
= 1;
7311 inst
.reloc
.type
= (thumb_p
7312 ? BFD_RELOC_ARM_THUMB_OFFSET
7314 ? BFD_RELOC_ARM_HWLITERAL
7315 : BFD_RELOC_ARM_LITERAL
));
7319 /* Functions for instruction encoding, sorted by sub-architecture.
7320 First some generics; their names are taken from the conventional
7321 bit positions for register arguments in ARM format instructions. */
7331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7337 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7338 inst
.instruction
|= inst
.operands
[1].reg
;
7344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7345 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7351 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7352 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7358 unsigned Rn
= inst
.operands
[2].reg
;
7359 /* Enforce restrictions on SWP instruction. */
7360 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7362 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7363 _("Rn must not overlap other operands"));
7365 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7366 if (warn_on_deprecated
7367 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7368 as_warn (_("swp{b} use is deprecated for this architecture"));
7371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7372 inst
.instruction
|= inst
.operands
[1].reg
;
7373 inst
.instruction
|= Rn
<< 16;
7379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7380 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7381 inst
.instruction
|= inst
.operands
[2].reg
;
7387 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7388 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7389 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7390 || inst
.reloc
.exp
.X_add_number
!= 0),
7392 inst
.instruction
|= inst
.operands
[0].reg
;
7393 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7394 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7400 inst
.instruction
|= inst
.operands
[0].imm
;
7406 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7407 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7410 /* ARM instructions, in alphabetical order by function name (except
7411 that wrapper functions appear immediately after the function they
7414 /* This is a pseudo-op of the form "adr rd, label" to be converted
7415 into a relative address of the form "add rd, pc, #label-.-8". */
7420 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7422 /* Frag hacking will turn this into a sub instruction if the offset turns
7423 out to be negative. */
7424 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7425 inst
.reloc
.pc_rel
= 1;
7426 inst
.reloc
.exp
.X_add_number
-= 8;
7429 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7430 into a relative address of the form:
7431 add rd, pc, #low(label-.-8)"
7432 add rd, rd, #high(label-.-8)" */
7437 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7439 /* Frag hacking will turn this into a sub instruction if the offset turns
7440 out to be negative. */
7441 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7442 inst
.reloc
.pc_rel
= 1;
7443 inst
.size
= INSN_SIZE
* 2;
7444 inst
.reloc
.exp
.X_add_number
-= 8;
7450 if (!inst
.operands
[1].present
)
7451 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7453 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7454 encode_arm_shifter_operand (2);
7460 if (inst
.operands
[0].present
)
7462 constraint ((inst
.instruction
& 0xf0) != 0x40
7463 && inst
.operands
[0].imm
> 0xf
7464 && inst
.operands
[0].imm
< 0x0,
7465 _("bad barrier type"));
7466 inst
.instruction
|= inst
.operands
[0].imm
;
7469 inst
.instruction
|= 0xf;
7475 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7476 constraint (msb
> 32, _("bit-field extends past end of register"));
7477 /* The instruction encoding stores the LSB and MSB,
7478 not the LSB and width. */
7479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7480 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7481 inst
.instruction
|= (msb
- 1) << 16;
7489 /* #0 in second position is alternative syntax for bfc, which is
7490 the same instruction but with REG_PC in the Rm field. */
7491 if (!inst
.operands
[1].isreg
)
7492 inst
.operands
[1].reg
= REG_PC
;
7494 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7495 constraint (msb
> 32, _("bit-field extends past end of register"));
7496 /* The instruction encoding stores the LSB and MSB,
7497 not the LSB and width. */
7498 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7499 inst
.instruction
|= inst
.operands
[1].reg
;
7500 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7501 inst
.instruction
|= (msb
- 1) << 16;
7507 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7508 _("bit-field extends past end of register"));
7509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7510 inst
.instruction
|= inst
.operands
[1].reg
;
7511 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7512 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7515 /* ARM V5 breakpoint instruction (argument parse)
7516 BKPT <16 bit unsigned immediate>
7517 Instruction is not conditional.
7518 The bit pattern given in insns[] has the COND_ALWAYS condition,
7519 and it is an error if the caller tried to override that. */
7524 /* Top 12 of 16 bits to bits 19:8. */
7525 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7527 /* Bottom 4 of 16 bits to bits 3:0. */
7528 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7532 encode_branch (int default_reloc
)
7534 if (inst
.operands
[0].hasreloc
)
7536 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7537 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7538 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7539 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7540 ? BFD_RELOC_ARM_PLT32
7541 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7544 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7545 inst
.reloc
.pc_rel
= 1;
7552 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7553 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7556 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7563 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7565 if (inst
.cond
== COND_ALWAYS
)
7566 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7568 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7572 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7575 /* ARM V5 branch-link-exchange instruction (argument parse)
7576 BLX <target_addr> ie BLX(1)
7577 BLX{<condition>} <Rm> ie BLX(2)
7578 Unfortunately, there are two different opcodes for this mnemonic.
7579 So, the insns[].value is not used, and the code here zaps values
7580 into inst.instruction.
7581 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7586 if (inst
.operands
[0].isreg
)
7588 /* Arg is a register; the opcode provided by insns[] is correct.
7589 It is not illegal to do "blx pc", just useless. */
7590 if (inst
.operands
[0].reg
== REG_PC
)
7591 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7593 inst
.instruction
|= inst
.operands
[0].reg
;
7597 /* Arg is an address; this instruction cannot be executed
7598 conditionally, and the opcode must be adjusted.
7599 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7600 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7601 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7602 inst
.instruction
= 0xfa000000;
7603 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7610 bfd_boolean want_reloc
;
7612 if (inst
.operands
[0].reg
== REG_PC
)
7613 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7615 inst
.instruction
|= inst
.operands
[0].reg
;
7616 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7617 it is for ARMv4t or earlier. */
7618 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7619 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7623 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7628 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7632 /* ARM v5TEJ. Jump to Jazelle code. */
7637 if (inst
.operands
[0].reg
== REG_PC
)
7638 as_tsktsk (_("use of r15 in bxj is not really useful"));
7640 inst
.instruction
|= inst
.operands
[0].reg
;
7643 /* Co-processor data operation:
7644 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7645 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7649 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7650 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7651 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7652 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7653 inst
.instruction
|= inst
.operands
[4].reg
;
7654 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7660 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7661 encode_arm_shifter_operand (1);
7664 /* Transfer between coprocessor and ARM registers.
7665 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7670 No special properties. */
7677 Rd
= inst
.operands
[2].reg
;
7680 if (inst
.instruction
== 0xee000010
7681 || inst
.instruction
== 0xfe000010)
7683 reject_bad_reg (Rd
);
7686 constraint (Rd
== REG_SP
, BAD_SP
);
7691 if (inst
.instruction
== 0xe000010)
7692 constraint (Rd
== REG_PC
, BAD_PC
);
7696 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7697 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7698 inst
.instruction
|= Rd
<< 12;
7699 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7700 inst
.instruction
|= inst
.operands
[4].reg
;
7701 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7704 /* Transfer between coprocessor register and pair of ARM registers.
7705 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7710 Two XScale instructions are special cases of these:
7712 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7713 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7715 Result unpredictable if Rd or Rn is R15. */
7722 Rd
= inst
.operands
[2].reg
;
7723 Rn
= inst
.operands
[3].reg
;
7727 reject_bad_reg (Rd
);
7728 reject_bad_reg (Rn
);
7732 constraint (Rd
== REG_PC
, BAD_PC
);
7733 constraint (Rn
== REG_PC
, BAD_PC
);
7736 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7737 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7738 inst
.instruction
|= Rd
<< 12;
7739 inst
.instruction
|= Rn
<< 16;
7740 inst
.instruction
|= inst
.operands
[4].reg
;
7746 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7747 if (inst
.operands
[1].present
)
7749 inst
.instruction
|= CPSI_MMOD
;
7750 inst
.instruction
|= inst
.operands
[1].imm
;
7757 inst
.instruction
|= inst
.operands
[0].imm
;
7763 unsigned Rd
, Rn
, Rm
;
7765 Rd
= inst
.operands
[0].reg
;
7766 Rn
= (inst
.operands
[1].present
7767 ? inst
.operands
[1].reg
: Rd
);
7768 Rm
= inst
.operands
[2].reg
;
7770 constraint ((Rd
== REG_PC
), BAD_PC
);
7771 constraint ((Rn
== REG_PC
), BAD_PC
);
7772 constraint ((Rm
== REG_PC
), BAD_PC
);
7774 inst
.instruction
|= Rd
<< 16;
7775 inst
.instruction
|= Rn
<< 0;
7776 inst
.instruction
|= Rm
<< 8;
7782 /* There is no IT instruction in ARM mode. We
7783 process it to do the validation as if in
7784 thumb mode, just in case the code gets
7785 assembled for thumb using the unified syntax. */
7790 set_it_insn_type (IT_INSN
);
7791 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7792 now_it
.cc
= inst
.operands
[0].imm
;
7799 int base_reg
= inst
.operands
[0].reg
;
7800 int range
= inst
.operands
[1].imm
;
7802 inst
.instruction
|= base_reg
<< 16;
7803 inst
.instruction
|= range
;
7805 if (inst
.operands
[1].writeback
)
7806 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7808 if (inst
.operands
[0].writeback
)
7810 inst
.instruction
|= WRITE_BACK
;
7811 /* Check for unpredictable uses of writeback. */
7812 if (inst
.instruction
& LOAD_BIT
)
7814 /* Not allowed in LDM type 2. */
7815 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7816 && ((range
& (1 << REG_PC
)) == 0))
7817 as_warn (_("writeback of base register is UNPREDICTABLE"));
7818 /* Only allowed if base reg not in list for other types. */
7819 else if (range
& (1 << base_reg
))
7820 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7824 /* Not allowed for type 2. */
7825 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7826 as_warn (_("writeback of base register is UNPREDICTABLE"));
7827 /* Only allowed if base reg not in list, or first in list. */
7828 else if ((range
& (1 << base_reg
))
7829 && (range
& ((1 << base_reg
) - 1)))
7830 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7835 /* ARMv5TE load-consecutive (argument parse)
7844 constraint (inst
.operands
[0].reg
% 2 != 0,
7845 _("first transfer register must be even"));
7846 constraint (inst
.operands
[1].present
7847 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7848 _("can only transfer two consecutive registers"));
7849 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7850 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7852 if (!inst
.operands
[1].present
)
7853 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7855 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7856 register and the first register written; we have to diagnose
7857 overlap between the base and the second register written here. */
7859 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7860 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7861 as_warn (_("base register written back, and overlaps "
7862 "second transfer register"));
7864 if (!(inst
.instruction
& V4_STR_BIT
))
7866 /* For an index-register load, the index register must not overlap the
7867 destination (even if not write-back). */
7868 if (inst
.operands
[2].immisreg
7869 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7870 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7871 as_warn (_("index register overlaps transfer register"));
7873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7874 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7880 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7881 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7882 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7883 || inst
.operands
[1].negative
7884 /* This can arise if the programmer has written
7886 or if they have mistakenly used a register name as the last
7889 It is very difficult to distinguish between these two cases
7890 because "rX" might actually be a label. ie the register
7891 name has been occluded by a symbol of the same name. So we
7892 just generate a general 'bad addressing mode' type error
7893 message and leave it up to the programmer to discover the
7894 true cause and fix their mistake. */
7895 || (inst
.operands
[1].reg
== REG_PC
),
7898 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7899 || inst
.reloc
.exp
.X_add_number
!= 0,
7900 _("offset must be zero in ARM encoding"));
7902 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7905 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7906 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7912 constraint (inst
.operands
[0].reg
% 2 != 0,
7913 _("even register required"));
7914 constraint (inst
.operands
[1].present
7915 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7916 _("can only load two consecutive registers"));
7917 /* If op 1 were present and equal to PC, this function wouldn't
7918 have been called in the first place. */
7919 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7922 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7925 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7926 which is not a multiple of four is UNPREDICTABLE. */
7928 check_ldr_r15_aligned (void)
7930 constraint (!(inst
.operands
[1].immisreg
)
7931 && (inst
.operands
[0].reg
== REG_PC
7932 && inst
.operands
[1].reg
== REG_PC
7933 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
7934 _("ldr to register 15 must be 4-byte alligned"));
7940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7941 if (!inst
.operands
[1].isreg
)
7942 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7944 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7945 check_ldr_r15_aligned ();
7951 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7953 if (inst
.operands
[1].preind
)
7955 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7956 || inst
.reloc
.exp
.X_add_number
!= 0,
7957 _("this instruction requires a post-indexed address"));
7959 inst
.operands
[1].preind
= 0;
7960 inst
.operands
[1].postind
= 1;
7961 inst
.operands
[1].writeback
= 1;
7963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7964 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7967 /* Halfword and signed-byte load/store operations. */
7972 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7974 if (!inst
.operands
[1].isreg
)
7975 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7977 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7983 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7985 if (inst
.operands
[1].preind
)
7987 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7988 || inst
.reloc
.exp
.X_add_number
!= 0,
7989 _("this instruction requires a post-indexed address"));
7991 inst
.operands
[1].preind
= 0;
7992 inst
.operands
[1].postind
= 1;
7993 inst
.operands
[1].writeback
= 1;
7995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7996 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7999 /* Co-processor register load/store.
8000 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8004 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8005 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8006 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8012 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8013 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8014 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8015 && !(inst
.instruction
& 0x00400000))
8016 as_tsktsk (_("Rd and Rm should be different in mla"));
8018 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8019 inst
.instruction
|= inst
.operands
[1].reg
;
8020 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8021 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8028 encode_arm_shifter_operand (1);
8031 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8038 top
= (inst
.instruction
& 0x00400000) != 0;
8039 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8040 _(":lower16: not allowed this instruction"));
8041 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8042 _(":upper16: not allowed instruction"));
8043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8044 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8046 imm
= inst
.reloc
.exp
.X_add_number
;
8047 /* The value is in two pieces: 0:11, 16:19. */
8048 inst
.instruction
|= (imm
& 0x00000fff);
8049 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8053 static void do_vfp_nsyn_opcode (const char *);
8056 do_vfp_nsyn_mrs (void)
8058 if (inst
.operands
[0].isvec
)
8060 if (inst
.operands
[1].reg
!= 1)
8061 first_error (_("operand 1 must be FPSCR"));
8062 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8063 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8064 do_vfp_nsyn_opcode ("fmstat");
8066 else if (inst
.operands
[1].isvec
)
8067 do_vfp_nsyn_opcode ("fmrx");
8075 do_vfp_nsyn_msr (void)
8077 if (inst
.operands
[0].isvec
)
8078 do_vfp_nsyn_opcode ("fmxr");
8088 unsigned Rt
= inst
.operands
[0].reg
;
8090 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8092 inst
.error
= BAD_SP
;
8096 /* APSR_ sets isvec. All other refs to PC are illegal. */
8097 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8099 inst
.error
= BAD_PC
;
8103 if (inst
.operands
[1].reg
!= 1)
8104 first_error (_("operand 1 must be FPSCR"));
8106 inst
.instruction
|= (Rt
<< 12);
8112 unsigned Rt
= inst
.operands
[1].reg
;
8115 reject_bad_reg (Rt
);
8116 else if (Rt
== REG_PC
)
8118 inst
.error
= BAD_PC
;
8122 if (inst
.operands
[0].reg
!= 1)
8123 first_error (_("operand 0 must be FPSCR"));
8125 inst
.instruction
|= (Rt
<< 12);
8133 if (do_vfp_nsyn_mrs () == SUCCESS
)
8136 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8137 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8139 if (inst
.operands
[1].isreg
)
8141 br
= inst
.operands
[1].reg
;
8142 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8143 as_bad (_("bad register for mrs"));
8147 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8148 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8150 _("'APSR', 'CPSR' or 'SPSR' expected"));
8151 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8154 inst
.instruction
|= br
;
8157 /* Two possible forms:
8158 "{C|S}PSR_<field>, Rm",
8159 "{C|S}PSR_f, #expression". */
8164 if (do_vfp_nsyn_msr () == SUCCESS
)
8167 inst
.instruction
|= inst
.operands
[0].imm
;
8168 if (inst
.operands
[1].isreg
)
8169 inst
.instruction
|= inst
.operands
[1].reg
;
8172 inst
.instruction
|= INST_IMMEDIATE
;
8173 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8174 inst
.reloc
.pc_rel
= 0;
8181 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8183 if (!inst
.operands
[2].present
)
8184 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8185 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8186 inst
.instruction
|= inst
.operands
[1].reg
;
8187 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8189 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8190 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8191 as_tsktsk (_("Rd and Rm should be different in mul"));
8194 /* Long Multiply Parser
8195 UMULL RdLo, RdHi, Rm, Rs
8196 SMULL RdLo, RdHi, Rm, Rs
8197 UMLAL RdLo, RdHi, Rm, Rs
8198 SMLAL RdLo, RdHi, Rm, Rs. */
8203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8205 inst
.instruction
|= inst
.operands
[2].reg
;
8206 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8208 /* rdhi and rdlo must be different. */
8209 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8210 as_tsktsk (_("rdhi and rdlo must be different"));
8212 /* rdhi, rdlo and rm must all be different before armv6. */
8213 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8214 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8215 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8216 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8222 if (inst
.operands
[0].present
8223 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8225 /* Architectural NOP hints are CPSR sets with no bits selected. */
8226 inst
.instruction
&= 0xf0000000;
8227 inst
.instruction
|= 0x0320f000;
8228 if (inst
.operands
[0].present
)
8229 inst
.instruction
|= inst
.operands
[0].imm
;
8233 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8234 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8235 Condition defaults to COND_ALWAYS.
8236 Error if Rd, Rn or Rm are R15. */
8241 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8242 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8243 inst
.instruction
|= inst
.operands
[2].reg
;
8244 if (inst
.operands
[3].present
)
8245 encode_arm_shift (3);
8248 /* ARM V6 PKHTB (Argument Parse). */
8253 if (!inst
.operands
[3].present
)
8255 /* If the shift specifier is omitted, turn the instruction
8256 into pkhbt rd, rm, rn. */
8257 inst
.instruction
&= 0xfff00010;
8258 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8259 inst
.instruction
|= inst
.operands
[1].reg
;
8260 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8265 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8266 inst
.instruction
|= inst
.operands
[2].reg
;
8267 encode_arm_shift (3);
8271 /* ARMv5TE: Preload-Cache
8272 MP Extensions: Preload for write
8276 Syntactically, like LDR with B=1, W=0, L=1. */
8281 constraint (!inst
.operands
[0].isreg
,
8282 _("'[' expected after PLD mnemonic"));
8283 constraint (inst
.operands
[0].postind
,
8284 _("post-indexed expression used in preload instruction"));
8285 constraint (inst
.operands
[0].writeback
,
8286 _("writeback used in preload instruction"));
8287 constraint (!inst
.operands
[0].preind
,
8288 _("unindexed addressing used in preload instruction"));
8289 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8292 /* ARMv7: PLI <addr_mode> */
8296 constraint (!inst
.operands
[0].isreg
,
8297 _("'[' expected after PLI mnemonic"));
8298 constraint (inst
.operands
[0].postind
,
8299 _("post-indexed expression used in preload instruction"));
8300 constraint (inst
.operands
[0].writeback
,
8301 _("writeback used in preload instruction"));
8302 constraint (!inst
.operands
[0].preind
,
8303 _("unindexed addressing used in preload instruction"));
8304 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8305 inst
.instruction
&= ~PRE_INDEX
;
8311 inst
.operands
[1] = inst
.operands
[0];
8312 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8313 inst
.operands
[0].isreg
= 1;
8314 inst
.operands
[0].writeback
= 1;
8315 inst
.operands
[0].reg
= REG_SP
;
8319 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8320 word at the specified address and the following word
8322 Unconditionally executed.
8323 Error if Rn is R15. */
8328 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8329 if (inst
.operands
[0].writeback
)
8330 inst
.instruction
|= WRITE_BACK
;
8333 /* ARM V6 ssat (argument parse). */
8338 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8339 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8340 inst
.instruction
|= inst
.operands
[2].reg
;
8342 if (inst
.operands
[3].present
)
8343 encode_arm_shift (3);
8346 /* ARM V6 usat (argument parse). */
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8352 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8353 inst
.instruction
|= inst
.operands
[2].reg
;
8355 if (inst
.operands
[3].present
)
8356 encode_arm_shift (3);
8359 /* ARM V6 ssat16 (argument parse). */
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8365 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8366 inst
.instruction
|= inst
.operands
[2].reg
;
8372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8373 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8374 inst
.instruction
|= inst
.operands
[2].reg
;
8377 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8378 preserving the other bits.
8380 setend <endian_specifier>, where <endian_specifier> is either
8386 if (inst
.operands
[0].imm
)
8387 inst
.instruction
|= 0x200;
8393 unsigned int Rm
= (inst
.operands
[1].present
8394 ? inst
.operands
[1].reg
8395 : inst
.operands
[0].reg
);
8397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8398 inst
.instruction
|= Rm
;
8399 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8401 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8402 inst
.instruction
|= SHIFT_BY_REG
;
8403 /* PR 12854: Error on extraneous shifts. */
8404 constraint (inst
.operands
[2].shifted
,
8405 _("extraneous shift as part of operand to shift insn"));
8408 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8414 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8415 inst
.reloc
.pc_rel
= 0;
8421 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8422 inst
.reloc
.pc_rel
= 0;
8428 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8429 inst
.reloc
.pc_rel
= 0;
8432 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8433 SMLAxy{cond} Rd,Rm,Rs,Rn
8434 SMLAWy{cond} Rd,Rm,Rs,Rn
8435 Error if any register is R15. */
8440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8441 inst
.instruction
|= inst
.operands
[1].reg
;
8442 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8443 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8446 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8447 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8448 Error if any register is R15.
8449 Warning if Rdlo == Rdhi. */
8454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8456 inst
.instruction
|= inst
.operands
[2].reg
;
8457 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8459 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8460 as_tsktsk (_("rdhi and rdlo must be different"));
8463 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8464 SMULxy{cond} Rd,Rm,Rs
8465 Error if any register is R15. */
8470 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8471 inst
.instruction
|= inst
.operands
[1].reg
;
8472 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8475 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8476 the same for both ARM and Thumb-2. */
8483 if (inst
.operands
[0].present
)
8485 reg
= inst
.operands
[0].reg
;
8486 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8491 inst
.instruction
|= reg
<< 16;
8492 inst
.instruction
|= inst
.operands
[1].imm
;
8493 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8494 inst
.instruction
|= WRITE_BACK
;
8497 /* ARM V6 strex (argument parse). */
8502 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8503 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8504 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8505 || inst
.operands
[2].negative
8506 /* See comment in do_ldrex(). */
8507 || (inst
.operands
[2].reg
== REG_PC
),
8510 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8511 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8513 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8514 || inst
.reloc
.exp
.X_add_number
!= 0,
8515 _("offset must be zero in ARM encoding"));
8517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8518 inst
.instruction
|= inst
.operands
[1].reg
;
8519 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8520 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8526 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8527 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8528 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8529 || inst
.operands
[2].negative
,
8532 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8533 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8541 constraint (inst
.operands
[1].reg
% 2 != 0,
8542 _("even register required"));
8543 constraint (inst
.operands
[2].present
8544 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8545 _("can only store two consecutive registers"));
8546 /* If op 2 were present and equal to PC, this function wouldn't
8547 have been called in the first place. */
8548 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8550 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8551 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8552 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8556 inst
.instruction
|= inst
.operands
[1].reg
;
8557 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8560 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8561 extends it to 32-bits, and adds the result to a value in another
8562 register. You can specify a rotation by 0, 8, 16, or 24 bits
8563 before extracting the 16-bit value.
8564 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8565 Condition defaults to COND_ALWAYS.
8566 Error if any register uses R15. */
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8572 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8573 inst
.instruction
|= inst
.operands
[2].reg
;
8574 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8579 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8580 Condition defaults to COND_ALWAYS.
8581 Error if any register uses R15. */
8586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8587 inst
.instruction
|= inst
.operands
[1].reg
;
8588 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8591 /* VFP instructions. In a logical order: SP variant first, monad
8592 before dyad, arithmetic then move then load/store. */
8595 do_vfp_sp_monadic (void)
8597 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8598 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8602 do_vfp_sp_dyadic (void)
8604 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8605 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8606 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8610 do_vfp_sp_compare_z (void)
8612 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8616 do_vfp_dp_sp_cvt (void)
8618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8619 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8623 do_vfp_sp_dp_cvt (void)
8625 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8626 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8630 do_vfp_reg_from_sp (void)
8632 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8633 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8637 do_vfp_reg2_from_sp2 (void)
8639 constraint (inst
.operands
[2].imm
!= 2,
8640 _("only two consecutive VFP SP registers allowed here"));
8641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8642 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8643 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8647 do_vfp_sp_from_reg (void)
8649 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8650 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8654 do_vfp_sp2_from_reg2 (void)
8656 constraint (inst
.operands
[0].imm
!= 2,
8657 _("only two consecutive VFP SP registers allowed here"));
8658 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8659 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8660 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8664 do_vfp_sp_ldst (void)
8666 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8667 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8671 do_vfp_dp_ldst (void)
8673 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8674 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8679 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8681 if (inst
.operands
[0].writeback
)
8682 inst
.instruction
|= WRITE_BACK
;
8684 constraint (ldstm_type
!= VFP_LDSTMIA
,
8685 _("this addressing mode requires base-register writeback"));
8686 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8688 inst
.instruction
|= inst
.operands
[1].imm
;
8692 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8696 if (inst
.operands
[0].writeback
)
8697 inst
.instruction
|= WRITE_BACK
;
8699 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8700 _("this addressing mode requires base-register writeback"));
8702 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8703 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8705 count
= inst
.operands
[1].imm
<< 1;
8706 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8709 inst
.instruction
|= count
;
8713 do_vfp_sp_ldstmia (void)
8715 vfp_sp_ldstm (VFP_LDSTMIA
);
8719 do_vfp_sp_ldstmdb (void)
8721 vfp_sp_ldstm (VFP_LDSTMDB
);
8725 do_vfp_dp_ldstmia (void)
8727 vfp_dp_ldstm (VFP_LDSTMIA
);
8731 do_vfp_dp_ldstmdb (void)
8733 vfp_dp_ldstm (VFP_LDSTMDB
);
8737 do_vfp_xp_ldstmia (void)
8739 vfp_dp_ldstm (VFP_LDSTMIAX
);
8743 do_vfp_xp_ldstmdb (void)
8745 vfp_dp_ldstm (VFP_LDSTMDBX
);
8749 do_vfp_dp_rd_rm (void)
8751 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8752 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8756 do_vfp_dp_rn_rd (void)
8758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8759 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8763 do_vfp_dp_rd_rn (void)
8765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8766 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8770 do_vfp_dp_rd_rn_rm (void)
8772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8773 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8774 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8784 do_vfp_dp_rm_rd_rn (void)
8786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8787 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8788 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8791 /* VFPv3 instructions. */
8793 do_vfp_sp_const (void)
8795 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8796 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8797 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8801 do_vfp_dp_const (void)
8803 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8804 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8805 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8809 vfp_conv (int srcsize
)
8811 int immbits
= srcsize
- inst
.operands
[1].imm
;
8813 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
8815 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8816 i.e. immbits must be in range 0 - 16. */
8817 inst
.error
= _("immediate value out of range, expected range [0, 16]");
8820 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
8822 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8823 i.e. immbits must be in range 0 - 31. */
8824 inst
.error
= _("immediate value out of range, expected range [1, 32]");
8828 inst
.instruction
|= (immbits
& 1) << 5;
8829 inst
.instruction
|= (immbits
>> 1);
8833 do_vfp_sp_conv_16 (void)
8835 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8840 do_vfp_dp_conv_16 (void)
8842 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8847 do_vfp_sp_conv_32 (void)
8849 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8854 do_vfp_dp_conv_32 (void)
8856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8860 /* FPA instructions. Also in a logical order. */
8865 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8866 inst
.instruction
|= inst
.operands
[1].reg
;
8870 do_fpa_ldmstm (void)
8872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8873 switch (inst
.operands
[1].imm
)
8875 case 1: inst
.instruction
|= CP_T_X
; break;
8876 case 2: inst
.instruction
|= CP_T_Y
; break;
8877 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8882 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8884 /* The instruction specified "ea" or "fd", so we can only accept
8885 [Rn]{!}. The instruction does not really support stacking or
8886 unstacking, so we have to emulate these by setting appropriate
8887 bits and offsets. */
8888 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8889 || inst
.reloc
.exp
.X_add_number
!= 0,
8890 _("this instruction does not support indexing"));
8892 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8893 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8895 if (!(inst
.instruction
& INDEX_UP
))
8896 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8898 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8900 inst
.operands
[2].preind
= 0;
8901 inst
.operands
[2].postind
= 1;
8905 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8908 /* iWMMXt instructions: strictly in alphabetical order. */
8911 do_iwmmxt_tandorc (void)
8913 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8917 do_iwmmxt_textrc (void)
8919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8920 inst
.instruction
|= inst
.operands
[1].imm
;
8924 do_iwmmxt_textrm (void)
8926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8928 inst
.instruction
|= inst
.operands
[2].imm
;
8932 do_iwmmxt_tinsr (void)
8934 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8935 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8936 inst
.instruction
|= inst
.operands
[2].imm
;
8940 do_iwmmxt_tmia (void)
8942 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8943 inst
.instruction
|= inst
.operands
[1].reg
;
8944 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8948 do_iwmmxt_waligni (void)
8950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8952 inst
.instruction
|= inst
.operands
[2].reg
;
8953 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8957 do_iwmmxt_wmerge (void)
8959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8960 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8961 inst
.instruction
|= inst
.operands
[2].reg
;
8962 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8966 do_iwmmxt_wmov (void)
8968 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8971 inst
.instruction
|= inst
.operands
[1].reg
;
8975 do_iwmmxt_wldstbh (void)
8978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8980 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8982 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8983 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8987 do_iwmmxt_wldstw (void)
8989 /* RIWR_RIWC clears .isreg for a control register. */
8990 if (!inst
.operands
[0].isreg
)
8992 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8993 inst
.instruction
|= 0xf0000000;
8996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8997 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9001 do_iwmmxt_wldstd (void)
9003 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9004 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9005 && inst
.operands
[1].immisreg
)
9007 inst
.instruction
&= ~0x1a000ff;
9008 inst
.instruction
|= (0xf << 28);
9009 if (inst
.operands
[1].preind
)
9010 inst
.instruction
|= PRE_INDEX
;
9011 if (!inst
.operands
[1].negative
)
9012 inst
.instruction
|= INDEX_UP
;
9013 if (inst
.operands
[1].writeback
)
9014 inst
.instruction
|= WRITE_BACK
;
9015 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9016 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9017 inst
.instruction
|= inst
.operands
[1].imm
;
9020 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9024 do_iwmmxt_wshufh (void)
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9027 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9028 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9029 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9033 do_iwmmxt_wzero (void)
9035 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9036 inst
.instruction
|= inst
.operands
[0].reg
;
9037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9038 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9042 do_iwmmxt_wrwrwr_or_imm5 (void)
9044 if (inst
.operands
[2].isreg
)
9047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9048 _("immediate operand requires iWMMXt2"));
9050 if (inst
.operands
[2].imm
== 0)
9052 switch ((inst
.instruction
>> 20) & 0xf)
9058 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9059 inst
.operands
[2].imm
= 16;
9060 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9066 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9067 inst
.operands
[2].imm
= 32;
9068 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9075 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9077 wrn
= (inst
.instruction
>> 16) & 0xf;
9078 inst
.instruction
&= 0xff0fff0f;
9079 inst
.instruction
|= wrn
;
9080 /* Bail out here; the instruction is now assembled. */
9085 /* Map 32 -> 0, etc. */
9086 inst
.operands
[2].imm
&= 0x1f;
9087 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9091 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9092 operations first, then control, shift, and load/store. */
9094 /* Insns like "foo X,Y,Z". */
9097 do_mav_triple (void)
9099 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9100 inst
.instruction
|= inst
.operands
[1].reg
;
9101 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9104 /* Insns like "foo W,X,Y,Z".
9105 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9110 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9111 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9112 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9113 inst
.instruction
|= inst
.operands
[3].reg
;
9116 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9120 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9123 /* Maverick shift immediate instructions.
9124 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9125 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9130 int imm
= inst
.operands
[2].imm
;
9132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9135 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9136 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9137 Bit 4 should be 0. */
9138 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9140 inst
.instruction
|= imm
;
9143 /* XScale instructions. Also sorted arithmetic before move. */
9145 /* Xscale multiply-accumulate (argument parse)
9148 MIAxycc acc0,Rm,Rs. */
9153 inst
.instruction
|= inst
.operands
[1].reg
;
9154 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9157 /* Xscale move-accumulator-register (argument parse)
9159 MARcc acc0,RdLo,RdHi. */
9164 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9165 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9168 /* Xscale move-register-accumulator (argument parse)
9170 MRAcc RdLo,RdHi,acc0. */
9175 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9176 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9177 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9180 /* Encoding functions relevant only to Thumb. */
9182 /* inst.operands[i] is a shifted-register operand; encode
9183 it into inst.instruction in the format used by Thumb32. */
9186 encode_thumb32_shifted_operand (int i
)
9188 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9189 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9191 constraint (inst
.operands
[i
].immisreg
,
9192 _("shift by register not allowed in thumb mode"));
9193 inst
.instruction
|= inst
.operands
[i
].reg
;
9194 if (shift
== SHIFT_RRX
)
9195 inst
.instruction
|= SHIFT_ROR
<< 4;
9198 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9199 _("expression too complex"));
9201 constraint (value
> 32
9202 || (value
== 32 && (shift
== SHIFT_LSL
9203 || shift
== SHIFT_ROR
)),
9204 _("shift expression is too large"));
9208 else if (value
== 32)
9211 inst
.instruction
|= shift
<< 4;
9212 inst
.instruction
|= (value
& 0x1c) << 10;
9213 inst
.instruction
|= (value
& 0x03) << 6;
9218 /* inst.operands[i] was set up by parse_address. Encode it into a
9219 Thumb32 format load or store instruction. Reject forms that cannot
9220 be used with such instructions. If is_t is true, reject forms that
9221 cannot be used with a T instruction; if is_d is true, reject forms
9222 that cannot be used with a D instruction. If it is a store insn,
9226 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9228 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9230 constraint (!inst
.operands
[i
].isreg
,
9231 _("Instruction does not support =N addresses"));
9233 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9234 if (inst
.operands
[i
].immisreg
)
9236 constraint (is_pc
, BAD_PC_ADDRESSING
);
9237 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9238 constraint (inst
.operands
[i
].negative
,
9239 _("Thumb does not support negative register indexing"));
9240 constraint (inst
.operands
[i
].postind
,
9241 _("Thumb does not support register post-indexing"));
9242 constraint (inst
.operands
[i
].writeback
,
9243 _("Thumb does not support register indexing with writeback"));
9244 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9245 _("Thumb supports only LSL in shifted register indexing"));
9247 inst
.instruction
|= inst
.operands
[i
].imm
;
9248 if (inst
.operands
[i
].shifted
)
9250 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9251 _("expression too complex"));
9252 constraint (inst
.reloc
.exp
.X_add_number
< 0
9253 || inst
.reloc
.exp
.X_add_number
> 3,
9254 _("shift out of range"));
9255 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9257 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9259 else if (inst
.operands
[i
].preind
)
9261 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9262 constraint (is_t
&& inst
.operands
[i
].writeback
,
9263 _("cannot use writeback with this instruction"));
9264 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9265 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9269 inst
.instruction
|= 0x01000000;
9270 if (inst
.operands
[i
].writeback
)
9271 inst
.instruction
|= 0x00200000;
9275 inst
.instruction
|= 0x00000c00;
9276 if (inst
.operands
[i
].writeback
)
9277 inst
.instruction
|= 0x00000100;
9279 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9281 else if (inst
.operands
[i
].postind
)
9283 gas_assert (inst
.operands
[i
].writeback
);
9284 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9285 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9288 inst
.instruction
|= 0x00200000;
9290 inst
.instruction
|= 0x00000900;
9291 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9293 else /* unindexed - only for coprocessor */
9294 inst
.error
= _("instruction does not accept unindexed addressing");
9297 /* Table of Thumb instructions which exist in both 16- and 32-bit
9298 encodings (the latter only in post-V6T2 cores). The index is the
9299 value used in the insns table below. When there is more than one
9300 possible 16-bit encoding for the instruction, this table always
9302 Also contains several pseudo-instructions used during relaxation. */
9303 #define T16_32_TAB \
9304 X(_adc, 4140, eb400000), \
9305 X(_adcs, 4140, eb500000), \
9306 X(_add, 1c00, eb000000), \
9307 X(_adds, 1c00, eb100000), \
9308 X(_addi, 0000, f1000000), \
9309 X(_addis, 0000, f1100000), \
9310 X(_add_pc,000f, f20f0000), \
9311 X(_add_sp,000d, f10d0000), \
9312 X(_adr, 000f, f20f0000), \
9313 X(_and, 4000, ea000000), \
9314 X(_ands, 4000, ea100000), \
9315 X(_asr, 1000, fa40f000), \
9316 X(_asrs, 1000, fa50f000), \
9317 X(_b, e000, f000b000), \
9318 X(_bcond, d000, f0008000), \
9319 X(_bic, 4380, ea200000), \
9320 X(_bics, 4380, ea300000), \
9321 X(_cmn, 42c0, eb100f00), \
9322 X(_cmp, 2800, ebb00f00), \
9323 X(_cpsie, b660, f3af8400), \
9324 X(_cpsid, b670, f3af8600), \
9325 X(_cpy, 4600, ea4f0000), \
9326 X(_dec_sp,80dd, f1ad0d00), \
9327 X(_eor, 4040, ea800000), \
9328 X(_eors, 4040, ea900000), \
9329 X(_inc_sp,00dd, f10d0d00), \
9330 X(_ldmia, c800, e8900000), \
9331 X(_ldr, 6800, f8500000), \
9332 X(_ldrb, 7800, f8100000), \
9333 X(_ldrh, 8800, f8300000), \
9334 X(_ldrsb, 5600, f9100000), \
9335 X(_ldrsh, 5e00, f9300000), \
9336 X(_ldr_pc,4800, f85f0000), \
9337 X(_ldr_pc2,4800, f85f0000), \
9338 X(_ldr_sp,9800, f85d0000), \
9339 X(_lsl, 0000, fa00f000), \
9340 X(_lsls, 0000, fa10f000), \
9341 X(_lsr, 0800, fa20f000), \
9342 X(_lsrs, 0800, fa30f000), \
9343 X(_mov, 2000, ea4f0000), \
9344 X(_movs, 2000, ea5f0000), \
9345 X(_mul, 4340, fb00f000), \
9346 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9347 X(_mvn, 43c0, ea6f0000), \
9348 X(_mvns, 43c0, ea7f0000), \
9349 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9350 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9351 X(_orr, 4300, ea400000), \
9352 X(_orrs, 4300, ea500000), \
9353 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9354 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9355 X(_rev, ba00, fa90f080), \
9356 X(_rev16, ba40, fa90f090), \
9357 X(_revsh, bac0, fa90f0b0), \
9358 X(_ror, 41c0, fa60f000), \
9359 X(_rors, 41c0, fa70f000), \
9360 X(_sbc, 4180, eb600000), \
9361 X(_sbcs, 4180, eb700000), \
9362 X(_stmia, c000, e8800000), \
9363 X(_str, 6000, f8400000), \
9364 X(_strb, 7000, f8000000), \
9365 X(_strh, 8000, f8200000), \
9366 X(_str_sp,9000, f84d0000), \
9367 X(_sub, 1e00, eba00000), \
9368 X(_subs, 1e00, ebb00000), \
9369 X(_subi, 8000, f1a00000), \
9370 X(_subis, 8000, f1b00000), \
9371 X(_sxtb, b240, fa4ff080), \
9372 X(_sxth, b200, fa0ff080), \
9373 X(_tst, 4200, ea100f00), \
9374 X(_uxtb, b2c0, fa5ff080), \
9375 X(_uxth, b280, fa1ff080), \
9376 X(_nop, bf00, f3af8000), \
9377 X(_yield, bf10, f3af8001), \
9378 X(_wfe, bf20, f3af8002), \
9379 X(_wfi, bf30, f3af8003), \
9380 X(_sev, bf40, f3af8004),
9382 /* To catch errors in encoding functions, the codes are all offset by
9383 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9384 as 16-bit instructions. */
9385 #define X(a,b,c) T_MNEM##a
9386 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9389 #define X(a,b,c) 0x##b
9390 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9391 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9394 #define X(a,b,c) 0x##c
9395 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9396 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9397 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9401 /* Thumb instruction encoders, in alphabetical order. */
9406 do_t_add_sub_w (void)
9410 Rd
= inst
.operands
[0].reg
;
9411 Rn
= inst
.operands
[1].reg
;
9413 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9414 is the SP-{plus,minus}-immediate form of the instruction. */
9416 constraint (Rd
== REG_PC
, BAD_PC
);
9418 reject_bad_reg (Rd
);
9420 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9421 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9424 /* Parse an add or subtract instruction. We get here with inst.instruction
9425 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9432 Rd
= inst
.operands
[0].reg
;
9433 Rs
= (inst
.operands
[1].present
9434 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9435 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9438 set_it_insn_type_last ();
9446 flags
= (inst
.instruction
== T_MNEM_adds
9447 || inst
.instruction
== T_MNEM_subs
);
9449 narrow
= !in_it_block ();
9451 narrow
= in_it_block ();
9452 if (!inst
.operands
[2].isreg
)
9456 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9458 add
= (inst
.instruction
== T_MNEM_add
9459 || inst
.instruction
== T_MNEM_adds
);
9461 if (inst
.size_req
!= 4)
9463 /* Attempt to use a narrow opcode, with relaxation if
9465 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9466 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9467 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9468 opcode
= T_MNEM_add_sp
;
9469 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9470 opcode
= T_MNEM_add_pc
;
9471 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9474 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9476 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9480 inst
.instruction
= THUMB_OP16(opcode
);
9481 inst
.instruction
|= (Rd
<< 4) | Rs
;
9482 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9483 if (inst
.size_req
!= 2)
9484 inst
.relax
= opcode
;
9487 constraint (inst
.size_req
== 2, BAD_HIREG
);
9489 if (inst
.size_req
== 4
9490 || (inst
.size_req
!= 2 && !opcode
))
9494 constraint (add
, BAD_PC
);
9495 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9496 _("only SUBS PC, LR, #const allowed"));
9497 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9498 _("expression too complex"));
9499 constraint (inst
.reloc
.exp
.X_add_number
< 0
9500 || inst
.reloc
.exp
.X_add_number
> 0xff,
9501 _("immediate value out of range"));
9502 inst
.instruction
= T2_SUBS_PC_LR
9503 | inst
.reloc
.exp
.X_add_number
;
9504 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9507 else if (Rs
== REG_PC
)
9509 /* Always use addw/subw. */
9510 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9511 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9515 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9516 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9519 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9521 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9523 inst
.instruction
|= Rd
<< 8;
9524 inst
.instruction
|= Rs
<< 16;
9529 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9530 unsigned int shift
= inst
.operands
[2].shift_kind
;
9532 Rn
= inst
.operands
[2].reg
;
9533 /* See if we can do this with a 16-bit instruction. */
9534 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9536 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9541 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9542 || inst
.instruction
== T_MNEM_add
)
9545 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9549 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9551 /* Thumb-1 cores (except v6-M) require at least one high
9552 register in a narrow non flag setting add. */
9553 if (Rd
> 7 || Rn
> 7
9554 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9555 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9562 inst
.instruction
= T_OPCODE_ADD_HI
;
9563 inst
.instruction
|= (Rd
& 8) << 4;
9564 inst
.instruction
|= (Rd
& 7);
9565 inst
.instruction
|= Rn
<< 3;
9571 constraint (Rd
== REG_PC
, BAD_PC
);
9572 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9573 constraint (Rs
== REG_PC
, BAD_PC
);
9574 reject_bad_reg (Rn
);
9576 /* If we get here, it can't be done in 16 bits. */
9577 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9578 _("shift must be constant"));
9579 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9580 inst
.instruction
|= Rd
<< 8;
9581 inst
.instruction
|= Rs
<< 16;
9582 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9583 _("shift value over 3 not allowed in thumb mode"));
9584 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9585 _("only LSL shift allowed in thumb mode"));
9586 encode_thumb32_shifted_operand (2);
9591 constraint (inst
.instruction
== T_MNEM_adds
9592 || inst
.instruction
== T_MNEM_subs
,
9595 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9597 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9598 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9601 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9603 inst
.instruction
|= (Rd
<< 4) | Rs
;
9604 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9608 Rn
= inst
.operands
[2].reg
;
9609 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9611 /* We now have Rd, Rs, and Rn set to registers. */
9612 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9614 /* Can't do this for SUB. */
9615 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9616 inst
.instruction
= T_OPCODE_ADD_HI
;
9617 inst
.instruction
|= (Rd
& 8) << 4;
9618 inst
.instruction
|= (Rd
& 7);
9620 inst
.instruction
|= Rn
<< 3;
9622 inst
.instruction
|= Rs
<< 3;
9624 constraint (1, _("dest must overlap one source register"));
9628 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9629 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9630 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9640 Rd
= inst
.operands
[0].reg
;
9641 reject_bad_reg (Rd
);
9643 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9645 /* Defer to section relaxation. */
9646 inst
.relax
= inst
.instruction
;
9647 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9648 inst
.instruction
|= Rd
<< 4;
9650 else if (unified_syntax
&& inst
.size_req
!= 2)
9652 /* Generate a 32-bit opcode. */
9653 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9654 inst
.instruction
|= Rd
<< 8;
9655 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9656 inst
.reloc
.pc_rel
= 1;
9660 /* Generate a 16-bit opcode. */
9661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9662 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9663 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9664 inst
.reloc
.pc_rel
= 1;
9666 inst
.instruction
|= Rd
<< 4;
9670 /* Arithmetic instructions for which there is just one 16-bit
9671 instruction encoding, and it allows only two low registers.
9672 For maximal compatibility with ARM syntax, we allow three register
9673 operands even when Thumb-32 instructions are not available, as long
9674 as the first two are identical. For instance, both "sbc r0,r1" and
9675 "sbc r0,r0,r1" are allowed. */
9681 Rd
= inst
.operands
[0].reg
;
9682 Rs
= (inst
.operands
[1].present
9683 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9684 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9685 Rn
= inst
.operands
[2].reg
;
9687 reject_bad_reg (Rd
);
9688 reject_bad_reg (Rs
);
9689 if (inst
.operands
[2].isreg
)
9690 reject_bad_reg (Rn
);
9694 if (!inst
.operands
[2].isreg
)
9696 /* For an immediate, we always generate a 32-bit opcode;
9697 section relaxation will shrink it later if possible. */
9698 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9699 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9700 inst
.instruction
|= Rd
<< 8;
9701 inst
.instruction
|= Rs
<< 16;
9702 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9708 /* See if we can do this with a 16-bit instruction. */
9709 if (THUMB_SETS_FLAGS (inst
.instruction
))
9710 narrow
= !in_it_block ();
9712 narrow
= in_it_block ();
9714 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9716 if (inst
.operands
[2].shifted
)
9718 if (inst
.size_req
== 4)
9724 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9725 inst
.instruction
|= Rd
;
9726 inst
.instruction
|= Rn
<< 3;
9730 /* If we get here, it can't be done in 16 bits. */
9731 constraint (inst
.operands
[2].shifted
9732 && inst
.operands
[2].immisreg
,
9733 _("shift must be constant"));
9734 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9735 inst
.instruction
|= Rd
<< 8;
9736 inst
.instruction
|= Rs
<< 16;
9737 encode_thumb32_shifted_operand (2);
9742 /* On its face this is a lie - the instruction does set the
9743 flags. However, the only supported mnemonic in this mode
9745 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9747 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9748 _("unshifted register required"));
9749 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9750 constraint (Rd
!= Rs
,
9751 _("dest and source1 must be the same register"));
9753 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9754 inst
.instruction
|= Rd
;
9755 inst
.instruction
|= Rn
<< 3;
9759 /* Similarly, but for instructions where the arithmetic operation is
9760 commutative, so we can allow either of them to be different from
9761 the destination operand in a 16-bit instruction. For instance, all
9762 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9769 Rd
= inst
.operands
[0].reg
;
9770 Rs
= (inst
.operands
[1].present
9771 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9772 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9773 Rn
= inst
.operands
[2].reg
;
9775 reject_bad_reg (Rd
);
9776 reject_bad_reg (Rs
);
9777 if (inst
.operands
[2].isreg
)
9778 reject_bad_reg (Rn
);
9782 if (!inst
.operands
[2].isreg
)
9784 /* For an immediate, we always generate a 32-bit opcode;
9785 section relaxation will shrink it later if possible. */
9786 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9787 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9788 inst
.instruction
|= Rd
<< 8;
9789 inst
.instruction
|= Rs
<< 16;
9790 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9796 /* See if we can do this with a 16-bit instruction. */
9797 if (THUMB_SETS_FLAGS (inst
.instruction
))
9798 narrow
= !in_it_block ();
9800 narrow
= in_it_block ();
9802 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9804 if (inst
.operands
[2].shifted
)
9806 if (inst
.size_req
== 4)
9813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9814 inst
.instruction
|= Rd
;
9815 inst
.instruction
|= Rn
<< 3;
9820 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9821 inst
.instruction
|= Rd
;
9822 inst
.instruction
|= Rs
<< 3;
9827 /* If we get here, it can't be done in 16 bits. */
9828 constraint (inst
.operands
[2].shifted
9829 && inst
.operands
[2].immisreg
,
9830 _("shift must be constant"));
9831 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9832 inst
.instruction
|= Rd
<< 8;
9833 inst
.instruction
|= Rs
<< 16;
9834 encode_thumb32_shifted_operand (2);
9839 /* On its face this is a lie - the instruction does set the
9840 flags. However, the only supported mnemonic in this mode
9842 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9844 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9845 _("unshifted register required"));
9846 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9848 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9849 inst
.instruction
|= Rd
;
9852 inst
.instruction
|= Rn
<< 3;
9854 inst
.instruction
|= Rs
<< 3;
9856 constraint (1, _("dest must overlap one source register"));
9863 if (inst
.operands
[0].present
)
9865 constraint ((inst
.instruction
& 0xf0) != 0x40
9866 && inst
.operands
[0].imm
> 0xf
9867 && inst
.operands
[0].imm
< 0x0,
9868 _("bad barrier type"));
9869 inst
.instruction
|= inst
.operands
[0].imm
;
9872 inst
.instruction
|= 0xf;
9879 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9880 constraint (msb
> 32, _("bit-field extends past end of register"));
9881 /* The instruction encoding stores the LSB and MSB,
9882 not the LSB and width. */
9883 Rd
= inst
.operands
[0].reg
;
9884 reject_bad_reg (Rd
);
9885 inst
.instruction
|= Rd
<< 8;
9886 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9887 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9888 inst
.instruction
|= msb
- 1;
9897 Rd
= inst
.operands
[0].reg
;
9898 reject_bad_reg (Rd
);
9900 /* #0 in second position is alternative syntax for bfc, which is
9901 the same instruction but with REG_PC in the Rm field. */
9902 if (!inst
.operands
[1].isreg
)
9906 Rn
= inst
.operands
[1].reg
;
9907 reject_bad_reg (Rn
);
9910 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9911 constraint (msb
> 32, _("bit-field extends past end of register"));
9912 /* The instruction encoding stores the LSB and MSB,
9913 not the LSB and width. */
9914 inst
.instruction
|= Rd
<< 8;
9915 inst
.instruction
|= Rn
<< 16;
9916 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9917 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9918 inst
.instruction
|= msb
- 1;
9926 Rd
= inst
.operands
[0].reg
;
9927 Rn
= inst
.operands
[1].reg
;
9929 reject_bad_reg (Rd
);
9930 reject_bad_reg (Rn
);
9932 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9933 _("bit-field extends past end of register"));
9934 inst
.instruction
|= Rd
<< 8;
9935 inst
.instruction
|= Rn
<< 16;
9936 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9937 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9938 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9941 /* ARM V5 Thumb BLX (argument parse)
9942 BLX <target_addr> which is BLX(1)
9943 BLX <Rm> which is BLX(2)
9944 Unfortunately, there are two different opcodes for this mnemonic.
9945 So, the insns[].value is not used, and the code here zaps values
9946 into inst.instruction.
9948 ??? How to take advantage of the additional two bits of displacement
9949 available in Thumb32 mode? Need new relocation? */
9954 set_it_insn_type_last ();
9956 if (inst
.operands
[0].isreg
)
9958 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9959 /* We have a register, so this is BLX(2). */
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9964 /* No register. This must be BLX(1). */
9965 inst
.instruction
= 0xf000e800;
9966 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9978 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9982 /* Conditional branches inside IT blocks are encoded as unconditional
9989 if (cond
!= COND_ALWAYS
)
9990 opcode
= T_MNEM_bcond
;
9992 opcode
= inst
.instruction
;
9995 && (inst
.size_req
== 4
9996 || (inst
.size_req
!= 2
9997 && (inst
.operands
[0].hasreloc
9998 || inst
.reloc
.exp
.X_op
== O_constant
))))
10000 inst
.instruction
= THUMB_OP32(opcode
);
10001 if (cond
== COND_ALWAYS
)
10002 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10005 gas_assert (cond
!= 0xF);
10006 inst
.instruction
|= cond
<< 22;
10007 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10012 inst
.instruction
= THUMB_OP16(opcode
);
10013 if (cond
== COND_ALWAYS
)
10014 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10017 inst
.instruction
|= cond
<< 8;
10018 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10020 /* Allow section relaxation. */
10021 if (unified_syntax
&& inst
.size_req
!= 2)
10022 inst
.relax
= opcode
;
10024 inst
.reloc
.type
= reloc
;
10025 inst
.reloc
.pc_rel
= 1;
10031 constraint (inst
.cond
!= COND_ALWAYS
,
10032 _("instruction is always unconditional"));
10033 if (inst
.operands
[0].present
)
10035 constraint (inst
.operands
[0].imm
> 255,
10036 _("immediate value out of range"));
10037 inst
.instruction
|= inst
.operands
[0].imm
;
10038 set_it_insn_type (NEUTRAL_IT_INSN
);
10043 do_t_branch23 (void)
10045 set_it_insn_type_last ();
10046 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10048 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10049 this file. We used to simply ignore the PLT reloc type here --
10050 the branch encoding is now needed to deal with TLSCALL relocs.
10051 So if we see a PLT reloc now, put it back to how it used to be to
10052 keep the preexisting behaviour. */
10053 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10054 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10056 #if defined(OBJ_COFF)
10057 /* If the destination of the branch is a defined symbol which does not have
10058 the THUMB_FUNC attribute, then we must be calling a function which has
10059 the (interfacearm) attribute. We look for the Thumb entry point to that
10060 function and change the branch to refer to that function instead. */
10061 if ( inst
.reloc
.exp
.X_op
== O_symbol
10062 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10063 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10064 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10065 inst
.reloc
.exp
.X_add_symbol
=
10066 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10073 set_it_insn_type_last ();
10074 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10075 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10076 should cause the alignment to be checked once it is known. This is
10077 because BX PC only works if the instruction is word aligned. */
10085 set_it_insn_type_last ();
10086 Rm
= inst
.operands
[0].reg
;
10087 reject_bad_reg (Rm
);
10088 inst
.instruction
|= Rm
<< 16;
10097 Rd
= inst
.operands
[0].reg
;
10098 Rm
= inst
.operands
[1].reg
;
10100 reject_bad_reg (Rd
);
10101 reject_bad_reg (Rm
);
10103 inst
.instruction
|= Rd
<< 8;
10104 inst
.instruction
|= Rm
<< 16;
10105 inst
.instruction
|= Rm
;
10111 set_it_insn_type (OUTSIDE_IT_INSN
);
10112 inst
.instruction
|= inst
.operands
[0].imm
;
10118 set_it_insn_type (OUTSIDE_IT_INSN
);
10120 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10121 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10123 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10124 inst
.instruction
= 0xf3af8000;
10125 inst
.instruction
|= imod
<< 9;
10126 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10127 if (inst
.operands
[1].present
)
10128 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10133 && (inst
.operands
[0].imm
& 4),
10134 _("selected processor does not support 'A' form "
10135 "of this instruction"));
10136 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10137 _("Thumb does not support the 2-argument "
10138 "form of this instruction"));
10139 inst
.instruction
|= inst
.operands
[0].imm
;
10143 /* THUMB CPY instruction (argument parse). */
10148 if (inst
.size_req
== 4)
10150 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10151 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10152 inst
.instruction
|= inst
.operands
[1].reg
;
10156 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10157 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10158 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10165 set_it_insn_type (OUTSIDE_IT_INSN
);
10166 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10167 inst
.instruction
|= inst
.operands
[0].reg
;
10168 inst
.reloc
.pc_rel
= 1;
10169 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10175 inst
.instruction
|= inst
.operands
[0].imm
;
10181 unsigned Rd
, Rn
, Rm
;
10183 Rd
= inst
.operands
[0].reg
;
10184 Rn
= (inst
.operands
[1].present
10185 ? inst
.operands
[1].reg
: Rd
);
10186 Rm
= inst
.operands
[2].reg
;
10188 reject_bad_reg (Rd
);
10189 reject_bad_reg (Rn
);
10190 reject_bad_reg (Rm
);
10192 inst
.instruction
|= Rd
<< 8;
10193 inst
.instruction
|= Rn
<< 16;
10194 inst
.instruction
|= Rm
;
10200 if (unified_syntax
&& inst
.size_req
== 4)
10201 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10203 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10209 unsigned int cond
= inst
.operands
[0].imm
;
10211 set_it_insn_type (IT_INSN
);
10212 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10215 /* If the condition is a negative condition, invert the mask. */
10216 if ((cond
& 0x1) == 0x0)
10218 unsigned int mask
= inst
.instruction
& 0x000f;
10220 if ((mask
& 0x7) == 0)
10221 /* no conversion needed */;
10222 else if ((mask
& 0x3) == 0)
10224 else if ((mask
& 0x1) == 0)
10229 inst
.instruction
&= 0xfff0;
10230 inst
.instruction
|= mask
;
10233 inst
.instruction
|= cond
<< 4;
10236 /* Helper function used for both push/pop and ldm/stm. */
10238 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10242 load
= (inst
.instruction
& (1 << 20)) != 0;
10244 if (mask
& (1 << 13))
10245 inst
.error
= _("SP not allowed in register list");
10247 if ((mask
& (1 << base
)) != 0
10249 inst
.error
= _("having the base register in the register list when "
10250 "using write back is UNPREDICTABLE");
10254 if (mask
& (1 << 15))
10256 if (mask
& (1 << 14))
10257 inst
.error
= _("LR and PC should not both be in register list");
10259 set_it_insn_type_last ();
10264 if (mask
& (1 << 15))
10265 inst
.error
= _("PC not allowed in register list");
10268 if ((mask
& (mask
- 1)) == 0)
10270 /* Single register transfers implemented as str/ldr. */
10273 if (inst
.instruction
& (1 << 23))
10274 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10276 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10280 if (inst
.instruction
& (1 << 23))
10281 inst
.instruction
= 0x00800000; /* ia -> [base] */
10283 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10286 inst
.instruction
|= 0xf8400000;
10288 inst
.instruction
|= 0x00100000;
10290 mask
= ffs (mask
) - 1;
10293 else if (writeback
)
10294 inst
.instruction
|= WRITE_BACK
;
10296 inst
.instruction
|= mask
;
10297 inst
.instruction
|= base
<< 16;
10303 /* This really doesn't seem worth it. */
10304 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10305 _("expression too complex"));
10306 constraint (inst
.operands
[1].writeback
,
10307 _("Thumb load/store multiple does not support {reglist}^"));
10309 if (unified_syntax
)
10311 bfd_boolean narrow
;
10315 /* See if we can use a 16-bit instruction. */
10316 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10317 && inst
.size_req
!= 4
10318 && !(inst
.operands
[1].imm
& ~0xff))
10320 mask
= 1 << inst
.operands
[0].reg
;
10322 if (inst
.operands
[0].reg
<= 7)
10324 if (inst
.instruction
== T_MNEM_stmia
10325 ? inst
.operands
[0].writeback
10326 : (inst
.operands
[0].writeback
10327 == !(inst
.operands
[1].imm
& mask
)))
10329 if (inst
.instruction
== T_MNEM_stmia
10330 && (inst
.operands
[1].imm
& mask
)
10331 && (inst
.operands
[1].imm
& (mask
- 1)))
10332 as_warn (_("value stored for r%d is UNKNOWN"),
10333 inst
.operands
[0].reg
);
10335 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10336 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10337 inst
.instruction
|= inst
.operands
[1].imm
;
10340 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10342 /* This means 1 register in reg list one of 3 situations:
10343 1. Instruction is stmia, but without writeback.
10344 2. lmdia without writeback, but with Rn not in
10346 3. ldmia with writeback, but with Rn in reglist.
10347 Case 3 is UNPREDICTABLE behaviour, so we handle
10348 case 1 and 2 which can be converted into a 16-bit
10349 str or ldr. The SP cases are handled below. */
10350 unsigned long opcode
;
10351 /* First, record an error for Case 3. */
10352 if (inst
.operands
[1].imm
& mask
10353 && inst
.operands
[0].writeback
)
10355 _("having the base register in the register list when "
10356 "using write back is UNPREDICTABLE");
10358 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10360 inst
.instruction
= THUMB_OP16 (opcode
);
10361 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10362 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10366 else if (inst
.operands
[0] .reg
== REG_SP
)
10368 if (inst
.operands
[0].writeback
)
10371 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10372 ? T_MNEM_push
: T_MNEM_pop
);
10373 inst
.instruction
|= inst
.operands
[1].imm
;
10376 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10379 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10380 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10381 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10389 if (inst
.instruction
< 0xffff)
10390 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10392 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10393 inst
.operands
[0].writeback
);
10398 constraint (inst
.operands
[0].reg
> 7
10399 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10400 constraint (inst
.instruction
!= T_MNEM_ldmia
10401 && inst
.instruction
!= T_MNEM_stmia
,
10402 _("Thumb-2 instruction only valid in unified syntax"));
10403 if (inst
.instruction
== T_MNEM_stmia
)
10405 if (!inst
.operands
[0].writeback
)
10406 as_warn (_("this instruction will write back the base register"));
10407 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10408 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10409 as_warn (_("value stored for r%d is UNKNOWN"),
10410 inst
.operands
[0].reg
);
10414 if (!inst
.operands
[0].writeback
10415 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10416 as_warn (_("this instruction will write back the base register"));
10417 else if (inst
.operands
[0].writeback
10418 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10419 as_warn (_("this instruction will not write back the base register"));
10422 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10423 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10424 inst
.instruction
|= inst
.operands
[1].imm
;
10431 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10432 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10433 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10434 || inst
.operands
[1].negative
,
10437 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10440 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10441 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10447 if (!inst
.operands
[1].present
)
10449 constraint (inst
.operands
[0].reg
== REG_LR
,
10450 _("r14 not allowed as first register "
10451 "when second register is omitted"));
10452 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10454 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10458 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10459 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10465 unsigned long opcode
;
10468 if (inst
.operands
[0].isreg
10469 && !inst
.operands
[0].preind
10470 && inst
.operands
[0].reg
== REG_PC
)
10471 set_it_insn_type_last ();
10473 opcode
= inst
.instruction
;
10474 if (unified_syntax
)
10476 if (!inst
.operands
[1].isreg
)
10478 if (opcode
<= 0xffff)
10479 inst
.instruction
= THUMB_OP32 (opcode
);
10480 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10483 if (inst
.operands
[1].isreg
10484 && !inst
.operands
[1].writeback
10485 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10486 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10487 && opcode
<= 0xffff
10488 && inst
.size_req
!= 4)
10490 /* Insn may have a 16-bit form. */
10491 Rn
= inst
.operands
[1].reg
;
10492 if (inst
.operands
[1].immisreg
)
10494 inst
.instruction
= THUMB_OP16 (opcode
);
10496 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10498 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10499 reject_bad_reg (inst
.operands
[1].imm
);
10501 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10502 && opcode
!= T_MNEM_ldrsb
)
10503 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10504 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10511 if (inst
.reloc
.pc_rel
)
10512 opcode
= T_MNEM_ldr_pc2
;
10514 opcode
= T_MNEM_ldr_pc
;
10518 if (opcode
== T_MNEM_ldr
)
10519 opcode
= T_MNEM_ldr_sp
;
10521 opcode
= T_MNEM_str_sp
;
10523 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10527 inst
.instruction
= inst
.operands
[0].reg
;
10528 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10530 inst
.instruction
|= THUMB_OP16 (opcode
);
10531 if (inst
.size_req
== 2)
10532 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10534 inst
.relax
= opcode
;
10538 /* Definitely a 32-bit variant. */
10540 /* Warning for Erratum 752419. */
10541 if (opcode
== T_MNEM_ldr
10542 && inst
.operands
[0].reg
== REG_SP
10543 && inst
.operands
[1].writeback
== 1
10544 && !inst
.operands
[1].immisreg
)
10546 if (no_cpu_selected ()
10547 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10548 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10549 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10550 as_warn (_("This instruction may be unpredictable "
10551 "if executed on M-profile cores "
10552 "with interrupts enabled."));
10555 /* Do some validations regarding addressing modes. */
10556 if (inst
.operands
[1].immisreg
)
10557 reject_bad_reg (inst
.operands
[1].imm
);
10559 constraint (inst
.operands
[1].writeback
== 1
10560 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10563 inst
.instruction
= THUMB_OP32 (opcode
);
10564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10565 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10566 check_ldr_r15_aligned ();
10570 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10572 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10574 /* Only [Rn,Rm] is acceptable. */
10575 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10576 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10577 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10578 || inst
.operands
[1].negative
,
10579 _("Thumb does not support this addressing mode"));
10580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10585 if (!inst
.operands
[1].isreg
)
10586 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10589 constraint (!inst
.operands
[1].preind
10590 || inst
.operands
[1].shifted
10591 || inst
.operands
[1].writeback
,
10592 _("Thumb does not support this addressing mode"));
10593 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10595 constraint (inst
.instruction
& 0x0600,
10596 _("byte or halfword not valid for base register"));
10597 constraint (inst
.operands
[1].reg
== REG_PC
10598 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10599 _("r15 based store not allowed"));
10600 constraint (inst
.operands
[1].immisreg
,
10601 _("invalid base register for register offset"));
10603 if (inst
.operands
[1].reg
== REG_PC
)
10604 inst
.instruction
= T_OPCODE_LDR_PC
;
10605 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10606 inst
.instruction
= T_OPCODE_LDR_SP
;
10608 inst
.instruction
= T_OPCODE_STR_SP
;
10610 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10611 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10615 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10616 if (!inst
.operands
[1].immisreg
)
10618 /* Immediate offset. */
10619 inst
.instruction
|= inst
.operands
[0].reg
;
10620 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10621 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10625 /* Register offset. */
10626 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10627 constraint (inst
.operands
[1].negative
,
10628 _("Thumb does not support this addressing mode"));
10631 switch (inst
.instruction
)
10633 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10634 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10635 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10636 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10637 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10638 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10639 case 0x5600 /* ldrsb */:
10640 case 0x5e00 /* ldrsh */: break;
10644 inst
.instruction
|= inst
.operands
[0].reg
;
10645 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10646 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10652 if (!inst
.operands
[1].present
)
10654 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10655 constraint (inst
.operands
[0].reg
== REG_LR
,
10656 _("r14 not allowed here"));
10658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10659 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10660 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10667 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10673 unsigned Rd
, Rn
, Rm
, Ra
;
10675 Rd
= inst
.operands
[0].reg
;
10676 Rn
= inst
.operands
[1].reg
;
10677 Rm
= inst
.operands
[2].reg
;
10678 Ra
= inst
.operands
[3].reg
;
10680 reject_bad_reg (Rd
);
10681 reject_bad_reg (Rn
);
10682 reject_bad_reg (Rm
);
10683 reject_bad_reg (Ra
);
10685 inst
.instruction
|= Rd
<< 8;
10686 inst
.instruction
|= Rn
<< 16;
10687 inst
.instruction
|= Rm
;
10688 inst
.instruction
|= Ra
<< 12;
10694 unsigned RdLo
, RdHi
, Rn
, Rm
;
10696 RdLo
= inst
.operands
[0].reg
;
10697 RdHi
= inst
.operands
[1].reg
;
10698 Rn
= inst
.operands
[2].reg
;
10699 Rm
= inst
.operands
[3].reg
;
10701 reject_bad_reg (RdLo
);
10702 reject_bad_reg (RdHi
);
10703 reject_bad_reg (Rn
);
10704 reject_bad_reg (Rm
);
10706 inst
.instruction
|= RdLo
<< 12;
10707 inst
.instruction
|= RdHi
<< 8;
10708 inst
.instruction
|= Rn
<< 16;
10709 inst
.instruction
|= Rm
;
10713 do_t_mov_cmp (void)
10717 Rn
= inst
.operands
[0].reg
;
10718 Rm
= inst
.operands
[1].reg
;
10721 set_it_insn_type_last ();
10723 if (unified_syntax
)
10725 int r0off
= (inst
.instruction
== T_MNEM_mov
10726 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10727 unsigned long opcode
;
10728 bfd_boolean narrow
;
10729 bfd_boolean low_regs
;
10731 low_regs
= (Rn
<= 7 && Rm
<= 7);
10732 opcode
= inst
.instruction
;
10733 if (in_it_block ())
10734 narrow
= opcode
!= T_MNEM_movs
;
10736 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10737 if (inst
.size_req
== 4
10738 || inst
.operands
[1].shifted
)
10741 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10742 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10743 && !inst
.operands
[1].shifted
10747 inst
.instruction
= T2_SUBS_PC_LR
;
10751 if (opcode
== T_MNEM_cmp
)
10753 constraint (Rn
== REG_PC
, BAD_PC
);
10756 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10758 warn_deprecated_sp (Rm
);
10759 /* R15 was documented as a valid choice for Rm in ARMv6,
10760 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10761 tools reject R15, so we do too. */
10762 constraint (Rm
== REG_PC
, BAD_PC
);
10765 reject_bad_reg (Rm
);
10767 else if (opcode
== T_MNEM_mov
10768 || opcode
== T_MNEM_movs
)
10770 if (inst
.operands
[1].isreg
)
10772 if (opcode
== T_MNEM_movs
)
10774 reject_bad_reg (Rn
);
10775 reject_bad_reg (Rm
);
10779 /* This is mov.n. */
10780 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10781 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10783 as_warn (_("Use of r%u as a source register is "
10784 "deprecated when r%u is the destination "
10785 "register."), Rm
, Rn
);
10790 /* This is mov.w. */
10791 constraint (Rn
== REG_PC
, BAD_PC
);
10792 constraint (Rm
== REG_PC
, BAD_PC
);
10793 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10797 reject_bad_reg (Rn
);
10800 if (!inst
.operands
[1].isreg
)
10802 /* Immediate operand. */
10803 if (!in_it_block () && opcode
== T_MNEM_mov
)
10805 if (low_regs
&& narrow
)
10807 inst
.instruction
= THUMB_OP16 (opcode
);
10808 inst
.instruction
|= Rn
<< 8;
10809 if (inst
.size_req
== 2)
10810 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10812 inst
.relax
= opcode
;
10816 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10817 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10818 inst
.instruction
|= Rn
<< r0off
;
10819 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10822 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10823 && (inst
.instruction
== T_MNEM_mov
10824 || inst
.instruction
== T_MNEM_movs
))
10826 /* Register shifts are encoded as separate shift instructions. */
10827 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10829 if (in_it_block ())
10834 if (inst
.size_req
== 4)
10837 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10843 switch (inst
.operands
[1].shift_kind
)
10846 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10849 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10852 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10855 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10861 inst
.instruction
= opcode
;
10864 inst
.instruction
|= Rn
;
10865 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10870 inst
.instruction
|= CONDS_BIT
;
10872 inst
.instruction
|= Rn
<< 8;
10873 inst
.instruction
|= Rm
<< 16;
10874 inst
.instruction
|= inst
.operands
[1].imm
;
10879 /* Some mov with immediate shift have narrow variants.
10880 Register shifts are handled above. */
10881 if (low_regs
&& inst
.operands
[1].shifted
10882 && (inst
.instruction
== T_MNEM_mov
10883 || inst
.instruction
== T_MNEM_movs
))
10885 if (in_it_block ())
10886 narrow
= (inst
.instruction
== T_MNEM_mov
);
10888 narrow
= (inst
.instruction
== T_MNEM_movs
);
10893 switch (inst
.operands
[1].shift_kind
)
10895 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10896 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10897 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10898 default: narrow
= FALSE
; break;
10904 inst
.instruction
|= Rn
;
10905 inst
.instruction
|= Rm
<< 3;
10906 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10910 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10911 inst
.instruction
|= Rn
<< r0off
;
10912 encode_thumb32_shifted_operand (1);
10916 switch (inst
.instruction
)
10919 /* In v4t or v5t a move of two lowregs produces unpredictable
10920 results. Don't allow this. */
10923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
10924 "MOV Rd, Rs with two low registers is not "
10925 "permitted on this architecture");
10926 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
10930 inst
.instruction
= T_OPCODE_MOV_HR
;
10931 inst
.instruction
|= (Rn
& 0x8) << 4;
10932 inst
.instruction
|= (Rn
& 0x7);
10933 inst
.instruction
|= Rm
<< 3;
10937 /* We know we have low registers at this point.
10938 Generate LSLS Rd, Rs, #0. */
10939 inst
.instruction
= T_OPCODE_LSL_I
;
10940 inst
.instruction
|= Rn
;
10941 inst
.instruction
|= Rm
<< 3;
10947 inst
.instruction
= T_OPCODE_CMP_LR
;
10948 inst
.instruction
|= Rn
;
10949 inst
.instruction
|= Rm
<< 3;
10953 inst
.instruction
= T_OPCODE_CMP_HR
;
10954 inst
.instruction
|= (Rn
& 0x8) << 4;
10955 inst
.instruction
|= (Rn
& 0x7);
10956 inst
.instruction
|= Rm
<< 3;
10963 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10965 /* PR 10443: Do not silently ignore shifted operands. */
10966 constraint (inst
.operands
[1].shifted
,
10967 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10969 if (inst
.operands
[1].isreg
)
10971 if (Rn
< 8 && Rm
< 8)
10973 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10974 since a MOV instruction produces unpredictable results. */
10975 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10976 inst
.instruction
= T_OPCODE_ADD_I3
;
10978 inst
.instruction
= T_OPCODE_CMP_LR
;
10980 inst
.instruction
|= Rn
;
10981 inst
.instruction
|= Rm
<< 3;
10985 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10986 inst
.instruction
= T_OPCODE_MOV_HR
;
10988 inst
.instruction
= T_OPCODE_CMP_HR
;
10994 constraint (Rn
> 7,
10995 _("only lo regs allowed with immediate"));
10996 inst
.instruction
|= Rn
<< 8;
10997 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11008 top
= (inst
.instruction
& 0x00800000) != 0;
11009 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11011 constraint (top
, _(":lower16: not allowed this instruction"));
11012 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11014 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11016 constraint (!top
, _(":upper16: not allowed this instruction"));
11017 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11020 Rd
= inst
.operands
[0].reg
;
11021 reject_bad_reg (Rd
);
11023 inst
.instruction
|= Rd
<< 8;
11024 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11026 imm
= inst
.reloc
.exp
.X_add_number
;
11027 inst
.instruction
|= (imm
& 0xf000) << 4;
11028 inst
.instruction
|= (imm
& 0x0800) << 15;
11029 inst
.instruction
|= (imm
& 0x0700) << 4;
11030 inst
.instruction
|= (imm
& 0x00ff);
11035 do_t_mvn_tst (void)
11039 Rn
= inst
.operands
[0].reg
;
11040 Rm
= inst
.operands
[1].reg
;
11042 if (inst
.instruction
== T_MNEM_cmp
11043 || inst
.instruction
== T_MNEM_cmn
)
11044 constraint (Rn
== REG_PC
, BAD_PC
);
11046 reject_bad_reg (Rn
);
11047 reject_bad_reg (Rm
);
11049 if (unified_syntax
)
11051 int r0off
= (inst
.instruction
== T_MNEM_mvn
11052 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11053 bfd_boolean narrow
;
11055 if (inst
.size_req
== 4
11056 || inst
.instruction
> 0xffff
11057 || inst
.operands
[1].shifted
11058 || Rn
> 7 || Rm
> 7)
11060 else if (inst
.instruction
== T_MNEM_cmn
)
11062 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11063 narrow
= !in_it_block ();
11065 narrow
= in_it_block ();
11067 if (!inst
.operands
[1].isreg
)
11069 /* For an immediate, we always generate a 32-bit opcode;
11070 section relaxation will shrink it later if possible. */
11071 if (inst
.instruction
< 0xffff)
11072 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11073 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11074 inst
.instruction
|= Rn
<< r0off
;
11075 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11079 /* See if we can do this with a 16-bit instruction. */
11082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11083 inst
.instruction
|= Rn
;
11084 inst
.instruction
|= Rm
<< 3;
11088 constraint (inst
.operands
[1].shifted
11089 && inst
.operands
[1].immisreg
,
11090 _("shift must be constant"));
11091 if (inst
.instruction
< 0xffff)
11092 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11093 inst
.instruction
|= Rn
<< r0off
;
11094 encode_thumb32_shifted_operand (1);
11100 constraint (inst
.instruction
> 0xffff
11101 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11102 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11103 _("unshifted register required"));
11104 constraint (Rn
> 7 || Rm
> 7,
11107 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11108 inst
.instruction
|= Rn
;
11109 inst
.instruction
|= Rm
<< 3;
11118 if (do_vfp_nsyn_mrs () == SUCCESS
)
11121 Rd
= inst
.operands
[0].reg
;
11122 reject_bad_reg (Rd
);
11123 inst
.instruction
|= Rd
<< 8;
11125 if (inst
.operands
[1].isreg
)
11127 unsigned br
= inst
.operands
[1].reg
;
11128 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11129 as_bad (_("bad register for mrs"));
11131 inst
.instruction
|= br
& (0xf << 16);
11132 inst
.instruction
|= (br
& 0x300) >> 4;
11133 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11137 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11139 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11140 constraint (flags
!= 0, _("selected processor does not support "
11141 "requested special purpose register"));
11143 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11145 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11146 _("'APSR', 'CPSR' or 'SPSR' expected"));
11148 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11149 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11150 inst
.instruction
|= 0xf0000;
11160 if (do_vfp_nsyn_msr () == SUCCESS
)
11163 constraint (!inst
.operands
[1].isreg
,
11164 _("Thumb encoding does not support an immediate here"));
11166 if (inst
.operands
[0].isreg
)
11167 flags
= (int)(inst
.operands
[0].reg
);
11169 flags
= inst
.operands
[0].imm
;
11171 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11173 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11175 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11176 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11177 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11179 _("selected processor does not support requested special "
11180 "purpose register"));
11183 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11184 "requested special purpose register"));
11186 Rn
= inst
.operands
[1].reg
;
11187 reject_bad_reg (Rn
);
11189 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11190 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11191 inst
.instruction
|= (flags
& 0x300) >> 4;
11192 inst
.instruction
|= (flags
& 0xff);
11193 inst
.instruction
|= Rn
<< 16;
11199 bfd_boolean narrow
;
11200 unsigned Rd
, Rn
, Rm
;
11202 if (!inst
.operands
[2].present
)
11203 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11205 Rd
= inst
.operands
[0].reg
;
11206 Rn
= inst
.operands
[1].reg
;
11207 Rm
= inst
.operands
[2].reg
;
11209 if (unified_syntax
)
11211 if (inst
.size_req
== 4
11217 else if (inst
.instruction
== T_MNEM_muls
)
11218 narrow
= !in_it_block ();
11220 narrow
= in_it_block ();
11224 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11225 constraint (Rn
> 7 || Rm
> 7,
11232 /* 16-bit MULS/Conditional MUL. */
11233 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11234 inst
.instruction
|= Rd
;
11237 inst
.instruction
|= Rm
<< 3;
11239 inst
.instruction
|= Rn
<< 3;
11241 constraint (1, _("dest must overlap one source register"));
11245 constraint (inst
.instruction
!= T_MNEM_mul
,
11246 _("Thumb-2 MUL must not set flags"));
11248 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11249 inst
.instruction
|= Rd
<< 8;
11250 inst
.instruction
|= Rn
<< 16;
11251 inst
.instruction
|= Rm
<< 0;
11253 reject_bad_reg (Rd
);
11254 reject_bad_reg (Rn
);
11255 reject_bad_reg (Rm
);
11262 unsigned RdLo
, RdHi
, Rn
, Rm
;
11264 RdLo
= inst
.operands
[0].reg
;
11265 RdHi
= inst
.operands
[1].reg
;
11266 Rn
= inst
.operands
[2].reg
;
11267 Rm
= inst
.operands
[3].reg
;
11269 reject_bad_reg (RdLo
);
11270 reject_bad_reg (RdHi
);
11271 reject_bad_reg (Rn
);
11272 reject_bad_reg (Rm
);
11274 inst
.instruction
|= RdLo
<< 12;
11275 inst
.instruction
|= RdHi
<< 8;
11276 inst
.instruction
|= Rn
<< 16;
11277 inst
.instruction
|= Rm
;
11280 as_tsktsk (_("rdhi and rdlo must be different"));
11286 set_it_insn_type (NEUTRAL_IT_INSN
);
11288 if (unified_syntax
)
11290 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11292 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11293 inst
.instruction
|= inst
.operands
[0].imm
;
11297 /* PR9722: Check for Thumb2 availability before
11298 generating a thumb2 nop instruction. */
11299 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11301 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11302 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11305 inst
.instruction
= 0x46c0;
11310 constraint (inst
.operands
[0].present
,
11311 _("Thumb does not support NOP with hints"));
11312 inst
.instruction
= 0x46c0;
11319 if (unified_syntax
)
11321 bfd_boolean narrow
;
11323 if (THUMB_SETS_FLAGS (inst
.instruction
))
11324 narrow
= !in_it_block ();
11326 narrow
= in_it_block ();
11327 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11329 if (inst
.size_req
== 4)
11334 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11335 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11340 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11341 inst
.instruction
|= inst
.operands
[0].reg
;
11342 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11347 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11349 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11352 inst
.instruction
|= inst
.operands
[0].reg
;
11353 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11362 Rd
= inst
.operands
[0].reg
;
11363 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11365 reject_bad_reg (Rd
);
11366 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11367 reject_bad_reg (Rn
);
11369 inst
.instruction
|= Rd
<< 8;
11370 inst
.instruction
|= Rn
<< 16;
11372 if (!inst
.operands
[2].isreg
)
11374 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11375 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11381 Rm
= inst
.operands
[2].reg
;
11382 reject_bad_reg (Rm
);
11384 constraint (inst
.operands
[2].shifted
11385 && inst
.operands
[2].immisreg
,
11386 _("shift must be constant"));
11387 encode_thumb32_shifted_operand (2);
11394 unsigned Rd
, Rn
, Rm
;
11396 Rd
= inst
.operands
[0].reg
;
11397 Rn
= inst
.operands
[1].reg
;
11398 Rm
= inst
.operands
[2].reg
;
11400 reject_bad_reg (Rd
);
11401 reject_bad_reg (Rn
);
11402 reject_bad_reg (Rm
);
11404 inst
.instruction
|= Rd
<< 8;
11405 inst
.instruction
|= Rn
<< 16;
11406 inst
.instruction
|= Rm
;
11407 if (inst
.operands
[3].present
)
11409 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11410 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11411 _("expression too complex"));
11412 inst
.instruction
|= (val
& 0x1c) << 10;
11413 inst
.instruction
|= (val
& 0x03) << 6;
11420 if (!inst
.operands
[3].present
)
11424 inst
.instruction
&= ~0x00000020;
11426 /* PR 10168. Swap the Rm and Rn registers. */
11427 Rtmp
= inst
.operands
[1].reg
;
11428 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11429 inst
.operands
[2].reg
= Rtmp
;
11437 if (inst
.operands
[0].immisreg
)
11438 reject_bad_reg (inst
.operands
[0].imm
);
11440 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11444 do_t_push_pop (void)
11448 constraint (inst
.operands
[0].writeback
,
11449 _("push/pop do not support {reglist}^"));
11450 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11451 _("expression too complex"));
11453 mask
= inst
.operands
[0].imm
;
11454 if ((mask
& ~0xff) == 0)
11455 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11456 else if ((inst
.instruction
== T_MNEM_push
11457 && (mask
& ~0xff) == 1 << REG_LR
)
11458 || (inst
.instruction
== T_MNEM_pop
11459 && (mask
& ~0xff) == 1 << REG_PC
))
11461 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11462 inst
.instruction
|= THUMB_PP_PC_LR
;
11463 inst
.instruction
|= mask
& 0xff;
11465 else if (unified_syntax
)
11467 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11468 encode_thumb2_ldmstm (13, mask
, TRUE
);
11472 inst
.error
= _("invalid register list to push/pop instruction");
11482 Rd
= inst
.operands
[0].reg
;
11483 Rm
= inst
.operands
[1].reg
;
11485 reject_bad_reg (Rd
);
11486 reject_bad_reg (Rm
);
11488 inst
.instruction
|= Rd
<< 8;
11489 inst
.instruction
|= Rm
<< 16;
11490 inst
.instruction
|= Rm
;
11498 Rd
= inst
.operands
[0].reg
;
11499 Rm
= inst
.operands
[1].reg
;
11501 reject_bad_reg (Rd
);
11502 reject_bad_reg (Rm
);
11504 if (Rd
<= 7 && Rm
<= 7
11505 && inst
.size_req
!= 4)
11507 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11508 inst
.instruction
|= Rd
;
11509 inst
.instruction
|= Rm
<< 3;
11511 else if (unified_syntax
)
11513 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11514 inst
.instruction
|= Rd
<< 8;
11515 inst
.instruction
|= Rm
<< 16;
11516 inst
.instruction
|= Rm
;
11519 inst
.error
= BAD_HIREG
;
11527 Rd
= inst
.operands
[0].reg
;
11528 Rm
= inst
.operands
[1].reg
;
11530 reject_bad_reg (Rd
);
11531 reject_bad_reg (Rm
);
11533 inst
.instruction
|= Rd
<< 8;
11534 inst
.instruction
|= Rm
;
11542 Rd
= inst
.operands
[0].reg
;
11543 Rs
= (inst
.operands
[1].present
11544 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11545 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11547 reject_bad_reg (Rd
);
11548 reject_bad_reg (Rs
);
11549 if (inst
.operands
[2].isreg
)
11550 reject_bad_reg (inst
.operands
[2].reg
);
11552 inst
.instruction
|= Rd
<< 8;
11553 inst
.instruction
|= Rs
<< 16;
11554 if (!inst
.operands
[2].isreg
)
11556 bfd_boolean narrow
;
11558 if ((inst
.instruction
& 0x00100000) != 0)
11559 narrow
= !in_it_block ();
11561 narrow
= in_it_block ();
11563 if (Rd
> 7 || Rs
> 7)
11566 if (inst
.size_req
== 4 || !unified_syntax
)
11569 if (inst
.reloc
.exp
.X_op
!= O_constant
11570 || inst
.reloc
.exp
.X_add_number
!= 0)
11573 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11574 relaxation, but it doesn't seem worth the hassle. */
11577 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11578 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11579 inst
.instruction
|= Rs
<< 3;
11580 inst
.instruction
|= Rd
;
11584 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11585 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11589 encode_thumb32_shifted_operand (2);
11595 set_it_insn_type (OUTSIDE_IT_INSN
);
11596 if (inst
.operands
[0].imm
)
11597 inst
.instruction
|= 0x8;
11603 if (!inst
.operands
[1].present
)
11604 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11606 if (unified_syntax
)
11608 bfd_boolean narrow
;
11611 switch (inst
.instruction
)
11614 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11616 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11618 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11620 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11624 if (THUMB_SETS_FLAGS (inst
.instruction
))
11625 narrow
= !in_it_block ();
11627 narrow
= in_it_block ();
11628 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11630 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11632 if (inst
.operands
[2].isreg
11633 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11634 || inst
.operands
[2].reg
> 7))
11636 if (inst
.size_req
== 4)
11639 reject_bad_reg (inst
.operands
[0].reg
);
11640 reject_bad_reg (inst
.operands
[1].reg
);
11644 if (inst
.operands
[2].isreg
)
11646 reject_bad_reg (inst
.operands
[2].reg
);
11647 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11648 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11649 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11650 inst
.instruction
|= inst
.operands
[2].reg
;
11652 /* PR 12854: Error on extraneous shifts. */
11653 constraint (inst
.operands
[2].shifted
,
11654 _("extraneous shift as part of operand to shift insn"));
11658 inst
.operands
[1].shifted
= 1;
11659 inst
.operands
[1].shift_kind
= shift_kind
;
11660 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11661 ? T_MNEM_movs
: T_MNEM_mov
);
11662 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11663 encode_thumb32_shifted_operand (1);
11664 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11665 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11670 if (inst
.operands
[2].isreg
)
11672 switch (shift_kind
)
11674 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11675 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11676 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11677 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11681 inst
.instruction
|= inst
.operands
[0].reg
;
11682 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11684 /* PR 12854: Error on extraneous shifts. */
11685 constraint (inst
.operands
[2].shifted
,
11686 _("extraneous shift as part of operand to shift insn"));
11690 switch (shift_kind
)
11692 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11693 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11694 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11697 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11698 inst
.instruction
|= inst
.operands
[0].reg
;
11699 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11705 constraint (inst
.operands
[0].reg
> 7
11706 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11707 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11709 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11711 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11712 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11713 _("source1 and dest must be same register"));
11715 switch (inst
.instruction
)
11717 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11718 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11719 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11720 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11724 inst
.instruction
|= inst
.operands
[0].reg
;
11725 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11727 /* PR 12854: Error on extraneous shifts. */
11728 constraint (inst
.operands
[2].shifted
,
11729 _("extraneous shift as part of operand to shift insn"));
11733 switch (inst
.instruction
)
11735 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11736 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11737 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11738 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11741 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11742 inst
.instruction
|= inst
.operands
[0].reg
;
11743 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11751 unsigned Rd
, Rn
, Rm
;
11753 Rd
= inst
.operands
[0].reg
;
11754 Rn
= inst
.operands
[1].reg
;
11755 Rm
= inst
.operands
[2].reg
;
11757 reject_bad_reg (Rd
);
11758 reject_bad_reg (Rn
);
11759 reject_bad_reg (Rm
);
11761 inst
.instruction
|= Rd
<< 8;
11762 inst
.instruction
|= Rn
<< 16;
11763 inst
.instruction
|= Rm
;
11769 unsigned Rd
, Rn
, Rm
;
11771 Rd
= inst
.operands
[0].reg
;
11772 Rm
= inst
.operands
[1].reg
;
11773 Rn
= inst
.operands
[2].reg
;
11775 reject_bad_reg (Rd
);
11776 reject_bad_reg (Rn
);
11777 reject_bad_reg (Rm
);
11779 inst
.instruction
|= Rd
<< 8;
11780 inst
.instruction
|= Rn
<< 16;
11781 inst
.instruction
|= Rm
;
11787 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11788 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11789 _("SMC is not permitted on this architecture"));
11790 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11791 _("expression too complex"));
11792 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11793 inst
.instruction
|= (value
& 0xf000) >> 12;
11794 inst
.instruction
|= (value
& 0x0ff0);
11795 inst
.instruction
|= (value
& 0x000f) << 16;
11801 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11803 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11804 inst
.instruction
|= (value
& 0x0fff);
11805 inst
.instruction
|= (value
& 0xf000) << 4;
11809 do_t_ssat_usat (int bias
)
11813 Rd
= inst
.operands
[0].reg
;
11814 Rn
= inst
.operands
[2].reg
;
11816 reject_bad_reg (Rd
);
11817 reject_bad_reg (Rn
);
11819 inst
.instruction
|= Rd
<< 8;
11820 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11821 inst
.instruction
|= Rn
<< 16;
11823 if (inst
.operands
[3].present
)
11825 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11827 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11829 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11830 _("expression too complex"));
11832 if (shift_amount
!= 0)
11834 constraint (shift_amount
> 31,
11835 _("shift expression is too large"));
11837 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11838 inst
.instruction
|= 0x00200000; /* sh bit. */
11840 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11841 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11849 do_t_ssat_usat (1);
11857 Rd
= inst
.operands
[0].reg
;
11858 Rn
= inst
.operands
[2].reg
;
11860 reject_bad_reg (Rd
);
11861 reject_bad_reg (Rn
);
11863 inst
.instruction
|= Rd
<< 8;
11864 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11865 inst
.instruction
|= Rn
<< 16;
11871 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11872 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11873 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11874 || inst
.operands
[2].negative
,
11877 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11879 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11880 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11881 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11882 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11888 if (!inst
.operands
[2].present
)
11889 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11891 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11892 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11893 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11896 inst
.instruction
|= inst
.operands
[0].reg
;
11897 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11898 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11899 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11905 unsigned Rd
, Rn
, Rm
;
11907 Rd
= inst
.operands
[0].reg
;
11908 Rn
= inst
.operands
[1].reg
;
11909 Rm
= inst
.operands
[2].reg
;
11911 reject_bad_reg (Rd
);
11912 reject_bad_reg (Rn
);
11913 reject_bad_reg (Rm
);
11915 inst
.instruction
|= Rd
<< 8;
11916 inst
.instruction
|= Rn
<< 16;
11917 inst
.instruction
|= Rm
;
11918 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11926 Rd
= inst
.operands
[0].reg
;
11927 Rm
= inst
.operands
[1].reg
;
11929 reject_bad_reg (Rd
);
11930 reject_bad_reg (Rm
);
11932 if (inst
.instruction
<= 0xffff
11933 && inst
.size_req
!= 4
11934 && Rd
<= 7 && Rm
<= 7
11935 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11937 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11938 inst
.instruction
|= Rd
;
11939 inst
.instruction
|= Rm
<< 3;
11941 else if (unified_syntax
)
11943 if (inst
.instruction
<= 0xffff)
11944 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11945 inst
.instruction
|= Rd
<< 8;
11946 inst
.instruction
|= Rm
;
11947 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11951 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11952 _("Thumb encoding does not support rotation"));
11953 constraint (1, BAD_HIREG
);
11960 /* We have to do the following check manually as ARM_EXT_OS only applies
11962 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11964 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11965 /* This only applies to the v6m howver, not later architectures. */
11966 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11967 as_bad (_("SVC is not permitted on this architecture"));
11968 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11971 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11980 half
= (inst
.instruction
& 0x10) != 0;
11981 set_it_insn_type_last ();
11982 constraint (inst
.operands
[0].immisreg
,
11983 _("instruction requires register index"));
11985 Rn
= inst
.operands
[0].reg
;
11986 Rm
= inst
.operands
[0].imm
;
11988 constraint (Rn
== REG_SP
, BAD_SP
);
11989 reject_bad_reg (Rm
);
11991 constraint (!half
&& inst
.operands
[0].shifted
,
11992 _("instruction does not allow shifted index"));
11993 inst
.instruction
|= (Rn
<< 16) | Rm
;
11999 do_t_ssat_usat (0);
12007 Rd
= inst
.operands
[0].reg
;
12008 Rn
= inst
.operands
[2].reg
;
12010 reject_bad_reg (Rd
);
12011 reject_bad_reg (Rn
);
12013 inst
.instruction
|= Rd
<< 8;
12014 inst
.instruction
|= inst
.operands
[1].imm
;
12015 inst
.instruction
|= Rn
<< 16;
12018 /* Neon instruction encoder helpers. */
12020 /* Encodings for the different types for various Neon opcodes. */
12022 /* An "invalid" code for the following tables. */
12025 struct neon_tab_entry
12028 unsigned float_or_poly
;
12029 unsigned scalar_or_imm
;
12032 /* Map overloaded Neon opcodes to their respective encodings. */
12033 #define NEON_ENC_TAB \
12034 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12035 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12036 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12037 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12038 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12039 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12040 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12041 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12042 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12043 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12044 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12045 /* Register variants of the following two instructions are encoded as
12046 vcge / vcgt with the operands reversed. */ \
12047 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12048 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12049 X(vfma, N_INV, 0x0000c10, N_INV), \
12050 X(vfms, N_INV, 0x0200c10, N_INV), \
12051 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12052 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12053 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12054 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12055 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12056 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12057 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12058 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12059 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12060 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12061 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12062 X(vshl, 0x0000400, N_INV, 0x0800510), \
12063 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12064 X(vand, 0x0000110, N_INV, 0x0800030), \
12065 X(vbic, 0x0100110, N_INV, 0x0800030), \
12066 X(veor, 0x1000110, N_INV, N_INV), \
12067 X(vorn, 0x0300110, N_INV, 0x0800010), \
12068 X(vorr, 0x0200110, N_INV, 0x0800010), \
12069 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12070 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12071 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12072 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12073 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12074 X(vst1, 0x0000000, 0x0800000, N_INV), \
12075 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12076 X(vst2, 0x0000100, 0x0800100, N_INV), \
12077 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12078 X(vst3, 0x0000200, 0x0800200, N_INV), \
12079 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12080 X(vst4, 0x0000300, 0x0800300, N_INV), \
12081 X(vmovn, 0x1b20200, N_INV, N_INV), \
12082 X(vtrn, 0x1b20080, N_INV, N_INV), \
12083 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12084 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12085 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12086 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12087 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12088 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12089 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12090 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12091 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12092 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12093 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12097 #define X(OPC,I,F,S) N_MNEM_##OPC
12102 static const struct neon_tab_entry neon_enc_tab
[] =
12104 #define X(OPC,I,F,S) { (I), (F), (S) }
12109 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12110 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12111 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12112 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12113 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12114 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12115 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12116 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12117 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12118 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12119 #define NEON_ENC_SINGLE_(X) \
12120 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12121 #define NEON_ENC_DOUBLE_(X) \
12122 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12124 #define NEON_ENCODE(type, inst) \
12127 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12128 inst.is_neon = 1; \
12132 #define check_neon_suffixes \
12135 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12137 as_bad (_("invalid neon suffix for non neon instruction")); \
12143 /* Define shapes for instruction operands. The following mnemonic characters
12144 are used in this table:
12146 F - VFP S<n> register
12147 D - Neon D<n> register
12148 Q - Neon Q<n> register
12152 L - D<n> register list
12154 This table is used to generate various data:
12155 - enumerations of the form NS_DDR to be used as arguments to
12157 - a table classifying shapes into single, double, quad, mixed.
12158 - a table used to drive neon_select_shape. */
12160 #define NEON_SHAPE_DEF \
12161 X(3, (D, D, D), DOUBLE), \
12162 X(3, (Q, Q, Q), QUAD), \
12163 X(3, (D, D, I), DOUBLE), \
12164 X(3, (Q, Q, I), QUAD), \
12165 X(3, (D, D, S), DOUBLE), \
12166 X(3, (Q, Q, S), QUAD), \
12167 X(2, (D, D), DOUBLE), \
12168 X(2, (Q, Q), QUAD), \
12169 X(2, (D, S), DOUBLE), \
12170 X(2, (Q, S), QUAD), \
12171 X(2, (D, R), DOUBLE), \
12172 X(2, (Q, R), QUAD), \
12173 X(2, (D, I), DOUBLE), \
12174 X(2, (Q, I), QUAD), \
12175 X(3, (D, L, D), DOUBLE), \
12176 X(2, (D, Q), MIXED), \
12177 X(2, (Q, D), MIXED), \
12178 X(3, (D, Q, I), MIXED), \
12179 X(3, (Q, D, I), MIXED), \
12180 X(3, (Q, D, D), MIXED), \
12181 X(3, (D, Q, Q), MIXED), \
12182 X(3, (Q, Q, D), MIXED), \
12183 X(3, (Q, D, S), MIXED), \
12184 X(3, (D, Q, S), MIXED), \
12185 X(4, (D, D, D, I), DOUBLE), \
12186 X(4, (Q, Q, Q, I), QUAD), \
12187 X(2, (F, F), SINGLE), \
12188 X(3, (F, F, F), SINGLE), \
12189 X(2, (F, I), SINGLE), \
12190 X(2, (F, D), MIXED), \
12191 X(2, (D, F), MIXED), \
12192 X(3, (F, F, I), MIXED), \
12193 X(4, (R, R, F, F), SINGLE), \
12194 X(4, (F, F, R, R), SINGLE), \
12195 X(3, (D, R, R), DOUBLE), \
12196 X(3, (R, R, D), DOUBLE), \
12197 X(2, (S, R), SINGLE), \
12198 X(2, (R, S), SINGLE), \
12199 X(2, (F, R), SINGLE), \
12200 X(2, (R, F), SINGLE)
12202 #define S2(A,B) NS_##A##B
12203 #define S3(A,B,C) NS_##A##B##C
12204 #define S4(A,B,C,D) NS_##A##B##C##D
12206 #define X(N, L, C) S##N L
12219 enum neon_shape_class
12227 #define X(N, L, C) SC_##C
12229 static enum neon_shape_class neon_shape_class
[] =
12247 /* Register widths of above. */
12248 static unsigned neon_shape_el_size
[] =
12259 struct neon_shape_info
12262 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12265 #define S2(A,B) { SE_##A, SE_##B }
12266 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12267 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12269 #define X(N, L, C) { N, S##N L }
12271 static struct neon_shape_info neon_shape_tab
[] =
12281 /* Bit masks used in type checking given instructions.
12282 'N_EQK' means the type must be the same as (or based on in some way) the key
12283 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12284 set, various other bits can be set as well in order to modify the meaning of
12285 the type constraint. */
12287 enum neon_type_mask
12310 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12311 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12312 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12313 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12314 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12315 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12316 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12317 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12318 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12319 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12321 N_MAX_NONSPECIAL
= N_F64
12324 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12326 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12327 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12328 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12329 #define N_SUF_32 (N_SU_32 | N_F32)
12330 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12331 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12333 /* Pass this as the first type argument to neon_check_type to ignore types
12335 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12337 /* Select a "shape" for the current instruction (describing register types or
12338 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12339 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12340 function of operand parsing, so this function doesn't need to be called.
12341 Shapes should be listed in order of decreasing length. */
12343 static enum neon_shape
12344 neon_select_shape (enum neon_shape shape
, ...)
12347 enum neon_shape first_shape
= shape
;
12349 /* Fix missing optional operands. FIXME: we don't know at this point how
12350 many arguments we should have, so this makes the assumption that we have
12351 > 1. This is true of all current Neon opcodes, I think, but may not be
12352 true in the future. */
12353 if (!inst
.operands
[1].present
)
12354 inst
.operands
[1] = inst
.operands
[0];
12356 va_start (ap
, shape
);
12358 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12363 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12365 if (!inst
.operands
[j
].present
)
12371 switch (neon_shape_tab
[shape
].el
[j
])
12374 if (!(inst
.operands
[j
].isreg
12375 && inst
.operands
[j
].isvec
12376 && inst
.operands
[j
].issingle
12377 && !inst
.operands
[j
].isquad
))
12382 if (!(inst
.operands
[j
].isreg
12383 && inst
.operands
[j
].isvec
12384 && !inst
.operands
[j
].isquad
12385 && !inst
.operands
[j
].issingle
))
12390 if (!(inst
.operands
[j
].isreg
12391 && !inst
.operands
[j
].isvec
))
12396 if (!(inst
.operands
[j
].isreg
12397 && inst
.operands
[j
].isvec
12398 && inst
.operands
[j
].isquad
12399 && !inst
.operands
[j
].issingle
))
12404 if (!(!inst
.operands
[j
].isreg
12405 && !inst
.operands
[j
].isscalar
))
12410 if (!(!inst
.operands
[j
].isreg
12411 && inst
.operands
[j
].isscalar
))
12421 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
12422 /* We've matched all the entries in the shape table, and we don't
12423 have any left over operands which have not been matched. */
12429 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12430 first_error (_("invalid instruction shape"));
12435 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12436 means the Q bit should be set). */
12439 neon_quad (enum neon_shape shape
)
12441 return neon_shape_class
[shape
] == SC_QUAD
;
12445 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12448 /* Allow modification to be made to types which are constrained to be
12449 based on the key element, based on bits set alongside N_EQK. */
12450 if ((typebits
& N_EQK
) != 0)
12452 if ((typebits
& N_HLF
) != 0)
12454 else if ((typebits
& N_DBL
) != 0)
12456 if ((typebits
& N_SGN
) != 0)
12457 *g_type
= NT_signed
;
12458 else if ((typebits
& N_UNS
) != 0)
12459 *g_type
= NT_unsigned
;
12460 else if ((typebits
& N_INT
) != 0)
12461 *g_type
= NT_integer
;
12462 else if ((typebits
& N_FLT
) != 0)
12463 *g_type
= NT_float
;
12464 else if ((typebits
& N_SIZ
) != 0)
12465 *g_type
= NT_untyped
;
12469 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12470 operand type, i.e. the single type specified in a Neon instruction when it
12471 is the only one given. */
12473 static struct neon_type_el
12474 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12476 struct neon_type_el dest
= *key
;
12478 gas_assert ((thisarg
& N_EQK
) != 0);
12480 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12485 /* Convert Neon type and size into compact bitmask representation. */
12487 static enum neon_type_mask
12488 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12495 case 8: return N_8
;
12496 case 16: return N_16
;
12497 case 32: return N_32
;
12498 case 64: return N_64
;
12506 case 8: return N_I8
;
12507 case 16: return N_I16
;
12508 case 32: return N_I32
;
12509 case 64: return N_I64
;
12517 case 16: return N_F16
;
12518 case 32: return N_F32
;
12519 case 64: return N_F64
;
12527 case 8: return N_P8
;
12528 case 16: return N_P16
;
12536 case 8: return N_S8
;
12537 case 16: return N_S16
;
12538 case 32: return N_S32
;
12539 case 64: return N_S64
;
12547 case 8: return N_U8
;
12548 case 16: return N_U16
;
12549 case 32: return N_U32
;
12550 case 64: return N_U64
;
12561 /* Convert compact Neon bitmask type representation to a type and size. Only
12562 handles the case where a single bit is set in the mask. */
12565 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12566 enum neon_type_mask mask
)
12568 if ((mask
& N_EQK
) != 0)
12571 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12573 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12575 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12577 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12582 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12584 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12585 *type
= NT_unsigned
;
12586 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12587 *type
= NT_integer
;
12588 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12589 *type
= NT_untyped
;
12590 else if ((mask
& (N_P8
| N_P16
)) != 0)
12592 else if ((mask
& (N_F32
| N_F64
)) != 0)
12600 /* Modify a bitmask of allowed types. This is only needed for type
12604 modify_types_allowed (unsigned allowed
, unsigned mods
)
12607 enum neon_el_type type
;
12613 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12615 if (el_type_of_type_chk (&type
, &size
,
12616 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12618 neon_modify_type_size (mods
, &type
, &size
);
12619 destmask
|= type_chk_of_el_type (type
, size
);
12626 /* Check type and return type classification.
12627 The manual states (paraphrase): If one datatype is given, it indicates the
12629 - the second operand, if there is one
12630 - the operand, if there is no second operand
12631 - the result, if there are no operands.
12632 This isn't quite good enough though, so we use a concept of a "key" datatype
12633 which is set on a per-instruction basis, which is the one which matters when
12634 only one data type is written.
12635 Note: this function has side-effects (e.g. filling in missing operands). All
12636 Neon instructions should call it before performing bit encoding. */
12638 static struct neon_type_el
12639 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12642 unsigned i
, pass
, key_el
= 0;
12643 unsigned types
[NEON_MAX_TYPE_ELS
];
12644 enum neon_el_type k_type
= NT_invtype
;
12645 unsigned k_size
= -1u;
12646 struct neon_type_el badtype
= {NT_invtype
, -1};
12647 unsigned key_allowed
= 0;
12649 /* Optional registers in Neon instructions are always (not) in operand 1.
12650 Fill in the missing operand here, if it was omitted. */
12651 if (els
> 1 && !inst
.operands
[1].present
)
12652 inst
.operands
[1] = inst
.operands
[0];
12654 /* Suck up all the varargs. */
12656 for (i
= 0; i
< els
; i
++)
12658 unsigned thisarg
= va_arg (ap
, unsigned);
12659 if (thisarg
== N_IGNORE_TYPE
)
12664 types
[i
] = thisarg
;
12665 if ((thisarg
& N_KEY
) != 0)
12670 if (inst
.vectype
.elems
> 0)
12671 for (i
= 0; i
< els
; i
++)
12672 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12674 first_error (_("types specified in both the mnemonic and operands"));
12678 /* Duplicate inst.vectype elements here as necessary.
12679 FIXME: No idea if this is exactly the same as the ARM assembler,
12680 particularly when an insn takes one register and one non-register
12682 if (inst
.vectype
.elems
== 1 && els
> 1)
12685 inst
.vectype
.elems
= els
;
12686 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12687 for (j
= 0; j
< els
; j
++)
12689 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12692 else if (inst
.vectype
.elems
== 0 && els
> 0)
12695 /* No types were given after the mnemonic, so look for types specified
12696 after each operand. We allow some flexibility here; as long as the
12697 "key" operand has a type, we can infer the others. */
12698 for (j
= 0; j
< els
; j
++)
12699 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12700 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12702 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12704 for (j
= 0; j
< els
; j
++)
12705 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12706 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12711 first_error (_("operand types can't be inferred"));
12715 else if (inst
.vectype
.elems
!= els
)
12717 first_error (_("type specifier has the wrong number of parts"));
12721 for (pass
= 0; pass
< 2; pass
++)
12723 for (i
= 0; i
< els
; i
++)
12725 unsigned thisarg
= types
[i
];
12726 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12727 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12728 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12729 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12731 /* Decay more-specific signed & unsigned types to sign-insensitive
12732 integer types if sign-specific variants are unavailable. */
12733 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12734 && (types_allowed
& N_SU_ALL
) == 0)
12735 g_type
= NT_integer
;
12737 /* If only untyped args are allowed, decay any more specific types to
12738 them. Some instructions only care about signs for some element
12739 sizes, so handle that properly. */
12740 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12741 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12742 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12743 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12744 g_type
= NT_untyped
;
12748 if ((thisarg
& N_KEY
) != 0)
12752 key_allowed
= thisarg
& ~N_KEY
;
12757 if ((thisarg
& N_VFP
) != 0)
12759 enum neon_shape_el regshape
;
12760 unsigned regwidth
, match
;
12762 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12765 first_error (_("invalid instruction shape"));
12768 regshape
= neon_shape_tab
[ns
].el
[i
];
12769 regwidth
= neon_shape_el_size
[regshape
];
12771 /* In VFP mode, operands must match register widths. If we
12772 have a key operand, use its width, else use the width of
12773 the current operand. */
12779 if (regwidth
!= match
)
12781 first_error (_("operand size must match register width"));
12786 if ((thisarg
& N_EQK
) == 0)
12788 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12790 if ((given_type
& types_allowed
) == 0)
12792 first_error (_("bad type in Neon instruction"));
12798 enum neon_el_type mod_k_type
= k_type
;
12799 unsigned mod_k_size
= k_size
;
12800 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12801 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12803 first_error (_("inconsistent types in Neon instruction"));
12811 return inst
.vectype
.el
[key_el
];
12814 /* Neon-style VFP instruction forwarding. */
12816 /* Thumb VFP instructions have 0xE in the condition field. */
12819 do_vfp_cond_or_thumb (void)
12824 inst
.instruction
|= 0xe0000000;
12826 inst
.instruction
|= inst
.cond
<< 28;
12829 /* Look up and encode a simple mnemonic, for use as a helper function for the
12830 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12831 etc. It is assumed that operand parsing has already been done, and that the
12832 operands are in the form expected by the given opcode (this isn't necessarily
12833 the same as the form in which they were parsed, hence some massaging must
12834 take place before this function is called).
12835 Checks current arch version against that in the looked-up opcode. */
12838 do_vfp_nsyn_opcode (const char *opname
)
12840 const struct asm_opcode
*opcode
;
12842 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12847 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12848 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12855 inst
.instruction
= opcode
->tvalue
;
12856 opcode
->tencode ();
12860 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12861 opcode
->aencode ();
12866 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12868 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12873 do_vfp_nsyn_opcode ("fadds");
12875 do_vfp_nsyn_opcode ("fsubs");
12880 do_vfp_nsyn_opcode ("faddd");
12882 do_vfp_nsyn_opcode ("fsubd");
12886 /* Check operand types to see if this is a VFP instruction, and if so call
12890 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12892 enum neon_shape rs
;
12893 struct neon_type_el et
;
12898 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12899 et
= neon_check_type (2, rs
,
12900 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12904 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12905 et
= neon_check_type (3, rs
,
12906 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12913 if (et
.type
!= NT_invtype
)
12924 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12926 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12931 do_vfp_nsyn_opcode ("fmacs");
12933 do_vfp_nsyn_opcode ("fnmacs");
12938 do_vfp_nsyn_opcode ("fmacd");
12940 do_vfp_nsyn_opcode ("fnmacd");
12945 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12947 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12952 do_vfp_nsyn_opcode ("ffmas");
12954 do_vfp_nsyn_opcode ("ffnmas");
12959 do_vfp_nsyn_opcode ("ffmad");
12961 do_vfp_nsyn_opcode ("ffnmad");
12966 do_vfp_nsyn_mul (enum neon_shape rs
)
12969 do_vfp_nsyn_opcode ("fmuls");
12971 do_vfp_nsyn_opcode ("fmuld");
12975 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12977 int is_neg
= (inst
.instruction
& 0x80) != 0;
12978 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12983 do_vfp_nsyn_opcode ("fnegs");
12985 do_vfp_nsyn_opcode ("fabss");
12990 do_vfp_nsyn_opcode ("fnegd");
12992 do_vfp_nsyn_opcode ("fabsd");
12996 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12997 insns belong to Neon, and are handled elsewhere. */
13000 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13002 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13006 do_vfp_nsyn_opcode ("fldmdbs");
13008 do_vfp_nsyn_opcode ("fldmias");
13013 do_vfp_nsyn_opcode ("fstmdbs");
13015 do_vfp_nsyn_opcode ("fstmias");
13020 do_vfp_nsyn_sqrt (void)
13022 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13023 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13026 do_vfp_nsyn_opcode ("fsqrts");
13028 do_vfp_nsyn_opcode ("fsqrtd");
13032 do_vfp_nsyn_div (void)
13034 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13035 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13036 N_F32
| N_F64
| N_KEY
| N_VFP
);
13039 do_vfp_nsyn_opcode ("fdivs");
13041 do_vfp_nsyn_opcode ("fdivd");
13045 do_vfp_nsyn_nmul (void)
13047 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13048 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13049 N_F32
| N_F64
| N_KEY
| N_VFP
);
13053 NEON_ENCODE (SINGLE
, inst
);
13054 do_vfp_sp_dyadic ();
13058 NEON_ENCODE (DOUBLE
, inst
);
13059 do_vfp_dp_rd_rn_rm ();
13061 do_vfp_cond_or_thumb ();
13065 do_vfp_nsyn_cmp (void)
13067 if (inst
.operands
[1].isreg
)
13069 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13070 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13074 NEON_ENCODE (SINGLE
, inst
);
13075 do_vfp_sp_monadic ();
13079 NEON_ENCODE (DOUBLE
, inst
);
13080 do_vfp_dp_rd_rm ();
13085 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13086 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13088 switch (inst
.instruction
& 0x0fffffff)
13091 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13094 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13102 NEON_ENCODE (SINGLE
, inst
);
13103 do_vfp_sp_compare_z ();
13107 NEON_ENCODE (DOUBLE
, inst
);
13111 do_vfp_cond_or_thumb ();
13115 nsyn_insert_sp (void)
13117 inst
.operands
[1] = inst
.operands
[0];
13118 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13119 inst
.operands
[0].reg
= REG_SP
;
13120 inst
.operands
[0].isreg
= 1;
13121 inst
.operands
[0].writeback
= 1;
13122 inst
.operands
[0].present
= 1;
13126 do_vfp_nsyn_push (void)
13129 if (inst
.operands
[1].issingle
)
13130 do_vfp_nsyn_opcode ("fstmdbs");
13132 do_vfp_nsyn_opcode ("fstmdbd");
13136 do_vfp_nsyn_pop (void)
13139 if (inst
.operands
[1].issingle
)
13140 do_vfp_nsyn_opcode ("fldmias");
13142 do_vfp_nsyn_opcode ("fldmiad");
13145 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13146 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13149 neon_dp_fixup (struct arm_it
* insn
)
13151 unsigned int i
= insn
->instruction
;
13156 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13167 insn
->instruction
= i
;
13170 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13174 neon_logbits (unsigned x
)
13176 return ffs (x
) - 4;
13179 #define LOW4(R) ((R) & 0xf)
13180 #define HI1(R) (((R) >> 4) & 1)
13182 /* Encode insns with bit pattern:
13184 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13185 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13187 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13188 different meaning for some instruction. */
13191 neon_three_same (int isquad
, int ubit
, int size
)
13193 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13194 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13195 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13196 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13197 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13198 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13199 inst
.instruction
|= (isquad
!= 0) << 6;
13200 inst
.instruction
|= (ubit
!= 0) << 24;
13202 inst
.instruction
|= neon_logbits (size
) << 20;
13204 neon_dp_fixup (&inst
);
13207 /* Encode instructions of the form:
13209 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13210 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13212 Don't write size if SIZE == -1. */
13215 neon_two_same (int qbit
, int ubit
, int size
)
13217 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13219 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13220 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13221 inst
.instruction
|= (qbit
!= 0) << 6;
13222 inst
.instruction
|= (ubit
!= 0) << 24;
13225 inst
.instruction
|= neon_logbits (size
) << 18;
13227 neon_dp_fixup (&inst
);
13230 /* Neon instruction encoders, in approximate order of appearance. */
13233 do_neon_dyadic_i_su (void)
13235 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13236 struct neon_type_el et
= neon_check_type (3, rs
,
13237 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13238 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13242 do_neon_dyadic_i64_su (void)
13244 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13245 struct neon_type_el et
= neon_check_type (3, rs
,
13246 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13247 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13251 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13254 unsigned size
= et
.size
>> 3;
13255 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13256 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13257 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13258 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13259 inst
.instruction
|= (isquad
!= 0) << 6;
13260 inst
.instruction
|= immbits
<< 16;
13261 inst
.instruction
|= (size
>> 3) << 7;
13262 inst
.instruction
|= (size
& 0x7) << 19;
13264 inst
.instruction
|= (uval
!= 0) << 24;
13266 neon_dp_fixup (&inst
);
13270 do_neon_shl_imm (void)
13272 if (!inst
.operands
[2].isreg
)
13274 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13275 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13276 NEON_ENCODE (IMMED
, inst
);
13277 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13281 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13282 struct neon_type_el et
= neon_check_type (3, rs
,
13283 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13286 /* VSHL/VQSHL 3-register variants have syntax such as:
13288 whereas other 3-register operations encoded by neon_three_same have
13291 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13293 tmp
= inst
.operands
[2].reg
;
13294 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13295 inst
.operands
[1].reg
= tmp
;
13296 NEON_ENCODE (INTEGER
, inst
);
13297 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13302 do_neon_qshl_imm (void)
13304 if (!inst
.operands
[2].isreg
)
13306 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13307 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13309 NEON_ENCODE (IMMED
, inst
);
13310 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13311 inst
.operands
[2].imm
);
13315 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13316 struct neon_type_el et
= neon_check_type (3, rs
,
13317 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13320 /* See note in do_neon_shl_imm. */
13321 tmp
= inst
.operands
[2].reg
;
13322 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13323 inst
.operands
[1].reg
= tmp
;
13324 NEON_ENCODE (INTEGER
, inst
);
13325 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13330 do_neon_rshl (void)
13332 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13333 struct neon_type_el et
= neon_check_type (3, rs
,
13334 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13337 tmp
= inst
.operands
[2].reg
;
13338 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13339 inst
.operands
[1].reg
= tmp
;
13340 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13344 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13346 /* Handle .I8 pseudo-instructions. */
13349 /* Unfortunately, this will make everything apart from zero out-of-range.
13350 FIXME is this the intended semantics? There doesn't seem much point in
13351 accepting .I8 if so. */
13352 immediate
|= immediate
<< 8;
13358 if (immediate
== (immediate
& 0x000000ff))
13360 *immbits
= immediate
;
13363 else if (immediate
== (immediate
& 0x0000ff00))
13365 *immbits
= immediate
>> 8;
13368 else if (immediate
== (immediate
& 0x00ff0000))
13370 *immbits
= immediate
>> 16;
13373 else if (immediate
== (immediate
& 0xff000000))
13375 *immbits
= immediate
>> 24;
13378 if ((immediate
& 0xffff) != (immediate
>> 16))
13379 goto bad_immediate
;
13380 immediate
&= 0xffff;
13383 if (immediate
== (immediate
& 0x000000ff))
13385 *immbits
= immediate
;
13388 else if (immediate
== (immediate
& 0x0000ff00))
13390 *immbits
= immediate
>> 8;
13395 first_error (_("immediate value out of range"));
13399 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13403 neon_bits_same_in_bytes (unsigned imm
)
13405 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13406 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13407 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13408 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13411 /* For immediate of above form, return 0bABCD. */
13414 neon_squash_bits (unsigned imm
)
13416 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13417 | ((imm
& 0x01000000) >> 21);
13420 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13423 neon_qfloat_bits (unsigned imm
)
13425 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13428 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13429 the instruction. *OP is passed as the initial value of the op field, and
13430 may be set to a different value depending on the constant (i.e.
13431 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13432 MVN). If the immediate looks like a repeated pattern then also
13433 try smaller element sizes. */
13436 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13437 unsigned *immbits
, int *op
, int size
,
13438 enum neon_el_type type
)
13440 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13442 if (type
== NT_float
&& !float_p
)
13445 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13447 if (size
!= 32 || *op
== 1)
13449 *immbits
= neon_qfloat_bits (immlo
);
13455 if (neon_bits_same_in_bytes (immhi
)
13456 && neon_bits_same_in_bytes (immlo
))
13460 *immbits
= (neon_squash_bits (immhi
) << 4)
13461 | neon_squash_bits (immlo
);
13466 if (immhi
!= immlo
)
13472 if (immlo
== (immlo
& 0x000000ff))
13477 else if (immlo
== (immlo
& 0x0000ff00))
13479 *immbits
= immlo
>> 8;
13482 else if (immlo
== (immlo
& 0x00ff0000))
13484 *immbits
= immlo
>> 16;
13487 else if (immlo
== (immlo
& 0xff000000))
13489 *immbits
= immlo
>> 24;
13492 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13494 *immbits
= (immlo
>> 8) & 0xff;
13497 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13499 *immbits
= (immlo
>> 16) & 0xff;
13503 if ((immlo
& 0xffff) != (immlo
>> 16))
13510 if (immlo
== (immlo
& 0x000000ff))
13515 else if (immlo
== (immlo
& 0x0000ff00))
13517 *immbits
= immlo
>> 8;
13521 if ((immlo
& 0xff) != (immlo
>> 8))
13526 if (immlo
== (immlo
& 0x000000ff))
13528 /* Don't allow MVN with 8-bit immediate. */
13538 /* Write immediate bits [7:0] to the following locations:
13540 |28/24|23 19|18 16|15 4|3 0|
13541 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13543 This function is used by VMOV/VMVN/VORR/VBIC. */
13546 neon_write_immbits (unsigned immbits
)
13548 inst
.instruction
|= immbits
& 0xf;
13549 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13550 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13553 /* Invert low-order SIZE bits of XHI:XLO. */
13556 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13558 unsigned immlo
= xlo
? *xlo
: 0;
13559 unsigned immhi
= xhi
? *xhi
: 0;
13564 immlo
= (~immlo
) & 0xff;
13568 immlo
= (~immlo
) & 0xffff;
13572 immhi
= (~immhi
) & 0xffffffff;
13573 /* fall through. */
13576 immlo
= (~immlo
) & 0xffffffff;
13591 do_neon_logic (void)
13593 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13595 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13596 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13597 /* U bit and size field were set as part of the bitmask. */
13598 NEON_ENCODE (INTEGER
, inst
);
13599 neon_three_same (neon_quad (rs
), 0, -1);
13603 const int three_ops_form
= (inst
.operands
[2].present
13604 && !inst
.operands
[2].isreg
);
13605 const int immoperand
= (three_ops_form
? 2 : 1);
13606 enum neon_shape rs
= (three_ops_form
13607 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13608 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13609 struct neon_type_el et
= neon_check_type (2, rs
,
13610 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13611 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13615 if (et
.type
== NT_invtype
)
13618 if (three_ops_form
)
13619 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13620 _("first and second operands shall be the same register"));
13622 NEON_ENCODE (IMMED
, inst
);
13624 immbits
= inst
.operands
[immoperand
].imm
;
13627 /* .i64 is a pseudo-op, so the immediate must be a repeating
13629 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13630 inst
.operands
[immoperand
].reg
: 0))
13632 /* Set immbits to an invalid constant. */
13633 immbits
= 0xdeadbeef;
13640 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13644 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13648 /* Pseudo-instruction for VBIC. */
13649 neon_invert_size (&immbits
, 0, et
.size
);
13650 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13654 /* Pseudo-instruction for VORR. */
13655 neon_invert_size (&immbits
, 0, et
.size
);
13656 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13666 inst
.instruction
|= neon_quad (rs
) << 6;
13667 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13668 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13669 inst
.instruction
|= cmode
<< 8;
13670 neon_write_immbits (immbits
);
13672 neon_dp_fixup (&inst
);
13677 do_neon_bitfield (void)
13679 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13680 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13681 neon_three_same (neon_quad (rs
), 0, -1);
13685 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13688 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13689 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13691 if (et
.type
== NT_float
)
13693 NEON_ENCODE (FLOAT
, inst
);
13694 neon_three_same (neon_quad (rs
), 0, -1);
13698 NEON_ENCODE (INTEGER
, inst
);
13699 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13704 do_neon_dyadic_if_su (void)
13706 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13710 do_neon_dyadic_if_su_d (void)
13712 /* This version only allow D registers, but that constraint is enforced during
13713 operand parsing so we don't need to do anything extra here. */
13714 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13718 do_neon_dyadic_if_i_d (void)
13720 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13721 affected if we specify unsigned args. */
13722 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13725 enum vfp_or_neon_is_neon_bits
13728 NEON_CHECK_ARCH
= 2
13731 /* Call this function if an instruction which may have belonged to the VFP or
13732 Neon instruction sets, but turned out to be a Neon instruction (due to the
13733 operand types involved, etc.). We have to check and/or fix-up a couple of
13736 - Make sure the user hasn't attempted to make a Neon instruction
13738 - Alter the value in the condition code field if necessary.
13739 - Make sure that the arch supports Neon instructions.
13741 Which of these operations take place depends on bits from enum
13742 vfp_or_neon_is_neon_bits.
13744 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13745 current instruction's condition is COND_ALWAYS, the condition field is
13746 changed to inst.uncond_value. This is necessary because instructions shared
13747 between VFP and Neon may be conditional for the VFP variants only, and the
13748 unconditional Neon version must have, e.g., 0xF in the condition field. */
13751 vfp_or_neon_is_neon (unsigned check
)
13753 /* Conditions are always legal in Thumb mode (IT blocks). */
13754 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13756 if (inst
.cond
!= COND_ALWAYS
)
13758 first_error (_(BAD_COND
));
13761 if (inst
.uncond_value
!= -1)
13762 inst
.instruction
|= inst
.uncond_value
<< 28;
13765 if ((check
& NEON_CHECK_ARCH
)
13766 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13768 first_error (_(BAD_FPU
));
13776 do_neon_addsub_if_i (void)
13778 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13781 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13784 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13785 affected if we specify unsigned args. */
13786 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13789 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13791 V<op> A,B (A is operand 0, B is operand 2)
13796 so handle that case specially. */
13799 neon_exchange_operands (void)
13801 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13802 if (inst
.operands
[1].present
)
13804 /* Swap operands[1] and operands[2]. */
13805 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13806 inst
.operands
[1] = inst
.operands
[2];
13807 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13811 inst
.operands
[1] = inst
.operands
[2];
13812 inst
.operands
[2] = inst
.operands
[0];
13817 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13819 if (inst
.operands
[2].isreg
)
13822 neon_exchange_operands ();
13823 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13827 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13828 struct neon_type_el et
= neon_check_type (2, rs
,
13829 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13831 NEON_ENCODE (IMMED
, inst
);
13832 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13833 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13834 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13835 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13836 inst
.instruction
|= neon_quad (rs
) << 6;
13837 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13838 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13840 neon_dp_fixup (&inst
);
13847 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13851 do_neon_cmp_inv (void)
13853 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13859 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13862 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13863 scalars, which are encoded in 5 bits, M : Rm.
13864 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13865 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13869 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13871 unsigned regno
= NEON_SCALAR_REG (scalar
);
13872 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13877 if (regno
> 7 || elno
> 3)
13879 return regno
| (elno
<< 3);
13882 if (regno
> 15 || elno
> 1)
13884 return regno
| (elno
<< 4);
13888 first_error (_("scalar out of range for multiply instruction"));
13894 /* Encode multiply / multiply-accumulate scalar instructions. */
13897 neon_mul_mac (struct neon_type_el et
, int ubit
)
13901 /* Give a more helpful error message if we have an invalid type. */
13902 if (et
.type
== NT_invtype
)
13905 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13906 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13907 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13908 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13909 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13910 inst
.instruction
|= LOW4 (scalar
);
13911 inst
.instruction
|= HI1 (scalar
) << 5;
13912 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13913 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13914 inst
.instruction
|= (ubit
!= 0) << 24;
13916 neon_dp_fixup (&inst
);
13920 do_neon_mac_maybe_scalar (void)
13922 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13925 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13928 if (inst
.operands
[2].isscalar
)
13930 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13931 struct neon_type_el et
= neon_check_type (3, rs
,
13932 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13933 NEON_ENCODE (SCALAR
, inst
);
13934 neon_mul_mac (et
, neon_quad (rs
));
13938 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13939 affected if we specify unsigned args. */
13940 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13945 do_neon_fmac (void)
13947 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13950 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13953 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13959 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13960 struct neon_type_el et
= neon_check_type (3, rs
,
13961 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13962 neon_three_same (neon_quad (rs
), 0, et
.size
);
13965 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13966 same types as the MAC equivalents. The polynomial type for this instruction
13967 is encoded the same as the integer type. */
13972 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13975 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13978 if (inst
.operands
[2].isscalar
)
13979 do_neon_mac_maybe_scalar ();
13981 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13985 do_neon_qdmulh (void)
13987 if (inst
.operands
[2].isscalar
)
13989 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13990 struct neon_type_el et
= neon_check_type (3, rs
,
13991 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13992 NEON_ENCODE (SCALAR
, inst
);
13993 neon_mul_mac (et
, neon_quad (rs
));
13997 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13998 struct neon_type_el et
= neon_check_type (3, rs
,
13999 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14000 NEON_ENCODE (INTEGER
, inst
);
14001 /* The U bit (rounding) comes from bit mask. */
14002 neon_three_same (neon_quad (rs
), 0, et
.size
);
14007 do_neon_fcmp_absolute (void)
14009 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14010 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14011 /* Size field comes from bit mask. */
14012 neon_three_same (neon_quad (rs
), 1, -1);
14016 do_neon_fcmp_absolute_inv (void)
14018 neon_exchange_operands ();
14019 do_neon_fcmp_absolute ();
14023 do_neon_step (void)
14025 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14026 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14027 neon_three_same (neon_quad (rs
), 0, -1);
14031 do_neon_abs_neg (void)
14033 enum neon_shape rs
;
14034 struct neon_type_el et
;
14036 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14039 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14042 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14043 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14045 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14046 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14047 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14048 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14049 inst
.instruction
|= neon_quad (rs
) << 6;
14050 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14051 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14053 neon_dp_fixup (&inst
);
14059 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14060 struct neon_type_el et
= neon_check_type (2, rs
,
14061 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14062 int imm
= inst
.operands
[2].imm
;
14063 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14064 _("immediate out of range for insert"));
14065 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14071 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14072 struct neon_type_el et
= neon_check_type (2, rs
,
14073 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14074 int imm
= inst
.operands
[2].imm
;
14075 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14076 _("immediate out of range for insert"));
14077 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14081 do_neon_qshlu_imm (void)
14083 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14084 struct neon_type_el et
= neon_check_type (2, rs
,
14085 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14086 int imm
= inst
.operands
[2].imm
;
14087 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14088 _("immediate out of range for shift"));
14089 /* Only encodes the 'U present' variant of the instruction.
14090 In this case, signed types have OP (bit 8) set to 0.
14091 Unsigned types have OP set to 1. */
14092 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14093 /* The rest of the bits are the same as other immediate shifts. */
14094 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14098 do_neon_qmovn (void)
14100 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14101 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14102 /* Saturating move where operands can be signed or unsigned, and the
14103 destination has the same signedness. */
14104 NEON_ENCODE (INTEGER
, inst
);
14105 if (et
.type
== NT_unsigned
)
14106 inst
.instruction
|= 0xc0;
14108 inst
.instruction
|= 0x80;
14109 neon_two_same (0, 1, et
.size
/ 2);
14113 do_neon_qmovun (void)
14115 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14116 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14117 /* Saturating move with unsigned results. Operands must be signed. */
14118 NEON_ENCODE (INTEGER
, inst
);
14119 neon_two_same (0, 1, et
.size
/ 2);
14123 do_neon_rshift_sat_narrow (void)
14125 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14126 or unsigned. If operands are unsigned, results must also be unsigned. */
14127 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14128 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14129 int imm
= inst
.operands
[2].imm
;
14130 /* This gets the bounds check, size encoding and immediate bits calculation
14134 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14135 VQMOVN.I<size> <Dd>, <Qm>. */
14138 inst
.operands
[2].present
= 0;
14139 inst
.instruction
= N_MNEM_vqmovn
;
14144 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14145 _("immediate out of range"));
14146 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14150 do_neon_rshift_sat_narrow_u (void)
14152 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14153 or unsigned. If operands are unsigned, results must also be unsigned. */
14154 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14155 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14156 int imm
= inst
.operands
[2].imm
;
14157 /* This gets the bounds check, size encoding and immediate bits calculation
14161 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14162 VQMOVUN.I<size> <Dd>, <Qm>. */
14165 inst
.operands
[2].present
= 0;
14166 inst
.instruction
= N_MNEM_vqmovun
;
14171 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14172 _("immediate out of range"));
14173 /* FIXME: The manual is kind of unclear about what value U should have in
14174 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14176 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14180 do_neon_movn (void)
14182 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14183 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14184 NEON_ENCODE (INTEGER
, inst
);
14185 neon_two_same (0, 1, et
.size
/ 2);
14189 do_neon_rshift_narrow (void)
14191 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14192 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14193 int imm
= inst
.operands
[2].imm
;
14194 /* This gets the bounds check, size encoding and immediate bits calculation
14198 /* If immediate is zero then we are a pseudo-instruction for
14199 VMOVN.I<size> <Dd>, <Qm> */
14202 inst
.operands
[2].present
= 0;
14203 inst
.instruction
= N_MNEM_vmovn
;
14208 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14209 _("immediate out of range for narrowing operation"));
14210 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14214 do_neon_shll (void)
14216 /* FIXME: Type checking when lengthening. */
14217 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14218 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14219 unsigned imm
= inst
.operands
[2].imm
;
14221 if (imm
== et
.size
)
14223 /* Maximum shift variant. */
14224 NEON_ENCODE (INTEGER
, inst
);
14225 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14226 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14227 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14228 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14229 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14231 neon_dp_fixup (&inst
);
14235 /* A more-specific type check for non-max versions. */
14236 et
= neon_check_type (2, NS_QDI
,
14237 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14238 NEON_ENCODE (IMMED
, inst
);
14239 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14243 /* Check the various types for the VCVT instruction, and return which version
14244 the current instruction is. */
14247 neon_cvt_flavour (enum neon_shape rs
)
14249 #define CVT_VAR(C,X,Y) \
14250 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14251 if (et.type != NT_invtype) \
14253 inst.error = NULL; \
14256 struct neon_type_el et
;
14257 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14258 || rs
== NS_FF
) ? N_VFP
: 0;
14259 /* The instruction versions which take an immediate take one register
14260 argument, which is extended to the width of the full register. Thus the
14261 "source" and "destination" registers must have the same width. Hack that
14262 here by making the size equal to the key (wider, in this case) operand. */
14263 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14265 CVT_VAR (0, N_S32
, N_F32
);
14266 CVT_VAR (1, N_U32
, N_F32
);
14267 CVT_VAR (2, N_F32
, N_S32
);
14268 CVT_VAR (3, N_F32
, N_U32
);
14269 /* Half-precision conversions. */
14270 CVT_VAR (4, N_F32
, N_F16
);
14271 CVT_VAR (5, N_F16
, N_F32
);
14275 /* VFP instructions. */
14276 CVT_VAR (6, N_F32
, N_F64
);
14277 CVT_VAR (7, N_F64
, N_F32
);
14278 CVT_VAR (8, N_S32
, N_F64
| key
);
14279 CVT_VAR (9, N_U32
, N_F64
| key
);
14280 CVT_VAR (10, N_F64
| key
, N_S32
);
14281 CVT_VAR (11, N_F64
| key
, N_U32
);
14282 /* VFP instructions with bitshift. */
14283 CVT_VAR (12, N_F32
| key
, N_S16
);
14284 CVT_VAR (13, N_F32
| key
, N_U16
);
14285 CVT_VAR (14, N_F64
| key
, N_S16
);
14286 CVT_VAR (15, N_F64
| key
, N_U16
);
14287 CVT_VAR (16, N_S16
, N_F32
| key
);
14288 CVT_VAR (17, N_U16
, N_F32
| key
);
14289 CVT_VAR (18, N_S16
, N_F64
| key
);
14290 CVT_VAR (19, N_U16
, N_F64
| key
);
14296 /* Neon-syntax VFP conversions. */
14299 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14301 const char *opname
= 0;
14303 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14305 /* Conversions with immediate bitshift. */
14306 const char *enc
[] =
14330 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14332 opname
= enc
[flavour
];
14333 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14334 _("operands 0 and 1 must be the same register"));
14335 inst
.operands
[1] = inst
.operands
[2];
14336 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14341 /* Conversions without bitshift. */
14342 const char *enc
[] =
14358 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14359 opname
= enc
[flavour
];
14363 do_vfp_nsyn_opcode (opname
);
14367 do_vfp_nsyn_cvtz (void)
14369 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14370 int flavour
= neon_cvt_flavour (rs
);
14371 const char *enc
[] =
14385 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14386 do_vfp_nsyn_opcode (enc
[flavour
]);
14390 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14392 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14393 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14394 int flavour
= neon_cvt_flavour (rs
);
14396 /* PR11109: Handle round-to-zero for VCVT conversions. */
14398 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14399 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14400 && (rs
== NS_FD
|| rs
== NS_FF
))
14402 do_vfp_nsyn_cvtz ();
14406 /* VFP rather than Neon conversions. */
14409 do_vfp_nsyn_cvt (rs
, flavour
);
14419 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14421 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14424 /* Fixed-point conversion with #0 immediate is encoded as an
14425 integer conversion. */
14426 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14428 immbits
= 32 - inst
.operands
[2].imm
;
14429 NEON_ENCODE (IMMED
, inst
);
14431 inst
.instruction
|= enctab
[flavour
];
14432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14436 inst
.instruction
|= neon_quad (rs
) << 6;
14437 inst
.instruction
|= 1 << 21;
14438 inst
.instruction
|= immbits
<< 16;
14440 neon_dp_fixup (&inst
);
14448 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14450 NEON_ENCODE (INTEGER
, inst
);
14452 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14456 inst
.instruction
|= enctab
[flavour
];
14458 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14459 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14460 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14461 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14462 inst
.instruction
|= neon_quad (rs
) << 6;
14463 inst
.instruction
|= 2 << 18;
14465 neon_dp_fixup (&inst
);
14469 /* Half-precision conversions for Advanced SIMD -- neon. */
14474 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14476 as_bad (_("operand size must match register width"));
14481 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14483 as_bad (_("operand size must match register width"));
14488 inst
.instruction
= 0x3b60600;
14490 inst
.instruction
= 0x3b60700;
14492 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14493 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14494 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14495 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14496 neon_dp_fixup (&inst
);
14500 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14501 do_vfp_nsyn_cvt (rs
, flavour
);
14506 do_neon_cvtr (void)
14508 do_neon_cvt_1 (FALSE
);
14514 do_neon_cvt_1 (TRUE
);
14518 do_neon_cvtb (void)
14520 inst
.instruction
= 0xeb20a40;
14522 /* The sizes are attached to the mnemonic. */
14523 if (inst
.vectype
.el
[0].type
!= NT_invtype
14524 && inst
.vectype
.el
[0].size
== 16)
14525 inst
.instruction
|= 0x00010000;
14527 /* Programmer's syntax: the sizes are attached to the operands. */
14528 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14529 && inst
.operands
[0].vectype
.size
== 16)
14530 inst
.instruction
|= 0x00010000;
14532 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14533 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14534 do_vfp_cond_or_thumb ();
14539 do_neon_cvtt (void)
14542 inst
.instruction
|= 0x80;
14546 neon_move_immediate (void)
14548 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14549 struct neon_type_el et
= neon_check_type (2, rs
,
14550 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14551 unsigned immlo
, immhi
= 0, immbits
;
14552 int op
, cmode
, float_p
;
14554 constraint (et
.type
== NT_invtype
,
14555 _("operand size must be specified for immediate VMOV"));
14557 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14558 op
= (inst
.instruction
& (1 << 5)) != 0;
14560 immlo
= inst
.operands
[1].imm
;
14561 if (inst
.operands
[1].regisimm
)
14562 immhi
= inst
.operands
[1].reg
;
14564 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14565 _("immediate has bits set outside the operand size"));
14567 float_p
= inst
.operands
[1].immisfloat
;
14569 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14570 et
.size
, et
.type
)) == FAIL
)
14572 /* Invert relevant bits only. */
14573 neon_invert_size (&immlo
, &immhi
, et
.size
);
14574 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14575 with one or the other; those cases are caught by
14576 neon_cmode_for_move_imm. */
14578 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14579 &op
, et
.size
, et
.type
)) == FAIL
)
14581 first_error (_("immediate out of range"));
14586 inst
.instruction
&= ~(1 << 5);
14587 inst
.instruction
|= op
<< 5;
14589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14591 inst
.instruction
|= neon_quad (rs
) << 6;
14592 inst
.instruction
|= cmode
<< 8;
14594 neon_write_immbits (immbits
);
14600 if (inst
.operands
[1].isreg
)
14602 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14604 NEON_ENCODE (INTEGER
, inst
);
14605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14608 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14609 inst
.instruction
|= neon_quad (rs
) << 6;
14613 NEON_ENCODE (IMMED
, inst
);
14614 neon_move_immediate ();
14617 neon_dp_fixup (&inst
);
14620 /* Encode instructions of form:
14622 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14623 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14626 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14628 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14629 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14630 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14631 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14632 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14633 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14634 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14635 inst
.instruction
|= neon_logbits (size
) << 20;
14637 neon_dp_fixup (&inst
);
14641 do_neon_dyadic_long (void)
14643 /* FIXME: Type checking for lengthening op. */
14644 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14645 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14646 neon_mixed_length (et
, et
.size
);
14650 do_neon_abal (void)
14652 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14653 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14654 neon_mixed_length (et
, et
.size
);
14658 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14660 if (inst
.operands
[2].isscalar
)
14662 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14663 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14664 NEON_ENCODE (SCALAR
, inst
);
14665 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14669 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14670 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14671 NEON_ENCODE (INTEGER
, inst
);
14672 neon_mixed_length (et
, et
.size
);
14677 do_neon_mac_maybe_scalar_long (void)
14679 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14683 do_neon_dyadic_wide (void)
14685 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14686 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14687 neon_mixed_length (et
, et
.size
);
14691 do_neon_dyadic_narrow (void)
14693 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14694 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14695 /* Operand sign is unimportant, and the U bit is part of the opcode,
14696 so force the operand type to integer. */
14697 et
.type
= NT_integer
;
14698 neon_mixed_length (et
, et
.size
/ 2);
14702 do_neon_mul_sat_scalar_long (void)
14704 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14708 do_neon_vmull (void)
14710 if (inst
.operands
[2].isscalar
)
14711 do_neon_mac_maybe_scalar_long ();
14714 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14715 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14716 if (et
.type
== NT_poly
)
14717 NEON_ENCODE (POLY
, inst
);
14719 NEON_ENCODE (INTEGER
, inst
);
14720 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14721 zero. Should be OK as-is. */
14722 neon_mixed_length (et
, et
.size
);
14729 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14730 struct neon_type_el et
= neon_check_type (3, rs
,
14731 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14732 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14734 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14735 _("shift out of range"));
14736 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14738 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14739 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14740 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14741 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14742 inst
.instruction
|= neon_quad (rs
) << 6;
14743 inst
.instruction
|= imm
<< 8;
14745 neon_dp_fixup (&inst
);
14751 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14752 struct neon_type_el et
= neon_check_type (2, rs
,
14753 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14754 unsigned op
= (inst
.instruction
>> 7) & 3;
14755 /* N (width of reversed regions) is encoded as part of the bitmask. We
14756 extract it here to check the elements to be reversed are smaller.
14757 Otherwise we'd get a reserved instruction. */
14758 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14759 gas_assert (elsize
!= 0);
14760 constraint (et
.size
>= elsize
,
14761 _("elements must be smaller than reversal region"));
14762 neon_two_same (neon_quad (rs
), 1, et
.size
);
14768 if (inst
.operands
[1].isscalar
)
14770 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14771 struct neon_type_el et
= neon_check_type (2, rs
,
14772 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14773 unsigned sizebits
= et
.size
>> 3;
14774 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14775 int logsize
= neon_logbits (et
.size
);
14776 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14778 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14781 NEON_ENCODE (SCALAR
, inst
);
14782 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14783 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14784 inst
.instruction
|= LOW4 (dm
);
14785 inst
.instruction
|= HI1 (dm
) << 5;
14786 inst
.instruction
|= neon_quad (rs
) << 6;
14787 inst
.instruction
|= x
<< 17;
14788 inst
.instruction
|= sizebits
<< 16;
14790 neon_dp_fixup (&inst
);
14794 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14795 struct neon_type_el et
= neon_check_type (2, rs
,
14796 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14797 /* Duplicate ARM register to lanes of vector. */
14798 NEON_ENCODE (ARMREG
, inst
);
14801 case 8: inst
.instruction
|= 0x400000; break;
14802 case 16: inst
.instruction
|= 0x000020; break;
14803 case 32: inst
.instruction
|= 0x000000; break;
14806 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14807 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14808 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14809 inst
.instruction
|= neon_quad (rs
) << 21;
14810 /* The encoding for this instruction is identical for the ARM and Thumb
14811 variants, except for the condition field. */
14812 do_vfp_cond_or_thumb ();
14816 /* VMOV has particularly many variations. It can be one of:
14817 0. VMOV<c><q> <Qd>, <Qm>
14818 1. VMOV<c><q> <Dd>, <Dm>
14819 (Register operations, which are VORR with Rm = Rn.)
14820 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14821 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14823 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14824 (ARM register to scalar.)
14825 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14826 (Two ARM registers to vector.)
14827 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14828 (Scalar to ARM register.)
14829 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14830 (Vector to two ARM registers.)
14831 8. VMOV.F32 <Sd>, <Sm>
14832 9. VMOV.F64 <Dd>, <Dm>
14833 (VFP register moves.)
14834 10. VMOV.F32 <Sd>, #imm
14835 11. VMOV.F64 <Dd>, #imm
14836 (VFP float immediate load.)
14837 12. VMOV <Rd>, <Sm>
14838 (VFP single to ARM reg.)
14839 13. VMOV <Sd>, <Rm>
14840 (ARM reg to VFP single.)
14841 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14842 (Two ARM regs to two VFP singles.)
14843 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14844 (Two VFP singles to two ARM regs.)
14846 These cases can be disambiguated using neon_select_shape, except cases 1/9
14847 and 3/11 which depend on the operand type too.
14849 All the encoded bits are hardcoded by this function.
14851 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14852 Cases 5, 7 may be used with VFPv2 and above.
14854 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14855 can specify a type where it doesn't make sense to, and is ignored). */
14860 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14861 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14863 struct neon_type_el et
;
14864 const char *ldconst
= 0;
14868 case NS_DD
: /* case 1/9. */
14869 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14870 /* It is not an error here if no type is given. */
14872 if (et
.type
== NT_float
&& et
.size
== 64)
14874 do_vfp_nsyn_opcode ("fcpyd");
14877 /* fall through. */
14879 case NS_QQ
: /* case 0/1. */
14881 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14883 /* The architecture manual I have doesn't explicitly state which
14884 value the U bit should have for register->register moves, but
14885 the equivalent VORR instruction has U = 0, so do that. */
14886 inst
.instruction
= 0x0200110;
14887 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14888 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14889 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14890 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14891 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14892 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14893 inst
.instruction
|= neon_quad (rs
) << 6;
14895 neon_dp_fixup (&inst
);
14899 case NS_DI
: /* case 3/11. */
14900 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14902 if (et
.type
== NT_float
&& et
.size
== 64)
14904 /* case 11 (fconstd). */
14905 ldconst
= "fconstd";
14906 goto encode_fconstd
;
14908 /* fall through. */
14910 case NS_QI
: /* case 2/3. */
14911 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14913 inst
.instruction
= 0x0800010;
14914 neon_move_immediate ();
14915 neon_dp_fixup (&inst
);
14918 case NS_SR
: /* case 4. */
14920 unsigned bcdebits
= 0;
14922 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14923 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14925 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14926 logsize
= neon_logbits (et
.size
);
14928 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14930 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14931 && et
.size
!= 32, _(BAD_FPU
));
14932 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14933 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14937 case 8: bcdebits
= 0x8; break;
14938 case 16: bcdebits
= 0x1; break;
14939 case 32: bcdebits
= 0x0; break;
14943 bcdebits
|= x
<< logsize
;
14945 inst
.instruction
= 0xe000b10;
14946 do_vfp_cond_or_thumb ();
14947 inst
.instruction
|= LOW4 (dn
) << 16;
14948 inst
.instruction
|= HI1 (dn
) << 7;
14949 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14950 inst
.instruction
|= (bcdebits
& 3) << 5;
14951 inst
.instruction
|= (bcdebits
>> 2) << 21;
14955 case NS_DRR
: /* case 5 (fmdrr). */
14956 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14959 inst
.instruction
= 0xc400b10;
14960 do_vfp_cond_or_thumb ();
14961 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14962 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14963 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14964 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14967 case NS_RS
: /* case 6. */
14970 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14971 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14972 unsigned abcdebits
= 0;
14974 et
= neon_check_type (2, NS_NULL
,
14975 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14976 logsize
= neon_logbits (et
.size
);
14978 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14980 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14981 && et
.size
!= 32, _(BAD_FPU
));
14982 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14983 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14987 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14988 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14989 case 32: abcdebits
= 0x00; break;
14993 abcdebits
|= x
<< logsize
;
14994 inst
.instruction
= 0xe100b10;
14995 do_vfp_cond_or_thumb ();
14996 inst
.instruction
|= LOW4 (dn
) << 16;
14997 inst
.instruction
|= HI1 (dn
) << 7;
14998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14999 inst
.instruction
|= (abcdebits
& 3) << 5;
15000 inst
.instruction
|= (abcdebits
>> 2) << 21;
15004 case NS_RRD
: /* case 7 (fmrrd). */
15005 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15008 inst
.instruction
= 0xc500b10;
15009 do_vfp_cond_or_thumb ();
15010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15012 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15013 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15016 case NS_FF
: /* case 8 (fcpys). */
15017 do_vfp_nsyn_opcode ("fcpys");
15020 case NS_FI
: /* case 10 (fconsts). */
15021 ldconst
= "fconsts";
15023 if (is_quarter_float (inst
.operands
[1].imm
))
15025 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15026 do_vfp_nsyn_opcode (ldconst
);
15029 first_error (_("immediate out of range"));
15032 case NS_RF
: /* case 12 (fmrs). */
15033 do_vfp_nsyn_opcode ("fmrs");
15036 case NS_FR
: /* case 13 (fmsr). */
15037 do_vfp_nsyn_opcode ("fmsr");
15040 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15041 (one of which is a list), but we have parsed four. Do some fiddling to
15042 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15044 case NS_RRFF
: /* case 14 (fmrrs). */
15045 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15046 _("VFP registers must be adjacent"));
15047 inst
.operands
[2].imm
= 2;
15048 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15049 do_vfp_nsyn_opcode ("fmrrs");
15052 case NS_FFRR
: /* case 15 (fmsrr). */
15053 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15054 _("VFP registers must be adjacent"));
15055 inst
.operands
[1] = inst
.operands
[2];
15056 inst
.operands
[2] = inst
.operands
[3];
15057 inst
.operands
[0].imm
= 2;
15058 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15059 do_vfp_nsyn_opcode ("fmsrr");
15068 do_neon_rshift_round_imm (void)
15070 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15071 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15072 int imm
= inst
.operands
[2].imm
;
15074 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15077 inst
.operands
[2].present
= 0;
15082 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15083 _("immediate out of range for shift"));
15084 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15089 do_neon_movl (void)
15091 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15092 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15093 unsigned sizebits
= et
.size
>> 3;
15094 inst
.instruction
|= sizebits
<< 19;
15095 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15101 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15102 struct neon_type_el et
= neon_check_type (2, rs
,
15103 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15104 NEON_ENCODE (INTEGER
, inst
);
15105 neon_two_same (neon_quad (rs
), 1, et
.size
);
15109 do_neon_zip_uzp (void)
15111 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15112 struct neon_type_el et
= neon_check_type (2, rs
,
15113 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15114 if (rs
== NS_DD
&& et
.size
== 32)
15116 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15117 inst
.instruction
= N_MNEM_vtrn
;
15121 neon_two_same (neon_quad (rs
), 1, et
.size
);
15125 do_neon_sat_abs_neg (void)
15127 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15128 struct neon_type_el et
= neon_check_type (2, rs
,
15129 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15130 neon_two_same (neon_quad (rs
), 1, et
.size
);
15134 do_neon_pair_long (void)
15136 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15137 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15138 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15139 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15140 neon_two_same (neon_quad (rs
), 1, et
.size
);
15144 do_neon_recip_est (void)
15146 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15147 struct neon_type_el et
= neon_check_type (2, rs
,
15148 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15149 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15150 neon_two_same (neon_quad (rs
), 1, et
.size
);
15156 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15157 struct neon_type_el et
= neon_check_type (2, rs
,
15158 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15159 neon_two_same (neon_quad (rs
), 1, et
.size
);
15165 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15166 struct neon_type_el et
= neon_check_type (2, rs
,
15167 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15168 neon_two_same (neon_quad (rs
), 1, et
.size
);
15174 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15175 struct neon_type_el et
= neon_check_type (2, rs
,
15176 N_EQK
| N_INT
, N_8
| N_KEY
);
15177 neon_two_same (neon_quad (rs
), 1, et
.size
);
15183 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15184 neon_two_same (neon_quad (rs
), 1, -1);
15188 do_neon_tbl_tbx (void)
15190 unsigned listlenbits
;
15191 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15193 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15195 first_error (_("bad list length for table lookup"));
15199 listlenbits
= inst
.operands
[1].imm
- 1;
15200 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15201 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15202 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15203 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15204 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15205 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15206 inst
.instruction
|= listlenbits
<< 8;
15208 neon_dp_fixup (&inst
);
15212 do_neon_ldm_stm (void)
15214 /* P, U and L bits are part of bitmask. */
15215 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15216 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15218 if (inst
.operands
[1].issingle
)
15220 do_vfp_nsyn_ldm_stm (is_dbmode
);
15224 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15225 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15227 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15228 _("register list must contain at least 1 and at most 16 "
15231 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15232 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15233 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15236 inst
.instruction
|= offsetbits
;
15238 do_vfp_cond_or_thumb ();
15242 do_neon_ldr_str (void)
15244 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15246 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15247 And is UNPREDICTABLE in thumb mode. */
15249 && inst
.operands
[1].reg
== REG_PC
15250 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15252 if (!thumb_mode
&& warn_on_deprecated
)
15253 as_warn (_("Use of PC here is deprecated"));
15255 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15258 if (inst
.operands
[0].issingle
)
15261 do_vfp_nsyn_opcode ("flds");
15263 do_vfp_nsyn_opcode ("fsts");
15268 do_vfp_nsyn_opcode ("fldd");
15270 do_vfp_nsyn_opcode ("fstd");
15274 /* "interleave" version also handles non-interleaving register VLD1/VST1
15278 do_neon_ld_st_interleave (void)
15280 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15281 N_8
| N_16
| N_32
| N_64
);
15282 unsigned alignbits
= 0;
15284 /* The bits in this table go:
15285 0: register stride of one (0) or two (1)
15286 1,2: register list length, minus one (1, 2, 3, 4).
15287 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15288 We use -1 for invalid entries. */
15289 const int typetable
[] =
15291 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15292 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15293 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15294 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15298 if (et
.type
== NT_invtype
)
15301 if (inst
.operands
[1].immisalign
)
15302 switch (inst
.operands
[1].imm
>> 8)
15304 case 64: alignbits
= 1; break;
15306 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15307 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15308 goto bad_alignment
;
15312 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15313 goto bad_alignment
;
15318 first_error (_("bad alignment"));
15322 inst
.instruction
|= alignbits
<< 4;
15323 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15325 /* Bits [4:6] of the immediate in a list specifier encode register stride
15326 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15327 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15328 up the right value for "type" in a table based on this value and the given
15329 list style, then stick it back. */
15330 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15331 | (((inst
.instruction
>> 8) & 3) << 3);
15333 typebits
= typetable
[idx
];
15335 constraint (typebits
== -1, _("bad list type for instruction"));
15337 inst
.instruction
&= ~0xf00;
15338 inst
.instruction
|= typebits
<< 8;
15341 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15342 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15343 otherwise. The variable arguments are a list of pairs of legal (size, align)
15344 values, terminated with -1. */
15347 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15350 int result
= FAIL
, thissize
, thisalign
;
15352 if (!inst
.operands
[1].immisalign
)
15358 va_start (ap
, do_align
);
15362 thissize
= va_arg (ap
, int);
15363 if (thissize
== -1)
15365 thisalign
= va_arg (ap
, int);
15367 if (size
== thissize
&& align
== thisalign
)
15370 while (result
!= SUCCESS
);
15374 if (result
== SUCCESS
)
15377 first_error (_("unsupported alignment for instruction"));
15383 do_neon_ld_st_lane (void)
15385 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15386 int align_good
, do_align
= 0;
15387 int logsize
= neon_logbits (et
.size
);
15388 int align
= inst
.operands
[1].imm
>> 8;
15389 int n
= (inst
.instruction
>> 8) & 3;
15390 int max_el
= 64 / et
.size
;
15392 if (et
.type
== NT_invtype
)
15395 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15396 _("bad list length"));
15397 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15398 _("scalar index out of range"));
15399 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15401 _("stride of 2 unavailable when element size is 8"));
15405 case 0: /* VLD1 / VST1. */
15406 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15408 if (align_good
== FAIL
)
15412 unsigned alignbits
= 0;
15415 case 16: alignbits
= 0x1; break;
15416 case 32: alignbits
= 0x3; break;
15419 inst
.instruction
|= alignbits
<< 4;
15423 case 1: /* VLD2 / VST2. */
15424 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15426 if (align_good
== FAIL
)
15429 inst
.instruction
|= 1 << 4;
15432 case 2: /* VLD3 / VST3. */
15433 constraint (inst
.operands
[1].immisalign
,
15434 _("can't use alignment with this instruction"));
15437 case 3: /* VLD4 / VST4. */
15438 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15439 16, 64, 32, 64, 32, 128, -1);
15440 if (align_good
== FAIL
)
15444 unsigned alignbits
= 0;
15447 case 8: alignbits
= 0x1; break;
15448 case 16: alignbits
= 0x1; break;
15449 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15452 inst
.instruction
|= alignbits
<< 4;
15459 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15460 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15461 inst
.instruction
|= 1 << (4 + logsize
);
15463 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15464 inst
.instruction
|= logsize
<< 10;
15467 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15470 do_neon_ld_dup (void)
15472 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15473 int align_good
, do_align
= 0;
15475 if (et
.type
== NT_invtype
)
15478 switch ((inst
.instruction
>> 8) & 3)
15480 case 0: /* VLD1. */
15481 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15482 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15483 &do_align
, 16, 16, 32, 32, -1);
15484 if (align_good
== FAIL
)
15486 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15489 case 2: inst
.instruction
|= 1 << 5; break;
15490 default: first_error (_("bad list length")); return;
15492 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15495 case 1: /* VLD2. */
15496 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15497 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15498 if (align_good
== FAIL
)
15500 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15501 _("bad list length"));
15502 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15503 inst
.instruction
|= 1 << 5;
15504 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15507 case 2: /* VLD3. */
15508 constraint (inst
.operands
[1].immisalign
,
15509 _("can't use alignment with this instruction"));
15510 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15511 _("bad list length"));
15512 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15513 inst
.instruction
|= 1 << 5;
15514 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15517 case 3: /* VLD4. */
15519 int align
= inst
.operands
[1].imm
>> 8;
15520 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15521 16, 64, 32, 64, 32, 128, -1);
15522 if (align_good
== FAIL
)
15524 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15525 _("bad list length"));
15526 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15527 inst
.instruction
|= 1 << 5;
15528 if (et
.size
== 32 && align
== 128)
15529 inst
.instruction
|= 0x3 << 6;
15531 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15538 inst
.instruction
|= do_align
<< 4;
15541 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15542 apart from bits [11:4]. */
15545 do_neon_ldx_stx (void)
15547 if (inst
.operands
[1].isreg
)
15548 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15550 switch (NEON_LANE (inst
.operands
[0].imm
))
15552 case NEON_INTERLEAVE_LANES
:
15553 NEON_ENCODE (INTERLV
, inst
);
15554 do_neon_ld_st_interleave ();
15557 case NEON_ALL_LANES
:
15558 NEON_ENCODE (DUP
, inst
);
15563 NEON_ENCODE (LANE
, inst
);
15564 do_neon_ld_st_lane ();
15567 /* L bit comes from bit mask. */
15568 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15569 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15570 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15572 if (inst
.operands
[1].postind
)
15574 int postreg
= inst
.operands
[1].imm
& 0xf;
15575 constraint (!inst
.operands
[1].immisreg
,
15576 _("post-index must be a register"));
15577 constraint (postreg
== 0xd || postreg
== 0xf,
15578 _("bad register for post-index"));
15579 inst
.instruction
|= postreg
;
15581 else if (inst
.operands
[1].writeback
)
15583 inst
.instruction
|= 0xd;
15586 inst
.instruction
|= 0xf;
15589 inst
.instruction
|= 0xf9000000;
15591 inst
.instruction
|= 0xf4000000;
15594 /* Overall per-instruction processing. */
15596 /* We need to be able to fix up arbitrary expressions in some statements.
15597 This is so that we can handle symbols that are an arbitrary distance from
15598 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15599 which returns part of an address in a form which will be valid for
15600 a data instruction. We do this by pushing the expression into a symbol
15601 in the expr_section, and creating a fix for that. */
15604 fix_new_arm (fragS
* frag
,
15618 /* Create an absolute valued symbol, so we have something to
15619 refer to in the object file. Unfortunately for us, gas's
15620 generic expression parsing will already have folded out
15621 any use of .set foo/.type foo %function that may have
15622 been used to set type information of the target location,
15623 that's being specified symbolically. We have to presume
15624 the user knows what they are doing. */
15628 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15630 symbol
= symbol_find_or_make (name
);
15631 S_SET_SEGMENT (symbol
, absolute_section
);
15632 symbol_set_frag (symbol
, &zero_address_frag
);
15633 S_SET_VALUE (symbol
, exp
->X_add_number
);
15634 exp
->X_op
= O_symbol
;
15635 exp
->X_add_symbol
= symbol
;
15636 exp
->X_add_number
= 0;
15642 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15643 (enum bfd_reloc_code_real
) reloc
);
15647 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15648 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15652 /* Mark whether the fix is to a THUMB instruction, or an ARM
15654 new_fix
->tc_fix_data
= thumb_mode
;
15657 /* Create a frg for an instruction requiring relaxation. */
15659 output_relax_insn (void)
15665 /* The size of the instruction is unknown, so tie the debug info to the
15666 start of the instruction. */
15667 dwarf2_emit_insn (0);
15669 switch (inst
.reloc
.exp
.X_op
)
15672 sym
= inst
.reloc
.exp
.X_add_symbol
;
15673 offset
= inst
.reloc
.exp
.X_add_number
;
15677 offset
= inst
.reloc
.exp
.X_add_number
;
15680 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15684 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15685 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15686 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15689 /* Write a 32-bit thumb instruction to buf. */
15691 put_thumb32_insn (char * buf
, unsigned long insn
)
15693 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15694 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15698 output_inst (const char * str
)
15704 as_bad ("%s -- `%s'", inst
.error
, str
);
15709 output_relax_insn ();
15712 if (inst
.size
== 0)
15715 to
= frag_more (inst
.size
);
15716 /* PR 9814: Record the thumb mode into the current frag so that we know
15717 what type of NOP padding to use, if necessary. We override any previous
15718 setting so that if the mode has changed then the NOPS that we use will
15719 match the encoding of the last instruction in the frag. */
15720 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15722 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15724 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15725 put_thumb32_insn (to
, inst
.instruction
);
15727 else if (inst
.size
> INSN_SIZE
)
15729 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15730 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15731 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15734 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15736 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15737 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15738 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15741 dwarf2_emit_insn (inst
.size
);
15745 output_it_inst (int cond
, int mask
, char * to
)
15747 unsigned long instruction
= 0xbf00;
15750 instruction
|= mask
;
15751 instruction
|= cond
<< 4;
15755 to
= frag_more (2);
15757 dwarf2_emit_insn (2);
15761 md_number_to_chars (to
, instruction
, 2);
15766 /* Tag values used in struct asm_opcode's tag field. */
15769 OT_unconditional
, /* Instruction cannot be conditionalized.
15770 The ARM condition field is still 0xE. */
15771 OT_unconditionalF
, /* Instruction cannot be conditionalized
15772 and carries 0xF in its ARM condition field. */
15773 OT_csuffix
, /* Instruction takes a conditional suffix. */
15774 OT_csuffixF
, /* Some forms of the instruction take a conditional
15775 suffix, others place 0xF where the condition field
15777 OT_cinfix3
, /* Instruction takes a conditional infix,
15778 beginning at character index 3. (In
15779 unified mode, it becomes a suffix.) */
15780 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15781 tsts, cmps, cmns, and teqs. */
15782 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15783 character index 3, even in unified mode. Used for
15784 legacy instructions where suffix and infix forms
15785 may be ambiguous. */
15786 OT_csuf_or_in3
, /* Instruction takes either a conditional
15787 suffix or an infix at character index 3. */
15788 OT_odd_infix_unc
, /* This is the unconditional variant of an
15789 instruction that takes a conditional infix
15790 at an unusual position. In unified mode,
15791 this variant will accept a suffix. */
15792 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15793 are the conditional variants of instructions that
15794 take conditional infixes in unusual positions.
15795 The infix appears at character index
15796 (tag - OT_odd_infix_0). These are not accepted
15797 in unified mode. */
15800 /* Subroutine of md_assemble, responsible for looking up the primary
15801 opcode from the mnemonic the user wrote. STR points to the
15802 beginning of the mnemonic.
15804 This is not simply a hash table lookup, because of conditional
15805 variants. Most instructions have conditional variants, which are
15806 expressed with a _conditional affix_ to the mnemonic. If we were
15807 to encode each conditional variant as a literal string in the opcode
15808 table, it would have approximately 20,000 entries.
15810 Most mnemonics take this affix as a suffix, and in unified syntax,
15811 'most' is upgraded to 'all'. However, in the divided syntax, some
15812 instructions take the affix as an infix, notably the s-variants of
15813 the arithmetic instructions. Of those instructions, all but six
15814 have the infix appear after the third character of the mnemonic.
15816 Accordingly, the algorithm for looking up primary opcodes given
15819 1. Look up the identifier in the opcode table.
15820 If we find a match, go to step U.
15822 2. Look up the last two characters of the identifier in the
15823 conditions table. If we find a match, look up the first N-2
15824 characters of the identifier in the opcode table. If we
15825 find a match, go to step CE.
15827 3. Look up the fourth and fifth characters of the identifier in
15828 the conditions table. If we find a match, extract those
15829 characters from the identifier, and look up the remaining
15830 characters in the opcode table. If we find a match, go
15835 U. Examine the tag field of the opcode structure, in case this is
15836 one of the six instructions with its conditional infix in an
15837 unusual place. If it is, the tag tells us where to find the
15838 infix; look it up in the conditions table and set inst.cond
15839 accordingly. Otherwise, this is an unconditional instruction.
15840 Again set inst.cond accordingly. Return the opcode structure.
15842 CE. Examine the tag field to make sure this is an instruction that
15843 should receive a conditional suffix. If it is not, fail.
15844 Otherwise, set inst.cond from the suffix we already looked up,
15845 and return the opcode structure.
15847 CM. Examine the tag field to make sure this is an instruction that
15848 should receive a conditional infix after the third character.
15849 If it is not, fail. Otherwise, undo the edits to the current
15850 line of input and proceed as for case CE. */
15852 static const struct asm_opcode
*
15853 opcode_lookup (char **str
)
15857 const struct asm_opcode
*opcode
;
15858 const struct asm_cond
*cond
;
15861 /* Scan up to the end of the mnemonic, which must end in white space,
15862 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15863 for (base
= end
= *str
; *end
!= '\0'; end
++)
15864 if (*end
== ' ' || *end
== '.')
15870 /* Handle a possible width suffix and/or Neon type suffix. */
15875 /* The .w and .n suffixes are only valid if the unified syntax is in
15877 if (unified_syntax
&& end
[1] == 'w')
15879 else if (unified_syntax
&& end
[1] == 'n')
15884 inst
.vectype
.elems
= 0;
15886 *str
= end
+ offset
;
15888 if (end
[offset
] == '.')
15890 /* See if we have a Neon type suffix (possible in either unified or
15891 non-unified ARM syntax mode). */
15892 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15895 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15901 /* Look for unaffixed or special-case affixed mnemonic. */
15902 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15907 if (opcode
->tag
< OT_odd_infix_0
)
15909 inst
.cond
= COND_ALWAYS
;
15913 if (warn_on_deprecated
&& unified_syntax
)
15914 as_warn (_("conditional infixes are deprecated in unified syntax"));
15915 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15916 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15919 inst
.cond
= cond
->value
;
15923 /* Cannot have a conditional suffix on a mnemonic of less than two
15925 if (end
- base
< 3)
15928 /* Look for suffixed mnemonic. */
15930 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15931 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15933 if (opcode
&& cond
)
15936 switch (opcode
->tag
)
15938 case OT_cinfix3_legacy
:
15939 /* Ignore conditional suffixes matched on infix only mnemonics. */
15943 case OT_cinfix3_deprecated
:
15944 case OT_odd_infix_unc
:
15945 if (!unified_syntax
)
15947 /* else fall through */
15951 case OT_csuf_or_in3
:
15952 inst
.cond
= cond
->value
;
15955 case OT_unconditional
:
15956 case OT_unconditionalF
:
15958 inst
.cond
= cond
->value
;
15961 /* Delayed diagnostic. */
15962 inst
.error
= BAD_COND
;
15963 inst
.cond
= COND_ALWAYS
;
15972 /* Cannot have a usual-position infix on a mnemonic of less than
15973 six characters (five would be a suffix). */
15974 if (end
- base
< 6)
15977 /* Look for infixed mnemonic in the usual position. */
15979 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15983 memcpy (save
, affix
, 2);
15984 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15985 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15987 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15988 memcpy (affix
, save
, 2);
15991 && (opcode
->tag
== OT_cinfix3
15992 || opcode
->tag
== OT_cinfix3_deprecated
15993 || opcode
->tag
== OT_csuf_or_in3
15994 || opcode
->tag
== OT_cinfix3_legacy
))
15997 if (warn_on_deprecated
&& unified_syntax
15998 && (opcode
->tag
== OT_cinfix3
15999 || opcode
->tag
== OT_cinfix3_deprecated
))
16000 as_warn (_("conditional infixes are deprecated in unified syntax"));
16002 inst
.cond
= cond
->value
;
16009 /* This function generates an initial IT instruction, leaving its block
16010 virtually open for the new instructions. Eventually,
16011 the mask will be updated by now_it_add_mask () each time
16012 a new instruction needs to be included in the IT block.
16013 Finally, the block is closed with close_automatic_it_block ().
16014 The block closure can be requested either from md_assemble (),
16015 a tencode (), or due to a label hook. */
16018 new_automatic_it_block (int cond
)
16020 now_it
.state
= AUTOMATIC_IT_BLOCK
;
16021 now_it
.mask
= 0x18;
16023 now_it
.block_length
= 1;
16024 mapping_state (MAP_THUMB
);
16025 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
16028 /* Close an automatic IT block.
16029 See comments in new_automatic_it_block (). */
16032 close_automatic_it_block (void)
16034 now_it
.mask
= 0x10;
16035 now_it
.block_length
= 0;
16038 /* Update the mask of the current automatically-generated IT
16039 instruction. See comments in new_automatic_it_block (). */
16042 now_it_add_mask (int cond
)
16044 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16045 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16046 | ((bitvalue) << (nbit)))
16047 const int resulting_bit
= (cond
& 1);
16049 now_it
.mask
&= 0xf;
16050 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
16052 (5 - now_it
.block_length
));
16053 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
16055 ((5 - now_it
.block_length
) - 1) );
16056 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
16059 #undef SET_BIT_VALUE
16062 /* The IT blocks handling machinery is accessed through the these functions:
16063 it_fsm_pre_encode () from md_assemble ()
16064 set_it_insn_type () optional, from the tencode functions
16065 set_it_insn_type_last () ditto
16066 in_it_block () ditto
16067 it_fsm_post_encode () from md_assemble ()
16068 force_automatic_it_block_close () from label habdling functions
16071 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16072 initializing the IT insn type with a generic initial value depending
16073 on the inst.condition.
16074 2) During the tencode function, two things may happen:
16075 a) The tencode function overrides the IT insn type by
16076 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16077 b) The tencode function queries the IT block state by
16078 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16080 Both set_it_insn_type and in_it_block run the internal FSM state
16081 handling function (handle_it_state), because: a) setting the IT insn
16082 type may incur in an invalid state (exiting the function),
16083 and b) querying the state requires the FSM to be updated.
16084 Specifically we want to avoid creating an IT block for conditional
16085 branches, so it_fsm_pre_encode is actually a guess and we can't
16086 determine whether an IT block is required until the tencode () routine
16087 has decided what type of instruction this actually it.
16088 Because of this, if set_it_insn_type and in_it_block have to be used,
16089 set_it_insn_type has to be called first.
16091 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16092 determines the insn IT type depending on the inst.cond code.
16093 When a tencode () routine encodes an instruction that can be
16094 either outside an IT block, or, in the case of being inside, has to be
16095 the last one, set_it_insn_type_last () will determine the proper
16096 IT instruction type based on the inst.cond code. Otherwise,
16097 set_it_insn_type can be called for overriding that logic or
16098 for covering other cases.
16100 Calling handle_it_state () may not transition the IT block state to
16101 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16102 still queried. Instead, if the FSM determines that the state should
16103 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16104 after the tencode () function: that's what it_fsm_post_encode () does.
16106 Since in_it_block () calls the state handling function to get an
16107 updated state, an error may occur (due to invalid insns combination).
16108 In that case, inst.error is set.
16109 Therefore, inst.error has to be checked after the execution of
16110 the tencode () routine.
16112 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16113 any pending state change (if any) that didn't take place in
16114 handle_it_state () as explained above. */
16117 it_fsm_pre_encode (void)
16119 if (inst
.cond
!= COND_ALWAYS
)
16120 inst
.it_insn_type
= INSIDE_IT_INSN
;
16122 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16124 now_it
.state_handled
= 0;
16127 /* IT state FSM handling function. */
16130 handle_it_state (void)
16132 now_it
.state_handled
= 1;
16134 switch (now_it
.state
)
16136 case OUTSIDE_IT_BLOCK
:
16137 switch (inst
.it_insn_type
)
16139 case OUTSIDE_IT_INSN
:
16142 case INSIDE_IT_INSN
:
16143 case INSIDE_IT_LAST_INSN
:
16144 if (thumb_mode
== 0)
16147 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16148 as_tsktsk (_("Warning: conditional outside an IT block"\
16153 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16154 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16156 /* Automatically generate the IT instruction. */
16157 new_automatic_it_block (inst
.cond
);
16158 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16159 close_automatic_it_block ();
16163 inst
.error
= BAD_OUT_IT
;
16169 case IF_INSIDE_IT_LAST_INSN
:
16170 case NEUTRAL_IT_INSN
:
16174 now_it
.state
= MANUAL_IT_BLOCK
;
16175 now_it
.block_length
= 0;
16180 case AUTOMATIC_IT_BLOCK
:
16181 /* Three things may happen now:
16182 a) We should increment current it block size;
16183 b) We should close current it block (closing insn or 4 insns);
16184 c) We should close current it block and start a new one (due
16185 to incompatible conditions or
16186 4 insns-length block reached). */
16188 switch (inst
.it_insn_type
)
16190 case OUTSIDE_IT_INSN
:
16191 /* The closure of the block shall happen immediatelly,
16192 so any in_it_block () call reports the block as closed. */
16193 force_automatic_it_block_close ();
16196 case INSIDE_IT_INSN
:
16197 case INSIDE_IT_LAST_INSN
:
16198 case IF_INSIDE_IT_LAST_INSN
:
16199 now_it
.block_length
++;
16201 if (now_it
.block_length
> 4
16202 || !now_it_compatible (inst
.cond
))
16204 force_automatic_it_block_close ();
16205 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16206 new_automatic_it_block (inst
.cond
);
16210 now_it_add_mask (inst
.cond
);
16213 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16214 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16215 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16216 close_automatic_it_block ();
16219 case NEUTRAL_IT_INSN
:
16220 now_it
.block_length
++;
16222 if (now_it
.block_length
> 4)
16223 force_automatic_it_block_close ();
16225 now_it_add_mask (now_it
.cc
& 1);
16229 close_automatic_it_block ();
16230 now_it
.state
= MANUAL_IT_BLOCK
;
16235 case MANUAL_IT_BLOCK
:
16237 /* Check conditional suffixes. */
16238 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16241 now_it
.mask
&= 0x1f;
16242 is_last
= (now_it
.mask
== 0x10);
16244 switch (inst
.it_insn_type
)
16246 case OUTSIDE_IT_INSN
:
16247 inst
.error
= BAD_NOT_IT
;
16250 case INSIDE_IT_INSN
:
16251 if (cond
!= inst
.cond
)
16253 inst
.error
= BAD_IT_COND
;
16258 case INSIDE_IT_LAST_INSN
:
16259 case IF_INSIDE_IT_LAST_INSN
:
16260 if (cond
!= inst
.cond
)
16262 inst
.error
= BAD_IT_COND
;
16267 inst
.error
= BAD_BRANCH
;
16272 case NEUTRAL_IT_INSN
:
16273 /* The BKPT instruction is unconditional even in an IT block. */
16277 inst
.error
= BAD_IT_IT
;
16288 it_fsm_post_encode (void)
16292 if (!now_it
.state_handled
)
16293 handle_it_state ();
16295 is_last
= (now_it
.mask
== 0x10);
16298 now_it
.state
= OUTSIDE_IT_BLOCK
;
16304 force_automatic_it_block_close (void)
16306 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16308 close_automatic_it_block ();
16309 now_it
.state
= OUTSIDE_IT_BLOCK
;
16317 if (!now_it
.state_handled
)
16318 handle_it_state ();
16320 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16324 md_assemble (char *str
)
16327 const struct asm_opcode
* opcode
;
16329 /* Align the previous label if needed. */
16330 if (last_label_seen
!= NULL
)
16332 symbol_set_frag (last_label_seen
, frag_now
);
16333 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16334 S_SET_SEGMENT (last_label_seen
, now_seg
);
16337 memset (&inst
, '\0', sizeof (inst
));
16338 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16340 opcode
= opcode_lookup (&p
);
16343 /* It wasn't an instruction, but it might be a register alias of
16344 the form alias .req reg, or a Neon .dn/.qn directive. */
16345 if (! create_register_alias (str
, p
)
16346 && ! create_neon_reg_alias (str
, p
))
16347 as_bad (_("bad instruction `%s'"), str
);
16352 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16353 as_warn (_("s suffix on comparison instruction is deprecated"));
16355 /* The value which unconditional instructions should have in place of the
16356 condition field. */
16357 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16361 arm_feature_set variant
;
16363 variant
= cpu_variant
;
16364 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16365 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16366 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16367 /* Check that this instruction is supported for this CPU. */
16368 if (!opcode
->tvariant
16369 || (thumb_mode
== 1
16370 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16372 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16375 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16376 && opcode
->tencode
!= do_t_branch
)
16378 as_bad (_("Thumb does not support conditional execution"));
16382 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16384 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16385 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16386 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16388 /* Two things are addressed here.
16389 1) Implicit require narrow instructions on Thumb-1.
16390 This avoids relaxation accidentally introducing Thumb-2
16392 2) Reject wide instructions in non Thumb-2 cores. */
16393 if (inst
.size_req
== 0)
16395 else if (inst
.size_req
== 4)
16397 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16403 inst
.instruction
= opcode
->tvalue
;
16405 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16407 /* Prepare the it_insn_type for those encodings that don't set
16409 it_fsm_pre_encode ();
16411 opcode
->tencode ();
16413 it_fsm_post_encode ();
16416 if (!(inst
.error
|| inst
.relax
))
16418 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16419 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16420 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16422 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16427 /* Something has gone badly wrong if we try to relax a fixed size
16429 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16431 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16432 *opcode
->tvariant
);
16433 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16434 set those bits when Thumb-2 32-bit instructions are seen. ie.
16435 anything other than bl/blx and v6-M instructions.
16436 This is overly pessimistic for relaxable instructions. */
16437 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16439 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16440 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16441 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16444 check_neon_suffixes
;
16448 mapping_state (MAP_THUMB
);
16451 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16455 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16456 is_bx
= (opcode
->aencode
== do_bx
);
16458 /* Check that this instruction is supported for this CPU. */
16459 if (!(is_bx
&& fix_v4bx
)
16460 && !(opcode
->avariant
&&
16461 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16463 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16468 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16472 inst
.instruction
= opcode
->avalue
;
16473 if (opcode
->tag
== OT_unconditionalF
)
16474 inst
.instruction
|= 0xF << 28;
16476 inst
.instruction
|= inst
.cond
<< 28;
16477 inst
.size
= INSN_SIZE
;
16478 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16480 it_fsm_pre_encode ();
16481 opcode
->aencode ();
16482 it_fsm_post_encode ();
16484 /* Arm mode bx is marked as both v4T and v5 because it's still required
16485 on a hypothetical non-thumb v5 core. */
16487 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16489 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16490 *opcode
->avariant
);
16492 check_neon_suffixes
;
16496 mapping_state (MAP_ARM
);
16501 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16509 check_it_blocks_finished (void)
16514 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16515 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16516 == MANUAL_IT_BLOCK
)
16518 as_warn (_("section '%s' finished with an open IT block."),
16522 if (now_it
.state
== MANUAL_IT_BLOCK
)
16523 as_warn (_("file finished with an open IT block."));
16527 /* Various frobbings of labels and their addresses. */
16530 arm_start_line_hook (void)
16532 last_label_seen
= NULL
;
16536 arm_frob_label (symbolS
* sym
)
16538 last_label_seen
= sym
;
16540 ARM_SET_THUMB (sym
, thumb_mode
);
16542 #if defined OBJ_COFF || defined OBJ_ELF
16543 ARM_SET_INTERWORK (sym
, support_interwork
);
16546 force_automatic_it_block_close ();
16548 /* Note - do not allow local symbols (.Lxxx) to be labelled
16549 as Thumb functions. This is because these labels, whilst
16550 they exist inside Thumb code, are not the entry points for
16551 possible ARM->Thumb calls. Also, these labels can be used
16552 as part of a computed goto or switch statement. eg gcc
16553 can generate code that looks like this:
16555 ldr r2, [pc, .Laaa]
16565 The first instruction loads the address of the jump table.
16566 The second instruction converts a table index into a byte offset.
16567 The third instruction gets the jump address out of the table.
16568 The fourth instruction performs the jump.
16570 If the address stored at .Laaa is that of a symbol which has the
16571 Thumb_Func bit set, then the linker will arrange for this address
16572 to have the bottom bit set, which in turn would mean that the
16573 address computation performed by the third instruction would end
16574 up with the bottom bit set. Since the ARM is capable of unaligned
16575 word loads, the instruction would then load the incorrect address
16576 out of the jump table, and chaos would ensue. */
16577 if (label_is_thumb_function_name
16578 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16579 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16581 /* When the address of a Thumb function is taken the bottom
16582 bit of that address should be set. This will allow
16583 interworking between Arm and Thumb functions to work
16586 THUMB_SET_FUNC (sym
, 1);
16588 label_is_thumb_function_name
= FALSE
;
16591 dwarf2_emit_label (sym
);
16595 arm_data_in_code (void)
16597 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16599 *input_line_pointer
= '/';
16600 input_line_pointer
+= 5;
16601 *input_line_pointer
= 0;
16609 arm_canonicalize_symbol_name (char * name
)
16613 if (thumb_mode
&& (len
= strlen (name
)) > 5
16614 && streq (name
+ len
- 5, "/data"))
16615 *(name
+ len
- 5) = 0;
16620 /* Table of all register names defined by default. The user can
16621 define additional names with .req. Note that all register names
16622 should appear in both upper and lowercase variants. Some registers
16623 also have mixed-case names. */
16625 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16626 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16627 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16628 #define REGSET(p,t) \
16629 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16630 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16631 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16632 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16633 #define REGSETH(p,t) \
16634 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16635 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16636 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16637 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16638 #define REGSET2(p,t) \
16639 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16640 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16641 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16642 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16643 #define SPLRBANK(base,bank,t) \
16644 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16645 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16646 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16647 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16648 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16649 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16651 static const struct reg_entry reg_names
[] =
16653 /* ARM integer registers. */
16654 REGSET(r
, RN
), REGSET(R
, RN
),
16656 /* ATPCS synonyms. */
16657 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16658 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16659 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16661 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16662 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16663 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16665 /* Well-known aliases. */
16666 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16667 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16669 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16670 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16672 /* Coprocessor numbers. */
16673 REGSET(p
, CP
), REGSET(P
, CP
),
16675 /* Coprocessor register numbers. The "cr" variants are for backward
16677 REGSET(c
, CN
), REGSET(C
, CN
),
16678 REGSET(cr
, CN
), REGSET(CR
, CN
),
16680 /* ARM banked registers. */
16681 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16682 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16683 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16684 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16685 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16686 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16687 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16689 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16690 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16691 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16692 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16693 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16694 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16695 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16696 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16698 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16699 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16700 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16701 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16702 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16703 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16704 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16705 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16706 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16708 /* FPA registers. */
16709 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16710 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16712 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16713 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16715 /* VFP SP registers. */
16716 REGSET(s
,VFS
), REGSET(S
,VFS
),
16717 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16719 /* VFP DP Registers. */
16720 REGSET(d
,VFD
), REGSET(D
,VFD
),
16721 /* Extra Neon DP registers. */
16722 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16724 /* Neon QP registers. */
16725 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16727 /* VFP control registers. */
16728 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16729 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16730 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16731 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16732 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16733 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16735 /* Maverick DSP coprocessor registers. */
16736 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16737 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16739 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16740 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16741 REGDEF(dspsc
,0,DSPSC
),
16743 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16744 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16745 REGDEF(DSPSC
,0,DSPSC
),
16747 /* iWMMXt data registers - p0, c0-15. */
16748 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16750 /* iWMMXt control registers - p1, c0-3. */
16751 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16752 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16753 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16754 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16756 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16757 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16758 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16759 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16760 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16762 /* XScale accumulator registers. */
16763 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16769 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16770 within psr_required_here. */
16771 static const struct asm_psr psrs
[] =
16773 /* Backward compatibility notation. Note that "all" is no longer
16774 truly all possible PSR bits. */
16775 {"all", PSR_c
| PSR_f
},
16779 /* Individual flags. */
16785 /* Combinations of flags. */
16786 {"fs", PSR_f
| PSR_s
},
16787 {"fx", PSR_f
| PSR_x
},
16788 {"fc", PSR_f
| PSR_c
},
16789 {"sf", PSR_s
| PSR_f
},
16790 {"sx", PSR_s
| PSR_x
},
16791 {"sc", PSR_s
| PSR_c
},
16792 {"xf", PSR_x
| PSR_f
},
16793 {"xs", PSR_x
| PSR_s
},
16794 {"xc", PSR_x
| PSR_c
},
16795 {"cf", PSR_c
| PSR_f
},
16796 {"cs", PSR_c
| PSR_s
},
16797 {"cx", PSR_c
| PSR_x
},
16798 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16799 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16800 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16801 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16802 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16803 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16804 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16805 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16806 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16807 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16808 {"scf", PSR_s
| PSR_c
| PSR_f
},
16809 {"scx", PSR_s
| PSR_c
| PSR_x
},
16810 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16811 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16812 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16813 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16814 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16815 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16816 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16817 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16818 {"csf", PSR_c
| PSR_s
| PSR_f
},
16819 {"csx", PSR_c
| PSR_s
| PSR_x
},
16820 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16821 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16822 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16823 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16824 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16825 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16826 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16827 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16828 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16829 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16830 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16831 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16832 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16833 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16834 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16835 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16836 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16837 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16838 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16839 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16840 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16841 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16842 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16843 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16844 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16845 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16848 /* Table of V7M psr names. */
16849 static const struct asm_psr v7m_psrs
[] =
16851 {"apsr", 0 }, {"APSR", 0 },
16852 {"iapsr", 1 }, {"IAPSR", 1 },
16853 {"eapsr", 2 }, {"EAPSR", 2 },
16854 {"psr", 3 }, {"PSR", 3 },
16855 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16856 {"ipsr", 5 }, {"IPSR", 5 },
16857 {"epsr", 6 }, {"EPSR", 6 },
16858 {"iepsr", 7 }, {"IEPSR", 7 },
16859 {"msp", 8 }, {"MSP", 8 },
16860 {"psp", 9 }, {"PSP", 9 },
16861 {"primask", 16}, {"PRIMASK", 16},
16862 {"basepri", 17}, {"BASEPRI", 17},
16863 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16864 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16865 {"faultmask", 19}, {"FAULTMASK", 19},
16866 {"control", 20}, {"CONTROL", 20}
16869 /* Table of all shift-in-operand names. */
16870 static const struct asm_shift_name shift_names
[] =
16872 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16873 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16874 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16875 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16876 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16877 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16880 /* Table of all explicit relocation names. */
16882 static struct reloc_entry reloc_names
[] =
16884 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16885 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16886 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16887 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16888 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16889 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16890 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16891 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16892 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16893 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16894 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16895 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16896 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16897 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16898 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16899 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16900 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16901 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16905 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16906 static const struct asm_cond conds
[] =
16910 {"cs", 0x2}, {"hs", 0x2},
16911 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16925 static struct asm_barrier_opt barrier_opt_names
[] =
16927 { "sy", 0xf }, { "SY", 0xf },
16928 { "un", 0x7 }, { "UN", 0x7 },
16929 { "st", 0xe }, { "ST", 0xe },
16930 { "unst", 0x6 }, { "UNST", 0x6 },
16931 { "ish", 0xb }, { "ISH", 0xb },
16932 { "sh", 0xb }, { "SH", 0xb },
16933 { "ishst", 0xa }, { "ISHST", 0xa },
16934 { "shst", 0xa }, { "SHST", 0xa },
16935 { "nsh", 0x7 }, { "NSH", 0x7 },
16936 { "nshst", 0x6 }, { "NSHST", 0x6 },
16937 { "osh", 0x3 }, { "OSH", 0x3 },
16938 { "oshst", 0x2 }, { "OSHST", 0x2 }
16941 /* Table of ARM-format instructions. */
16943 /* Macros for gluing together operand strings. N.B. In all cases
16944 other than OPS0, the trailing OP_stop comes from default
16945 zero-initialization of the unspecified elements of the array. */
16946 #define OPS0() { OP_stop, }
16947 #define OPS1(a) { OP_##a, }
16948 #define OPS2(a,b) { OP_##a,OP_##b, }
16949 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16950 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16951 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16952 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16954 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16955 This is useful when mixing operands for ARM and THUMB, i.e. using the
16956 MIX_ARM_THUMB_OPERANDS macro.
16957 In order to use these macros, prefix the number of operands with _
16959 #define OPS_1(a) { a, }
16960 #define OPS_2(a,b) { a,b, }
16961 #define OPS_3(a,b,c) { a,b,c, }
16962 #define OPS_4(a,b,c,d) { a,b,c,d, }
16963 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16964 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16966 /* These macros abstract out the exact format of the mnemonic table and
16967 save some repeated characters. */
16969 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16970 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16971 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16972 THUMB_VARIANT, do_##ae, do_##te }
16974 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16975 a T_MNEM_xyz enumerator. */
16976 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16977 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16978 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16979 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16981 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16982 infix after the third character. */
16983 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16984 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16985 THUMB_VARIANT, do_##ae, do_##te }
16986 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16987 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16988 THUMB_VARIANT, do_##ae, do_##te }
16989 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16990 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16991 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16992 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16993 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16994 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16995 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16996 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16998 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16999 appear in the condition table. */
17000 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17001 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17002 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17004 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17005 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17006 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17007 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17008 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17009 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17010 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17011 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17012 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17013 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17014 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17015 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17016 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17017 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17018 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17019 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17020 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17021 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17022 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17023 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17025 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17026 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17027 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17028 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17030 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17031 field is still 0xE. Many of the Thumb variants can be executed
17032 conditionally, so this is checked separately. */
17033 #define TUE(mnem, op, top, nops, ops, ae, te) \
17034 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17035 THUMB_VARIANT, do_##ae, do_##te }
17037 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17038 condition code field. */
17039 #define TUF(mnem, op, top, nops, ops, ae, te) \
17040 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17041 THUMB_VARIANT, do_##ae, do_##te }
17043 /* ARM-only variants of all the above. */
17044 #define CE(mnem, op, nops, ops, ae) \
17045 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17047 #define C3(mnem, op, nops, ops, ae) \
17048 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17050 /* Legacy mnemonics that always have conditional infix after the third
17052 #define CL(mnem, op, nops, ops, ae) \
17053 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17054 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17056 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17057 #define cCE(mnem, op, nops, ops, ae) \
17058 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17060 /* Legacy coprocessor instructions where conditional infix and conditional
17061 suffix are ambiguous. For consistency this includes all FPA instructions,
17062 not just the potentially ambiguous ones. */
17063 #define cCL(mnem, op, nops, ops, ae) \
17064 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17065 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17067 /* Coprocessor, takes either a suffix or a position-3 infix
17068 (for an FPA corner case). */
17069 #define C3E(mnem, op, nops, ops, ae) \
17070 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17071 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17073 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17074 { m1 #m2 m3, OPS##nops ops, \
17075 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17076 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17078 #define CM(m1, m2, op, nops, ops, ae) \
17079 xCM_ (m1, , m2, op, nops, ops, ae), \
17080 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17081 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17082 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17083 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17084 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17085 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17086 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17087 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17088 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17089 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17090 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17091 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17092 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17093 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17094 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17095 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17096 xCM_ (m1, le, m2, op, nops, ops, ae), \
17097 xCM_ (m1, al, m2, op, nops, ops, ae)
17099 #define UE(mnem, op, nops, ops, ae) \
17100 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17102 #define UF(mnem, op, nops, ops, ae) \
17103 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17105 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17106 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17107 use the same encoding function for each. */
17108 #define NUF(mnem, op, nops, ops, enc) \
17109 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17110 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17112 /* Neon data processing, version which indirects through neon_enc_tab for
17113 the various overloaded versions of opcodes. */
17114 #define nUF(mnem, op, nops, ops, enc) \
17115 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17116 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17118 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17120 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17121 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17122 THUMB_VARIANT, do_##enc, do_##enc }
17124 #define NCE(mnem, op, nops, ops, enc) \
17125 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17127 #define NCEF(mnem, op, nops, ops, enc) \
17128 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17130 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17131 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17132 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17133 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17135 #define nCE(mnem, op, nops, ops, enc) \
17136 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17138 #define nCEF(mnem, op, nops, ops, enc) \
17139 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17143 static const struct asm_opcode insns
[] =
17145 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17146 #define THUMB_VARIANT &arm_ext_v4t
17147 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17148 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17149 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17150 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17151 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17152 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17153 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17154 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17155 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17156 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17157 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17158 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17159 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17160 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17161 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17162 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17164 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17165 for setting PSR flag bits. They are obsolete in V6 and do not
17166 have Thumb equivalents. */
17167 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17168 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17169 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17170 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17171 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17172 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17173 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17174 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17175 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17177 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17178 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17179 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17180 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17182 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17183 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17184 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17186 OP_ADDRGLDR
),ldst
, t_ldst
),
17187 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17189 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17190 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17191 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17192 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17193 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17194 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17196 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17197 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17198 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17199 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17202 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17203 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17204 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17206 /* Thumb-compatibility pseudo ops. */
17207 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17208 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17209 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17210 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17211 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17212 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17213 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17214 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17215 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17216 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17217 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17218 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17220 /* These may simplify to neg. */
17221 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17222 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17224 #undef THUMB_VARIANT
17225 #define THUMB_VARIANT & arm_ext_v6
17227 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17229 /* V1 instructions with no Thumb analogue prior to V6T2. */
17230 #undef THUMB_VARIANT
17231 #define THUMB_VARIANT & arm_ext_v6t2
17233 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17234 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17235 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17237 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17238 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17239 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17240 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17242 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17243 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17245 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17246 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17248 /* V1 instructions with no Thumb analogue at all. */
17249 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17250 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17252 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17253 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17254 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17255 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17256 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17257 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17258 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17259 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17262 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17263 #undef THUMB_VARIANT
17264 #define THUMB_VARIANT & arm_ext_v4t
17266 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17267 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17269 #undef THUMB_VARIANT
17270 #define THUMB_VARIANT & arm_ext_v6t2
17272 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17273 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17275 /* Generic coprocessor instructions. */
17276 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17277 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17278 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17279 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17280 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17281 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17282 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17285 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17287 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17288 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17291 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17292 #undef THUMB_VARIANT
17293 #define THUMB_VARIANT & arm_ext_msr
17295 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17296 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17299 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17300 #undef THUMB_VARIANT
17301 #define THUMB_VARIANT & arm_ext_v6t2
17303 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17304 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17305 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17306 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17307 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17308 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17309 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17310 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17313 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17314 #undef THUMB_VARIANT
17315 #define THUMB_VARIANT & arm_ext_v4t
17317 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17318 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17319 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17320 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17321 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17322 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17325 #define ARM_VARIANT & arm_ext_v4t_5
17327 /* ARM Architecture 4T. */
17328 /* Note: bx (and blx) are required on V5, even if the processor does
17329 not support Thumb. */
17330 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17333 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17334 #undef THUMB_VARIANT
17335 #define THUMB_VARIANT & arm_ext_v5t
17337 /* Note: blx has 2 variants; the .value coded here is for
17338 BLX(2). Only this variant has conditional execution. */
17339 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17340 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17342 #undef THUMB_VARIANT
17343 #define THUMB_VARIANT & arm_ext_v6t2
17345 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17346 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17347 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17348 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17349 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17350 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17351 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17352 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17355 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17356 #undef THUMB_VARIANT
17357 #define THUMB_VARIANT &arm_ext_v5exp
17359 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17360 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17361 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17362 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17364 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17365 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17367 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17368 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17369 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17370 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17372 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17373 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17374 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17375 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17377 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17378 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17380 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17381 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17382 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17383 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17386 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17387 #undef THUMB_VARIANT
17388 #define THUMB_VARIANT &arm_ext_v6t2
17390 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17391 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17393 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17394 ADDRGLDRS
), ldrd
, t_ldstd
),
17396 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17397 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17400 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17402 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17405 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17406 #undef THUMB_VARIANT
17407 #define THUMB_VARIANT & arm_ext_v6
17409 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17410 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17411 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17412 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17413 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17414 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17415 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17416 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17417 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17418 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17420 #undef THUMB_VARIANT
17421 #define THUMB_VARIANT & arm_ext_v6t2
17423 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17424 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17426 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17427 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17429 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17430 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17432 /* ARM V6 not included in V7M. */
17433 #undef THUMB_VARIANT
17434 #define THUMB_VARIANT & arm_ext_v6_notm
17435 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17436 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17437 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17438 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17439 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17440 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17441 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17442 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17443 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17444 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17445 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17446 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17448 /* ARM V6 not included in V7M (eg. integer SIMD). */
17449 #undef THUMB_VARIANT
17450 #define THUMB_VARIANT & arm_ext_v6_dsp
17451 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17452 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17453 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17454 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17455 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17456 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17457 /* Old name for QASX. */
17458 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17459 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17460 /* Old name for QSAX. */
17461 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17462 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17463 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17464 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17465 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17466 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17467 /* Old name for SASX. */
17468 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17469 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17470 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17471 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17472 /* Old name for SHASX. */
17473 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17474 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17475 /* Old name for SHSAX. */
17476 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17477 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17478 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17479 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17480 /* Old name for SSAX. */
17481 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17482 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17483 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17484 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17485 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17486 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17487 /* Old name for UASX. */
17488 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17489 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17490 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17491 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17492 /* Old name for UHASX. */
17493 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17494 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17495 /* Old name for UHSAX. */
17496 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17497 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17498 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17499 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17500 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17501 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17502 /* Old name for UQASX. */
17503 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17504 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17505 /* Old name for UQSAX. */
17506 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17507 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17508 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17509 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17510 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17511 /* Old name for USAX. */
17512 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17513 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17514 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17515 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17516 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17517 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17518 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17519 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17520 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17521 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17522 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17523 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17524 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17525 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17526 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17527 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17528 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17529 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17530 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17531 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17532 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17533 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17534 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17535 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17536 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17537 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17538 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17539 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17540 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17541 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17542 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17543 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17544 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17545 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17548 #define ARM_VARIANT & arm_ext_v6k
17549 #undef THUMB_VARIANT
17550 #define THUMB_VARIANT & arm_ext_v6k
17552 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17553 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17554 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17555 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17557 #undef THUMB_VARIANT
17558 #define THUMB_VARIANT & arm_ext_v6_notm
17559 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17561 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17562 RRnpcb
), strexd
, t_strexd
),
17564 #undef THUMB_VARIANT
17565 #define THUMB_VARIANT & arm_ext_v6t2
17566 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17568 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17570 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17572 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17574 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17577 #define ARM_VARIANT & arm_ext_sec
17578 #undef THUMB_VARIANT
17579 #define THUMB_VARIANT & arm_ext_sec
17581 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17584 #define ARM_VARIANT & arm_ext_virt
17585 #undef THUMB_VARIANT
17586 #define THUMB_VARIANT & arm_ext_virt
17588 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17589 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17592 #define ARM_VARIANT & arm_ext_v6t2
17593 #undef THUMB_VARIANT
17594 #define THUMB_VARIANT & arm_ext_v6t2
17596 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17597 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17598 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17599 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17601 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17602 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17603 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17604 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17606 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17607 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17608 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17609 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17611 /* Thumb-only instructions. */
17613 #define ARM_VARIANT NULL
17614 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17615 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17617 /* ARM does not really have an IT instruction, so always allow it.
17618 The opcode is copied from Thumb in order to allow warnings in
17619 -mimplicit-it=[never | arm] modes. */
17621 #define ARM_VARIANT & arm_ext_v1
17623 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17624 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17625 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17626 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17627 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17628 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17629 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17630 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17631 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17632 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17633 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17634 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17635 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17636 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17637 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17638 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17639 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17640 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17642 /* Thumb2 only instructions. */
17644 #define ARM_VARIANT NULL
17646 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17647 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17648 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17649 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17650 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17651 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17653 /* Hardware division instructions. */
17655 #define ARM_VARIANT & arm_ext_adiv
17656 #undef THUMB_VARIANT
17657 #define THUMB_VARIANT & arm_ext_div
17659 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17660 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17662 /* ARM V6M/V7 instructions. */
17664 #define ARM_VARIANT & arm_ext_barrier
17665 #undef THUMB_VARIANT
17666 #define THUMB_VARIANT & arm_ext_barrier
17668 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17669 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17670 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17672 /* ARM V7 instructions. */
17674 #define ARM_VARIANT & arm_ext_v7
17675 #undef THUMB_VARIANT
17676 #define THUMB_VARIANT & arm_ext_v7
17678 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17679 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17682 #define ARM_VARIANT & arm_ext_mp
17683 #undef THUMB_VARIANT
17684 #define THUMB_VARIANT & arm_ext_mp
17686 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17689 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17691 cCE("wfs", e200110
, 1, (RR
), rd
),
17692 cCE("rfs", e300110
, 1, (RR
), rd
),
17693 cCE("wfc", e400110
, 1, (RR
), rd
),
17694 cCE("rfc", e500110
, 1, (RR
), rd
),
17696 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17697 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17698 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17699 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17701 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17702 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17703 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17704 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17706 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17710 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17711 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17713 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17714 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17715 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17716 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17717 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17719 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17720 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17721 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17722 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17723 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17724 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17725 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17726 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17727 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17728 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17729 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17730 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17732 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17733 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17734 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17735 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17736 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17737 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17738 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17739 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17740 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17741 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17742 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17743 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17745 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17746 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17747 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17748 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17749 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17750 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17751 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17752 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17753 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17754 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17755 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17756 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17758 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17759 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17760 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17761 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17762 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17763 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17764 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17765 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17766 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17767 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17768 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17769 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17771 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17772 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17773 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17774 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17775 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17776 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17777 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17778 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17779 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17780 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17781 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17782 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17784 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17785 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17786 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17787 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17788 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17789 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17790 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17791 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17792 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17793 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17794 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17795 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17797 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17798 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17799 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17800 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17801 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17802 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17803 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17804 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17805 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17806 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17807 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17808 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17810 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17811 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17812 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17813 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17814 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17815 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17816 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17817 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17818 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17819 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17820 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17821 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17823 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17824 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17825 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17826 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17827 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17828 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17829 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17830 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17831 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17832 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17833 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17834 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17836 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17837 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17838 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17839 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17840 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17841 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17842 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17843 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17844 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17845 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17846 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17847 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17849 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17850 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17851 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17852 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17853 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17854 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17855 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17856 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17857 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17858 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17859 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17860 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17862 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17863 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17864 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17865 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17866 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17867 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17868 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17869 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17870 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17871 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17872 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17873 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17875 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17876 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17877 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17878 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17879 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17880 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17881 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17882 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17883 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17884 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17885 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17886 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17888 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17889 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17890 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17891 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17892 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17893 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17894 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17895 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17896 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17897 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17898 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17899 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17901 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17902 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17903 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17904 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17905 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17906 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17907 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17908 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17909 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17910 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17911 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17912 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17914 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17915 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17916 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17917 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17918 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17919 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17920 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17921 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17922 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17923 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17924 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17925 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17927 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17928 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17929 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17930 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17931 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17932 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17933 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17934 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17935 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17936 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17937 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17938 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17940 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17941 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17942 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17943 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17944 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17945 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17946 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17947 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17948 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17949 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17950 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17951 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17953 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17954 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17955 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17956 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17957 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17958 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17959 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17960 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17961 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17962 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17963 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17964 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17966 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17967 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17968 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17969 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17970 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17971 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17972 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17973 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17974 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17975 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17976 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17977 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17979 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17980 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17981 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17982 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17983 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17984 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17985 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17986 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17987 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17988 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17989 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17990 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17992 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17993 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17994 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17995 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17996 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17997 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17998 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17999 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18000 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18001 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18002 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18003 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18005 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18006 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18007 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18008 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18009 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18010 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18011 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18012 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18013 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18014 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18015 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18016 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18018 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18019 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18020 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18021 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18022 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18023 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18024 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18025 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18026 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18027 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18028 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18029 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18031 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18032 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18033 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18034 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18035 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18036 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18037 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18038 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18039 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18040 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18041 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18042 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18044 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18045 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18046 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18047 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18048 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18049 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18050 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18051 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18052 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18053 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18054 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18055 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18057 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18058 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18059 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18060 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18061 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18062 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18063 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18064 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18065 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18066 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18067 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18068 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18070 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18071 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18072 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18073 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18074 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18075 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18076 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18077 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18078 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18079 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18080 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18081 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18083 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18084 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18085 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18086 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18088 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
18089 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
18090 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
18091 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
18092 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
18093 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
18094 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
18095 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
18096 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
18097 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
18098 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
18099 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
18101 /* The implementation of the FIX instruction is broken on some
18102 assemblers, in that it accepts a precision specifier as well as a
18103 rounding specifier, despite the fact that this is meaningless.
18104 To be more compatible, we accept it as well, though of course it
18105 does not set any bits. */
18106 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
18107 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
18108 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
18109 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
18110 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
18111 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18112 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18113 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18114 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18115 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18116 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18117 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18118 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18120 /* Instructions that were new with the real FPA, call them V2. */
18122 #define ARM_VARIANT & fpu_fpa_ext_v2
18124 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18125 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18126 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18127 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18128 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18129 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18132 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18134 /* Moves and type conversions. */
18135 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18136 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18137 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18138 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18139 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
18140 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
18141 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18142 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18143 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18144 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18145 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18146 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18147 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18148 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
18150 /* Memory operations. */
18151 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18152 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18153 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18154 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18155 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18156 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18157 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18158 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18159 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18160 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18161 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18162 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18163 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18164 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18165 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18166 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18167 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18168 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18170 /* Monadic operations. */
18171 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18172 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18173 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18175 /* Dyadic operations. */
18176 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18177 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18178 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18179 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18180 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18181 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18182 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18183 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18184 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18187 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18188 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18189 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18190 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18192 /* Double precision load/store are still present on single precision
18193 implementations. */
18194 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18195 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18196 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18197 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18198 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18199 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18200 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18201 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18202 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18203 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18206 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18208 /* Moves and type conversions. */
18209 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18210 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18211 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18212 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18213 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18214 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18215 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18216 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18217 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18218 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18219 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18220 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18221 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18223 /* Monadic operations. */
18224 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18225 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18226 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18228 /* Dyadic operations. */
18229 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18230 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18231 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18232 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18233 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18234 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18235 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18236 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18237 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18240 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18241 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18242 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18243 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18246 #define ARM_VARIANT & fpu_vfp_ext_v2
18248 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18249 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18250 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18251 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18253 /* Instructions which may belong to either the Neon or VFP instruction sets.
18254 Individual encoder functions perform additional architecture checks. */
18256 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18257 #undef THUMB_VARIANT
18258 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18260 /* These mnemonics are unique to VFP. */
18261 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18262 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18263 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18264 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18265 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18266 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18267 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18268 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18269 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18270 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18272 /* Mnemonics shared by Neon and VFP. */
18273 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18274 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18275 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18277 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18278 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18280 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18281 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18283 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18284 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18285 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18286 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18287 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18288 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18289 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18290 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18292 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
18293 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18294 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18295 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18298 /* NOTE: All VMOV encoding is special-cased! */
18299 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18300 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18302 #undef THUMB_VARIANT
18303 #define THUMB_VARIANT & fpu_neon_ext_v1
18305 #define ARM_VARIANT & fpu_neon_ext_v1
18307 /* Data processing with three registers of the same length. */
18308 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18309 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18310 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18311 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18312 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18313 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18314 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18315 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18316 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18317 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18318 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18319 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18320 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18321 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18322 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18323 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18324 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18325 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18326 /* If not immediate, fall back to neon_dyadic_i64_su.
18327 shl_imm should accept I8 I16 I32 I64,
18328 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18329 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18330 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18331 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18332 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18333 /* Logic ops, types optional & ignored. */
18334 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18335 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18336 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18337 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18338 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18339 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18340 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18341 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18342 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18343 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18344 /* Bitfield ops, untyped. */
18345 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18346 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18347 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18348 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18349 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18350 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18351 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18352 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18353 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18354 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18355 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18356 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18357 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18358 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18359 back to neon_dyadic_if_su. */
18360 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18361 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18362 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18363 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18364 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18365 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18366 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18367 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18368 /* Comparison. Type I8 I16 I32 F32. */
18369 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18370 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18371 /* As above, D registers only. */
18372 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18373 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18374 /* Int and float variants, signedness unimportant. */
18375 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18376 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18377 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18378 /* Add/sub take types I8 I16 I32 I64 F32. */
18379 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18380 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18381 /* vtst takes sizes 8, 16, 32. */
18382 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18383 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18384 /* VMUL takes I8 I16 I32 F32 P8. */
18385 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18386 /* VQD{R}MULH takes S16 S32. */
18387 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18388 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18389 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18390 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18391 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18392 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18393 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18394 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18395 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18396 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18397 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18398 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18399 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18400 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18401 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18402 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18404 /* Two address, int/float. Types S8 S16 S32 F32. */
18405 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18406 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18408 /* Data processing with two registers and a shift amount. */
18409 /* Right shifts, and variants with rounding.
18410 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18411 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18412 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18413 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18414 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18415 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18416 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18417 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18418 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18419 /* Shift and insert. Sizes accepted 8 16 32 64. */
18420 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18421 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18422 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18423 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18424 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18425 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18426 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18427 /* Right shift immediate, saturating & narrowing, with rounding variants.
18428 Types accepted S16 S32 S64 U16 U32 U64. */
18429 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18430 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18431 /* As above, unsigned. Types accepted S16 S32 S64. */
18432 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18433 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18434 /* Right shift narrowing. Types accepted I16 I32 I64. */
18435 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18436 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18437 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18438 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18439 /* CVT with optional immediate for fixed-point variant. */
18440 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18442 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18443 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18445 /* Data processing, three registers of different lengths. */
18446 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18447 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18448 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18449 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18450 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18451 /* If not scalar, fall back to neon_dyadic_long.
18452 Vector types as above, scalar types S16 S32 U16 U32. */
18453 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18454 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18455 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18456 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18457 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18458 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18459 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18460 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18461 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18462 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18463 /* Saturating doubling multiplies. Types S16 S32. */
18464 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18465 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18466 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18467 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18468 S16 S32 U16 U32. */
18469 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18471 /* Extract. Size 8. */
18472 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18473 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18475 /* Two registers, miscellaneous. */
18476 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18477 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18478 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18479 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18480 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18481 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18482 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18483 /* Vector replicate. Sizes 8 16 32. */
18484 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18485 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18486 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18487 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18488 /* VMOVN. Types I16 I32 I64. */
18489 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18490 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18491 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18492 /* VQMOVUN. Types S16 S32 S64. */
18493 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18494 /* VZIP / VUZP. Sizes 8 16 32. */
18495 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18496 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18497 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18498 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18499 /* VQABS / VQNEG. Types S8 S16 S32. */
18500 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18501 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18502 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18503 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18504 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18505 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18506 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18507 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18508 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18509 /* Reciprocal estimates. Types U32 F32. */
18510 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18511 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18512 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18513 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18514 /* VCLS. Types S8 S16 S32. */
18515 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18516 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18517 /* VCLZ. Types I8 I16 I32. */
18518 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18519 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18520 /* VCNT. Size 8. */
18521 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18522 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18523 /* Two address, untyped. */
18524 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18525 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18526 /* VTRN. Sizes 8 16 32. */
18527 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18528 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18530 /* Table lookup. Size 8. */
18531 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18532 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18534 #undef THUMB_VARIANT
18535 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18537 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18539 /* Neon element/structure load/store. */
18540 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18541 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18542 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18543 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18544 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18545 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18546 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18547 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18549 #undef THUMB_VARIANT
18550 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18552 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18553 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18554 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18555 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18556 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18557 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18558 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18559 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18560 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18561 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18563 #undef THUMB_VARIANT
18564 #define THUMB_VARIANT & fpu_vfp_ext_v3
18566 #define ARM_VARIANT & fpu_vfp_ext_v3
18568 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18569 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18570 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18571 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18572 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18573 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18574 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18575 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18576 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18579 #define ARM_VARIANT &fpu_vfp_ext_fma
18580 #undef THUMB_VARIANT
18581 #define THUMB_VARIANT &fpu_vfp_ext_fma
18582 /* Mnemonics shared by Neon and VFP. These are included in the
18583 VFP FMA variant; NEON and VFP FMA always includes the NEON
18584 FMA instructions. */
18585 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18586 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18587 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18588 the v form should always be used. */
18589 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18590 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18591 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18592 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18593 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18594 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18596 #undef THUMB_VARIANT
18598 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18600 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18601 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18602 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18603 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18604 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18605 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18606 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18607 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18610 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18612 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18613 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18614 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18615 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18616 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18617 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18618 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18619 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18620 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18621 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18622 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18623 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18624 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18625 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18626 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18627 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18628 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18629 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18630 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18631 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18632 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18633 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18634 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18635 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18636 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18637 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18638 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18639 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18640 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18641 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18642 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18643 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18644 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18645 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18646 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18647 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18648 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18649 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18650 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18651 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18652 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18653 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18654 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18655 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18656 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18657 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18658 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18659 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18660 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18661 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18662 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18663 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18664 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18665 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18666 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18667 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18668 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18669 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18670 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18671 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18672 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18673 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18674 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18675 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18676 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18677 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18678 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18679 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18680 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18681 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18682 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18683 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18684 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18685 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18686 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18687 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18688 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18689 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18690 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18691 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18692 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18693 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18694 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18695 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18696 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18697 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18698 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18699 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18700 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18701 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18702 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18703 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18704 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18705 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18706 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18707 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18708 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18709 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18710 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18711 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18712 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18713 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18714 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18715 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18716 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18717 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18718 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18719 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18720 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18721 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18722 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18723 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18724 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18725 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18726 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18727 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18728 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18729 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18730 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18731 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18732 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18733 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18734 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18735 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18736 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18737 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18738 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18739 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18740 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18741 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18742 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18743 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18744 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18745 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18746 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18747 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18748 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18749 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18750 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18751 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18752 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18753 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18754 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18755 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18756 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18757 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18758 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18759 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18760 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18761 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18762 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18763 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18764 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18765 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18766 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18767 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18768 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18769 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18770 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18771 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18772 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18773 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18776 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18778 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18779 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18780 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18781 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18782 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18783 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18784 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18785 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18786 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18787 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18788 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18789 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18790 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18791 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18792 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18793 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18794 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18795 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18796 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18797 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18798 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18799 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18800 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18801 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18802 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18803 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18804 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18805 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18806 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18807 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18808 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18809 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18810 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18811 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18812 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18813 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18814 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18815 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18816 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18817 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18818 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18819 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18820 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18821 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18822 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18823 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18824 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18825 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18826 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18827 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18828 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18829 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18830 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18831 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18832 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18833 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18834 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18837 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18839 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18840 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18841 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18842 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18843 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18844 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18845 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18846 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18847 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18848 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18849 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18850 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18851 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18852 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18853 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18854 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18855 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18856 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18857 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18858 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18859 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18860 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18861 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18862 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18863 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18864 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18865 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18866 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18867 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18868 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18869 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18870 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18871 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18872 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18873 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18874 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18875 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18876 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18877 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18878 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18879 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18880 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18881 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18882 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18883 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18884 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18885 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18886 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18887 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18888 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18889 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18890 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18891 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18892 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18893 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18894 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18895 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18896 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18897 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18898 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18899 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18900 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18901 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18902 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18903 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18904 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18905 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18906 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18907 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18908 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18909 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18910 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18911 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18912 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18913 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18914 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18917 #undef THUMB_VARIANT
18944 /* MD interface: bits in the object file. */
18946 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18947 for use in the a.out file, and stores them in the array pointed to by buf.
18948 This knows about the endian-ness of the target machine and does
18949 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18950 2 (short) and 4 (long) Floating numbers are put out as a series of
18951 LITTLENUMS (shorts, here at least). */
18954 md_number_to_chars (char * buf
, valueT val
, int n
)
18956 if (target_big_endian
)
18957 number_to_chars_bigendian (buf
, val
, n
);
18959 number_to_chars_littleendian (buf
, val
, n
);
18963 md_chars_to_number (char * buf
, int n
)
18966 unsigned char * where
= (unsigned char *) buf
;
18968 if (target_big_endian
)
18973 result
|= (*where
++ & 255);
18981 result
|= (where
[n
] & 255);
18988 /* MD interface: Sections. */
18990 /* Estimate the size of a frag before relaxing. Assume everything fits in
18994 md_estimate_size_before_relax (fragS
* fragp
,
18995 segT segtype ATTRIBUTE_UNUSED
)
19001 /* Convert a machine dependent frag. */
19004 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
19006 unsigned long insn
;
19007 unsigned long old_op
;
19015 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19017 old_op
= bfd_get_16(abfd
, buf
);
19018 if (fragp
->fr_symbol
)
19020 exp
.X_op
= O_symbol
;
19021 exp
.X_add_symbol
= fragp
->fr_symbol
;
19025 exp
.X_op
= O_constant
;
19027 exp
.X_add_number
= fragp
->fr_offset
;
19028 opcode
= fragp
->fr_subtype
;
19031 case T_MNEM_ldr_pc
:
19032 case T_MNEM_ldr_pc2
:
19033 case T_MNEM_ldr_sp
:
19034 case T_MNEM_str_sp
:
19041 if (fragp
->fr_var
== 4)
19043 insn
= THUMB_OP32 (opcode
);
19044 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
19046 insn
|= (old_op
& 0x700) << 4;
19050 insn
|= (old_op
& 7) << 12;
19051 insn
|= (old_op
& 0x38) << 13;
19053 insn
|= 0x00000c00;
19054 put_thumb32_insn (buf
, insn
);
19055 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
19059 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
19061 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
19064 if (fragp
->fr_var
== 4)
19066 insn
= THUMB_OP32 (opcode
);
19067 insn
|= (old_op
& 0xf0) << 4;
19068 put_thumb32_insn (buf
, insn
);
19069 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
19073 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19074 exp
.X_add_number
-= 4;
19082 if (fragp
->fr_var
== 4)
19084 int r0off
= (opcode
== T_MNEM_mov
19085 || opcode
== T_MNEM_movs
) ? 0 : 8;
19086 insn
= THUMB_OP32 (opcode
);
19087 insn
= (insn
& 0xe1ffffff) | 0x10000000;
19088 insn
|= (old_op
& 0x700) << r0off
;
19089 put_thumb32_insn (buf
, insn
);
19090 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19094 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
19099 if (fragp
->fr_var
== 4)
19101 insn
= THUMB_OP32(opcode
);
19102 put_thumb32_insn (buf
, insn
);
19103 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
19106 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
19110 if (fragp
->fr_var
== 4)
19112 insn
= THUMB_OP32(opcode
);
19113 insn
|= (old_op
& 0xf00) << 14;
19114 put_thumb32_insn (buf
, insn
);
19115 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19118 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19121 case T_MNEM_add_sp
:
19122 case T_MNEM_add_pc
:
19123 case T_MNEM_inc_sp
:
19124 case T_MNEM_dec_sp
:
19125 if (fragp
->fr_var
== 4)
19127 /* ??? Choose between add and addw. */
19128 insn
= THUMB_OP32 (opcode
);
19129 insn
|= (old_op
& 0xf0) << 4;
19130 put_thumb32_insn (buf
, insn
);
19131 if (opcode
== T_MNEM_add_pc
)
19132 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
19134 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19137 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19145 if (fragp
->fr_var
== 4)
19147 insn
= THUMB_OP32 (opcode
);
19148 insn
|= (old_op
& 0xf0) << 4;
19149 insn
|= (old_op
& 0xf) << 16;
19150 put_thumb32_insn (buf
, insn
);
19151 if (insn
& (1 << 20))
19152 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19154 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19157 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19163 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
19164 (enum bfd_reloc_code_real
) reloc_type
);
19165 fixp
->fx_file
= fragp
->fr_file
;
19166 fixp
->fx_line
= fragp
->fr_line
;
19167 fragp
->fr_fix
+= fragp
->fr_var
;
19170 /* Return the size of a relaxable immediate operand instruction.
19171 SHIFT and SIZE specify the form of the allowable immediate. */
19173 relax_immediate (fragS
*fragp
, int size
, int shift
)
19179 /* ??? Should be able to do better than this. */
19180 if (fragp
->fr_symbol
)
19183 low
= (1 << shift
) - 1;
19184 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19185 offset
= fragp
->fr_offset
;
19186 /* Force misaligned offsets to 32-bit variant. */
19189 if (offset
& ~mask
)
19194 /* Get the address of a symbol during relaxation. */
19196 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19202 sym
= fragp
->fr_symbol
;
19203 sym_frag
= symbol_get_frag (sym
);
19204 know (S_GET_SEGMENT (sym
) != absolute_section
19205 || sym_frag
== &zero_address_frag
);
19206 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19208 /* If frag has yet to be reached on this pass, assume it will
19209 move by STRETCH just as we did. If this is not so, it will
19210 be because some frag between grows, and that will force
19214 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19218 /* Adjust stretch for any alignment frag. Note that if have
19219 been expanding the earlier code, the symbol may be
19220 defined in what appears to be an earlier frag. FIXME:
19221 This doesn't handle the fr_subtype field, which specifies
19222 a maximum number of bytes to skip when doing an
19224 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19226 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19229 stretch
= - ((- stretch
)
19230 & ~ ((1 << (int) f
->fr_offset
) - 1));
19232 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19244 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19247 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19252 /* Assume worst case for symbols not known to be in the same section. */
19253 if (fragp
->fr_symbol
== NULL
19254 || !S_IS_DEFINED (fragp
->fr_symbol
)
19255 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19256 || S_IS_WEAK (fragp
->fr_symbol
))
19259 val
= relaxed_symbol_addr (fragp
, stretch
);
19260 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19261 addr
= (addr
+ 4) & ~3;
19262 /* Force misaligned targets to 32-bit variant. */
19266 if (val
< 0 || val
> 1020)
19271 /* Return the size of a relaxable add/sub immediate instruction. */
19273 relax_addsub (fragS
*fragp
, asection
*sec
)
19278 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19279 op
= bfd_get_16(sec
->owner
, buf
);
19280 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19281 return relax_immediate (fragp
, 8, 0);
19283 return relax_immediate (fragp
, 3, 0);
19287 /* Return the size of a relaxable branch instruction. BITS is the
19288 size of the offset field in the narrow instruction. */
19291 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19297 /* Assume worst case for symbols not known to be in the same section. */
19298 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19299 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19300 || S_IS_WEAK (fragp
->fr_symbol
))
19304 if (S_IS_DEFINED (fragp
->fr_symbol
)
19305 && ARM_IS_FUNC (fragp
->fr_symbol
))
19308 /* PR 12532. Global symbols with default visibility might
19309 be preempted, so do not relax relocations to them. */
19310 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19311 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19315 val
= relaxed_symbol_addr (fragp
, stretch
);
19316 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19319 /* Offset is a signed value *2 */
19321 if (val
>= limit
|| val
< -limit
)
19327 /* Relax a machine dependent frag. This returns the amount by which
19328 the current size of the frag should change. */
19331 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19336 oldsize
= fragp
->fr_var
;
19337 switch (fragp
->fr_subtype
)
19339 case T_MNEM_ldr_pc2
:
19340 newsize
= relax_adr (fragp
, sec
, stretch
);
19342 case T_MNEM_ldr_pc
:
19343 case T_MNEM_ldr_sp
:
19344 case T_MNEM_str_sp
:
19345 newsize
= relax_immediate (fragp
, 8, 2);
19349 newsize
= relax_immediate (fragp
, 5, 2);
19353 newsize
= relax_immediate (fragp
, 5, 1);
19357 newsize
= relax_immediate (fragp
, 5, 0);
19360 newsize
= relax_adr (fragp
, sec
, stretch
);
19366 newsize
= relax_immediate (fragp
, 8, 0);
19369 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19372 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19374 case T_MNEM_add_sp
:
19375 case T_MNEM_add_pc
:
19376 newsize
= relax_immediate (fragp
, 8, 2);
19378 case T_MNEM_inc_sp
:
19379 case T_MNEM_dec_sp
:
19380 newsize
= relax_immediate (fragp
, 7, 2);
19386 newsize
= relax_addsub (fragp
, sec
);
19392 fragp
->fr_var
= newsize
;
19393 /* Freeze wide instructions that are at or before the same location as
19394 in the previous pass. This avoids infinite loops.
19395 Don't freeze them unconditionally because targets may be artificially
19396 misaligned by the expansion of preceding frags. */
19397 if (stretch
<= 0 && newsize
> 2)
19399 md_convert_frag (sec
->owner
, sec
, fragp
);
19403 return newsize
- oldsize
;
19406 /* Round up a section size to the appropriate boundary. */
19409 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19412 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19413 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19415 /* For a.out, force the section size to be aligned. If we don't do
19416 this, BFD will align it for us, but it will not write out the
19417 final bytes of the section. This may be a bug in BFD, but it is
19418 easier to fix it here since that is how the other a.out targets
19422 align
= bfd_get_section_alignment (stdoutput
, segment
);
19423 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19430 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19431 of an rs_align_code fragment. */
19434 arm_handle_align (fragS
* fragP
)
19436 static char const arm_noop
[2][2][4] =
19439 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19440 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19443 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19444 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19447 static char const thumb_noop
[2][2][2] =
19450 {0xc0, 0x46}, /* LE */
19451 {0x46, 0xc0}, /* BE */
19454 {0x00, 0xbf}, /* LE */
19455 {0xbf, 0x00} /* BE */
19458 static char const wide_thumb_noop
[2][4] =
19459 { /* Wide Thumb-2 */
19460 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19461 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19464 unsigned bytes
, fix
, noop_size
;
19467 const char *narrow_noop
= NULL
;
19472 if (fragP
->fr_type
!= rs_align_code
)
19475 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19476 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19479 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19480 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19482 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19484 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19486 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19488 narrow_noop
= thumb_noop
[1][target_big_endian
];
19489 noop
= wide_thumb_noop
[target_big_endian
];
19492 noop
= thumb_noop
[0][target_big_endian
];
19500 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19501 [target_big_endian
];
19508 fragP
->fr_var
= noop_size
;
19510 if (bytes
& (noop_size
- 1))
19512 fix
= bytes
& (noop_size
- 1);
19514 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19516 memset (p
, 0, fix
);
19523 if (bytes
& noop_size
)
19525 /* Insert a narrow noop. */
19526 memcpy (p
, narrow_noop
, noop_size
);
19528 bytes
-= noop_size
;
19532 /* Use wide noops for the remainder */
19536 while (bytes
>= noop_size
)
19538 memcpy (p
, noop
, noop_size
);
19540 bytes
-= noop_size
;
19544 fragP
->fr_fix
+= fix
;
19547 /* Called from md_do_align. Used to create an alignment
19548 frag in a code section. */
19551 arm_frag_align_code (int n
, int max
)
19555 /* We assume that there will never be a requirement
19556 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19557 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19562 _("alignments greater than %d bytes not supported in .text sections."),
19563 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19564 as_fatal ("%s", err_msg
);
19567 p
= frag_var (rs_align_code
,
19568 MAX_MEM_FOR_RS_ALIGN_CODE
,
19570 (relax_substateT
) max
,
19577 /* Perform target specific initialisation of a frag.
19578 Note - despite the name this initialisation is not done when the frag
19579 is created, but only when its type is assigned. A frag can be created
19580 and used a long time before its type is set, so beware of assuming that
19581 this initialisationis performed first. */
19585 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19587 /* Record whether this frag is in an ARM or a THUMB area. */
19588 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19591 #else /* OBJ_ELF is defined. */
19593 arm_init_frag (fragS
* fragP
, int max_chars
)
19595 /* If the current ARM vs THUMB mode has not already
19596 been recorded into this frag then do so now. */
19597 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19599 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19601 /* Record a mapping symbol for alignment frags. We will delete this
19602 later if the alignment ends up empty. */
19603 switch (fragP
->fr_type
)
19606 case rs_align_test
:
19608 mapping_state_2 (MAP_DATA
, max_chars
);
19610 case rs_align_code
:
19611 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19619 /* When we change sections we need to issue a new mapping symbol. */
19622 arm_elf_change_section (void)
19624 /* Link an unlinked unwind index table section to the .text section. */
19625 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19626 && elf_linked_to_section (now_seg
) == NULL
)
19627 elf_linked_to_section (now_seg
) = text_section
;
19631 arm_elf_section_type (const char * str
, size_t len
)
19633 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19634 return SHT_ARM_EXIDX
;
19639 /* Code to deal with unwinding tables. */
19641 static void add_unwind_adjustsp (offsetT
);
19643 /* Generate any deferred unwind frame offset. */
19646 flush_pending_unwind (void)
19650 offset
= unwind
.pending_offset
;
19651 unwind
.pending_offset
= 0;
19653 add_unwind_adjustsp (offset
);
19656 /* Add an opcode to this list for this function. Two-byte opcodes should
19657 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19661 add_unwind_opcode (valueT op
, int length
)
19663 /* Add any deferred stack adjustment. */
19664 if (unwind
.pending_offset
)
19665 flush_pending_unwind ();
19667 unwind
.sp_restored
= 0;
19669 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19671 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19672 if (unwind
.opcodes
)
19673 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19674 unwind
.opcode_alloc
);
19676 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19681 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19683 unwind
.opcode_count
++;
19687 /* Add unwind opcodes to adjust the stack pointer. */
19690 add_unwind_adjustsp (offsetT offset
)
19694 if (offset
> 0x200)
19696 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19701 /* Long form: 0xb2, uleb128. */
19702 /* This might not fit in a word so add the individual bytes,
19703 remembering the list is built in reverse order. */
19704 o
= (valueT
) ((offset
- 0x204) >> 2);
19706 add_unwind_opcode (0, 1);
19708 /* Calculate the uleb128 encoding of the offset. */
19712 bytes
[n
] = o
& 0x7f;
19718 /* Add the insn. */
19720 add_unwind_opcode (bytes
[n
- 1], 1);
19721 add_unwind_opcode (0xb2, 1);
19723 else if (offset
> 0x100)
19725 /* Two short opcodes. */
19726 add_unwind_opcode (0x3f, 1);
19727 op
= (offset
- 0x104) >> 2;
19728 add_unwind_opcode (op
, 1);
19730 else if (offset
> 0)
19732 /* Short opcode. */
19733 op
= (offset
- 4) >> 2;
19734 add_unwind_opcode (op
, 1);
19736 else if (offset
< 0)
19739 while (offset
> 0x100)
19741 add_unwind_opcode (0x7f, 1);
19744 op
= ((offset
- 4) >> 2) | 0x40;
19745 add_unwind_opcode (op
, 1);
19749 /* Finish the list of unwind opcodes for this function. */
19751 finish_unwind_opcodes (void)
19755 if (unwind
.fp_used
)
19757 /* Adjust sp as necessary. */
19758 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19759 flush_pending_unwind ();
19761 /* After restoring sp from the frame pointer. */
19762 op
= 0x90 | unwind
.fp_reg
;
19763 add_unwind_opcode (op
, 1);
19766 flush_pending_unwind ();
19770 /* Start an exception table entry. If idx is nonzero this is an index table
19774 start_unwind_section (const segT text_seg
, int idx
)
19776 const char * text_name
;
19777 const char * prefix
;
19778 const char * prefix_once
;
19779 const char * group_name
;
19783 size_t sec_name_len
;
19790 prefix
= ELF_STRING_ARM_unwind
;
19791 prefix_once
= ELF_STRING_ARM_unwind_once
;
19792 type
= SHT_ARM_EXIDX
;
19796 prefix
= ELF_STRING_ARM_unwind_info
;
19797 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19798 type
= SHT_PROGBITS
;
19801 text_name
= segment_name (text_seg
);
19802 if (streq (text_name
, ".text"))
19805 if (strncmp (text_name
, ".gnu.linkonce.t.",
19806 strlen (".gnu.linkonce.t.")) == 0)
19808 prefix
= prefix_once
;
19809 text_name
+= strlen (".gnu.linkonce.t.");
19812 prefix_len
= strlen (prefix
);
19813 text_len
= strlen (text_name
);
19814 sec_name_len
= prefix_len
+ text_len
;
19815 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19816 memcpy (sec_name
, prefix
, prefix_len
);
19817 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19818 sec_name
[prefix_len
+ text_len
] = '\0';
19824 /* Handle COMDAT group. */
19825 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19827 group_name
= elf_group_name (text_seg
);
19828 if (group_name
== NULL
)
19830 as_bad (_("Group section `%s' has no group signature"),
19831 segment_name (text_seg
));
19832 ignore_rest_of_line ();
19835 flags
|= SHF_GROUP
;
19839 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19841 /* Set the section link for index tables. */
19843 elf_linked_to_section (now_seg
) = text_seg
;
19847 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19848 personality routine data. Returns zero, or the index table value for
19849 and inline entry. */
19852 create_unwind_entry (int have_data
)
19857 /* The current word of data. */
19859 /* The number of bytes left in this word. */
19862 finish_unwind_opcodes ();
19864 /* Remember the current text section. */
19865 unwind
.saved_seg
= now_seg
;
19866 unwind
.saved_subseg
= now_subseg
;
19868 start_unwind_section (now_seg
, 0);
19870 if (unwind
.personality_routine
== NULL
)
19872 if (unwind
.personality_index
== -2)
19875 as_bad (_("handlerdata in cantunwind frame"));
19876 return 1; /* EXIDX_CANTUNWIND. */
19879 /* Use a default personality routine if none is specified. */
19880 if (unwind
.personality_index
== -1)
19882 if (unwind
.opcode_count
> 3)
19883 unwind
.personality_index
= 1;
19885 unwind
.personality_index
= 0;
19888 /* Space for the personality routine entry. */
19889 if (unwind
.personality_index
== 0)
19891 if (unwind
.opcode_count
> 3)
19892 as_bad (_("too many unwind opcodes for personality routine 0"));
19896 /* All the data is inline in the index table. */
19899 while (unwind
.opcode_count
> 0)
19901 unwind
.opcode_count
--;
19902 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19906 /* Pad with "finish" opcodes. */
19908 data
= (data
<< 8) | 0xb0;
19915 /* We get two opcodes "free" in the first word. */
19916 size
= unwind
.opcode_count
- 2;
19919 /* An extra byte is required for the opcode count. */
19920 size
= unwind
.opcode_count
+ 1;
19922 size
= (size
+ 3) >> 2;
19924 as_bad (_("too many unwind opcodes"));
19926 frag_align (2, 0, 0);
19927 record_alignment (now_seg
, 2);
19928 unwind
.table_entry
= expr_build_dot ();
19930 /* Allocate the table entry. */
19931 ptr
= frag_more ((size
<< 2) + 4);
19932 where
= frag_now_fix () - ((size
<< 2) + 4);
19934 switch (unwind
.personality_index
)
19937 /* ??? Should this be a PLT generating relocation? */
19938 /* Custom personality routine. */
19939 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19940 BFD_RELOC_ARM_PREL31
);
19945 /* Set the first byte to the number of additional words. */
19950 /* ABI defined personality routines. */
19952 /* Three opcodes bytes are packed into the first word. */
19959 /* The size and first two opcode bytes go in the first word. */
19960 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19965 /* Should never happen. */
19969 /* Pack the opcodes into words (MSB first), reversing the list at the same
19971 while (unwind
.opcode_count
> 0)
19975 md_number_to_chars (ptr
, data
, 4);
19980 unwind
.opcode_count
--;
19982 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19985 /* Finish off the last word. */
19988 /* Pad with "finish" opcodes. */
19990 data
= (data
<< 8) | 0xb0;
19992 md_number_to_chars (ptr
, data
, 4);
19997 /* Add an empty descriptor if there is no user-specified data. */
19998 ptr
= frag_more (4);
19999 md_number_to_chars (ptr
, 0, 4);
20006 /* Initialize the DWARF-2 unwind information for this procedure. */
20009 tc_arm_frame_initial_instructions (void)
20011 cfi_add_CFA_def_cfa (REG_SP
, 0);
20013 #endif /* OBJ_ELF */
20015 /* Convert REGNAME to a DWARF-2 register number. */
20018 tc_arm_regname_to_dw2regnum (char *regname
)
20020 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
20030 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
20034 exp
.X_op
= O_secrel
;
20035 exp
.X_add_symbol
= symbol
;
20036 exp
.X_add_number
= 0;
20037 emit_expr (&exp
, size
);
20041 /* MD interface: Symbol and relocation handling. */
20043 /* Return the address within the segment that a PC-relative fixup is
20044 relative to. For ARM, PC-relative fixups applied to instructions
20045 are generally relative to the location of the fixup plus 8 bytes.
20046 Thumb branches are offset by 4, and Thumb loads relative to PC
20047 require special handling. */
20050 md_pcrel_from_section (fixS
* fixP
, segT seg
)
20052 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20054 /* If this is pc-relative and we are going to emit a relocation
20055 then we just want to put out any pipeline compensation that the linker
20056 will need. Otherwise we want to use the calculated base.
20057 For WinCE we skip the bias for externals as well, since this
20058 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20060 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20061 || (arm_force_relocation (fixP
)
20063 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20069 switch (fixP
->fx_r_type
)
20071 /* PC relative addressing on the Thumb is slightly odd as the
20072 bottom two bits of the PC are forced to zero for the
20073 calculation. This happens *after* application of the
20074 pipeline offset. However, Thumb adrl already adjusts for
20075 this, so we need not do it again. */
20076 case BFD_RELOC_ARM_THUMB_ADD
:
20079 case BFD_RELOC_ARM_THUMB_OFFSET
:
20080 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20081 case BFD_RELOC_ARM_T32_ADD_PC12
:
20082 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20083 return (base
+ 4) & ~3;
20085 /* Thumb branches are simply offset by +4. */
20086 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20087 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20088 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20089 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20090 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20093 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20095 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20096 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20097 && ARM_IS_FUNC (fixP
->fx_addsy
)
20098 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20099 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20102 /* BLX is like branches above, but forces the low two bits of PC to
20104 case BFD_RELOC_THUMB_PCREL_BLX
:
20106 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20107 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20108 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20109 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20110 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20111 return (base
+ 4) & ~3;
20113 /* ARM mode branches are offset by +8. However, the Windows CE
20114 loader expects the relocation not to take this into account. */
20115 case BFD_RELOC_ARM_PCREL_BLX
:
20117 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20118 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20119 && ARM_IS_FUNC (fixP
->fx_addsy
)
20120 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20121 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20124 case BFD_RELOC_ARM_PCREL_CALL
:
20126 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20127 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20128 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20129 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20130 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20133 case BFD_RELOC_ARM_PCREL_BRANCH
:
20134 case BFD_RELOC_ARM_PCREL_JUMP
:
20135 case BFD_RELOC_ARM_PLT32
:
20137 /* When handling fixups immediately, because we have already
20138 discovered the value of a symbol, or the address of the frag involved
20139 we must account for the offset by +8, as the OS loader will never see the reloc.
20140 see fixup_segment() in write.c
20141 The S_IS_EXTERNAL test handles the case of global symbols.
20142 Those need the calculated base, not just the pipe compensation the linker will need. */
20144 && fixP
->fx_addsy
!= NULL
20145 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20146 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
20154 /* ARM mode loads relative to PC are also offset by +8. Unlike
20155 branches, the Windows CE loader *does* expect the relocation
20156 to take this into account. */
20157 case BFD_RELOC_ARM_OFFSET_IMM
:
20158 case BFD_RELOC_ARM_OFFSET_IMM8
:
20159 case BFD_RELOC_ARM_HWLITERAL
:
20160 case BFD_RELOC_ARM_LITERAL
:
20161 case BFD_RELOC_ARM_CP_OFF_IMM
:
20165 /* Other PC-relative relocations are un-offset. */
20171 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20172 Otherwise we have no need to default values of symbols. */
20175 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20178 if (name
[0] == '_' && name
[1] == 'G'
20179 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20183 if (symbol_find (name
))
20184 as_bad (_("GOT already in the symbol table"));
20186 GOT_symbol
= symbol_new (name
, undefined_section
,
20187 (valueT
) 0, & zero_address_frag
);
20197 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20198 computed as two separate immediate values, added together. We
20199 already know that this value cannot be computed by just one ARM
20202 static unsigned int
20203 validate_immediate_twopart (unsigned int val
,
20204 unsigned int * highpart
)
20209 for (i
= 0; i
< 32; i
+= 2)
20210 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20216 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20218 else if (a
& 0xff0000)
20220 if (a
& 0xff000000)
20222 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20226 gas_assert (a
& 0xff000000);
20227 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20230 return (a
& 0xff) | (i
<< 7);
20237 validate_offset_imm (unsigned int val
, int hwse
)
20239 if ((hwse
&& val
> 255) || val
> 4095)
20244 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20245 negative immediate constant by altering the instruction. A bit of
20250 by inverting the second operand, and
20253 by negating the second operand. */
20256 negate_data_op (unsigned long * instruction
,
20257 unsigned long value
)
20260 unsigned long negated
, inverted
;
20262 negated
= encode_arm_immediate (-value
);
20263 inverted
= encode_arm_immediate (~value
);
20265 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20268 /* First negates. */
20269 case OPCODE_SUB
: /* ADD <-> SUB */
20270 new_inst
= OPCODE_ADD
;
20275 new_inst
= OPCODE_SUB
;
20279 case OPCODE_CMP
: /* CMP <-> CMN */
20280 new_inst
= OPCODE_CMN
;
20285 new_inst
= OPCODE_CMP
;
20289 /* Now Inverted ops. */
20290 case OPCODE_MOV
: /* MOV <-> MVN */
20291 new_inst
= OPCODE_MVN
;
20296 new_inst
= OPCODE_MOV
;
20300 case OPCODE_AND
: /* AND <-> BIC */
20301 new_inst
= OPCODE_BIC
;
20306 new_inst
= OPCODE_AND
;
20310 case OPCODE_ADC
: /* ADC <-> SBC */
20311 new_inst
= OPCODE_SBC
;
20316 new_inst
= OPCODE_ADC
;
20320 /* We cannot do anything. */
20325 if (value
== (unsigned) FAIL
)
20328 *instruction
&= OPCODE_MASK
;
20329 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20333 /* Like negate_data_op, but for Thumb-2. */
20335 static unsigned int
20336 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20340 unsigned int negated
, inverted
;
20342 negated
= encode_thumb32_immediate (-value
);
20343 inverted
= encode_thumb32_immediate (~value
);
20345 rd
= (*instruction
>> 8) & 0xf;
20346 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20349 /* ADD <-> SUB. Includes CMP <-> CMN. */
20350 case T2_OPCODE_SUB
:
20351 new_inst
= T2_OPCODE_ADD
;
20355 case T2_OPCODE_ADD
:
20356 new_inst
= T2_OPCODE_SUB
;
20360 /* ORR <-> ORN. Includes MOV <-> MVN. */
20361 case T2_OPCODE_ORR
:
20362 new_inst
= T2_OPCODE_ORN
;
20366 case T2_OPCODE_ORN
:
20367 new_inst
= T2_OPCODE_ORR
;
20371 /* AND <-> BIC. TST has no inverted equivalent. */
20372 case T2_OPCODE_AND
:
20373 new_inst
= T2_OPCODE_BIC
;
20380 case T2_OPCODE_BIC
:
20381 new_inst
= T2_OPCODE_AND
;
20386 case T2_OPCODE_ADC
:
20387 new_inst
= T2_OPCODE_SBC
;
20391 case T2_OPCODE_SBC
:
20392 new_inst
= T2_OPCODE_ADC
;
20396 /* We cannot do anything. */
20401 if (value
== (unsigned int)FAIL
)
20404 *instruction
&= T2_OPCODE_MASK
;
20405 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20409 /* Read a 32-bit thumb instruction from buf. */
20410 static unsigned long
20411 get_thumb32_insn (char * buf
)
20413 unsigned long insn
;
20414 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20415 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20421 /* We usually want to set the low bit on the address of thumb function
20422 symbols. In particular .word foo - . should have the low bit set.
20423 Generic code tries to fold the difference of two symbols to
20424 a constant. Prevent this and force a relocation when the first symbols
20425 is a thumb function. */
20428 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20430 if (op
== O_subtract
20431 && l
->X_op
== O_symbol
20432 && r
->X_op
== O_symbol
20433 && THUMB_IS_FUNC (l
->X_add_symbol
))
20435 l
->X_op
= O_subtract
;
20436 l
->X_op_symbol
= r
->X_add_symbol
;
20437 l
->X_add_number
-= r
->X_add_number
;
20441 /* Process as normal. */
20445 /* Encode Thumb2 unconditional branches and calls. The encoding
20446 for the 2 are identical for the immediate values. */
20449 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20451 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20454 addressT S
, I1
, I2
, lo
, hi
;
20456 S
= (value
>> 24) & 0x01;
20457 I1
= (value
>> 23) & 0x01;
20458 I2
= (value
>> 22) & 0x01;
20459 hi
= (value
>> 12) & 0x3ff;
20460 lo
= (value
>> 1) & 0x7ff;
20461 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20462 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20463 newval
|= (S
<< 10) | hi
;
20464 newval2
&= ~T2I1I2MASK
;
20465 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20466 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20467 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20471 md_apply_fix (fixS
* fixP
,
20475 offsetT value
= * valP
;
20477 unsigned int newimm
;
20478 unsigned long temp
;
20480 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20482 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20484 /* Note whether this will delete the relocation. */
20486 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20489 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20490 consistency with the behaviour on 32-bit hosts. Remember value
20492 value
&= 0xffffffff;
20493 value
^= 0x80000000;
20494 value
-= 0x80000000;
20497 fixP
->fx_addnumber
= value
;
20499 /* Same treatment for fixP->fx_offset. */
20500 fixP
->fx_offset
&= 0xffffffff;
20501 fixP
->fx_offset
^= 0x80000000;
20502 fixP
->fx_offset
-= 0x80000000;
20504 switch (fixP
->fx_r_type
)
20506 case BFD_RELOC_NONE
:
20507 /* This will need to go in the object file. */
20511 case BFD_RELOC_ARM_IMMEDIATE
:
20512 /* We claim that this fixup has been processed here,
20513 even if in fact we generate an error because we do
20514 not have a reloc for it, so tc_gen_reloc will reject it. */
20517 if (fixP
->fx_addsy
)
20519 const char *msg
= 0;
20521 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20522 msg
= _("undefined symbol %s used as an immediate value");
20523 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20524 msg
= _("symbol %s is in a different section");
20525 else if (S_IS_WEAK (fixP
->fx_addsy
))
20526 msg
= _("symbol %s is weak and may be overridden later");
20530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20531 msg
, S_GET_NAME (fixP
->fx_addsy
));
20536 newimm
= encode_arm_immediate (value
);
20537 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20539 /* If the instruction will fail, see if we can fix things up by
20540 changing the opcode. */
20541 if (newimm
== (unsigned int) FAIL
20542 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20545 _("invalid constant (%lx) after fixup"),
20546 (unsigned long) value
);
20550 newimm
|= (temp
& 0xfffff000);
20551 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20554 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20556 unsigned int highpart
= 0;
20557 unsigned int newinsn
= 0xe1a00000; /* nop. */
20559 if (fixP
->fx_addsy
)
20561 const char *msg
= 0;
20563 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20564 msg
= _("undefined symbol %s used as an immediate value");
20565 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20566 msg
= _("symbol %s is in a different section");
20567 else if (S_IS_WEAK (fixP
->fx_addsy
))
20568 msg
= _("symbol %s is weak and may be overridden later");
20572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20573 msg
, S_GET_NAME (fixP
->fx_addsy
));
20578 newimm
= encode_arm_immediate (value
);
20579 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20581 /* If the instruction will fail, see if we can fix things up by
20582 changing the opcode. */
20583 if (newimm
== (unsigned int) FAIL
20584 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20586 /* No ? OK - try using two ADD instructions to generate
20588 newimm
= validate_immediate_twopart (value
, & highpart
);
20590 /* Yes - then make sure that the second instruction is
20592 if (newimm
!= (unsigned int) FAIL
)
20594 /* Still No ? Try using a negated value. */
20595 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20596 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20597 /* Otherwise - give up. */
20600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20601 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20606 /* Replace the first operand in the 2nd instruction (which
20607 is the PC) with the destination register. We have
20608 already added in the PC in the first instruction and we
20609 do not want to do it again. */
20610 newinsn
&= ~ 0xf0000;
20611 newinsn
|= ((newinsn
& 0x0f000) << 4);
20614 newimm
|= (temp
& 0xfffff000);
20615 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20617 highpart
|= (newinsn
& 0xfffff000);
20618 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20622 case BFD_RELOC_ARM_OFFSET_IMM
:
20623 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20626 case BFD_RELOC_ARM_LITERAL
:
20632 if (validate_offset_imm (value
, 0) == FAIL
)
20634 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20636 _("invalid literal constant: pool needs to be closer"));
20638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20639 _("bad immediate value for offset (%ld)"),
20644 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20646 newval
&= 0xfffff000;
20649 newval
&= 0xff7ff000;
20650 newval
|= value
| (sign
? INDEX_UP
: 0);
20652 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20655 case BFD_RELOC_ARM_OFFSET_IMM8
:
20656 case BFD_RELOC_ARM_HWLITERAL
:
20662 if (validate_offset_imm (value
, 1) == FAIL
)
20664 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20666 _("invalid literal constant: pool needs to be closer"));
20668 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20673 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20675 newval
&= 0xfffff0f0;
20678 newval
&= 0xff7ff0f0;
20679 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20681 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20684 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20685 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20687 _("bad immediate value for offset (%ld)"), (long) value
);
20690 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20692 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20695 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20696 /* This is a complicated relocation used for all varieties of Thumb32
20697 load/store instruction with immediate offset:
20699 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20700 *4, optional writeback(W)
20701 (doubleword load/store)
20703 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20704 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20705 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20706 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20707 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20709 Uppercase letters indicate bits that are already encoded at
20710 this point. Lowercase letters are our problem. For the
20711 second block of instructions, the secondary opcode nybble
20712 (bits 8..11) is present, and bit 23 is zero, even if this is
20713 a PC-relative operation. */
20714 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20716 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20718 if ((newval
& 0xf0000000) == 0xe0000000)
20720 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20722 newval
|= (1 << 23);
20725 if (value
% 4 != 0)
20727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20728 _("offset not a multiple of 4"));
20734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20735 _("offset out of range"));
20740 else if ((newval
& 0x000f0000) == 0x000f0000)
20742 /* PC-relative, 12-bit offset. */
20744 newval
|= (1 << 23);
20749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20750 _("offset out of range"));
20755 else if ((newval
& 0x00000100) == 0x00000100)
20757 /* Writeback: 8-bit, +/- offset. */
20759 newval
|= (1 << 9);
20764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20765 _("offset out of range"));
20770 else if ((newval
& 0x00000f00) == 0x00000e00)
20772 /* T-instruction: positive 8-bit offset. */
20773 if (value
< 0 || value
> 0xff)
20775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20776 _("offset out of range"));
20784 /* Positive 12-bit or negative 8-bit offset. */
20788 newval
|= (1 << 23);
20798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20799 _("offset out of range"));
20806 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20807 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20810 case BFD_RELOC_ARM_SHIFT_IMM
:
20811 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20812 if (((unsigned long) value
) > 32
20814 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20817 _("shift expression is too large"));
20822 /* Shifts of zero must be done as lsl. */
20824 else if (value
== 32)
20826 newval
&= 0xfffff07f;
20827 newval
|= (value
& 0x1f) << 7;
20828 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20831 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20832 case BFD_RELOC_ARM_T32_ADD_IMM
:
20833 case BFD_RELOC_ARM_T32_IMM12
:
20834 case BFD_RELOC_ARM_T32_ADD_PC12
:
20835 /* We claim that this fixup has been processed here,
20836 even if in fact we generate an error because we do
20837 not have a reloc for it, so tc_gen_reloc will reject it. */
20841 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20844 _("undefined symbol %s used as an immediate value"),
20845 S_GET_NAME (fixP
->fx_addsy
));
20849 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20851 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20854 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20855 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20857 newimm
= encode_thumb32_immediate (value
);
20858 if (newimm
== (unsigned int) FAIL
)
20859 newimm
= thumb32_negate_data_op (&newval
, value
);
20861 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20862 && newimm
== (unsigned int) FAIL
)
20864 /* Turn add/sum into addw/subw. */
20865 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20866 newval
= (newval
& 0xfeffffff) | 0x02000000;
20867 /* No flat 12-bit imm encoding for addsw/subsw. */
20868 if ((newval
& 0x00100000) == 0)
20870 /* 12 bit immediate for addw/subw. */
20874 newval
^= 0x00a00000;
20877 newimm
= (unsigned int) FAIL
;
20883 if (newimm
== (unsigned int)FAIL
)
20885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20886 _("invalid constant (%lx) after fixup"),
20887 (unsigned long) value
);
20891 newval
|= (newimm
& 0x800) << 15;
20892 newval
|= (newimm
& 0x700) << 4;
20893 newval
|= (newimm
& 0x0ff);
20895 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20896 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20899 case BFD_RELOC_ARM_SMC
:
20900 if (((unsigned long) value
) > 0xffff)
20901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20902 _("invalid smc expression"));
20903 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20904 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20905 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20908 case BFD_RELOC_ARM_HVC
:
20909 if (((unsigned long) value
) > 0xffff)
20910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20911 _("invalid hvc expression"));
20912 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20913 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20914 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20917 case BFD_RELOC_ARM_SWI
:
20918 if (fixP
->tc_fix_data
!= 0)
20920 if (((unsigned long) value
) > 0xff)
20921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20922 _("invalid swi expression"));
20923 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20925 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20929 if (((unsigned long) value
) > 0x00ffffff)
20930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20931 _("invalid swi expression"));
20932 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20934 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20938 case BFD_RELOC_ARM_MULTI
:
20939 if (((unsigned long) value
) > 0xffff)
20940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20941 _("invalid expression in load/store multiple"));
20942 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20943 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20947 case BFD_RELOC_ARM_PCREL_CALL
:
20949 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20951 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20952 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20953 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20954 /* Flip the bl to blx. This is a simple flip
20955 bit here because we generate PCREL_CALL for
20956 unconditional bls. */
20958 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20959 newval
= newval
| 0x10000000;
20960 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20966 goto arm_branch_common
;
20968 case BFD_RELOC_ARM_PCREL_JUMP
:
20969 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20971 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20972 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20973 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20975 /* This would map to a bl<cond>, b<cond>,
20976 b<always> to a Thumb function. We
20977 need to force a relocation for this particular
20979 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20983 case BFD_RELOC_ARM_PLT32
:
20985 case BFD_RELOC_ARM_PCREL_BRANCH
:
20987 goto arm_branch_common
;
20989 case BFD_RELOC_ARM_PCREL_BLX
:
20992 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20994 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20995 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20996 && ARM_IS_FUNC (fixP
->fx_addsy
))
20998 /* Flip the blx to a bl and warn. */
20999 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21000 newval
= 0xeb000000;
21001 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21002 _("blx to '%s' an ARM ISA state function changed to bl"),
21004 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21010 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21011 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
21015 /* We are going to store value (shifted right by two) in the
21016 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21017 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21018 also be be clear. */
21020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21021 _("misaligned branch destination"));
21022 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
21023 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
21024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21026 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21028 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21029 newval
|= (value
>> 2) & 0x00ffffff;
21030 /* Set the H bit on BLX instructions. */
21034 newval
|= 0x01000000;
21036 newval
&= ~0x01000000;
21038 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21042 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
21043 /* CBZ can only branch forward. */
21045 /* Attempts to use CBZ to branch to the next instruction
21046 (which, strictly speaking, are prohibited) will be turned into
21049 FIXME: It may be better to remove the instruction completely and
21050 perform relaxation. */
21053 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21054 newval
= 0xbf00; /* NOP encoding T1 */
21055 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21062 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21064 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21065 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
21066 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21071 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
21072 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
21073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21075 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21077 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21078 newval
|= (value
& 0x1ff) >> 1;
21079 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21083 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
21084 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
21085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21087 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21089 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21090 newval
|= (value
& 0xfff) >> 1;
21091 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21095 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21097 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21098 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21099 && ARM_IS_FUNC (fixP
->fx_addsy
)
21100 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21102 /* Force a relocation for a branch 20 bits wide. */
21105 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
21106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21107 _("conditional branch out of range"));
21109 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21112 addressT S
, J1
, J2
, lo
, hi
;
21114 S
= (value
& 0x00100000) >> 20;
21115 J2
= (value
& 0x00080000) >> 19;
21116 J1
= (value
& 0x00040000) >> 18;
21117 hi
= (value
& 0x0003f000) >> 12;
21118 lo
= (value
& 0x00000ffe) >> 1;
21120 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21121 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21122 newval
|= (S
<< 10) | hi
;
21123 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
21124 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21125 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21129 case BFD_RELOC_THUMB_PCREL_BLX
:
21130 /* If there is a blx from a thumb state function to
21131 another thumb function flip this to a bl and warn
21135 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21136 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21137 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21139 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21140 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21141 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21143 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21144 newval
= newval
| 0x1000;
21145 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21146 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21151 goto thumb_bl_common
;
21153 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21154 /* A bl from Thumb state ISA to an internal ARM state function
21155 is converted to a blx. */
21157 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21158 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21159 && ARM_IS_FUNC (fixP
->fx_addsy
)
21160 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21162 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21163 newval
= newval
& ~0x1000;
21164 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21165 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
21172 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
21173 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21174 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21177 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21178 /* For a BLX instruction, make sure that the relocation is rounded up
21179 to a word boundary. This follows the semantics of the instruction
21180 which specifies that bit 1 of the target address will come from bit
21181 1 of the base address. */
21182 value
= (value
+ 1) & ~ 1;
21184 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21186 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21188 else if ((value
& ~0x1ffffff)
21189 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21191 _("Thumb2 branch out of range"));
21194 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21195 encode_thumb2_b_bl_offset (buf
, value
);
21199 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21200 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
21201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21203 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21204 encode_thumb2_b_bl_offset (buf
, value
);
21209 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21210 md_number_to_chars (buf
, value
, 1);
21214 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21215 md_number_to_chars (buf
, value
, 2);
21219 case BFD_RELOC_ARM_TLS_CALL
:
21220 case BFD_RELOC_ARM_THM_TLS_CALL
:
21221 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21222 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21223 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21226 case BFD_RELOC_ARM_TLS_GOTDESC
:
21227 case BFD_RELOC_ARM_TLS_GD32
:
21228 case BFD_RELOC_ARM_TLS_LE32
:
21229 case BFD_RELOC_ARM_TLS_IE32
:
21230 case BFD_RELOC_ARM_TLS_LDM32
:
21231 case BFD_RELOC_ARM_TLS_LDO32
:
21232 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21235 case BFD_RELOC_ARM_GOT32
:
21236 case BFD_RELOC_ARM_GOTOFF
:
21237 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21238 md_number_to_chars (buf
, 0, 4);
21241 case BFD_RELOC_ARM_GOT_PREL
:
21242 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21243 md_number_to_chars (buf
, value
, 4);
21246 case BFD_RELOC_ARM_TARGET2
:
21247 /* TARGET2 is not partial-inplace, so we need to write the
21248 addend here for REL targets, because it won't be written out
21249 during reloc processing later. */
21250 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21251 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21255 case BFD_RELOC_RVA
:
21257 case BFD_RELOC_ARM_TARGET1
:
21258 case BFD_RELOC_ARM_ROSEGREL32
:
21259 case BFD_RELOC_ARM_SBREL32
:
21260 case BFD_RELOC_32_PCREL
:
21262 case BFD_RELOC_32_SECREL
:
21264 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21266 /* For WinCE we only do this for pcrel fixups. */
21267 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21269 md_number_to_chars (buf
, value
, 4);
21273 case BFD_RELOC_ARM_PREL31
:
21274 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21276 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21277 if ((value
^ (value
>> 1)) & 0x40000000)
21279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21280 _("rel31 relocation overflow"));
21282 newval
|= value
& 0x7fffffff;
21283 md_number_to_chars (buf
, newval
, 4);
21288 case BFD_RELOC_ARM_CP_OFF_IMM
:
21289 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21290 if (value
< -1023 || value
> 1023 || (value
& 3))
21291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21292 _("co-processor offset out of range"));
21297 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21298 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21299 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21301 newval
= get_thumb32_insn (buf
);
21303 newval
&= 0xffffff00;
21306 newval
&= 0xff7fff00;
21307 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21309 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21310 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21311 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21313 put_thumb32_insn (buf
, newval
);
21316 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21317 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21318 if (value
< -255 || value
> 255)
21319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21320 _("co-processor offset out of range"));
21322 goto cp_off_common
;
21324 case BFD_RELOC_ARM_THUMB_OFFSET
:
21325 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21326 /* Exactly what ranges, and where the offset is inserted depends
21327 on the type of instruction, we can establish this from the
21329 switch (newval
>> 12)
21331 case 4: /* PC load. */
21332 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21333 forced to zero for these loads; md_pcrel_from has already
21334 compensated for this. */
21336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21337 _("invalid offset, target not word aligned (0x%08lX)"),
21338 (((unsigned long) fixP
->fx_frag
->fr_address
21339 + (unsigned long) fixP
->fx_where
) & ~3)
21340 + (unsigned long) value
);
21342 if (value
& ~0x3fc)
21343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21344 _("invalid offset, value too big (0x%08lX)"),
21347 newval
|= value
>> 2;
21350 case 9: /* SP load/store. */
21351 if (value
& ~0x3fc)
21352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21353 _("invalid offset, value too big (0x%08lX)"),
21355 newval
|= value
>> 2;
21358 case 6: /* Word load/store. */
21360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21361 _("invalid offset, value too big (0x%08lX)"),
21363 newval
|= value
<< 4; /* 6 - 2. */
21366 case 7: /* Byte load/store. */
21368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21369 _("invalid offset, value too big (0x%08lX)"),
21371 newval
|= value
<< 6;
21374 case 8: /* Halfword load/store. */
21376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21377 _("invalid offset, value too big (0x%08lX)"),
21379 newval
|= value
<< 5; /* 6 - 1. */
21383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21384 "Unable to process relocation for thumb opcode: %lx",
21385 (unsigned long) newval
);
21388 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21391 case BFD_RELOC_ARM_THUMB_ADD
:
21392 /* This is a complicated relocation, since we use it for all of
21393 the following immediate relocations:
21397 9bit ADD/SUB SP word-aligned
21398 10bit ADD PC/SP word-aligned
21400 The type of instruction being processed is encoded in the
21407 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21409 int rd
= (newval
>> 4) & 0xf;
21410 int rs
= newval
& 0xf;
21411 int subtract
= !!(newval
& 0x8000);
21413 /* Check for HI regs, only very restricted cases allowed:
21414 Adjusting SP, and using PC or SP to get an address. */
21415 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21416 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21417 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21418 _("invalid Hi register with immediate"));
21420 /* If value is negative, choose the opposite instruction. */
21424 subtract
= !subtract
;
21426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21427 _("immediate value out of range"));
21432 if (value
& ~0x1fc)
21433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21434 _("invalid immediate for stack address calculation"));
21435 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21436 newval
|= value
>> 2;
21438 else if (rs
== REG_PC
|| rs
== REG_SP
)
21440 if (subtract
|| value
& ~0x3fc)
21441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21442 _("invalid immediate for address calculation (value = 0x%08lX)"),
21443 (unsigned long) value
);
21444 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21446 newval
|= value
>> 2;
21451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21452 _("immediate value out of range"));
21453 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21454 newval
|= (rd
<< 8) | value
;
21459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21460 _("immediate value out of range"));
21461 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21462 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21465 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21468 case BFD_RELOC_ARM_THUMB_IMM
:
21469 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21470 if (value
< 0 || value
> 255)
21471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21472 _("invalid immediate: %ld is out of range"),
21475 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21478 case BFD_RELOC_ARM_THUMB_SHIFT
:
21479 /* 5bit shift value (0..32). LSL cannot take 32. */
21480 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21481 temp
= newval
& 0xf800;
21482 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21484 _("invalid shift value: %ld"), (long) value
);
21485 /* Shifts of zero must be encoded as LSL. */
21487 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21488 /* Shifts of 32 are encoded as zero. */
21489 else if (value
== 32)
21491 newval
|= value
<< 6;
21492 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21495 case BFD_RELOC_VTABLE_INHERIT
:
21496 case BFD_RELOC_VTABLE_ENTRY
:
21500 case BFD_RELOC_ARM_MOVW
:
21501 case BFD_RELOC_ARM_MOVT
:
21502 case BFD_RELOC_ARM_THUMB_MOVW
:
21503 case BFD_RELOC_ARM_THUMB_MOVT
:
21504 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21506 /* REL format relocations are limited to a 16-bit addend. */
21507 if (!fixP
->fx_done
)
21509 if (value
< -0x8000 || value
> 0x7fff)
21510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21511 _("offset out of range"));
21513 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21514 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21519 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21520 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21522 newval
= get_thumb32_insn (buf
);
21523 newval
&= 0xfbf08f00;
21524 newval
|= (value
& 0xf000) << 4;
21525 newval
|= (value
& 0x0800) << 15;
21526 newval
|= (value
& 0x0700) << 4;
21527 newval
|= (value
& 0x00ff);
21528 put_thumb32_insn (buf
, newval
);
21532 newval
= md_chars_to_number (buf
, 4);
21533 newval
&= 0xfff0f000;
21534 newval
|= value
& 0x0fff;
21535 newval
|= (value
& 0xf000) << 4;
21536 md_number_to_chars (buf
, newval
, 4);
21541 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21542 case BFD_RELOC_ARM_ALU_PC_G0
:
21543 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21544 case BFD_RELOC_ARM_ALU_PC_G1
:
21545 case BFD_RELOC_ARM_ALU_PC_G2
:
21546 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21547 case BFD_RELOC_ARM_ALU_SB_G0
:
21548 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21549 case BFD_RELOC_ARM_ALU_SB_G1
:
21550 case BFD_RELOC_ARM_ALU_SB_G2
:
21551 gas_assert (!fixP
->fx_done
);
21552 if (!seg
->use_rela_p
)
21555 bfd_vma encoded_addend
;
21556 bfd_vma addend_abs
= abs (value
);
21558 /* Check that the absolute value of the addend can be
21559 expressed as an 8-bit constant plus a rotation. */
21560 encoded_addend
= encode_arm_immediate (addend_abs
);
21561 if (encoded_addend
== (unsigned int) FAIL
)
21562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21563 _("the offset 0x%08lX is not representable"),
21564 (unsigned long) addend_abs
);
21566 /* Extract the instruction. */
21567 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21569 /* If the addend is positive, use an ADD instruction.
21570 Otherwise use a SUB. Take care not to destroy the S bit. */
21571 insn
&= 0xff1fffff;
21577 /* Place the encoded addend into the first 12 bits of the
21579 insn
&= 0xfffff000;
21580 insn
|= encoded_addend
;
21582 /* Update the instruction. */
21583 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21587 case BFD_RELOC_ARM_LDR_PC_G0
:
21588 case BFD_RELOC_ARM_LDR_PC_G1
:
21589 case BFD_RELOC_ARM_LDR_PC_G2
:
21590 case BFD_RELOC_ARM_LDR_SB_G0
:
21591 case BFD_RELOC_ARM_LDR_SB_G1
:
21592 case BFD_RELOC_ARM_LDR_SB_G2
:
21593 gas_assert (!fixP
->fx_done
);
21594 if (!seg
->use_rela_p
)
21597 bfd_vma addend_abs
= abs (value
);
21599 /* Check that the absolute value of the addend can be
21600 encoded in 12 bits. */
21601 if (addend_abs
>= 0x1000)
21602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21603 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21604 (unsigned long) addend_abs
);
21606 /* Extract the instruction. */
21607 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21609 /* If the addend is negative, clear bit 23 of the instruction.
21610 Otherwise set it. */
21612 insn
&= ~(1 << 23);
21616 /* Place the absolute value of the addend into the first 12 bits
21617 of the instruction. */
21618 insn
&= 0xfffff000;
21619 insn
|= addend_abs
;
21621 /* Update the instruction. */
21622 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21626 case BFD_RELOC_ARM_LDRS_PC_G0
:
21627 case BFD_RELOC_ARM_LDRS_PC_G1
:
21628 case BFD_RELOC_ARM_LDRS_PC_G2
:
21629 case BFD_RELOC_ARM_LDRS_SB_G0
:
21630 case BFD_RELOC_ARM_LDRS_SB_G1
:
21631 case BFD_RELOC_ARM_LDRS_SB_G2
:
21632 gas_assert (!fixP
->fx_done
);
21633 if (!seg
->use_rela_p
)
21636 bfd_vma addend_abs
= abs (value
);
21638 /* Check that the absolute value of the addend can be
21639 encoded in 8 bits. */
21640 if (addend_abs
>= 0x100)
21641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21642 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21643 (unsigned long) addend_abs
);
21645 /* Extract the instruction. */
21646 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21648 /* If the addend is negative, clear bit 23 of the instruction.
21649 Otherwise set it. */
21651 insn
&= ~(1 << 23);
21655 /* Place the first four bits of the absolute value of the addend
21656 into the first 4 bits of the instruction, and the remaining
21657 four into bits 8 .. 11. */
21658 insn
&= 0xfffff0f0;
21659 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21661 /* Update the instruction. */
21662 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21666 case BFD_RELOC_ARM_LDC_PC_G0
:
21667 case BFD_RELOC_ARM_LDC_PC_G1
:
21668 case BFD_RELOC_ARM_LDC_PC_G2
:
21669 case BFD_RELOC_ARM_LDC_SB_G0
:
21670 case BFD_RELOC_ARM_LDC_SB_G1
:
21671 case BFD_RELOC_ARM_LDC_SB_G2
:
21672 gas_assert (!fixP
->fx_done
);
21673 if (!seg
->use_rela_p
)
21676 bfd_vma addend_abs
= abs (value
);
21678 /* Check that the absolute value of the addend is a multiple of
21679 four and, when divided by four, fits in 8 bits. */
21680 if (addend_abs
& 0x3)
21681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21682 _("bad offset 0x%08lX (must be word-aligned)"),
21683 (unsigned long) addend_abs
);
21685 if ((addend_abs
>> 2) > 0xff)
21686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21687 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21688 (unsigned long) addend_abs
);
21690 /* Extract the instruction. */
21691 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21693 /* If the addend is negative, clear bit 23 of the instruction.
21694 Otherwise set it. */
21696 insn
&= ~(1 << 23);
21700 /* Place the addend (divided by four) into the first eight
21701 bits of the instruction. */
21702 insn
&= 0xfffffff0;
21703 insn
|= addend_abs
>> 2;
21705 /* Update the instruction. */
21706 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21710 case BFD_RELOC_ARM_V4BX
:
21711 /* This will need to go in the object file. */
21715 case BFD_RELOC_UNUSED
:
21717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21718 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21722 /* Translate internal representation of relocation info to BFD target
21726 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21729 bfd_reloc_code_real_type code
;
21731 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21733 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21734 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21735 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21737 if (fixp
->fx_pcrel
)
21739 if (section
->use_rela_p
)
21740 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21742 fixp
->fx_offset
= reloc
->address
;
21744 reloc
->addend
= fixp
->fx_offset
;
21746 switch (fixp
->fx_r_type
)
21749 if (fixp
->fx_pcrel
)
21751 code
= BFD_RELOC_8_PCREL
;
21756 if (fixp
->fx_pcrel
)
21758 code
= BFD_RELOC_16_PCREL
;
21763 if (fixp
->fx_pcrel
)
21765 code
= BFD_RELOC_32_PCREL
;
21769 case BFD_RELOC_ARM_MOVW
:
21770 if (fixp
->fx_pcrel
)
21772 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21776 case BFD_RELOC_ARM_MOVT
:
21777 if (fixp
->fx_pcrel
)
21779 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21783 case BFD_RELOC_ARM_THUMB_MOVW
:
21784 if (fixp
->fx_pcrel
)
21786 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21790 case BFD_RELOC_ARM_THUMB_MOVT
:
21791 if (fixp
->fx_pcrel
)
21793 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21797 case BFD_RELOC_NONE
:
21798 case BFD_RELOC_ARM_PCREL_BRANCH
:
21799 case BFD_RELOC_ARM_PCREL_BLX
:
21800 case BFD_RELOC_RVA
:
21801 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21802 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21803 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21804 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21805 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21806 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21807 case BFD_RELOC_VTABLE_ENTRY
:
21808 case BFD_RELOC_VTABLE_INHERIT
:
21810 case BFD_RELOC_32_SECREL
:
21812 code
= fixp
->fx_r_type
;
21815 case BFD_RELOC_THUMB_PCREL_BLX
:
21817 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21818 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21821 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21824 case BFD_RELOC_ARM_LITERAL
:
21825 case BFD_RELOC_ARM_HWLITERAL
:
21826 /* If this is called then the a literal has
21827 been referenced across a section boundary. */
21828 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21829 _("literal referenced across section boundary"));
21833 case BFD_RELOC_ARM_TLS_CALL
:
21834 case BFD_RELOC_ARM_THM_TLS_CALL
:
21835 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21836 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21837 case BFD_RELOC_ARM_GOT32
:
21838 case BFD_RELOC_ARM_GOTOFF
:
21839 case BFD_RELOC_ARM_GOT_PREL
:
21840 case BFD_RELOC_ARM_PLT32
:
21841 case BFD_RELOC_ARM_TARGET1
:
21842 case BFD_RELOC_ARM_ROSEGREL32
:
21843 case BFD_RELOC_ARM_SBREL32
:
21844 case BFD_RELOC_ARM_PREL31
:
21845 case BFD_RELOC_ARM_TARGET2
:
21846 case BFD_RELOC_ARM_TLS_LE32
:
21847 case BFD_RELOC_ARM_TLS_LDO32
:
21848 case BFD_RELOC_ARM_PCREL_CALL
:
21849 case BFD_RELOC_ARM_PCREL_JUMP
:
21850 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21851 case BFD_RELOC_ARM_ALU_PC_G0
:
21852 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21853 case BFD_RELOC_ARM_ALU_PC_G1
:
21854 case BFD_RELOC_ARM_ALU_PC_G2
:
21855 case BFD_RELOC_ARM_LDR_PC_G0
:
21856 case BFD_RELOC_ARM_LDR_PC_G1
:
21857 case BFD_RELOC_ARM_LDR_PC_G2
:
21858 case BFD_RELOC_ARM_LDRS_PC_G0
:
21859 case BFD_RELOC_ARM_LDRS_PC_G1
:
21860 case BFD_RELOC_ARM_LDRS_PC_G2
:
21861 case BFD_RELOC_ARM_LDC_PC_G0
:
21862 case BFD_RELOC_ARM_LDC_PC_G1
:
21863 case BFD_RELOC_ARM_LDC_PC_G2
:
21864 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21865 case BFD_RELOC_ARM_ALU_SB_G0
:
21866 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21867 case BFD_RELOC_ARM_ALU_SB_G1
:
21868 case BFD_RELOC_ARM_ALU_SB_G2
:
21869 case BFD_RELOC_ARM_LDR_SB_G0
:
21870 case BFD_RELOC_ARM_LDR_SB_G1
:
21871 case BFD_RELOC_ARM_LDR_SB_G2
:
21872 case BFD_RELOC_ARM_LDRS_SB_G0
:
21873 case BFD_RELOC_ARM_LDRS_SB_G1
:
21874 case BFD_RELOC_ARM_LDRS_SB_G2
:
21875 case BFD_RELOC_ARM_LDC_SB_G0
:
21876 case BFD_RELOC_ARM_LDC_SB_G1
:
21877 case BFD_RELOC_ARM_LDC_SB_G2
:
21878 case BFD_RELOC_ARM_V4BX
:
21879 code
= fixp
->fx_r_type
;
21882 case BFD_RELOC_ARM_TLS_GOTDESC
:
21883 case BFD_RELOC_ARM_TLS_GD32
:
21884 case BFD_RELOC_ARM_TLS_IE32
:
21885 case BFD_RELOC_ARM_TLS_LDM32
:
21886 /* BFD will include the symbol's address in the addend.
21887 But we don't want that, so subtract it out again here. */
21888 if (!S_IS_COMMON (fixp
->fx_addsy
))
21889 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21890 code
= fixp
->fx_r_type
;
21894 case BFD_RELOC_ARM_IMMEDIATE
:
21895 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21896 _("internal relocation (type: IMMEDIATE) not fixed up"));
21899 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21900 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21901 _("ADRL used for a symbol not defined in the same file"));
21904 case BFD_RELOC_ARM_OFFSET_IMM
:
21905 if (section
->use_rela_p
)
21907 code
= fixp
->fx_r_type
;
21911 if (fixp
->fx_addsy
!= NULL
21912 && !S_IS_DEFINED (fixp
->fx_addsy
)
21913 && S_IS_LOCAL (fixp
->fx_addsy
))
21915 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21916 _("undefined local label `%s'"),
21917 S_GET_NAME (fixp
->fx_addsy
));
21921 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21922 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21929 switch (fixp
->fx_r_type
)
21931 case BFD_RELOC_NONE
: type
= "NONE"; break;
21932 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21933 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21934 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21935 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21936 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21937 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21938 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21939 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21940 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21941 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21942 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21943 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21944 default: type
= _("<unknown>"); break;
21946 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21947 _("cannot represent %s relocation in this object file format"),
21954 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21956 && fixp
->fx_addsy
== GOT_symbol
)
21958 code
= BFD_RELOC_ARM_GOTPC
;
21959 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21963 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21965 if (reloc
->howto
== NULL
)
21967 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21968 _("cannot represent %s relocation in this object file format"),
21969 bfd_get_reloc_code_name (code
));
21973 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21974 vtable entry to be used in the relocation's section offset. */
21975 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21976 reloc
->address
= fixp
->fx_offset
;
21981 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21984 cons_fix_new_arm (fragS
* frag
,
21989 bfd_reloc_code_real_type type
;
21993 FIXME: @@ Should look at CPU word size. */
21997 type
= BFD_RELOC_8
;
22000 type
= BFD_RELOC_16
;
22004 type
= BFD_RELOC_32
;
22007 type
= BFD_RELOC_64
;
22012 if (exp
->X_op
== O_secrel
)
22014 exp
->X_op
= O_symbol
;
22015 type
= BFD_RELOC_32_SECREL
;
22019 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
22022 #if defined (OBJ_COFF)
22024 arm_validate_fix (fixS
* fixP
)
22026 /* If the destination of the branch is a defined symbol which does not have
22027 the THUMB_FUNC attribute, then we must be calling a function which has
22028 the (interfacearm) attribute. We look for the Thumb entry point to that
22029 function and change the branch to refer to that function instead. */
22030 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
22031 && fixP
->fx_addsy
!= NULL
22032 && S_IS_DEFINED (fixP
->fx_addsy
)
22033 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
22035 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
22042 arm_force_relocation (struct fix
* fixp
)
22044 #if defined (OBJ_COFF) && defined (TE_PE)
22045 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
22049 /* In case we have a call or a branch to a function in ARM ISA mode from
22050 a thumb function or vice-versa force the relocation. These relocations
22051 are cleared off for some cores that might have blx and simple transformations
22055 switch (fixp
->fx_r_type
)
22057 case BFD_RELOC_ARM_PCREL_JUMP
:
22058 case BFD_RELOC_ARM_PCREL_CALL
:
22059 case BFD_RELOC_THUMB_PCREL_BLX
:
22060 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
22064 case BFD_RELOC_ARM_PCREL_BLX
:
22065 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22066 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22067 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22068 if (ARM_IS_FUNC (fixp
->fx_addsy
))
22077 /* Resolve these relocations even if the symbol is extern or weak.
22078 Technically this is probably wrong due to symbol preemption.
22079 In practice these relocations do not have enough range to be useful
22080 at dynamic link time, and some code (e.g. in the Linux kernel)
22081 expects these references to be resolved. */
22082 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
22083 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
22084 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
22085 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
22086 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22087 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
22088 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
22089 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
22090 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22091 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
22092 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
22093 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
22094 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
22095 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
22098 /* Always leave these relocations for the linker. */
22099 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22100 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22101 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22104 /* Always generate relocations against function symbols. */
22105 if (fixp
->fx_r_type
== BFD_RELOC_32
22107 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22110 return generic_force_reloc (fixp
);
22113 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22114 /* Relocations against function names must be left unadjusted,
22115 so that the linker can use this information to generate interworking
22116 stubs. The MIPS version of this function
22117 also prevents relocations that are mips-16 specific, but I do not
22118 know why it does this.
22121 There is one other problem that ought to be addressed here, but
22122 which currently is not: Taking the address of a label (rather
22123 than a function) and then later jumping to that address. Such
22124 addresses also ought to have their bottom bit set (assuming that
22125 they reside in Thumb code), but at the moment they will not. */
22128 arm_fix_adjustable (fixS
* fixP
)
22130 if (fixP
->fx_addsy
== NULL
)
22133 /* Preserve relocations against symbols with function type. */
22134 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
22137 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
22138 && fixP
->fx_subsy
== NULL
)
22141 /* We need the symbol name for the VTABLE entries. */
22142 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
22143 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22146 /* Don't allow symbols to be discarded on GOT related relocs. */
22147 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
22148 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
22149 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
22150 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
22151 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
22152 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
22153 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
22154 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
22155 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
22156 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
22157 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
22158 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
22159 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
22160 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
22163 /* Similarly for group relocations. */
22164 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22165 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22166 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22169 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22170 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
22171 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22172 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
22173 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
22174 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22175 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
22176 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
22177 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22182 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22187 elf32_arm_target_format (void)
22190 return (target_big_endian
22191 ? "elf32-bigarm-symbian"
22192 : "elf32-littlearm-symbian");
22193 #elif defined (TE_VXWORKS)
22194 return (target_big_endian
22195 ? "elf32-bigarm-vxworks"
22196 : "elf32-littlearm-vxworks");
22198 if (target_big_endian
)
22199 return "elf32-bigarm";
22201 return "elf32-littlearm";
22206 armelf_frob_symbol (symbolS
* symp
,
22209 elf_frob_symbol (symp
, puntp
);
22213 /* MD interface: Finalization. */
22218 literal_pool
* pool
;
22220 /* Ensure that all the IT blocks are properly closed. */
22221 check_it_blocks_finished ();
22223 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22225 /* Put it at the end of the relevant section. */
22226 subseg_set (pool
->section
, pool
->sub_section
);
22228 arm_elf_change_section ();
22235 /* Remove any excess mapping symbols generated for alignment frags in
22236 SEC. We may have created a mapping symbol before a zero byte
22237 alignment; remove it if there's a mapping symbol after the
22240 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22241 void *dummy ATTRIBUTE_UNUSED
)
22243 segment_info_type
*seginfo
= seg_info (sec
);
22246 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22249 for (fragp
= seginfo
->frchainP
->frch_root
;
22251 fragp
= fragp
->fr_next
)
22253 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22254 fragS
*next
= fragp
->fr_next
;
22256 /* Variable-sized frags have been converted to fixed size by
22257 this point. But if this was variable-sized to start with,
22258 there will be a fixed-size frag after it. So don't handle
22260 if (sym
== NULL
|| next
== NULL
)
22263 if (S_GET_VALUE (sym
) < next
->fr_address
)
22264 /* Not at the end of this frag. */
22266 know (S_GET_VALUE (sym
) == next
->fr_address
);
22270 if (next
->tc_frag_data
.first_map
!= NULL
)
22272 /* Next frag starts with a mapping symbol. Discard this
22274 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22278 if (next
->fr_next
== NULL
)
22280 /* This mapping symbol is at the end of the section. Discard
22282 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22283 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22287 /* As long as we have empty frags without any mapping symbols,
22289 /* If the next frag is non-empty and does not start with a
22290 mapping symbol, then this mapping symbol is required. */
22291 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22294 next
= next
->fr_next
;
22296 while (next
!= NULL
);
22301 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22305 arm_adjust_symtab (void)
22310 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22312 if (ARM_IS_THUMB (sym
))
22314 if (THUMB_IS_FUNC (sym
))
22316 /* Mark the symbol as a Thumb function. */
22317 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22318 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22319 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22321 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22322 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22324 as_bad (_("%s: unexpected function type: %d"),
22325 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22327 else switch (S_GET_STORAGE_CLASS (sym
))
22330 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22333 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22336 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22344 if (ARM_IS_INTERWORK (sym
))
22345 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22352 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22354 if (ARM_IS_THUMB (sym
))
22356 elf_symbol_type
* elf_sym
;
22358 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22359 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22361 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22362 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22364 /* If it's a .thumb_func, declare it as so,
22365 otherwise tag label as .code 16. */
22366 if (THUMB_IS_FUNC (sym
))
22367 elf_sym
->internal_elf_sym
.st_target_internal
22368 = ST_BRANCH_TO_THUMB
;
22369 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22370 elf_sym
->internal_elf_sym
.st_info
=
22371 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22376 /* Remove any overlapping mapping symbols generated by alignment frags. */
22377 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22378 /* Now do generic ELF adjustments. */
22379 elf_adjust_symtab ();
22383 /* MD interface: Initialization. */
22386 set_constant_flonums (void)
22390 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22391 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22395 /* Auto-select Thumb mode if it's the only available instruction set for the
22396 given architecture. */
22399 autoselect_thumb_from_cpu_variant (void)
22401 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22402 opcode_select (16);
22411 if ( (arm_ops_hsh
= hash_new ()) == NULL
22412 || (arm_cond_hsh
= hash_new ()) == NULL
22413 || (arm_shift_hsh
= hash_new ()) == NULL
22414 || (arm_psr_hsh
= hash_new ()) == NULL
22415 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22416 || (arm_reg_hsh
= hash_new ()) == NULL
22417 || (arm_reloc_hsh
= hash_new ()) == NULL
22418 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22419 as_fatal (_("virtual memory exhausted"));
22421 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22422 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22423 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22424 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22425 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22426 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22427 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22428 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22429 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22430 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22431 (void *) (v7m_psrs
+ i
));
22432 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22433 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22435 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22437 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22438 (void *) (barrier_opt_names
+ i
));
22440 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
22442 struct reloc_entry
* entry
= reloc_names
+ i
;
22444 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
22445 /* This makes encode_branch() use the EABI versions of this relocation. */
22446 entry
->reloc
= BFD_RELOC_UNUSED
;
22448 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
22452 set_constant_flonums ();
22454 /* Set the cpu variant based on the command-line options. We prefer
22455 -mcpu= over -march= if both are set (as for GCC); and we prefer
22456 -mfpu= over any other way of setting the floating point unit.
22457 Use of legacy options with new options are faulted. */
22460 if (mcpu_cpu_opt
|| march_cpu_opt
)
22461 as_bad (_("use of old and new-style options to set CPU type"));
22463 mcpu_cpu_opt
= legacy_cpu
;
22465 else if (!mcpu_cpu_opt
)
22466 mcpu_cpu_opt
= march_cpu_opt
;
22471 as_bad (_("use of old and new-style options to set FPU type"));
22473 mfpu_opt
= legacy_fpu
;
22475 else if (!mfpu_opt
)
22477 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22478 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22479 /* Some environments specify a default FPU. If they don't, infer it
22480 from the processor. */
22482 mfpu_opt
= mcpu_fpu_opt
;
22484 mfpu_opt
= march_fpu_opt
;
22486 mfpu_opt
= &fpu_default
;
22492 if (mcpu_cpu_opt
!= NULL
)
22493 mfpu_opt
= &fpu_default
;
22494 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22495 mfpu_opt
= &fpu_arch_vfp_v2
;
22497 mfpu_opt
= &fpu_arch_fpa
;
22503 mcpu_cpu_opt
= &cpu_default
;
22504 selected_cpu
= cpu_default
;
22508 selected_cpu
= *mcpu_cpu_opt
;
22510 mcpu_cpu_opt
= &arm_arch_any
;
22513 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22515 autoselect_thumb_from_cpu_variant ();
22517 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22519 #if defined OBJ_COFF || defined OBJ_ELF
22521 unsigned int flags
= 0;
22523 #if defined OBJ_ELF
22524 flags
= meabi_flags
;
22526 switch (meabi_flags
)
22528 case EF_ARM_EABI_UNKNOWN
:
22530 /* Set the flags in the private structure. */
22531 if (uses_apcs_26
) flags
|= F_APCS26
;
22532 if (support_interwork
) flags
|= F_INTERWORK
;
22533 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22534 if (pic_code
) flags
|= F_PIC
;
22535 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22536 flags
|= F_SOFT_FLOAT
;
22538 switch (mfloat_abi_opt
)
22540 case ARM_FLOAT_ABI_SOFT
:
22541 case ARM_FLOAT_ABI_SOFTFP
:
22542 flags
|= F_SOFT_FLOAT
;
22545 case ARM_FLOAT_ABI_HARD
:
22546 if (flags
& F_SOFT_FLOAT
)
22547 as_bad (_("hard-float conflicts with specified fpu"));
22551 /* Using pure-endian doubles (even if soft-float). */
22552 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22553 flags
|= F_VFP_FLOAT
;
22555 #if defined OBJ_ELF
22556 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22557 flags
|= EF_ARM_MAVERICK_FLOAT
;
22560 case EF_ARM_EABI_VER4
:
22561 case EF_ARM_EABI_VER5
:
22562 /* No additional flags to set. */
22569 bfd_set_private_flags (stdoutput
, flags
);
22571 /* We have run out flags in the COFF header to encode the
22572 status of ATPCS support, so instead we create a dummy,
22573 empty, debug section called .arm.atpcs. */
22578 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22582 bfd_set_section_flags
22583 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22584 bfd_set_section_size (stdoutput
, sec
, 0);
22585 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22591 /* Record the CPU type as well. */
22592 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22593 mach
= bfd_mach_arm_iWMMXt2
;
22594 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22595 mach
= bfd_mach_arm_iWMMXt
;
22596 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22597 mach
= bfd_mach_arm_XScale
;
22598 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22599 mach
= bfd_mach_arm_ep9312
;
22600 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22601 mach
= bfd_mach_arm_5TE
;
22602 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22604 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22605 mach
= bfd_mach_arm_5T
;
22607 mach
= bfd_mach_arm_5
;
22609 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22611 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22612 mach
= bfd_mach_arm_4T
;
22614 mach
= bfd_mach_arm_4
;
22616 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22617 mach
= bfd_mach_arm_3M
;
22618 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22619 mach
= bfd_mach_arm_3
;
22620 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22621 mach
= bfd_mach_arm_2a
;
22622 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22623 mach
= bfd_mach_arm_2
;
22625 mach
= bfd_mach_arm_unknown
;
22627 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22630 /* Command line processing. */
22633 Invocation line includes a switch not recognized by the base assembler.
22634 See if it's a processor-specific option.
22636 This routine is somewhat complicated by the need for backwards
22637 compatibility (since older releases of gcc can't be changed).
22638 The new options try to make the interface as compatible as
22641 New options (supported) are:
22643 -mcpu=<cpu name> Assemble for selected processor
22644 -march=<architecture name> Assemble for selected architecture
22645 -mfpu=<fpu architecture> Assemble for selected FPU.
22646 -EB/-mbig-endian Big-endian
22647 -EL/-mlittle-endian Little-endian
22648 -k Generate PIC code
22649 -mthumb Start in Thumb mode
22650 -mthumb-interwork Code supports ARM/Thumb interworking
22652 -m[no-]warn-deprecated Warn about deprecated features
22654 For now we will also provide support for:
22656 -mapcs-32 32-bit Program counter
22657 -mapcs-26 26-bit Program counter
22658 -macps-float Floats passed in FP registers
22659 -mapcs-reentrant Reentrant code
22661 (sometime these will probably be replaced with -mapcs=<list of options>
22662 and -matpcs=<list of options>)
22664 The remaining options are only supported for back-wards compatibility.
22665 Cpu variants, the arm part is optional:
22666 -m[arm]1 Currently not supported.
22667 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22668 -m[arm]3 Arm 3 processor
22669 -m[arm]6[xx], Arm 6 processors
22670 -m[arm]7[xx][t][[d]m] Arm 7 processors
22671 -m[arm]8[10] Arm 8 processors
22672 -m[arm]9[20][tdmi] Arm 9 processors
22673 -mstrongarm[110[0]] StrongARM processors
22674 -mxscale XScale processors
22675 -m[arm]v[2345[t[e]]] Arm architectures
22676 -mall All (except the ARM1)
22678 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22679 -mfpe-old (No float load/store multiples)
22680 -mvfpxd VFP Single precision
22682 -mno-fpu Disable all floating point instructions
22684 The following CPU names are recognized:
22685 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22686 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22687 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22688 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22689 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22690 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22691 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22695 const char * md_shortopts
= "m:k";
22697 #ifdef ARM_BI_ENDIAN
22698 #define OPTION_EB (OPTION_MD_BASE + 0)
22699 #define OPTION_EL (OPTION_MD_BASE + 1)
22701 #if TARGET_BYTES_BIG_ENDIAN
22702 #define OPTION_EB (OPTION_MD_BASE + 0)
22704 #define OPTION_EL (OPTION_MD_BASE + 1)
22707 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22709 struct option md_longopts
[] =
22712 {"EB", no_argument
, NULL
, OPTION_EB
},
22715 {"EL", no_argument
, NULL
, OPTION_EL
},
22717 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22718 {NULL
, no_argument
, NULL
, 0}
22721 size_t md_longopts_size
= sizeof (md_longopts
);
22723 struct arm_option_table
22725 char *option
; /* Option name to match. */
22726 char *help
; /* Help information. */
22727 int *var
; /* Variable to change. */
22728 int value
; /* What to change it to. */
22729 char *deprecated
; /* If non-null, print this message. */
22732 struct arm_option_table arm_opts
[] =
22734 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22735 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22736 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22737 &support_interwork
, 1, NULL
},
22738 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22739 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22740 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22742 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22743 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22744 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22745 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22748 /* These are recognized by the assembler, but have no affect on code. */
22749 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22750 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22752 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22753 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22754 &warn_on_deprecated
, 0, NULL
},
22755 {NULL
, NULL
, NULL
, 0, NULL
}
22758 struct arm_legacy_option_table
22760 char *option
; /* Option name to match. */
22761 const arm_feature_set
**var
; /* Variable to change. */
22762 const arm_feature_set value
; /* What to change it to. */
22763 char *deprecated
; /* If non-null, print this message. */
22766 const struct arm_legacy_option_table arm_legacy_opts
[] =
22768 /* DON'T add any new processors to this list -- we want the whole list
22769 to go away... Add them to the processors table instead. */
22770 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22771 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22772 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22773 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22774 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22775 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22776 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22777 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22778 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22779 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22780 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22781 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22782 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22783 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22784 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22785 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22786 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22787 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22788 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22789 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22790 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22791 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22792 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22793 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22794 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22795 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22796 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22797 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22798 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22799 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22800 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22801 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22802 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22803 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22804 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22805 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22806 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22807 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22808 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22809 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22810 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22811 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22812 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22813 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22814 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22815 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22816 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22817 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22818 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22819 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22820 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22821 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22822 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22823 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22824 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22825 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22826 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22827 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22828 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22829 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22830 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22831 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22832 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22833 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22834 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22835 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22836 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22837 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22838 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22839 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22840 N_("use -mcpu=strongarm110")},
22841 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22842 N_("use -mcpu=strongarm1100")},
22843 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22844 N_("use -mcpu=strongarm1110")},
22845 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22846 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22847 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22849 /* Architecture variants -- don't add any more to this list either. */
22850 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22851 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22852 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22853 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22854 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22855 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22856 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22857 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22858 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22859 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22860 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22861 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22862 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22863 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22864 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22865 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22866 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22867 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22869 /* Floating point variants -- don't add any more to this list either. */
22870 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22871 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22872 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22873 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22874 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22876 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22879 struct arm_cpu_option_table
22883 const arm_feature_set value
;
22884 /* For some CPUs we assume an FPU unless the user explicitly sets
22886 const arm_feature_set default_fpu
;
22887 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22889 const char *canonical_name
;
22892 /* This list should, at a minimum, contain all the cpu names
22893 recognized by GCC. */
22894 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
22895 static const struct arm_cpu_option_table arm_cpus
[] =
22897 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
22898 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
22899 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
22900 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
22901 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
22902 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22903 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22904 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22905 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22906 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22907 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22908 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
22909 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22910 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
22911 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22912 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
22913 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22914 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22915 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22916 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22917 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22918 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22919 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22920 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22921 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22922 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22923 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22924 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
22925 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22926 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22927 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22928 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22929 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22930 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22931 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22932 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22933 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22934 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22935 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22936 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
22937 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22938 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22939 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22940 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
22941 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22942 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
22943 /* For V5 or later processors we default to using VFP; but the user
22944 should really set the FPU type explicitly. */
22945 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
22946 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22947 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
22948 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
22949 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
22950 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
22951 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
22952 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22953 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
22954 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
22955 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22956 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22957 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
22958 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
22959 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22960 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
22961 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
22962 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22963 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22964 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
22966 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
22967 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22968 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22969 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22970 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22971 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
22972 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
22973 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
22974 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
22976 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
22977 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
22978 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
22979 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
22980 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
22981 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
22982 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
22983 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22984 FPU_NONE
, "Cortex-A5"),
22985 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22986 FPU_ARCH_NEON_VFP_V4
,
22988 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
22989 ARM_FEATURE (0, FPU_VFP_V3
22990 | FPU_NEON_EXT_V1
),
22992 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22993 ARM_FEATURE (0, FPU_VFP_V3
22994 | FPU_NEON_EXT_V1
),
22996 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22997 FPU_ARCH_NEON_VFP_V4
,
22999 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
23000 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
23002 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
23003 FPU_NONE
, "Cortex-R5"),
23004 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
23005 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
23006 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
23007 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
23008 /* ??? XSCALE is really an architecture. */
23009 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
23010 /* ??? iwmmxt is not a processor. */
23011 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
23012 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
23013 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
23015 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
23018 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
23022 struct arm_arch_option_table
23026 const arm_feature_set value
;
23027 const arm_feature_set default_fpu
;
23030 /* This list should, at a minimum, contain all the architecture names
23031 recognized by GCC. */
23032 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23033 static const struct arm_arch_option_table arm_archs
[] =
23035 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
23036 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
23037 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
23038 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
23039 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
23040 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
23041 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
23042 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
23043 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
23044 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
23045 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
23046 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
23047 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
23048 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
23049 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
23050 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
23051 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
23052 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
23053 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
23054 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
23055 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
23056 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
23057 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
23058 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
23059 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
23060 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
23061 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
23062 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
23063 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
23064 /* The official spelling of the ARMv7 profile variants is the dashed form.
23065 Accept the non-dashed form for compatibility with old toolchains. */
23066 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
23067 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
23068 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
23069 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
23070 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
23071 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
23072 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
23073 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
23074 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
23075 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
23076 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23078 #undef ARM_ARCH_OPT
23080 /* ISA extensions in the co-processor and main instruction set space. */
23081 struct arm_option_extension_value_table
23085 const arm_feature_set value
;
23086 const arm_feature_set allowed_archs
;
23089 /* The following table must be in alphabetical order with a NULL last entry.
23091 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23092 static const struct arm_option_extension_value_table arm_extensions
[] =
23094 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23095 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
23096 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
23097 ARM_EXT_OPT ("iwmmxt2",
23098 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
23099 ARM_EXT_OPT ("maverick",
23100 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
23101 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
23102 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
23103 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
23104 ARM_FEATURE (ARM_EXT_V6M
, 0)),
23105 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
23106 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
23107 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
23109 ARM_FEATURE (ARM_EXT_V7A
, 0)),
23110 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
23111 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23115 /* ISA floating-point and Advanced SIMD extensions. */
23116 struct arm_option_fpu_value_table
23119 const arm_feature_set value
;
23122 /* This list should, at a minimum, contain all the fpu names
23123 recognized by GCC. */
23124 static const struct arm_option_fpu_value_table arm_fpus
[] =
23126 {"softfpa", FPU_NONE
},
23127 {"fpe", FPU_ARCH_FPE
},
23128 {"fpe2", FPU_ARCH_FPE
},
23129 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
23130 {"fpa", FPU_ARCH_FPA
},
23131 {"fpa10", FPU_ARCH_FPA
},
23132 {"fpa11", FPU_ARCH_FPA
},
23133 {"arm7500fe", FPU_ARCH_FPA
},
23134 {"softvfp", FPU_ARCH_VFP
},
23135 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
23136 {"vfp", FPU_ARCH_VFP_V2
},
23137 {"vfp9", FPU_ARCH_VFP_V2
},
23138 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
23139 {"vfp10", FPU_ARCH_VFP_V2
},
23140 {"vfp10-r0", FPU_ARCH_VFP_V1
},
23141 {"vfpxd", FPU_ARCH_VFP_V1xD
},
23142 {"vfpv2", FPU_ARCH_VFP_V2
},
23143 {"vfpv3", FPU_ARCH_VFP_V3
},
23144 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
23145 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
23146 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
23147 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
23148 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
23149 {"arm1020t", FPU_ARCH_VFP_V1
},
23150 {"arm1020e", FPU_ARCH_VFP_V2
},
23151 {"arm1136jfs", FPU_ARCH_VFP_V2
},
23152 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
23153 {"maverick", FPU_ARCH_MAVERICK
},
23154 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
23155 {"neon-fp16", FPU_ARCH_NEON_FP16
},
23156 {"vfpv4", FPU_ARCH_VFP_V4
},
23157 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
23158 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
23159 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
23160 {NULL
, ARM_ARCH_NONE
}
23163 struct arm_option_value_table
23169 static const struct arm_option_value_table arm_float_abis
[] =
23171 {"hard", ARM_FLOAT_ABI_HARD
},
23172 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
23173 {"soft", ARM_FLOAT_ABI_SOFT
},
23178 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23179 static const struct arm_option_value_table arm_eabis
[] =
23181 {"gnu", EF_ARM_EABI_UNKNOWN
},
23182 {"4", EF_ARM_EABI_VER4
},
23183 {"5", EF_ARM_EABI_VER5
},
23188 struct arm_long_option_table
23190 char * option
; /* Substring to match. */
23191 char * help
; /* Help information. */
23192 int (* func
) (char * subopt
); /* Function to decode sub-option. */
23193 char * deprecated
; /* If non-null, print this message. */
23197 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
23199 arm_feature_set
*ext_set
= (arm_feature_set
*)
23200 xmalloc (sizeof (arm_feature_set
));
23202 /* We insist on extensions being specified in alphabetical order, and with
23203 extensions being added before being removed. We achieve this by having
23204 the global ARM_EXTENSIONS table in alphabetical order, and using the
23205 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23206 or removing it (0) and only allowing it to change in the order
23208 const struct arm_option_extension_value_table
* opt
= NULL
;
23209 int adding_value
= -1;
23211 /* Copy the feature set, so that we can modify it. */
23212 *ext_set
= **opt_p
;
23215 while (str
!= NULL
&& *str
!= 0)
23222 as_bad (_("invalid architectural extension"));
23227 ext
= strchr (str
, '+');
23232 len
= strlen (str
);
23234 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
23236 if (adding_value
!= 0)
23239 opt
= arm_extensions
;
23247 if (adding_value
== -1)
23250 opt
= arm_extensions
;
23252 else if (adding_value
!= 1)
23254 as_bad (_("must specify extensions to add before specifying "
23255 "those to remove"));
23262 as_bad (_("missing architectural extension"));
23266 gas_assert (adding_value
!= -1);
23267 gas_assert (opt
!= NULL
);
23269 /* Scan over the options table trying to find an exact match. */
23270 for (; opt
->name
!= NULL
; opt
++)
23271 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23273 /* Check we can apply the extension to this architecture. */
23274 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23276 as_bad (_("extension does not apply to the base architecture"));
23280 /* Add or remove the extension. */
23282 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23284 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23289 if (opt
->name
== NULL
)
23291 /* Did we fail to find an extension because it wasn't specified in
23292 alphabetical order, or because it does not exist? */
23294 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23295 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23298 if (opt
->name
== NULL
)
23299 as_bad (_("unknown architectural extension `%s'"), str
);
23301 as_bad (_("architectural extensions must be specified in "
23302 "alphabetical order"));
23308 /* We should skip the extension we've just matched the next time
23320 arm_parse_cpu (char *str
)
23322 const struct arm_cpu_option_table
*opt
;
23323 char *ext
= strchr (str
, '+');
23329 len
= strlen (str
);
23333 as_bad (_("missing cpu name `%s'"), str
);
23337 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23338 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23340 mcpu_cpu_opt
= &opt
->value
;
23341 mcpu_fpu_opt
= &opt
->default_fpu
;
23342 if (opt
->canonical_name
)
23343 strcpy (selected_cpu_name
, opt
->canonical_name
);
23348 for (i
= 0; i
< len
; i
++)
23349 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23350 selected_cpu_name
[i
] = 0;
23354 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23359 as_bad (_("unknown cpu `%s'"), str
);
23364 arm_parse_arch (char *str
)
23366 const struct arm_arch_option_table
*opt
;
23367 char *ext
= strchr (str
, '+');
23373 len
= strlen (str
);
23377 as_bad (_("missing architecture name `%s'"), str
);
23381 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23382 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23384 march_cpu_opt
= &opt
->value
;
23385 march_fpu_opt
= &opt
->default_fpu
;
23386 strcpy (selected_cpu_name
, opt
->name
);
23389 return arm_parse_extension (ext
, &march_cpu_opt
);
23394 as_bad (_("unknown architecture `%s'\n"), str
);
23399 arm_parse_fpu (char * str
)
23401 const struct arm_option_fpu_value_table
* opt
;
23403 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23404 if (streq (opt
->name
, str
))
23406 mfpu_opt
= &opt
->value
;
23410 as_bad (_("unknown floating point format `%s'\n"), str
);
23415 arm_parse_float_abi (char * str
)
23417 const struct arm_option_value_table
* opt
;
23419 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23420 if (streq (opt
->name
, str
))
23422 mfloat_abi_opt
= opt
->value
;
23426 as_bad (_("unknown floating point abi `%s'\n"), str
);
23432 arm_parse_eabi (char * str
)
23434 const struct arm_option_value_table
*opt
;
23436 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23437 if (streq (opt
->name
, str
))
23439 meabi_flags
= opt
->value
;
23442 as_bad (_("unknown EABI `%s'\n"), str
);
23448 arm_parse_it_mode (char * str
)
23450 bfd_boolean ret
= TRUE
;
23452 if (streq ("arm", str
))
23453 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23454 else if (streq ("thumb", str
))
23455 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23456 else if (streq ("always", str
))
23457 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23458 else if (streq ("never", str
))
23459 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23462 as_bad (_("unknown implicit IT mode `%s', should be "\
23463 "arm, thumb, always, or never."), str
);
23470 struct arm_long_option_table arm_long_opts
[] =
23472 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23473 arm_parse_cpu
, NULL
},
23474 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23475 arm_parse_arch
, NULL
},
23476 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23477 arm_parse_fpu
, NULL
},
23478 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23479 arm_parse_float_abi
, NULL
},
23481 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23482 arm_parse_eabi
, NULL
},
23484 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23485 arm_parse_it_mode
, NULL
},
23486 {NULL
, NULL
, 0, NULL
}
23490 md_parse_option (int c
, char * arg
)
23492 struct arm_option_table
*opt
;
23493 const struct arm_legacy_option_table
*fopt
;
23494 struct arm_long_option_table
*lopt
;
23500 target_big_endian
= 1;
23506 target_big_endian
= 0;
23510 case OPTION_FIX_V4BX
:
23515 /* Listing option. Just ignore these, we don't support additional
23520 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23522 if (c
== opt
->option
[0]
23523 && ((arg
== NULL
&& opt
->option
[1] == 0)
23524 || streq (arg
, opt
->option
+ 1)))
23526 /* If the option is deprecated, tell the user. */
23527 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23528 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23529 arg
? arg
: "", _(opt
->deprecated
));
23531 if (opt
->var
!= NULL
)
23532 *opt
->var
= opt
->value
;
23538 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23540 if (c
== fopt
->option
[0]
23541 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23542 || streq (arg
, fopt
->option
+ 1)))
23544 /* If the option is deprecated, tell the user. */
23545 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23546 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23547 arg
? arg
: "", _(fopt
->deprecated
));
23549 if (fopt
->var
!= NULL
)
23550 *fopt
->var
= &fopt
->value
;
23556 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23558 /* These options are expected to have an argument. */
23559 if (c
== lopt
->option
[0]
23561 && strncmp (arg
, lopt
->option
+ 1,
23562 strlen (lopt
->option
+ 1)) == 0)
23564 /* If the option is deprecated, tell the user. */
23565 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23566 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23567 _(lopt
->deprecated
));
23569 /* Call the sup-option parser. */
23570 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23581 md_show_usage (FILE * fp
)
23583 struct arm_option_table
*opt
;
23584 struct arm_long_option_table
*lopt
;
23586 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23588 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23589 if (opt
->help
!= NULL
)
23590 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23592 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23593 if (lopt
->help
!= NULL
)
23594 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23598 -EB assemble code for a big-endian cpu\n"));
23603 -EL assemble code for a little-endian cpu\n"));
23607 --fix-v4bx Allow BX in ARMv4 code\n"));
23615 arm_feature_set flags
;
23616 } cpu_arch_ver_table
;
23618 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23619 least features first. */
23620 static const cpu_arch_ver_table cpu_arch_ver
[] =
23626 {4, ARM_ARCH_V5TE
},
23627 {5, ARM_ARCH_V5TEJ
},
23631 {11, ARM_ARCH_V6M
},
23632 {12, ARM_ARCH_V6SM
},
23633 {8, ARM_ARCH_V6T2
},
23634 {10, ARM_ARCH_V7A
},
23635 {10, ARM_ARCH_V7R
},
23636 {10, ARM_ARCH_V7M
},
23640 /* Set an attribute if it has not already been set by the user. */
23642 aeabi_set_attribute_int (int tag
, int value
)
23645 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23646 || !attributes_set_explicitly
[tag
])
23647 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23651 aeabi_set_attribute_string (int tag
, const char *value
)
23654 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23655 || !attributes_set_explicitly
[tag
])
23656 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23659 /* Set the public EABI object attributes. */
23661 aeabi_set_public_attributes (void)
23665 arm_feature_set flags
;
23666 arm_feature_set tmp
;
23667 const cpu_arch_ver_table
*p
;
23669 /* Choose the architecture based on the capabilities of the requested cpu
23670 (if any) and/or the instructions actually used. */
23671 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23672 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23673 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23675 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
23676 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
23678 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
23679 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
23681 /* Allow the user to override the reported architecture. */
23684 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23685 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23688 /* We need to make sure that the attributes do not identify us as v6S-M
23689 when the only v6S-M feature in use is the Operating System Extensions. */
23690 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23691 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23692 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23696 for (p
= cpu_arch_ver
; p
->val
; p
++)
23698 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23701 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23705 /* The table lookup above finds the last architecture to contribute
23706 a new feature. Unfortunately, Tag13 is a subset of the union of
23707 v6T2 and v7-M, so it is never seen as contributing a new feature.
23708 We can not search for the last entry which is entirely used,
23709 because if no CPU is specified we build up only those flags
23710 actually used. Perhaps we should separate out the specified
23711 and implicit cases. Avoid taking this path for -march=all by
23712 checking for contradictory v7-A / v7-M features. */
23714 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23715 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23716 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23719 /* Tag_CPU_name. */
23720 if (selected_cpu_name
[0])
23724 q
= selected_cpu_name
;
23725 if (strncmp (q
, "armv", 4) == 0)
23730 for (i
= 0; q
[i
]; i
++)
23731 q
[i
] = TOUPPER (q
[i
]);
23733 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23736 /* Tag_CPU_arch. */
23737 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23739 /* Tag_CPU_arch_profile. */
23740 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23741 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23742 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23743 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23744 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23745 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23747 /* Tag_ARM_ISA_use. */
23748 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23750 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23752 /* Tag_THUMB_ISA_use. */
23753 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23755 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23756 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23758 /* Tag_VFP_arch. */
23759 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23760 aeabi_set_attribute_int (Tag_VFP_arch
,
23761 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23763 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23764 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23765 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23766 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23767 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23768 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23769 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23770 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23771 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23773 /* Tag_ABI_HardFP_use. */
23774 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23775 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23776 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23778 /* Tag_WMMX_arch. */
23779 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23780 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23781 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23782 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23784 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23785 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23786 aeabi_set_attribute_int
23787 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23790 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23791 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23792 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23795 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23796 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23797 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23798 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23800 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23802 /* Tag_MP_extension_use. */
23803 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23804 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23806 /* Tag Virtualization_use. */
23807 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23809 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23812 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23815 /* Add the default contents for the .ARM.attributes section. */
23819 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23822 aeabi_set_public_attributes ();
23824 #endif /* OBJ_ELF */
23827 /* Parse a .cpu directive. */
23830 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23832 const struct arm_cpu_option_table
*opt
;
23836 name
= input_line_pointer
;
23837 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23838 input_line_pointer
++;
23839 saved_char
= *input_line_pointer
;
23840 *input_line_pointer
= 0;
23842 /* Skip the first "all" entry. */
23843 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23844 if (streq (opt
->name
, name
))
23846 mcpu_cpu_opt
= &opt
->value
;
23847 selected_cpu
= opt
->value
;
23848 if (opt
->canonical_name
)
23849 strcpy (selected_cpu_name
, opt
->canonical_name
);
23853 for (i
= 0; opt
->name
[i
]; i
++)
23854 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23856 selected_cpu_name
[i
] = 0;
23858 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23859 *input_line_pointer
= saved_char
;
23860 demand_empty_rest_of_line ();
23863 as_bad (_("unknown cpu `%s'"), name
);
23864 *input_line_pointer
= saved_char
;
23865 ignore_rest_of_line ();
23869 /* Parse a .arch directive. */
23872 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23874 const struct arm_arch_option_table
*opt
;
23878 name
= input_line_pointer
;
23879 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23880 input_line_pointer
++;
23881 saved_char
= *input_line_pointer
;
23882 *input_line_pointer
= 0;
23884 /* Skip the first "all" entry. */
23885 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23886 if (streq (opt
->name
, name
))
23888 mcpu_cpu_opt
= &opt
->value
;
23889 selected_cpu
= opt
->value
;
23890 strcpy (selected_cpu_name
, opt
->name
);
23891 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23892 *input_line_pointer
= saved_char
;
23893 demand_empty_rest_of_line ();
23897 as_bad (_("unknown architecture `%s'\n"), name
);
23898 *input_line_pointer
= saved_char
;
23899 ignore_rest_of_line ();
23903 /* Parse a .object_arch directive. */
23906 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23908 const struct arm_arch_option_table
*opt
;
23912 name
= input_line_pointer
;
23913 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23914 input_line_pointer
++;
23915 saved_char
= *input_line_pointer
;
23916 *input_line_pointer
= 0;
23918 /* Skip the first "all" entry. */
23919 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23920 if (streq (opt
->name
, name
))
23922 object_arch
= &opt
->value
;
23923 *input_line_pointer
= saved_char
;
23924 demand_empty_rest_of_line ();
23928 as_bad (_("unknown architecture `%s'\n"), name
);
23929 *input_line_pointer
= saved_char
;
23930 ignore_rest_of_line ();
23933 /* Parse a .arch_extension directive. */
23936 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23938 const struct arm_option_extension_value_table
*opt
;
23941 int adding_value
= 1;
23943 name
= input_line_pointer
;
23944 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23945 input_line_pointer
++;
23946 saved_char
= *input_line_pointer
;
23947 *input_line_pointer
= 0;
23949 if (strlen (name
) >= 2
23950 && strncmp (name
, "no", 2) == 0)
23956 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23957 if (streq (opt
->name
, name
))
23959 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23961 as_bad (_("architectural extension `%s' is not allowed for the "
23962 "current base architecture"), name
);
23967 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23969 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23971 mcpu_cpu_opt
= &selected_cpu
;
23972 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23973 *input_line_pointer
= saved_char
;
23974 demand_empty_rest_of_line ();
23978 if (opt
->name
== NULL
)
23979 as_bad (_("unknown architecture `%s'\n"), name
);
23981 *input_line_pointer
= saved_char
;
23982 ignore_rest_of_line ();
23985 /* Parse a .fpu directive. */
23988 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23990 const struct arm_option_fpu_value_table
*opt
;
23994 name
= input_line_pointer
;
23995 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23996 input_line_pointer
++;
23997 saved_char
= *input_line_pointer
;
23998 *input_line_pointer
= 0;
24000 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24001 if (streq (opt
->name
, name
))
24003 mfpu_opt
= &opt
->value
;
24004 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24005 *input_line_pointer
= saved_char
;
24006 demand_empty_rest_of_line ();
24010 as_bad (_("unknown floating point format `%s'\n"), name
);
24011 *input_line_pointer
= saved_char
;
24012 ignore_rest_of_line ();
24015 /* Copy symbol information. */
24018 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
24020 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
24024 /* Given a symbolic attribute NAME, return the proper integer value.
24025 Returns -1 if the attribute is not known. */
24028 arm_convert_symbolic_attribute (const char *name
)
24030 static const struct
24035 attribute_table
[] =
24037 /* When you modify this table you should
24038 also modify the list in doc/c-arm.texi. */
24039 #define T(tag) {#tag, tag}
24040 T (Tag_CPU_raw_name
),
24043 T (Tag_CPU_arch_profile
),
24044 T (Tag_ARM_ISA_use
),
24045 T (Tag_THUMB_ISA_use
),
24049 T (Tag_Advanced_SIMD_arch
),
24050 T (Tag_PCS_config
),
24051 T (Tag_ABI_PCS_R9_use
),
24052 T (Tag_ABI_PCS_RW_data
),
24053 T (Tag_ABI_PCS_RO_data
),
24054 T (Tag_ABI_PCS_GOT_use
),
24055 T (Tag_ABI_PCS_wchar_t
),
24056 T (Tag_ABI_FP_rounding
),
24057 T (Tag_ABI_FP_denormal
),
24058 T (Tag_ABI_FP_exceptions
),
24059 T (Tag_ABI_FP_user_exceptions
),
24060 T (Tag_ABI_FP_number_model
),
24061 T (Tag_ABI_align_needed
),
24062 T (Tag_ABI_align8_needed
),
24063 T (Tag_ABI_align_preserved
),
24064 T (Tag_ABI_align8_preserved
),
24065 T (Tag_ABI_enum_size
),
24066 T (Tag_ABI_HardFP_use
),
24067 T (Tag_ABI_VFP_args
),
24068 T (Tag_ABI_WMMX_args
),
24069 T (Tag_ABI_optimization_goals
),
24070 T (Tag_ABI_FP_optimization_goals
),
24071 T (Tag_compatibility
),
24072 T (Tag_CPU_unaligned_access
),
24073 T (Tag_FP_HP_extension
),
24074 T (Tag_VFP_HP_extension
),
24075 T (Tag_ABI_FP_16bit_format
),
24076 T (Tag_MPextension_use
),
24078 T (Tag_nodefaults
),
24079 T (Tag_also_compatible_with
),
24080 T (Tag_conformance
),
24082 T (Tag_Virtualization_use
),
24083 /* We deliberately do not include Tag_MPextension_use_legacy. */
24091 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
24092 if (streq (name
, attribute_table
[i
].name
))
24093 return attribute_table
[i
].tag
;
24099 /* Apply sym value for relocations only in the case that
24100 they are for local symbols and you have the respective
24101 architectural feature for blx and simple switches. */
24103 arm_apply_sym_value (struct fix
* fixP
)
24106 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24107 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
24109 switch (fixP
->fx_r_type
)
24111 case BFD_RELOC_ARM_PCREL_BLX
:
24112 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24113 if (ARM_IS_FUNC (fixP
->fx_addsy
))
24117 case BFD_RELOC_ARM_PCREL_CALL
:
24118 case BFD_RELOC_THUMB_PCREL_BLX
:
24119 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
24130 #endif /* OBJ_ELF */