1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
* legacy_cpu
= NULL
;
147 static const arm_feature_set
* legacy_fpu
= NULL
;
149 static const arm_feature_set
* mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
* dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
* mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
* march_cpu_opt
= NULL
;
153 static arm_feature_set
* dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
* march_fpu_opt
= NULL
;
155 static const arm_feature_set
* mfpu_opt
= NULL
;
156 static const arm_feature_set
* object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_fp16_fml
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
240 static const arm_feature_set arm_ext_v8_2
=
241 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
242 static const arm_feature_set arm_ext_v8_3
=
243 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
245 static const arm_feature_set arm_arch_any
= ARM_ANY
;
247 static const arm_feature_set fpu_any
= FPU_ANY
;
249 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
250 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
251 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
253 static const arm_feature_set arm_cext_iwmmxt2
=
254 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
255 static const arm_feature_set arm_cext_iwmmxt
=
256 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
257 static const arm_feature_set arm_cext_xscale
=
258 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
259 static const arm_feature_set arm_cext_maverick
=
260 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
261 static const arm_feature_set fpu_fpa_ext_v1
=
262 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
263 static const arm_feature_set fpu_fpa_ext_v2
=
264 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
265 static const arm_feature_set fpu_vfp_ext_v1xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
267 static const arm_feature_set fpu_vfp_ext_v1
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
269 static const arm_feature_set fpu_vfp_ext_v2
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
271 static const arm_feature_set fpu_vfp_ext_v3xd
=
272 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
273 static const arm_feature_set fpu_vfp_ext_v3
=
274 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
275 static const arm_feature_set fpu_vfp_ext_d32
=
276 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
277 static const arm_feature_set fpu_neon_ext_v1
=
278 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
279 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
282 static const arm_feature_set fpu_vfp_fp16
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
284 static const arm_feature_set fpu_neon_ext_fma
=
285 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
287 static const arm_feature_set fpu_vfp_ext_fma
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
289 static const arm_feature_set fpu_vfp_ext_armv8
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
291 static const arm_feature_set fpu_vfp_ext_armv8xd
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
293 static const arm_feature_set fpu_neon_ext_armv8
=
294 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
295 static const arm_feature_set fpu_crypto_ext_armv8
=
296 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
297 static const arm_feature_set crc_ext_armv8
=
298 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
299 static const arm_feature_set fpu_neon_ext_v8_1
=
300 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
301 static const arm_feature_set fpu_neon_ext_dotprod
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
304 static int mfloat_abi_opt
= -1;
305 /* Record user cpu selection for object attributes. */
306 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
307 /* Must be long enough to hold any of the names in arm_cpus. */
308 static char selected_cpu_name
[20];
310 extern FLONUM_TYPE generic_floating_point_number
;
312 /* Return if no cpu was selected on command-line. */
314 no_cpu_selected (void)
316 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
321 static int meabi_flags
= EABI_DEFAULT
;
323 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
326 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
331 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
336 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
337 symbolS
* GOT_symbol
;
340 /* 0: assemble for ARM,
341 1: assemble for Thumb,
342 2: assemble for Thumb even though target CPU does not support thumb
344 static int thumb_mode
= 0;
345 /* A value distinct from the possible values for thumb_mode that we
346 can use to record whether thumb_mode has been copied into the
347 tc_frag_data field of a frag. */
348 #define MODE_RECORDED (1 << 4)
350 /* Specifies the intrinsic IT insn behavior mode. */
351 enum implicit_it_mode
353 IMPLICIT_IT_MODE_NEVER
= 0x00,
354 IMPLICIT_IT_MODE_ARM
= 0x01,
355 IMPLICIT_IT_MODE_THUMB
= 0x02,
356 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
358 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
360 /* If unified_syntax is true, we are processing the new unified
361 ARM/Thumb syntax. Important differences from the old ARM mode:
363 - Immediate operands do not require a # prefix.
364 - Conditional affixes always appear at the end of the
365 instruction. (For backward compatibility, those instructions
366 that formerly had them in the middle, continue to accept them
368 - The IT instruction may appear, and if it does is validated
369 against subsequent conditional affixes. It does not generate
372 Important differences from the old Thumb mode:
374 - Immediate operands do not require a # prefix.
375 - Most of the V6T2 instructions are only available in unified mode.
376 - The .N and .W suffixes are recognized and honored (it is an error
377 if they cannot be honored).
378 - All instructions set the flags if and only if they have an 's' affix.
379 - Conditional affixes may be used. They are validated against
380 preceding IT instructions. Unlike ARM mode, you cannot use a
381 conditional affix except in the scope of an IT instruction. */
383 static bfd_boolean unified_syntax
= FALSE
;
385 /* An immediate operand can start with #, and ld*, st*, pld operands
386 can contain [ and ]. We need to tell APP not to elide whitespace
387 before a [, which can appear as the first operand for pld.
388 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
389 const char arm_symbol_chars
[] = "#[]{}";
404 enum neon_el_type type
;
408 #define NEON_MAX_TYPE_ELS 4
412 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
416 enum it_instruction_type
421 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
422 if inside, should be the last one. */
423 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
424 i.e. BKPT and NOP. */
425 IT_INSN
/* The IT insn has been parsed. */
428 /* The maximum number of operands we need. */
429 #define ARM_IT_MAX_OPERANDS 6
434 unsigned long instruction
;
438 /* "uncond_value" is set to the value in place of the conditional field in
439 unconditional versions of the instruction, or -1 if nothing is
442 struct neon_type vectype
;
443 /* This does not indicate an actual NEON instruction, only that
444 the mnemonic accepts neon-style type suffixes. */
446 /* Set to the opcode if the instruction needs relaxation.
447 Zero if the instruction is not relaxed. */
451 bfd_reloc_code_real_type type
;
456 enum it_instruction_type it_insn_type
;
462 struct neon_type_el vectype
;
463 unsigned present
: 1; /* Operand present. */
464 unsigned isreg
: 1; /* Operand was a register. */
465 unsigned immisreg
: 1; /* .imm field is a second register. */
466 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
467 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
468 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
469 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
470 instructions. This allows us to disambiguate ARM <-> vector insns. */
471 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
472 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
473 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
474 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
475 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
476 unsigned writeback
: 1; /* Operand has trailing ! */
477 unsigned preind
: 1; /* Preindexed address. */
478 unsigned postind
: 1; /* Postindexed address. */
479 unsigned negative
: 1; /* Index register was negated. */
480 unsigned shifted
: 1; /* Shift applied to operation. */
481 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
482 } operands
[ARM_IT_MAX_OPERANDS
];
485 static struct arm_it inst
;
487 #define NUM_FLOAT_VALS 8
489 const char * fp_const
[] =
491 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
494 /* Number of littlenums required to hold an extended precision number. */
495 #define MAX_LITTLENUMS 6
497 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
507 #define CP_T_X 0x00008000
508 #define CP_T_Y 0x00400000
510 #define CONDS_BIT 0x00100000
511 #define LOAD_BIT 0x00100000
513 #define DOUBLE_LOAD_FLAG 0x00000001
517 const char * template_name
;
521 #define COND_ALWAYS 0xE
525 const char * template_name
;
529 struct asm_barrier_opt
531 const char * template_name
;
533 const arm_feature_set arch
;
536 /* The bit that distinguishes CPSR and SPSR. */
537 #define SPSR_BIT (1 << 22)
539 /* The individual PSR flag bits. */
540 #define PSR_c (1 << 16)
541 #define PSR_x (1 << 17)
542 #define PSR_s (1 << 18)
543 #define PSR_f (1 << 19)
548 bfd_reloc_code_real_type reloc
;
553 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
554 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
559 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
562 /* Bits for DEFINED field in neon_typed_alias. */
563 #define NTA_HASTYPE 1
564 #define NTA_HASINDEX 2
566 struct neon_typed_alias
568 unsigned char defined
;
570 struct neon_type_el eltype
;
573 /* ARM register categories. This includes coprocessor numbers and various
574 architecture extensions' registers. Each entry should have an error message
575 in reg_expected_msgs below. */
603 /* Structure for a hash table entry for a register.
604 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
605 information which states whether a vector type or index is specified (for a
606 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
612 unsigned char builtin
;
613 struct neon_typed_alias
* neon
;
616 /* Diagnostics used when we don't get a register of the expected type. */
617 const char * const reg_expected_msgs
[] =
619 [REG_TYPE_RN
] = N_("ARM register expected"),
620 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
621 [REG_TYPE_CN
] = N_("co-processor register expected"),
622 [REG_TYPE_FN
] = N_("FPA register expected"),
623 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
624 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
625 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
626 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
627 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
628 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
629 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
631 [REG_TYPE_VFC
] = N_("VFP system register expected"),
632 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
633 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
634 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
635 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
636 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
637 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
638 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
639 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
640 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
641 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
642 [REG_TYPE_RNB
] = N_("")
645 /* Some well known registers that we refer to directly elsewhere. */
651 /* ARM instructions take 4bytes in the object file, Thumb instructions
657 /* Basic string to match. */
658 const char * template_name
;
660 /* Parameters to instruction. */
661 unsigned int operands
[8];
663 /* Conditional tag - see opcode_lookup. */
664 unsigned int tag
: 4;
666 /* Basic instruction code. */
667 unsigned int avalue
: 28;
669 /* Thumb-format instruction code. */
672 /* Which architecture variant provides this instruction. */
673 const arm_feature_set
* avariant
;
674 const arm_feature_set
* tvariant
;
676 /* Function to call to encode instruction in ARM format. */
677 void (* aencode
) (void);
679 /* Function to call to encode instruction in Thumb format. */
680 void (* tencode
) (void);
683 /* Defines for various bits that we will want to toggle. */
684 #define INST_IMMEDIATE 0x02000000
685 #define OFFSET_REG 0x02000000
686 #define HWOFFSET_IMM 0x00400000
687 #define SHIFT_BY_REG 0x00000010
688 #define PRE_INDEX 0x01000000
689 #define INDEX_UP 0x00800000
690 #define WRITE_BACK 0x00200000
691 #define LDM_TYPE_2_OR_3 0x00400000
692 #define CPSI_MMOD 0x00020000
694 #define LITERAL_MASK 0xf000f000
695 #define OPCODE_MASK 0xfe1fffff
696 #define V4_STR_BIT 0x00000020
697 #define VLDR_VMOV_SAME 0x0040f000
699 #define T2_SUBS_PC_LR 0xf3de8f00
701 #define DATA_OP_SHIFT 21
702 #define SBIT_SHIFT 20
704 #define T2_OPCODE_MASK 0xfe1fffff
705 #define T2_DATA_OP_SHIFT 21
706 #define T2_SBIT_SHIFT 20
708 #define A_COND_MASK 0xf0000000
709 #define A_PUSH_POP_OP_MASK 0x0fff0000
711 /* Opcodes for pushing/poping registers to/from the stack. */
712 #define A1_OPCODE_PUSH 0x092d0000
713 #define A2_OPCODE_PUSH 0x052d0004
714 #define A2_OPCODE_POP 0x049d0004
716 /* Codes to distinguish the arithmetic instructions. */
727 #define OPCODE_CMP 10
728 #define OPCODE_CMN 11
729 #define OPCODE_ORR 12
730 #define OPCODE_MOV 13
731 #define OPCODE_BIC 14
732 #define OPCODE_MVN 15
734 #define T2_OPCODE_AND 0
735 #define T2_OPCODE_BIC 1
736 #define T2_OPCODE_ORR 2
737 #define T2_OPCODE_ORN 3
738 #define T2_OPCODE_EOR 4
739 #define T2_OPCODE_ADD 8
740 #define T2_OPCODE_ADC 10
741 #define T2_OPCODE_SBC 11
742 #define T2_OPCODE_SUB 13
743 #define T2_OPCODE_RSB 14
745 #define T_OPCODE_MUL 0x4340
746 #define T_OPCODE_TST 0x4200
747 #define T_OPCODE_CMN 0x42c0
748 #define T_OPCODE_NEG 0x4240
749 #define T_OPCODE_MVN 0x43c0
751 #define T_OPCODE_ADD_R3 0x1800
752 #define T_OPCODE_SUB_R3 0x1a00
753 #define T_OPCODE_ADD_HI 0x4400
754 #define T_OPCODE_ADD_ST 0xb000
755 #define T_OPCODE_SUB_ST 0xb080
756 #define T_OPCODE_ADD_SP 0xa800
757 #define T_OPCODE_ADD_PC 0xa000
758 #define T_OPCODE_ADD_I8 0x3000
759 #define T_OPCODE_SUB_I8 0x3800
760 #define T_OPCODE_ADD_I3 0x1c00
761 #define T_OPCODE_SUB_I3 0x1e00
763 #define T_OPCODE_ASR_R 0x4100
764 #define T_OPCODE_LSL_R 0x4080
765 #define T_OPCODE_LSR_R 0x40c0
766 #define T_OPCODE_ROR_R 0x41c0
767 #define T_OPCODE_ASR_I 0x1000
768 #define T_OPCODE_LSL_I 0x0000
769 #define T_OPCODE_LSR_I 0x0800
771 #define T_OPCODE_MOV_I8 0x2000
772 #define T_OPCODE_CMP_I8 0x2800
773 #define T_OPCODE_CMP_LR 0x4280
774 #define T_OPCODE_MOV_HR 0x4600
775 #define T_OPCODE_CMP_HR 0x4500
777 #define T_OPCODE_LDR_PC 0x4800
778 #define T_OPCODE_LDR_SP 0x9800
779 #define T_OPCODE_STR_SP 0x9000
780 #define T_OPCODE_LDR_IW 0x6800
781 #define T_OPCODE_STR_IW 0x6000
782 #define T_OPCODE_LDR_IH 0x8800
783 #define T_OPCODE_STR_IH 0x8000
784 #define T_OPCODE_LDR_IB 0x7800
785 #define T_OPCODE_STR_IB 0x7000
786 #define T_OPCODE_LDR_RW 0x5800
787 #define T_OPCODE_STR_RW 0x5000
788 #define T_OPCODE_LDR_RH 0x5a00
789 #define T_OPCODE_STR_RH 0x5200
790 #define T_OPCODE_LDR_RB 0x5c00
791 #define T_OPCODE_STR_RB 0x5400
793 #define T_OPCODE_PUSH 0xb400
794 #define T_OPCODE_POP 0xbc00
796 #define T_OPCODE_BRANCH 0xe000
798 #define THUMB_SIZE 2 /* Size of thumb instruction. */
799 #define THUMB_PP_PC_LR 0x0100
800 #define THUMB_LOAD_BIT 0x0800
801 #define THUMB2_LOAD_BIT 0x00100000
803 #define BAD_ARGS _("bad arguments to instruction")
804 #define BAD_SP _("r13 not allowed here")
805 #define BAD_PC _("r15 not allowed here")
806 #define BAD_COND _("instruction cannot be conditional")
807 #define BAD_OVERLAP _("registers may not be the same")
808 #define BAD_HIREG _("lo register required")
809 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
810 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
811 #define BAD_BRANCH _("branch must be last instruction in IT block")
812 #define BAD_NOT_IT _("instruction not allowed in IT block")
813 #define BAD_FPU _("selected FPU does not support instruction")
814 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
815 #define BAD_IT_COND _("incorrect condition in IT block")
816 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
817 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
818 #define BAD_PC_ADDRESSING \
819 _("cannot use register index with PC-relative addressing")
820 #define BAD_PC_WRITEBACK \
821 _("cannot use writeback with PC-relative addressing")
822 #define BAD_RANGE _("branch out of range")
823 #define BAD_FP16 _("selected processor does not support fp16 instruction")
824 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
825 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
827 static struct hash_control
* arm_ops_hsh
;
828 static struct hash_control
* arm_cond_hsh
;
829 static struct hash_control
* arm_shift_hsh
;
830 static struct hash_control
* arm_psr_hsh
;
831 static struct hash_control
* arm_v7m_psr_hsh
;
832 static struct hash_control
* arm_reg_hsh
;
833 static struct hash_control
* arm_reloc_hsh
;
834 static struct hash_control
* arm_barrier_opt_hsh
;
836 /* Stuff needed to resolve the label ambiguity
845 symbolS
* last_label_seen
;
846 static int label_is_thumb_function_name
= FALSE
;
848 /* Literal pool structure. Held on a per-section
849 and per-sub-section basis. */
851 #define MAX_LITERAL_POOL_SIZE 1024
852 typedef struct literal_pool
854 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
855 unsigned int next_free_entry
;
861 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
863 struct literal_pool
* next
;
864 unsigned int alignment
;
867 /* Pointer to a linked list of literal pools. */
868 literal_pool
* list_of_pools
= NULL
;
870 typedef enum asmfunc_states
873 WAITING_ASMFUNC_NAME
,
877 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
880 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
882 static struct current_it now_it
;
886 now_it_compatible (int cond
)
888 return (cond
& ~1) == (now_it
.cc
& ~1);
892 conditional_insn (void)
894 return inst
.cond
!= COND_ALWAYS
;
897 static int in_it_block (void);
899 static int handle_it_state (void);
901 static void force_automatic_it_block_close (void);
903 static void it_fsm_post_encode (void);
905 #define set_it_insn_type(type) \
908 inst.it_insn_type = type; \
909 if (handle_it_state () == FAIL) \
914 #define set_it_insn_type_nonvoid(type, failret) \
917 inst.it_insn_type = type; \
918 if (handle_it_state () == FAIL) \
923 #define set_it_insn_type_last() \
926 if (inst.cond == COND_ALWAYS) \
927 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
929 set_it_insn_type (INSIDE_IT_LAST_INSN); \
935 /* This array holds the chars that always start a comment. If the
936 pre-processor is disabled, these aren't very useful. */
937 char arm_comment_chars
[] = "@";
939 /* This array holds the chars that only start a comment at the beginning of
940 a line. If the line seems to have the form '# 123 filename'
941 .line and .file directives will appear in the pre-processed output. */
942 /* Note that input_file.c hand checks for '#' at the beginning of the
943 first line of the input file. This is because the compiler outputs
944 #NO_APP at the beginning of its output. */
945 /* Also note that comments like this one will always work. */
946 const char line_comment_chars
[] = "#";
948 char arm_line_separator_chars
[] = ";";
950 /* Chars that can be used to separate mant
951 from exp in floating point numbers. */
952 const char EXP_CHARS
[] = "eE";
954 /* Chars that mean this number is a floating point constant. */
958 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
960 /* Prefix characters that indicate the start of an immediate
962 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
964 /* Separator character handling. */
966 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
969 skip_past_char (char ** str
, char c
)
971 /* PR gas/14987: Allow for whitespace before the expected character. */
972 skip_whitespace (*str
);
983 #define skip_past_comma(str) skip_past_char (str, ',')
985 /* Arithmetic expressions (possibly involving symbols). */
987 /* Return TRUE if anything in the expression is a bignum. */
990 walk_no_bignums (symbolS
* sp
)
992 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
995 if (symbol_get_value_expression (sp
)->X_add_symbol
)
997 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
998 || (symbol_get_value_expression (sp
)->X_op_symbol
999 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1005 static bfd_boolean in_my_get_expression
= FALSE
;
1007 /* Third argument to my_get_expression. */
1008 #define GE_NO_PREFIX 0
1009 #define GE_IMM_PREFIX 1
1010 #define GE_OPT_PREFIX 2
1011 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1012 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1013 #define GE_OPT_PREFIX_BIG 3
1016 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1021 /* In unified syntax, all prefixes are optional. */
1023 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1026 switch (prefix_mode
)
1028 case GE_NO_PREFIX
: break;
1030 if (!is_immediate_prefix (**str
))
1032 inst
.error
= _("immediate expression requires a # prefix");
1038 case GE_OPT_PREFIX_BIG
:
1039 if (is_immediate_prefix (**str
))
1046 memset (ep
, 0, sizeof (expressionS
));
1048 save_in
= input_line_pointer
;
1049 input_line_pointer
= *str
;
1050 in_my_get_expression
= TRUE
;
1051 seg
= expression (ep
);
1052 in_my_get_expression
= FALSE
;
1054 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1056 /* We found a bad or missing expression in md_operand(). */
1057 *str
= input_line_pointer
;
1058 input_line_pointer
= save_in
;
1059 if (inst
.error
== NULL
)
1060 inst
.error
= (ep
->X_op
== O_absent
1061 ? _("missing expression") :_("bad expression"));
1066 if (seg
!= absolute_section
1067 && seg
!= text_section
1068 && seg
!= data_section
1069 && seg
!= bss_section
1070 && seg
!= undefined_section
)
1072 inst
.error
= _("bad segment");
1073 *str
= input_line_pointer
;
1074 input_line_pointer
= save_in
;
1081 /* Get rid of any bignums now, so that we don't generate an error for which
1082 we can't establish a line number later on. Big numbers are never valid
1083 in instructions, which is where this routine is always called. */
1084 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1085 && (ep
->X_op
== O_big
1086 || (ep
->X_add_symbol
1087 && (walk_no_bignums (ep
->X_add_symbol
)
1089 && walk_no_bignums (ep
->X_op_symbol
))))))
1091 inst
.error
= _("invalid constant");
1092 *str
= input_line_pointer
;
1093 input_line_pointer
= save_in
;
1097 *str
= input_line_pointer
;
1098 input_line_pointer
= save_in
;
1102 /* Turn a string in input_line_pointer into a floating point constant
1103 of type TYPE, and store the appropriate bytes in *LITP. The number
1104 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1105 returned, or NULL on OK.
1107 Note that fp constants aren't represent in the normal way on the ARM.
1108 In big endian mode, things are as expected. However, in little endian
1109 mode fp constants are big-endian word-wise, and little-endian byte-wise
1110 within the words. For example, (double) 1.1 in big endian mode is
1111 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1112 the byte sequence 99 99 f1 3f 9a 99 99 99.
1114 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1117 md_atof (int type
, char * litP
, int * sizeP
)
1120 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1152 return _("Unrecognized or unsupported floating point constant");
1155 t
= atof_ieee (input_line_pointer
, type
, words
);
1157 input_line_pointer
= t
;
1158 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1160 if (target_big_endian
)
1162 for (i
= 0; i
< prec
; i
++)
1164 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1165 litP
+= sizeof (LITTLENUM_TYPE
);
1170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1171 for (i
= prec
- 1; i
>= 0; i
--)
1173 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1174 litP
+= sizeof (LITTLENUM_TYPE
);
1177 /* For a 4 byte float the order of elements in `words' is 1 0.
1178 For an 8 byte float the order is 1 0 3 2. */
1179 for (i
= 0; i
< prec
; i
+= 2)
1181 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1182 sizeof (LITTLENUM_TYPE
));
1183 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1184 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1185 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1192 /* We handle all bad expressions here, so that we can report the faulty
1193 instruction in the error message. */
1196 md_operand (expressionS
* exp
)
1198 if (in_my_get_expression
)
1199 exp
->X_op
= O_illegal
;
1202 /* Immediate values. */
1205 /* Generic immediate-value read function for use in directives.
1206 Accepts anything that 'expression' can fold to a constant.
1207 *val receives the number. */
1210 immediate_for_directive (int *val
)
1213 exp
.X_op
= O_illegal
;
1215 if (is_immediate_prefix (*input_line_pointer
))
1217 input_line_pointer
++;
1221 if (exp
.X_op
!= O_constant
)
1223 as_bad (_("expected #constant"));
1224 ignore_rest_of_line ();
1227 *val
= exp
.X_add_number
;
1232 /* Register parsing. */
1234 /* Generic register parser. CCP points to what should be the
1235 beginning of a register name. If it is indeed a valid register
1236 name, advance CCP over it and return the reg_entry structure;
1237 otherwise return NULL. Does not issue diagnostics. */
1239 static struct reg_entry
*
1240 arm_reg_parse_multi (char **ccp
)
1244 struct reg_entry
*reg
;
1246 skip_whitespace (start
);
1248 #ifdef REGISTER_PREFIX
1249 if (*start
!= REGISTER_PREFIX
)
1253 #ifdef OPTIONAL_REGISTER_PREFIX
1254 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1259 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1264 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1266 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1276 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1277 enum arm_reg_type type
)
1279 /* Alternative syntaxes are accepted for a few register classes. */
1286 /* Generic coprocessor register names are allowed for these. */
1287 if (reg
&& reg
->type
== REG_TYPE_CN
)
1292 /* For backward compatibility, a bare number is valid here. */
1294 unsigned long processor
= strtoul (start
, ccp
, 10);
1295 if (*ccp
!= start
&& processor
<= 15)
1300 case REG_TYPE_MMXWC
:
1301 /* WC includes WCG. ??? I'm not sure this is true for all
1302 instructions that take WC registers. */
1303 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1314 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1315 return value is the register number or FAIL. */
1318 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1321 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1324 /* Do not allow a scalar (reg+index) to parse as a register. */
1325 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1328 if (reg
&& reg
->type
== type
)
1331 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1338 /* Parse a Neon type specifier. *STR should point at the leading '.'
1339 character. Does no verification at this stage that the type fits the opcode
1346 Can all be legally parsed by this function.
1348 Fills in neon_type struct pointer with parsed information, and updates STR
1349 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1350 type, FAIL if not. */
1353 parse_neon_type (struct neon_type
*type
, char **str
)
1360 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1362 enum neon_el_type thistype
= NT_untyped
;
1363 unsigned thissize
= -1u;
1370 /* Just a size without an explicit type. */
1374 switch (TOLOWER (*ptr
))
1376 case 'i': thistype
= NT_integer
; break;
1377 case 'f': thistype
= NT_float
; break;
1378 case 'p': thistype
= NT_poly
; break;
1379 case 's': thistype
= NT_signed
; break;
1380 case 'u': thistype
= NT_unsigned
; break;
1382 thistype
= NT_float
;
1387 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1393 /* .f is an abbreviation for .f32. */
1394 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1399 thissize
= strtoul (ptr
, &ptr
, 10);
1401 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1404 as_bad (_("bad size %d in type specifier"), thissize
);
1412 type
->el
[type
->elems
].type
= thistype
;
1413 type
->el
[type
->elems
].size
= thissize
;
1418 /* Empty/missing type is not a successful parse. */
1419 if (type
->elems
== 0)
1427 /* Errors may be set multiple times during parsing or bit encoding
1428 (particularly in the Neon bits), but usually the earliest error which is set
1429 will be the most meaningful. Avoid overwriting it with later (cascading)
1430 errors by calling this function. */
1433 first_error (const char *err
)
1439 /* Parse a single type, e.g. ".s32", leading period included. */
1441 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1444 struct neon_type optype
;
1448 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1450 if (optype
.elems
== 1)
1451 *vectype
= optype
.el
[0];
1454 first_error (_("only one type should be specified for operand"));
1460 first_error (_("vector type expected"));
1472 /* Special meanings for indices (which have a range of 0-7), which will fit into
1475 #define NEON_ALL_LANES 15
1476 #define NEON_INTERLEAVE_LANES 14
1478 /* Parse either a register or a scalar, with an optional type. Return the
1479 register number, and optionally fill in the actual type of the register
1480 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1481 type/index information in *TYPEINFO. */
1484 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1485 enum arm_reg_type
*rtype
,
1486 struct neon_typed_alias
*typeinfo
)
1489 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1490 struct neon_typed_alias atype
;
1491 struct neon_type_el parsetype
;
1495 atype
.eltype
.type
= NT_invtype
;
1496 atype
.eltype
.size
= -1;
1498 /* Try alternate syntax for some types of register. Note these are mutually
1499 exclusive with the Neon syntax extensions. */
1502 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1510 /* Undo polymorphism when a set of register types may be accepted. */
1511 if ((type
== REG_TYPE_NDQ
1512 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1513 || (type
== REG_TYPE_VFSD
1514 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1515 || (type
== REG_TYPE_NSDQ
1516 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1517 || reg
->type
== REG_TYPE_NQ
))
1518 || (type
== REG_TYPE_NSD
1519 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1520 || (type
== REG_TYPE_MMXWC
1521 && (reg
->type
== REG_TYPE_MMXWCG
)))
1522 type
= (enum arm_reg_type
) reg
->type
;
1524 if (type
!= reg
->type
)
1530 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1532 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1534 first_error (_("can't redefine type for operand"));
1537 atype
.defined
|= NTA_HASTYPE
;
1538 atype
.eltype
= parsetype
;
1541 if (skip_past_char (&str
, '[') == SUCCESS
)
1543 if (type
!= REG_TYPE_VFD
1544 && !(type
== REG_TYPE_VFS
1545 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1547 first_error (_("only D registers may be indexed"));
1551 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1553 first_error (_("can't change index for operand"));
1557 atype
.defined
|= NTA_HASINDEX
;
1559 if (skip_past_char (&str
, ']') == SUCCESS
)
1560 atype
.index
= NEON_ALL_LANES
;
1565 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1567 if (exp
.X_op
!= O_constant
)
1569 first_error (_("constant expression required"));
1573 if (skip_past_char (&str
, ']') == FAIL
)
1576 atype
.index
= exp
.X_add_number
;
1591 /* Like arm_reg_parse, but allow allow the following extra features:
1592 - If RTYPE is non-zero, return the (possibly restricted) type of the
1593 register (e.g. Neon double or quad reg when either has been requested).
1594 - If this is a Neon vector type with additional type information, fill
1595 in the struct pointed to by VECTYPE (if non-NULL).
1596 This function will fault on encountering a scalar. */
1599 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1600 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1602 struct neon_typed_alias atype
;
1604 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1609 /* Do not allow regname(... to parse as a register. */
1613 /* Do not allow a scalar (reg+index) to parse as a register. */
1614 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1616 first_error (_("register operand expected, but got scalar"));
1621 *vectype
= atype
.eltype
;
1628 #define NEON_SCALAR_REG(X) ((X) >> 4)
1629 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1631 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1632 have enough information to be able to do a good job bounds-checking. So, we
1633 just do easy checks here, and do further checks later. */
1636 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1640 struct neon_typed_alias atype
;
1641 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1644 reg_type
= REG_TYPE_VFS
;
1646 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1648 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1651 if (atype
.index
== NEON_ALL_LANES
)
1653 first_error (_("scalar must have an index"));
1656 else if (atype
.index
>= 64 / elsize
)
1658 first_error (_("scalar index out of range"));
1663 *type
= atype
.eltype
;
1667 return reg
* 16 + atype
.index
;
1670 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1673 parse_reg_list (char ** strp
)
1675 char * str
= * strp
;
1679 /* We come back here if we get ranges concatenated by '+' or '|'. */
1682 skip_whitespace (str
);
1696 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1698 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1708 first_error (_("bad range in register list"));
1712 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1714 if (range
& (1 << i
))
1716 (_("Warning: duplicated register (r%d) in register list"),
1724 if (range
& (1 << reg
))
1725 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1727 else if (reg
<= cur_reg
)
1728 as_tsktsk (_("Warning: register range not in ascending order"));
1733 while (skip_past_comma (&str
) != FAIL
1734 || (in_range
= 1, *str
++ == '-'));
1737 if (skip_past_char (&str
, '}') == FAIL
)
1739 first_error (_("missing `}'"));
1747 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1750 if (exp
.X_op
== O_constant
)
1752 if (exp
.X_add_number
1753 != (exp
.X_add_number
& 0x0000ffff))
1755 inst
.error
= _("invalid register mask");
1759 if ((range
& exp
.X_add_number
) != 0)
1761 int regno
= range
& exp
.X_add_number
;
1764 regno
= (1 << regno
) - 1;
1766 (_("Warning: duplicated register (r%d) in register list"),
1770 range
|= exp
.X_add_number
;
1774 if (inst
.reloc
.type
!= 0)
1776 inst
.error
= _("expression too complex");
1780 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1781 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1782 inst
.reloc
.pc_rel
= 0;
1786 if (*str
== '|' || *str
== '+')
1792 while (another_range
);
1798 /* Types of registers in a list. */
1807 /* Parse a VFP register list. If the string is invalid return FAIL.
1808 Otherwise return the number of registers, and set PBASE to the first
1809 register. Parses registers of type ETYPE.
1810 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1811 - Q registers can be used to specify pairs of D registers
1812 - { } can be omitted from around a singleton register list
1813 FIXME: This is not implemented, as it would require backtracking in
1816 This could be done (the meaning isn't really ambiguous), but doesn't
1817 fit in well with the current parsing framework.
1818 - 32 D registers may be used (also true for VFPv3).
1819 FIXME: Types are ignored in these register lists, which is probably a
1823 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1828 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1832 unsigned long mask
= 0;
1835 if (skip_past_char (&str
, '{') == FAIL
)
1837 inst
.error
= _("expecting {");
1844 regtype
= REG_TYPE_VFS
;
1849 regtype
= REG_TYPE_VFD
;
1852 case REGLIST_NEON_D
:
1853 regtype
= REG_TYPE_NDQ
;
1857 if (etype
!= REGLIST_VFP_S
)
1859 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1860 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1864 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1867 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1874 base_reg
= max_regs
;
1878 int setmask
= 1, addregs
= 1;
1880 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1882 if (new_base
== FAIL
)
1884 first_error (_(reg_expected_msgs
[regtype
]));
1888 if (new_base
>= max_regs
)
1890 first_error (_("register out of range in list"));
1894 /* Note: a value of 2 * n is returned for the register Q<n>. */
1895 if (regtype
== REG_TYPE_NQ
)
1901 if (new_base
< base_reg
)
1902 base_reg
= new_base
;
1904 if (mask
& (setmask
<< new_base
))
1906 first_error (_("invalid register list"));
1910 if ((mask
>> new_base
) != 0 && ! warned
)
1912 as_tsktsk (_("register list not in ascending order"));
1916 mask
|= setmask
<< new_base
;
1919 if (*str
== '-') /* We have the start of a range expression */
1925 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1928 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1932 if (high_range
>= max_regs
)
1934 first_error (_("register out of range in list"));
1938 if (regtype
== REG_TYPE_NQ
)
1939 high_range
= high_range
+ 1;
1941 if (high_range
<= new_base
)
1943 inst
.error
= _("register range not in ascending order");
1947 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1949 if (mask
& (setmask
<< new_base
))
1951 inst
.error
= _("invalid register list");
1955 mask
|= setmask
<< new_base
;
1960 while (skip_past_comma (&str
) != FAIL
);
1964 /* Sanity check -- should have raised a parse error above. */
1965 if (count
== 0 || count
> max_regs
)
1970 /* Final test -- the registers must be consecutive. */
1972 for (i
= 0; i
< count
; i
++)
1974 if ((mask
& (1u << i
)) == 0)
1976 inst
.error
= _("non-contiguous register range");
1986 /* True if two alias types are the same. */
1989 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1997 if (a
->defined
!= b
->defined
)
2000 if ((a
->defined
& NTA_HASTYPE
) != 0
2001 && (a
->eltype
.type
!= b
->eltype
.type
2002 || a
->eltype
.size
!= b
->eltype
.size
))
2005 if ((a
->defined
& NTA_HASINDEX
) != 0
2006 && (a
->index
!= b
->index
))
2012 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2013 The base register is put in *PBASE.
2014 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2016 The register stride (minus one) is put in bit 4 of the return value.
2017 Bits [6:5] encode the list length (minus one).
2018 The type of the list elements is put in *ELTYPE, if non-NULL. */
2020 #define NEON_LANE(X) ((X) & 0xf)
2021 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2022 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2025 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2026 struct neon_type_el
*eltype
)
2033 int leading_brace
= 0;
2034 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2035 const char *const incr_error
= _("register stride must be 1 or 2");
2036 const char *const type_error
= _("mismatched element/structure types in list");
2037 struct neon_typed_alias firsttype
;
2038 firsttype
.defined
= 0;
2039 firsttype
.eltype
.type
= NT_invtype
;
2040 firsttype
.eltype
.size
= -1;
2041 firsttype
.index
= -1;
2043 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2048 struct neon_typed_alias atype
;
2049 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2053 first_error (_(reg_expected_msgs
[rtype
]));
2060 if (rtype
== REG_TYPE_NQ
)
2066 else if (reg_incr
== -1)
2068 reg_incr
= getreg
- base_reg
;
2069 if (reg_incr
< 1 || reg_incr
> 2)
2071 first_error (_(incr_error
));
2075 else if (getreg
!= base_reg
+ reg_incr
* count
)
2077 first_error (_(incr_error
));
2081 if (! neon_alias_types_same (&atype
, &firsttype
))
2083 first_error (_(type_error
));
2087 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2091 struct neon_typed_alias htype
;
2092 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2094 lane
= NEON_INTERLEAVE_LANES
;
2095 else if (lane
!= NEON_INTERLEAVE_LANES
)
2097 first_error (_(type_error
));
2102 else if (reg_incr
!= 1)
2104 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2108 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2111 first_error (_(reg_expected_msgs
[rtype
]));
2114 if (! neon_alias_types_same (&htype
, &firsttype
))
2116 first_error (_(type_error
));
2119 count
+= hireg
+ dregs
- getreg
;
2123 /* If we're using Q registers, we can't use [] or [n] syntax. */
2124 if (rtype
== REG_TYPE_NQ
)
2130 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2134 else if (lane
!= atype
.index
)
2136 first_error (_(type_error
));
2140 else if (lane
== -1)
2141 lane
= NEON_INTERLEAVE_LANES
;
2142 else if (lane
!= NEON_INTERLEAVE_LANES
)
2144 first_error (_(type_error
));
2149 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2151 /* No lane set by [x]. We must be interleaving structures. */
2153 lane
= NEON_INTERLEAVE_LANES
;
2156 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2157 || (count
> 1 && reg_incr
== -1))
2159 first_error (_("error parsing element/structure list"));
2163 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2165 first_error (_("expected }"));
2173 *eltype
= firsttype
.eltype
;
2178 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2181 /* Parse an explicit relocation suffix on an expression. This is
2182 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2183 arm_reloc_hsh contains no entries, so this function can only
2184 succeed if there is no () after the word. Returns -1 on error,
2185 BFD_RELOC_UNUSED if there wasn't any suffix. */
2188 parse_reloc (char **str
)
2190 struct reloc_entry
*r
;
2194 return BFD_RELOC_UNUSED
;
2199 while (*q
&& *q
!= ')' && *q
!= ',')
2204 if ((r
= (struct reloc_entry
*)
2205 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2212 /* Directives: register aliases. */
2214 static struct reg_entry
*
2215 insert_reg_alias (char *str
, unsigned number
, int type
)
2217 struct reg_entry
*new_reg
;
2220 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2222 if (new_reg
->builtin
)
2223 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2225 /* Only warn about a redefinition if it's not defined as the
2227 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2228 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2233 name
= xstrdup (str
);
2234 new_reg
= XNEW (struct reg_entry
);
2236 new_reg
->name
= name
;
2237 new_reg
->number
= number
;
2238 new_reg
->type
= type
;
2239 new_reg
->builtin
= FALSE
;
2240 new_reg
->neon
= NULL
;
2242 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2249 insert_neon_reg_alias (char *str
, int number
, int type
,
2250 struct neon_typed_alias
*atype
)
2252 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2256 first_error (_("attempt to redefine typed alias"));
2262 reg
->neon
= XNEW (struct neon_typed_alias
);
2263 *reg
->neon
= *atype
;
2267 /* Look for the .req directive. This is of the form:
2269 new_register_name .req existing_register_name
2271 If we find one, or if it looks sufficiently like one that we want to
2272 handle any error here, return TRUE. Otherwise return FALSE. */
2275 create_register_alias (char * newname
, char *p
)
2277 struct reg_entry
*old
;
2278 char *oldname
, *nbuf
;
2281 /* The input scrubber ensures that whitespace after the mnemonic is
2282 collapsed to single spaces. */
2284 if (strncmp (oldname
, " .req ", 6) != 0)
2288 if (*oldname
== '\0')
2291 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2294 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2298 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2299 the desired alias name, and p points to its end. If not, then
2300 the desired alias name is in the global original_case_string. */
2301 #ifdef TC_CASE_SENSITIVE
2304 newname
= original_case_string
;
2305 nlen
= strlen (newname
);
2308 nbuf
= xmemdup0 (newname
, nlen
);
2310 /* Create aliases under the new name as stated; an all-lowercase
2311 version of the new name; and an all-uppercase version of the new
2313 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2315 for (p
= nbuf
; *p
; p
++)
2318 if (strncmp (nbuf
, newname
, nlen
))
2320 /* If this attempt to create an additional alias fails, do not bother
2321 trying to create the all-lower case alias. We will fail and issue
2322 a second, duplicate error message. This situation arises when the
2323 programmer does something like:
2326 The second .req creates the "Foo" alias but then fails to create
2327 the artificial FOO alias because it has already been created by the
2329 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2336 for (p
= nbuf
; *p
; p
++)
2339 if (strncmp (nbuf
, newname
, nlen
))
2340 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2347 /* Create a Neon typed/indexed register alias using directives, e.g.:
2352 These typed registers can be used instead of the types specified after the
2353 Neon mnemonic, so long as all operands given have types. Types can also be
2354 specified directly, e.g.:
2355 vadd d0.s32, d1.s32, d2.s32 */
2358 create_neon_reg_alias (char *newname
, char *p
)
2360 enum arm_reg_type basetype
;
2361 struct reg_entry
*basereg
;
2362 struct reg_entry mybasereg
;
2363 struct neon_type ntype
;
2364 struct neon_typed_alias typeinfo
;
2365 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2368 typeinfo
.defined
= 0;
2369 typeinfo
.eltype
.type
= NT_invtype
;
2370 typeinfo
.eltype
.size
= -1;
2371 typeinfo
.index
= -1;
2375 if (strncmp (p
, " .dn ", 5) == 0)
2376 basetype
= REG_TYPE_VFD
;
2377 else if (strncmp (p
, " .qn ", 5) == 0)
2378 basetype
= REG_TYPE_NQ
;
2387 basereg
= arm_reg_parse_multi (&p
);
2389 if (basereg
&& basereg
->type
!= basetype
)
2391 as_bad (_("bad type for register"));
2395 if (basereg
== NULL
)
2398 /* Try parsing as an integer. */
2399 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2400 if (exp
.X_op
!= O_constant
)
2402 as_bad (_("expression must be constant"));
2405 basereg
= &mybasereg
;
2406 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2412 typeinfo
= *basereg
->neon
;
2414 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2416 /* We got a type. */
2417 if (typeinfo
.defined
& NTA_HASTYPE
)
2419 as_bad (_("can't redefine the type of a register alias"));
2423 typeinfo
.defined
|= NTA_HASTYPE
;
2424 if (ntype
.elems
!= 1)
2426 as_bad (_("you must specify a single type only"));
2429 typeinfo
.eltype
= ntype
.el
[0];
2432 if (skip_past_char (&p
, '[') == SUCCESS
)
2435 /* We got a scalar index. */
2437 if (typeinfo
.defined
& NTA_HASINDEX
)
2439 as_bad (_("can't redefine the index of a scalar alias"));
2443 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2445 if (exp
.X_op
!= O_constant
)
2447 as_bad (_("scalar index must be constant"));
2451 typeinfo
.defined
|= NTA_HASINDEX
;
2452 typeinfo
.index
= exp
.X_add_number
;
2454 if (skip_past_char (&p
, ']') == FAIL
)
2456 as_bad (_("expecting ]"));
2461 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2462 the desired alias name, and p points to its end. If not, then
2463 the desired alias name is in the global original_case_string. */
2464 #ifdef TC_CASE_SENSITIVE
2465 namelen
= nameend
- newname
;
2467 newname
= original_case_string
;
2468 namelen
= strlen (newname
);
2471 namebuf
= xmemdup0 (newname
, namelen
);
2473 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2474 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2476 /* Insert name in all uppercase. */
2477 for (p
= namebuf
; *p
; p
++)
2480 if (strncmp (namebuf
, newname
, namelen
))
2481 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2482 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2484 /* Insert name in all lowercase. */
2485 for (p
= namebuf
; *p
; p
++)
2488 if (strncmp (namebuf
, newname
, namelen
))
2489 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2490 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2496 /* Should never be called, as .req goes between the alias and the
2497 register name, not at the beginning of the line. */
2500 s_req (int a ATTRIBUTE_UNUSED
)
2502 as_bad (_("invalid syntax for .req directive"));
2506 s_dn (int a ATTRIBUTE_UNUSED
)
2508 as_bad (_("invalid syntax for .dn directive"));
2512 s_qn (int a ATTRIBUTE_UNUSED
)
2514 as_bad (_("invalid syntax for .qn directive"));
2517 /* The .unreq directive deletes an alias which was previously defined
2518 by .req. For example:
2524 s_unreq (int a ATTRIBUTE_UNUSED
)
2529 name
= input_line_pointer
;
2531 while (*input_line_pointer
!= 0
2532 && *input_line_pointer
!= ' '
2533 && *input_line_pointer
!= '\n')
2534 ++input_line_pointer
;
2536 saved_char
= *input_line_pointer
;
2537 *input_line_pointer
= 0;
2540 as_bad (_("invalid syntax for .unreq directive"));
2543 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2547 as_bad (_("unknown register alias '%s'"), name
);
2548 else if (reg
->builtin
)
2549 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2556 hash_delete (arm_reg_hsh
, name
, FALSE
);
2557 free ((char *) reg
->name
);
2562 /* Also locate the all upper case and all lower case versions.
2563 Do not complain if we cannot find one or the other as it
2564 was probably deleted above. */
2566 nbuf
= strdup (name
);
2567 for (p
= nbuf
; *p
; p
++)
2569 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2572 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2573 free ((char *) reg
->name
);
2579 for (p
= nbuf
; *p
; p
++)
2581 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2584 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2585 free ((char *) reg
->name
);
2595 *input_line_pointer
= saved_char
;
2596 demand_empty_rest_of_line ();
2599 /* Directives: Instruction set selection. */
2602 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2603 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2604 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2605 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2607 /* Create a new mapping symbol for the transition to STATE. */
2610 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2613 const char * symname
;
2620 type
= BSF_NO_FLAGS
;
2624 type
= BSF_NO_FLAGS
;
2628 type
= BSF_NO_FLAGS
;
2634 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2635 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2640 THUMB_SET_FUNC (symbolP
, 0);
2641 ARM_SET_THUMB (symbolP
, 0);
2642 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2646 THUMB_SET_FUNC (symbolP
, 1);
2647 ARM_SET_THUMB (symbolP
, 1);
2648 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2656 /* Save the mapping symbols for future reference. Also check that
2657 we do not place two mapping symbols at the same offset within a
2658 frag. We'll handle overlap between frags in
2659 check_mapping_symbols.
2661 If .fill or other data filling directive generates zero sized data,
2662 the mapping symbol for the following code will have the same value
2663 as the one generated for the data filling directive. In this case,
2664 we replace the old symbol with the new one at the same address. */
2667 if (frag
->tc_frag_data
.first_map
!= NULL
)
2669 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2670 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2672 frag
->tc_frag_data
.first_map
= symbolP
;
2674 if (frag
->tc_frag_data
.last_map
!= NULL
)
2676 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2677 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2678 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2680 frag
->tc_frag_data
.last_map
= symbolP
;
2683 /* We must sometimes convert a region marked as code to data during
2684 code alignment, if an odd number of bytes have to be padded. The
2685 code mapping symbol is pushed to an aligned address. */
2688 insert_data_mapping_symbol (enum mstate state
,
2689 valueT value
, fragS
*frag
, offsetT bytes
)
2691 /* If there was already a mapping symbol, remove it. */
2692 if (frag
->tc_frag_data
.last_map
!= NULL
2693 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2695 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2699 know (frag
->tc_frag_data
.first_map
== symp
);
2700 frag
->tc_frag_data
.first_map
= NULL
;
2702 frag
->tc_frag_data
.last_map
= NULL
;
2703 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2706 make_mapping_symbol (MAP_DATA
, value
, frag
);
2707 make_mapping_symbol (state
, value
+ bytes
, frag
);
2710 static void mapping_state_2 (enum mstate state
, int max_chars
);
2712 /* Set the mapping state to STATE. Only call this when about to
2713 emit some STATE bytes to the file. */
2715 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2717 mapping_state (enum mstate state
)
2719 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2721 if (mapstate
== state
)
2722 /* The mapping symbol has already been emitted.
2723 There is nothing else to do. */
2726 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2728 All ARM instructions require 4-byte alignment.
2729 (Almost) all Thumb instructions require 2-byte alignment.
2731 When emitting instructions into any section, mark the section
2734 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2735 but themselves require 2-byte alignment; this applies to some
2736 PC- relative forms. However, these cases will involve implicit
2737 literal pool generation or an explicit .align >=2, both of
2738 which will cause the section to me marked with sufficient
2739 alignment. Thus, we don't handle those cases here. */
2740 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2743 /* This case will be evaluated later. */
2746 mapping_state_2 (state
, 0);
2749 /* Same as mapping_state, but MAX_CHARS bytes have already been
2750 allocated. Put the mapping symbol that far back. */
2753 mapping_state_2 (enum mstate state
, int max_chars
)
2755 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2757 if (!SEG_NORMAL (now_seg
))
2760 if (mapstate
== state
)
2761 /* The mapping symbol has already been emitted.
2762 There is nothing else to do. */
2765 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2766 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2768 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2769 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2772 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2775 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2776 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2780 #define mapping_state(x) ((void)0)
2781 #define mapping_state_2(x, y) ((void)0)
2784 /* Find the real, Thumb encoded start of a Thumb function. */
2788 find_real_start (symbolS
* symbolP
)
2791 const char * name
= S_GET_NAME (symbolP
);
2792 symbolS
* new_target
;
2794 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2795 #define STUB_NAME ".real_start_of"
2800 /* The compiler may generate BL instructions to local labels because
2801 it needs to perform a branch to a far away location. These labels
2802 do not have a corresponding ".real_start_of" label. We check
2803 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2804 the ".real_start_of" convention for nonlocal branches. */
2805 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2808 real_start
= concat (STUB_NAME
, name
, NULL
);
2809 new_target
= symbol_find (real_start
);
2812 if (new_target
== NULL
)
2814 as_warn (_("Failed to find real start of function: %s\n"), name
);
2815 new_target
= symbolP
;
2823 opcode_select (int width
)
2830 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2831 as_bad (_("selected processor does not support THUMB opcodes"));
2834 /* No need to force the alignment, since we will have been
2835 coming from ARM mode, which is word-aligned. */
2836 record_alignment (now_seg
, 1);
2843 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2844 as_bad (_("selected processor does not support ARM opcodes"));
2849 frag_align (2, 0, 0);
2851 record_alignment (now_seg
, 1);
2856 as_bad (_("invalid instruction size selected (%d)"), width
);
2861 s_arm (int ignore ATTRIBUTE_UNUSED
)
2864 demand_empty_rest_of_line ();
2868 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2871 demand_empty_rest_of_line ();
2875 s_code (int unused ATTRIBUTE_UNUSED
)
2879 temp
= get_absolute_expression ();
2884 opcode_select (temp
);
2888 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2893 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2895 /* If we are not already in thumb mode go into it, EVEN if
2896 the target processor does not support thumb instructions.
2897 This is used by gcc/config/arm/lib1funcs.asm for example
2898 to compile interworking support functions even if the
2899 target processor should not support interworking. */
2903 record_alignment (now_seg
, 1);
2906 demand_empty_rest_of_line ();
2910 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2914 /* The following label is the name/address of the start of a Thumb function.
2915 We need to know this for the interworking support. */
2916 label_is_thumb_function_name
= TRUE
;
2919 /* Perform a .set directive, but also mark the alias as
2920 being a thumb function. */
2923 s_thumb_set (int equiv
)
2925 /* XXX the following is a duplicate of the code for s_set() in read.c
2926 We cannot just call that code as we need to get at the symbol that
2933 /* Especial apologies for the random logic:
2934 This just grew, and could be parsed much more simply!
2936 delim
= get_symbol_name (& name
);
2937 end_name
= input_line_pointer
;
2938 (void) restore_line_pointer (delim
);
2940 if (*input_line_pointer
!= ',')
2943 as_bad (_("expected comma after name \"%s\""), name
);
2945 ignore_rest_of_line ();
2949 input_line_pointer
++;
2952 if (name
[0] == '.' && name
[1] == '\0')
2954 /* XXX - this should not happen to .thumb_set. */
2958 if ((symbolP
= symbol_find (name
)) == NULL
2959 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2962 /* When doing symbol listings, play games with dummy fragments living
2963 outside the normal fragment chain to record the file and line info
2965 if (listing
& LISTING_SYMBOLS
)
2967 extern struct list_info_struct
* listing_tail
;
2968 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2970 memset (dummy_frag
, 0, sizeof (fragS
));
2971 dummy_frag
->fr_type
= rs_fill
;
2972 dummy_frag
->line
= listing_tail
;
2973 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2974 dummy_frag
->fr_symbol
= symbolP
;
2978 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2981 /* "set" symbols are local unless otherwise specified. */
2982 SF_SET_LOCAL (symbolP
);
2983 #endif /* OBJ_COFF */
2984 } /* Make a new symbol. */
2986 symbol_table_insert (symbolP
);
2991 && S_IS_DEFINED (symbolP
)
2992 && S_GET_SEGMENT (symbolP
) != reg_section
)
2993 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2995 pseudo_set (symbolP
);
2997 demand_empty_rest_of_line ();
2999 /* XXX Now we come to the Thumb specific bit of code. */
3001 THUMB_SET_FUNC (symbolP
, 1);
3002 ARM_SET_THUMB (symbolP
, 1);
3003 #if defined OBJ_ELF || defined OBJ_COFF
3004 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3008 /* Directives: Mode selection. */
3010 /* .syntax [unified|divided] - choose the new unified syntax
3011 (same for Arm and Thumb encoding, modulo slight differences in what
3012 can be represented) or the old divergent syntax for each mode. */
3014 s_syntax (int unused ATTRIBUTE_UNUSED
)
3018 delim
= get_symbol_name (& name
);
3020 if (!strcasecmp (name
, "unified"))
3021 unified_syntax
= TRUE
;
3022 else if (!strcasecmp (name
, "divided"))
3023 unified_syntax
= FALSE
;
3026 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3029 (void) restore_line_pointer (delim
);
3030 demand_empty_rest_of_line ();
3033 /* Directives: sectioning and alignment. */
3036 s_bss (int ignore ATTRIBUTE_UNUSED
)
3038 /* We don't support putting frags in the BSS segment, we fake it by
3039 marking in_bss, then looking at s_skip for clues. */
3040 subseg_set (bss_section
, 0);
3041 demand_empty_rest_of_line ();
3043 #ifdef md_elf_section_change_hook
3044 md_elf_section_change_hook ();
3049 s_even (int ignore ATTRIBUTE_UNUSED
)
3051 /* Never make frag if expect extra pass. */
3053 frag_align (1, 0, 0);
3055 record_alignment (now_seg
, 1);
3057 demand_empty_rest_of_line ();
3060 /* Directives: CodeComposer Studio. */
3062 /* .ref (for CodeComposer Studio syntax only). */
3064 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3066 if (codecomposer_syntax
)
3067 ignore_rest_of_line ();
3069 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3072 /* If name is not NULL, then it is used for marking the beginning of a
3073 function, whereas if it is NULL then it means the function end. */
3075 asmfunc_debug (const char * name
)
3077 static const char * last_name
= NULL
;
3081 gas_assert (last_name
== NULL
);
3084 if (debug_type
== DEBUG_STABS
)
3085 stabs_generate_asm_func (name
, name
);
3089 gas_assert (last_name
!= NULL
);
3091 if (debug_type
== DEBUG_STABS
)
3092 stabs_generate_asm_endfunc (last_name
, last_name
);
3099 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3101 if (codecomposer_syntax
)
3103 switch (asmfunc_state
)
3105 case OUTSIDE_ASMFUNC
:
3106 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3109 case WAITING_ASMFUNC_NAME
:
3110 as_bad (_(".asmfunc repeated."));
3113 case WAITING_ENDASMFUNC
:
3114 as_bad (_(".asmfunc without function."));
3117 demand_empty_rest_of_line ();
3120 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3124 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3126 if (codecomposer_syntax
)
3128 switch (asmfunc_state
)
3130 case OUTSIDE_ASMFUNC
:
3131 as_bad (_(".endasmfunc without a .asmfunc."));
3134 case WAITING_ASMFUNC_NAME
:
3135 as_bad (_(".endasmfunc without function."));
3138 case WAITING_ENDASMFUNC
:
3139 asmfunc_state
= OUTSIDE_ASMFUNC
;
3140 asmfunc_debug (NULL
);
3143 demand_empty_rest_of_line ();
3146 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3150 s_ccs_def (int name
)
3152 if (codecomposer_syntax
)
3155 as_bad (_(".def pseudo-op only available with -mccs flag."));
3158 /* Directives: Literal pools. */
3160 static literal_pool
*
3161 find_literal_pool (void)
3163 literal_pool
* pool
;
3165 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3167 if (pool
->section
== now_seg
3168 && pool
->sub_section
== now_subseg
)
3175 static literal_pool
*
3176 find_or_make_literal_pool (void)
3178 /* Next literal pool ID number. */
3179 static unsigned int latest_pool_num
= 1;
3180 literal_pool
* pool
;
3182 pool
= find_literal_pool ();
3186 /* Create a new pool. */
3187 pool
= XNEW (literal_pool
);
3191 pool
->next_free_entry
= 0;
3192 pool
->section
= now_seg
;
3193 pool
->sub_section
= now_subseg
;
3194 pool
->next
= list_of_pools
;
3195 pool
->symbol
= NULL
;
3196 pool
->alignment
= 2;
3198 /* Add it to the list. */
3199 list_of_pools
= pool
;
3202 /* New pools, and emptied pools, will have a NULL symbol. */
3203 if (pool
->symbol
== NULL
)
3205 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3206 (valueT
) 0, &zero_address_frag
);
3207 pool
->id
= latest_pool_num
++;
3214 /* Add the literal in the global 'inst'
3215 structure to the relevant literal pool. */
3218 add_to_lit_pool (unsigned int nbytes
)
3220 #define PADDING_SLOT 0x1
3221 #define LIT_ENTRY_SIZE_MASK 0xFF
3222 literal_pool
* pool
;
3223 unsigned int entry
, pool_size
= 0;
3224 bfd_boolean padding_slot_p
= FALSE
;
3230 imm1
= inst
.operands
[1].imm
;
3231 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3232 : inst
.reloc
.exp
.X_unsigned
? 0
3233 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3234 if (target_big_endian
)
3237 imm2
= inst
.operands
[1].imm
;
3241 pool
= find_or_make_literal_pool ();
3243 /* Check if this literal value is already in the pool. */
3244 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3248 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3249 && (inst
.reloc
.exp
.X_op
== O_constant
)
3250 && (pool
->literals
[entry
].X_add_number
3251 == inst
.reloc
.exp
.X_add_number
)
3252 && (pool
->literals
[entry
].X_md
== nbytes
)
3253 && (pool
->literals
[entry
].X_unsigned
3254 == inst
.reloc
.exp
.X_unsigned
))
3257 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3258 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3259 && (pool
->literals
[entry
].X_add_number
3260 == inst
.reloc
.exp
.X_add_number
)
3261 && (pool
->literals
[entry
].X_add_symbol
3262 == inst
.reloc
.exp
.X_add_symbol
)
3263 && (pool
->literals
[entry
].X_op_symbol
3264 == inst
.reloc
.exp
.X_op_symbol
)
3265 && (pool
->literals
[entry
].X_md
== nbytes
))
3268 else if ((nbytes
== 8)
3269 && !(pool_size
& 0x7)
3270 && ((entry
+ 1) != pool
->next_free_entry
)
3271 && (pool
->literals
[entry
].X_op
== O_constant
)
3272 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3273 && (pool
->literals
[entry
].X_unsigned
3274 == inst
.reloc
.exp
.X_unsigned
)
3275 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3276 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3277 && (pool
->literals
[entry
+ 1].X_unsigned
3278 == inst
.reloc
.exp
.X_unsigned
))
3281 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3282 if (padding_slot_p
&& (nbytes
== 4))
3288 /* Do we need to create a new entry? */
3289 if (entry
== pool
->next_free_entry
)
3291 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3293 inst
.error
= _("literal pool overflow");
3299 /* For 8-byte entries, we align to an 8-byte boundary,
3300 and split it into two 4-byte entries, because on 32-bit
3301 host, 8-byte constants are treated as big num, thus
3302 saved in "generic_bignum" which will be overwritten
3303 by later assignments.
3305 We also need to make sure there is enough space for
3308 We also check to make sure the literal operand is a
3310 if (!(inst
.reloc
.exp
.X_op
== O_constant
3311 || inst
.reloc
.exp
.X_op
== O_big
))
3313 inst
.error
= _("invalid type for literal pool");
3316 else if (pool_size
& 0x7)
3318 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3320 inst
.error
= _("literal pool overflow");
3324 pool
->literals
[entry
] = inst
.reloc
.exp
;
3325 pool
->literals
[entry
].X_op
= O_constant
;
3326 pool
->literals
[entry
].X_add_number
= 0;
3327 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3328 pool
->next_free_entry
+= 1;
3331 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3333 inst
.error
= _("literal pool overflow");
3337 pool
->literals
[entry
] = inst
.reloc
.exp
;
3338 pool
->literals
[entry
].X_op
= O_constant
;
3339 pool
->literals
[entry
].X_add_number
= imm1
;
3340 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3341 pool
->literals
[entry
++].X_md
= 4;
3342 pool
->literals
[entry
] = inst
.reloc
.exp
;
3343 pool
->literals
[entry
].X_op
= O_constant
;
3344 pool
->literals
[entry
].X_add_number
= imm2
;
3345 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3346 pool
->literals
[entry
].X_md
= 4;
3347 pool
->alignment
= 3;
3348 pool
->next_free_entry
+= 1;
3352 pool
->literals
[entry
] = inst
.reloc
.exp
;
3353 pool
->literals
[entry
].X_md
= 4;
3357 /* PR ld/12974: Record the location of the first source line to reference
3358 this entry in the literal pool. If it turns out during linking that the
3359 symbol does not exist we will be able to give an accurate line number for
3360 the (first use of the) missing reference. */
3361 if (debug_type
== DEBUG_DWARF2
)
3362 dwarf2_where (pool
->locs
+ entry
);
3364 pool
->next_free_entry
+= 1;
3366 else if (padding_slot_p
)
3368 pool
->literals
[entry
] = inst
.reloc
.exp
;
3369 pool
->literals
[entry
].X_md
= nbytes
;
3372 inst
.reloc
.exp
.X_op
= O_symbol
;
3373 inst
.reloc
.exp
.X_add_number
= pool_size
;
3374 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3380 tc_start_label_without_colon (void)
3382 bfd_boolean ret
= TRUE
;
3384 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3386 const char *label
= input_line_pointer
;
3388 while (!is_end_of_line
[(int) label
[-1]])
3393 as_bad (_("Invalid label '%s'"), label
);
3397 asmfunc_debug (label
);
3399 asmfunc_state
= WAITING_ENDASMFUNC
;
3405 /* Can't use symbol_new here, so have to create a symbol and then at
3406 a later date assign it a value. That's what these functions do. */
3409 symbol_locate (symbolS
* symbolP
,
3410 const char * name
, /* It is copied, the caller can modify. */
3411 segT segment
, /* Segment identifier (SEG_<something>). */
3412 valueT valu
, /* Symbol value. */
3413 fragS
* frag
) /* Associated fragment. */
3416 char * preserved_copy_of_name
;
3418 name_length
= strlen (name
) + 1; /* +1 for \0. */
3419 obstack_grow (¬es
, name
, name_length
);
3420 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3422 #ifdef tc_canonicalize_symbol_name
3423 preserved_copy_of_name
=
3424 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3427 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3429 S_SET_SEGMENT (symbolP
, segment
);
3430 S_SET_VALUE (symbolP
, valu
);
3431 symbol_clear_list_pointers (symbolP
);
3433 symbol_set_frag (symbolP
, frag
);
3435 /* Link to end of symbol chain. */
3437 extern int symbol_table_frozen
;
3439 if (symbol_table_frozen
)
3443 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3445 obj_symbol_new_hook (symbolP
);
3447 #ifdef tc_symbol_new_hook
3448 tc_symbol_new_hook (symbolP
);
3452 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3453 #endif /* DEBUG_SYMS */
3457 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3460 literal_pool
* pool
;
3463 pool
= find_literal_pool ();
3465 || pool
->symbol
== NULL
3466 || pool
->next_free_entry
== 0)
3469 /* Align pool as you have word accesses.
3470 Only make a frag if we have to. */
3472 frag_align (pool
->alignment
, 0, 0);
3474 record_alignment (now_seg
, 2);
3477 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3478 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3480 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3482 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3483 (valueT
) frag_now_fix (), frag_now
);
3484 symbol_table_insert (pool
->symbol
);
3486 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3488 #if defined OBJ_COFF || defined OBJ_ELF
3489 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3492 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3495 if (debug_type
== DEBUG_DWARF2
)
3496 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3498 /* First output the expression in the instruction to the pool. */
3499 emit_expr (&(pool
->literals
[entry
]),
3500 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3503 /* Mark the pool as empty. */
3504 pool
->next_free_entry
= 0;
3505 pool
->symbol
= NULL
;
3509 /* Forward declarations for functions below, in the MD interface
3511 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3512 static valueT
create_unwind_entry (int);
3513 static void start_unwind_section (const segT
, int);
3514 static void add_unwind_opcode (valueT
, int);
3515 static void flush_pending_unwind (void);
3517 /* Directives: Data. */
3520 s_arm_elf_cons (int nbytes
)
3524 #ifdef md_flush_pending_output
3525 md_flush_pending_output ();
3528 if (is_it_end_of_statement ())
3530 demand_empty_rest_of_line ();
3534 #ifdef md_cons_align
3535 md_cons_align (nbytes
);
3538 mapping_state (MAP_DATA
);
3542 char *base
= input_line_pointer
;
3546 if (exp
.X_op
!= O_symbol
)
3547 emit_expr (&exp
, (unsigned int) nbytes
);
3550 char *before_reloc
= input_line_pointer
;
3551 reloc
= parse_reloc (&input_line_pointer
);
3554 as_bad (_("unrecognized relocation suffix"));
3555 ignore_rest_of_line ();
3558 else if (reloc
== BFD_RELOC_UNUSED
)
3559 emit_expr (&exp
, (unsigned int) nbytes
);
3562 reloc_howto_type
*howto
= (reloc_howto_type
*)
3563 bfd_reloc_type_lookup (stdoutput
,
3564 (bfd_reloc_code_real_type
) reloc
);
3565 int size
= bfd_get_reloc_size (howto
);
3567 if (reloc
== BFD_RELOC_ARM_PLT32
)
3569 as_bad (_("(plt) is only valid on branch targets"));
3570 reloc
= BFD_RELOC_UNUSED
;
3575 as_bad (ngettext ("%s relocations do not fit in %d byte",
3576 "%s relocations do not fit in %d bytes",
3578 howto
->name
, nbytes
);
3581 /* We've parsed an expression stopping at O_symbol.
3582 But there may be more expression left now that we
3583 have parsed the relocation marker. Parse it again.
3584 XXX Surely there is a cleaner way to do this. */
3585 char *p
= input_line_pointer
;
3587 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3589 memcpy (save_buf
, base
, input_line_pointer
- base
);
3590 memmove (base
+ (input_line_pointer
- before_reloc
),
3591 base
, before_reloc
- base
);
3593 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3595 memcpy (base
, save_buf
, p
- base
);
3597 offset
= nbytes
- size
;
3598 p
= frag_more (nbytes
);
3599 memset (p
, 0, nbytes
);
3600 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3601 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3607 while (*input_line_pointer
++ == ',');
3609 /* Put terminator back into stream. */
3610 input_line_pointer
--;
3611 demand_empty_rest_of_line ();
3614 /* Emit an expression containing a 32-bit thumb instruction.
3615 Implementation based on put_thumb32_insn. */
3618 emit_thumb32_expr (expressionS
* exp
)
3620 expressionS exp_high
= *exp
;
3622 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3623 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3624 exp
->X_add_number
&= 0xffff;
3625 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3628 /* Guess the instruction size based on the opcode. */
3631 thumb_insn_size (int opcode
)
3633 if ((unsigned int) opcode
< 0xe800u
)
3635 else if ((unsigned int) opcode
>= 0xe8000000u
)
3642 emit_insn (expressionS
*exp
, int nbytes
)
3646 if (exp
->X_op
== O_constant
)
3651 size
= thumb_insn_size (exp
->X_add_number
);
3655 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3657 as_bad (_(".inst.n operand too big. "\
3658 "Use .inst.w instead"));
3663 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3664 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3666 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3668 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3669 emit_thumb32_expr (exp
);
3671 emit_expr (exp
, (unsigned int) size
);
3673 it_fsm_post_encode ();
3677 as_bad (_("cannot determine Thumb instruction size. " \
3678 "Use .inst.n/.inst.w instead"));
3681 as_bad (_("constant expression required"));
3686 /* Like s_arm_elf_cons but do not use md_cons_align and
3687 set the mapping state to MAP_ARM/MAP_THUMB. */
3690 s_arm_elf_inst (int nbytes
)
3692 if (is_it_end_of_statement ())
3694 demand_empty_rest_of_line ();
3698 /* Calling mapping_state () here will not change ARM/THUMB,
3699 but will ensure not to be in DATA state. */
3702 mapping_state (MAP_THUMB
);
3707 as_bad (_("width suffixes are invalid in ARM mode"));
3708 ignore_rest_of_line ();
3714 mapping_state (MAP_ARM
);
3723 if (! emit_insn (& exp
, nbytes
))
3725 ignore_rest_of_line ();
3729 while (*input_line_pointer
++ == ',');
3731 /* Put terminator back into stream. */
3732 input_line_pointer
--;
3733 demand_empty_rest_of_line ();
3736 /* Parse a .rel31 directive. */
3739 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3746 if (*input_line_pointer
== '1')
3747 highbit
= 0x80000000;
3748 else if (*input_line_pointer
!= '0')
3749 as_bad (_("expected 0 or 1"));
3751 input_line_pointer
++;
3752 if (*input_line_pointer
!= ',')
3753 as_bad (_("missing comma"));
3754 input_line_pointer
++;
3756 #ifdef md_flush_pending_output
3757 md_flush_pending_output ();
3760 #ifdef md_cons_align
3764 mapping_state (MAP_DATA
);
3769 md_number_to_chars (p
, highbit
, 4);
3770 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3771 BFD_RELOC_ARM_PREL31
);
3773 demand_empty_rest_of_line ();
3776 /* Directives: AEABI stack-unwind tables. */
3778 /* Parse an unwind_fnstart directive. Simply records the current location. */
3781 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3783 demand_empty_rest_of_line ();
3784 if (unwind
.proc_start
)
3786 as_bad (_("duplicate .fnstart directive"));
3790 /* Mark the start of the function. */
3791 unwind
.proc_start
= expr_build_dot ();
3793 /* Reset the rest of the unwind info. */
3794 unwind
.opcode_count
= 0;
3795 unwind
.table_entry
= NULL
;
3796 unwind
.personality_routine
= NULL
;
3797 unwind
.personality_index
= -1;
3798 unwind
.frame_size
= 0;
3799 unwind
.fp_offset
= 0;
3800 unwind
.fp_reg
= REG_SP
;
3802 unwind
.sp_restored
= 0;
3806 /* Parse a handlerdata directive. Creates the exception handling table entry
3807 for the function. */
3810 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3812 demand_empty_rest_of_line ();
3813 if (!unwind
.proc_start
)
3814 as_bad (MISSING_FNSTART
);
3816 if (unwind
.table_entry
)
3817 as_bad (_("duplicate .handlerdata directive"));
3819 create_unwind_entry (1);
3822 /* Parse an unwind_fnend directive. Generates the index table entry. */
3825 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3830 unsigned int marked_pr_dependency
;
3832 demand_empty_rest_of_line ();
3834 if (!unwind
.proc_start
)
3836 as_bad (_(".fnend directive without .fnstart"));
3840 /* Add eh table entry. */
3841 if (unwind
.table_entry
== NULL
)
3842 val
= create_unwind_entry (0);
3846 /* Add index table entry. This is two words. */
3847 start_unwind_section (unwind
.saved_seg
, 1);
3848 frag_align (2, 0, 0);
3849 record_alignment (now_seg
, 2);
3851 ptr
= frag_more (8);
3853 where
= frag_now_fix () - 8;
3855 /* Self relative offset of the function start. */
3856 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3857 BFD_RELOC_ARM_PREL31
);
3859 /* Indicate dependency on EHABI-defined personality routines to the
3860 linker, if it hasn't been done already. */
3861 marked_pr_dependency
3862 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3863 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3864 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3866 static const char *const name
[] =
3868 "__aeabi_unwind_cpp_pr0",
3869 "__aeabi_unwind_cpp_pr1",
3870 "__aeabi_unwind_cpp_pr2"
3872 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3873 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3874 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3875 |= 1 << unwind
.personality_index
;
3879 /* Inline exception table entry. */
3880 md_number_to_chars (ptr
+ 4, val
, 4);
3882 /* Self relative offset of the table entry. */
3883 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3884 BFD_RELOC_ARM_PREL31
);
3886 /* Restore the original section. */
3887 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3889 unwind
.proc_start
= NULL
;
3893 /* Parse an unwind_cantunwind directive. */
3896 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3898 demand_empty_rest_of_line ();
3899 if (!unwind
.proc_start
)
3900 as_bad (MISSING_FNSTART
);
3902 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3903 as_bad (_("personality routine specified for cantunwind frame"));
3905 unwind
.personality_index
= -2;
3909 /* Parse a personalityindex directive. */
3912 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3916 if (!unwind
.proc_start
)
3917 as_bad (MISSING_FNSTART
);
3919 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3920 as_bad (_("duplicate .personalityindex directive"));
3924 if (exp
.X_op
!= O_constant
3925 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3927 as_bad (_("bad personality routine number"));
3928 ignore_rest_of_line ();
3932 unwind
.personality_index
= exp
.X_add_number
;
3934 demand_empty_rest_of_line ();
3938 /* Parse a personality directive. */
3941 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3945 if (!unwind
.proc_start
)
3946 as_bad (MISSING_FNSTART
);
3948 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3949 as_bad (_("duplicate .personality directive"));
3951 c
= get_symbol_name (& name
);
3952 p
= input_line_pointer
;
3954 ++ input_line_pointer
;
3955 unwind
.personality_routine
= symbol_find_or_make (name
);
3957 demand_empty_rest_of_line ();
3961 /* Parse a directive saving core registers. */
3964 s_arm_unwind_save_core (void)
3970 range
= parse_reg_list (&input_line_pointer
);
3973 as_bad (_("expected register list"));
3974 ignore_rest_of_line ();
3978 demand_empty_rest_of_line ();
3980 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3981 into .unwind_save {..., sp...}. We aren't bothered about the value of
3982 ip because it is clobbered by calls. */
3983 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3984 && (range
& 0x3000) == 0x1000)
3986 unwind
.opcode_count
--;
3987 unwind
.sp_restored
= 0;
3988 range
= (range
| 0x2000) & ~0x1000;
3989 unwind
.pending_offset
= 0;
3995 /* See if we can use the short opcodes. These pop a block of up to 8
3996 registers starting with r4, plus maybe r14. */
3997 for (n
= 0; n
< 8; n
++)
3999 /* Break at the first non-saved register. */
4000 if ((range
& (1 << (n
+ 4))) == 0)
4003 /* See if there are any other bits set. */
4004 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4006 /* Use the long form. */
4007 op
= 0x8000 | ((range
>> 4) & 0xfff);
4008 add_unwind_opcode (op
, 2);
4012 /* Use the short form. */
4014 op
= 0xa8; /* Pop r14. */
4016 op
= 0xa0; /* Do not pop r14. */
4018 add_unwind_opcode (op
, 1);
4025 op
= 0xb100 | (range
& 0xf);
4026 add_unwind_opcode (op
, 2);
4029 /* Record the number of bytes pushed. */
4030 for (n
= 0; n
< 16; n
++)
4032 if (range
& (1 << n
))
4033 unwind
.frame_size
+= 4;
4038 /* Parse a directive saving FPA registers. */
4041 s_arm_unwind_save_fpa (int reg
)
4047 /* Get Number of registers to transfer. */
4048 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4051 exp
.X_op
= O_illegal
;
4053 if (exp
.X_op
!= O_constant
)
4055 as_bad (_("expected , <constant>"));
4056 ignore_rest_of_line ();
4060 num_regs
= exp
.X_add_number
;
4062 if (num_regs
< 1 || num_regs
> 4)
4064 as_bad (_("number of registers must be in the range [1:4]"));
4065 ignore_rest_of_line ();
4069 demand_empty_rest_of_line ();
4074 op
= 0xb4 | (num_regs
- 1);
4075 add_unwind_opcode (op
, 1);
4080 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4081 add_unwind_opcode (op
, 2);
4083 unwind
.frame_size
+= num_regs
* 12;
4087 /* Parse a directive saving VFP registers for ARMv6 and above. */
4090 s_arm_unwind_save_vfp_armv6 (void)
4095 int num_vfpv3_regs
= 0;
4096 int num_regs_below_16
;
4098 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4101 as_bad (_("expected register list"));
4102 ignore_rest_of_line ();
4106 demand_empty_rest_of_line ();
4108 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4109 than FSTMX/FLDMX-style ones). */
4111 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4113 num_vfpv3_regs
= count
;
4114 else if (start
+ count
> 16)
4115 num_vfpv3_regs
= start
+ count
- 16;
4117 if (num_vfpv3_regs
> 0)
4119 int start_offset
= start
> 16 ? start
- 16 : 0;
4120 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4121 add_unwind_opcode (op
, 2);
4124 /* Generate opcode for registers numbered in the range 0 .. 15. */
4125 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4126 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4127 if (num_regs_below_16
> 0)
4129 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4130 add_unwind_opcode (op
, 2);
4133 unwind
.frame_size
+= count
* 8;
4137 /* Parse a directive saving VFP registers for pre-ARMv6. */
4140 s_arm_unwind_save_vfp (void)
4146 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4149 as_bad (_("expected register list"));
4150 ignore_rest_of_line ();
4154 demand_empty_rest_of_line ();
4159 op
= 0xb8 | (count
- 1);
4160 add_unwind_opcode (op
, 1);
4165 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4166 add_unwind_opcode (op
, 2);
4168 unwind
.frame_size
+= count
* 8 + 4;
4172 /* Parse a directive saving iWMMXt data registers. */
4175 s_arm_unwind_save_mmxwr (void)
4183 if (*input_line_pointer
== '{')
4184 input_line_pointer
++;
4188 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4192 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4197 as_tsktsk (_("register list not in ascending order"));
4200 if (*input_line_pointer
== '-')
4202 input_line_pointer
++;
4203 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4206 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4209 else if (reg
>= hi_reg
)
4211 as_bad (_("bad register range"));
4214 for (; reg
< hi_reg
; reg
++)
4218 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4220 skip_past_char (&input_line_pointer
, '}');
4222 demand_empty_rest_of_line ();
4224 /* Generate any deferred opcodes because we're going to be looking at
4226 flush_pending_unwind ();
4228 for (i
= 0; i
< 16; i
++)
4230 if (mask
& (1 << i
))
4231 unwind
.frame_size
+= 8;
4234 /* Attempt to combine with a previous opcode. We do this because gcc
4235 likes to output separate unwind directives for a single block of
4237 if (unwind
.opcode_count
> 0)
4239 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4240 if ((i
& 0xf8) == 0xc0)
4243 /* Only merge if the blocks are contiguous. */
4246 if ((mask
& 0xfe00) == (1 << 9))
4248 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4249 unwind
.opcode_count
--;
4252 else if (i
== 6 && unwind
.opcode_count
>= 2)
4254 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4258 op
= 0xffff << (reg
- 1);
4260 && ((mask
& op
) == (1u << (reg
- 1))))
4262 op
= (1 << (reg
+ i
+ 1)) - 1;
4263 op
&= ~((1 << reg
) - 1);
4265 unwind
.opcode_count
-= 2;
4272 /* We want to generate opcodes in the order the registers have been
4273 saved, ie. descending order. */
4274 for (reg
= 15; reg
>= -1; reg
--)
4276 /* Save registers in blocks. */
4278 || !(mask
& (1 << reg
)))
4280 /* We found an unsaved reg. Generate opcodes to save the
4287 op
= 0xc0 | (hi_reg
- 10);
4288 add_unwind_opcode (op
, 1);
4293 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4294 add_unwind_opcode (op
, 2);
4303 ignore_rest_of_line ();
4307 s_arm_unwind_save_mmxwcg (void)
4314 if (*input_line_pointer
== '{')
4315 input_line_pointer
++;
4317 skip_whitespace (input_line_pointer
);
4321 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4325 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4331 as_tsktsk (_("register list not in ascending order"));
4334 if (*input_line_pointer
== '-')
4336 input_line_pointer
++;
4337 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4340 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4343 else if (reg
>= hi_reg
)
4345 as_bad (_("bad register range"));
4348 for (; reg
< hi_reg
; reg
++)
4352 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4354 skip_past_char (&input_line_pointer
, '}');
4356 demand_empty_rest_of_line ();
4358 /* Generate any deferred opcodes because we're going to be looking at
4360 flush_pending_unwind ();
4362 for (reg
= 0; reg
< 16; reg
++)
4364 if (mask
& (1 << reg
))
4365 unwind
.frame_size
+= 4;
4368 add_unwind_opcode (op
, 2);
4371 ignore_rest_of_line ();
4375 /* Parse an unwind_save directive.
4376 If the argument is non-zero, this is a .vsave directive. */
4379 s_arm_unwind_save (int arch_v6
)
4382 struct reg_entry
*reg
;
4383 bfd_boolean had_brace
= FALSE
;
4385 if (!unwind
.proc_start
)
4386 as_bad (MISSING_FNSTART
);
4388 /* Figure out what sort of save we have. */
4389 peek
= input_line_pointer
;
4397 reg
= arm_reg_parse_multi (&peek
);
4401 as_bad (_("register expected"));
4402 ignore_rest_of_line ();
4411 as_bad (_("FPA .unwind_save does not take a register list"));
4412 ignore_rest_of_line ();
4415 input_line_pointer
= peek
;
4416 s_arm_unwind_save_fpa (reg
->number
);
4420 s_arm_unwind_save_core ();
4425 s_arm_unwind_save_vfp_armv6 ();
4427 s_arm_unwind_save_vfp ();
4430 case REG_TYPE_MMXWR
:
4431 s_arm_unwind_save_mmxwr ();
4434 case REG_TYPE_MMXWCG
:
4435 s_arm_unwind_save_mmxwcg ();
4439 as_bad (_(".unwind_save does not support this kind of register"));
4440 ignore_rest_of_line ();
4445 /* Parse an unwind_movsp directive. */
4448 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4454 if (!unwind
.proc_start
)
4455 as_bad (MISSING_FNSTART
);
4457 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4460 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4461 ignore_rest_of_line ();
4465 /* Optional constant. */
4466 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4468 if (immediate_for_directive (&offset
) == FAIL
)
4474 demand_empty_rest_of_line ();
4476 if (reg
== REG_SP
|| reg
== REG_PC
)
4478 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4482 if (unwind
.fp_reg
!= REG_SP
)
4483 as_bad (_("unexpected .unwind_movsp directive"));
4485 /* Generate opcode to restore the value. */
4487 add_unwind_opcode (op
, 1);
4489 /* Record the information for later. */
4490 unwind
.fp_reg
= reg
;
4491 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4492 unwind
.sp_restored
= 1;
4495 /* Parse an unwind_pad directive. */
4498 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4502 if (!unwind
.proc_start
)
4503 as_bad (MISSING_FNSTART
);
4505 if (immediate_for_directive (&offset
) == FAIL
)
4510 as_bad (_("stack increment must be multiple of 4"));
4511 ignore_rest_of_line ();
4515 /* Don't generate any opcodes, just record the details for later. */
4516 unwind
.frame_size
+= offset
;
4517 unwind
.pending_offset
+= offset
;
4519 demand_empty_rest_of_line ();
4522 /* Parse an unwind_setfp directive. */
4525 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4531 if (!unwind
.proc_start
)
4532 as_bad (MISSING_FNSTART
);
4534 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4535 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4538 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4540 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4542 as_bad (_("expected <reg>, <reg>"));
4543 ignore_rest_of_line ();
4547 /* Optional constant. */
4548 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4550 if (immediate_for_directive (&offset
) == FAIL
)
4556 demand_empty_rest_of_line ();
4558 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4560 as_bad (_("register must be either sp or set by a previous"
4561 "unwind_movsp directive"));
4565 /* Don't generate any opcodes, just record the information for later. */
4566 unwind
.fp_reg
= fp_reg
;
4568 if (sp_reg
== REG_SP
)
4569 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4571 unwind
.fp_offset
-= offset
;
4574 /* Parse an unwind_raw directive. */
4577 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4580 /* This is an arbitrary limit. */
4581 unsigned char op
[16];
4584 if (!unwind
.proc_start
)
4585 as_bad (MISSING_FNSTART
);
4588 if (exp
.X_op
== O_constant
4589 && skip_past_comma (&input_line_pointer
) != FAIL
)
4591 unwind
.frame_size
+= exp
.X_add_number
;
4595 exp
.X_op
= O_illegal
;
4597 if (exp
.X_op
!= O_constant
)
4599 as_bad (_("expected <offset>, <opcode>"));
4600 ignore_rest_of_line ();
4606 /* Parse the opcode. */
4611 as_bad (_("unwind opcode too long"));
4612 ignore_rest_of_line ();
4614 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4616 as_bad (_("invalid unwind opcode"));
4617 ignore_rest_of_line ();
4620 op
[count
++] = exp
.X_add_number
;
4622 /* Parse the next byte. */
4623 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4629 /* Add the opcode bytes in reverse order. */
4631 add_unwind_opcode (op
[count
], 1);
4633 demand_empty_rest_of_line ();
4637 /* Parse a .eabi_attribute directive. */
4640 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4642 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4644 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4645 attributes_set_explicitly
[tag
] = 1;
4648 /* Emit a tls fix for the symbol. */
4651 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4655 #ifdef md_flush_pending_output
4656 md_flush_pending_output ();
4659 #ifdef md_cons_align
4663 /* Since we're just labelling the code, there's no need to define a
4666 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4667 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4668 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4669 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4671 #endif /* OBJ_ELF */
4673 static void s_arm_arch (int);
4674 static void s_arm_object_arch (int);
4675 static void s_arm_cpu (int);
4676 static void s_arm_fpu (int);
4677 static void s_arm_arch_extension (int);
4682 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4689 if (exp
.X_op
== O_symbol
)
4690 exp
.X_op
= O_secrel
;
4692 emit_expr (&exp
, 4);
4694 while (*input_line_pointer
++ == ',');
4696 input_line_pointer
--;
4697 demand_empty_rest_of_line ();
4701 /* This table describes all the machine specific pseudo-ops the assembler
4702 has to support. The fields are:
4703 pseudo-op name without dot
4704 function to call to execute this pseudo-op
4705 Integer arg to pass to the function. */
4707 const pseudo_typeS md_pseudo_table
[] =
4709 /* Never called because '.req' does not start a line. */
4710 { "req", s_req
, 0 },
4711 /* Following two are likewise never called. */
4714 { "unreq", s_unreq
, 0 },
4715 { "bss", s_bss
, 0 },
4716 { "align", s_align_ptwo
, 2 },
4717 { "arm", s_arm
, 0 },
4718 { "thumb", s_thumb
, 0 },
4719 { "code", s_code
, 0 },
4720 { "force_thumb", s_force_thumb
, 0 },
4721 { "thumb_func", s_thumb_func
, 0 },
4722 { "thumb_set", s_thumb_set
, 0 },
4723 { "even", s_even
, 0 },
4724 { "ltorg", s_ltorg
, 0 },
4725 { "pool", s_ltorg
, 0 },
4726 { "syntax", s_syntax
, 0 },
4727 { "cpu", s_arm_cpu
, 0 },
4728 { "arch", s_arm_arch
, 0 },
4729 { "object_arch", s_arm_object_arch
, 0 },
4730 { "fpu", s_arm_fpu
, 0 },
4731 { "arch_extension", s_arm_arch_extension
, 0 },
4733 { "word", s_arm_elf_cons
, 4 },
4734 { "long", s_arm_elf_cons
, 4 },
4735 { "inst.n", s_arm_elf_inst
, 2 },
4736 { "inst.w", s_arm_elf_inst
, 4 },
4737 { "inst", s_arm_elf_inst
, 0 },
4738 { "rel31", s_arm_rel31
, 0 },
4739 { "fnstart", s_arm_unwind_fnstart
, 0 },
4740 { "fnend", s_arm_unwind_fnend
, 0 },
4741 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4742 { "personality", s_arm_unwind_personality
, 0 },
4743 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4744 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4745 { "save", s_arm_unwind_save
, 0 },
4746 { "vsave", s_arm_unwind_save
, 1 },
4747 { "movsp", s_arm_unwind_movsp
, 0 },
4748 { "pad", s_arm_unwind_pad
, 0 },
4749 { "setfp", s_arm_unwind_setfp
, 0 },
4750 { "unwind_raw", s_arm_unwind_raw
, 0 },
4751 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4752 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4756 /* These are used for dwarf. */
4760 /* These are used for dwarf2. */
4761 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4762 { "loc", dwarf2_directive_loc
, 0 },
4763 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4765 { "extend", float_cons
, 'x' },
4766 { "ldouble", float_cons
, 'x' },
4767 { "packed", float_cons
, 'p' },
4769 {"secrel32", pe_directive_secrel
, 0},
4772 /* These are for compatibility with CodeComposer Studio. */
4773 {"ref", s_ccs_ref
, 0},
4774 {"def", s_ccs_def
, 0},
4775 {"asmfunc", s_ccs_asmfunc
, 0},
4776 {"endasmfunc", s_ccs_endasmfunc
, 0},
4781 /* Parser functions used exclusively in instruction operands. */
4783 /* Generic immediate-value read function for use in insn parsing.
4784 STR points to the beginning of the immediate (the leading #);
4785 VAL receives the value; if the value is outside [MIN, MAX]
4786 issue an error. PREFIX_OPT is true if the immediate prefix is
4790 parse_immediate (char **str
, int *val
, int min
, int max
,
4791 bfd_boolean prefix_opt
)
4795 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4796 if (exp
.X_op
!= O_constant
)
4798 inst
.error
= _("constant expression required");
4802 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4804 inst
.error
= _("immediate value out of range");
4808 *val
= exp
.X_add_number
;
4812 /* Less-generic immediate-value read function with the possibility of loading a
4813 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4814 instructions. Puts the result directly in inst.operands[i]. */
4817 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4818 bfd_boolean allow_symbol_p
)
4821 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4824 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4826 if (exp_p
->X_op
== O_constant
)
4828 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4829 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4830 O_constant. We have to be careful not to break compilation for
4831 32-bit X_add_number, though. */
4832 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4834 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4835 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4837 inst
.operands
[i
].regisimm
= 1;
4840 else if (exp_p
->X_op
== O_big
4841 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4843 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4845 /* Bignums have their least significant bits in
4846 generic_bignum[0]. Make sure we put 32 bits in imm and
4847 32 bits in reg, in a (hopefully) portable way. */
4848 gas_assert (parts
!= 0);
4850 /* Make sure that the number is not too big.
4851 PR 11972: Bignums can now be sign-extended to the
4852 size of a .octa so check that the out of range bits
4853 are all zero or all one. */
4854 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4856 LITTLENUM_TYPE m
= -1;
4858 if (generic_bignum
[parts
* 2] != 0
4859 && generic_bignum
[parts
* 2] != m
)
4862 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4863 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4867 inst
.operands
[i
].imm
= 0;
4868 for (j
= 0; j
< parts
; j
++, idx
++)
4869 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4870 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4871 inst
.operands
[i
].reg
= 0;
4872 for (j
= 0; j
< parts
; j
++, idx
++)
4873 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4874 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4875 inst
.operands
[i
].regisimm
= 1;
4877 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4885 /* Returns the pseudo-register number of an FPA immediate constant,
4886 or FAIL if there isn't a valid constant here. */
4889 parse_fpa_immediate (char ** str
)
4891 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4897 /* First try and match exact strings, this is to guarantee
4898 that some formats will work even for cross assembly. */
4900 for (i
= 0; fp_const
[i
]; i
++)
4902 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4906 *str
+= strlen (fp_const
[i
]);
4907 if (is_end_of_line
[(unsigned char) **str
])
4913 /* Just because we didn't get a match doesn't mean that the constant
4914 isn't valid, just that it is in a format that we don't
4915 automatically recognize. Try parsing it with the standard
4916 expression routines. */
4918 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4920 /* Look for a raw floating point number. */
4921 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4922 && is_end_of_line
[(unsigned char) *save_in
])
4924 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4926 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4928 if (words
[j
] != fp_values
[i
][j
])
4932 if (j
== MAX_LITTLENUMS
)
4940 /* Try and parse a more complex expression, this will probably fail
4941 unless the code uses a floating point prefix (eg "0f"). */
4942 save_in
= input_line_pointer
;
4943 input_line_pointer
= *str
;
4944 if (expression (&exp
) == absolute_section
4945 && exp
.X_op
== O_big
4946 && exp
.X_add_number
< 0)
4948 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4950 #define X_PRECISION 5
4951 #define E_PRECISION 15L
4952 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4954 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4956 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4958 if (words
[j
] != fp_values
[i
][j
])
4962 if (j
== MAX_LITTLENUMS
)
4964 *str
= input_line_pointer
;
4965 input_line_pointer
= save_in
;
4972 *str
= input_line_pointer
;
4973 input_line_pointer
= save_in
;
4974 inst
.error
= _("invalid FPA immediate expression");
4978 /* Returns 1 if a number has "quarter-precision" float format
4979 0baBbbbbbc defgh000 00000000 00000000. */
4982 is_quarter_float (unsigned imm
)
4984 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4985 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4989 /* Detect the presence of a floating point or integer zero constant,
4993 parse_ifimm_zero (char **in
)
4997 if (!is_immediate_prefix (**in
))
4999 /* In unified syntax, all prefixes are optional. */
5000 if (!unified_syntax
)
5006 /* Accept #0x0 as a synonym for #0. */
5007 if (strncmp (*in
, "0x", 2) == 0)
5010 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5015 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5016 &generic_floating_point_number
);
5019 && generic_floating_point_number
.sign
== '+'
5020 && (generic_floating_point_number
.low
5021 > generic_floating_point_number
.leader
))
5027 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5028 0baBbbbbbc defgh000 00000000 00000000.
5029 The zero and minus-zero cases need special handling, since they can't be
5030 encoded in the "quarter-precision" float format, but can nonetheless be
5031 loaded as integer constants. */
5034 parse_qfloat_immediate (char **ccp
, int *immed
)
5038 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5039 int found_fpchar
= 0;
5041 skip_past_char (&str
, '#');
5043 /* We must not accidentally parse an integer as a floating-point number. Make
5044 sure that the value we parse is not an integer by checking for special
5045 characters '.' or 'e'.
5046 FIXME: This is a horrible hack, but doing better is tricky because type
5047 information isn't in a very usable state at parse time. */
5049 skip_whitespace (fpnum
);
5051 if (strncmp (fpnum
, "0x", 2) == 0)
5055 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5056 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5066 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5068 unsigned fpword
= 0;
5071 /* Our FP word must be 32 bits (single-precision FP). */
5072 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5074 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5078 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5091 /* Shift operands. */
5094 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5097 struct asm_shift_name
5100 enum shift_kind kind
;
5103 /* Third argument to parse_shift. */
5104 enum parse_shift_mode
5106 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5107 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5108 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5109 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5110 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5113 /* Parse a <shift> specifier on an ARM data processing instruction.
5114 This has three forms:
5116 (LSL|LSR|ASL|ASR|ROR) Rs
5117 (LSL|LSR|ASL|ASR|ROR) #imm
5120 Note that ASL is assimilated to LSL in the instruction encoding, and
5121 RRX to ROR #0 (which cannot be written as such). */
5124 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5126 const struct asm_shift_name
*shift_name
;
5127 enum shift_kind shift
;
5132 for (p
= *str
; ISALPHA (*p
); p
++)
5137 inst
.error
= _("shift expression expected");
5141 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5144 if (shift_name
== NULL
)
5146 inst
.error
= _("shift expression expected");
5150 shift
= shift_name
->kind
;
5154 case NO_SHIFT_RESTRICT
:
5155 case SHIFT_IMMEDIATE
: break;
5157 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5158 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5160 inst
.error
= _("'LSL' or 'ASR' required");
5165 case SHIFT_LSL_IMMEDIATE
:
5166 if (shift
!= SHIFT_LSL
)
5168 inst
.error
= _("'LSL' required");
5173 case SHIFT_ASR_IMMEDIATE
:
5174 if (shift
!= SHIFT_ASR
)
5176 inst
.error
= _("'ASR' required");
5184 if (shift
!= SHIFT_RRX
)
5186 /* Whitespace can appear here if the next thing is a bare digit. */
5187 skip_whitespace (p
);
5189 if (mode
== NO_SHIFT_RESTRICT
5190 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5192 inst
.operands
[i
].imm
= reg
;
5193 inst
.operands
[i
].immisreg
= 1;
5195 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5198 inst
.operands
[i
].shift_kind
= shift
;
5199 inst
.operands
[i
].shifted
= 1;
5204 /* Parse a <shifter_operand> for an ARM data processing instruction:
5207 #<immediate>, <rotate>
5211 where <shift> is defined by parse_shift above, and <rotate> is a
5212 multiple of 2 between 0 and 30. Validation of immediate operands
5213 is deferred to md_apply_fix. */
5216 parse_shifter_operand (char **str
, int i
)
5221 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5223 inst
.operands
[i
].reg
= value
;
5224 inst
.operands
[i
].isreg
= 1;
5226 /* parse_shift will override this if appropriate */
5227 inst
.reloc
.exp
.X_op
= O_constant
;
5228 inst
.reloc
.exp
.X_add_number
= 0;
5230 if (skip_past_comma (str
) == FAIL
)
5233 /* Shift operation on register. */
5234 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5237 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5240 if (skip_past_comma (str
) == SUCCESS
)
5242 /* #x, y -- ie explicit rotation by Y. */
5243 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5246 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5248 inst
.error
= _("constant expression expected");
5252 value
= exp
.X_add_number
;
5253 if (value
< 0 || value
> 30 || value
% 2 != 0)
5255 inst
.error
= _("invalid rotation");
5258 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5260 inst
.error
= _("invalid constant");
5264 /* Encode as specified. */
5265 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5269 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5270 inst
.reloc
.pc_rel
= 0;
5274 /* Group relocation information. Each entry in the table contains the
5275 textual name of the relocation as may appear in assembler source
5276 and must end with a colon.
5277 Along with this textual name are the relocation codes to be used if
5278 the corresponding instruction is an ALU instruction (ADD or SUB only),
5279 an LDR, an LDRS, or an LDC. */
5281 struct group_reloc_table_entry
5292 /* Varieties of non-ALU group relocation. */
5299 static struct group_reloc_table_entry group_reloc_table
[] =
5300 { /* Program counter relative: */
5302 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5307 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5308 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5309 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5310 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5312 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5318 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5323 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5324 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5325 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5326 /* Section base relative */
5328 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5333 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5334 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5335 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5336 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5338 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5343 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5344 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5345 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5346 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5348 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5349 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5350 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5351 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5352 /* Absolute thumb alu relocations. */
5354 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5359 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5364 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5369 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5374 /* Given the address of a pointer pointing to the textual name of a group
5375 relocation as may appear in assembler source, attempt to find its details
5376 in group_reloc_table. The pointer will be updated to the character after
5377 the trailing colon. On failure, FAIL will be returned; SUCCESS
5378 otherwise. On success, *entry will be updated to point at the relevant
5379 group_reloc_table entry. */
5382 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5385 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5387 int length
= strlen (group_reloc_table
[i
].name
);
5389 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5390 && (*str
)[length
] == ':')
5392 *out
= &group_reloc_table
[i
];
5393 *str
+= (length
+ 1);
5401 /* Parse a <shifter_operand> for an ARM data processing instruction
5402 (as for parse_shifter_operand) where group relocations are allowed:
5405 #<immediate>, <rotate>
5406 #:<group_reloc>:<expression>
5410 where <group_reloc> is one of the strings defined in group_reloc_table.
5411 The hashes are optional.
5413 Everything else is as for parse_shifter_operand. */
5415 static parse_operand_result
5416 parse_shifter_operand_group_reloc (char **str
, int i
)
5418 /* Determine if we have the sequence of characters #: or just :
5419 coming next. If we do, then we check for a group relocation.
5420 If we don't, punt the whole lot to parse_shifter_operand. */
5422 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5423 || (*str
)[0] == ':')
5425 struct group_reloc_table_entry
*entry
;
5427 if ((*str
)[0] == '#')
5432 /* Try to parse a group relocation. Anything else is an error. */
5433 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5435 inst
.error
= _("unknown group relocation");
5436 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5439 /* We now have the group relocation table entry corresponding to
5440 the name in the assembler source. Next, we parse the expression. */
5441 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5442 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5444 /* Record the relocation type (always the ALU variant here). */
5445 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5446 gas_assert (inst
.reloc
.type
!= 0);
5448 return PARSE_OPERAND_SUCCESS
;
5451 return parse_shifter_operand (str
, i
) == SUCCESS
5452 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5454 /* Never reached. */
5457 /* Parse a Neon alignment expression. Information is written to
5458 inst.operands[i]. We assume the initial ':' has been skipped.
5460 align .imm = align << 8, .immisalign=1, .preind=0 */
5461 static parse_operand_result
5462 parse_neon_alignment (char **str
, int i
)
5467 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5469 if (exp
.X_op
!= O_constant
)
5471 inst
.error
= _("alignment must be constant");
5472 return PARSE_OPERAND_FAIL
;
5475 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5476 inst
.operands
[i
].immisalign
= 1;
5477 /* Alignments are not pre-indexes. */
5478 inst
.operands
[i
].preind
= 0;
5481 return PARSE_OPERAND_SUCCESS
;
5484 /* Parse all forms of an ARM address expression. Information is written
5485 to inst.operands[i] and/or inst.reloc.
5487 Preindexed addressing (.preind=1):
5489 [Rn, #offset] .reg=Rn .reloc.exp=offset
5490 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5491 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5492 .shift_kind=shift .reloc.exp=shift_imm
5494 These three may have a trailing ! which causes .writeback to be set also.
5496 Postindexed addressing (.postind=1, .writeback=1):
5498 [Rn], #offset .reg=Rn .reloc.exp=offset
5499 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5500 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5501 .shift_kind=shift .reloc.exp=shift_imm
5503 Unindexed addressing (.preind=0, .postind=0):
5505 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5509 [Rn]{!} shorthand for [Rn,#0]{!}
5510 =immediate .isreg=0 .reloc.exp=immediate
5511 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5513 It is the caller's responsibility to check for addressing modes not
5514 supported by the instruction, and to set inst.reloc.type. */
5516 static parse_operand_result
5517 parse_address_main (char **str
, int i
, int group_relocations
,
5518 group_reloc_type group_type
)
5523 if (skip_past_char (&p
, '[') == FAIL
)
5525 if (skip_past_char (&p
, '=') == FAIL
)
5527 /* Bare address - translate to PC-relative offset. */
5528 inst
.reloc
.pc_rel
= 1;
5529 inst
.operands
[i
].reg
= REG_PC
;
5530 inst
.operands
[i
].isreg
= 1;
5531 inst
.operands
[i
].preind
= 1;
5533 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5534 return PARSE_OPERAND_FAIL
;
5536 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5537 /*allow_symbol_p=*/TRUE
))
5538 return PARSE_OPERAND_FAIL
;
5541 return PARSE_OPERAND_SUCCESS
;
5544 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5545 skip_whitespace (p
);
5547 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5549 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5550 return PARSE_OPERAND_FAIL
;
5552 inst
.operands
[i
].reg
= reg
;
5553 inst
.operands
[i
].isreg
= 1;
5555 if (skip_past_comma (&p
) == SUCCESS
)
5557 inst
.operands
[i
].preind
= 1;
5560 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5562 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5564 inst
.operands
[i
].imm
= reg
;
5565 inst
.operands
[i
].immisreg
= 1;
5567 if (skip_past_comma (&p
) == SUCCESS
)
5568 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5569 return PARSE_OPERAND_FAIL
;
5571 else if (skip_past_char (&p
, ':') == SUCCESS
)
5573 /* FIXME: '@' should be used here, but it's filtered out by generic
5574 code before we get to see it here. This may be subject to
5576 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5578 if (result
!= PARSE_OPERAND_SUCCESS
)
5583 if (inst
.operands
[i
].negative
)
5585 inst
.operands
[i
].negative
= 0;
5589 if (group_relocations
5590 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5592 struct group_reloc_table_entry
*entry
;
5594 /* Skip over the #: or : sequence. */
5600 /* Try to parse a group relocation. Anything else is an
5602 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5604 inst
.error
= _("unknown group relocation");
5605 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5608 /* We now have the group relocation table entry corresponding to
5609 the name in the assembler source. Next, we parse the
5611 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5612 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5614 /* Record the relocation type. */
5618 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5622 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5626 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5633 if (inst
.reloc
.type
== 0)
5635 inst
.error
= _("this group relocation is not allowed on this instruction");
5636 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5643 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5644 return PARSE_OPERAND_FAIL
;
5645 /* If the offset is 0, find out if it's a +0 or -0. */
5646 if (inst
.reloc
.exp
.X_op
== O_constant
5647 && inst
.reloc
.exp
.X_add_number
== 0)
5649 skip_whitespace (q
);
5653 skip_whitespace (q
);
5656 inst
.operands
[i
].negative
= 1;
5661 else if (skip_past_char (&p
, ':') == SUCCESS
)
5663 /* FIXME: '@' should be used here, but it's filtered out by generic code
5664 before we get to see it here. This may be subject to change. */
5665 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5667 if (result
!= PARSE_OPERAND_SUCCESS
)
5671 if (skip_past_char (&p
, ']') == FAIL
)
5673 inst
.error
= _("']' expected");
5674 return PARSE_OPERAND_FAIL
;
5677 if (skip_past_char (&p
, '!') == SUCCESS
)
5678 inst
.operands
[i
].writeback
= 1;
5680 else if (skip_past_comma (&p
) == SUCCESS
)
5682 if (skip_past_char (&p
, '{') == SUCCESS
)
5684 /* [Rn], {expr} - unindexed, with option */
5685 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5686 0, 255, TRUE
) == FAIL
)
5687 return PARSE_OPERAND_FAIL
;
5689 if (skip_past_char (&p
, '}') == FAIL
)
5691 inst
.error
= _("'}' expected at end of 'option' field");
5692 return PARSE_OPERAND_FAIL
;
5694 if (inst
.operands
[i
].preind
)
5696 inst
.error
= _("cannot combine index with option");
5697 return PARSE_OPERAND_FAIL
;
5700 return PARSE_OPERAND_SUCCESS
;
5704 inst
.operands
[i
].postind
= 1;
5705 inst
.operands
[i
].writeback
= 1;
5707 if (inst
.operands
[i
].preind
)
5709 inst
.error
= _("cannot combine pre- and post-indexing");
5710 return PARSE_OPERAND_FAIL
;
5714 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5716 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5718 /* We might be using the immediate for alignment already. If we
5719 are, OR the register number into the low-order bits. */
5720 if (inst
.operands
[i
].immisalign
)
5721 inst
.operands
[i
].imm
|= reg
;
5723 inst
.operands
[i
].imm
= reg
;
5724 inst
.operands
[i
].immisreg
= 1;
5726 if (skip_past_comma (&p
) == SUCCESS
)
5727 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5728 return PARSE_OPERAND_FAIL
;
5734 if (inst
.operands
[i
].negative
)
5736 inst
.operands
[i
].negative
= 0;
5739 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5740 return PARSE_OPERAND_FAIL
;
5741 /* If the offset is 0, find out if it's a +0 or -0. */
5742 if (inst
.reloc
.exp
.X_op
== O_constant
5743 && inst
.reloc
.exp
.X_add_number
== 0)
5745 skip_whitespace (q
);
5749 skip_whitespace (q
);
5752 inst
.operands
[i
].negative
= 1;
5758 /* If at this point neither .preind nor .postind is set, we have a
5759 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5760 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5762 inst
.operands
[i
].preind
= 1;
5763 inst
.reloc
.exp
.X_op
= O_constant
;
5764 inst
.reloc
.exp
.X_add_number
= 0;
5767 return PARSE_OPERAND_SUCCESS
;
5771 parse_address (char **str
, int i
)
5773 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5777 static parse_operand_result
5778 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5780 return parse_address_main (str
, i
, 1, type
);
5783 /* Parse an operand for a MOVW or MOVT instruction. */
5785 parse_half (char **str
)
5790 skip_past_char (&p
, '#');
5791 if (strncasecmp (p
, ":lower16:", 9) == 0)
5792 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5793 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5794 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5796 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5799 skip_whitespace (p
);
5802 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5805 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5807 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5809 inst
.error
= _("constant expression expected");
5812 if (inst
.reloc
.exp
.X_add_number
< 0
5813 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5815 inst
.error
= _("immediate value out of range");
5823 /* Miscellaneous. */
5825 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5826 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5828 parse_psr (char **str
, bfd_boolean lhs
)
5831 unsigned long psr_field
;
5832 const struct asm_psr
*psr
;
5834 bfd_boolean is_apsr
= FALSE
;
5835 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5837 /* PR gas/12698: If the user has specified -march=all then m_profile will
5838 be TRUE, but we want to ignore it in this case as we are building for any
5839 CPU type, including non-m variants. */
5840 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5843 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5844 feature for ease of use and backwards compatibility. */
5846 if (strncasecmp (p
, "SPSR", 4) == 0)
5849 goto unsupported_psr
;
5851 psr_field
= SPSR_BIT
;
5853 else if (strncasecmp (p
, "CPSR", 4) == 0)
5856 goto unsupported_psr
;
5860 else if (strncasecmp (p
, "APSR", 4) == 0)
5862 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5863 and ARMv7-R architecture CPUs. */
5872 while (ISALNUM (*p
) || *p
== '_');
5874 if (strncasecmp (start
, "iapsr", 5) == 0
5875 || strncasecmp (start
, "eapsr", 5) == 0
5876 || strncasecmp (start
, "xpsr", 4) == 0
5877 || strncasecmp (start
, "psr", 3) == 0)
5878 p
= start
+ strcspn (start
, "rR") + 1;
5880 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5886 /* If APSR is being written, a bitfield may be specified. Note that
5887 APSR itself is handled above. */
5888 if (psr
->field
<= 3)
5890 psr_field
= psr
->field
;
5896 /* M-profile MSR instructions have the mask field set to "10", except
5897 *PSR variants which modify APSR, which may use a different mask (and
5898 have been handled already). Do that by setting the PSR_f field
5900 return psr
->field
| (lhs
? PSR_f
: 0);
5903 goto unsupported_psr
;
5909 /* A suffix follows. */
5915 while (ISALNUM (*p
) || *p
== '_');
5919 /* APSR uses a notation for bits, rather than fields. */
5920 unsigned int nzcvq_bits
= 0;
5921 unsigned int g_bit
= 0;
5924 for (bit
= start
; bit
!= p
; bit
++)
5926 switch (TOLOWER (*bit
))
5929 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5933 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5937 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5941 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5945 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5949 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5953 inst
.error
= _("unexpected bit specified after APSR");
5958 if (nzcvq_bits
== 0x1f)
5963 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5965 inst
.error
= _("selected processor does not "
5966 "support DSP extension");
5973 if ((nzcvq_bits
& 0x20) != 0
5974 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5975 || (g_bit
& 0x2) != 0)
5977 inst
.error
= _("bad bitmask specified after APSR");
5983 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5988 psr_field
|= psr
->field
;
5994 goto error
; /* Garbage after "[CS]PSR". */
5996 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5997 is deprecated, but allow it anyway. */
6001 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6004 else if (!m_profile
)
6005 /* These bits are never right for M-profile devices: don't set them
6006 (only code paths which read/write APSR reach here). */
6007 psr_field
|= (PSR_c
| PSR_f
);
6013 inst
.error
= _("selected processor does not support requested special "
6014 "purpose register");
6018 inst
.error
= _("flag for {c}psr instruction expected");
6022 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6023 value suitable for splatting into the AIF field of the instruction. */
6026 parse_cps_flags (char **str
)
6035 case '\0': case ',':
6038 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6039 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6040 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6043 inst
.error
= _("unrecognized CPS flag");
6048 if (saw_a_flag
== 0)
6050 inst
.error
= _("missing CPS flags");
6058 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6059 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6062 parse_endian_specifier (char **str
)
6067 if (strncasecmp (s
, "BE", 2))
6069 else if (strncasecmp (s
, "LE", 2))
6073 inst
.error
= _("valid endian specifiers are be or le");
6077 if (ISALNUM (s
[2]) || s
[2] == '_')
6079 inst
.error
= _("valid endian specifiers are be or le");
6084 return little_endian
;
6087 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6088 value suitable for poking into the rotate field of an sxt or sxta
6089 instruction, or FAIL on error. */
6092 parse_ror (char **str
)
6097 if (strncasecmp (s
, "ROR", 3) == 0)
6101 inst
.error
= _("missing rotation field after comma");
6105 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6110 case 0: *str
= s
; return 0x0;
6111 case 8: *str
= s
; return 0x1;
6112 case 16: *str
= s
; return 0x2;
6113 case 24: *str
= s
; return 0x3;
6116 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6121 /* Parse a conditional code (from conds[] below). The value returned is in the
6122 range 0 .. 14, or FAIL. */
6124 parse_cond (char **str
)
6127 const struct asm_cond
*c
;
6129 /* Condition codes are always 2 characters, so matching up to
6130 3 characters is sufficient. */
6135 while (ISALPHA (*q
) && n
< 3)
6137 cond
[n
] = TOLOWER (*q
);
6142 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6145 inst
.error
= _("condition required");
6153 /* Record a use of the given feature. */
6155 record_feature_use (const arm_feature_set
*feature
)
6158 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6160 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6163 /* If the given feature available in the selected CPU, mark it as used.
6164 Returns TRUE iff feature is available. */
6166 mark_feature_used (const arm_feature_set
*feature
)
6168 /* Ensure the option is valid on the current architecture. */
6169 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6172 /* Add the appropriate architecture feature for the barrier option used.
6174 record_feature_use (feature
);
6179 /* Parse an option for a barrier instruction. Returns the encoding for the
6182 parse_barrier (char **str
)
6185 const struct asm_barrier_opt
*o
;
6188 while (ISALPHA (*q
))
6191 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6196 if (!mark_feature_used (&o
->arch
))
6203 /* Parse the operands of a table branch instruction. Similar to a memory
6206 parse_tb (char **str
)
6211 if (skip_past_char (&p
, '[') == FAIL
)
6213 inst
.error
= _("'[' expected");
6217 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6219 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6222 inst
.operands
[0].reg
= reg
;
6224 if (skip_past_comma (&p
) == FAIL
)
6226 inst
.error
= _("',' expected");
6230 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6232 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6235 inst
.operands
[0].imm
= reg
;
6237 if (skip_past_comma (&p
) == SUCCESS
)
6239 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6241 if (inst
.reloc
.exp
.X_add_number
!= 1)
6243 inst
.error
= _("invalid shift");
6246 inst
.operands
[0].shifted
= 1;
6249 if (skip_past_char (&p
, ']') == FAIL
)
6251 inst
.error
= _("']' expected");
6258 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6259 information on the types the operands can take and how they are encoded.
6260 Up to four operands may be read; this function handles setting the
6261 ".present" field for each read operand itself.
6262 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6263 else returns FAIL. */
6266 parse_neon_mov (char **str
, int *which_operand
)
6268 int i
= *which_operand
, val
;
6269 enum arm_reg_type rtype
;
6271 struct neon_type_el optype
;
6273 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6275 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6276 inst
.operands
[i
].reg
= val
;
6277 inst
.operands
[i
].isscalar
= 1;
6278 inst
.operands
[i
].vectype
= optype
;
6279 inst
.operands
[i
++].present
= 1;
6281 if (skip_past_comma (&ptr
) == FAIL
)
6284 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6287 inst
.operands
[i
].reg
= val
;
6288 inst
.operands
[i
].isreg
= 1;
6289 inst
.operands
[i
].present
= 1;
6291 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6294 /* Cases 0, 1, 2, 3, 5 (D only). */
6295 if (skip_past_comma (&ptr
) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6301 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6302 inst
.operands
[i
].isvec
= 1;
6303 inst
.operands
[i
].vectype
= optype
;
6304 inst
.operands
[i
++].present
= 1;
6306 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6308 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6309 Case 13: VMOV <Sd>, <Rm> */
6310 inst
.operands
[i
].reg
= val
;
6311 inst
.operands
[i
].isreg
= 1;
6312 inst
.operands
[i
].present
= 1;
6314 if (rtype
== REG_TYPE_NQ
)
6316 first_error (_("can't use Neon quad register here"));
6319 else if (rtype
!= REG_TYPE_VFS
)
6322 if (skip_past_comma (&ptr
) == FAIL
)
6324 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6328 inst
.operands
[i
].present
= 1;
6331 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6334 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6335 Case 1: VMOV<c><q> <Dd>, <Dm>
6336 Case 8: VMOV.F32 <Sd>, <Sm>
6337 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6339 inst
.operands
[i
].reg
= val
;
6340 inst
.operands
[i
].isreg
= 1;
6341 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6342 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6343 inst
.operands
[i
].isvec
= 1;
6344 inst
.operands
[i
].vectype
= optype
;
6345 inst
.operands
[i
].present
= 1;
6347 if (skip_past_comma (&ptr
) == SUCCESS
)
6352 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6355 inst
.operands
[i
].reg
= val
;
6356 inst
.operands
[i
].isreg
= 1;
6357 inst
.operands
[i
++].present
= 1;
6359 if (skip_past_comma (&ptr
) == FAIL
)
6362 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
].present
= 1;
6370 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6371 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6372 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6373 Case 10: VMOV.F32 <Sd>, #<imm>
6374 Case 11: VMOV.F64 <Dd>, #<imm> */
6375 inst
.operands
[i
].immisfloat
= 1;
6376 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6378 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6379 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6383 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6387 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6390 inst
.operands
[i
].reg
= val
;
6391 inst
.operands
[i
].isreg
= 1;
6392 inst
.operands
[i
++].present
= 1;
6394 if (skip_past_comma (&ptr
) == FAIL
)
6397 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6399 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6400 inst
.operands
[i
].reg
= val
;
6401 inst
.operands
[i
].isscalar
= 1;
6402 inst
.operands
[i
].present
= 1;
6403 inst
.operands
[i
].vectype
= optype
;
6405 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6407 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6408 inst
.operands
[i
].reg
= val
;
6409 inst
.operands
[i
].isreg
= 1;
6410 inst
.operands
[i
++].present
= 1;
6412 if (skip_past_comma (&ptr
) == FAIL
)
6415 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6418 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6422 inst
.operands
[i
].reg
= val
;
6423 inst
.operands
[i
].isreg
= 1;
6424 inst
.operands
[i
].isvec
= 1;
6425 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6426 inst
.operands
[i
].vectype
= optype
;
6427 inst
.operands
[i
].present
= 1;
6429 if (rtype
== REG_TYPE_VFS
)
6433 if (skip_past_comma (&ptr
) == FAIL
)
6435 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6438 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6441 inst
.operands
[i
].reg
= val
;
6442 inst
.operands
[i
].isreg
= 1;
6443 inst
.operands
[i
].isvec
= 1;
6444 inst
.operands
[i
].issingle
= 1;
6445 inst
.operands
[i
].vectype
= optype
;
6446 inst
.operands
[i
].present
= 1;
6449 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6453 inst
.operands
[i
].reg
= val
;
6454 inst
.operands
[i
].isreg
= 1;
6455 inst
.operands
[i
].isvec
= 1;
6456 inst
.operands
[i
].issingle
= 1;
6457 inst
.operands
[i
].vectype
= optype
;
6458 inst
.operands
[i
].present
= 1;
6463 first_error (_("parse error"));
6467 /* Successfully parsed the operands. Update args. */
6473 first_error (_("expected comma"));
6477 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6481 /* Use this macro when the operand constraints are different
6482 for ARM and THUMB (e.g. ldrd). */
6483 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6484 ((arm_operand) | ((thumb_operand) << 16))
6486 /* Matcher codes for parse_operands. */
6487 enum operand_parse_code
6489 OP_stop
, /* end of line */
6491 OP_RR
, /* ARM register */
6492 OP_RRnpc
, /* ARM register, not r15 */
6493 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6494 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6495 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6496 optional trailing ! */
6497 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6498 OP_RCP
, /* Coprocessor number */
6499 OP_RCN
, /* Coprocessor register */
6500 OP_RF
, /* FPA register */
6501 OP_RVS
, /* VFP single precision register */
6502 OP_RVD
, /* VFP double precision register (0..15) */
6503 OP_RND
, /* Neon double precision register (0..31) */
6504 OP_RNQ
, /* Neon quad precision register */
6505 OP_RVSD
, /* VFP single or double precision register */
6506 OP_RNSD
, /* Neon single or double precision register */
6507 OP_RNDQ
, /* Neon double or quad precision register */
6508 OP_RNSDQ
, /* Neon single, double or quad precision register */
6509 OP_RNSC
, /* Neon scalar D[X] */
6510 OP_RVC
, /* VFP control register */
6511 OP_RMF
, /* Maverick F register */
6512 OP_RMD
, /* Maverick D register */
6513 OP_RMFX
, /* Maverick FX register */
6514 OP_RMDX
, /* Maverick DX register */
6515 OP_RMAX
, /* Maverick AX register */
6516 OP_RMDS
, /* Maverick DSPSC register */
6517 OP_RIWR
, /* iWMMXt wR register */
6518 OP_RIWC
, /* iWMMXt wC register */
6519 OP_RIWG
, /* iWMMXt wCG register */
6520 OP_RXA
, /* XScale accumulator register */
6522 OP_REGLST
, /* ARM register list */
6523 OP_VRSLST
, /* VFP single-precision register list */
6524 OP_VRDLST
, /* VFP double-precision register list */
6525 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6526 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6527 OP_NSTRLST
, /* Neon element/structure list */
6529 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6530 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6531 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6532 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6533 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6534 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6535 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6536 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6537 OP_VMOV
, /* Neon VMOV operands. */
6538 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6539 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6540 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6542 OP_I0
, /* immediate zero */
6543 OP_I7
, /* immediate value 0 .. 7 */
6544 OP_I15
, /* 0 .. 15 */
6545 OP_I16
, /* 1 .. 16 */
6546 OP_I16z
, /* 0 .. 16 */
6547 OP_I31
, /* 0 .. 31 */
6548 OP_I31w
, /* 0 .. 31, optional trailing ! */
6549 OP_I32
, /* 1 .. 32 */
6550 OP_I32z
, /* 0 .. 32 */
6551 OP_I63
, /* 0 .. 63 */
6552 OP_I63s
, /* -64 .. 63 */
6553 OP_I64
, /* 1 .. 64 */
6554 OP_I64z
, /* 0 .. 64 */
6555 OP_I255
, /* 0 .. 255 */
6557 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6558 OP_I7b
, /* 0 .. 7 */
6559 OP_I15b
, /* 0 .. 15 */
6560 OP_I31b
, /* 0 .. 31 */
6562 OP_SH
, /* shifter operand */
6563 OP_SHG
, /* shifter operand with possible group relocation */
6564 OP_ADDR
, /* Memory address expression (any mode) */
6565 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6566 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6567 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6568 OP_EXP
, /* arbitrary expression */
6569 OP_EXPi
, /* same, with optional immediate prefix */
6570 OP_EXPr
, /* same, with optional relocation suffix */
6571 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6572 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6573 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6575 OP_CPSF
, /* CPS flags */
6576 OP_ENDI
, /* Endianness specifier */
6577 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6578 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6579 OP_COND
, /* conditional code */
6580 OP_TB
, /* Table branch. */
6582 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6584 OP_RRnpc_I0
, /* ARM register or literal 0 */
6585 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6586 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6587 OP_RF_IF
, /* FPA register or immediate */
6588 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6589 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6591 /* Optional operands. */
6592 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6593 OP_oI31b
, /* 0 .. 31 */
6594 OP_oI32b
, /* 1 .. 32 */
6595 OP_oI32z
, /* 0 .. 32 */
6596 OP_oIffffb
, /* 0 .. 65535 */
6597 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6599 OP_oRR
, /* ARM register */
6600 OP_oRRnpc
, /* ARM register, not the PC */
6601 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6602 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6603 OP_oRND
, /* Optional Neon double precision register */
6604 OP_oRNQ
, /* Optional Neon quad precision register */
6605 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6606 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6607 OP_oSHll
, /* LSL immediate */
6608 OP_oSHar
, /* ASR immediate */
6609 OP_oSHllar
, /* LSL or ASR immediate */
6610 OP_oROR
, /* ROR 0/8/16/24 */
6611 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6613 /* Some pre-defined mixed (ARM/THUMB) operands. */
6614 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6615 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6616 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6618 OP_FIRST_OPTIONAL
= OP_oI7b
6621 /* Generic instruction operand parser. This does no encoding and no
6622 semantic validation; it merely squirrels values away in the inst
6623 structure. Returns SUCCESS or FAIL depending on whether the
6624 specified grammar matched. */
6626 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6628 unsigned const int *upat
= pattern
;
6629 char *backtrack_pos
= 0;
6630 const char *backtrack_error
= 0;
6631 int i
, val
= 0, backtrack_index
= 0;
6632 enum arm_reg_type rtype
;
6633 parse_operand_result result
;
6634 unsigned int op_parse_code
;
6636 #define po_char_or_fail(chr) \
6639 if (skip_past_char (&str, chr) == FAIL) \
6644 #define po_reg_or_fail(regtype) \
6647 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6648 & inst.operands[i].vectype); \
6651 first_error (_(reg_expected_msgs[regtype])); \
6654 inst.operands[i].reg = val; \
6655 inst.operands[i].isreg = 1; \
6656 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6657 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6658 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6659 || rtype == REG_TYPE_VFD \
6660 || rtype == REG_TYPE_NQ); \
6664 #define po_reg_or_goto(regtype, label) \
6667 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6668 & inst.operands[i].vectype); \
6672 inst.operands[i].reg = val; \
6673 inst.operands[i].isreg = 1; \
6674 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6675 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6676 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6677 || rtype == REG_TYPE_VFD \
6678 || rtype == REG_TYPE_NQ); \
6682 #define po_imm_or_fail(min, max, popt) \
6685 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6687 inst.operands[i].imm = val; \
6691 #define po_scalar_or_goto(elsz, label) \
6694 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6697 inst.operands[i].reg = val; \
6698 inst.operands[i].isscalar = 1; \
6702 #define po_misc_or_fail(expr) \
6710 #define po_misc_or_fail_no_backtrack(expr) \
6714 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6715 backtrack_pos = 0; \
6716 if (result != PARSE_OPERAND_SUCCESS) \
6721 #define po_barrier_or_imm(str) \
6724 val = parse_barrier (&str); \
6725 if (val == FAIL && ! ISALPHA (*str)) \
6728 /* ISB can only take SY as an option. */ \
6729 || ((inst.instruction & 0xf0) == 0x60 \
6732 inst.error = _("invalid barrier type"); \
6733 backtrack_pos = 0; \
6739 skip_whitespace (str
);
6741 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6743 op_parse_code
= upat
[i
];
6744 if (op_parse_code
>= 1<<16)
6745 op_parse_code
= thumb
? (op_parse_code
>> 16)
6746 : (op_parse_code
& ((1<<16)-1));
6748 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6750 /* Remember where we are in case we need to backtrack. */
6751 gas_assert (!backtrack_pos
);
6752 backtrack_pos
= str
;
6753 backtrack_error
= inst
.error
;
6754 backtrack_index
= i
;
6757 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6758 po_char_or_fail (',');
6760 switch (op_parse_code
)
6768 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6769 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6770 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6771 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6772 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6773 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6775 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6777 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6779 /* Also accept generic coprocessor regs for unknown registers. */
6781 po_reg_or_fail (REG_TYPE_CN
);
6783 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6784 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6785 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6786 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6787 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6788 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6789 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6790 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6791 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6792 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6794 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6795 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6797 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6798 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6800 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6802 /* Neon scalar. Using an element size of 8 means that some invalid
6803 scalars are accepted here, so deal with those in later code. */
6804 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6808 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6811 po_imm_or_fail (0, 0, TRUE
);
6816 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6821 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6824 if (parse_ifimm_zero (&str
))
6825 inst
.operands
[i
].imm
= 0;
6829 = _("only floating point zero is allowed as immediate value");
6837 po_scalar_or_goto (8, try_rr
);
6840 po_reg_or_fail (REG_TYPE_RN
);
6846 po_scalar_or_goto (8, try_nsdq
);
6849 po_reg_or_fail (REG_TYPE_NSDQ
);
6855 po_scalar_or_goto (8, try_s_scalar
);
6858 po_scalar_or_goto (4, try_nsd
);
6861 po_reg_or_fail (REG_TYPE_NSD
);
6867 po_scalar_or_goto (8, try_ndq
);
6870 po_reg_or_fail (REG_TYPE_NDQ
);
6876 po_scalar_or_goto (8, try_vfd
);
6879 po_reg_or_fail (REG_TYPE_VFD
);
6884 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6885 not careful then bad things might happen. */
6886 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6891 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6894 /* There's a possibility of getting a 64-bit immediate here, so
6895 we need special handling. */
6896 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6899 inst
.error
= _("immediate value is out of range");
6907 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6910 po_imm_or_fail (0, 63, TRUE
);
6915 po_char_or_fail ('[');
6916 po_reg_or_fail (REG_TYPE_RN
);
6917 po_char_or_fail (']');
6923 po_reg_or_fail (REG_TYPE_RN
);
6924 if (skip_past_char (&str
, '!') == SUCCESS
)
6925 inst
.operands
[i
].writeback
= 1;
6929 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6930 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6931 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6932 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6933 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6934 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6935 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6936 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6937 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6938 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6939 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6940 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6942 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6944 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6945 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6947 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6948 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6949 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6950 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6952 /* Immediate variants */
6954 po_char_or_fail ('{');
6955 po_imm_or_fail (0, 255, TRUE
);
6956 po_char_or_fail ('}');
6960 /* The expression parser chokes on a trailing !, so we have
6961 to find it first and zap it. */
6964 while (*s
&& *s
!= ',')
6969 inst
.operands
[i
].writeback
= 1;
6971 po_imm_or_fail (0, 31, TRUE
);
6979 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6984 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6989 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6991 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6993 val
= parse_reloc (&str
);
6996 inst
.error
= _("unrecognized relocation suffix");
6999 else if (val
!= BFD_RELOC_UNUSED
)
7001 inst
.operands
[i
].imm
= val
;
7002 inst
.operands
[i
].hasreloc
= 1;
7007 /* Operand for MOVW or MOVT. */
7009 po_misc_or_fail (parse_half (&str
));
7012 /* Register or expression. */
7013 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7014 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7016 /* Register or immediate. */
7017 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7018 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7020 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7022 if (!is_immediate_prefix (*str
))
7025 val
= parse_fpa_immediate (&str
);
7028 /* FPA immediates are encoded as registers 8-15.
7029 parse_fpa_immediate has already applied the offset. */
7030 inst
.operands
[i
].reg
= val
;
7031 inst
.operands
[i
].isreg
= 1;
7034 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7035 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7037 /* Two kinds of register. */
7040 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7042 || (rege
->type
!= REG_TYPE_MMXWR
7043 && rege
->type
!= REG_TYPE_MMXWC
7044 && rege
->type
!= REG_TYPE_MMXWCG
))
7046 inst
.error
= _("iWMMXt data or control register expected");
7049 inst
.operands
[i
].reg
= rege
->number
;
7050 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7056 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7058 || (rege
->type
!= REG_TYPE_MMXWC
7059 && rege
->type
!= REG_TYPE_MMXWCG
))
7061 inst
.error
= _("iWMMXt control register expected");
7064 inst
.operands
[i
].reg
= rege
->number
;
7065 inst
.operands
[i
].isreg
= 1;
7070 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7071 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7072 case OP_oROR
: val
= parse_ror (&str
); break;
7073 case OP_COND
: val
= parse_cond (&str
); break;
7074 case OP_oBARRIER_I15
:
7075 po_barrier_or_imm (str
); break;
7077 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7083 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7084 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7086 inst
.error
= _("Banked registers are not available with this "
7092 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7096 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7099 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7101 if (strncasecmp (str
, "APSR_", 5) == 0)
7108 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7109 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7110 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7111 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7112 default: found
= 16;
7116 inst
.operands
[i
].isvec
= 1;
7117 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7118 inst
.operands
[i
].reg
= REG_PC
;
7125 po_misc_or_fail (parse_tb (&str
));
7128 /* Register lists. */
7130 val
= parse_reg_list (&str
);
7133 inst
.operands
[i
].writeback
= 1;
7139 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7143 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7147 /* Allow Q registers too. */
7148 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7153 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7155 inst
.operands
[i
].issingle
= 1;
7160 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7165 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7166 &inst
.operands
[i
].vectype
);
7169 /* Addressing modes */
7171 po_misc_or_fail (parse_address (&str
, i
));
7175 po_misc_or_fail_no_backtrack (
7176 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7180 po_misc_or_fail_no_backtrack (
7181 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7185 po_misc_or_fail_no_backtrack (
7186 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7190 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7194 po_misc_or_fail_no_backtrack (
7195 parse_shifter_operand_group_reloc (&str
, i
));
7199 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7203 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7207 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7211 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7214 /* Various value-based sanity checks and shared operations. We
7215 do not signal immediate failures for the register constraints;
7216 this allows a syntax error to take precedence. */
7217 switch (op_parse_code
)
7225 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7226 inst
.error
= BAD_PC
;
7231 if (inst
.operands
[i
].isreg
)
7233 if (inst
.operands
[i
].reg
== REG_PC
)
7234 inst
.error
= BAD_PC
;
7235 else if (inst
.operands
[i
].reg
== REG_SP
7236 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7237 relaxed since ARMv8-A. */
7238 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7241 inst
.error
= BAD_SP
;
7247 if (inst
.operands
[i
].isreg
7248 && inst
.operands
[i
].reg
== REG_PC
7249 && (inst
.operands
[i
].writeback
|| thumb
))
7250 inst
.error
= BAD_PC
;
7259 case OP_oBARRIER_I15
:
7268 inst
.operands
[i
].imm
= val
;
7275 /* If we get here, this operand was successfully parsed. */
7276 inst
.operands
[i
].present
= 1;
7280 inst
.error
= BAD_ARGS
;
7285 /* The parse routine should already have set inst.error, but set a
7286 default here just in case. */
7288 inst
.error
= _("syntax error");
7292 /* Do not backtrack over a trailing optional argument that
7293 absorbed some text. We will only fail again, with the
7294 'garbage following instruction' error message, which is
7295 probably less helpful than the current one. */
7296 if (backtrack_index
== i
&& backtrack_pos
!= str
7297 && upat
[i
+1] == OP_stop
)
7300 inst
.error
= _("syntax error");
7304 /* Try again, skipping the optional argument at backtrack_pos. */
7305 str
= backtrack_pos
;
7306 inst
.error
= backtrack_error
;
7307 inst
.operands
[backtrack_index
].present
= 0;
7308 i
= backtrack_index
;
7312 /* Check that we have parsed all the arguments. */
7313 if (*str
!= '\0' && !inst
.error
)
7314 inst
.error
= _("garbage following instruction");
7316 return inst
.error
? FAIL
: SUCCESS
;
7319 #undef po_char_or_fail
7320 #undef po_reg_or_fail
7321 #undef po_reg_or_goto
7322 #undef po_imm_or_fail
7323 #undef po_scalar_or_fail
7324 #undef po_barrier_or_imm
7326 /* Shorthand macro for instruction encoding functions issuing errors. */
7327 #define constraint(expr, err) \
7338 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7339 instructions are unpredictable if these registers are used. This
7340 is the BadReg predicate in ARM's Thumb-2 documentation.
7342 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7343 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7344 #define reject_bad_reg(reg) \
7346 if (reg == REG_PC) \
7348 inst.error = BAD_PC; \
7351 else if (reg == REG_SP \
7352 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7354 inst.error = BAD_SP; \
7359 /* If REG is R13 (the stack pointer), warn that its use is
7361 #define warn_deprecated_sp(reg) \
7363 if (warn_on_deprecated && reg == REG_SP) \
7364 as_tsktsk (_("use of r13 is deprecated")); \
7367 /* Functions for operand encoding. ARM, then Thumb. */
7369 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7371 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7373 The only binary encoding difference is the Coprocessor number. Coprocessor
7374 9 is used for half-precision calculations or conversions. The format of the
7375 instruction is the same as the equivalent Coprocessor 10 instruction that
7376 exists for Single-Precision operation. */
7379 do_scalar_fp16_v82_encode (void)
7381 if (inst
.cond
!= COND_ALWAYS
)
7382 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7383 " the behaviour is UNPREDICTABLE"));
7384 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7387 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7388 mark_feature_used (&arm_ext_fp16
);
7391 /* If VAL can be encoded in the immediate field of an ARM instruction,
7392 return the encoded form. Otherwise, return FAIL. */
7395 encode_arm_immediate (unsigned int val
)
7402 for (i
= 2; i
< 32; i
+= 2)
7403 if ((a
= rotate_left (val
, i
)) <= 0xff)
7404 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7409 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7410 return the encoded form. Otherwise, return FAIL. */
7412 encode_thumb32_immediate (unsigned int val
)
7419 for (i
= 1; i
<= 24; i
++)
7422 if ((val
& ~(0xff << i
)) == 0)
7423 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7427 if (val
== ((a
<< 16) | a
))
7429 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7433 if (val
== ((a
<< 16) | a
))
7434 return 0x200 | (a
>> 8);
7438 /* Encode a VFP SP or DP register number into inst.instruction. */
7441 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7443 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7446 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7449 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7452 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7457 first_error (_("D register out of range for selected VFP version"));
7465 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7469 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7473 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7477 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7481 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7485 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7493 /* Encode a <shift> in an ARM-format instruction. The immediate,
7494 if any, is handled by md_apply_fix. */
7496 encode_arm_shift (int i
)
7498 /* register-shifted register. */
7499 if (inst
.operands
[i
].immisreg
)
7502 for (op_index
= 0; op_index
<= i
; ++op_index
)
7504 /* Check the operand only when it's presented. In pre-UAL syntax,
7505 if the destination register is the same as the first operand, two
7506 register form of the instruction can be used. */
7507 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7508 && inst
.operands
[op_index
].reg
== REG_PC
)
7509 as_warn (UNPRED_REG ("r15"));
7512 if (inst
.operands
[i
].imm
== REG_PC
)
7513 as_warn (UNPRED_REG ("r15"));
7516 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7517 inst
.instruction
|= SHIFT_ROR
<< 5;
7520 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7521 if (inst
.operands
[i
].immisreg
)
7523 inst
.instruction
|= SHIFT_BY_REG
;
7524 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7527 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7532 encode_arm_shifter_operand (int i
)
7534 if (inst
.operands
[i
].isreg
)
7536 inst
.instruction
|= inst
.operands
[i
].reg
;
7537 encode_arm_shift (i
);
7541 inst
.instruction
|= INST_IMMEDIATE
;
7542 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7543 inst
.instruction
|= inst
.operands
[i
].imm
;
7547 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7549 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7552 Generate an error if the operand is not a register. */
7553 constraint (!inst
.operands
[i
].isreg
,
7554 _("Instruction does not support =N addresses"));
7556 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7558 if (inst
.operands
[i
].preind
)
7562 inst
.error
= _("instruction does not accept preindexed addressing");
7565 inst
.instruction
|= PRE_INDEX
;
7566 if (inst
.operands
[i
].writeback
)
7567 inst
.instruction
|= WRITE_BACK
;
7570 else if (inst
.operands
[i
].postind
)
7572 gas_assert (inst
.operands
[i
].writeback
);
7574 inst
.instruction
|= WRITE_BACK
;
7576 else /* unindexed - only for coprocessor */
7578 inst
.error
= _("instruction does not accept unindexed addressing");
7582 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7583 && (((inst
.instruction
& 0x000f0000) >> 16)
7584 == ((inst
.instruction
& 0x0000f000) >> 12)))
7585 as_warn ((inst
.instruction
& LOAD_BIT
)
7586 ? _("destination register same as write-back base")
7587 : _("source register same as write-back base"));
7590 /* inst.operands[i] was set up by parse_address. Encode it into an
7591 ARM-format mode 2 load or store instruction. If is_t is true,
7592 reject forms that cannot be used with a T instruction (i.e. not
7595 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7597 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7599 encode_arm_addr_mode_common (i
, is_t
);
7601 if (inst
.operands
[i
].immisreg
)
7603 constraint ((inst
.operands
[i
].imm
== REG_PC
7604 || (is_pc
&& inst
.operands
[i
].writeback
)),
7606 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7607 inst
.instruction
|= inst
.operands
[i
].imm
;
7608 if (!inst
.operands
[i
].negative
)
7609 inst
.instruction
|= INDEX_UP
;
7610 if (inst
.operands
[i
].shifted
)
7612 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7613 inst
.instruction
|= SHIFT_ROR
<< 5;
7616 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7617 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7621 else /* immediate offset in inst.reloc */
7623 if (is_pc
&& !inst
.reloc
.pc_rel
)
7625 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7627 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7628 cannot use PC in addressing.
7629 PC cannot be used in writeback addressing, either. */
7630 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7633 /* Use of PC in str is deprecated for ARMv7. */
7634 if (warn_on_deprecated
7636 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7637 as_tsktsk (_("use of PC in this instruction is deprecated"));
7640 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7642 /* Prefer + for zero encoded value. */
7643 if (!inst
.operands
[i
].negative
)
7644 inst
.instruction
|= INDEX_UP
;
7645 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7650 /* inst.operands[i] was set up by parse_address. Encode it into an
7651 ARM-format mode 3 load or store instruction. Reject forms that
7652 cannot be used with such instructions. If is_t is true, reject
7653 forms that cannot be used with a T instruction (i.e. not
7656 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7658 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7660 inst
.error
= _("instruction does not accept scaled register index");
7664 encode_arm_addr_mode_common (i
, is_t
);
7666 if (inst
.operands
[i
].immisreg
)
7668 constraint ((inst
.operands
[i
].imm
== REG_PC
7669 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7671 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7673 inst
.instruction
|= inst
.operands
[i
].imm
;
7674 if (!inst
.operands
[i
].negative
)
7675 inst
.instruction
|= INDEX_UP
;
7677 else /* immediate offset in inst.reloc */
7679 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7680 && inst
.operands
[i
].writeback
),
7682 inst
.instruction
|= HWOFFSET_IMM
;
7683 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7685 /* Prefer + for zero encoded value. */
7686 if (!inst
.operands
[i
].negative
)
7687 inst
.instruction
|= INDEX_UP
;
7689 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7694 /* Write immediate bits [7:0] to the following locations:
7696 |28/24|23 19|18 16|15 4|3 0|
7697 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7699 This function is used by VMOV/VMVN/VORR/VBIC. */
7702 neon_write_immbits (unsigned immbits
)
7704 inst
.instruction
|= immbits
& 0xf;
7705 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7706 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7709 /* Invert low-order SIZE bits of XHI:XLO. */
7712 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7714 unsigned immlo
= xlo
? *xlo
: 0;
7715 unsigned immhi
= xhi
? *xhi
: 0;
7720 immlo
= (~immlo
) & 0xff;
7724 immlo
= (~immlo
) & 0xffff;
7728 immhi
= (~immhi
) & 0xffffffff;
7732 immlo
= (~immlo
) & 0xffffffff;
7746 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7750 neon_bits_same_in_bytes (unsigned imm
)
7752 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7753 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7754 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7755 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7758 /* For immediate of above form, return 0bABCD. */
7761 neon_squash_bits (unsigned imm
)
7763 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7764 | ((imm
& 0x01000000) >> 21);
7767 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7770 neon_qfloat_bits (unsigned imm
)
7772 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7775 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7776 the instruction. *OP is passed as the initial value of the op field, and
7777 may be set to a different value depending on the constant (i.e.
7778 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7779 MVN). If the immediate looks like a repeated pattern then also
7780 try smaller element sizes. */
7783 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7784 unsigned *immbits
, int *op
, int size
,
7785 enum neon_el_type type
)
7787 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7789 if (type
== NT_float
&& !float_p
)
7792 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7794 if (size
!= 32 || *op
== 1)
7796 *immbits
= neon_qfloat_bits (immlo
);
7802 if (neon_bits_same_in_bytes (immhi
)
7803 && neon_bits_same_in_bytes (immlo
))
7807 *immbits
= (neon_squash_bits (immhi
) << 4)
7808 | neon_squash_bits (immlo
);
7819 if (immlo
== (immlo
& 0x000000ff))
7824 else if (immlo
== (immlo
& 0x0000ff00))
7826 *immbits
= immlo
>> 8;
7829 else if (immlo
== (immlo
& 0x00ff0000))
7831 *immbits
= immlo
>> 16;
7834 else if (immlo
== (immlo
& 0xff000000))
7836 *immbits
= immlo
>> 24;
7839 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7841 *immbits
= (immlo
>> 8) & 0xff;
7844 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7846 *immbits
= (immlo
>> 16) & 0xff;
7850 if ((immlo
& 0xffff) != (immlo
>> 16))
7857 if (immlo
== (immlo
& 0x000000ff))
7862 else if (immlo
== (immlo
& 0x0000ff00))
7864 *immbits
= immlo
>> 8;
7868 if ((immlo
& 0xff) != (immlo
>> 8))
7873 if (immlo
== (immlo
& 0x000000ff))
7875 /* Don't allow MVN with 8-bit immediate. */
7885 #if defined BFD_HOST_64_BIT
7886 /* Returns TRUE if double precision value V may be cast
7887 to single precision without loss of accuracy. */
7890 is_double_a_single (bfd_int64_t v
)
7892 int exp
= (int)((v
>> 52) & 0x7FF);
7893 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7895 return (exp
== 0 || exp
== 0x7FF
7896 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7897 && (mantissa
& 0x1FFFFFFFl
) == 0;
7900 /* Returns a double precision value casted to single precision
7901 (ignoring the least significant bits in exponent and mantissa). */
7904 double_to_single (bfd_int64_t v
)
7906 int sign
= (int) ((v
>> 63) & 1l);
7907 int exp
= (int) ((v
>> 52) & 0x7FF);
7908 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7914 exp
= exp
- 1023 + 127;
7923 /* No denormalized numbers. */
7929 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7931 #endif /* BFD_HOST_64_BIT */
7940 static void do_vfp_nsyn_opcode (const char *);
7942 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7943 Determine whether it can be performed with a move instruction; if
7944 it can, convert inst.instruction to that move instruction and
7945 return TRUE; if it can't, convert inst.instruction to a literal-pool
7946 load and return FALSE. If this is not a valid thing to do in the
7947 current context, set inst.error and return TRUE.
7949 inst.operands[i] describes the destination register. */
7952 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7955 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7956 bfd_boolean arm_p
= (t
== CONST_ARM
);
7959 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7963 if ((inst
.instruction
& tbit
) == 0)
7965 inst
.error
= _("invalid pseudo operation");
7969 if (inst
.reloc
.exp
.X_op
!= O_constant
7970 && inst
.reloc
.exp
.X_op
!= O_symbol
7971 && inst
.reloc
.exp
.X_op
!= O_big
)
7973 inst
.error
= _("constant expression expected");
7977 if (inst
.reloc
.exp
.X_op
== O_constant
7978 || inst
.reloc
.exp
.X_op
== O_big
)
7980 #if defined BFD_HOST_64_BIT
7985 if (inst
.reloc
.exp
.X_op
== O_big
)
7987 LITTLENUM_TYPE w
[X_PRECISION
];
7990 if (inst
.reloc
.exp
.X_add_number
== -1)
7992 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7994 /* FIXME: Should we check words w[2..5] ? */
7999 #if defined BFD_HOST_64_BIT
8001 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8002 << LITTLENUM_NUMBER_OF_BITS
)
8003 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8004 << LITTLENUM_NUMBER_OF_BITS
)
8005 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8006 << LITTLENUM_NUMBER_OF_BITS
)
8007 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8009 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8010 | (l
[0] & LITTLENUM_MASK
);
8014 v
= inst
.reloc
.exp
.X_add_number
;
8016 if (!inst
.operands
[i
].issingle
)
8020 /* LDR should not use lead in a flag-setting instruction being
8021 chosen so we do not check whether movs can be used. */
8023 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8024 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8025 && inst
.operands
[i
].reg
!= 13
8026 && inst
.operands
[i
].reg
!= 15)
8028 /* Check if on thumb2 it can be done with a mov.w, mvn or
8029 movw instruction. */
8030 unsigned int newimm
;
8031 bfd_boolean isNegated
;
8033 newimm
= encode_thumb32_immediate (v
);
8034 if (newimm
!= (unsigned int) FAIL
)
8038 newimm
= encode_thumb32_immediate (~v
);
8039 if (newimm
!= (unsigned int) FAIL
)
8043 /* The number can be loaded with a mov.w or mvn
8045 if (newimm
!= (unsigned int) FAIL
8046 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8048 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8049 | (inst
.operands
[i
].reg
<< 8));
8050 /* Change to MOVN. */
8051 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8052 inst
.instruction
|= (newimm
& 0x800) << 15;
8053 inst
.instruction
|= (newimm
& 0x700) << 4;
8054 inst
.instruction
|= (newimm
& 0x0ff);
8057 /* The number can be loaded with a movw instruction. */
8058 else if ((v
& ~0xFFFF) == 0
8059 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8061 int imm
= v
& 0xFFFF;
8063 inst
.instruction
= 0xf2400000; /* MOVW. */
8064 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8065 inst
.instruction
|= (imm
& 0xf000) << 4;
8066 inst
.instruction
|= (imm
& 0x0800) << 15;
8067 inst
.instruction
|= (imm
& 0x0700) << 4;
8068 inst
.instruction
|= (imm
& 0x00ff);
8075 int value
= encode_arm_immediate (v
);
8079 /* This can be done with a mov instruction. */
8080 inst
.instruction
&= LITERAL_MASK
;
8081 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8082 inst
.instruction
|= value
& 0xfff;
8086 value
= encode_arm_immediate (~ v
);
8089 /* This can be done with a mvn instruction. */
8090 inst
.instruction
&= LITERAL_MASK
;
8091 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8092 inst
.instruction
|= value
& 0xfff;
8096 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8099 unsigned immbits
= 0;
8100 unsigned immlo
= inst
.operands
[1].imm
;
8101 unsigned immhi
= inst
.operands
[1].regisimm
8102 ? inst
.operands
[1].reg
8103 : inst
.reloc
.exp
.X_unsigned
8105 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8106 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8107 &op
, 64, NT_invtype
);
8111 neon_invert_size (&immlo
, &immhi
, 64);
8113 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8114 &op
, 64, NT_invtype
);
8119 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8125 /* Fill other bits in vmov encoding for both thumb and arm. */
8127 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8129 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8130 neon_write_immbits (immbits
);
8138 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8139 if (inst
.operands
[i
].issingle
8140 && is_quarter_float (inst
.operands
[1].imm
)
8141 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8143 inst
.operands
[1].imm
=
8144 neon_qfloat_bits (v
);
8145 do_vfp_nsyn_opcode ("fconsts");
8149 /* If our host does not support a 64-bit type then we cannot perform
8150 the following optimization. This mean that there will be a
8151 discrepancy between the output produced by an assembler built for
8152 a 32-bit-only host and the output produced from a 64-bit host, but
8153 this cannot be helped. */
8154 #if defined BFD_HOST_64_BIT
8155 else if (!inst
.operands
[1].issingle
8156 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8158 if (is_double_a_single (v
)
8159 && is_quarter_float (double_to_single (v
)))
8161 inst
.operands
[1].imm
=
8162 neon_qfloat_bits (double_to_single (v
));
8163 do_vfp_nsyn_opcode ("fconstd");
8171 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8172 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8175 inst
.operands
[1].reg
= REG_PC
;
8176 inst
.operands
[1].isreg
= 1;
8177 inst
.operands
[1].preind
= 1;
8178 inst
.reloc
.pc_rel
= 1;
8179 inst
.reloc
.type
= (thumb_p
8180 ? BFD_RELOC_ARM_THUMB_OFFSET
8182 ? BFD_RELOC_ARM_HWLITERAL
8183 : BFD_RELOC_ARM_LITERAL
));
8187 /* inst.operands[i] was set up by parse_address. Encode it into an
8188 ARM-format instruction. Reject all forms which cannot be encoded
8189 into a coprocessor load/store instruction. If wb_ok is false,
8190 reject use of writeback; if unind_ok is false, reject use of
8191 unindexed addressing. If reloc_override is not 0, use it instead
8192 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8193 (in which case it is preserved). */
8196 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8198 if (!inst
.operands
[i
].isreg
)
8201 if (! inst
.operands
[0].isvec
)
8203 inst
.error
= _("invalid co-processor operand");
8206 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8210 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8212 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8214 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8216 gas_assert (!inst
.operands
[i
].writeback
);
8219 inst
.error
= _("instruction does not support unindexed addressing");
8222 inst
.instruction
|= inst
.operands
[i
].imm
;
8223 inst
.instruction
|= INDEX_UP
;
8227 if (inst
.operands
[i
].preind
)
8228 inst
.instruction
|= PRE_INDEX
;
8230 if (inst
.operands
[i
].writeback
)
8232 if (inst
.operands
[i
].reg
== REG_PC
)
8234 inst
.error
= _("pc may not be used with write-back");
8239 inst
.error
= _("instruction does not support writeback");
8242 inst
.instruction
|= WRITE_BACK
;
8246 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8247 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8248 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8249 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8252 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8254 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8257 /* Prefer + for zero encoded value. */
8258 if (!inst
.operands
[i
].negative
)
8259 inst
.instruction
|= INDEX_UP
;
8264 /* Functions for instruction encoding, sorted by sub-architecture.
8265 First some generics; their names are taken from the conventional
8266 bit positions for register arguments in ARM format instructions. */
8276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8282 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8289 inst
.instruction
|= inst
.operands
[1].reg
;
8295 inst
.instruction
|= inst
.operands
[0].reg
;
8296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8309 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8310 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8316 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8317 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8321 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8323 if (ARM_CPU_IS_ANY (cpu_variant
))
8325 as_tsktsk ("%s", msg
);
8328 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8340 unsigned Rn
= inst
.operands
[2].reg
;
8341 /* Enforce restrictions on SWP instruction. */
8342 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8344 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8345 _("Rn must not overlap other operands"));
8347 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8349 if (!check_obsolete (&arm_ext_v8
,
8350 _("swp{b} use is obsoleted for ARMv8 and later"))
8351 && warn_on_deprecated
8352 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8353 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8357 inst
.instruction
|= inst
.operands
[1].reg
;
8358 inst
.instruction
|= Rn
<< 16;
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8365 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8366 inst
.instruction
|= inst
.operands
[2].reg
;
8372 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8373 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8374 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8375 || inst
.reloc
.exp
.X_add_number
!= 0),
8377 inst
.instruction
|= inst
.operands
[0].reg
;
8378 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8379 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8385 inst
.instruction
|= inst
.operands
[0].imm
;
8391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8392 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8395 /* ARM instructions, in alphabetical order by function name (except
8396 that wrapper functions appear immediately after the function they
8399 /* This is a pseudo-op of the form "adr rd, label" to be converted
8400 into a relative address of the form "add rd, pc, #label-.-8". */
8405 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8407 /* Frag hacking will turn this into a sub instruction if the offset turns
8408 out to be negative. */
8409 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8410 inst
.reloc
.pc_rel
= 1;
8411 inst
.reloc
.exp
.X_add_number
-= 8;
8413 if (inst
.reloc
.exp
.X_op
== O_symbol
8414 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8415 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8416 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8417 inst
.reloc
.exp
.X_add_number
+= 1;
8420 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8421 into a relative address of the form:
8422 add rd, pc, #low(label-.-8)"
8423 add rd, rd, #high(label-.-8)" */
8428 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8430 /* Frag hacking will turn this into a sub instruction if the offset turns
8431 out to be negative. */
8432 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8433 inst
.reloc
.pc_rel
= 1;
8434 inst
.size
= INSN_SIZE
* 2;
8435 inst
.reloc
.exp
.X_add_number
-= 8;
8437 if (inst
.reloc
.exp
.X_op
== O_symbol
8438 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8439 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8440 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8441 inst
.reloc
.exp
.X_add_number
+= 1;
8447 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8448 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8450 if (!inst
.operands
[1].present
)
8451 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8453 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8454 encode_arm_shifter_operand (2);
8460 if (inst
.operands
[0].present
)
8461 inst
.instruction
|= inst
.operands
[0].imm
;
8463 inst
.instruction
|= 0xf;
8469 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8470 constraint (msb
> 32, _("bit-field extends past end of register"));
8471 /* The instruction encoding stores the LSB and MSB,
8472 not the LSB and width. */
8473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8474 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8475 inst
.instruction
|= (msb
- 1) << 16;
8483 /* #0 in second position is alternative syntax for bfc, which is
8484 the same instruction but with REG_PC in the Rm field. */
8485 if (!inst
.operands
[1].isreg
)
8486 inst
.operands
[1].reg
= REG_PC
;
8488 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8489 constraint (msb
> 32, _("bit-field extends past end of register"));
8490 /* The instruction encoding stores the LSB and MSB,
8491 not the LSB and width. */
8492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8493 inst
.instruction
|= inst
.operands
[1].reg
;
8494 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8495 inst
.instruction
|= (msb
- 1) << 16;
8501 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8502 _("bit-field extends past end of register"));
8503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8504 inst
.instruction
|= inst
.operands
[1].reg
;
8505 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8506 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8509 /* ARM V5 breakpoint instruction (argument parse)
8510 BKPT <16 bit unsigned immediate>
8511 Instruction is not conditional.
8512 The bit pattern given in insns[] has the COND_ALWAYS condition,
8513 and it is an error if the caller tried to override that. */
8518 /* Top 12 of 16 bits to bits 19:8. */
8519 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8521 /* Bottom 4 of 16 bits to bits 3:0. */
8522 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8526 encode_branch (int default_reloc
)
8528 if (inst
.operands
[0].hasreloc
)
8530 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8531 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8532 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8533 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8534 ? BFD_RELOC_ARM_PLT32
8535 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8538 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8539 inst
.reloc
.pc_rel
= 1;
8546 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8547 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8550 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8557 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8559 if (inst
.cond
== COND_ALWAYS
)
8560 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8562 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8566 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8569 /* ARM V5 branch-link-exchange instruction (argument parse)
8570 BLX <target_addr> ie BLX(1)
8571 BLX{<condition>} <Rm> ie BLX(2)
8572 Unfortunately, there are two different opcodes for this mnemonic.
8573 So, the insns[].value is not used, and the code here zaps values
8574 into inst.instruction.
8575 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8580 if (inst
.operands
[0].isreg
)
8582 /* Arg is a register; the opcode provided by insns[] is correct.
8583 It is not illegal to do "blx pc", just useless. */
8584 if (inst
.operands
[0].reg
== REG_PC
)
8585 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8587 inst
.instruction
|= inst
.operands
[0].reg
;
8591 /* Arg is an address; this instruction cannot be executed
8592 conditionally, and the opcode must be adjusted.
8593 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8594 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8595 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8596 inst
.instruction
= 0xfa000000;
8597 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8604 bfd_boolean want_reloc
;
8606 if (inst
.operands
[0].reg
== REG_PC
)
8607 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8609 inst
.instruction
|= inst
.operands
[0].reg
;
8610 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8611 it is for ARMv4t or earlier. */
8612 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8613 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8617 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8622 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8626 /* ARM v5TEJ. Jump to Jazelle code. */
8631 if (inst
.operands
[0].reg
== REG_PC
)
8632 as_tsktsk (_("use of r15 in bxj is not really useful"));
8634 inst
.instruction
|= inst
.operands
[0].reg
;
8637 /* Co-processor data operation:
8638 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8639 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8643 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8644 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8645 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8646 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8647 inst
.instruction
|= inst
.operands
[4].reg
;
8648 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8655 encode_arm_shifter_operand (1);
8658 /* Transfer between coprocessor and ARM registers.
8659 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8664 No special properties. */
8666 struct deprecated_coproc_regs_s
8673 arm_feature_set deprecated
;
8674 arm_feature_set obsoleted
;
8675 const char *dep_msg
;
8676 const char *obs_msg
;
8679 #define DEPR_ACCESS_V8 \
8680 N_("This coprocessor register access is deprecated in ARMv8")
8682 /* Table of all deprecated coprocessor registers. */
8683 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8685 {15, 0, 7, 10, 5, /* CP15DMB. */
8686 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8687 DEPR_ACCESS_V8
, NULL
},
8688 {15, 0, 7, 10, 4, /* CP15DSB. */
8689 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8690 DEPR_ACCESS_V8
, NULL
},
8691 {15, 0, 7, 5, 4, /* CP15ISB. */
8692 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8693 DEPR_ACCESS_V8
, NULL
},
8694 {14, 6, 1, 0, 0, /* TEEHBR. */
8695 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8696 DEPR_ACCESS_V8
, NULL
},
8697 {14, 6, 0, 0, 0, /* TEECR. */
8698 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8699 DEPR_ACCESS_V8
, NULL
},
8702 #undef DEPR_ACCESS_V8
8704 static const size_t deprecated_coproc_reg_count
=
8705 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8713 Rd
= inst
.operands
[2].reg
;
8716 if (inst
.instruction
== 0xee000010
8717 || inst
.instruction
== 0xfe000010)
8719 reject_bad_reg (Rd
);
8720 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8722 constraint (Rd
== REG_SP
, BAD_SP
);
8727 if (inst
.instruction
== 0xe000010)
8728 constraint (Rd
== REG_PC
, BAD_PC
);
8731 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8733 const struct deprecated_coproc_regs_s
*r
=
8734 deprecated_coproc_regs
+ i
;
8736 if (inst
.operands
[0].reg
== r
->cp
8737 && inst
.operands
[1].imm
== r
->opc1
8738 && inst
.operands
[3].reg
== r
->crn
8739 && inst
.operands
[4].reg
== r
->crm
8740 && inst
.operands
[5].imm
== r
->opc2
)
8742 if (! ARM_CPU_IS_ANY (cpu_variant
)
8743 && warn_on_deprecated
8744 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8745 as_tsktsk ("%s", r
->dep_msg
);
8749 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8750 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8751 inst
.instruction
|= Rd
<< 12;
8752 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8753 inst
.instruction
|= inst
.operands
[4].reg
;
8754 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8757 /* Transfer between coprocessor register and pair of ARM registers.
8758 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8763 Two XScale instructions are special cases of these:
8765 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8766 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8768 Result unpredictable if Rd or Rn is R15. */
8775 Rd
= inst
.operands
[2].reg
;
8776 Rn
= inst
.operands
[3].reg
;
8780 reject_bad_reg (Rd
);
8781 reject_bad_reg (Rn
);
8785 constraint (Rd
== REG_PC
, BAD_PC
);
8786 constraint (Rn
== REG_PC
, BAD_PC
);
8789 /* Only check the MRRC{2} variants. */
8790 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8792 /* If Rd == Rn, error that the operation is
8793 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8794 constraint (Rd
== Rn
, BAD_OVERLAP
);
8797 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8798 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8799 inst
.instruction
|= Rd
<< 12;
8800 inst
.instruction
|= Rn
<< 16;
8801 inst
.instruction
|= inst
.operands
[4].reg
;
8807 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8808 if (inst
.operands
[1].present
)
8810 inst
.instruction
|= CPSI_MMOD
;
8811 inst
.instruction
|= inst
.operands
[1].imm
;
8818 inst
.instruction
|= inst
.operands
[0].imm
;
8824 unsigned Rd
, Rn
, Rm
;
8826 Rd
= inst
.operands
[0].reg
;
8827 Rn
= (inst
.operands
[1].present
8828 ? inst
.operands
[1].reg
: Rd
);
8829 Rm
= inst
.operands
[2].reg
;
8831 constraint ((Rd
== REG_PC
), BAD_PC
);
8832 constraint ((Rn
== REG_PC
), BAD_PC
);
8833 constraint ((Rm
== REG_PC
), BAD_PC
);
8835 inst
.instruction
|= Rd
<< 16;
8836 inst
.instruction
|= Rn
<< 0;
8837 inst
.instruction
|= Rm
<< 8;
8843 /* There is no IT instruction in ARM mode. We
8844 process it to do the validation as if in
8845 thumb mode, just in case the code gets
8846 assembled for thumb using the unified syntax. */
8851 set_it_insn_type (IT_INSN
);
8852 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8853 now_it
.cc
= inst
.operands
[0].imm
;
8857 /* If there is only one register in the register list,
8858 then return its register number. Otherwise return -1. */
8860 only_one_reg_in_list (int range
)
8862 int i
= ffs (range
) - 1;
8863 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8867 encode_ldmstm(int from_push_pop_mnem
)
8869 int base_reg
= inst
.operands
[0].reg
;
8870 int range
= inst
.operands
[1].imm
;
8873 inst
.instruction
|= base_reg
<< 16;
8874 inst
.instruction
|= range
;
8876 if (inst
.operands
[1].writeback
)
8877 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8879 if (inst
.operands
[0].writeback
)
8881 inst
.instruction
|= WRITE_BACK
;
8882 /* Check for unpredictable uses of writeback. */
8883 if (inst
.instruction
& LOAD_BIT
)
8885 /* Not allowed in LDM type 2. */
8886 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8887 && ((range
& (1 << REG_PC
)) == 0))
8888 as_warn (_("writeback of base register is UNPREDICTABLE"));
8889 /* Only allowed if base reg not in list for other types. */
8890 else if (range
& (1 << base_reg
))
8891 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8895 /* Not allowed for type 2. */
8896 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8897 as_warn (_("writeback of base register is UNPREDICTABLE"));
8898 /* Only allowed if base reg not in list, or first in list. */
8899 else if ((range
& (1 << base_reg
))
8900 && (range
& ((1 << base_reg
) - 1)))
8901 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8905 /* If PUSH/POP has only one register, then use the A2 encoding. */
8906 one_reg
= only_one_reg_in_list (range
);
8907 if (from_push_pop_mnem
&& one_reg
>= 0)
8909 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8911 inst
.instruction
&= A_COND_MASK
;
8912 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8913 inst
.instruction
|= one_reg
<< 12;
8920 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8923 /* ARMv5TE load-consecutive (argument parse)
8932 constraint (inst
.operands
[0].reg
% 2 != 0,
8933 _("first transfer register must be even"));
8934 constraint (inst
.operands
[1].present
8935 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8936 _("can only transfer two consecutive registers"));
8937 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8938 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8940 if (!inst
.operands
[1].present
)
8941 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8943 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8944 register and the first register written; we have to diagnose
8945 overlap between the base and the second register written here. */
8947 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8948 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8949 as_warn (_("base register written back, and overlaps "
8950 "second transfer register"));
8952 if (!(inst
.instruction
& V4_STR_BIT
))
8954 /* For an index-register load, the index register must not overlap the
8955 destination (even if not write-back). */
8956 if (inst
.operands
[2].immisreg
8957 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8958 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8959 as_warn (_("index register overlaps transfer register"));
8961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8962 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8968 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8969 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8970 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8971 || inst
.operands
[1].negative
8972 /* This can arise if the programmer has written
8974 or if they have mistakenly used a register name as the last
8977 It is very difficult to distinguish between these two cases
8978 because "rX" might actually be a label. ie the register
8979 name has been occluded by a symbol of the same name. So we
8980 just generate a general 'bad addressing mode' type error
8981 message and leave it up to the programmer to discover the
8982 true cause and fix their mistake. */
8983 || (inst
.operands
[1].reg
== REG_PC
),
8986 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8987 || inst
.reloc
.exp
.X_add_number
!= 0,
8988 _("offset must be zero in ARM encoding"));
8990 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8994 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9000 constraint (inst
.operands
[0].reg
% 2 != 0,
9001 _("even register required"));
9002 constraint (inst
.operands
[1].present
9003 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9004 _("can only load two consecutive registers"));
9005 /* If op 1 were present and equal to PC, this function wouldn't
9006 have been called in the first place. */
9007 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9010 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9013 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9014 which is not a multiple of four is UNPREDICTABLE. */
9016 check_ldr_r15_aligned (void)
9018 constraint (!(inst
.operands
[1].immisreg
)
9019 && (inst
.operands
[0].reg
== REG_PC
9020 && inst
.operands
[1].reg
== REG_PC
9021 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9022 _("ldr to register 15 must be 4-byte aligned"));
9028 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9029 if (!inst
.operands
[1].isreg
)
9030 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9032 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9033 check_ldr_r15_aligned ();
9039 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9041 if (inst
.operands
[1].preind
)
9043 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9044 || inst
.reloc
.exp
.X_add_number
!= 0,
9045 _("this instruction requires a post-indexed address"));
9047 inst
.operands
[1].preind
= 0;
9048 inst
.operands
[1].postind
= 1;
9049 inst
.operands
[1].writeback
= 1;
9051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9052 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9055 /* Halfword and signed-byte load/store operations. */
9060 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9062 if (!inst
.operands
[1].isreg
)
9063 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9065 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9071 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9073 if (inst
.operands
[1].preind
)
9075 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9076 || inst
.reloc
.exp
.X_add_number
!= 0,
9077 _("this instruction requires a post-indexed address"));
9079 inst
.operands
[1].preind
= 0;
9080 inst
.operands
[1].postind
= 1;
9081 inst
.operands
[1].writeback
= 1;
9083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9084 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9087 /* Co-processor register load/store.
9088 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9092 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9093 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9094 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9100 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9101 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9102 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9103 && !(inst
.instruction
& 0x00400000))
9104 as_tsktsk (_("Rd and Rm should be different in mla"));
9106 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9107 inst
.instruction
|= inst
.operands
[1].reg
;
9108 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9109 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9115 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9116 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9119 encode_arm_shifter_operand (1);
9122 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9129 top
= (inst
.instruction
& 0x00400000) != 0;
9130 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9131 _(":lower16: not allowed in this instruction"));
9132 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9133 _(":upper16: not allowed in this instruction"));
9134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9135 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9137 imm
= inst
.reloc
.exp
.X_add_number
;
9138 /* The value is in two pieces: 0:11, 16:19. */
9139 inst
.instruction
|= (imm
& 0x00000fff);
9140 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9145 do_vfp_nsyn_mrs (void)
9147 if (inst
.operands
[0].isvec
)
9149 if (inst
.operands
[1].reg
!= 1)
9150 first_error (_("operand 1 must be FPSCR"));
9151 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9152 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9153 do_vfp_nsyn_opcode ("fmstat");
9155 else if (inst
.operands
[1].isvec
)
9156 do_vfp_nsyn_opcode ("fmrx");
9164 do_vfp_nsyn_msr (void)
9166 if (inst
.operands
[0].isvec
)
9167 do_vfp_nsyn_opcode ("fmxr");
9177 unsigned Rt
= inst
.operands
[0].reg
;
9179 if (thumb_mode
&& Rt
== REG_SP
)
9181 inst
.error
= BAD_SP
;
9185 /* MVFR2 is only valid at ARMv8-A. */
9186 if (inst
.operands
[1].reg
== 5)
9187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9190 /* APSR_ sets isvec. All other refs to PC are illegal. */
9191 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9193 inst
.error
= BAD_PC
;
9197 /* If we get through parsing the register name, we just insert the number
9198 generated into the instruction without further validation. */
9199 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9200 inst
.instruction
|= (Rt
<< 12);
9206 unsigned Rt
= inst
.operands
[1].reg
;
9209 reject_bad_reg (Rt
);
9210 else if (Rt
== REG_PC
)
9212 inst
.error
= BAD_PC
;
9216 /* MVFR2 is only valid for ARMv8-A. */
9217 if (inst
.operands
[0].reg
== 5)
9218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9221 /* If we get through parsing the register name, we just insert the number
9222 generated into the instruction without further validation. */
9223 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9224 inst
.instruction
|= (Rt
<< 12);
9232 if (do_vfp_nsyn_mrs () == SUCCESS
)
9235 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9238 if (inst
.operands
[1].isreg
)
9240 br
= inst
.operands
[1].reg
;
9241 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9242 as_bad (_("bad register for mrs"));
9246 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9247 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9249 _("'APSR', 'CPSR' or 'SPSR' expected"));
9250 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9253 inst
.instruction
|= br
;
9256 /* Two possible forms:
9257 "{C|S}PSR_<field>, Rm",
9258 "{C|S}PSR_f, #expression". */
9263 if (do_vfp_nsyn_msr () == SUCCESS
)
9266 inst
.instruction
|= inst
.operands
[0].imm
;
9267 if (inst
.operands
[1].isreg
)
9268 inst
.instruction
|= inst
.operands
[1].reg
;
9271 inst
.instruction
|= INST_IMMEDIATE
;
9272 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9273 inst
.reloc
.pc_rel
= 0;
9280 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9282 if (!inst
.operands
[2].present
)
9283 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9284 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9285 inst
.instruction
|= inst
.operands
[1].reg
;
9286 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9288 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9289 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9290 as_tsktsk (_("Rd and Rm should be different in mul"));
9293 /* Long Multiply Parser
9294 UMULL RdLo, RdHi, Rm, Rs
9295 SMULL RdLo, RdHi, Rm, Rs
9296 UMLAL RdLo, RdHi, Rm, Rs
9297 SMLAL RdLo, RdHi, Rm, Rs. */
9302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9304 inst
.instruction
|= inst
.operands
[2].reg
;
9305 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9307 /* rdhi and rdlo must be different. */
9308 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9309 as_tsktsk (_("rdhi and rdlo must be different"));
9311 /* rdhi, rdlo and rm must all be different before armv6. */
9312 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9313 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9314 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9315 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9321 if (inst
.operands
[0].present
9322 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9324 /* Architectural NOP hints are CPSR sets with no bits selected. */
9325 inst
.instruction
&= 0xf0000000;
9326 inst
.instruction
|= 0x0320f000;
9327 if (inst
.operands
[0].present
)
9328 inst
.instruction
|= inst
.operands
[0].imm
;
9332 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9333 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9334 Condition defaults to COND_ALWAYS.
9335 Error if Rd, Rn or Rm are R15. */
9340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9341 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9342 inst
.instruction
|= inst
.operands
[2].reg
;
9343 if (inst
.operands
[3].present
)
9344 encode_arm_shift (3);
9347 /* ARM V6 PKHTB (Argument Parse). */
9352 if (!inst
.operands
[3].present
)
9354 /* If the shift specifier is omitted, turn the instruction
9355 into pkhbt rd, rm, rn. */
9356 inst
.instruction
&= 0xfff00010;
9357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9358 inst
.instruction
|= inst
.operands
[1].reg
;
9359 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9364 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9365 inst
.instruction
|= inst
.operands
[2].reg
;
9366 encode_arm_shift (3);
9370 /* ARMv5TE: Preload-Cache
9371 MP Extensions: Preload for write
9375 Syntactically, like LDR with B=1, W=0, L=1. */
9380 constraint (!inst
.operands
[0].isreg
,
9381 _("'[' expected after PLD mnemonic"));
9382 constraint (inst
.operands
[0].postind
,
9383 _("post-indexed expression used in preload instruction"));
9384 constraint (inst
.operands
[0].writeback
,
9385 _("writeback used in preload instruction"));
9386 constraint (!inst
.operands
[0].preind
,
9387 _("unindexed addressing used in preload instruction"));
9388 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9391 /* ARMv7: PLI <addr_mode> */
9395 constraint (!inst
.operands
[0].isreg
,
9396 _("'[' expected after PLI mnemonic"));
9397 constraint (inst
.operands
[0].postind
,
9398 _("post-indexed expression used in preload instruction"));
9399 constraint (inst
.operands
[0].writeback
,
9400 _("writeback used in preload instruction"));
9401 constraint (!inst
.operands
[0].preind
,
9402 _("unindexed addressing used in preload instruction"));
9403 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9404 inst
.instruction
&= ~PRE_INDEX
;
9410 constraint (inst
.operands
[0].writeback
,
9411 _("push/pop do not support {reglist}^"));
9412 inst
.operands
[1] = inst
.operands
[0];
9413 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9414 inst
.operands
[0].isreg
= 1;
9415 inst
.operands
[0].writeback
= 1;
9416 inst
.operands
[0].reg
= REG_SP
;
9417 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9420 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9421 word at the specified address and the following word
9423 Unconditionally executed.
9424 Error if Rn is R15. */
9429 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9430 if (inst
.operands
[0].writeback
)
9431 inst
.instruction
|= WRITE_BACK
;
9434 /* ARM V6 ssat (argument parse). */
9439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9440 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9441 inst
.instruction
|= inst
.operands
[2].reg
;
9443 if (inst
.operands
[3].present
)
9444 encode_arm_shift (3);
9447 /* ARM V6 usat (argument parse). */
9452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9453 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9454 inst
.instruction
|= inst
.operands
[2].reg
;
9456 if (inst
.operands
[3].present
)
9457 encode_arm_shift (3);
9460 /* ARM V6 ssat16 (argument parse). */
9465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9466 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9467 inst
.instruction
|= inst
.operands
[2].reg
;
9473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9474 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9475 inst
.instruction
|= inst
.operands
[2].reg
;
9478 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9479 preserving the other bits.
9481 setend <endian_specifier>, where <endian_specifier> is either
9487 if (warn_on_deprecated
9488 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9489 as_tsktsk (_("setend use is deprecated for ARMv8"));
9491 if (inst
.operands
[0].imm
)
9492 inst
.instruction
|= 0x200;
9498 unsigned int Rm
= (inst
.operands
[1].present
9499 ? inst
.operands
[1].reg
9500 : inst
.operands
[0].reg
);
9502 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9503 inst
.instruction
|= Rm
;
9504 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9506 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9507 inst
.instruction
|= SHIFT_BY_REG
;
9508 /* PR 12854: Error on extraneous shifts. */
9509 constraint (inst
.operands
[2].shifted
,
9510 _("extraneous shift as part of operand to shift insn"));
9513 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9519 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9520 inst
.reloc
.pc_rel
= 0;
9526 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9527 inst
.reloc
.pc_rel
= 0;
9533 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9534 inst
.reloc
.pc_rel
= 0;
9540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9541 _("selected processor does not support SETPAN instruction"));
9543 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9549 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9550 _("selected processor does not support SETPAN instruction"));
9552 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9555 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9556 SMLAxy{cond} Rd,Rm,Rs,Rn
9557 SMLAWy{cond} Rd,Rm,Rs,Rn
9558 Error if any register is R15. */
9563 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9564 inst
.instruction
|= inst
.operands
[1].reg
;
9565 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9566 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9569 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9570 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9571 Error if any register is R15.
9572 Warning if Rdlo == Rdhi. */
9577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9578 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9579 inst
.instruction
|= inst
.operands
[2].reg
;
9580 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9582 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9583 as_tsktsk (_("rdhi and rdlo must be different"));
9586 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9587 SMULxy{cond} Rd,Rm,Rs
9588 Error if any register is R15. */
9593 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9594 inst
.instruction
|= inst
.operands
[1].reg
;
9595 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9598 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9599 the same for both ARM and Thumb-2. */
9606 if (inst
.operands
[0].present
)
9608 reg
= inst
.operands
[0].reg
;
9609 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9614 inst
.instruction
|= reg
<< 16;
9615 inst
.instruction
|= inst
.operands
[1].imm
;
9616 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9617 inst
.instruction
|= WRITE_BACK
;
9620 /* ARM V6 strex (argument parse). */
9625 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9626 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9627 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9628 || inst
.operands
[2].negative
9629 /* See comment in do_ldrex(). */
9630 || (inst
.operands
[2].reg
== REG_PC
),
9633 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9634 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9636 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9637 || inst
.reloc
.exp
.X_add_number
!= 0,
9638 _("offset must be zero in ARM encoding"));
9640 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9641 inst
.instruction
|= inst
.operands
[1].reg
;
9642 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9643 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9649 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9650 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9651 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9652 || inst
.operands
[2].negative
,
9655 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9656 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9664 constraint (inst
.operands
[1].reg
% 2 != 0,
9665 _("even register required"));
9666 constraint (inst
.operands
[2].present
9667 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9668 _("can only store two consecutive registers"));
9669 /* If op 2 were present and equal to PC, this function wouldn't
9670 have been called in the first place. */
9671 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9673 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9674 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9675 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9679 inst
.instruction
|= inst
.operands
[1].reg
;
9680 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9687 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9688 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9696 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9697 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9702 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9703 extends it to 32-bits, and adds the result to a value in another
9704 register. You can specify a rotation by 0, 8, 16, or 24 bits
9705 before extracting the 16-bit value.
9706 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9707 Condition defaults to COND_ALWAYS.
9708 Error if any register uses R15. */
9713 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9714 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9715 inst
.instruction
|= inst
.operands
[2].reg
;
9716 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9721 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9722 Condition defaults to COND_ALWAYS.
9723 Error if any register uses R15. */
9728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9729 inst
.instruction
|= inst
.operands
[1].reg
;
9730 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9733 /* VFP instructions. In a logical order: SP variant first, monad
9734 before dyad, arithmetic then move then load/store. */
9737 do_vfp_sp_monadic (void)
9739 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9740 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9744 do_vfp_sp_dyadic (void)
9746 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9747 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9748 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9752 do_vfp_sp_compare_z (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9758 do_vfp_dp_sp_cvt (void)
9760 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9761 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9765 do_vfp_sp_dp_cvt (void)
9767 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9768 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9772 do_vfp_reg_from_sp (void)
9774 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9775 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9779 do_vfp_reg2_from_sp2 (void)
9781 constraint (inst
.operands
[2].imm
!= 2,
9782 _("only two consecutive VFP SP registers allowed here"));
9783 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9784 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9785 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9789 do_vfp_sp_from_reg (void)
9791 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9792 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9796 do_vfp_sp2_from_reg2 (void)
9798 constraint (inst
.operands
[0].imm
!= 2,
9799 _("only two consecutive VFP SP registers allowed here"));
9800 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9801 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9802 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9806 do_vfp_sp_ldst (void)
9808 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9809 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9813 do_vfp_dp_ldst (void)
9815 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9816 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9821 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9823 if (inst
.operands
[0].writeback
)
9824 inst
.instruction
|= WRITE_BACK
;
9826 constraint (ldstm_type
!= VFP_LDSTMIA
,
9827 _("this addressing mode requires base-register writeback"));
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9829 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9830 inst
.instruction
|= inst
.operands
[1].imm
;
9834 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9838 if (inst
.operands
[0].writeback
)
9839 inst
.instruction
|= WRITE_BACK
;
9841 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9842 _("this addressing mode requires base-register writeback"));
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9845 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9847 count
= inst
.operands
[1].imm
<< 1;
9848 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9851 inst
.instruction
|= count
;
9855 do_vfp_sp_ldstmia (void)
9857 vfp_sp_ldstm (VFP_LDSTMIA
);
9861 do_vfp_sp_ldstmdb (void)
9863 vfp_sp_ldstm (VFP_LDSTMDB
);
9867 do_vfp_dp_ldstmia (void)
9869 vfp_dp_ldstm (VFP_LDSTMIA
);
9873 do_vfp_dp_ldstmdb (void)
9875 vfp_dp_ldstm (VFP_LDSTMDB
);
9879 do_vfp_xp_ldstmia (void)
9881 vfp_dp_ldstm (VFP_LDSTMIAX
);
9885 do_vfp_xp_ldstmdb (void)
9887 vfp_dp_ldstm (VFP_LDSTMDBX
);
9891 do_vfp_dp_rd_rm (void)
9893 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9894 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9898 do_vfp_dp_rn_rd (void)
9900 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9901 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9905 do_vfp_dp_rd_rn (void)
9907 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9908 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9912 do_vfp_dp_rd_rn_rm (void)
9914 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9915 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9916 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9922 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9926 do_vfp_dp_rm_rd_rn (void)
9928 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9929 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9930 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9933 /* VFPv3 instructions. */
9935 do_vfp_sp_const (void)
9937 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9938 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9939 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9943 do_vfp_dp_const (void)
9945 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9946 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9947 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9951 vfp_conv (int srcsize
)
9953 int immbits
= srcsize
- inst
.operands
[1].imm
;
9955 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9957 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9958 i.e. immbits must be in range 0 - 16. */
9959 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9962 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9964 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9965 i.e. immbits must be in range 0 - 31. */
9966 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9970 inst
.instruction
|= (immbits
& 1) << 5;
9971 inst
.instruction
|= (immbits
>> 1);
9975 do_vfp_sp_conv_16 (void)
9977 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9982 do_vfp_dp_conv_16 (void)
9984 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9989 do_vfp_sp_conv_32 (void)
9991 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9996 do_vfp_dp_conv_32 (void)
9998 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10002 /* FPA instructions. Also in a logical order. */
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10008 inst
.instruction
|= inst
.operands
[1].reg
;
10012 do_fpa_ldmstm (void)
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10015 switch (inst
.operands
[1].imm
)
10017 case 1: inst
.instruction
|= CP_T_X
; break;
10018 case 2: inst
.instruction
|= CP_T_Y
; break;
10019 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10024 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10026 /* The instruction specified "ea" or "fd", so we can only accept
10027 [Rn]{!}. The instruction does not really support stacking or
10028 unstacking, so we have to emulate these by setting appropriate
10029 bits and offsets. */
10030 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10031 || inst
.reloc
.exp
.X_add_number
!= 0,
10032 _("this instruction does not support indexing"));
10034 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10035 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10037 if (!(inst
.instruction
& INDEX_UP
))
10038 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10040 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10042 inst
.operands
[2].preind
= 0;
10043 inst
.operands
[2].postind
= 1;
10047 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10050 /* iWMMXt instructions: strictly in alphabetical order. */
10053 do_iwmmxt_tandorc (void)
10055 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10059 do_iwmmxt_textrc (void)
10061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10062 inst
.instruction
|= inst
.operands
[1].imm
;
10066 do_iwmmxt_textrm (void)
10068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10069 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10070 inst
.instruction
|= inst
.operands
[2].imm
;
10074 do_iwmmxt_tinsr (void)
10076 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10077 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10078 inst
.instruction
|= inst
.operands
[2].imm
;
10082 do_iwmmxt_tmia (void)
10084 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10085 inst
.instruction
|= inst
.operands
[1].reg
;
10086 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10090 do_iwmmxt_waligni (void)
10092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10093 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10094 inst
.instruction
|= inst
.operands
[2].reg
;
10095 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10099 do_iwmmxt_wmerge (void)
10101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10102 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10103 inst
.instruction
|= inst
.operands
[2].reg
;
10104 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10108 do_iwmmxt_wmov (void)
10110 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10112 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10113 inst
.instruction
|= inst
.operands
[1].reg
;
10117 do_iwmmxt_wldstbh (void)
10120 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10122 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10124 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10125 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10129 do_iwmmxt_wldstw (void)
10131 /* RIWR_RIWC clears .isreg for a control register. */
10132 if (!inst
.operands
[0].isreg
)
10134 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10135 inst
.instruction
|= 0xf0000000;
10138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10139 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10143 do_iwmmxt_wldstd (void)
10145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10146 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10147 && inst
.operands
[1].immisreg
)
10149 inst
.instruction
&= ~0x1a000ff;
10150 inst
.instruction
|= (0xfU
<< 28);
10151 if (inst
.operands
[1].preind
)
10152 inst
.instruction
|= PRE_INDEX
;
10153 if (!inst
.operands
[1].negative
)
10154 inst
.instruction
|= INDEX_UP
;
10155 if (inst
.operands
[1].writeback
)
10156 inst
.instruction
|= WRITE_BACK
;
10157 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10158 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10159 inst
.instruction
|= inst
.operands
[1].imm
;
10162 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10166 do_iwmmxt_wshufh (void)
10168 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10169 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10170 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10171 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10175 do_iwmmxt_wzero (void)
10177 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10178 inst
.instruction
|= inst
.operands
[0].reg
;
10179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10180 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10184 do_iwmmxt_wrwrwr_or_imm5 (void)
10186 if (inst
.operands
[2].isreg
)
10189 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10190 _("immediate operand requires iWMMXt2"));
10192 if (inst
.operands
[2].imm
== 0)
10194 switch ((inst
.instruction
>> 20) & 0xf)
10200 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10201 inst
.operands
[2].imm
= 16;
10202 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10208 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10209 inst
.operands
[2].imm
= 32;
10210 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10217 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10219 wrn
= (inst
.instruction
>> 16) & 0xf;
10220 inst
.instruction
&= 0xff0fff0f;
10221 inst
.instruction
|= wrn
;
10222 /* Bail out here; the instruction is now assembled. */
10227 /* Map 32 -> 0, etc. */
10228 inst
.operands
[2].imm
&= 0x1f;
10229 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10233 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10234 operations first, then control, shift, and load/store. */
10236 /* Insns like "foo X,Y,Z". */
10239 do_mav_triple (void)
10241 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10242 inst
.instruction
|= inst
.operands
[1].reg
;
10243 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10246 /* Insns like "foo W,X,Y,Z".
10247 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10252 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10253 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10254 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10255 inst
.instruction
|= inst
.operands
[3].reg
;
10258 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10260 do_mav_dspsc (void)
10262 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10265 /* Maverick shift immediate instructions.
10266 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10267 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10270 do_mav_shift (void)
10272 int imm
= inst
.operands
[2].imm
;
10274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10275 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10277 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10278 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10279 Bit 4 should be 0. */
10280 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10282 inst
.instruction
|= imm
;
10285 /* XScale instructions. Also sorted arithmetic before move. */
10287 /* Xscale multiply-accumulate (argument parse)
10290 MIAxycc acc0,Rm,Rs. */
10295 inst
.instruction
|= inst
.operands
[1].reg
;
10296 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10299 /* Xscale move-accumulator-register (argument parse)
10301 MARcc acc0,RdLo,RdHi. */
10306 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10307 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10310 /* Xscale move-register-accumulator (argument parse)
10312 MRAcc RdLo,RdHi,acc0. */
10317 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10319 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10322 /* Encoding functions relevant only to Thumb. */
10324 /* inst.operands[i] is a shifted-register operand; encode
10325 it into inst.instruction in the format used by Thumb32. */
10328 encode_thumb32_shifted_operand (int i
)
10330 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10331 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10333 constraint (inst
.operands
[i
].immisreg
,
10334 _("shift by register not allowed in thumb mode"));
10335 inst
.instruction
|= inst
.operands
[i
].reg
;
10336 if (shift
== SHIFT_RRX
)
10337 inst
.instruction
|= SHIFT_ROR
<< 4;
10340 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10341 _("expression too complex"));
10343 constraint (value
> 32
10344 || (value
== 32 && (shift
== SHIFT_LSL
10345 || shift
== SHIFT_ROR
)),
10346 _("shift expression is too large"));
10350 else if (value
== 32)
10353 inst
.instruction
|= shift
<< 4;
10354 inst
.instruction
|= (value
& 0x1c) << 10;
10355 inst
.instruction
|= (value
& 0x03) << 6;
10360 /* inst.operands[i] was set up by parse_address. Encode it into a
10361 Thumb32 format load or store instruction. Reject forms that cannot
10362 be used with such instructions. If is_t is true, reject forms that
10363 cannot be used with a T instruction; if is_d is true, reject forms
10364 that cannot be used with a D instruction. If it is a store insn,
10365 reject PC in Rn. */
10368 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10370 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10372 constraint (!inst
.operands
[i
].isreg
,
10373 _("Instruction does not support =N addresses"));
10375 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10376 if (inst
.operands
[i
].immisreg
)
10378 constraint (is_pc
, BAD_PC_ADDRESSING
);
10379 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10380 constraint (inst
.operands
[i
].negative
,
10381 _("Thumb does not support negative register indexing"));
10382 constraint (inst
.operands
[i
].postind
,
10383 _("Thumb does not support register post-indexing"));
10384 constraint (inst
.operands
[i
].writeback
,
10385 _("Thumb does not support register indexing with writeback"));
10386 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10387 _("Thumb supports only LSL in shifted register indexing"));
10389 inst
.instruction
|= inst
.operands
[i
].imm
;
10390 if (inst
.operands
[i
].shifted
)
10392 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10393 _("expression too complex"));
10394 constraint (inst
.reloc
.exp
.X_add_number
< 0
10395 || inst
.reloc
.exp
.X_add_number
> 3,
10396 _("shift out of range"));
10397 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10399 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10401 else if (inst
.operands
[i
].preind
)
10403 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10404 constraint (is_t
&& inst
.operands
[i
].writeback
,
10405 _("cannot use writeback with this instruction"));
10406 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10407 BAD_PC_ADDRESSING
);
10411 inst
.instruction
|= 0x01000000;
10412 if (inst
.operands
[i
].writeback
)
10413 inst
.instruction
|= 0x00200000;
10417 inst
.instruction
|= 0x00000c00;
10418 if (inst
.operands
[i
].writeback
)
10419 inst
.instruction
|= 0x00000100;
10421 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10423 else if (inst
.operands
[i
].postind
)
10425 gas_assert (inst
.operands
[i
].writeback
);
10426 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10427 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10430 inst
.instruction
|= 0x00200000;
10432 inst
.instruction
|= 0x00000900;
10433 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10435 else /* unindexed - only for coprocessor */
10436 inst
.error
= _("instruction does not accept unindexed addressing");
10439 /* Table of Thumb instructions which exist in both 16- and 32-bit
10440 encodings (the latter only in post-V6T2 cores). The index is the
10441 value used in the insns table below. When there is more than one
10442 possible 16-bit encoding for the instruction, this table always
10444 Also contains several pseudo-instructions used during relaxation. */
10445 #define T16_32_TAB \
10446 X(_adc, 4140, eb400000), \
10447 X(_adcs, 4140, eb500000), \
10448 X(_add, 1c00, eb000000), \
10449 X(_adds, 1c00, eb100000), \
10450 X(_addi, 0000, f1000000), \
10451 X(_addis, 0000, f1100000), \
10452 X(_add_pc,000f, f20f0000), \
10453 X(_add_sp,000d, f10d0000), \
10454 X(_adr, 000f, f20f0000), \
10455 X(_and, 4000, ea000000), \
10456 X(_ands, 4000, ea100000), \
10457 X(_asr, 1000, fa40f000), \
10458 X(_asrs, 1000, fa50f000), \
10459 X(_b, e000, f000b000), \
10460 X(_bcond, d000, f0008000), \
10461 X(_bic, 4380, ea200000), \
10462 X(_bics, 4380, ea300000), \
10463 X(_cmn, 42c0, eb100f00), \
10464 X(_cmp, 2800, ebb00f00), \
10465 X(_cpsie, b660, f3af8400), \
10466 X(_cpsid, b670, f3af8600), \
10467 X(_cpy, 4600, ea4f0000), \
10468 X(_dec_sp,80dd, f1ad0d00), \
10469 X(_eor, 4040, ea800000), \
10470 X(_eors, 4040, ea900000), \
10471 X(_inc_sp,00dd, f10d0d00), \
10472 X(_ldmia, c800, e8900000), \
10473 X(_ldr, 6800, f8500000), \
10474 X(_ldrb, 7800, f8100000), \
10475 X(_ldrh, 8800, f8300000), \
10476 X(_ldrsb, 5600, f9100000), \
10477 X(_ldrsh, 5e00, f9300000), \
10478 X(_ldr_pc,4800, f85f0000), \
10479 X(_ldr_pc2,4800, f85f0000), \
10480 X(_ldr_sp,9800, f85d0000), \
10481 X(_lsl, 0000, fa00f000), \
10482 X(_lsls, 0000, fa10f000), \
10483 X(_lsr, 0800, fa20f000), \
10484 X(_lsrs, 0800, fa30f000), \
10485 X(_mov, 2000, ea4f0000), \
10486 X(_movs, 2000, ea5f0000), \
10487 X(_mul, 4340, fb00f000), \
10488 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10489 X(_mvn, 43c0, ea6f0000), \
10490 X(_mvns, 43c0, ea7f0000), \
10491 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10492 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10493 X(_orr, 4300, ea400000), \
10494 X(_orrs, 4300, ea500000), \
10495 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10496 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10497 X(_rev, ba00, fa90f080), \
10498 X(_rev16, ba40, fa90f090), \
10499 X(_revsh, bac0, fa90f0b0), \
10500 X(_ror, 41c0, fa60f000), \
10501 X(_rors, 41c0, fa70f000), \
10502 X(_sbc, 4180, eb600000), \
10503 X(_sbcs, 4180, eb700000), \
10504 X(_stmia, c000, e8800000), \
10505 X(_str, 6000, f8400000), \
10506 X(_strb, 7000, f8000000), \
10507 X(_strh, 8000, f8200000), \
10508 X(_str_sp,9000, f84d0000), \
10509 X(_sub, 1e00, eba00000), \
10510 X(_subs, 1e00, ebb00000), \
10511 X(_subi, 8000, f1a00000), \
10512 X(_subis, 8000, f1b00000), \
10513 X(_sxtb, b240, fa4ff080), \
10514 X(_sxth, b200, fa0ff080), \
10515 X(_tst, 4200, ea100f00), \
10516 X(_uxtb, b2c0, fa5ff080), \
10517 X(_uxth, b280, fa1ff080), \
10518 X(_nop, bf00, f3af8000), \
10519 X(_yield, bf10, f3af8001), \
10520 X(_wfe, bf20, f3af8002), \
10521 X(_wfi, bf30, f3af8003), \
10522 X(_sev, bf40, f3af8004), \
10523 X(_sevl, bf50, f3af8005), \
10524 X(_udf, de00, f7f0a000)
10526 /* To catch errors in encoding functions, the codes are all offset by
10527 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10528 as 16-bit instructions. */
10529 #define X(a,b,c) T_MNEM##a
10530 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10533 #define X(a,b,c) 0x##b
10534 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10535 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10538 #define X(a,b,c) 0x##c
10539 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10540 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10541 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10545 /* Thumb instruction encoders, in alphabetical order. */
10547 /* ADDW or SUBW. */
10550 do_t_add_sub_w (void)
10554 Rd
= inst
.operands
[0].reg
;
10555 Rn
= inst
.operands
[1].reg
;
10557 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10558 is the SP-{plus,minus}-immediate form of the instruction. */
10560 constraint (Rd
== REG_PC
, BAD_PC
);
10562 reject_bad_reg (Rd
);
10564 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10565 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10568 /* Parse an add or subtract instruction. We get here with inst.instruction
10569 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10572 do_t_add_sub (void)
10576 Rd
= inst
.operands
[0].reg
;
10577 Rs
= (inst
.operands
[1].present
10578 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10579 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10582 set_it_insn_type_last ();
10584 if (unified_syntax
)
10587 bfd_boolean narrow
;
10590 flags
= (inst
.instruction
== T_MNEM_adds
10591 || inst
.instruction
== T_MNEM_subs
);
10593 narrow
= !in_it_block ();
10595 narrow
= in_it_block ();
10596 if (!inst
.operands
[2].isreg
)
10600 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10601 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10603 add
= (inst
.instruction
== T_MNEM_add
10604 || inst
.instruction
== T_MNEM_adds
);
10606 if (inst
.size_req
!= 4)
10608 /* Attempt to use a narrow opcode, with relaxation if
10610 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10611 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10612 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10613 opcode
= T_MNEM_add_sp
;
10614 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10615 opcode
= T_MNEM_add_pc
;
10616 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10619 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10621 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10625 inst
.instruction
= THUMB_OP16(opcode
);
10626 inst
.instruction
|= (Rd
<< 4) | Rs
;
10627 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10628 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10630 if (inst
.size_req
== 2)
10631 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10633 inst
.relax
= opcode
;
10637 constraint (inst
.size_req
== 2, BAD_HIREG
);
10639 if (inst
.size_req
== 4
10640 || (inst
.size_req
!= 2 && !opcode
))
10642 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10643 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10644 THUMB1_RELOC_ONLY
);
10647 constraint (add
, BAD_PC
);
10648 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10649 _("only SUBS PC, LR, #const allowed"));
10650 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10651 _("expression too complex"));
10652 constraint (inst
.reloc
.exp
.X_add_number
< 0
10653 || inst
.reloc
.exp
.X_add_number
> 0xff,
10654 _("immediate value out of range"));
10655 inst
.instruction
= T2_SUBS_PC_LR
10656 | inst
.reloc
.exp
.X_add_number
;
10657 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10660 else if (Rs
== REG_PC
)
10662 /* Always use addw/subw. */
10663 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10664 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10669 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10672 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10674 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10676 inst
.instruction
|= Rd
<< 8;
10677 inst
.instruction
|= Rs
<< 16;
10682 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10683 unsigned int shift
= inst
.operands
[2].shift_kind
;
10685 Rn
= inst
.operands
[2].reg
;
10686 /* See if we can do this with a 16-bit instruction. */
10687 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10689 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10694 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10695 || inst
.instruction
== T_MNEM_add
)
10697 : T_OPCODE_SUB_R3
);
10698 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10702 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10704 /* Thumb-1 cores (except v6-M) require at least one high
10705 register in a narrow non flag setting add. */
10706 if (Rd
> 7 || Rn
> 7
10707 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10708 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10715 inst
.instruction
= T_OPCODE_ADD_HI
;
10716 inst
.instruction
|= (Rd
& 8) << 4;
10717 inst
.instruction
|= (Rd
& 7);
10718 inst
.instruction
|= Rn
<< 3;
10724 constraint (Rd
== REG_PC
, BAD_PC
);
10725 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10726 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10727 constraint (Rs
== REG_PC
, BAD_PC
);
10728 reject_bad_reg (Rn
);
10730 /* If we get here, it can't be done in 16 bits. */
10731 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10732 _("shift must be constant"));
10733 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10734 inst
.instruction
|= Rd
<< 8;
10735 inst
.instruction
|= Rs
<< 16;
10736 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10737 _("shift value over 3 not allowed in thumb mode"));
10738 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10739 _("only LSL shift allowed in thumb mode"));
10740 encode_thumb32_shifted_operand (2);
10745 constraint (inst
.instruction
== T_MNEM_adds
10746 || inst
.instruction
== T_MNEM_subs
,
10749 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10751 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10752 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10755 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10756 ? 0x0000 : 0x8000);
10757 inst
.instruction
|= (Rd
<< 4) | Rs
;
10758 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10762 Rn
= inst
.operands
[2].reg
;
10763 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10765 /* We now have Rd, Rs, and Rn set to registers. */
10766 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10768 /* Can't do this for SUB. */
10769 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10770 inst
.instruction
= T_OPCODE_ADD_HI
;
10771 inst
.instruction
|= (Rd
& 8) << 4;
10772 inst
.instruction
|= (Rd
& 7);
10774 inst
.instruction
|= Rn
<< 3;
10776 inst
.instruction
|= Rs
<< 3;
10778 constraint (1, _("dest must overlap one source register"));
10782 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10783 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10784 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10794 Rd
= inst
.operands
[0].reg
;
10795 reject_bad_reg (Rd
);
10797 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10799 /* Defer to section relaxation. */
10800 inst
.relax
= inst
.instruction
;
10801 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10802 inst
.instruction
|= Rd
<< 4;
10804 else if (unified_syntax
&& inst
.size_req
!= 2)
10806 /* Generate a 32-bit opcode. */
10807 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10808 inst
.instruction
|= Rd
<< 8;
10809 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10810 inst
.reloc
.pc_rel
= 1;
10814 /* Generate a 16-bit opcode. */
10815 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10816 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10817 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10818 inst
.reloc
.pc_rel
= 1;
10819 inst
.instruction
|= Rd
<< 4;
10822 if (inst
.reloc
.exp
.X_op
== O_symbol
10823 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10824 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10825 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10826 inst
.reloc
.exp
.X_add_number
+= 1;
10829 /* Arithmetic instructions for which there is just one 16-bit
10830 instruction encoding, and it allows only two low registers.
10831 For maximal compatibility with ARM syntax, we allow three register
10832 operands even when Thumb-32 instructions are not available, as long
10833 as the first two are identical. For instance, both "sbc r0,r1" and
10834 "sbc r0,r0,r1" are allowed. */
10840 Rd
= inst
.operands
[0].reg
;
10841 Rs
= (inst
.operands
[1].present
10842 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10843 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10844 Rn
= inst
.operands
[2].reg
;
10846 reject_bad_reg (Rd
);
10847 reject_bad_reg (Rs
);
10848 if (inst
.operands
[2].isreg
)
10849 reject_bad_reg (Rn
);
10851 if (unified_syntax
)
10853 if (!inst
.operands
[2].isreg
)
10855 /* For an immediate, we always generate a 32-bit opcode;
10856 section relaxation will shrink it later if possible. */
10857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10858 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10859 inst
.instruction
|= Rd
<< 8;
10860 inst
.instruction
|= Rs
<< 16;
10861 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10865 bfd_boolean narrow
;
10867 /* See if we can do this with a 16-bit instruction. */
10868 if (THUMB_SETS_FLAGS (inst
.instruction
))
10869 narrow
= !in_it_block ();
10871 narrow
= in_it_block ();
10873 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10875 if (inst
.operands
[2].shifted
)
10877 if (inst
.size_req
== 4)
10883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10884 inst
.instruction
|= Rd
;
10885 inst
.instruction
|= Rn
<< 3;
10889 /* If we get here, it can't be done in 16 bits. */
10890 constraint (inst
.operands
[2].shifted
10891 && inst
.operands
[2].immisreg
,
10892 _("shift must be constant"));
10893 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10894 inst
.instruction
|= Rd
<< 8;
10895 inst
.instruction
|= Rs
<< 16;
10896 encode_thumb32_shifted_operand (2);
10901 /* On its face this is a lie - the instruction does set the
10902 flags. However, the only supported mnemonic in this mode
10903 says it doesn't. */
10904 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10906 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10907 _("unshifted register required"));
10908 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10909 constraint (Rd
!= Rs
,
10910 _("dest and source1 must be the same register"));
10912 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10913 inst
.instruction
|= Rd
;
10914 inst
.instruction
|= Rn
<< 3;
10918 /* Similarly, but for instructions where the arithmetic operation is
10919 commutative, so we can allow either of them to be different from
10920 the destination operand in a 16-bit instruction. For instance, all
10921 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10928 Rd
= inst
.operands
[0].reg
;
10929 Rs
= (inst
.operands
[1].present
10930 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10931 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10932 Rn
= inst
.operands
[2].reg
;
10934 reject_bad_reg (Rd
);
10935 reject_bad_reg (Rs
);
10936 if (inst
.operands
[2].isreg
)
10937 reject_bad_reg (Rn
);
10939 if (unified_syntax
)
10941 if (!inst
.operands
[2].isreg
)
10943 /* For an immediate, we always generate a 32-bit opcode;
10944 section relaxation will shrink it later if possible. */
10945 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10946 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10947 inst
.instruction
|= Rd
<< 8;
10948 inst
.instruction
|= Rs
<< 16;
10949 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10953 bfd_boolean narrow
;
10955 /* See if we can do this with a 16-bit instruction. */
10956 if (THUMB_SETS_FLAGS (inst
.instruction
))
10957 narrow
= !in_it_block ();
10959 narrow
= in_it_block ();
10961 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10963 if (inst
.operands
[2].shifted
)
10965 if (inst
.size_req
== 4)
10972 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10973 inst
.instruction
|= Rd
;
10974 inst
.instruction
|= Rn
<< 3;
10979 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10980 inst
.instruction
|= Rd
;
10981 inst
.instruction
|= Rs
<< 3;
10986 /* If we get here, it can't be done in 16 bits. */
10987 constraint (inst
.operands
[2].shifted
10988 && inst
.operands
[2].immisreg
,
10989 _("shift must be constant"));
10990 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10991 inst
.instruction
|= Rd
<< 8;
10992 inst
.instruction
|= Rs
<< 16;
10993 encode_thumb32_shifted_operand (2);
10998 /* On its face this is a lie - the instruction does set the
10999 flags. However, the only supported mnemonic in this mode
11000 says it doesn't. */
11001 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11003 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11004 _("unshifted register required"));
11005 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11007 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11008 inst
.instruction
|= Rd
;
11011 inst
.instruction
|= Rn
<< 3;
11013 inst
.instruction
|= Rs
<< 3;
11015 constraint (1, _("dest must overlap one source register"));
11023 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11024 constraint (msb
> 32, _("bit-field extends past end of register"));
11025 /* The instruction encoding stores the LSB and MSB,
11026 not the LSB and width. */
11027 Rd
= inst
.operands
[0].reg
;
11028 reject_bad_reg (Rd
);
11029 inst
.instruction
|= Rd
<< 8;
11030 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11031 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11032 inst
.instruction
|= msb
- 1;
11041 Rd
= inst
.operands
[0].reg
;
11042 reject_bad_reg (Rd
);
11044 /* #0 in second position is alternative syntax for bfc, which is
11045 the same instruction but with REG_PC in the Rm field. */
11046 if (!inst
.operands
[1].isreg
)
11050 Rn
= inst
.operands
[1].reg
;
11051 reject_bad_reg (Rn
);
11054 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11055 constraint (msb
> 32, _("bit-field extends past end of register"));
11056 /* The instruction encoding stores the LSB and MSB,
11057 not the LSB and width. */
11058 inst
.instruction
|= Rd
<< 8;
11059 inst
.instruction
|= Rn
<< 16;
11060 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11061 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11062 inst
.instruction
|= msb
- 1;
11070 Rd
= inst
.operands
[0].reg
;
11071 Rn
= inst
.operands
[1].reg
;
11073 reject_bad_reg (Rd
);
11074 reject_bad_reg (Rn
);
11076 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11077 _("bit-field extends past end of register"));
11078 inst
.instruction
|= Rd
<< 8;
11079 inst
.instruction
|= Rn
<< 16;
11080 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11081 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11082 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11085 /* ARM V5 Thumb BLX (argument parse)
11086 BLX <target_addr> which is BLX(1)
11087 BLX <Rm> which is BLX(2)
11088 Unfortunately, there are two different opcodes for this mnemonic.
11089 So, the insns[].value is not used, and the code here zaps values
11090 into inst.instruction.
11092 ??? How to take advantage of the additional two bits of displacement
11093 available in Thumb32 mode? Need new relocation? */
11098 set_it_insn_type_last ();
11100 if (inst
.operands
[0].isreg
)
11102 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11103 /* We have a register, so this is BLX(2). */
11104 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11108 /* No register. This must be BLX(1). */
11109 inst
.instruction
= 0xf000e800;
11110 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11119 bfd_reloc_code_real_type reloc
;
11122 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11124 if (in_it_block ())
11126 /* Conditional branches inside IT blocks are encoded as unconditional
11128 cond
= COND_ALWAYS
;
11133 if (cond
!= COND_ALWAYS
)
11134 opcode
= T_MNEM_bcond
;
11136 opcode
= inst
.instruction
;
11139 && (inst
.size_req
== 4
11140 || (inst
.size_req
!= 2
11141 && (inst
.operands
[0].hasreloc
11142 || inst
.reloc
.exp
.X_op
== O_constant
))))
11144 inst
.instruction
= THUMB_OP32(opcode
);
11145 if (cond
== COND_ALWAYS
)
11146 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11150 _("selected architecture does not support "
11151 "wide conditional branch instruction"));
11153 gas_assert (cond
!= 0xF);
11154 inst
.instruction
|= cond
<< 22;
11155 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11160 inst
.instruction
= THUMB_OP16(opcode
);
11161 if (cond
== COND_ALWAYS
)
11162 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11165 inst
.instruction
|= cond
<< 8;
11166 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11168 /* Allow section relaxation. */
11169 if (unified_syntax
&& inst
.size_req
!= 2)
11170 inst
.relax
= opcode
;
11172 inst
.reloc
.type
= reloc
;
11173 inst
.reloc
.pc_rel
= 1;
11176 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11177 between the two is the maximum immediate allowed - which is passed in
11180 do_t_bkpt_hlt1 (int range
)
11182 constraint (inst
.cond
!= COND_ALWAYS
,
11183 _("instruction is always unconditional"));
11184 if (inst
.operands
[0].present
)
11186 constraint (inst
.operands
[0].imm
> range
,
11187 _("immediate value out of range"));
11188 inst
.instruction
|= inst
.operands
[0].imm
;
11191 set_it_insn_type (NEUTRAL_IT_INSN
);
11197 do_t_bkpt_hlt1 (63);
11203 do_t_bkpt_hlt1 (255);
11207 do_t_branch23 (void)
11209 set_it_insn_type_last ();
11210 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11212 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11213 this file. We used to simply ignore the PLT reloc type here --
11214 the branch encoding is now needed to deal with TLSCALL relocs.
11215 So if we see a PLT reloc now, put it back to how it used to be to
11216 keep the preexisting behaviour. */
11217 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11218 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11220 #if defined(OBJ_COFF)
11221 /* If the destination of the branch is a defined symbol which does not have
11222 the THUMB_FUNC attribute, then we must be calling a function which has
11223 the (interfacearm) attribute. We look for the Thumb entry point to that
11224 function and change the branch to refer to that function instead. */
11225 if ( inst
.reloc
.exp
.X_op
== O_symbol
11226 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11227 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11228 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11229 inst
.reloc
.exp
.X_add_symbol
=
11230 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11237 set_it_insn_type_last ();
11238 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11239 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11240 should cause the alignment to be checked once it is known. This is
11241 because BX PC only works if the instruction is word aligned. */
11249 set_it_insn_type_last ();
11250 Rm
= inst
.operands
[0].reg
;
11251 reject_bad_reg (Rm
);
11252 inst
.instruction
|= Rm
<< 16;
11261 Rd
= inst
.operands
[0].reg
;
11262 Rm
= inst
.operands
[1].reg
;
11264 reject_bad_reg (Rd
);
11265 reject_bad_reg (Rm
);
11267 inst
.instruction
|= Rd
<< 8;
11268 inst
.instruction
|= Rm
<< 16;
11269 inst
.instruction
|= Rm
;
11275 set_it_insn_type (OUTSIDE_IT_INSN
);
11276 inst
.instruction
|= inst
.operands
[0].imm
;
11282 set_it_insn_type (OUTSIDE_IT_INSN
);
11284 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11285 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11287 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11288 inst
.instruction
= 0xf3af8000;
11289 inst
.instruction
|= imod
<< 9;
11290 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11291 if (inst
.operands
[1].present
)
11292 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11297 && (inst
.operands
[0].imm
& 4),
11298 _("selected processor does not support 'A' form "
11299 "of this instruction"));
11300 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11301 _("Thumb does not support the 2-argument "
11302 "form of this instruction"));
11303 inst
.instruction
|= inst
.operands
[0].imm
;
11307 /* THUMB CPY instruction (argument parse). */
11312 if (inst
.size_req
== 4)
11314 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11315 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11316 inst
.instruction
|= inst
.operands
[1].reg
;
11320 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11321 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11322 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11329 set_it_insn_type (OUTSIDE_IT_INSN
);
11330 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11331 inst
.instruction
|= inst
.operands
[0].reg
;
11332 inst
.reloc
.pc_rel
= 1;
11333 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11339 inst
.instruction
|= inst
.operands
[0].imm
;
11345 unsigned Rd
, Rn
, Rm
;
11347 Rd
= inst
.operands
[0].reg
;
11348 Rn
= (inst
.operands
[1].present
11349 ? inst
.operands
[1].reg
: Rd
);
11350 Rm
= inst
.operands
[2].reg
;
11352 reject_bad_reg (Rd
);
11353 reject_bad_reg (Rn
);
11354 reject_bad_reg (Rm
);
11356 inst
.instruction
|= Rd
<< 8;
11357 inst
.instruction
|= Rn
<< 16;
11358 inst
.instruction
|= Rm
;
11364 if (unified_syntax
&& inst
.size_req
== 4)
11365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11367 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11373 unsigned int cond
= inst
.operands
[0].imm
;
11375 set_it_insn_type (IT_INSN
);
11376 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11378 now_it
.warn_deprecated
= FALSE
;
11380 /* If the condition is a negative condition, invert the mask. */
11381 if ((cond
& 0x1) == 0x0)
11383 unsigned int mask
= inst
.instruction
& 0x000f;
11385 if ((mask
& 0x7) == 0)
11387 /* No conversion needed. */
11388 now_it
.block_length
= 1;
11390 else if ((mask
& 0x3) == 0)
11393 now_it
.block_length
= 2;
11395 else if ((mask
& 0x1) == 0)
11398 now_it
.block_length
= 3;
11403 now_it
.block_length
= 4;
11406 inst
.instruction
&= 0xfff0;
11407 inst
.instruction
|= mask
;
11410 inst
.instruction
|= cond
<< 4;
11413 /* Helper function used for both push/pop and ldm/stm. */
11415 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11419 load
= (inst
.instruction
& (1 << 20)) != 0;
11421 if (mask
& (1 << 13))
11422 inst
.error
= _("SP not allowed in register list");
11424 if ((mask
& (1 << base
)) != 0
11426 inst
.error
= _("having the base register in the register list when "
11427 "using write back is UNPREDICTABLE");
11431 if (mask
& (1 << 15))
11433 if (mask
& (1 << 14))
11434 inst
.error
= _("LR and PC should not both be in register list");
11436 set_it_insn_type_last ();
11441 if (mask
& (1 << 15))
11442 inst
.error
= _("PC not allowed in register list");
11445 if ((mask
& (mask
- 1)) == 0)
11447 /* Single register transfers implemented as str/ldr. */
11450 if (inst
.instruction
& (1 << 23))
11451 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11453 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11457 if (inst
.instruction
& (1 << 23))
11458 inst
.instruction
= 0x00800000; /* ia -> [base] */
11460 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11463 inst
.instruction
|= 0xf8400000;
11465 inst
.instruction
|= 0x00100000;
11467 mask
= ffs (mask
) - 1;
11470 else if (writeback
)
11471 inst
.instruction
|= WRITE_BACK
;
11473 inst
.instruction
|= mask
;
11474 inst
.instruction
|= base
<< 16;
11480 /* This really doesn't seem worth it. */
11481 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11482 _("expression too complex"));
11483 constraint (inst
.operands
[1].writeback
,
11484 _("Thumb load/store multiple does not support {reglist}^"));
11486 if (unified_syntax
)
11488 bfd_boolean narrow
;
11492 /* See if we can use a 16-bit instruction. */
11493 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11494 && inst
.size_req
!= 4
11495 && !(inst
.operands
[1].imm
& ~0xff))
11497 mask
= 1 << inst
.operands
[0].reg
;
11499 if (inst
.operands
[0].reg
<= 7)
11501 if (inst
.instruction
== T_MNEM_stmia
11502 ? inst
.operands
[0].writeback
11503 : (inst
.operands
[0].writeback
11504 == !(inst
.operands
[1].imm
& mask
)))
11506 if (inst
.instruction
== T_MNEM_stmia
11507 && (inst
.operands
[1].imm
& mask
)
11508 && (inst
.operands
[1].imm
& (mask
- 1)))
11509 as_warn (_("value stored for r%d is UNKNOWN"),
11510 inst
.operands
[0].reg
);
11512 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11513 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11514 inst
.instruction
|= inst
.operands
[1].imm
;
11517 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11519 /* This means 1 register in reg list one of 3 situations:
11520 1. Instruction is stmia, but without writeback.
11521 2. lmdia without writeback, but with Rn not in
11523 3. ldmia with writeback, but with Rn in reglist.
11524 Case 3 is UNPREDICTABLE behaviour, so we handle
11525 case 1 and 2 which can be converted into a 16-bit
11526 str or ldr. The SP cases are handled below. */
11527 unsigned long opcode
;
11528 /* First, record an error for Case 3. */
11529 if (inst
.operands
[1].imm
& mask
11530 && inst
.operands
[0].writeback
)
11532 _("having the base register in the register list when "
11533 "using write back is UNPREDICTABLE");
11535 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11537 inst
.instruction
= THUMB_OP16 (opcode
);
11538 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11539 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11543 else if (inst
.operands
[0] .reg
== REG_SP
)
11545 if (inst
.operands
[0].writeback
)
11548 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11549 ? T_MNEM_push
: T_MNEM_pop
);
11550 inst
.instruction
|= inst
.operands
[1].imm
;
11553 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11556 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11557 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11558 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11566 if (inst
.instruction
< 0xffff)
11567 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11569 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11570 inst
.operands
[0].writeback
);
11575 constraint (inst
.operands
[0].reg
> 7
11576 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11577 constraint (inst
.instruction
!= T_MNEM_ldmia
11578 && inst
.instruction
!= T_MNEM_stmia
,
11579 _("Thumb-2 instruction only valid in unified syntax"));
11580 if (inst
.instruction
== T_MNEM_stmia
)
11582 if (!inst
.operands
[0].writeback
)
11583 as_warn (_("this instruction will write back the base register"));
11584 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11585 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11586 as_warn (_("value stored for r%d is UNKNOWN"),
11587 inst
.operands
[0].reg
);
11591 if (!inst
.operands
[0].writeback
11592 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11593 as_warn (_("this instruction will write back the base register"));
11594 else if (inst
.operands
[0].writeback
11595 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11596 as_warn (_("this instruction will not write back the base register"));
11599 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11600 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11601 inst
.instruction
|= inst
.operands
[1].imm
;
11608 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11609 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11610 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11611 || inst
.operands
[1].negative
,
11614 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11616 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11617 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11618 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11624 if (!inst
.operands
[1].present
)
11626 constraint (inst
.operands
[0].reg
== REG_LR
,
11627 _("r14 not allowed as first register "
11628 "when second register is omitted"));
11629 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11631 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11634 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11635 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11636 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11642 unsigned long opcode
;
11645 if (inst
.operands
[0].isreg
11646 && !inst
.operands
[0].preind
11647 && inst
.operands
[0].reg
== REG_PC
)
11648 set_it_insn_type_last ();
11650 opcode
= inst
.instruction
;
11651 if (unified_syntax
)
11653 if (!inst
.operands
[1].isreg
)
11655 if (opcode
<= 0xffff)
11656 inst
.instruction
= THUMB_OP32 (opcode
);
11657 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11660 if (inst
.operands
[1].isreg
11661 && !inst
.operands
[1].writeback
11662 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11663 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11664 && opcode
<= 0xffff
11665 && inst
.size_req
!= 4)
11667 /* Insn may have a 16-bit form. */
11668 Rn
= inst
.operands
[1].reg
;
11669 if (inst
.operands
[1].immisreg
)
11671 inst
.instruction
= THUMB_OP16 (opcode
);
11673 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11675 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11676 reject_bad_reg (inst
.operands
[1].imm
);
11678 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11679 && opcode
!= T_MNEM_ldrsb
)
11680 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11681 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11688 if (inst
.reloc
.pc_rel
)
11689 opcode
= T_MNEM_ldr_pc2
;
11691 opcode
= T_MNEM_ldr_pc
;
11695 if (opcode
== T_MNEM_ldr
)
11696 opcode
= T_MNEM_ldr_sp
;
11698 opcode
= T_MNEM_str_sp
;
11700 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11704 inst
.instruction
= inst
.operands
[0].reg
;
11705 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11707 inst
.instruction
|= THUMB_OP16 (opcode
);
11708 if (inst
.size_req
== 2)
11709 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11711 inst
.relax
= opcode
;
11715 /* Definitely a 32-bit variant. */
11717 /* Warning for Erratum 752419. */
11718 if (opcode
== T_MNEM_ldr
11719 && inst
.operands
[0].reg
== REG_SP
11720 && inst
.operands
[1].writeback
== 1
11721 && !inst
.operands
[1].immisreg
)
11723 if (no_cpu_selected ()
11724 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11725 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11726 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11727 as_warn (_("This instruction may be unpredictable "
11728 "if executed on M-profile cores "
11729 "with interrupts enabled."));
11732 /* Do some validations regarding addressing modes. */
11733 if (inst
.operands
[1].immisreg
)
11734 reject_bad_reg (inst
.operands
[1].imm
);
11736 constraint (inst
.operands
[1].writeback
== 1
11737 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11740 inst
.instruction
= THUMB_OP32 (opcode
);
11741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11742 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11743 check_ldr_r15_aligned ();
11747 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11749 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11751 /* Only [Rn,Rm] is acceptable. */
11752 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11753 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11754 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11755 || inst
.operands
[1].negative
,
11756 _("Thumb does not support this addressing mode"));
11757 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11762 if (!inst
.operands
[1].isreg
)
11763 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11766 constraint (!inst
.operands
[1].preind
11767 || inst
.operands
[1].shifted
11768 || inst
.operands
[1].writeback
,
11769 _("Thumb does not support this addressing mode"));
11770 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11772 constraint (inst
.instruction
& 0x0600,
11773 _("byte or halfword not valid for base register"));
11774 constraint (inst
.operands
[1].reg
== REG_PC
11775 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11776 _("r15 based store not allowed"));
11777 constraint (inst
.operands
[1].immisreg
,
11778 _("invalid base register for register offset"));
11780 if (inst
.operands
[1].reg
== REG_PC
)
11781 inst
.instruction
= T_OPCODE_LDR_PC
;
11782 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11783 inst
.instruction
= T_OPCODE_LDR_SP
;
11785 inst
.instruction
= T_OPCODE_STR_SP
;
11787 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11788 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11792 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11793 if (!inst
.operands
[1].immisreg
)
11795 /* Immediate offset. */
11796 inst
.instruction
|= inst
.operands
[0].reg
;
11797 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11798 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11802 /* Register offset. */
11803 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11804 constraint (inst
.operands
[1].negative
,
11805 _("Thumb does not support this addressing mode"));
11808 switch (inst
.instruction
)
11810 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11811 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11812 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11813 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11814 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11815 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11816 case 0x5600 /* ldrsb */:
11817 case 0x5e00 /* ldrsh */: break;
11821 inst
.instruction
|= inst
.operands
[0].reg
;
11822 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11823 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11829 if (!inst
.operands
[1].present
)
11831 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11832 constraint (inst
.operands
[0].reg
== REG_LR
,
11833 _("r14 not allowed here"));
11834 constraint (inst
.operands
[0].reg
== REG_R12
,
11835 _("r12 not allowed here"));
11838 if (inst
.operands
[2].writeback
11839 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11840 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11841 as_warn (_("base register written back, and overlaps "
11842 "one of transfer registers"));
11844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11845 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11846 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11853 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11859 unsigned Rd
, Rn
, Rm
, Ra
;
11861 Rd
= inst
.operands
[0].reg
;
11862 Rn
= inst
.operands
[1].reg
;
11863 Rm
= inst
.operands
[2].reg
;
11864 Ra
= inst
.operands
[3].reg
;
11866 reject_bad_reg (Rd
);
11867 reject_bad_reg (Rn
);
11868 reject_bad_reg (Rm
);
11869 reject_bad_reg (Ra
);
11871 inst
.instruction
|= Rd
<< 8;
11872 inst
.instruction
|= Rn
<< 16;
11873 inst
.instruction
|= Rm
;
11874 inst
.instruction
|= Ra
<< 12;
11880 unsigned RdLo
, RdHi
, Rn
, Rm
;
11882 RdLo
= inst
.operands
[0].reg
;
11883 RdHi
= inst
.operands
[1].reg
;
11884 Rn
= inst
.operands
[2].reg
;
11885 Rm
= inst
.operands
[3].reg
;
11887 reject_bad_reg (RdLo
);
11888 reject_bad_reg (RdHi
);
11889 reject_bad_reg (Rn
);
11890 reject_bad_reg (Rm
);
11892 inst
.instruction
|= RdLo
<< 12;
11893 inst
.instruction
|= RdHi
<< 8;
11894 inst
.instruction
|= Rn
<< 16;
11895 inst
.instruction
|= Rm
;
11899 do_t_mov_cmp (void)
11903 Rn
= inst
.operands
[0].reg
;
11904 Rm
= inst
.operands
[1].reg
;
11907 set_it_insn_type_last ();
11909 if (unified_syntax
)
11911 int r0off
= (inst
.instruction
== T_MNEM_mov
11912 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11913 unsigned long opcode
;
11914 bfd_boolean narrow
;
11915 bfd_boolean low_regs
;
11917 low_regs
= (Rn
<= 7 && Rm
<= 7);
11918 opcode
= inst
.instruction
;
11919 if (in_it_block ())
11920 narrow
= opcode
!= T_MNEM_movs
;
11922 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11923 if (inst
.size_req
== 4
11924 || inst
.operands
[1].shifted
)
11927 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11928 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11929 && !inst
.operands
[1].shifted
11933 inst
.instruction
= T2_SUBS_PC_LR
;
11937 if (opcode
== T_MNEM_cmp
)
11939 constraint (Rn
== REG_PC
, BAD_PC
);
11942 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11944 warn_deprecated_sp (Rm
);
11945 /* R15 was documented as a valid choice for Rm in ARMv6,
11946 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11947 tools reject R15, so we do too. */
11948 constraint (Rm
== REG_PC
, BAD_PC
);
11951 reject_bad_reg (Rm
);
11953 else if (opcode
== T_MNEM_mov
11954 || opcode
== T_MNEM_movs
)
11956 if (inst
.operands
[1].isreg
)
11958 if (opcode
== T_MNEM_movs
)
11960 reject_bad_reg (Rn
);
11961 reject_bad_reg (Rm
);
11965 /* This is mov.n. */
11966 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11967 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11969 as_tsktsk (_("Use of r%u as a source register is "
11970 "deprecated when r%u is the destination "
11971 "register."), Rm
, Rn
);
11976 /* This is mov.w. */
11977 constraint (Rn
== REG_PC
, BAD_PC
);
11978 constraint (Rm
== REG_PC
, BAD_PC
);
11979 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11980 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11984 reject_bad_reg (Rn
);
11987 if (!inst
.operands
[1].isreg
)
11989 /* Immediate operand. */
11990 if (!in_it_block () && opcode
== T_MNEM_mov
)
11992 if (low_regs
&& narrow
)
11994 inst
.instruction
= THUMB_OP16 (opcode
);
11995 inst
.instruction
|= Rn
<< 8;
11996 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11997 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11999 if (inst
.size_req
== 2)
12000 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12002 inst
.relax
= opcode
;
12007 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12008 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12009 THUMB1_RELOC_ONLY
);
12011 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12012 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12013 inst
.instruction
|= Rn
<< r0off
;
12014 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12017 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12018 && (inst
.instruction
== T_MNEM_mov
12019 || inst
.instruction
== T_MNEM_movs
))
12021 /* Register shifts are encoded as separate shift instructions. */
12022 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12024 if (in_it_block ())
12029 if (inst
.size_req
== 4)
12032 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12038 switch (inst
.operands
[1].shift_kind
)
12041 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12044 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12047 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12050 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12056 inst
.instruction
= opcode
;
12059 inst
.instruction
|= Rn
;
12060 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12065 inst
.instruction
|= CONDS_BIT
;
12067 inst
.instruction
|= Rn
<< 8;
12068 inst
.instruction
|= Rm
<< 16;
12069 inst
.instruction
|= inst
.operands
[1].imm
;
12074 /* Some mov with immediate shift have narrow variants.
12075 Register shifts are handled above. */
12076 if (low_regs
&& inst
.operands
[1].shifted
12077 && (inst
.instruction
== T_MNEM_mov
12078 || inst
.instruction
== T_MNEM_movs
))
12080 if (in_it_block ())
12081 narrow
= (inst
.instruction
== T_MNEM_mov
);
12083 narrow
= (inst
.instruction
== T_MNEM_movs
);
12088 switch (inst
.operands
[1].shift_kind
)
12090 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12091 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12092 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12093 default: narrow
= FALSE
; break;
12099 inst
.instruction
|= Rn
;
12100 inst
.instruction
|= Rm
<< 3;
12101 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12105 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12106 inst
.instruction
|= Rn
<< r0off
;
12107 encode_thumb32_shifted_operand (1);
12111 switch (inst
.instruction
)
12114 /* In v4t or v5t a move of two lowregs produces unpredictable
12115 results. Don't allow this. */
12118 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12119 "MOV Rd, Rs with two low registers is not "
12120 "permitted on this architecture");
12121 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12125 inst
.instruction
= T_OPCODE_MOV_HR
;
12126 inst
.instruction
|= (Rn
& 0x8) << 4;
12127 inst
.instruction
|= (Rn
& 0x7);
12128 inst
.instruction
|= Rm
<< 3;
12132 /* We know we have low registers at this point.
12133 Generate LSLS Rd, Rs, #0. */
12134 inst
.instruction
= T_OPCODE_LSL_I
;
12135 inst
.instruction
|= Rn
;
12136 inst
.instruction
|= Rm
<< 3;
12142 inst
.instruction
= T_OPCODE_CMP_LR
;
12143 inst
.instruction
|= Rn
;
12144 inst
.instruction
|= Rm
<< 3;
12148 inst
.instruction
= T_OPCODE_CMP_HR
;
12149 inst
.instruction
|= (Rn
& 0x8) << 4;
12150 inst
.instruction
|= (Rn
& 0x7);
12151 inst
.instruction
|= Rm
<< 3;
12158 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12160 /* PR 10443: Do not silently ignore shifted operands. */
12161 constraint (inst
.operands
[1].shifted
,
12162 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12164 if (inst
.operands
[1].isreg
)
12166 if (Rn
< 8 && Rm
< 8)
12168 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12169 since a MOV instruction produces unpredictable results. */
12170 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12171 inst
.instruction
= T_OPCODE_ADD_I3
;
12173 inst
.instruction
= T_OPCODE_CMP_LR
;
12175 inst
.instruction
|= Rn
;
12176 inst
.instruction
|= Rm
<< 3;
12180 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12181 inst
.instruction
= T_OPCODE_MOV_HR
;
12183 inst
.instruction
= T_OPCODE_CMP_HR
;
12189 constraint (Rn
> 7,
12190 _("only lo regs allowed with immediate"));
12191 inst
.instruction
|= Rn
<< 8;
12192 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12203 top
= (inst
.instruction
& 0x00800000) != 0;
12204 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12206 constraint (top
, _(":lower16: not allowed in this instruction"));
12207 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12209 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12211 constraint (!top
, _(":upper16: not allowed in this instruction"));
12212 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12215 Rd
= inst
.operands
[0].reg
;
12216 reject_bad_reg (Rd
);
12218 inst
.instruction
|= Rd
<< 8;
12219 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12221 imm
= inst
.reloc
.exp
.X_add_number
;
12222 inst
.instruction
|= (imm
& 0xf000) << 4;
12223 inst
.instruction
|= (imm
& 0x0800) << 15;
12224 inst
.instruction
|= (imm
& 0x0700) << 4;
12225 inst
.instruction
|= (imm
& 0x00ff);
12230 do_t_mvn_tst (void)
12234 Rn
= inst
.operands
[0].reg
;
12235 Rm
= inst
.operands
[1].reg
;
12237 if (inst
.instruction
== T_MNEM_cmp
12238 || inst
.instruction
== T_MNEM_cmn
)
12239 constraint (Rn
== REG_PC
, BAD_PC
);
12241 reject_bad_reg (Rn
);
12242 reject_bad_reg (Rm
);
12244 if (unified_syntax
)
12246 int r0off
= (inst
.instruction
== T_MNEM_mvn
12247 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12248 bfd_boolean narrow
;
12250 if (inst
.size_req
== 4
12251 || inst
.instruction
> 0xffff
12252 || inst
.operands
[1].shifted
12253 || Rn
> 7 || Rm
> 7)
12255 else if (inst
.instruction
== T_MNEM_cmn
12256 || inst
.instruction
== T_MNEM_tst
)
12258 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12259 narrow
= !in_it_block ();
12261 narrow
= in_it_block ();
12263 if (!inst
.operands
[1].isreg
)
12265 /* For an immediate, we always generate a 32-bit opcode;
12266 section relaxation will shrink it later if possible. */
12267 if (inst
.instruction
< 0xffff)
12268 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12269 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12270 inst
.instruction
|= Rn
<< r0off
;
12271 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12275 /* See if we can do this with a 16-bit instruction. */
12278 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12279 inst
.instruction
|= Rn
;
12280 inst
.instruction
|= Rm
<< 3;
12284 constraint (inst
.operands
[1].shifted
12285 && inst
.operands
[1].immisreg
,
12286 _("shift must be constant"));
12287 if (inst
.instruction
< 0xffff)
12288 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12289 inst
.instruction
|= Rn
<< r0off
;
12290 encode_thumb32_shifted_operand (1);
12296 constraint (inst
.instruction
> 0xffff
12297 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12298 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12299 _("unshifted register required"));
12300 constraint (Rn
> 7 || Rm
> 7,
12303 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12304 inst
.instruction
|= Rn
;
12305 inst
.instruction
|= Rm
<< 3;
12314 if (do_vfp_nsyn_mrs () == SUCCESS
)
12317 Rd
= inst
.operands
[0].reg
;
12318 reject_bad_reg (Rd
);
12319 inst
.instruction
|= Rd
<< 8;
12321 if (inst
.operands
[1].isreg
)
12323 unsigned br
= inst
.operands
[1].reg
;
12324 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12325 as_bad (_("bad register for mrs"));
12327 inst
.instruction
|= br
& (0xf << 16);
12328 inst
.instruction
|= (br
& 0x300) >> 4;
12329 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12333 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12335 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12337 /* PR gas/12698: The constraint is only applied for m_profile.
12338 If the user has specified -march=all, we want to ignore it as
12339 we are building for any CPU type, including non-m variants. */
12340 bfd_boolean m_profile
=
12341 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12342 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12343 "not support requested special purpose register"));
12346 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12348 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12349 _("'APSR', 'CPSR' or 'SPSR' expected"));
12351 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12352 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12353 inst
.instruction
|= 0xf0000;
12363 if (do_vfp_nsyn_msr () == SUCCESS
)
12366 constraint (!inst
.operands
[1].isreg
,
12367 _("Thumb encoding does not support an immediate here"));
12369 if (inst
.operands
[0].isreg
)
12370 flags
= (int)(inst
.operands
[0].reg
);
12372 flags
= inst
.operands
[0].imm
;
12374 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12376 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12378 /* PR gas/12698: The constraint is only applied for m_profile.
12379 If the user has specified -march=all, we want to ignore it as
12380 we are building for any CPU type, including non-m variants. */
12381 bfd_boolean m_profile
=
12382 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12383 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12384 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12385 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12386 && bits
!= PSR_f
)) && m_profile
,
12387 _("selected processor does not support requested special "
12388 "purpose register"));
12391 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12392 "requested special purpose register"));
12394 Rn
= inst
.operands
[1].reg
;
12395 reject_bad_reg (Rn
);
12397 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12398 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12399 inst
.instruction
|= (flags
& 0x300) >> 4;
12400 inst
.instruction
|= (flags
& 0xff);
12401 inst
.instruction
|= Rn
<< 16;
12407 bfd_boolean narrow
;
12408 unsigned Rd
, Rn
, Rm
;
12410 if (!inst
.operands
[2].present
)
12411 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12413 Rd
= inst
.operands
[0].reg
;
12414 Rn
= inst
.operands
[1].reg
;
12415 Rm
= inst
.operands
[2].reg
;
12417 if (unified_syntax
)
12419 if (inst
.size_req
== 4
12425 else if (inst
.instruction
== T_MNEM_muls
)
12426 narrow
= !in_it_block ();
12428 narrow
= in_it_block ();
12432 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12433 constraint (Rn
> 7 || Rm
> 7,
12440 /* 16-bit MULS/Conditional MUL. */
12441 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12442 inst
.instruction
|= Rd
;
12445 inst
.instruction
|= Rm
<< 3;
12447 inst
.instruction
|= Rn
<< 3;
12449 constraint (1, _("dest must overlap one source register"));
12453 constraint (inst
.instruction
!= T_MNEM_mul
,
12454 _("Thumb-2 MUL must not set flags"));
12456 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12457 inst
.instruction
|= Rd
<< 8;
12458 inst
.instruction
|= Rn
<< 16;
12459 inst
.instruction
|= Rm
<< 0;
12461 reject_bad_reg (Rd
);
12462 reject_bad_reg (Rn
);
12463 reject_bad_reg (Rm
);
12470 unsigned RdLo
, RdHi
, Rn
, Rm
;
12472 RdLo
= inst
.operands
[0].reg
;
12473 RdHi
= inst
.operands
[1].reg
;
12474 Rn
= inst
.operands
[2].reg
;
12475 Rm
= inst
.operands
[3].reg
;
12477 reject_bad_reg (RdLo
);
12478 reject_bad_reg (RdHi
);
12479 reject_bad_reg (Rn
);
12480 reject_bad_reg (Rm
);
12482 inst
.instruction
|= RdLo
<< 12;
12483 inst
.instruction
|= RdHi
<< 8;
12484 inst
.instruction
|= Rn
<< 16;
12485 inst
.instruction
|= Rm
;
12488 as_tsktsk (_("rdhi and rdlo must be different"));
12494 set_it_insn_type (NEUTRAL_IT_INSN
);
12496 if (unified_syntax
)
12498 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12500 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12501 inst
.instruction
|= inst
.operands
[0].imm
;
12505 /* PR9722: Check for Thumb2 availability before
12506 generating a thumb2 nop instruction. */
12507 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12509 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12510 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12513 inst
.instruction
= 0x46c0;
12518 constraint (inst
.operands
[0].present
,
12519 _("Thumb does not support NOP with hints"));
12520 inst
.instruction
= 0x46c0;
12527 if (unified_syntax
)
12529 bfd_boolean narrow
;
12531 if (THUMB_SETS_FLAGS (inst
.instruction
))
12532 narrow
= !in_it_block ();
12534 narrow
= in_it_block ();
12535 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12537 if (inst
.size_req
== 4)
12542 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12543 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12544 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12548 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12549 inst
.instruction
|= inst
.operands
[0].reg
;
12550 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12555 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12557 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12559 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12560 inst
.instruction
|= inst
.operands
[0].reg
;
12561 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12570 Rd
= inst
.operands
[0].reg
;
12571 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12573 reject_bad_reg (Rd
);
12574 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12575 reject_bad_reg (Rn
);
12577 inst
.instruction
|= Rd
<< 8;
12578 inst
.instruction
|= Rn
<< 16;
12580 if (!inst
.operands
[2].isreg
)
12582 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12583 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12589 Rm
= inst
.operands
[2].reg
;
12590 reject_bad_reg (Rm
);
12592 constraint (inst
.operands
[2].shifted
12593 && inst
.operands
[2].immisreg
,
12594 _("shift must be constant"));
12595 encode_thumb32_shifted_operand (2);
12602 unsigned Rd
, Rn
, Rm
;
12604 Rd
= inst
.operands
[0].reg
;
12605 Rn
= inst
.operands
[1].reg
;
12606 Rm
= inst
.operands
[2].reg
;
12608 reject_bad_reg (Rd
);
12609 reject_bad_reg (Rn
);
12610 reject_bad_reg (Rm
);
12612 inst
.instruction
|= Rd
<< 8;
12613 inst
.instruction
|= Rn
<< 16;
12614 inst
.instruction
|= Rm
;
12615 if (inst
.operands
[3].present
)
12617 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12618 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12619 _("expression too complex"));
12620 inst
.instruction
|= (val
& 0x1c) << 10;
12621 inst
.instruction
|= (val
& 0x03) << 6;
12628 if (!inst
.operands
[3].present
)
12632 inst
.instruction
&= ~0x00000020;
12634 /* PR 10168. Swap the Rm and Rn registers. */
12635 Rtmp
= inst
.operands
[1].reg
;
12636 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12637 inst
.operands
[2].reg
= Rtmp
;
12645 if (inst
.operands
[0].immisreg
)
12646 reject_bad_reg (inst
.operands
[0].imm
);
12648 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12652 do_t_push_pop (void)
12656 constraint (inst
.operands
[0].writeback
,
12657 _("push/pop do not support {reglist}^"));
12658 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12659 _("expression too complex"));
12661 mask
= inst
.operands
[0].imm
;
12662 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12663 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12664 else if (inst
.size_req
!= 4
12665 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12666 ? REG_LR
: REG_PC
)))
12668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12669 inst
.instruction
|= THUMB_PP_PC_LR
;
12670 inst
.instruction
|= mask
& 0xff;
12672 else if (unified_syntax
)
12674 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12675 encode_thumb2_ldmstm (13, mask
, TRUE
);
12679 inst
.error
= _("invalid register list to push/pop instruction");
12689 Rd
= inst
.operands
[0].reg
;
12690 Rm
= inst
.operands
[1].reg
;
12692 reject_bad_reg (Rd
);
12693 reject_bad_reg (Rm
);
12695 inst
.instruction
|= Rd
<< 8;
12696 inst
.instruction
|= Rm
<< 16;
12697 inst
.instruction
|= Rm
;
12705 Rd
= inst
.operands
[0].reg
;
12706 Rm
= inst
.operands
[1].reg
;
12708 reject_bad_reg (Rd
);
12709 reject_bad_reg (Rm
);
12711 if (Rd
<= 7 && Rm
<= 7
12712 && inst
.size_req
!= 4)
12714 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12715 inst
.instruction
|= Rd
;
12716 inst
.instruction
|= Rm
<< 3;
12718 else if (unified_syntax
)
12720 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12721 inst
.instruction
|= Rd
<< 8;
12722 inst
.instruction
|= Rm
<< 16;
12723 inst
.instruction
|= Rm
;
12726 inst
.error
= BAD_HIREG
;
12734 Rd
= inst
.operands
[0].reg
;
12735 Rm
= inst
.operands
[1].reg
;
12737 reject_bad_reg (Rd
);
12738 reject_bad_reg (Rm
);
12740 inst
.instruction
|= Rd
<< 8;
12741 inst
.instruction
|= Rm
;
12749 Rd
= inst
.operands
[0].reg
;
12750 Rs
= (inst
.operands
[1].present
12751 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12752 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12754 reject_bad_reg (Rd
);
12755 reject_bad_reg (Rs
);
12756 if (inst
.operands
[2].isreg
)
12757 reject_bad_reg (inst
.operands
[2].reg
);
12759 inst
.instruction
|= Rd
<< 8;
12760 inst
.instruction
|= Rs
<< 16;
12761 if (!inst
.operands
[2].isreg
)
12763 bfd_boolean narrow
;
12765 if ((inst
.instruction
& 0x00100000) != 0)
12766 narrow
= !in_it_block ();
12768 narrow
= in_it_block ();
12770 if (Rd
> 7 || Rs
> 7)
12773 if (inst
.size_req
== 4 || !unified_syntax
)
12776 if (inst
.reloc
.exp
.X_op
!= O_constant
12777 || inst
.reloc
.exp
.X_add_number
!= 0)
12780 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12781 relaxation, but it doesn't seem worth the hassle. */
12784 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12785 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12786 inst
.instruction
|= Rs
<< 3;
12787 inst
.instruction
|= Rd
;
12791 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12792 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12796 encode_thumb32_shifted_operand (2);
12802 if (warn_on_deprecated
12803 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12804 as_tsktsk (_("setend use is deprecated for ARMv8"));
12806 set_it_insn_type (OUTSIDE_IT_INSN
);
12807 if (inst
.operands
[0].imm
)
12808 inst
.instruction
|= 0x8;
12814 if (!inst
.operands
[1].present
)
12815 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12817 if (unified_syntax
)
12819 bfd_boolean narrow
;
12822 switch (inst
.instruction
)
12825 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12827 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12829 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12831 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12835 if (THUMB_SETS_FLAGS (inst
.instruction
))
12836 narrow
= !in_it_block ();
12838 narrow
= in_it_block ();
12839 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12841 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12843 if (inst
.operands
[2].isreg
12844 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12845 || inst
.operands
[2].reg
> 7))
12847 if (inst
.size_req
== 4)
12850 reject_bad_reg (inst
.operands
[0].reg
);
12851 reject_bad_reg (inst
.operands
[1].reg
);
12855 if (inst
.operands
[2].isreg
)
12857 reject_bad_reg (inst
.operands
[2].reg
);
12858 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12859 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12860 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12861 inst
.instruction
|= inst
.operands
[2].reg
;
12863 /* PR 12854: Error on extraneous shifts. */
12864 constraint (inst
.operands
[2].shifted
,
12865 _("extraneous shift as part of operand to shift insn"));
12869 inst
.operands
[1].shifted
= 1;
12870 inst
.operands
[1].shift_kind
= shift_kind
;
12871 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12872 ? T_MNEM_movs
: T_MNEM_mov
);
12873 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12874 encode_thumb32_shifted_operand (1);
12875 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12876 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12881 if (inst
.operands
[2].isreg
)
12883 switch (shift_kind
)
12885 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12886 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12887 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12888 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12892 inst
.instruction
|= inst
.operands
[0].reg
;
12893 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12895 /* PR 12854: Error on extraneous shifts. */
12896 constraint (inst
.operands
[2].shifted
,
12897 _("extraneous shift as part of operand to shift insn"));
12901 switch (shift_kind
)
12903 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12904 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12905 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12908 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12909 inst
.instruction
|= inst
.operands
[0].reg
;
12910 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12916 constraint (inst
.operands
[0].reg
> 7
12917 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12918 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12920 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12922 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12923 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12924 _("source1 and dest must be same register"));
12926 switch (inst
.instruction
)
12928 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12929 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12930 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12931 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12935 inst
.instruction
|= inst
.operands
[0].reg
;
12936 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12938 /* PR 12854: Error on extraneous shifts. */
12939 constraint (inst
.operands
[2].shifted
,
12940 _("extraneous shift as part of operand to shift insn"));
12944 switch (inst
.instruction
)
12946 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12947 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12948 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12949 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12952 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12953 inst
.instruction
|= inst
.operands
[0].reg
;
12954 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12962 unsigned Rd
, Rn
, Rm
;
12964 Rd
= inst
.operands
[0].reg
;
12965 Rn
= inst
.operands
[1].reg
;
12966 Rm
= inst
.operands
[2].reg
;
12968 reject_bad_reg (Rd
);
12969 reject_bad_reg (Rn
);
12970 reject_bad_reg (Rm
);
12972 inst
.instruction
|= Rd
<< 8;
12973 inst
.instruction
|= Rn
<< 16;
12974 inst
.instruction
|= Rm
;
12980 unsigned Rd
, Rn
, Rm
;
12982 Rd
= inst
.operands
[0].reg
;
12983 Rm
= inst
.operands
[1].reg
;
12984 Rn
= inst
.operands
[2].reg
;
12986 reject_bad_reg (Rd
);
12987 reject_bad_reg (Rn
);
12988 reject_bad_reg (Rm
);
12990 inst
.instruction
|= Rd
<< 8;
12991 inst
.instruction
|= Rn
<< 16;
12992 inst
.instruction
|= Rm
;
12998 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12999 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13000 _("SMC is not permitted on this architecture"));
13001 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13002 _("expression too complex"));
13003 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13004 inst
.instruction
|= (value
& 0xf000) >> 12;
13005 inst
.instruction
|= (value
& 0x0ff0);
13006 inst
.instruction
|= (value
& 0x000f) << 16;
13007 /* PR gas/15623: SMC instructions must be last in an IT block. */
13008 set_it_insn_type_last ();
13014 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13016 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13017 inst
.instruction
|= (value
& 0x0fff);
13018 inst
.instruction
|= (value
& 0xf000) << 4;
13022 do_t_ssat_usat (int bias
)
13026 Rd
= inst
.operands
[0].reg
;
13027 Rn
= inst
.operands
[2].reg
;
13029 reject_bad_reg (Rd
);
13030 reject_bad_reg (Rn
);
13032 inst
.instruction
|= Rd
<< 8;
13033 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13034 inst
.instruction
|= Rn
<< 16;
13036 if (inst
.operands
[3].present
)
13038 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13040 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13042 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13043 _("expression too complex"));
13045 if (shift_amount
!= 0)
13047 constraint (shift_amount
> 31,
13048 _("shift expression is too large"));
13050 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13051 inst
.instruction
|= 0x00200000; /* sh bit. */
13053 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13054 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13062 do_t_ssat_usat (1);
13070 Rd
= inst
.operands
[0].reg
;
13071 Rn
= inst
.operands
[2].reg
;
13073 reject_bad_reg (Rd
);
13074 reject_bad_reg (Rn
);
13076 inst
.instruction
|= Rd
<< 8;
13077 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13078 inst
.instruction
|= Rn
<< 16;
13084 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13085 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13086 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13087 || inst
.operands
[2].negative
,
13090 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13092 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13093 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13094 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13095 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13101 if (!inst
.operands
[2].present
)
13102 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13104 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13105 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13106 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13109 inst
.instruction
|= inst
.operands
[0].reg
;
13110 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13111 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13112 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13118 unsigned Rd
, Rn
, Rm
;
13120 Rd
= inst
.operands
[0].reg
;
13121 Rn
= inst
.operands
[1].reg
;
13122 Rm
= inst
.operands
[2].reg
;
13124 reject_bad_reg (Rd
);
13125 reject_bad_reg (Rn
);
13126 reject_bad_reg (Rm
);
13128 inst
.instruction
|= Rd
<< 8;
13129 inst
.instruction
|= Rn
<< 16;
13130 inst
.instruction
|= Rm
;
13131 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13139 Rd
= inst
.operands
[0].reg
;
13140 Rm
= inst
.operands
[1].reg
;
13142 reject_bad_reg (Rd
);
13143 reject_bad_reg (Rm
);
13145 if (inst
.instruction
<= 0xffff
13146 && inst
.size_req
!= 4
13147 && Rd
<= 7 && Rm
<= 7
13148 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13150 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13151 inst
.instruction
|= Rd
;
13152 inst
.instruction
|= Rm
<< 3;
13154 else if (unified_syntax
)
13156 if (inst
.instruction
<= 0xffff)
13157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13158 inst
.instruction
|= Rd
<< 8;
13159 inst
.instruction
|= Rm
;
13160 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13164 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13165 _("Thumb encoding does not support rotation"));
13166 constraint (1, BAD_HIREG
);
13173 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13182 half
= (inst
.instruction
& 0x10) != 0;
13183 set_it_insn_type_last ();
13184 constraint (inst
.operands
[0].immisreg
,
13185 _("instruction requires register index"));
13187 Rn
= inst
.operands
[0].reg
;
13188 Rm
= inst
.operands
[0].imm
;
13190 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13191 constraint (Rn
== REG_SP
, BAD_SP
);
13192 reject_bad_reg (Rm
);
13194 constraint (!half
&& inst
.operands
[0].shifted
,
13195 _("instruction does not allow shifted index"));
13196 inst
.instruction
|= (Rn
<< 16) | Rm
;
13202 if (!inst
.operands
[0].present
)
13203 inst
.operands
[0].imm
= 0;
13205 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13207 constraint (inst
.size_req
== 2,
13208 _("immediate value out of range"));
13209 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13210 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13211 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13215 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13216 inst
.instruction
|= inst
.operands
[0].imm
;
13219 set_it_insn_type (NEUTRAL_IT_INSN
);
13226 do_t_ssat_usat (0);
13234 Rd
= inst
.operands
[0].reg
;
13235 Rn
= inst
.operands
[2].reg
;
13237 reject_bad_reg (Rd
);
13238 reject_bad_reg (Rn
);
13240 inst
.instruction
|= Rd
<< 8;
13241 inst
.instruction
|= inst
.operands
[1].imm
;
13242 inst
.instruction
|= Rn
<< 16;
13245 /* Neon instruction encoder helpers. */
13247 /* Encodings for the different types for various Neon opcodes. */
13249 /* An "invalid" code for the following tables. */
13252 struct neon_tab_entry
13255 unsigned float_or_poly
;
13256 unsigned scalar_or_imm
;
13259 /* Map overloaded Neon opcodes to their respective encodings. */
13260 #define NEON_ENC_TAB \
13261 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13262 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13263 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13264 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13265 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13266 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13267 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13268 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13269 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13270 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13271 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13272 /* Register variants of the following two instructions are encoded as
13273 vcge / vcgt with the operands reversed. */ \
13274 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13275 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13276 X(vfma, N_INV, 0x0000c10, N_INV), \
13277 X(vfms, N_INV, 0x0200c10, N_INV), \
13278 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13279 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13280 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13281 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13282 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13283 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13284 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13285 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13286 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13287 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13288 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13289 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13290 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13291 X(vshl, 0x0000400, N_INV, 0x0800510), \
13292 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13293 X(vand, 0x0000110, N_INV, 0x0800030), \
13294 X(vbic, 0x0100110, N_INV, 0x0800030), \
13295 X(veor, 0x1000110, N_INV, N_INV), \
13296 X(vorn, 0x0300110, N_INV, 0x0800010), \
13297 X(vorr, 0x0200110, N_INV, 0x0800010), \
13298 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13299 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13300 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13301 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13302 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13303 X(vst1, 0x0000000, 0x0800000, N_INV), \
13304 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13305 X(vst2, 0x0000100, 0x0800100, N_INV), \
13306 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13307 X(vst3, 0x0000200, 0x0800200, N_INV), \
13308 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13309 X(vst4, 0x0000300, 0x0800300, N_INV), \
13310 X(vmovn, 0x1b20200, N_INV, N_INV), \
13311 X(vtrn, 0x1b20080, N_INV, N_INV), \
13312 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13313 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13314 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13315 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13316 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13317 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13318 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13319 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13320 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13321 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13322 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13323 X(vseleq, 0xe000a00, N_INV, N_INV), \
13324 X(vselvs, 0xe100a00, N_INV, N_INV), \
13325 X(vselge, 0xe200a00, N_INV, N_INV), \
13326 X(vselgt, 0xe300a00, N_INV, N_INV), \
13327 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13328 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13329 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13330 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13331 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13332 X(aes, 0x3b00300, N_INV, N_INV), \
13333 X(sha3op, 0x2000c00, N_INV, N_INV), \
13334 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13335 X(sha2op, 0x3ba0380, N_INV, N_INV)
13339 #define X(OPC,I,F,S) N_MNEM_##OPC
13344 static const struct neon_tab_entry neon_enc_tab
[] =
13346 #define X(OPC,I,F,S) { (I), (F), (S) }
13351 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13352 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13353 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13354 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13355 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13356 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13357 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13358 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13359 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13360 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13361 #define NEON_ENC_SINGLE_(X) \
13362 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13363 #define NEON_ENC_DOUBLE_(X) \
13364 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13365 #define NEON_ENC_FPV8_(X) \
13366 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13368 #define NEON_ENCODE(type, inst) \
13371 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13372 inst.is_neon = 1; \
13376 #define check_neon_suffixes \
13379 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13381 as_bad (_("invalid neon suffix for non neon instruction")); \
13387 /* Define shapes for instruction operands. The following mnemonic characters
13388 are used in this table:
13390 F - VFP S<n> register
13391 D - Neon D<n> register
13392 Q - Neon Q<n> register
13396 L - D<n> register list
13398 This table is used to generate various data:
13399 - enumerations of the form NS_DDR to be used as arguments to
13401 - a table classifying shapes into single, double, quad, mixed.
13402 - a table used to drive neon_select_shape. */
13404 #define NEON_SHAPE_DEF \
13405 X(3, (D, D, D), DOUBLE), \
13406 X(3, (Q, Q, Q), QUAD), \
13407 X(3, (D, D, I), DOUBLE), \
13408 X(3, (Q, Q, I), QUAD), \
13409 X(3, (D, D, S), DOUBLE), \
13410 X(3, (Q, Q, S), QUAD), \
13411 X(2, (D, D), DOUBLE), \
13412 X(2, (Q, Q), QUAD), \
13413 X(2, (D, S), DOUBLE), \
13414 X(2, (Q, S), QUAD), \
13415 X(2, (D, R), DOUBLE), \
13416 X(2, (Q, R), QUAD), \
13417 X(2, (D, I), DOUBLE), \
13418 X(2, (Q, I), QUAD), \
13419 X(3, (D, L, D), DOUBLE), \
13420 X(2, (D, Q), MIXED), \
13421 X(2, (Q, D), MIXED), \
13422 X(3, (D, Q, I), MIXED), \
13423 X(3, (Q, D, I), MIXED), \
13424 X(3, (Q, D, D), MIXED), \
13425 X(3, (D, Q, Q), MIXED), \
13426 X(3, (Q, Q, D), MIXED), \
13427 X(3, (Q, D, S), MIXED), \
13428 X(3, (D, Q, S), MIXED), \
13429 X(4, (D, D, D, I), DOUBLE), \
13430 X(4, (Q, Q, Q, I), QUAD), \
13431 X(4, (D, D, S, I), DOUBLE), \
13432 X(4, (Q, Q, S, I), QUAD), \
13433 X(2, (F, F), SINGLE), \
13434 X(3, (F, F, F), SINGLE), \
13435 X(2, (F, I), SINGLE), \
13436 X(2, (F, D), MIXED), \
13437 X(2, (D, F), MIXED), \
13438 X(3, (F, F, I), MIXED), \
13439 X(4, (R, R, F, F), SINGLE), \
13440 X(4, (F, F, R, R), SINGLE), \
13441 X(3, (D, R, R), DOUBLE), \
13442 X(3, (R, R, D), DOUBLE), \
13443 X(2, (S, R), SINGLE), \
13444 X(2, (R, S), SINGLE), \
13445 X(2, (F, R), SINGLE), \
13446 X(2, (R, F), SINGLE), \
13447 /* Half float shape supported so far. */\
13448 X (2, (H, D), MIXED), \
13449 X (2, (D, H), MIXED), \
13450 X (2, (H, F), MIXED), \
13451 X (2, (F, H), MIXED), \
13452 X (2, (H, H), HALF), \
13453 X (2, (H, R), HALF), \
13454 X (2, (R, H), HALF), \
13455 X (2, (H, I), HALF), \
13456 X (3, (H, H, H), HALF), \
13457 X (3, (H, F, I), MIXED), \
13458 X (3, (F, H, I), MIXED), \
13459 X (3, (D, H, H), MIXED), \
13460 X (3, (D, H, S), MIXED)
13462 #define S2(A,B) NS_##A##B
13463 #define S3(A,B,C) NS_##A##B##C
13464 #define S4(A,B,C,D) NS_##A##B##C##D
13466 #define X(N, L, C) S##N L
13479 enum neon_shape_class
13488 #define X(N, L, C) SC_##C
13490 static enum neon_shape_class neon_shape_class
[] =
13509 /* Register widths of above. */
13510 static unsigned neon_shape_el_size
[] =
13522 struct neon_shape_info
13525 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13528 #define S2(A,B) { SE_##A, SE_##B }
13529 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13530 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13532 #define X(N, L, C) { N, S##N L }
13534 static struct neon_shape_info neon_shape_tab
[] =
13544 /* Bit masks used in type checking given instructions.
13545 'N_EQK' means the type must be the same as (or based on in some way) the key
13546 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13547 set, various other bits can be set as well in order to modify the meaning of
13548 the type constraint. */
13550 enum neon_type_mask
13574 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13575 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13576 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13577 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13578 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13579 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13580 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13581 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13582 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13583 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13584 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13586 N_MAX_NONSPECIAL
= N_P64
13589 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13591 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13592 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13593 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13594 #define N_S_32 (N_S8 | N_S16 | N_S32)
13595 #define N_F_16_32 (N_F16 | N_F32)
13596 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13597 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13598 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13599 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13601 /* Pass this as the first type argument to neon_check_type to ignore types
13603 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13605 /* Select a "shape" for the current instruction (describing register types or
13606 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13607 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13608 function of operand parsing, so this function doesn't need to be called.
13609 Shapes should be listed in order of decreasing length. */
13611 static enum neon_shape
13612 neon_select_shape (enum neon_shape shape
, ...)
13615 enum neon_shape first_shape
= shape
;
13617 /* Fix missing optional operands. FIXME: we don't know at this point how
13618 many arguments we should have, so this makes the assumption that we have
13619 > 1. This is true of all current Neon opcodes, I think, but may not be
13620 true in the future. */
13621 if (!inst
.operands
[1].present
)
13622 inst
.operands
[1] = inst
.operands
[0];
13624 va_start (ap
, shape
);
13626 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13631 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13633 if (!inst
.operands
[j
].present
)
13639 switch (neon_shape_tab
[shape
].el
[j
])
13641 /* If a .f16, .16, .u16, .s16 type specifier is given over
13642 a VFP single precision register operand, it's essentially
13643 means only half of the register is used.
13645 If the type specifier is given after the mnemonics, the
13646 information is stored in inst.vectype. If the type specifier
13647 is given after register operand, the information is stored
13648 in inst.operands[].vectype.
13650 When there is only one type specifier, and all the register
13651 operands are the same type of hardware register, the type
13652 specifier applies to all register operands.
13654 If no type specifier is given, the shape is inferred from
13655 operand information.
13658 vadd.f16 s0, s1, s2: NS_HHH
13659 vabs.f16 s0, s1: NS_HH
13660 vmov.f16 s0, r1: NS_HR
13661 vmov.f16 r0, s1: NS_RH
13662 vcvt.f16 r0, s1: NS_RH
13663 vcvt.f16.s32 s2, s2, #29: NS_HFI
13664 vcvt.f16.s32 s2, s2: NS_HF
13667 if (!(inst
.operands
[j
].isreg
13668 && inst
.operands
[j
].isvec
13669 && inst
.operands
[j
].issingle
13670 && !inst
.operands
[j
].isquad
13671 && ((inst
.vectype
.elems
== 1
13672 && inst
.vectype
.el
[0].size
== 16)
13673 || (inst
.vectype
.elems
> 1
13674 && inst
.vectype
.el
[j
].size
== 16)
13675 || (inst
.vectype
.elems
== 0
13676 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13677 && inst
.operands
[j
].vectype
.size
== 16))))
13682 if (!(inst
.operands
[j
].isreg
13683 && inst
.operands
[j
].isvec
13684 && inst
.operands
[j
].issingle
13685 && !inst
.operands
[j
].isquad
13686 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13687 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13688 || (inst
.vectype
.elems
== 0
13689 && (inst
.operands
[j
].vectype
.size
== 32
13690 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13695 if (!(inst
.operands
[j
].isreg
13696 && inst
.operands
[j
].isvec
13697 && !inst
.operands
[j
].isquad
13698 && !inst
.operands
[j
].issingle
))
13703 if (!(inst
.operands
[j
].isreg
13704 && !inst
.operands
[j
].isvec
))
13709 if (!(inst
.operands
[j
].isreg
13710 && inst
.operands
[j
].isvec
13711 && inst
.operands
[j
].isquad
13712 && !inst
.operands
[j
].issingle
))
13717 if (!(!inst
.operands
[j
].isreg
13718 && !inst
.operands
[j
].isscalar
))
13723 if (!(!inst
.operands
[j
].isreg
13724 && inst
.operands
[j
].isscalar
))
13734 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13735 /* We've matched all the entries in the shape table, and we don't
13736 have any left over operands which have not been matched. */
13742 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13743 first_error (_("invalid instruction shape"));
13748 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13749 means the Q bit should be set). */
13752 neon_quad (enum neon_shape shape
)
13754 return neon_shape_class
[shape
] == SC_QUAD
;
13758 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13761 /* Allow modification to be made to types which are constrained to be
13762 based on the key element, based on bits set alongside N_EQK. */
13763 if ((typebits
& N_EQK
) != 0)
13765 if ((typebits
& N_HLF
) != 0)
13767 else if ((typebits
& N_DBL
) != 0)
13769 if ((typebits
& N_SGN
) != 0)
13770 *g_type
= NT_signed
;
13771 else if ((typebits
& N_UNS
) != 0)
13772 *g_type
= NT_unsigned
;
13773 else if ((typebits
& N_INT
) != 0)
13774 *g_type
= NT_integer
;
13775 else if ((typebits
& N_FLT
) != 0)
13776 *g_type
= NT_float
;
13777 else if ((typebits
& N_SIZ
) != 0)
13778 *g_type
= NT_untyped
;
13782 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13783 operand type, i.e. the single type specified in a Neon instruction when it
13784 is the only one given. */
13786 static struct neon_type_el
13787 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13789 struct neon_type_el dest
= *key
;
13791 gas_assert ((thisarg
& N_EQK
) != 0);
13793 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13798 /* Convert Neon type and size into compact bitmask representation. */
13800 static enum neon_type_mask
13801 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13808 case 8: return N_8
;
13809 case 16: return N_16
;
13810 case 32: return N_32
;
13811 case 64: return N_64
;
13819 case 8: return N_I8
;
13820 case 16: return N_I16
;
13821 case 32: return N_I32
;
13822 case 64: return N_I64
;
13830 case 16: return N_F16
;
13831 case 32: return N_F32
;
13832 case 64: return N_F64
;
13840 case 8: return N_P8
;
13841 case 16: return N_P16
;
13842 case 64: return N_P64
;
13850 case 8: return N_S8
;
13851 case 16: return N_S16
;
13852 case 32: return N_S32
;
13853 case 64: return N_S64
;
13861 case 8: return N_U8
;
13862 case 16: return N_U16
;
13863 case 32: return N_U32
;
13864 case 64: return N_U64
;
13875 /* Convert compact Neon bitmask type representation to a type and size. Only
13876 handles the case where a single bit is set in the mask. */
13879 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13880 enum neon_type_mask mask
)
13882 if ((mask
& N_EQK
) != 0)
13885 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13887 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13889 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13891 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13896 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13898 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13899 *type
= NT_unsigned
;
13900 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13901 *type
= NT_integer
;
13902 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13903 *type
= NT_untyped
;
13904 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13906 else if ((mask
& (N_F_ALL
)) != 0)
13914 /* Modify a bitmask of allowed types. This is only needed for type
13918 modify_types_allowed (unsigned allowed
, unsigned mods
)
13921 enum neon_el_type type
;
13927 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13929 if (el_type_of_type_chk (&type
, &size
,
13930 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13932 neon_modify_type_size (mods
, &type
, &size
);
13933 destmask
|= type_chk_of_el_type (type
, size
);
13940 /* Check type and return type classification.
13941 The manual states (paraphrase): If one datatype is given, it indicates the
13943 - the second operand, if there is one
13944 - the operand, if there is no second operand
13945 - the result, if there are no operands.
13946 This isn't quite good enough though, so we use a concept of a "key" datatype
13947 which is set on a per-instruction basis, which is the one which matters when
13948 only one data type is written.
13949 Note: this function has side-effects (e.g. filling in missing operands). All
13950 Neon instructions should call it before performing bit encoding. */
13952 static struct neon_type_el
13953 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13956 unsigned i
, pass
, key_el
= 0;
13957 unsigned types
[NEON_MAX_TYPE_ELS
];
13958 enum neon_el_type k_type
= NT_invtype
;
13959 unsigned k_size
= -1u;
13960 struct neon_type_el badtype
= {NT_invtype
, -1};
13961 unsigned key_allowed
= 0;
13963 /* Optional registers in Neon instructions are always (not) in operand 1.
13964 Fill in the missing operand here, if it was omitted. */
13965 if (els
> 1 && !inst
.operands
[1].present
)
13966 inst
.operands
[1] = inst
.operands
[0];
13968 /* Suck up all the varargs. */
13970 for (i
= 0; i
< els
; i
++)
13972 unsigned thisarg
= va_arg (ap
, unsigned);
13973 if (thisarg
== N_IGNORE_TYPE
)
13978 types
[i
] = thisarg
;
13979 if ((thisarg
& N_KEY
) != 0)
13984 if (inst
.vectype
.elems
> 0)
13985 for (i
= 0; i
< els
; i
++)
13986 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13988 first_error (_("types specified in both the mnemonic and operands"));
13992 /* Duplicate inst.vectype elements here as necessary.
13993 FIXME: No idea if this is exactly the same as the ARM assembler,
13994 particularly when an insn takes one register and one non-register
13996 if (inst
.vectype
.elems
== 1 && els
> 1)
13999 inst
.vectype
.elems
= els
;
14000 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14001 for (j
= 0; j
< els
; j
++)
14003 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14006 else if (inst
.vectype
.elems
== 0 && els
> 0)
14009 /* No types were given after the mnemonic, so look for types specified
14010 after each operand. We allow some flexibility here; as long as the
14011 "key" operand has a type, we can infer the others. */
14012 for (j
= 0; j
< els
; j
++)
14013 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14014 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14016 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14018 for (j
= 0; j
< els
; j
++)
14019 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14020 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14025 first_error (_("operand types can't be inferred"));
14029 else if (inst
.vectype
.elems
!= els
)
14031 first_error (_("type specifier has the wrong number of parts"));
14035 for (pass
= 0; pass
< 2; pass
++)
14037 for (i
= 0; i
< els
; i
++)
14039 unsigned thisarg
= types
[i
];
14040 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14041 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14042 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14043 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14045 /* Decay more-specific signed & unsigned types to sign-insensitive
14046 integer types if sign-specific variants are unavailable. */
14047 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14048 && (types_allowed
& N_SU_ALL
) == 0)
14049 g_type
= NT_integer
;
14051 /* If only untyped args are allowed, decay any more specific types to
14052 them. Some instructions only care about signs for some element
14053 sizes, so handle that properly. */
14054 if (((types_allowed
& N_UNT
) == 0)
14055 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14056 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14057 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14058 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14059 g_type
= NT_untyped
;
14063 if ((thisarg
& N_KEY
) != 0)
14067 key_allowed
= thisarg
& ~N_KEY
;
14069 /* Check architecture constraint on FP16 extension. */
14071 && k_type
== NT_float
14072 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14074 inst
.error
= _(BAD_FP16
);
14081 if ((thisarg
& N_VFP
) != 0)
14083 enum neon_shape_el regshape
;
14084 unsigned regwidth
, match
;
14086 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14089 first_error (_("invalid instruction shape"));
14092 regshape
= neon_shape_tab
[ns
].el
[i
];
14093 regwidth
= neon_shape_el_size
[regshape
];
14095 /* In VFP mode, operands must match register widths. If we
14096 have a key operand, use its width, else use the width of
14097 the current operand. */
14103 /* FP16 will use a single precision register. */
14104 if (regwidth
== 32 && match
== 16)
14106 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14110 inst
.error
= _(BAD_FP16
);
14115 if (regwidth
!= match
)
14117 first_error (_("operand size must match register width"));
14122 if ((thisarg
& N_EQK
) == 0)
14124 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14126 if ((given_type
& types_allowed
) == 0)
14128 first_error (_("bad type in Neon instruction"));
14134 enum neon_el_type mod_k_type
= k_type
;
14135 unsigned mod_k_size
= k_size
;
14136 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14137 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14139 first_error (_("inconsistent types in Neon instruction"));
14147 return inst
.vectype
.el
[key_el
];
14150 /* Neon-style VFP instruction forwarding. */
14152 /* Thumb VFP instructions have 0xE in the condition field. */
14155 do_vfp_cond_or_thumb (void)
14160 inst
.instruction
|= 0xe0000000;
14162 inst
.instruction
|= inst
.cond
<< 28;
14165 /* Look up and encode a simple mnemonic, for use as a helper function for the
14166 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14167 etc. It is assumed that operand parsing has already been done, and that the
14168 operands are in the form expected by the given opcode (this isn't necessarily
14169 the same as the form in which they were parsed, hence some massaging must
14170 take place before this function is called).
14171 Checks current arch version against that in the looked-up opcode. */
14174 do_vfp_nsyn_opcode (const char *opname
)
14176 const struct asm_opcode
*opcode
;
14178 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14183 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14184 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14191 inst
.instruction
= opcode
->tvalue
;
14192 opcode
->tencode ();
14196 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14197 opcode
->aencode ();
14202 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14204 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14206 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14209 do_vfp_nsyn_opcode ("fadds");
14211 do_vfp_nsyn_opcode ("fsubs");
14213 /* ARMv8.2 fp16 instruction. */
14215 do_scalar_fp16_v82_encode ();
14220 do_vfp_nsyn_opcode ("faddd");
14222 do_vfp_nsyn_opcode ("fsubd");
14226 /* Check operand types to see if this is a VFP instruction, and if so call
14230 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14232 enum neon_shape rs
;
14233 struct neon_type_el et
;
14238 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14239 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14243 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14244 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14245 N_F_ALL
| N_KEY
| N_VFP
);
14252 if (et
.type
!= NT_invtype
)
14263 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14265 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14267 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14270 do_vfp_nsyn_opcode ("fmacs");
14272 do_vfp_nsyn_opcode ("fnmacs");
14274 /* ARMv8.2 fp16 instruction. */
14276 do_scalar_fp16_v82_encode ();
14281 do_vfp_nsyn_opcode ("fmacd");
14283 do_vfp_nsyn_opcode ("fnmacd");
14288 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14290 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14292 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14295 do_vfp_nsyn_opcode ("ffmas");
14297 do_vfp_nsyn_opcode ("ffnmas");
14299 /* ARMv8.2 fp16 instruction. */
14301 do_scalar_fp16_v82_encode ();
14306 do_vfp_nsyn_opcode ("ffmad");
14308 do_vfp_nsyn_opcode ("ffnmad");
14313 do_vfp_nsyn_mul (enum neon_shape rs
)
14315 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14317 do_vfp_nsyn_opcode ("fmuls");
14319 /* ARMv8.2 fp16 instruction. */
14321 do_scalar_fp16_v82_encode ();
14324 do_vfp_nsyn_opcode ("fmuld");
14328 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14330 int is_neg
= (inst
.instruction
& 0x80) != 0;
14331 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14333 if (rs
== NS_FF
|| rs
== NS_HH
)
14336 do_vfp_nsyn_opcode ("fnegs");
14338 do_vfp_nsyn_opcode ("fabss");
14340 /* ARMv8.2 fp16 instruction. */
14342 do_scalar_fp16_v82_encode ();
14347 do_vfp_nsyn_opcode ("fnegd");
14349 do_vfp_nsyn_opcode ("fabsd");
14353 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14354 insns belong to Neon, and are handled elsewhere. */
14357 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14359 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14363 do_vfp_nsyn_opcode ("fldmdbs");
14365 do_vfp_nsyn_opcode ("fldmias");
14370 do_vfp_nsyn_opcode ("fstmdbs");
14372 do_vfp_nsyn_opcode ("fstmias");
14377 do_vfp_nsyn_sqrt (void)
14379 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14380 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14382 if (rs
== NS_FF
|| rs
== NS_HH
)
14384 do_vfp_nsyn_opcode ("fsqrts");
14386 /* ARMv8.2 fp16 instruction. */
14388 do_scalar_fp16_v82_encode ();
14391 do_vfp_nsyn_opcode ("fsqrtd");
14395 do_vfp_nsyn_div (void)
14397 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14398 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14399 N_F_ALL
| N_KEY
| N_VFP
);
14401 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14403 do_vfp_nsyn_opcode ("fdivs");
14405 /* ARMv8.2 fp16 instruction. */
14407 do_scalar_fp16_v82_encode ();
14410 do_vfp_nsyn_opcode ("fdivd");
14414 do_vfp_nsyn_nmul (void)
14416 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14417 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14418 N_F_ALL
| N_KEY
| N_VFP
);
14420 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14422 NEON_ENCODE (SINGLE
, inst
);
14423 do_vfp_sp_dyadic ();
14425 /* ARMv8.2 fp16 instruction. */
14427 do_scalar_fp16_v82_encode ();
14431 NEON_ENCODE (DOUBLE
, inst
);
14432 do_vfp_dp_rd_rn_rm ();
14434 do_vfp_cond_or_thumb ();
14439 do_vfp_nsyn_cmp (void)
14441 enum neon_shape rs
;
14442 if (inst
.operands
[1].isreg
)
14444 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14445 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14447 if (rs
== NS_FF
|| rs
== NS_HH
)
14449 NEON_ENCODE (SINGLE
, inst
);
14450 do_vfp_sp_monadic ();
14454 NEON_ENCODE (DOUBLE
, inst
);
14455 do_vfp_dp_rd_rm ();
14460 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14461 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14463 switch (inst
.instruction
& 0x0fffffff)
14466 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14469 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14475 if (rs
== NS_FI
|| rs
== NS_HI
)
14477 NEON_ENCODE (SINGLE
, inst
);
14478 do_vfp_sp_compare_z ();
14482 NEON_ENCODE (DOUBLE
, inst
);
14486 do_vfp_cond_or_thumb ();
14488 /* ARMv8.2 fp16 instruction. */
14489 if (rs
== NS_HI
|| rs
== NS_HH
)
14490 do_scalar_fp16_v82_encode ();
14494 nsyn_insert_sp (void)
14496 inst
.operands
[1] = inst
.operands
[0];
14497 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14498 inst
.operands
[0].reg
= REG_SP
;
14499 inst
.operands
[0].isreg
= 1;
14500 inst
.operands
[0].writeback
= 1;
14501 inst
.operands
[0].present
= 1;
14505 do_vfp_nsyn_push (void)
14509 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14510 _("register list must contain at least 1 and at most 16 "
14513 if (inst
.operands
[1].issingle
)
14514 do_vfp_nsyn_opcode ("fstmdbs");
14516 do_vfp_nsyn_opcode ("fstmdbd");
14520 do_vfp_nsyn_pop (void)
14524 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14525 _("register list must contain at least 1 and at most 16 "
14528 if (inst
.operands
[1].issingle
)
14529 do_vfp_nsyn_opcode ("fldmias");
14531 do_vfp_nsyn_opcode ("fldmiad");
14534 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14535 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14538 neon_dp_fixup (struct arm_it
* insn
)
14540 unsigned int i
= insn
->instruction
;
14545 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14556 insn
->instruction
= i
;
14559 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14563 neon_logbits (unsigned x
)
14565 return ffs (x
) - 4;
14568 #define LOW4(R) ((R) & 0xf)
14569 #define HI1(R) (((R) >> 4) & 1)
14571 /* Encode insns with bit pattern:
14573 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14574 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14576 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14577 different meaning for some instruction. */
14580 neon_three_same (int isquad
, int ubit
, int size
)
14582 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14583 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14584 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14585 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14586 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14587 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14588 inst
.instruction
|= (isquad
!= 0) << 6;
14589 inst
.instruction
|= (ubit
!= 0) << 24;
14591 inst
.instruction
|= neon_logbits (size
) << 20;
14593 neon_dp_fixup (&inst
);
14596 /* Encode instructions of the form:
14598 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14599 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14601 Don't write size if SIZE == -1. */
14604 neon_two_same (int qbit
, int ubit
, int size
)
14606 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14607 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14608 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14609 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14610 inst
.instruction
|= (qbit
!= 0) << 6;
14611 inst
.instruction
|= (ubit
!= 0) << 24;
14614 inst
.instruction
|= neon_logbits (size
) << 18;
14616 neon_dp_fixup (&inst
);
14619 /* Neon instruction encoders, in approximate order of appearance. */
14622 do_neon_dyadic_i_su (void)
14624 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14625 struct neon_type_el et
= neon_check_type (3, rs
,
14626 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14627 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14631 do_neon_dyadic_i64_su (void)
14633 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14634 struct neon_type_el et
= neon_check_type (3, rs
,
14635 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14636 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14640 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14643 unsigned size
= et
.size
>> 3;
14644 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14645 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14646 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14647 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14648 inst
.instruction
|= (isquad
!= 0) << 6;
14649 inst
.instruction
|= immbits
<< 16;
14650 inst
.instruction
|= (size
>> 3) << 7;
14651 inst
.instruction
|= (size
& 0x7) << 19;
14653 inst
.instruction
|= (uval
!= 0) << 24;
14655 neon_dp_fixup (&inst
);
14659 do_neon_shl_imm (void)
14661 if (!inst
.operands
[2].isreg
)
14663 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14664 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14665 int imm
= inst
.operands
[2].imm
;
14667 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14668 _("immediate out of range for shift"));
14669 NEON_ENCODE (IMMED
, inst
);
14670 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14674 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14675 struct neon_type_el et
= neon_check_type (3, rs
,
14676 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14679 /* VSHL/VQSHL 3-register variants have syntax such as:
14681 whereas other 3-register operations encoded by neon_three_same have
14684 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14686 tmp
= inst
.operands
[2].reg
;
14687 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14688 inst
.operands
[1].reg
= tmp
;
14689 NEON_ENCODE (INTEGER
, inst
);
14690 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14695 do_neon_qshl_imm (void)
14697 if (!inst
.operands
[2].isreg
)
14699 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14700 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14701 int imm
= inst
.operands
[2].imm
;
14703 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14704 _("immediate out of range for shift"));
14705 NEON_ENCODE (IMMED
, inst
);
14706 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14710 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14711 struct neon_type_el et
= neon_check_type (3, rs
,
14712 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14715 /* See note in do_neon_shl_imm. */
14716 tmp
= inst
.operands
[2].reg
;
14717 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14718 inst
.operands
[1].reg
= tmp
;
14719 NEON_ENCODE (INTEGER
, inst
);
14720 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14725 do_neon_rshl (void)
14727 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14728 struct neon_type_el et
= neon_check_type (3, rs
,
14729 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14732 tmp
= inst
.operands
[2].reg
;
14733 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14734 inst
.operands
[1].reg
= tmp
;
14735 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14739 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14741 /* Handle .I8 pseudo-instructions. */
14744 /* Unfortunately, this will make everything apart from zero out-of-range.
14745 FIXME is this the intended semantics? There doesn't seem much point in
14746 accepting .I8 if so. */
14747 immediate
|= immediate
<< 8;
14753 if (immediate
== (immediate
& 0x000000ff))
14755 *immbits
= immediate
;
14758 else if (immediate
== (immediate
& 0x0000ff00))
14760 *immbits
= immediate
>> 8;
14763 else if (immediate
== (immediate
& 0x00ff0000))
14765 *immbits
= immediate
>> 16;
14768 else if (immediate
== (immediate
& 0xff000000))
14770 *immbits
= immediate
>> 24;
14773 if ((immediate
& 0xffff) != (immediate
>> 16))
14774 goto bad_immediate
;
14775 immediate
&= 0xffff;
14778 if (immediate
== (immediate
& 0x000000ff))
14780 *immbits
= immediate
;
14783 else if (immediate
== (immediate
& 0x0000ff00))
14785 *immbits
= immediate
>> 8;
14790 first_error (_("immediate value out of range"));
14795 do_neon_logic (void)
14797 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14799 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14800 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14801 /* U bit and size field were set as part of the bitmask. */
14802 NEON_ENCODE (INTEGER
, inst
);
14803 neon_three_same (neon_quad (rs
), 0, -1);
14807 const int three_ops_form
= (inst
.operands
[2].present
14808 && !inst
.operands
[2].isreg
);
14809 const int immoperand
= (three_ops_form
? 2 : 1);
14810 enum neon_shape rs
= (three_ops_form
14811 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14812 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14813 struct neon_type_el et
= neon_check_type (2, rs
,
14814 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14815 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14819 if (et
.type
== NT_invtype
)
14822 if (three_ops_form
)
14823 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14824 _("first and second operands shall be the same register"));
14826 NEON_ENCODE (IMMED
, inst
);
14828 immbits
= inst
.operands
[immoperand
].imm
;
14831 /* .i64 is a pseudo-op, so the immediate must be a repeating
14833 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14834 inst
.operands
[immoperand
].reg
: 0))
14836 /* Set immbits to an invalid constant. */
14837 immbits
= 0xdeadbeef;
14844 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14848 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14852 /* Pseudo-instruction for VBIC. */
14853 neon_invert_size (&immbits
, 0, et
.size
);
14854 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14858 /* Pseudo-instruction for VORR. */
14859 neon_invert_size (&immbits
, 0, et
.size
);
14860 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14870 inst
.instruction
|= neon_quad (rs
) << 6;
14871 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14872 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14873 inst
.instruction
|= cmode
<< 8;
14874 neon_write_immbits (immbits
);
14876 neon_dp_fixup (&inst
);
14881 do_neon_bitfield (void)
14883 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14884 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14885 neon_three_same (neon_quad (rs
), 0, -1);
14889 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14892 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14893 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14895 if (et
.type
== NT_float
)
14897 NEON_ENCODE (FLOAT
, inst
);
14898 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14902 NEON_ENCODE (INTEGER
, inst
);
14903 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14908 do_neon_dyadic_if_su (void)
14910 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14914 do_neon_dyadic_if_su_d (void)
14916 /* This version only allow D registers, but that constraint is enforced during
14917 operand parsing so we don't need to do anything extra here. */
14918 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14922 do_neon_dyadic_if_i_d (void)
14924 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14925 affected if we specify unsigned args. */
14926 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14929 enum vfp_or_neon_is_neon_bits
14932 NEON_CHECK_ARCH
= 2,
14933 NEON_CHECK_ARCH8
= 4
14936 /* Call this function if an instruction which may have belonged to the VFP or
14937 Neon instruction sets, but turned out to be a Neon instruction (due to the
14938 operand types involved, etc.). We have to check and/or fix-up a couple of
14941 - Make sure the user hasn't attempted to make a Neon instruction
14943 - Alter the value in the condition code field if necessary.
14944 - Make sure that the arch supports Neon instructions.
14946 Which of these operations take place depends on bits from enum
14947 vfp_or_neon_is_neon_bits.
14949 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14950 current instruction's condition is COND_ALWAYS, the condition field is
14951 changed to inst.uncond_value. This is necessary because instructions shared
14952 between VFP and Neon may be conditional for the VFP variants only, and the
14953 unconditional Neon version must have, e.g., 0xF in the condition field. */
14956 vfp_or_neon_is_neon (unsigned check
)
14958 /* Conditions are always legal in Thumb mode (IT blocks). */
14959 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14961 if (inst
.cond
!= COND_ALWAYS
)
14963 first_error (_(BAD_COND
));
14966 if (inst
.uncond_value
!= -1)
14967 inst
.instruction
|= inst
.uncond_value
<< 28;
14970 if ((check
& NEON_CHECK_ARCH
)
14971 && !mark_feature_used (&fpu_neon_ext_v1
))
14973 first_error (_(BAD_FPU
));
14977 if ((check
& NEON_CHECK_ARCH8
)
14978 && !mark_feature_used (&fpu_neon_ext_armv8
))
14980 first_error (_(BAD_FPU
));
14988 do_neon_addsub_if_i (void)
14990 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14993 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14996 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14997 affected if we specify unsigned args. */
14998 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15001 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15003 V<op> A,B (A is operand 0, B is operand 2)
15008 so handle that case specially. */
15011 neon_exchange_operands (void)
15013 if (inst
.operands
[1].present
)
15015 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15017 /* Swap operands[1] and operands[2]. */
15018 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15019 inst
.operands
[1] = inst
.operands
[2];
15020 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15025 inst
.operands
[1] = inst
.operands
[2];
15026 inst
.operands
[2] = inst
.operands
[0];
15031 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15033 if (inst
.operands
[2].isreg
)
15036 neon_exchange_operands ();
15037 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15041 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15042 struct neon_type_el et
= neon_check_type (2, rs
,
15043 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15045 NEON_ENCODE (IMMED
, inst
);
15046 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15047 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15048 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15049 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15050 inst
.instruction
|= neon_quad (rs
) << 6;
15051 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15052 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15054 neon_dp_fixup (&inst
);
15061 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15065 do_neon_cmp_inv (void)
15067 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15073 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15076 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15077 scalars, which are encoded in 5 bits, M : Rm.
15078 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15079 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15082 Dot Product instructions are similar to multiply instructions except elsize
15083 should always be 32.
15085 This function translates SCALAR, which is GAS's internal encoding of indexed
15086 scalar register, to raw encoding. There is also register and index range
15087 check based on ELSIZE. */
15090 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15092 unsigned regno
= NEON_SCALAR_REG (scalar
);
15093 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15098 if (regno
> 7 || elno
> 3)
15100 return regno
| (elno
<< 3);
15103 if (regno
> 15 || elno
> 1)
15105 return regno
| (elno
<< 4);
15109 first_error (_("scalar out of range for multiply instruction"));
15115 /* Encode multiply / multiply-accumulate scalar instructions. */
15118 neon_mul_mac (struct neon_type_el et
, int ubit
)
15122 /* Give a more helpful error message if we have an invalid type. */
15123 if (et
.type
== NT_invtype
)
15126 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15127 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15128 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15129 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15130 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15131 inst
.instruction
|= LOW4 (scalar
);
15132 inst
.instruction
|= HI1 (scalar
) << 5;
15133 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15134 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15135 inst
.instruction
|= (ubit
!= 0) << 24;
15137 neon_dp_fixup (&inst
);
15141 do_neon_mac_maybe_scalar (void)
15143 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15146 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15149 if (inst
.operands
[2].isscalar
)
15151 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15152 struct neon_type_el et
= neon_check_type (3, rs
,
15153 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15154 NEON_ENCODE (SCALAR
, inst
);
15155 neon_mul_mac (et
, neon_quad (rs
));
15159 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15160 affected if we specify unsigned args. */
15161 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15166 do_neon_fmac (void)
15168 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15171 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15174 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15180 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15181 struct neon_type_el et
= neon_check_type (3, rs
,
15182 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15183 neon_three_same (neon_quad (rs
), 0, et
.size
);
15186 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15187 same types as the MAC equivalents. The polynomial type for this instruction
15188 is encoded the same as the integer type. */
15193 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15196 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15199 if (inst
.operands
[2].isscalar
)
15200 do_neon_mac_maybe_scalar ();
15202 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15206 do_neon_qdmulh (void)
15208 if (inst
.operands
[2].isscalar
)
15210 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15211 struct neon_type_el et
= neon_check_type (3, rs
,
15212 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15213 NEON_ENCODE (SCALAR
, inst
);
15214 neon_mul_mac (et
, neon_quad (rs
));
15218 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15219 struct neon_type_el et
= neon_check_type (3, rs
,
15220 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15221 NEON_ENCODE (INTEGER
, inst
);
15222 /* The U bit (rounding) comes from bit mask. */
15223 neon_three_same (neon_quad (rs
), 0, et
.size
);
15228 do_neon_qrdmlah (void)
15230 /* Check we're on the correct architecture. */
15231 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15233 _("instruction form not available on this architecture.");
15234 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15236 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15237 record_feature_use (&fpu_neon_ext_v8_1
);
15240 if (inst
.operands
[2].isscalar
)
15242 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15243 struct neon_type_el et
= neon_check_type (3, rs
,
15244 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15245 NEON_ENCODE (SCALAR
, inst
);
15246 neon_mul_mac (et
, neon_quad (rs
));
15250 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15251 struct neon_type_el et
= neon_check_type (3, rs
,
15252 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15253 NEON_ENCODE (INTEGER
, inst
);
15254 /* The U bit (rounding) comes from bit mask. */
15255 neon_three_same (neon_quad (rs
), 0, et
.size
);
15260 do_neon_fcmp_absolute (void)
15262 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15263 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15264 N_F_16_32
| N_KEY
);
15265 /* Size field comes from bit mask. */
15266 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15270 do_neon_fcmp_absolute_inv (void)
15272 neon_exchange_operands ();
15273 do_neon_fcmp_absolute ();
15277 do_neon_step (void)
15279 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15280 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15281 N_F_16_32
| N_KEY
);
15282 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15286 do_neon_abs_neg (void)
15288 enum neon_shape rs
;
15289 struct neon_type_el et
;
15291 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15294 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15297 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15298 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15300 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15301 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15302 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15303 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15304 inst
.instruction
|= neon_quad (rs
) << 6;
15305 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15306 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15308 neon_dp_fixup (&inst
);
15314 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15315 struct neon_type_el et
= neon_check_type (2, rs
,
15316 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15317 int imm
= inst
.operands
[2].imm
;
15318 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15319 _("immediate out of range for insert"));
15320 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15326 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15327 struct neon_type_el et
= neon_check_type (2, rs
,
15328 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15329 int imm
= inst
.operands
[2].imm
;
15330 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15331 _("immediate out of range for insert"));
15332 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15336 do_neon_qshlu_imm (void)
15338 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15339 struct neon_type_el et
= neon_check_type (2, rs
,
15340 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15341 int imm
= inst
.operands
[2].imm
;
15342 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15343 _("immediate out of range for shift"));
15344 /* Only encodes the 'U present' variant of the instruction.
15345 In this case, signed types have OP (bit 8) set to 0.
15346 Unsigned types have OP set to 1. */
15347 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15348 /* The rest of the bits are the same as other immediate shifts. */
15349 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15353 do_neon_qmovn (void)
15355 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15356 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15357 /* Saturating move where operands can be signed or unsigned, and the
15358 destination has the same signedness. */
15359 NEON_ENCODE (INTEGER
, inst
);
15360 if (et
.type
== NT_unsigned
)
15361 inst
.instruction
|= 0xc0;
15363 inst
.instruction
|= 0x80;
15364 neon_two_same (0, 1, et
.size
/ 2);
15368 do_neon_qmovun (void)
15370 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15371 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15372 /* Saturating move with unsigned results. Operands must be signed. */
15373 NEON_ENCODE (INTEGER
, inst
);
15374 neon_two_same (0, 1, et
.size
/ 2);
15378 do_neon_rshift_sat_narrow (void)
15380 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15381 or unsigned. If operands are unsigned, results must also be unsigned. */
15382 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15383 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15384 int imm
= inst
.operands
[2].imm
;
15385 /* This gets the bounds check, size encoding and immediate bits calculation
15389 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15390 VQMOVN.I<size> <Dd>, <Qm>. */
15393 inst
.operands
[2].present
= 0;
15394 inst
.instruction
= N_MNEM_vqmovn
;
15399 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15400 _("immediate out of range"));
15401 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15405 do_neon_rshift_sat_narrow_u (void)
15407 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15408 or unsigned. If operands are unsigned, results must also be unsigned. */
15409 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15410 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15411 int imm
= inst
.operands
[2].imm
;
15412 /* This gets the bounds check, size encoding and immediate bits calculation
15416 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15417 VQMOVUN.I<size> <Dd>, <Qm>. */
15420 inst
.operands
[2].present
= 0;
15421 inst
.instruction
= N_MNEM_vqmovun
;
15426 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15427 _("immediate out of range"));
15428 /* FIXME: The manual is kind of unclear about what value U should have in
15429 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15431 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15435 do_neon_movn (void)
15437 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15438 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15439 NEON_ENCODE (INTEGER
, inst
);
15440 neon_two_same (0, 1, et
.size
/ 2);
15444 do_neon_rshift_narrow (void)
15446 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15447 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15448 int imm
= inst
.operands
[2].imm
;
15449 /* This gets the bounds check, size encoding and immediate bits calculation
15453 /* If immediate is zero then we are a pseudo-instruction for
15454 VMOVN.I<size> <Dd>, <Qm> */
15457 inst
.operands
[2].present
= 0;
15458 inst
.instruction
= N_MNEM_vmovn
;
15463 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15464 _("immediate out of range for narrowing operation"));
15465 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15469 do_neon_shll (void)
15471 /* FIXME: Type checking when lengthening. */
15472 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15473 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15474 unsigned imm
= inst
.operands
[2].imm
;
15476 if (imm
== et
.size
)
15478 /* Maximum shift variant. */
15479 NEON_ENCODE (INTEGER
, inst
);
15480 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15481 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15482 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15483 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15484 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15486 neon_dp_fixup (&inst
);
15490 /* A more-specific type check for non-max versions. */
15491 et
= neon_check_type (2, NS_QDI
,
15492 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15493 NEON_ENCODE (IMMED
, inst
);
15494 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15498 /* Check the various types for the VCVT instruction, and return which version
15499 the current instruction is. */
15501 #define CVT_FLAVOUR_VAR \
15502 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15503 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15504 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15505 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15506 /* Half-precision conversions. */ \
15507 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15508 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15509 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15510 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15511 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15512 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15513 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15514 Compared with single/double precision variants, only the co-processor \
15515 field is different, so the encoding flow is reused here. */ \
15516 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15517 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15518 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15519 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15520 /* VFP instructions. */ \
15521 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15522 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15523 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15524 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15525 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15526 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15527 /* VFP instructions with bitshift. */ \
15528 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15529 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15530 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15531 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15532 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15533 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15534 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15535 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15537 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15538 neon_cvt_flavour_##C,
15540 /* The different types of conversions we can do. */
15541 enum neon_cvt_flavour
15544 neon_cvt_flavour_invalid
,
15545 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15550 static enum neon_cvt_flavour
15551 get_neon_cvt_flavour (enum neon_shape rs
)
15553 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15554 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15555 if (et.type != NT_invtype) \
15557 inst.error = NULL; \
15558 return (neon_cvt_flavour_##C); \
15561 struct neon_type_el et
;
15562 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15563 || rs
== NS_FF
) ? N_VFP
: 0;
15564 /* The instruction versions which take an immediate take one register
15565 argument, which is extended to the width of the full register. Thus the
15566 "source" and "destination" registers must have the same width. Hack that
15567 here by making the size equal to the key (wider, in this case) operand. */
15568 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15572 return neon_cvt_flavour_invalid
;
15587 /* Neon-syntax VFP conversions. */
15590 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15592 const char *opname
= 0;
15594 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15595 || rs
== NS_FHI
|| rs
== NS_HFI
)
15597 /* Conversions with immediate bitshift. */
15598 const char *enc
[] =
15600 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15606 if (flavour
< (int) ARRAY_SIZE (enc
))
15608 opname
= enc
[flavour
];
15609 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15610 _("operands 0 and 1 must be the same register"));
15611 inst
.operands
[1] = inst
.operands
[2];
15612 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15617 /* Conversions without bitshift. */
15618 const char *enc
[] =
15620 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15626 if (flavour
< (int) ARRAY_SIZE (enc
))
15627 opname
= enc
[flavour
];
15631 do_vfp_nsyn_opcode (opname
);
15633 /* ARMv8.2 fp16 VCVT instruction. */
15634 if (flavour
== neon_cvt_flavour_s32_f16
15635 || flavour
== neon_cvt_flavour_u32_f16
15636 || flavour
== neon_cvt_flavour_f16_u32
15637 || flavour
== neon_cvt_flavour_f16_s32
)
15638 do_scalar_fp16_v82_encode ();
15642 do_vfp_nsyn_cvtz (void)
15644 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15645 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15646 const char *enc
[] =
15648 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15654 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15655 do_vfp_nsyn_opcode (enc
[flavour
]);
15659 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15660 enum neon_cvt_mode mode
)
15665 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15666 D register operands. */
15667 if (flavour
== neon_cvt_flavour_s32_f64
15668 || flavour
== neon_cvt_flavour_u32_f64
)
15669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15672 if (flavour
== neon_cvt_flavour_s32_f16
15673 || flavour
== neon_cvt_flavour_u32_f16
)
15674 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15677 set_it_insn_type (OUTSIDE_IT_INSN
);
15681 case neon_cvt_flavour_s32_f64
:
15685 case neon_cvt_flavour_s32_f32
:
15689 case neon_cvt_flavour_s32_f16
:
15693 case neon_cvt_flavour_u32_f64
:
15697 case neon_cvt_flavour_u32_f32
:
15701 case neon_cvt_flavour_u32_f16
:
15706 first_error (_("invalid instruction shape"));
15712 case neon_cvt_mode_a
: rm
= 0; break;
15713 case neon_cvt_mode_n
: rm
= 1; break;
15714 case neon_cvt_mode_p
: rm
= 2; break;
15715 case neon_cvt_mode_m
: rm
= 3; break;
15716 default: first_error (_("invalid rounding mode")); return;
15719 NEON_ENCODE (FPV8
, inst
);
15720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15721 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15722 inst
.instruction
|= sz
<< 8;
15724 /* ARMv8.2 fp16 VCVT instruction. */
15725 if (flavour
== neon_cvt_flavour_s32_f16
15726 ||flavour
== neon_cvt_flavour_u32_f16
)
15727 do_scalar_fp16_v82_encode ();
15728 inst
.instruction
|= op
<< 7;
15729 inst
.instruction
|= rm
<< 16;
15730 inst
.instruction
|= 0xf0000000;
15731 inst
.is_neon
= TRUE
;
15735 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15737 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15738 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15739 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15741 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15743 if (flavour
== neon_cvt_flavour_invalid
)
15746 /* PR11109: Handle round-to-zero for VCVT conversions. */
15747 if (mode
== neon_cvt_mode_z
15748 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15749 && (flavour
== neon_cvt_flavour_s16_f16
15750 || flavour
== neon_cvt_flavour_u16_f16
15751 || flavour
== neon_cvt_flavour_s32_f32
15752 || flavour
== neon_cvt_flavour_u32_f32
15753 || flavour
== neon_cvt_flavour_s32_f64
15754 || flavour
== neon_cvt_flavour_u32_f64
)
15755 && (rs
== NS_FD
|| rs
== NS_FF
))
15757 do_vfp_nsyn_cvtz ();
15761 /* ARMv8.2 fp16 VCVT conversions. */
15762 if (mode
== neon_cvt_mode_z
15763 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15764 && (flavour
== neon_cvt_flavour_s32_f16
15765 || flavour
== neon_cvt_flavour_u32_f16
)
15768 do_vfp_nsyn_cvtz ();
15769 do_scalar_fp16_v82_encode ();
15773 /* VFP rather than Neon conversions. */
15774 if (flavour
>= neon_cvt_flavour_first_fp
)
15776 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15777 do_vfp_nsyn_cvt (rs
, flavour
);
15779 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15790 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15791 0x0000100, 0x1000100, 0x0, 0x1000000};
15793 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15796 /* Fixed-point conversion with #0 immediate is encoded as an
15797 integer conversion. */
15798 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15800 NEON_ENCODE (IMMED
, inst
);
15801 if (flavour
!= neon_cvt_flavour_invalid
)
15802 inst
.instruction
|= enctab
[flavour
];
15803 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15804 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15805 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15806 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15807 inst
.instruction
|= neon_quad (rs
) << 6;
15808 inst
.instruction
|= 1 << 21;
15809 if (flavour
< neon_cvt_flavour_s16_f16
)
15811 inst
.instruction
|= 1 << 21;
15812 immbits
= 32 - inst
.operands
[2].imm
;
15813 inst
.instruction
|= immbits
<< 16;
15817 inst
.instruction
|= 3 << 20;
15818 immbits
= 16 - inst
.operands
[2].imm
;
15819 inst
.instruction
|= immbits
<< 16;
15820 inst
.instruction
&= ~(1 << 9);
15823 neon_dp_fixup (&inst
);
15829 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15831 NEON_ENCODE (FLOAT
, inst
);
15832 set_it_insn_type (OUTSIDE_IT_INSN
);
15834 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15841 inst
.instruction
|= neon_quad (rs
) << 6;
15842 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15843 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15844 inst
.instruction
|= mode
<< 8;
15845 if (flavour
== neon_cvt_flavour_u16_f16
15846 || flavour
== neon_cvt_flavour_s16_f16
)
15847 /* Mask off the original size bits and reencode them. */
15848 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15851 inst
.instruction
|= 0xfc000000;
15853 inst
.instruction
|= 0xf0000000;
15859 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15860 0x100, 0x180, 0x0, 0x080};
15862 NEON_ENCODE (INTEGER
, inst
);
15864 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15867 if (flavour
!= neon_cvt_flavour_invalid
)
15868 inst
.instruction
|= enctab
[flavour
];
15870 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15871 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15872 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15873 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15874 inst
.instruction
|= neon_quad (rs
) << 6;
15875 if (flavour
>= neon_cvt_flavour_s16_f16
15876 && flavour
<= neon_cvt_flavour_f16_u16
)
15877 /* Half precision. */
15878 inst
.instruction
|= 1 << 18;
15880 inst
.instruction
|= 2 << 18;
15882 neon_dp_fixup (&inst
);
15887 /* Half-precision conversions for Advanced SIMD -- neon. */
15892 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15894 as_bad (_("operand size must match register width"));
15899 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15901 as_bad (_("operand size must match register width"));
15906 inst
.instruction
= 0x3b60600;
15908 inst
.instruction
= 0x3b60700;
15910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15911 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15912 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15913 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15914 neon_dp_fixup (&inst
);
15918 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15919 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15920 do_vfp_nsyn_cvt (rs
, flavour
);
15922 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15927 do_neon_cvtr (void)
15929 do_neon_cvt_1 (neon_cvt_mode_x
);
15935 do_neon_cvt_1 (neon_cvt_mode_z
);
15939 do_neon_cvta (void)
15941 do_neon_cvt_1 (neon_cvt_mode_a
);
15945 do_neon_cvtn (void)
15947 do_neon_cvt_1 (neon_cvt_mode_n
);
15951 do_neon_cvtp (void)
15953 do_neon_cvt_1 (neon_cvt_mode_p
);
15957 do_neon_cvtm (void)
15959 do_neon_cvt_1 (neon_cvt_mode_m
);
15963 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15966 mark_feature_used (&fpu_vfp_ext_armv8
);
15968 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15969 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15970 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15971 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15972 inst
.instruction
|= to
? 0x10000 : 0;
15973 inst
.instruction
|= t
? 0x80 : 0;
15974 inst
.instruction
|= is_double
? 0x100 : 0;
15975 do_vfp_cond_or_thumb ();
15979 do_neon_cvttb_1 (bfd_boolean t
)
15981 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15982 NS_DF
, NS_DH
, NS_NULL
);
15986 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15989 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15991 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15994 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15996 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15998 /* The VCVTB and VCVTT instructions with D-register operands
15999 don't work for SP only targets. */
16000 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16004 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16006 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16008 /* The VCVTB and VCVTT instructions with D-register operands
16009 don't work for SP only targets. */
16010 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16014 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16021 do_neon_cvtb (void)
16023 do_neon_cvttb_1 (FALSE
);
16028 do_neon_cvtt (void)
16030 do_neon_cvttb_1 (TRUE
);
16034 neon_move_immediate (void)
16036 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16037 struct neon_type_el et
= neon_check_type (2, rs
,
16038 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16039 unsigned immlo
, immhi
= 0, immbits
;
16040 int op
, cmode
, float_p
;
16042 constraint (et
.type
== NT_invtype
,
16043 _("operand size must be specified for immediate VMOV"));
16045 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16046 op
= (inst
.instruction
& (1 << 5)) != 0;
16048 immlo
= inst
.operands
[1].imm
;
16049 if (inst
.operands
[1].regisimm
)
16050 immhi
= inst
.operands
[1].reg
;
16052 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16053 _("immediate has bits set outside the operand size"));
16055 float_p
= inst
.operands
[1].immisfloat
;
16057 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16058 et
.size
, et
.type
)) == FAIL
)
16060 /* Invert relevant bits only. */
16061 neon_invert_size (&immlo
, &immhi
, et
.size
);
16062 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16063 with one or the other; those cases are caught by
16064 neon_cmode_for_move_imm. */
16066 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16067 &op
, et
.size
, et
.type
)) == FAIL
)
16069 first_error (_("immediate out of range"));
16074 inst
.instruction
&= ~(1 << 5);
16075 inst
.instruction
|= op
<< 5;
16077 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16078 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16079 inst
.instruction
|= neon_quad (rs
) << 6;
16080 inst
.instruction
|= cmode
<< 8;
16082 neon_write_immbits (immbits
);
16088 if (inst
.operands
[1].isreg
)
16090 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16092 NEON_ENCODE (INTEGER
, inst
);
16093 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16094 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16095 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16096 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16097 inst
.instruction
|= neon_quad (rs
) << 6;
16101 NEON_ENCODE (IMMED
, inst
);
16102 neon_move_immediate ();
16105 neon_dp_fixup (&inst
);
16108 /* Encode instructions of form:
16110 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16111 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16114 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16116 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16118 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16119 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16120 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16121 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16122 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16123 inst
.instruction
|= neon_logbits (size
) << 20;
16125 neon_dp_fixup (&inst
);
16129 do_neon_dyadic_long (void)
16131 /* FIXME: Type checking for lengthening op. */
16132 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16133 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16134 neon_mixed_length (et
, et
.size
);
16138 do_neon_abal (void)
16140 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16141 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16142 neon_mixed_length (et
, et
.size
);
16146 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16148 if (inst
.operands
[2].isscalar
)
16150 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16151 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16152 NEON_ENCODE (SCALAR
, inst
);
16153 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16157 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16158 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16159 NEON_ENCODE (INTEGER
, inst
);
16160 neon_mixed_length (et
, et
.size
);
16165 do_neon_mac_maybe_scalar_long (void)
16167 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16170 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16171 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16174 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16176 unsigned regno
= NEON_SCALAR_REG (scalar
);
16177 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16181 if (regno
> 7 || elno
> 3)
16184 return ((regno
& 0x7)
16185 | ((elno
& 0x1) << 3)
16186 | (((elno
>> 1) & 0x1) << 5));
16190 if (regno
> 15 || elno
> 1)
16193 return (((regno
& 0x1) << 5)
16194 | ((regno
>> 1) & 0x7)
16195 | ((elno
& 0x1) << 3));
16199 first_error (_("scalar out of range for multiply instruction"));
16204 do_neon_fmac_maybe_scalar_long (int subtype
)
16206 enum neon_shape rs
;
16208 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16209 field (bits[21:20]) has different meaning. For scalar index variant, it's
16210 used to differentiate add and subtract, otherwise it's with fixed value
16214 if (inst
.cond
!= COND_ALWAYS
)
16215 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16216 "behaviour is UNPREDICTABLE"));
16218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16221 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16224 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16225 be a scalar index register. */
16226 if (inst
.operands
[2].isscalar
)
16228 high8
= 0xfe000000;
16231 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16235 high8
= 0xfc000000;
16238 inst
.instruction
|= (0x1 << 23);
16239 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16242 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16244 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16245 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16246 so we simply pass -1 as size. */
16247 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16248 neon_three_same (quad_p
, 0, size
);
16250 /* Undo neon_dp_fixup. Redo the high eight bits. */
16251 inst
.instruction
&= 0x00ffffff;
16252 inst
.instruction
|= high8
;
16254 #define LOW1(R) ((R) & 0x1)
16255 #define HI4(R) (((R) >> 1) & 0xf)
16256 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16257 whether the instruction is in Q form and whether Vm is a scalar indexed
16259 if (inst
.operands
[2].isscalar
)
16262 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16263 inst
.instruction
&= 0xffffffd0;
16264 inst
.instruction
|= rm
;
16268 /* Redo Rn as well. */
16269 inst
.instruction
&= 0xfff0ff7f;
16270 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16271 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16276 /* Redo Rn and Rm. */
16277 inst
.instruction
&= 0xfff0ff50;
16278 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16279 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16280 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16281 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16286 do_neon_vfmal (void)
16288 return do_neon_fmac_maybe_scalar_long (0);
16292 do_neon_vfmsl (void)
16294 return do_neon_fmac_maybe_scalar_long (1);
16298 do_neon_dyadic_wide (void)
16300 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16301 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16302 neon_mixed_length (et
, et
.size
);
16306 do_neon_dyadic_narrow (void)
16308 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16309 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16310 /* Operand sign is unimportant, and the U bit is part of the opcode,
16311 so force the operand type to integer. */
16312 et
.type
= NT_integer
;
16313 neon_mixed_length (et
, et
.size
/ 2);
16317 do_neon_mul_sat_scalar_long (void)
16319 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16323 do_neon_vmull (void)
16325 if (inst
.operands
[2].isscalar
)
16326 do_neon_mac_maybe_scalar_long ();
16329 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16330 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16332 if (et
.type
== NT_poly
)
16333 NEON_ENCODE (POLY
, inst
);
16335 NEON_ENCODE (INTEGER
, inst
);
16337 /* For polynomial encoding the U bit must be zero, and the size must
16338 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16339 obviously, as 0b10). */
16342 /* Check we're on the correct architecture. */
16343 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16345 _("Instruction form not available on this architecture.");
16350 neon_mixed_length (et
, et
.size
);
16357 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16358 struct neon_type_el et
= neon_check_type (3, rs
,
16359 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16360 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16362 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16363 _("shift out of range"));
16364 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16365 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16366 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16367 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16368 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16369 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16370 inst
.instruction
|= neon_quad (rs
) << 6;
16371 inst
.instruction
|= imm
<< 8;
16373 neon_dp_fixup (&inst
);
16379 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16380 struct neon_type_el et
= neon_check_type (2, rs
,
16381 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16382 unsigned op
= (inst
.instruction
>> 7) & 3;
16383 /* N (width of reversed regions) is encoded as part of the bitmask. We
16384 extract it here to check the elements to be reversed are smaller.
16385 Otherwise we'd get a reserved instruction. */
16386 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16387 gas_assert (elsize
!= 0);
16388 constraint (et
.size
>= elsize
,
16389 _("elements must be smaller than reversal region"));
16390 neon_two_same (neon_quad (rs
), 1, et
.size
);
16396 if (inst
.operands
[1].isscalar
)
16398 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16399 struct neon_type_el et
= neon_check_type (2, rs
,
16400 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16401 unsigned sizebits
= et
.size
>> 3;
16402 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16403 int logsize
= neon_logbits (et
.size
);
16404 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16406 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16409 NEON_ENCODE (SCALAR
, inst
);
16410 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16411 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16412 inst
.instruction
|= LOW4 (dm
);
16413 inst
.instruction
|= HI1 (dm
) << 5;
16414 inst
.instruction
|= neon_quad (rs
) << 6;
16415 inst
.instruction
|= x
<< 17;
16416 inst
.instruction
|= sizebits
<< 16;
16418 neon_dp_fixup (&inst
);
16422 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16423 struct neon_type_el et
= neon_check_type (2, rs
,
16424 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16425 /* Duplicate ARM register to lanes of vector. */
16426 NEON_ENCODE (ARMREG
, inst
);
16429 case 8: inst
.instruction
|= 0x400000; break;
16430 case 16: inst
.instruction
|= 0x000020; break;
16431 case 32: inst
.instruction
|= 0x000000; break;
16434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16435 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16436 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16437 inst
.instruction
|= neon_quad (rs
) << 21;
16438 /* The encoding for this instruction is identical for the ARM and Thumb
16439 variants, except for the condition field. */
16440 do_vfp_cond_or_thumb ();
16444 /* VMOV has particularly many variations. It can be one of:
16445 0. VMOV<c><q> <Qd>, <Qm>
16446 1. VMOV<c><q> <Dd>, <Dm>
16447 (Register operations, which are VORR with Rm = Rn.)
16448 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16449 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16451 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16452 (ARM register to scalar.)
16453 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16454 (Two ARM registers to vector.)
16455 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16456 (Scalar to ARM register.)
16457 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16458 (Vector to two ARM registers.)
16459 8. VMOV.F32 <Sd>, <Sm>
16460 9. VMOV.F64 <Dd>, <Dm>
16461 (VFP register moves.)
16462 10. VMOV.F32 <Sd>, #imm
16463 11. VMOV.F64 <Dd>, #imm
16464 (VFP float immediate load.)
16465 12. VMOV <Rd>, <Sm>
16466 (VFP single to ARM reg.)
16467 13. VMOV <Sd>, <Rm>
16468 (ARM reg to VFP single.)
16469 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16470 (Two ARM regs to two VFP singles.)
16471 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16472 (Two VFP singles to two ARM regs.)
16474 These cases can be disambiguated using neon_select_shape, except cases 1/9
16475 and 3/11 which depend on the operand type too.
16477 All the encoded bits are hardcoded by this function.
16479 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16480 Cases 5, 7 may be used with VFPv2 and above.
16482 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16483 can specify a type where it doesn't make sense to, and is ignored). */
16488 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16489 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16490 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16491 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16492 struct neon_type_el et
;
16493 const char *ldconst
= 0;
16497 case NS_DD
: /* case 1/9. */
16498 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16499 /* It is not an error here if no type is given. */
16501 if (et
.type
== NT_float
&& et
.size
== 64)
16503 do_vfp_nsyn_opcode ("fcpyd");
16506 /* fall through. */
16508 case NS_QQ
: /* case 0/1. */
16510 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16512 /* The architecture manual I have doesn't explicitly state which
16513 value the U bit should have for register->register moves, but
16514 the equivalent VORR instruction has U = 0, so do that. */
16515 inst
.instruction
= 0x0200110;
16516 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16517 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16518 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16519 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16520 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16521 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16522 inst
.instruction
|= neon_quad (rs
) << 6;
16524 neon_dp_fixup (&inst
);
16528 case NS_DI
: /* case 3/11. */
16529 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16531 if (et
.type
== NT_float
&& et
.size
== 64)
16533 /* case 11 (fconstd). */
16534 ldconst
= "fconstd";
16535 goto encode_fconstd
;
16537 /* fall through. */
16539 case NS_QI
: /* case 2/3. */
16540 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16542 inst
.instruction
= 0x0800010;
16543 neon_move_immediate ();
16544 neon_dp_fixup (&inst
);
16547 case NS_SR
: /* case 4. */
16549 unsigned bcdebits
= 0;
16551 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16552 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16554 /* .<size> is optional here, defaulting to .32. */
16555 if (inst
.vectype
.elems
== 0
16556 && inst
.operands
[0].vectype
.type
== NT_invtype
16557 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16559 inst
.vectype
.el
[0].type
= NT_untyped
;
16560 inst
.vectype
.el
[0].size
= 32;
16561 inst
.vectype
.elems
= 1;
16564 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16565 logsize
= neon_logbits (et
.size
);
16567 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16569 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16570 && et
.size
!= 32, _(BAD_FPU
));
16571 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16572 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16576 case 8: bcdebits
= 0x8; break;
16577 case 16: bcdebits
= 0x1; break;
16578 case 32: bcdebits
= 0x0; break;
16582 bcdebits
|= x
<< logsize
;
16584 inst
.instruction
= 0xe000b10;
16585 do_vfp_cond_or_thumb ();
16586 inst
.instruction
|= LOW4 (dn
) << 16;
16587 inst
.instruction
|= HI1 (dn
) << 7;
16588 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16589 inst
.instruction
|= (bcdebits
& 3) << 5;
16590 inst
.instruction
|= (bcdebits
>> 2) << 21;
16594 case NS_DRR
: /* case 5 (fmdrr). */
16595 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16598 inst
.instruction
= 0xc400b10;
16599 do_vfp_cond_or_thumb ();
16600 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16601 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16602 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16603 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16606 case NS_RS
: /* case 6. */
16609 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16610 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16611 unsigned abcdebits
= 0;
16613 /* .<dt> is optional here, defaulting to .32. */
16614 if (inst
.vectype
.elems
== 0
16615 && inst
.operands
[0].vectype
.type
== NT_invtype
16616 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16618 inst
.vectype
.el
[0].type
= NT_untyped
;
16619 inst
.vectype
.el
[0].size
= 32;
16620 inst
.vectype
.elems
= 1;
16623 et
= neon_check_type (2, NS_NULL
,
16624 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16625 logsize
= neon_logbits (et
.size
);
16627 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16629 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16630 && et
.size
!= 32, _(BAD_FPU
));
16631 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16632 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16636 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16637 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16638 case 32: abcdebits
= 0x00; break;
16642 abcdebits
|= x
<< logsize
;
16643 inst
.instruction
= 0xe100b10;
16644 do_vfp_cond_or_thumb ();
16645 inst
.instruction
|= LOW4 (dn
) << 16;
16646 inst
.instruction
|= HI1 (dn
) << 7;
16647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16648 inst
.instruction
|= (abcdebits
& 3) << 5;
16649 inst
.instruction
|= (abcdebits
>> 2) << 21;
16653 case NS_RRD
: /* case 7 (fmrrd). */
16654 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16657 inst
.instruction
= 0xc500b10;
16658 do_vfp_cond_or_thumb ();
16659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16660 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16661 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16662 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16665 case NS_FF
: /* case 8 (fcpys). */
16666 do_vfp_nsyn_opcode ("fcpys");
16670 case NS_FI
: /* case 10 (fconsts). */
16671 ldconst
= "fconsts";
16673 if (is_quarter_float (inst
.operands
[1].imm
))
16675 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16676 do_vfp_nsyn_opcode (ldconst
);
16678 /* ARMv8.2 fp16 vmov.f16 instruction. */
16680 do_scalar_fp16_v82_encode ();
16683 first_error (_("immediate out of range"));
16687 case NS_RF
: /* case 12 (fmrs). */
16688 do_vfp_nsyn_opcode ("fmrs");
16689 /* ARMv8.2 fp16 vmov.f16 instruction. */
16691 do_scalar_fp16_v82_encode ();
16695 case NS_FR
: /* case 13 (fmsr). */
16696 do_vfp_nsyn_opcode ("fmsr");
16697 /* ARMv8.2 fp16 vmov.f16 instruction. */
16699 do_scalar_fp16_v82_encode ();
16702 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16703 (one of which is a list), but we have parsed four. Do some fiddling to
16704 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16706 case NS_RRFF
: /* case 14 (fmrrs). */
16707 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16708 _("VFP registers must be adjacent"));
16709 inst
.operands
[2].imm
= 2;
16710 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16711 do_vfp_nsyn_opcode ("fmrrs");
16714 case NS_FFRR
: /* case 15 (fmsrr). */
16715 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16716 _("VFP registers must be adjacent"));
16717 inst
.operands
[1] = inst
.operands
[2];
16718 inst
.operands
[2] = inst
.operands
[3];
16719 inst
.operands
[0].imm
= 2;
16720 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16721 do_vfp_nsyn_opcode ("fmsrr");
16725 /* neon_select_shape has determined that the instruction
16726 shape is wrong and has already set the error message. */
16735 do_neon_rshift_round_imm (void)
16737 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16738 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16739 int imm
= inst
.operands
[2].imm
;
16741 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16744 inst
.operands
[2].present
= 0;
16749 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16750 _("immediate out of range for shift"));
16751 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16756 do_neon_movhf (void)
16758 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16759 constraint (rs
!= NS_HH
, _("invalid suffix"));
16761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16764 do_vfp_sp_monadic ();
16767 inst
.instruction
|= 0xf0000000;
16771 do_neon_movl (void)
16773 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16774 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16775 unsigned sizebits
= et
.size
>> 3;
16776 inst
.instruction
|= sizebits
<< 19;
16777 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16783 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16784 struct neon_type_el et
= neon_check_type (2, rs
,
16785 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16786 NEON_ENCODE (INTEGER
, inst
);
16787 neon_two_same (neon_quad (rs
), 1, et
.size
);
16791 do_neon_zip_uzp (void)
16793 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16794 struct neon_type_el et
= neon_check_type (2, rs
,
16795 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16796 if (rs
== NS_DD
&& et
.size
== 32)
16798 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16799 inst
.instruction
= N_MNEM_vtrn
;
16803 neon_two_same (neon_quad (rs
), 1, et
.size
);
16807 do_neon_sat_abs_neg (void)
16809 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16810 struct neon_type_el et
= neon_check_type (2, rs
,
16811 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16812 neon_two_same (neon_quad (rs
), 1, et
.size
);
16816 do_neon_pair_long (void)
16818 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16819 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16820 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16821 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16822 neon_two_same (neon_quad (rs
), 1, et
.size
);
16826 do_neon_recip_est (void)
16828 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16829 struct neon_type_el et
= neon_check_type (2, rs
,
16830 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16831 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16832 neon_two_same (neon_quad (rs
), 1, et
.size
);
16838 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16839 struct neon_type_el et
= neon_check_type (2, rs
,
16840 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16841 neon_two_same (neon_quad (rs
), 1, et
.size
);
16847 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16848 struct neon_type_el et
= neon_check_type (2, rs
,
16849 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16850 neon_two_same (neon_quad (rs
), 1, et
.size
);
16856 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16857 struct neon_type_el et
= neon_check_type (2, rs
,
16858 N_EQK
| N_INT
, N_8
| N_KEY
);
16859 neon_two_same (neon_quad (rs
), 1, et
.size
);
16865 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16866 neon_two_same (neon_quad (rs
), 1, -1);
16870 do_neon_tbl_tbx (void)
16872 unsigned listlenbits
;
16873 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16875 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16877 first_error (_("bad list length for table lookup"));
16881 listlenbits
= inst
.operands
[1].imm
- 1;
16882 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16883 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16884 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16885 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16886 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16887 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16888 inst
.instruction
|= listlenbits
<< 8;
16890 neon_dp_fixup (&inst
);
16894 do_neon_ldm_stm (void)
16896 /* P, U and L bits are part of bitmask. */
16897 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16898 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16900 if (inst
.operands
[1].issingle
)
16902 do_vfp_nsyn_ldm_stm (is_dbmode
);
16906 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16907 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16909 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16910 _("register list must contain at least 1 and at most 16 "
16913 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16914 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16915 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16916 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16918 inst
.instruction
|= offsetbits
;
16920 do_vfp_cond_or_thumb ();
16924 do_neon_ldr_str (void)
16926 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16928 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16929 And is UNPREDICTABLE in thumb mode. */
16931 && inst
.operands
[1].reg
== REG_PC
16932 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16935 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16936 else if (warn_on_deprecated
)
16937 as_tsktsk (_("Use of PC here is deprecated"));
16940 if (inst
.operands
[0].issingle
)
16943 do_vfp_nsyn_opcode ("flds");
16945 do_vfp_nsyn_opcode ("fsts");
16947 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16948 if (inst
.vectype
.el
[0].size
== 16)
16949 do_scalar_fp16_v82_encode ();
16954 do_vfp_nsyn_opcode ("fldd");
16956 do_vfp_nsyn_opcode ("fstd");
16960 /* "interleave" version also handles non-interleaving register VLD1/VST1
16964 do_neon_ld_st_interleave (void)
16966 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16967 N_8
| N_16
| N_32
| N_64
);
16968 unsigned alignbits
= 0;
16970 /* The bits in this table go:
16971 0: register stride of one (0) or two (1)
16972 1,2: register list length, minus one (1, 2, 3, 4).
16973 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16974 We use -1 for invalid entries. */
16975 const int typetable
[] =
16977 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16978 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16979 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16980 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16984 if (et
.type
== NT_invtype
)
16987 if (inst
.operands
[1].immisalign
)
16988 switch (inst
.operands
[1].imm
>> 8)
16990 case 64: alignbits
= 1; break;
16992 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16993 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16994 goto bad_alignment
;
16998 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16999 goto bad_alignment
;
17004 first_error (_("bad alignment"));
17008 inst
.instruction
|= alignbits
<< 4;
17009 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17011 /* Bits [4:6] of the immediate in a list specifier encode register stride
17012 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17013 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17014 up the right value for "type" in a table based on this value and the given
17015 list style, then stick it back. */
17016 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17017 | (((inst
.instruction
>> 8) & 3) << 3);
17019 typebits
= typetable
[idx
];
17021 constraint (typebits
== -1, _("bad list type for instruction"));
17022 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17023 _("bad element type for instruction"));
17025 inst
.instruction
&= ~0xf00;
17026 inst
.instruction
|= typebits
<< 8;
17029 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17030 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17031 otherwise. The variable arguments are a list of pairs of legal (size, align)
17032 values, terminated with -1. */
17035 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17038 int result
= FAIL
, thissize
, thisalign
;
17040 if (!inst
.operands
[1].immisalign
)
17046 va_start (ap
, do_alignment
);
17050 thissize
= va_arg (ap
, int);
17051 if (thissize
== -1)
17053 thisalign
= va_arg (ap
, int);
17055 if (size
== thissize
&& align
== thisalign
)
17058 while (result
!= SUCCESS
);
17062 if (result
== SUCCESS
)
17065 first_error (_("unsupported alignment for instruction"));
17071 do_neon_ld_st_lane (void)
17073 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17074 int align_good
, do_alignment
= 0;
17075 int logsize
= neon_logbits (et
.size
);
17076 int align
= inst
.operands
[1].imm
>> 8;
17077 int n
= (inst
.instruction
>> 8) & 3;
17078 int max_el
= 64 / et
.size
;
17080 if (et
.type
== NT_invtype
)
17083 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17084 _("bad list length"));
17085 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17086 _("scalar index out of range"));
17087 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17089 _("stride of 2 unavailable when element size is 8"));
17093 case 0: /* VLD1 / VST1. */
17094 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17096 if (align_good
== FAIL
)
17100 unsigned alignbits
= 0;
17103 case 16: alignbits
= 0x1; break;
17104 case 32: alignbits
= 0x3; break;
17107 inst
.instruction
|= alignbits
<< 4;
17111 case 1: /* VLD2 / VST2. */
17112 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17113 16, 32, 32, 64, -1);
17114 if (align_good
== FAIL
)
17117 inst
.instruction
|= 1 << 4;
17120 case 2: /* VLD3 / VST3. */
17121 constraint (inst
.operands
[1].immisalign
,
17122 _("can't use alignment with this instruction"));
17125 case 3: /* VLD4 / VST4. */
17126 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17127 16, 64, 32, 64, 32, 128, -1);
17128 if (align_good
== FAIL
)
17132 unsigned alignbits
= 0;
17135 case 8: alignbits
= 0x1; break;
17136 case 16: alignbits
= 0x1; break;
17137 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17140 inst
.instruction
|= alignbits
<< 4;
17147 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17148 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17149 inst
.instruction
|= 1 << (4 + logsize
);
17151 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17152 inst
.instruction
|= logsize
<< 10;
17155 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17158 do_neon_ld_dup (void)
17160 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17161 int align_good
, do_alignment
= 0;
17163 if (et
.type
== NT_invtype
)
17166 switch ((inst
.instruction
>> 8) & 3)
17168 case 0: /* VLD1. */
17169 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17170 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17171 &do_alignment
, 16, 16, 32, 32, -1);
17172 if (align_good
== FAIL
)
17174 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17177 case 2: inst
.instruction
|= 1 << 5; break;
17178 default: first_error (_("bad list length")); return;
17180 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17183 case 1: /* VLD2. */
17184 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17185 &do_alignment
, 8, 16, 16, 32, 32, 64,
17187 if (align_good
== FAIL
)
17189 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17190 _("bad list length"));
17191 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17192 inst
.instruction
|= 1 << 5;
17193 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17196 case 2: /* VLD3. */
17197 constraint (inst
.operands
[1].immisalign
,
17198 _("can't use alignment with this instruction"));
17199 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17200 _("bad list length"));
17201 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17202 inst
.instruction
|= 1 << 5;
17203 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17206 case 3: /* VLD4. */
17208 int align
= inst
.operands
[1].imm
>> 8;
17209 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17210 16, 64, 32, 64, 32, 128, -1);
17211 if (align_good
== FAIL
)
17213 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17214 _("bad list length"));
17215 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17216 inst
.instruction
|= 1 << 5;
17217 if (et
.size
== 32 && align
== 128)
17218 inst
.instruction
|= 0x3 << 6;
17220 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17227 inst
.instruction
|= do_alignment
<< 4;
17230 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17231 apart from bits [11:4]. */
17234 do_neon_ldx_stx (void)
17236 if (inst
.operands
[1].isreg
)
17237 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17239 switch (NEON_LANE (inst
.operands
[0].imm
))
17241 case NEON_INTERLEAVE_LANES
:
17242 NEON_ENCODE (INTERLV
, inst
);
17243 do_neon_ld_st_interleave ();
17246 case NEON_ALL_LANES
:
17247 NEON_ENCODE (DUP
, inst
);
17248 if (inst
.instruction
== N_INV
)
17250 first_error ("only loads support such operands");
17257 NEON_ENCODE (LANE
, inst
);
17258 do_neon_ld_st_lane ();
17261 /* L bit comes from bit mask. */
17262 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17263 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17264 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17266 if (inst
.operands
[1].postind
)
17268 int postreg
= inst
.operands
[1].imm
& 0xf;
17269 constraint (!inst
.operands
[1].immisreg
,
17270 _("post-index must be a register"));
17271 constraint (postreg
== 0xd || postreg
== 0xf,
17272 _("bad register for post-index"));
17273 inst
.instruction
|= postreg
;
17277 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17278 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17279 || inst
.reloc
.exp
.X_add_number
!= 0,
17282 if (inst
.operands
[1].writeback
)
17284 inst
.instruction
|= 0xd;
17287 inst
.instruction
|= 0xf;
17291 inst
.instruction
|= 0xf9000000;
17293 inst
.instruction
|= 0xf4000000;
17298 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17300 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17301 D register operands. */
17302 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17306 NEON_ENCODE (FPV8
, inst
);
17308 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17310 do_vfp_sp_dyadic ();
17312 /* ARMv8.2 fp16 instruction. */
17314 do_scalar_fp16_v82_encode ();
17317 do_vfp_dp_rd_rn_rm ();
17320 inst
.instruction
|= 0x100;
17322 inst
.instruction
|= 0xf0000000;
17328 set_it_insn_type (OUTSIDE_IT_INSN
);
17330 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17331 first_error (_("invalid instruction shape"));
17337 set_it_insn_type (OUTSIDE_IT_INSN
);
17339 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17342 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17345 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17349 do_vrint_1 (enum neon_cvt_mode mode
)
17351 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17352 struct neon_type_el et
;
17357 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17358 D register operands. */
17359 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17360 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17363 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17365 if (et
.type
!= NT_invtype
)
17367 /* VFP encodings. */
17368 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17369 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17370 set_it_insn_type (OUTSIDE_IT_INSN
);
17372 NEON_ENCODE (FPV8
, inst
);
17373 if (rs
== NS_FF
|| rs
== NS_HH
)
17374 do_vfp_sp_monadic ();
17376 do_vfp_dp_rd_rm ();
17380 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17381 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17382 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17383 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17384 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17385 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17386 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17390 inst
.instruction
|= (rs
== NS_DD
) << 8;
17391 do_vfp_cond_or_thumb ();
17393 /* ARMv8.2 fp16 vrint instruction. */
17395 do_scalar_fp16_v82_encode ();
17399 /* Neon encodings (or something broken...). */
17401 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17403 if (et
.type
== NT_invtype
)
17406 set_it_insn_type (OUTSIDE_IT_INSN
);
17407 NEON_ENCODE (FLOAT
, inst
);
17409 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17412 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17414 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17415 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17416 inst
.instruction
|= neon_quad (rs
) << 6;
17417 /* Mask off the original size bits and reencode them. */
17418 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17419 | neon_logbits (et
.size
) << 18);
17423 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17424 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17425 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17426 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17427 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17428 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17429 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17434 inst
.instruction
|= 0xfc000000;
17436 inst
.instruction
|= 0xf0000000;
17443 do_vrint_1 (neon_cvt_mode_x
);
17449 do_vrint_1 (neon_cvt_mode_z
);
17455 do_vrint_1 (neon_cvt_mode_r
);
17461 do_vrint_1 (neon_cvt_mode_a
);
17467 do_vrint_1 (neon_cvt_mode_n
);
17473 do_vrint_1 (neon_cvt_mode_p
);
17479 do_vrint_1 (neon_cvt_mode_m
);
17483 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17485 unsigned regno
= NEON_SCALAR_REG (opnd
);
17486 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17488 if (elsize
== 16 && elno
< 2 && regno
< 16)
17489 return regno
| (elno
<< 4);
17490 else if (elsize
== 32 && elno
== 0)
17493 first_error (_("scalar out of range"));
17500 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17502 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17503 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17504 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17505 _("immediate out of range"));
17507 if (inst
.operands
[2].isscalar
)
17509 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17510 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17511 N_KEY
| N_F16
| N_F32
).size
;
17512 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17514 inst
.instruction
= 0xfe000800;
17515 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17516 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17517 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17518 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17519 inst
.instruction
|= LOW4 (m
);
17520 inst
.instruction
|= HI1 (m
) << 5;
17521 inst
.instruction
|= neon_quad (rs
) << 6;
17522 inst
.instruction
|= rot
<< 20;
17523 inst
.instruction
|= (size
== 32) << 23;
17527 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17528 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17529 N_KEY
| N_F16
| N_F32
).size
;
17530 neon_three_same (neon_quad (rs
), 0, -1);
17531 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17532 inst
.instruction
|= 0xfc200800;
17533 inst
.instruction
|= rot
<< 23;
17534 inst
.instruction
|= (size
== 32) << 20;
17541 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17543 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17544 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17545 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17546 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17547 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17548 N_KEY
| N_F16
| N_F32
).size
;
17549 neon_three_same (neon_quad (rs
), 0, -1);
17550 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17551 inst
.instruction
|= 0xfc800800;
17552 inst
.instruction
|= (rot
== 270) << 24;
17553 inst
.instruction
|= (size
== 32) << 20;
17556 /* Dot Product instructions encoding support. */
17559 do_neon_dotproduct (int unsigned_p
)
17561 enum neon_shape rs
;
17562 unsigned scalar_oprd2
= 0;
17565 if (inst
.cond
!= COND_ALWAYS
)
17566 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17567 "is UNPREDICTABLE"));
17569 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17572 /* Dot Product instructions are in three-same D/Q register format or the third
17573 operand can be a scalar index register. */
17574 if (inst
.operands
[2].isscalar
)
17576 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17577 high8
= 0xfe000000;
17578 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17582 high8
= 0xfc000000;
17583 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17587 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17589 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17591 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17592 Product instruction, so we pass 0 as the "ubit" parameter. And the
17593 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17594 neon_three_same (neon_quad (rs
), 0, 32);
17596 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17597 different NEON three-same encoding. */
17598 inst
.instruction
&= 0x00ffffff;
17599 inst
.instruction
|= high8
;
17600 /* Encode 'U' bit which indicates signedness. */
17601 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17602 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17603 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17604 the instruction encoding. */
17605 if (inst
.operands
[2].isscalar
)
17607 inst
.instruction
&= 0xffffffd0;
17608 inst
.instruction
|= LOW4 (scalar_oprd2
);
17609 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17613 /* Dot Product instructions for signed integer. */
17616 do_neon_dotproduct_s (void)
17618 return do_neon_dotproduct (0);
17621 /* Dot Product instructions for unsigned integer. */
17624 do_neon_dotproduct_u (void)
17626 return do_neon_dotproduct (1);
17629 /* Crypto v1 instructions. */
17631 do_crypto_2op_1 (unsigned elttype
, int op
)
17633 set_it_insn_type (OUTSIDE_IT_INSN
);
17635 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17641 NEON_ENCODE (INTEGER
, inst
);
17642 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17643 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17644 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17645 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17647 inst
.instruction
|= op
<< 6;
17650 inst
.instruction
|= 0xfc000000;
17652 inst
.instruction
|= 0xf0000000;
17656 do_crypto_3op_1 (int u
, int op
)
17658 set_it_insn_type (OUTSIDE_IT_INSN
);
17660 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17661 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17666 NEON_ENCODE (INTEGER
, inst
);
17667 neon_three_same (1, u
, 8 << op
);
17673 do_crypto_2op_1 (N_8
, 0);
17679 do_crypto_2op_1 (N_8
, 1);
17685 do_crypto_2op_1 (N_8
, 2);
17691 do_crypto_2op_1 (N_8
, 3);
17697 do_crypto_3op_1 (0, 0);
17703 do_crypto_3op_1 (0, 1);
17709 do_crypto_3op_1 (0, 2);
17715 do_crypto_3op_1 (0, 3);
17721 do_crypto_3op_1 (1, 0);
17727 do_crypto_3op_1 (1, 1);
17731 do_sha256su1 (void)
17733 do_crypto_3op_1 (1, 2);
17739 do_crypto_2op_1 (N_32
, -1);
17745 do_crypto_2op_1 (N_32
, 0);
17749 do_sha256su0 (void)
17751 do_crypto_2op_1 (N_32
, 1);
17755 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17757 unsigned int Rd
= inst
.operands
[0].reg
;
17758 unsigned int Rn
= inst
.operands
[1].reg
;
17759 unsigned int Rm
= inst
.operands
[2].reg
;
17761 set_it_insn_type (OUTSIDE_IT_INSN
);
17762 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17763 inst
.instruction
|= LOW4 (Rn
) << 16;
17764 inst
.instruction
|= LOW4 (Rm
);
17765 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17766 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17768 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17769 as_warn (UNPRED_REG ("r15"));
17811 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17813 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17814 do_vfp_sp_dp_cvt ();
17815 do_vfp_cond_or_thumb ();
17819 /* Overall per-instruction processing. */
17821 /* We need to be able to fix up arbitrary expressions in some statements.
17822 This is so that we can handle symbols that are an arbitrary distance from
17823 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17824 which returns part of an address in a form which will be valid for
17825 a data instruction. We do this by pushing the expression into a symbol
17826 in the expr_section, and creating a fix for that. */
17829 fix_new_arm (fragS
* frag
,
17843 /* Create an absolute valued symbol, so we have something to
17844 refer to in the object file. Unfortunately for us, gas's
17845 generic expression parsing will already have folded out
17846 any use of .set foo/.type foo %function that may have
17847 been used to set type information of the target location,
17848 that's being specified symbolically. We have to presume
17849 the user knows what they are doing. */
17853 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17855 symbol
= symbol_find_or_make (name
);
17856 S_SET_SEGMENT (symbol
, absolute_section
);
17857 symbol_set_frag (symbol
, &zero_address_frag
);
17858 S_SET_VALUE (symbol
, exp
->X_add_number
);
17859 exp
->X_op
= O_symbol
;
17860 exp
->X_add_symbol
= symbol
;
17861 exp
->X_add_number
= 0;
17867 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17868 (enum bfd_reloc_code_real
) reloc
);
17872 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17873 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17877 /* Mark whether the fix is to a THUMB instruction, or an ARM
17879 new_fix
->tc_fix_data
= thumb_mode
;
17882 /* Create a frg for an instruction requiring relaxation. */
17884 output_relax_insn (void)
17890 /* The size of the instruction is unknown, so tie the debug info to the
17891 start of the instruction. */
17892 dwarf2_emit_insn (0);
17894 switch (inst
.reloc
.exp
.X_op
)
17897 sym
= inst
.reloc
.exp
.X_add_symbol
;
17898 offset
= inst
.reloc
.exp
.X_add_number
;
17902 offset
= inst
.reloc
.exp
.X_add_number
;
17905 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17909 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17910 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17911 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17914 /* Write a 32-bit thumb instruction to buf. */
17916 put_thumb32_insn (char * buf
, unsigned long insn
)
17918 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17919 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17923 output_inst (const char * str
)
17929 as_bad ("%s -- `%s'", inst
.error
, str
);
17934 output_relax_insn ();
17937 if (inst
.size
== 0)
17940 to
= frag_more (inst
.size
);
17941 /* PR 9814: Record the thumb mode into the current frag so that we know
17942 what type of NOP padding to use, if necessary. We override any previous
17943 setting so that if the mode has changed then the NOPS that we use will
17944 match the encoding of the last instruction in the frag. */
17945 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17947 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17949 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17950 put_thumb32_insn (to
, inst
.instruction
);
17952 else if (inst
.size
> INSN_SIZE
)
17954 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17955 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17956 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17959 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17961 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17962 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17963 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17966 dwarf2_emit_insn (inst
.size
);
17970 output_it_inst (int cond
, int mask
, char * to
)
17972 unsigned long instruction
= 0xbf00;
17975 instruction
|= mask
;
17976 instruction
|= cond
<< 4;
17980 to
= frag_more (2);
17982 dwarf2_emit_insn (2);
17986 md_number_to_chars (to
, instruction
, 2);
17991 /* Tag values used in struct asm_opcode's tag field. */
17994 OT_unconditional
, /* Instruction cannot be conditionalized.
17995 The ARM condition field is still 0xE. */
17996 OT_unconditionalF
, /* Instruction cannot be conditionalized
17997 and carries 0xF in its ARM condition field. */
17998 OT_csuffix
, /* Instruction takes a conditional suffix. */
17999 OT_csuffixF
, /* Some forms of the instruction take a conditional
18000 suffix, others place 0xF where the condition field
18002 OT_cinfix3
, /* Instruction takes a conditional infix,
18003 beginning at character index 3. (In
18004 unified mode, it becomes a suffix.) */
18005 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18006 tsts, cmps, cmns, and teqs. */
18007 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18008 character index 3, even in unified mode. Used for
18009 legacy instructions where suffix and infix forms
18010 may be ambiguous. */
18011 OT_csuf_or_in3
, /* Instruction takes either a conditional
18012 suffix or an infix at character index 3. */
18013 OT_odd_infix_unc
, /* This is the unconditional variant of an
18014 instruction that takes a conditional infix
18015 at an unusual position. In unified mode,
18016 this variant will accept a suffix. */
18017 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18018 are the conditional variants of instructions that
18019 take conditional infixes in unusual positions.
18020 The infix appears at character index
18021 (tag - OT_odd_infix_0). These are not accepted
18022 in unified mode. */
18025 /* Subroutine of md_assemble, responsible for looking up the primary
18026 opcode from the mnemonic the user wrote. STR points to the
18027 beginning of the mnemonic.
18029 This is not simply a hash table lookup, because of conditional
18030 variants. Most instructions have conditional variants, which are
18031 expressed with a _conditional affix_ to the mnemonic. If we were
18032 to encode each conditional variant as a literal string in the opcode
18033 table, it would have approximately 20,000 entries.
18035 Most mnemonics take this affix as a suffix, and in unified syntax,
18036 'most' is upgraded to 'all'. However, in the divided syntax, some
18037 instructions take the affix as an infix, notably the s-variants of
18038 the arithmetic instructions. Of those instructions, all but six
18039 have the infix appear after the third character of the mnemonic.
18041 Accordingly, the algorithm for looking up primary opcodes given
18044 1. Look up the identifier in the opcode table.
18045 If we find a match, go to step U.
18047 2. Look up the last two characters of the identifier in the
18048 conditions table. If we find a match, look up the first N-2
18049 characters of the identifier in the opcode table. If we
18050 find a match, go to step CE.
18052 3. Look up the fourth and fifth characters of the identifier in
18053 the conditions table. If we find a match, extract those
18054 characters from the identifier, and look up the remaining
18055 characters in the opcode table. If we find a match, go
18060 U. Examine the tag field of the opcode structure, in case this is
18061 one of the six instructions with its conditional infix in an
18062 unusual place. If it is, the tag tells us where to find the
18063 infix; look it up in the conditions table and set inst.cond
18064 accordingly. Otherwise, this is an unconditional instruction.
18065 Again set inst.cond accordingly. Return the opcode structure.
18067 CE. Examine the tag field to make sure this is an instruction that
18068 should receive a conditional suffix. If it is not, fail.
18069 Otherwise, set inst.cond from the suffix we already looked up,
18070 and return the opcode structure.
18072 CM. Examine the tag field to make sure this is an instruction that
18073 should receive a conditional infix after the third character.
18074 If it is not, fail. Otherwise, undo the edits to the current
18075 line of input and proceed as for case CE. */
18077 static const struct asm_opcode
*
18078 opcode_lookup (char **str
)
18082 const struct asm_opcode
*opcode
;
18083 const struct asm_cond
*cond
;
18086 /* Scan up to the end of the mnemonic, which must end in white space,
18087 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18088 for (base
= end
= *str
; *end
!= '\0'; end
++)
18089 if (*end
== ' ' || *end
== '.')
18095 /* Handle a possible width suffix and/or Neon type suffix. */
18100 /* The .w and .n suffixes are only valid if the unified syntax is in
18102 if (unified_syntax
&& end
[1] == 'w')
18104 else if (unified_syntax
&& end
[1] == 'n')
18109 inst
.vectype
.elems
= 0;
18111 *str
= end
+ offset
;
18113 if (end
[offset
] == '.')
18115 /* See if we have a Neon type suffix (possible in either unified or
18116 non-unified ARM syntax mode). */
18117 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18120 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18126 /* Look for unaffixed or special-case affixed mnemonic. */
18127 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18132 if (opcode
->tag
< OT_odd_infix_0
)
18134 inst
.cond
= COND_ALWAYS
;
18138 if (warn_on_deprecated
&& unified_syntax
)
18139 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18140 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18141 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18144 inst
.cond
= cond
->value
;
18148 /* Cannot have a conditional suffix on a mnemonic of less than two
18150 if (end
- base
< 3)
18153 /* Look for suffixed mnemonic. */
18155 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18156 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18158 if (opcode
&& cond
)
18161 switch (opcode
->tag
)
18163 case OT_cinfix3_legacy
:
18164 /* Ignore conditional suffixes matched on infix only mnemonics. */
18168 case OT_cinfix3_deprecated
:
18169 case OT_odd_infix_unc
:
18170 if (!unified_syntax
)
18172 /* Fall through. */
18176 case OT_csuf_or_in3
:
18177 inst
.cond
= cond
->value
;
18180 case OT_unconditional
:
18181 case OT_unconditionalF
:
18183 inst
.cond
= cond
->value
;
18186 /* Delayed diagnostic. */
18187 inst
.error
= BAD_COND
;
18188 inst
.cond
= COND_ALWAYS
;
18197 /* Cannot have a usual-position infix on a mnemonic of less than
18198 six characters (five would be a suffix). */
18199 if (end
- base
< 6)
18202 /* Look for infixed mnemonic in the usual position. */
18204 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18208 memcpy (save
, affix
, 2);
18209 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18210 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18212 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18213 memcpy (affix
, save
, 2);
18216 && (opcode
->tag
== OT_cinfix3
18217 || opcode
->tag
== OT_cinfix3_deprecated
18218 || opcode
->tag
== OT_csuf_or_in3
18219 || opcode
->tag
== OT_cinfix3_legacy
))
18222 if (warn_on_deprecated
&& unified_syntax
18223 && (opcode
->tag
== OT_cinfix3
18224 || opcode
->tag
== OT_cinfix3_deprecated
))
18225 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18227 inst
.cond
= cond
->value
;
18234 /* This function generates an initial IT instruction, leaving its block
18235 virtually open for the new instructions. Eventually,
18236 the mask will be updated by now_it_add_mask () each time
18237 a new instruction needs to be included in the IT block.
18238 Finally, the block is closed with close_automatic_it_block ().
18239 The block closure can be requested either from md_assemble (),
18240 a tencode (), or due to a label hook. */
18243 new_automatic_it_block (int cond
)
18245 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18246 now_it
.mask
= 0x18;
18248 now_it
.block_length
= 1;
18249 mapping_state (MAP_THUMB
);
18250 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18251 now_it
.warn_deprecated
= FALSE
;
18252 now_it
.insn_cond
= TRUE
;
18255 /* Close an automatic IT block.
18256 See comments in new_automatic_it_block (). */
18259 close_automatic_it_block (void)
18261 now_it
.mask
= 0x10;
18262 now_it
.block_length
= 0;
18265 /* Update the mask of the current automatically-generated IT
18266 instruction. See comments in new_automatic_it_block (). */
18269 now_it_add_mask (int cond
)
18271 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18272 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18273 | ((bitvalue) << (nbit)))
18274 const int resulting_bit
= (cond
& 1);
18276 now_it
.mask
&= 0xf;
18277 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18279 (5 - now_it
.block_length
));
18280 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18282 ((5 - now_it
.block_length
) - 1) );
18283 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18286 #undef SET_BIT_VALUE
18289 /* The IT blocks handling machinery is accessed through the these functions:
18290 it_fsm_pre_encode () from md_assemble ()
18291 set_it_insn_type () optional, from the tencode functions
18292 set_it_insn_type_last () ditto
18293 in_it_block () ditto
18294 it_fsm_post_encode () from md_assemble ()
18295 force_automatic_it_block_close () from label handling functions
18298 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18299 initializing the IT insn type with a generic initial value depending
18300 on the inst.condition.
18301 2) During the tencode function, two things may happen:
18302 a) The tencode function overrides the IT insn type by
18303 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18304 b) The tencode function queries the IT block state by
18305 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18307 Both set_it_insn_type and in_it_block run the internal FSM state
18308 handling function (handle_it_state), because: a) setting the IT insn
18309 type may incur in an invalid state (exiting the function),
18310 and b) querying the state requires the FSM to be updated.
18311 Specifically we want to avoid creating an IT block for conditional
18312 branches, so it_fsm_pre_encode is actually a guess and we can't
18313 determine whether an IT block is required until the tencode () routine
18314 has decided what type of instruction this actually it.
18315 Because of this, if set_it_insn_type and in_it_block have to be used,
18316 set_it_insn_type has to be called first.
18318 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18319 determines the insn IT type depending on the inst.cond code.
18320 When a tencode () routine encodes an instruction that can be
18321 either outside an IT block, or, in the case of being inside, has to be
18322 the last one, set_it_insn_type_last () will determine the proper
18323 IT instruction type based on the inst.cond code. Otherwise,
18324 set_it_insn_type can be called for overriding that logic or
18325 for covering other cases.
18327 Calling handle_it_state () may not transition the IT block state to
18328 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18329 still queried. Instead, if the FSM determines that the state should
18330 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18331 after the tencode () function: that's what it_fsm_post_encode () does.
18333 Since in_it_block () calls the state handling function to get an
18334 updated state, an error may occur (due to invalid insns combination).
18335 In that case, inst.error is set.
18336 Therefore, inst.error has to be checked after the execution of
18337 the tencode () routine.
18339 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18340 any pending state change (if any) that didn't take place in
18341 handle_it_state () as explained above. */
18344 it_fsm_pre_encode (void)
18346 if (inst
.cond
!= COND_ALWAYS
)
18347 inst
.it_insn_type
= INSIDE_IT_INSN
;
18349 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18351 now_it
.state_handled
= 0;
18354 /* IT state FSM handling function. */
18357 handle_it_state (void)
18359 now_it
.state_handled
= 1;
18360 now_it
.insn_cond
= FALSE
;
18362 switch (now_it
.state
)
18364 case OUTSIDE_IT_BLOCK
:
18365 switch (inst
.it_insn_type
)
18367 case OUTSIDE_IT_INSN
:
18370 case INSIDE_IT_INSN
:
18371 case INSIDE_IT_LAST_INSN
:
18372 if (thumb_mode
== 0)
18375 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18376 as_tsktsk (_("Warning: conditional outside an IT block"\
18381 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18382 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18384 /* Automatically generate the IT instruction. */
18385 new_automatic_it_block (inst
.cond
);
18386 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18387 close_automatic_it_block ();
18391 inst
.error
= BAD_OUT_IT
;
18397 case IF_INSIDE_IT_LAST_INSN
:
18398 case NEUTRAL_IT_INSN
:
18402 now_it
.state
= MANUAL_IT_BLOCK
;
18403 now_it
.block_length
= 0;
18408 case AUTOMATIC_IT_BLOCK
:
18409 /* Three things may happen now:
18410 a) We should increment current it block size;
18411 b) We should close current it block (closing insn or 4 insns);
18412 c) We should close current it block and start a new one (due
18413 to incompatible conditions or
18414 4 insns-length block reached). */
18416 switch (inst
.it_insn_type
)
18418 case OUTSIDE_IT_INSN
:
18419 /* The closure of the block shall happen immediately,
18420 so any in_it_block () call reports the block as closed. */
18421 force_automatic_it_block_close ();
18424 case INSIDE_IT_INSN
:
18425 case INSIDE_IT_LAST_INSN
:
18426 case IF_INSIDE_IT_LAST_INSN
:
18427 now_it
.block_length
++;
18429 if (now_it
.block_length
> 4
18430 || !now_it_compatible (inst
.cond
))
18432 force_automatic_it_block_close ();
18433 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18434 new_automatic_it_block (inst
.cond
);
18438 now_it
.insn_cond
= TRUE
;
18439 now_it_add_mask (inst
.cond
);
18442 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18443 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18444 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18445 close_automatic_it_block ();
18448 case NEUTRAL_IT_INSN
:
18449 now_it
.block_length
++;
18450 now_it
.insn_cond
= TRUE
;
18452 if (now_it
.block_length
> 4)
18453 force_automatic_it_block_close ();
18455 now_it_add_mask (now_it
.cc
& 1);
18459 close_automatic_it_block ();
18460 now_it
.state
= MANUAL_IT_BLOCK
;
18465 case MANUAL_IT_BLOCK
:
18467 /* Check conditional suffixes. */
18468 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18471 now_it
.mask
&= 0x1f;
18472 is_last
= (now_it
.mask
== 0x10);
18473 now_it
.insn_cond
= TRUE
;
18475 switch (inst
.it_insn_type
)
18477 case OUTSIDE_IT_INSN
:
18478 inst
.error
= BAD_NOT_IT
;
18481 case INSIDE_IT_INSN
:
18482 if (cond
!= inst
.cond
)
18484 inst
.error
= BAD_IT_COND
;
18489 case INSIDE_IT_LAST_INSN
:
18490 case IF_INSIDE_IT_LAST_INSN
:
18491 if (cond
!= inst
.cond
)
18493 inst
.error
= BAD_IT_COND
;
18498 inst
.error
= BAD_BRANCH
;
18503 case NEUTRAL_IT_INSN
:
18504 /* The BKPT instruction is unconditional even in an IT block. */
18508 inst
.error
= BAD_IT_IT
;
18518 struct depr_insn_mask
18520 unsigned long pattern
;
18521 unsigned long mask
;
18522 const char* description
;
18525 /* List of 16-bit instruction patterns deprecated in an IT block in
18527 static const struct depr_insn_mask depr_it_insns
[] = {
18528 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18529 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18530 { 0xa000, 0xb800, N_("ADR") },
18531 { 0x4800, 0xf800, N_("Literal loads") },
18532 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18533 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18534 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18535 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18536 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18541 it_fsm_post_encode (void)
18545 if (!now_it
.state_handled
)
18546 handle_it_state ();
18548 if (now_it
.insn_cond
18549 && !now_it
.warn_deprecated
18550 && warn_on_deprecated
18551 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18553 if (inst
.instruction
>= 0x10000)
18555 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18556 "deprecated in ARMv8"));
18557 now_it
.warn_deprecated
= TRUE
;
18561 const struct depr_insn_mask
*p
= depr_it_insns
;
18563 while (p
->mask
!= 0)
18565 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18567 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18568 "of the following class are deprecated in ARMv8: "
18569 "%s"), p
->description
);
18570 now_it
.warn_deprecated
= TRUE
;
18578 if (now_it
.block_length
> 1)
18580 as_tsktsk (_("IT blocks containing more than one conditional "
18581 "instruction are deprecated in ARMv8"));
18582 now_it
.warn_deprecated
= TRUE
;
18586 is_last
= (now_it
.mask
== 0x10);
18589 now_it
.state
= OUTSIDE_IT_BLOCK
;
18595 force_automatic_it_block_close (void)
18597 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18599 close_automatic_it_block ();
18600 now_it
.state
= OUTSIDE_IT_BLOCK
;
18608 if (!now_it
.state_handled
)
18609 handle_it_state ();
18611 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18614 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18615 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18616 here, hence the "known" in the function name. */
18619 known_t32_only_insn (const struct asm_opcode
*opcode
)
18621 /* Original Thumb-1 wide instruction. */
18622 if (opcode
->tencode
== do_t_blx
18623 || opcode
->tencode
== do_t_branch23
18624 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18625 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18628 /* Wide-only instruction added to ARMv8-M Baseline. */
18629 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18630 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18631 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18632 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18638 /* Whether wide instruction variant can be used if available for a valid OPCODE
18642 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18644 if (known_t32_only_insn (opcode
))
18647 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18648 of variant T3 of B.W is checked in do_t_branch. */
18649 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18650 && opcode
->tencode
== do_t_branch
)
18653 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18654 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18655 && opcode
->tencode
== do_t_mov_cmp
18656 /* Make sure CMP instruction is not affected. */
18657 && opcode
->aencode
== do_mov
)
18660 /* Wide instruction variants of all instructions with narrow *and* wide
18661 variants become available with ARMv6t2. Other opcodes are either
18662 narrow-only or wide-only and are thus available if OPCODE is valid. */
18663 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18666 /* OPCODE with narrow only instruction variant or wide variant not
18672 md_assemble (char *str
)
18675 const struct asm_opcode
* opcode
;
18677 /* Align the previous label if needed. */
18678 if (last_label_seen
!= NULL
)
18680 symbol_set_frag (last_label_seen
, frag_now
);
18681 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18682 S_SET_SEGMENT (last_label_seen
, now_seg
);
18685 memset (&inst
, '\0', sizeof (inst
));
18686 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18688 opcode
= opcode_lookup (&p
);
18691 /* It wasn't an instruction, but it might be a register alias of
18692 the form alias .req reg, or a Neon .dn/.qn directive. */
18693 if (! create_register_alias (str
, p
)
18694 && ! create_neon_reg_alias (str
, p
))
18695 as_bad (_("bad instruction `%s'"), str
);
18700 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18701 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18703 /* The value which unconditional instructions should have in place of the
18704 condition field. */
18705 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18709 arm_feature_set variant
;
18711 variant
= cpu_variant
;
18712 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18713 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18714 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18715 /* Check that this instruction is supported for this CPU. */
18716 if (!opcode
->tvariant
18717 || (thumb_mode
== 1
18718 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18720 if (opcode
->tencode
== do_t_swi
)
18721 as_bad (_("SVC is not permitted on this architecture"));
18723 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18726 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18727 && opcode
->tencode
!= do_t_branch
)
18729 as_bad (_("Thumb does not support conditional execution"));
18733 /* Two things are addressed here:
18734 1) Implicit require narrow instructions on Thumb-1.
18735 This avoids relaxation accidentally introducing Thumb-2
18737 2) Reject wide instructions in non Thumb-2 cores.
18739 Only instructions with narrow and wide variants need to be handled
18740 but selecting all non wide-only instructions is easier. */
18741 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18742 && !t32_insn_ok (variant
, opcode
))
18744 if (inst
.size_req
== 0)
18746 else if (inst
.size_req
== 4)
18748 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18749 as_bad (_("selected processor does not support 32bit wide "
18750 "variant of instruction `%s'"), str
);
18752 as_bad (_("selected processor does not support `%s' in "
18753 "Thumb-2 mode"), str
);
18758 inst
.instruction
= opcode
->tvalue
;
18760 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18762 /* Prepare the it_insn_type for those encodings that don't set
18764 it_fsm_pre_encode ();
18766 opcode
->tencode ();
18768 it_fsm_post_encode ();
18771 if (!(inst
.error
|| inst
.relax
))
18773 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18774 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18775 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18777 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18782 /* Something has gone badly wrong if we try to relax a fixed size
18784 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18786 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18787 *opcode
->tvariant
);
18788 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18789 set those bits when Thumb-2 32-bit instructions are seen. The impact
18790 of relaxable instructions will be considered later after we finish all
18792 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18793 variant
= arm_arch_none
;
18795 variant
= cpu_variant
;
18796 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18797 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18800 check_neon_suffixes
;
18804 mapping_state (MAP_THUMB
);
18807 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18811 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18812 is_bx
= (opcode
->aencode
== do_bx
);
18814 /* Check that this instruction is supported for this CPU. */
18815 if (!(is_bx
&& fix_v4bx
)
18816 && !(opcode
->avariant
&&
18817 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18819 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18824 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18828 inst
.instruction
= opcode
->avalue
;
18829 if (opcode
->tag
== OT_unconditionalF
)
18830 inst
.instruction
|= 0xFU
<< 28;
18832 inst
.instruction
|= inst
.cond
<< 28;
18833 inst
.size
= INSN_SIZE
;
18834 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18836 it_fsm_pre_encode ();
18837 opcode
->aencode ();
18838 it_fsm_post_encode ();
18840 /* Arm mode bx is marked as both v4T and v5 because it's still required
18841 on a hypothetical non-thumb v5 core. */
18843 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18845 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18846 *opcode
->avariant
);
18848 check_neon_suffixes
;
18852 mapping_state (MAP_ARM
);
18857 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18865 check_it_blocks_finished (void)
18870 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18871 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18872 == MANUAL_IT_BLOCK
)
18874 as_warn (_("section '%s' finished with an open IT block."),
18878 if (now_it
.state
== MANUAL_IT_BLOCK
)
18879 as_warn (_("file finished with an open IT block."));
18883 /* Various frobbings of labels and their addresses. */
18886 arm_start_line_hook (void)
18888 last_label_seen
= NULL
;
18892 arm_frob_label (symbolS
* sym
)
18894 last_label_seen
= sym
;
18896 ARM_SET_THUMB (sym
, thumb_mode
);
18898 #if defined OBJ_COFF || defined OBJ_ELF
18899 ARM_SET_INTERWORK (sym
, support_interwork
);
18902 force_automatic_it_block_close ();
18904 /* Note - do not allow local symbols (.Lxxx) to be labelled
18905 as Thumb functions. This is because these labels, whilst
18906 they exist inside Thumb code, are not the entry points for
18907 possible ARM->Thumb calls. Also, these labels can be used
18908 as part of a computed goto or switch statement. eg gcc
18909 can generate code that looks like this:
18911 ldr r2, [pc, .Laaa]
18921 The first instruction loads the address of the jump table.
18922 The second instruction converts a table index into a byte offset.
18923 The third instruction gets the jump address out of the table.
18924 The fourth instruction performs the jump.
18926 If the address stored at .Laaa is that of a symbol which has the
18927 Thumb_Func bit set, then the linker will arrange for this address
18928 to have the bottom bit set, which in turn would mean that the
18929 address computation performed by the third instruction would end
18930 up with the bottom bit set. Since the ARM is capable of unaligned
18931 word loads, the instruction would then load the incorrect address
18932 out of the jump table, and chaos would ensue. */
18933 if (label_is_thumb_function_name
18934 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18935 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18937 /* When the address of a Thumb function is taken the bottom
18938 bit of that address should be set. This will allow
18939 interworking between Arm and Thumb functions to work
18942 THUMB_SET_FUNC (sym
, 1);
18944 label_is_thumb_function_name
= FALSE
;
18947 dwarf2_emit_label (sym
);
18951 arm_data_in_code (void)
18953 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18955 *input_line_pointer
= '/';
18956 input_line_pointer
+= 5;
18957 *input_line_pointer
= 0;
18965 arm_canonicalize_symbol_name (char * name
)
18969 if (thumb_mode
&& (len
= strlen (name
)) > 5
18970 && streq (name
+ len
- 5, "/data"))
18971 *(name
+ len
- 5) = 0;
18976 /* Table of all register names defined by default. The user can
18977 define additional names with .req. Note that all register names
18978 should appear in both upper and lowercase variants. Some registers
18979 also have mixed-case names. */
18981 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18982 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18983 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18984 #define REGSET(p,t) \
18985 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18986 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18987 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18988 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18989 #define REGSETH(p,t) \
18990 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18991 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18992 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18993 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18994 #define REGSET2(p,t) \
18995 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18996 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18997 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18998 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18999 #define SPLRBANK(base,bank,t) \
19000 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19001 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19002 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19003 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19004 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19005 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19007 static const struct reg_entry reg_names
[] =
19009 /* ARM integer registers. */
19010 REGSET(r
, RN
), REGSET(R
, RN
),
19012 /* ATPCS synonyms. */
19013 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19014 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19015 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19017 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19018 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19019 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19021 /* Well-known aliases. */
19022 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19023 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19025 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19026 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19028 /* Coprocessor numbers. */
19029 REGSET(p
, CP
), REGSET(P
, CP
),
19031 /* Coprocessor register numbers. The "cr" variants are for backward
19033 REGSET(c
, CN
), REGSET(C
, CN
),
19034 REGSET(cr
, CN
), REGSET(CR
, CN
),
19036 /* ARM banked registers. */
19037 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19038 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19039 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19040 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19041 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19042 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19043 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19045 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19046 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19047 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19048 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19049 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19050 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19051 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19052 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19054 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19055 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19056 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19057 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19058 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19059 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19060 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19061 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19062 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19064 /* FPA registers. */
19065 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19066 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19068 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19069 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19071 /* VFP SP registers. */
19072 REGSET(s
,VFS
), REGSET(S
,VFS
),
19073 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19075 /* VFP DP Registers. */
19076 REGSET(d
,VFD
), REGSET(D
,VFD
),
19077 /* Extra Neon DP registers. */
19078 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19080 /* Neon QP registers. */
19081 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19083 /* VFP control registers. */
19084 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19085 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19086 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19087 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19088 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19089 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19090 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19092 /* Maverick DSP coprocessor registers. */
19093 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19094 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19096 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19097 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19098 REGDEF(dspsc
,0,DSPSC
),
19100 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19101 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19102 REGDEF(DSPSC
,0,DSPSC
),
19104 /* iWMMXt data registers - p0, c0-15. */
19105 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19107 /* iWMMXt control registers - p1, c0-3. */
19108 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19109 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19110 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19111 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19113 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19114 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19115 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19116 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19117 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19119 /* XScale accumulator registers. */
19120 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19126 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19127 within psr_required_here. */
19128 static const struct asm_psr psrs
[] =
19130 /* Backward compatibility notation. Note that "all" is no longer
19131 truly all possible PSR bits. */
19132 {"all", PSR_c
| PSR_f
},
19136 /* Individual flags. */
19142 /* Combinations of flags. */
19143 {"fs", PSR_f
| PSR_s
},
19144 {"fx", PSR_f
| PSR_x
},
19145 {"fc", PSR_f
| PSR_c
},
19146 {"sf", PSR_s
| PSR_f
},
19147 {"sx", PSR_s
| PSR_x
},
19148 {"sc", PSR_s
| PSR_c
},
19149 {"xf", PSR_x
| PSR_f
},
19150 {"xs", PSR_x
| PSR_s
},
19151 {"xc", PSR_x
| PSR_c
},
19152 {"cf", PSR_c
| PSR_f
},
19153 {"cs", PSR_c
| PSR_s
},
19154 {"cx", PSR_c
| PSR_x
},
19155 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19156 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19157 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19158 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19159 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19160 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19161 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19162 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19163 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19164 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19165 {"scf", PSR_s
| PSR_c
| PSR_f
},
19166 {"scx", PSR_s
| PSR_c
| PSR_x
},
19167 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19168 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19169 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19170 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19171 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19172 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19173 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19174 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19175 {"csf", PSR_c
| PSR_s
| PSR_f
},
19176 {"csx", PSR_c
| PSR_s
| PSR_x
},
19177 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19178 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19179 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19180 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19181 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19182 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19183 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19184 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19185 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19186 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19187 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19188 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19189 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19190 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19191 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19192 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19193 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19194 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19195 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19196 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19197 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19198 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19199 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19200 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19201 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19202 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19205 /* Table of V7M psr names. */
19206 static const struct asm_psr v7m_psrs
[] =
19208 {"apsr", 0x0 }, {"APSR", 0x0 },
19209 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19210 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19211 {"psr", 0x3 }, {"PSR", 0x3 },
19212 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19213 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19214 {"epsr", 0x6 }, {"EPSR", 0x6 },
19215 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19216 {"msp", 0x8 }, {"MSP", 0x8 },
19217 {"psp", 0x9 }, {"PSP", 0x9 },
19218 {"msplim", 0xa }, {"MSPLIM", 0xa },
19219 {"psplim", 0xb }, {"PSPLIM", 0xb },
19220 {"primask", 0x10}, {"PRIMASK", 0x10},
19221 {"basepri", 0x11}, {"BASEPRI", 0x11},
19222 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19223 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19224 {"control", 0x14}, {"CONTROL", 0x14},
19225 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19226 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19227 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19228 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19229 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19230 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19231 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19232 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19233 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19236 /* Table of all shift-in-operand names. */
19237 static const struct asm_shift_name shift_names
[] =
19239 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19240 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19241 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19242 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19243 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19244 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19247 /* Table of all explicit relocation names. */
19249 static struct reloc_entry reloc_names
[] =
19251 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19252 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19253 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19254 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19255 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19256 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19257 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19258 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19259 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19260 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19261 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19262 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19263 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19264 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19265 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19266 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19267 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19268 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19272 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19273 static const struct asm_cond conds
[] =
19277 {"cs", 0x2}, {"hs", 0x2},
19278 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19292 #define UL_BARRIER(L,U,CODE,FEAT) \
19293 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19294 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19296 static struct asm_barrier_opt barrier_opt_names
[] =
19298 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19299 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19300 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19301 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19302 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19303 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19304 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19305 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19306 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19307 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19308 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19309 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19310 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19311 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19312 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19313 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19318 /* Table of ARM-format instructions. */
19320 /* Macros for gluing together operand strings. N.B. In all cases
19321 other than OPS0, the trailing OP_stop comes from default
19322 zero-initialization of the unspecified elements of the array. */
19323 #define OPS0() { OP_stop, }
19324 #define OPS1(a) { OP_##a, }
19325 #define OPS2(a,b) { OP_##a,OP_##b, }
19326 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19327 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19328 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19329 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19331 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19332 This is useful when mixing operands for ARM and THUMB, i.e. using the
19333 MIX_ARM_THUMB_OPERANDS macro.
19334 In order to use these macros, prefix the number of operands with _
19336 #define OPS_1(a) { a, }
19337 #define OPS_2(a,b) { a,b, }
19338 #define OPS_3(a,b,c) { a,b,c, }
19339 #define OPS_4(a,b,c,d) { a,b,c,d, }
19340 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19341 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19343 /* These macros abstract out the exact format of the mnemonic table and
19344 save some repeated characters. */
19346 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19347 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19348 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19349 THUMB_VARIANT, do_##ae, do_##te }
19351 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19352 a T_MNEM_xyz enumerator. */
19353 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19354 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19355 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19356 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19358 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19359 infix after the third character. */
19360 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19361 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19362 THUMB_VARIANT, do_##ae, do_##te }
19363 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19364 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19365 THUMB_VARIANT, do_##ae, do_##te }
19366 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19367 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19368 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19369 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19370 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19371 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19372 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19373 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19375 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19376 field is still 0xE. Many of the Thumb variants can be executed
19377 conditionally, so this is checked separately. */
19378 #define TUE(mnem, op, top, nops, ops, ae, te) \
19379 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19380 THUMB_VARIANT, do_##ae, do_##te }
19382 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19383 Used by mnemonics that have very minimal differences in the encoding for
19384 ARM and Thumb variants and can be handled in a common function. */
19385 #define TUEc(mnem, op, top, nops, ops, en) \
19386 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19387 THUMB_VARIANT, do_##en, do_##en }
19389 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19390 condition code field. */
19391 #define TUF(mnem, op, top, nops, ops, ae, te) \
19392 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19393 THUMB_VARIANT, do_##ae, do_##te }
19395 /* ARM-only variants of all the above. */
19396 #define CE(mnem, op, nops, ops, ae) \
19397 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19399 #define C3(mnem, op, nops, ops, ae) \
19400 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19402 /* Legacy mnemonics that always have conditional infix after the third
19404 #define CL(mnem, op, nops, ops, ae) \
19405 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19406 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19408 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19409 #define cCE(mnem, op, nops, ops, ae) \
19410 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19412 /* Legacy coprocessor instructions where conditional infix and conditional
19413 suffix are ambiguous. For consistency this includes all FPA instructions,
19414 not just the potentially ambiguous ones. */
19415 #define cCL(mnem, op, nops, ops, ae) \
19416 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19417 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19419 /* Coprocessor, takes either a suffix or a position-3 infix
19420 (for an FPA corner case). */
19421 #define C3E(mnem, op, nops, ops, ae) \
19422 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19423 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19425 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19426 { m1 #m2 m3, OPS##nops ops, \
19427 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19428 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19430 #define CM(m1, m2, op, nops, ops, ae) \
19431 xCM_ (m1, , m2, op, nops, ops, ae), \
19432 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19433 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19434 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19435 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19436 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19437 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19438 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19439 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19440 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19441 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19442 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19443 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19444 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19445 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19446 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19447 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19448 xCM_ (m1, le, m2, op, nops, ops, ae), \
19449 xCM_ (m1, al, m2, op, nops, ops, ae)
19451 #define UE(mnem, op, nops, ops, ae) \
19452 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19454 #define UF(mnem, op, nops, ops, ae) \
19455 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19457 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19458 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19459 use the same encoding function for each. */
19460 #define NUF(mnem, op, nops, ops, enc) \
19461 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19462 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19464 /* Neon data processing, version which indirects through neon_enc_tab for
19465 the various overloaded versions of opcodes. */
19466 #define nUF(mnem, op, nops, ops, enc) \
19467 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19468 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19470 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19472 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19473 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19474 THUMB_VARIANT, do_##enc, do_##enc }
19476 #define NCE(mnem, op, nops, ops, enc) \
19477 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19479 #define NCEF(mnem, op, nops, ops, enc) \
19480 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19482 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19483 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19484 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19485 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19487 #define nCE(mnem, op, nops, ops, enc) \
19488 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19490 #define nCEF(mnem, op, nops, ops, enc) \
19491 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19495 static const struct asm_opcode insns
[] =
19497 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19498 #define THUMB_VARIANT & arm_ext_v4t
19499 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19500 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19501 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19502 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19503 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19504 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19505 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19506 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19507 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19508 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19509 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19510 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19511 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19512 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19513 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19514 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19516 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19517 for setting PSR flag bits. They are obsolete in V6 and do not
19518 have Thumb equivalents. */
19519 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19520 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19521 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19522 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19523 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19524 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19525 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19526 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19527 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19529 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19530 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19531 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19532 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19534 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19535 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19536 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19538 OP_ADDRGLDR
),ldst
, t_ldst
),
19539 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19541 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19542 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19543 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19544 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19545 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19546 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19548 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19549 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19552 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19553 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19554 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19555 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19557 /* Thumb-compatibility pseudo ops. */
19558 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19559 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19560 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19561 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19562 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19563 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19564 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19565 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19566 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19567 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19568 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19569 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19571 /* These may simplify to neg. */
19572 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19573 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19575 #undef THUMB_VARIANT
19576 #define THUMB_VARIANT & arm_ext_os
19578 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19579 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19581 #undef THUMB_VARIANT
19582 #define THUMB_VARIANT & arm_ext_v6
19584 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19586 /* V1 instructions with no Thumb analogue prior to V6T2. */
19587 #undef THUMB_VARIANT
19588 #define THUMB_VARIANT & arm_ext_v6t2
19590 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19591 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19592 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19594 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19595 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19596 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19597 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19599 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19600 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19602 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19603 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19605 /* V1 instructions with no Thumb analogue at all. */
19606 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19607 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19609 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19610 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19611 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19612 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19613 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19614 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19615 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19616 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19619 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19620 #undef THUMB_VARIANT
19621 #define THUMB_VARIANT & arm_ext_v4t
19623 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19624 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19626 #undef THUMB_VARIANT
19627 #define THUMB_VARIANT & arm_ext_v6t2
19629 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19630 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19632 /* Generic coprocessor instructions. */
19633 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19634 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19635 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19636 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19637 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19638 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19639 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19642 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19644 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19645 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19648 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19649 #undef THUMB_VARIANT
19650 #define THUMB_VARIANT & arm_ext_msr
19652 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19653 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19656 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19657 #undef THUMB_VARIANT
19658 #define THUMB_VARIANT & arm_ext_v6t2
19660 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19661 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19662 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19663 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19664 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19665 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19666 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19667 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19670 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19671 #undef THUMB_VARIANT
19672 #define THUMB_VARIANT & arm_ext_v4t
19674 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19675 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19676 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19677 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19678 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19679 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19682 #define ARM_VARIANT & arm_ext_v4t_5
19684 /* ARM Architecture 4T. */
19685 /* Note: bx (and blx) are required on V5, even if the processor does
19686 not support Thumb. */
19687 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19690 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19691 #undef THUMB_VARIANT
19692 #define THUMB_VARIANT & arm_ext_v5t
19694 /* Note: blx has 2 variants; the .value coded here is for
19695 BLX(2). Only this variant has conditional execution. */
19696 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19697 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19699 #undef THUMB_VARIANT
19700 #define THUMB_VARIANT & arm_ext_v6t2
19702 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19703 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19704 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19705 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19706 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19707 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19708 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19709 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19712 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19713 #undef THUMB_VARIANT
19714 #define THUMB_VARIANT & arm_ext_v5exp
19716 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19717 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19718 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19719 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19721 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19722 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19724 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19725 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19726 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19727 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19729 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19730 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19731 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19732 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19734 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19735 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19737 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19738 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19739 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19740 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19743 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19744 #undef THUMB_VARIANT
19745 #define THUMB_VARIANT & arm_ext_v6t2
19747 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19748 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19750 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19751 ADDRGLDRS
), ldrd
, t_ldstd
),
19753 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19754 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19757 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19759 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19762 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19763 #undef THUMB_VARIANT
19764 #define THUMB_VARIANT & arm_ext_v6
19766 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19767 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19768 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19769 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19770 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19771 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19772 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19773 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19774 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19775 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19780 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19781 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19783 #undef THUMB_VARIANT
19784 #define THUMB_VARIANT & arm_ext_v6t2
19786 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19787 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19789 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19790 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19792 /* ARM V6 not included in V7M. */
19793 #undef THUMB_VARIANT
19794 #define THUMB_VARIANT & arm_ext_v6_notm
19795 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19796 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19797 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19798 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19799 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19800 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19801 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19802 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19803 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19804 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19805 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19806 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19807 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19808 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19809 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19810 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19811 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19812 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19813 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19815 /* ARM V6 not included in V7M (eg. integer SIMD). */
19816 #undef THUMB_VARIANT
19817 #define THUMB_VARIANT & arm_ext_v6_dsp
19818 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19819 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19820 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19821 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19822 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19823 /* Old name for QASX. */
19824 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19825 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19826 /* Old name for QSAX. */
19827 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19828 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19829 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19830 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19831 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19832 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19833 /* Old name for SASX. */
19834 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19835 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19836 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19837 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19838 /* Old name for SHASX. */
19839 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19840 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19841 /* Old name for SHSAX. */
19842 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19843 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19844 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19845 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19846 /* Old name for SSAX. */
19847 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19848 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19849 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19850 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19851 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19852 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19853 /* Old name for UASX. */
19854 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19855 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19856 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19857 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19858 /* Old name for UHASX. */
19859 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19860 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19861 /* Old name for UHSAX. */
19862 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19863 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19864 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19865 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19866 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19867 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19868 /* Old name for UQASX. */
19869 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19870 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19871 /* Old name for UQSAX. */
19872 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19873 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19874 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19875 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19876 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19877 /* Old name for USAX. */
19878 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19879 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19880 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19881 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19882 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19883 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19884 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19885 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19886 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19887 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19888 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19889 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19890 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19891 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19892 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19893 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19894 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19895 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19896 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19897 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19898 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19899 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19900 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19901 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19902 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19903 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19904 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19905 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19906 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19907 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19908 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19909 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19910 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19911 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19914 #define ARM_VARIANT & arm_ext_v6k
19915 #undef THUMB_VARIANT
19916 #define THUMB_VARIANT & arm_ext_v6k
19918 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19919 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19920 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19921 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19923 #undef THUMB_VARIANT
19924 #define THUMB_VARIANT & arm_ext_v6_notm
19925 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19927 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19928 RRnpcb
), strexd
, t_strexd
),
19930 #undef THUMB_VARIANT
19931 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19932 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19934 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19936 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19938 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19940 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19943 #define ARM_VARIANT & arm_ext_sec
19944 #undef THUMB_VARIANT
19945 #define THUMB_VARIANT & arm_ext_sec
19947 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19950 #define ARM_VARIANT & arm_ext_virt
19951 #undef THUMB_VARIANT
19952 #define THUMB_VARIANT & arm_ext_virt
19954 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19955 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19958 #define ARM_VARIANT & arm_ext_pan
19959 #undef THUMB_VARIANT
19960 #define THUMB_VARIANT & arm_ext_pan
19962 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19965 #define ARM_VARIANT & arm_ext_v6t2
19966 #undef THUMB_VARIANT
19967 #define THUMB_VARIANT & arm_ext_v6t2
19969 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19970 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19971 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19972 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19974 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19975 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19977 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19978 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19979 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19980 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19982 #undef THUMB_VARIANT
19983 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19984 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19985 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19987 /* Thumb-only instructions. */
19989 #define ARM_VARIANT NULL
19990 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19991 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19993 /* ARM does not really have an IT instruction, so always allow it.
19994 The opcode is copied from Thumb in order to allow warnings in
19995 -mimplicit-it=[never | arm] modes. */
19997 #define ARM_VARIANT & arm_ext_v1
19998 #undef THUMB_VARIANT
19999 #define THUMB_VARIANT & arm_ext_v6t2
20001 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20002 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20003 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20004 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20005 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20006 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20007 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20008 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20009 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20010 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20011 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20012 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20013 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20014 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20015 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20016 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20017 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20018 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20020 /* Thumb2 only instructions. */
20022 #define ARM_VARIANT NULL
20024 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20025 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20026 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20027 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20028 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20029 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20031 /* Hardware division instructions. */
20033 #define ARM_VARIANT & arm_ext_adiv
20034 #undef THUMB_VARIANT
20035 #define THUMB_VARIANT & arm_ext_div
20037 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20038 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20040 /* ARM V6M/V7 instructions. */
20042 #define ARM_VARIANT & arm_ext_barrier
20043 #undef THUMB_VARIANT
20044 #define THUMB_VARIANT & arm_ext_barrier
20046 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20047 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20048 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20050 /* ARM V7 instructions. */
20052 #define ARM_VARIANT & arm_ext_v7
20053 #undef THUMB_VARIANT
20054 #define THUMB_VARIANT & arm_ext_v7
20056 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20057 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20060 #define ARM_VARIANT & arm_ext_mp
20061 #undef THUMB_VARIANT
20062 #define THUMB_VARIANT & arm_ext_mp
20064 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20066 /* AArchv8 instructions. */
20068 #define ARM_VARIANT & arm_ext_v8
20070 /* Instructions shared between armv8-a and armv8-m. */
20071 #undef THUMB_VARIANT
20072 #define THUMB_VARIANT & arm_ext_atomics
20074 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20075 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20076 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20077 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20078 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20079 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20080 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20081 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20082 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20083 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20085 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20087 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20089 #undef THUMB_VARIANT
20090 #define THUMB_VARIANT & arm_ext_v8
20092 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20093 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20094 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20096 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20098 /* ARMv8 T32 only. */
20100 #define ARM_VARIANT NULL
20101 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20102 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20103 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20105 /* FP for ARMv8. */
20107 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20108 #undef THUMB_VARIANT
20109 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20111 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20112 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20113 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20114 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20115 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20116 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20117 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20118 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20119 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20120 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20121 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20122 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20123 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20124 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20125 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20126 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20127 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20129 /* Crypto v1 extensions. */
20131 #define ARM_VARIANT & fpu_crypto_ext_armv8
20132 #undef THUMB_VARIANT
20133 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20135 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20136 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20137 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20138 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20139 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20140 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20141 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20142 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20143 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20144 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20145 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20146 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20147 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20148 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20151 #define ARM_VARIANT & crc_ext_armv8
20152 #undef THUMB_VARIANT
20153 #define THUMB_VARIANT & crc_ext_armv8
20154 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20155 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20156 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20157 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20158 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20159 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20161 /* ARMv8.2 RAS extension. */
20163 #define ARM_VARIANT & arm_ext_ras
20164 #undef THUMB_VARIANT
20165 #define THUMB_VARIANT & arm_ext_ras
20166 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20169 #define ARM_VARIANT & arm_ext_v8_3
20170 #undef THUMB_VARIANT
20171 #define THUMB_VARIANT & arm_ext_v8_3
20172 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20173 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20174 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20177 #define ARM_VARIANT & fpu_neon_ext_dotprod
20178 #undef THUMB_VARIANT
20179 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20180 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20181 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20184 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20185 #undef THUMB_VARIANT
20186 #define THUMB_VARIANT NULL
20188 cCE("wfs", e200110
, 1, (RR
), rd
),
20189 cCE("rfs", e300110
, 1, (RR
), rd
),
20190 cCE("wfc", e400110
, 1, (RR
), rd
),
20191 cCE("rfc", e500110
, 1, (RR
), rd
),
20193 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20194 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20195 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20196 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20198 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20199 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20200 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20201 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20203 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20204 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20205 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20206 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20207 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20208 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20209 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20210 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20211 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20212 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20213 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20214 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20216 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20217 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20218 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20219 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20220 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20221 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20222 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20223 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20224 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20225 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20226 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20227 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20229 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20230 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20231 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20232 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20233 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20234 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20235 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20236 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20237 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20238 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20239 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20240 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20242 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20243 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20244 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20245 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20246 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20247 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20248 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20249 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20250 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20251 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20252 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20253 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20255 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20256 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20257 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20258 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20259 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20260 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20261 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20262 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20263 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20264 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20265 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20266 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20268 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20269 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20270 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20271 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20272 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20273 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20274 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20275 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20276 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20277 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20278 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20279 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20281 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20282 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20283 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20284 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20285 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20286 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20287 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20288 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20289 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20290 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20291 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20292 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20294 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20295 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20296 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20297 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20298 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20299 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20300 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20301 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20302 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20303 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20304 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20305 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20307 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20308 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20309 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20310 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20311 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20314 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20316 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20323 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20324 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20327 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20329 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20337 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20340 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20350 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20353 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20363 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20366 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20376 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20379 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20389 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20392 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20402 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20405 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20407 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20408 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20412 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20413 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20414 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20415 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20416 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20417 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20418 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20419 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20420 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20421 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20422 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20424 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20425 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20426 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20427 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20428 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20429 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20430 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20431 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20432 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20433 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20434 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20435 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20437 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20438 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20439 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20440 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20441 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20442 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20443 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20444 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20445 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20446 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20447 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20448 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20450 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20451 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20452 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20453 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20454 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20455 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20456 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20457 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20458 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20459 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20460 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20461 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20463 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20464 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20465 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20466 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20467 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20468 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20469 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20470 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20471 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20472 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20473 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20474 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20476 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20477 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20478 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20479 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20480 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20481 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20482 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20483 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20484 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20485 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20486 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20487 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20489 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20490 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20491 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20492 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20493 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20494 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20495 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20496 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20497 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20498 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20499 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20500 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20502 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20503 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20504 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20505 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20506 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20507 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20508 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20509 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20510 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20511 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20512 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20513 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20515 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20516 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20517 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20518 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20519 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20522 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20524 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20531 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20532 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20535 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20537 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20545 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20548 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20558 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20561 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20571 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20574 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20576 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20577 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20581 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20582 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20583 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20585 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20586 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20587 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20588 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20589 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20590 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20591 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20592 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20593 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20594 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20595 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20596 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20598 /* The implementation of the FIX instruction is broken on some
20599 assemblers, in that it accepts a precision specifier as well as a
20600 rounding specifier, despite the fact that this is meaningless.
20601 To be more compatible, we accept it as well, though of course it
20602 does not set any bits. */
20603 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20604 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20605 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20606 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20607 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20608 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20609 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20610 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20611 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20612 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20613 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20614 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20615 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20617 /* Instructions that were new with the real FPA, call them V2. */
20619 #define ARM_VARIANT & fpu_fpa_ext_v2
20621 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20622 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20623 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20624 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20625 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20626 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20629 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20631 /* Moves and type conversions. */
20632 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20633 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20634 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20635 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20636 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20637 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20638 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20639 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20640 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20641 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20642 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20643 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20644 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20645 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20647 /* Memory operations. */
20648 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20649 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20650 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20651 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20652 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20653 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20654 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20655 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20656 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20657 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20658 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20659 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20660 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20661 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20662 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20663 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20664 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20665 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20667 /* Monadic operations. */
20668 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20669 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20670 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20672 /* Dyadic operations. */
20673 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20674 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20675 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20676 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20677 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20678 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20679 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20680 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20681 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20684 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20685 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20686 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20687 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20689 /* Double precision load/store are still present on single precision
20690 implementations. */
20691 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20692 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20693 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20694 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20695 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20696 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20697 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20698 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20699 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20700 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20703 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20705 /* Moves and type conversions. */
20706 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20707 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20708 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20709 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20710 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20711 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20712 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20713 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20714 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20715 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20716 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20717 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20718 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20720 /* Monadic operations. */
20721 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20722 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20723 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20725 /* Dyadic operations. */
20726 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20727 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20728 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20729 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20730 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20731 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20732 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20733 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20734 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20737 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20738 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20739 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20740 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20743 #define ARM_VARIANT & fpu_vfp_ext_v2
20745 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20746 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20747 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20748 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20750 /* Instructions which may belong to either the Neon or VFP instruction sets.
20751 Individual encoder functions perform additional architecture checks. */
20753 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20754 #undef THUMB_VARIANT
20755 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20757 /* These mnemonics are unique to VFP. */
20758 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20759 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20760 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20761 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20762 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20763 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20764 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20765 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20766 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20767 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20769 /* Mnemonics shared by Neon and VFP. */
20770 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20771 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20772 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20774 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20775 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20777 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20778 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20780 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20781 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20782 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20783 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20784 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20785 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20786 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20787 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20789 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20790 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20791 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20792 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20795 /* NOTE: All VMOV encoding is special-cased! */
20796 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20797 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20800 #define ARM_VARIANT & arm_ext_fp16
20801 #undef THUMB_VARIANT
20802 #define THUMB_VARIANT & arm_ext_fp16
20803 /* New instructions added from v8.2, allowing the extraction and insertion of
20804 the upper 16 bits of a 32-bit vector register. */
20805 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20806 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20808 /* New backported fma/fms instructions optional in v8.2. */
20809 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20810 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20812 #undef THUMB_VARIANT
20813 #define THUMB_VARIANT & fpu_neon_ext_v1
20815 #define ARM_VARIANT & fpu_neon_ext_v1
20817 /* Data processing with three registers of the same length. */
20818 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20819 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20820 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20821 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20822 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20823 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20824 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20825 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20826 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20827 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20828 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20829 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20830 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20831 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20832 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20833 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20834 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20835 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20836 /* If not immediate, fall back to neon_dyadic_i64_su.
20837 shl_imm should accept I8 I16 I32 I64,
20838 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20839 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20840 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20841 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20842 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20843 /* Logic ops, types optional & ignored. */
20844 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20845 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20846 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20847 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20848 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20849 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20850 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20851 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20852 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20853 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20854 /* Bitfield ops, untyped. */
20855 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20856 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20857 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20858 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20859 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20860 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20861 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20862 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20863 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20864 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20865 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20866 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20867 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20868 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20869 back to neon_dyadic_if_su. */
20870 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20871 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20872 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20873 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20874 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20875 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20876 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20877 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20878 /* Comparison. Type I8 I16 I32 F32. */
20879 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20880 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20881 /* As above, D registers only. */
20882 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20883 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20884 /* Int and float variants, signedness unimportant. */
20885 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20886 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20887 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20888 /* Add/sub take types I8 I16 I32 I64 F32. */
20889 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20890 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20891 /* vtst takes sizes 8, 16, 32. */
20892 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20893 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20894 /* VMUL takes I8 I16 I32 F32 P8. */
20895 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20896 /* VQD{R}MULH takes S16 S32. */
20897 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20898 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20899 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20900 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20901 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20902 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20903 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20904 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20905 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20906 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20907 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20908 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20909 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20910 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20911 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20912 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20913 /* ARM v8.1 extension. */
20914 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20915 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20916 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20917 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20919 /* Two address, int/float. Types S8 S16 S32 F32. */
20920 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20921 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20923 /* Data processing with two registers and a shift amount. */
20924 /* Right shifts, and variants with rounding.
20925 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20926 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20927 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20928 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20929 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20930 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20931 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20932 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20933 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20934 /* Shift and insert. Sizes accepted 8 16 32 64. */
20935 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20936 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20937 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20938 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20939 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20940 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20941 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20942 /* Right shift immediate, saturating & narrowing, with rounding variants.
20943 Types accepted S16 S32 S64 U16 U32 U64. */
20944 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20945 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20946 /* As above, unsigned. Types accepted S16 S32 S64. */
20947 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20948 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20949 /* Right shift narrowing. Types accepted I16 I32 I64. */
20950 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20951 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20952 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20953 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20954 /* CVT with optional immediate for fixed-point variant. */
20955 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20957 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20958 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20960 /* Data processing, three registers of different lengths. */
20961 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20962 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20963 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20964 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20965 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20966 /* If not scalar, fall back to neon_dyadic_long.
20967 Vector types as above, scalar types S16 S32 U16 U32. */
20968 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20969 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20970 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20971 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20972 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20973 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20974 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20975 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20976 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20977 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20978 /* Saturating doubling multiplies. Types S16 S32. */
20979 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20980 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20981 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20982 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20983 S16 S32 U16 U32. */
20984 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20986 /* Extract. Size 8. */
20987 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20988 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20990 /* Two registers, miscellaneous. */
20991 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20992 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20993 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20994 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20995 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20996 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20997 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20998 /* Vector replicate. Sizes 8 16 32. */
20999 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21000 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21001 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21002 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21003 /* VMOVN. Types I16 I32 I64. */
21004 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21005 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21006 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21007 /* VQMOVUN. Types S16 S32 S64. */
21008 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21009 /* VZIP / VUZP. Sizes 8 16 32. */
21010 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21011 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21012 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21013 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21014 /* VQABS / VQNEG. Types S8 S16 S32. */
21015 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21016 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21017 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21018 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21019 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21020 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21021 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21022 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21023 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21024 /* Reciprocal estimates. Types U32 F16 F32. */
21025 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21026 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21027 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21028 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21029 /* VCLS. Types S8 S16 S32. */
21030 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21031 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21032 /* VCLZ. Types I8 I16 I32. */
21033 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21034 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21035 /* VCNT. Size 8. */
21036 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21037 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21038 /* Two address, untyped. */
21039 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21040 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21041 /* VTRN. Sizes 8 16 32. */
21042 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21043 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21045 /* Table lookup. Size 8. */
21046 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21047 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21049 #undef THUMB_VARIANT
21050 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21052 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21054 /* Neon element/structure load/store. */
21055 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21056 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21057 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21058 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21059 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21060 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21061 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21062 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21064 #undef THUMB_VARIANT
21065 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21067 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21068 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21069 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21070 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21071 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21072 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21073 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21074 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21075 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21076 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21078 #undef THUMB_VARIANT
21079 #define THUMB_VARIANT & fpu_vfp_ext_v3
21081 #define ARM_VARIANT & fpu_vfp_ext_v3
21083 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21084 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21085 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21086 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21087 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21088 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21089 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21090 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21091 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21094 #define ARM_VARIANT & fpu_vfp_ext_fma
21095 #undef THUMB_VARIANT
21096 #define THUMB_VARIANT & fpu_vfp_ext_fma
21097 /* Mnemonics shared by Neon and VFP. These are included in the
21098 VFP FMA variant; NEON and VFP FMA always includes the NEON
21099 FMA instructions. */
21100 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21101 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21102 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21103 the v form should always be used. */
21104 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21105 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21106 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21107 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21108 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21109 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21111 #undef THUMB_VARIANT
21113 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21115 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21116 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21117 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21118 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21119 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21120 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21121 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21122 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21125 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21127 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21128 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21129 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21130 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21131 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21132 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21133 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21134 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21135 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21136 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21137 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21138 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21139 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21140 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21141 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21142 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21143 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21144 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21145 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21146 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21147 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21148 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21149 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21150 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21151 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21152 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21153 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21154 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21155 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21156 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21157 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21158 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21159 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21160 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21161 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21162 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21163 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21164 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21165 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21166 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21167 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21168 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21169 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21170 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21171 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21172 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21173 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21174 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21175 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21176 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21177 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21178 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21179 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21180 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21181 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21182 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21183 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21184 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21185 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21186 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21187 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21188 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21189 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21190 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21191 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21192 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21193 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21194 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21195 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21196 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21197 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21198 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21199 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21200 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21201 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21202 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21203 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21204 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21205 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21206 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21207 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21208 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21209 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21210 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21211 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21212 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21213 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21214 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21215 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21216 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21217 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21218 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21219 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21220 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21221 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21222 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21223 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21224 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21225 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21226 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21227 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21228 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21229 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21230 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21231 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21232 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21233 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21234 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21235 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21236 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21237 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21238 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21239 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21240 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21241 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21242 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21243 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21244 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21245 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21246 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21247 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21248 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21249 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21250 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21251 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21252 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21253 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21254 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21255 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21256 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21257 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21258 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21259 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21260 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21261 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21262 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21263 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21264 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21265 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21266 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21267 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21268 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21269 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21270 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21271 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21272 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21273 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21274 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21275 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21276 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21277 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21278 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21279 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21280 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21281 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21282 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21283 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21284 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21285 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21286 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21287 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21288 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21291 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21293 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21294 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21295 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21296 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21297 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21298 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21299 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21300 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21301 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21302 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21303 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21304 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21305 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21309 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21311 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21312 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21313 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21314 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21315 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21316 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21317 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21318 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21319 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21320 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21321 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21322 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21323 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21324 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21325 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21326 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21327 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21328 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21329 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21330 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21331 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21332 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21333 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21336 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21337 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21338 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21339 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21340 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21341 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21342 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21343 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21344 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21345 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21346 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21347 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21348 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21349 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21352 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21354 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21355 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21356 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21357 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21358 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21359 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21360 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21361 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21362 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21363 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21364 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21365 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21366 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21367 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21368 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21369 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21370 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21371 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21372 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21373 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21374 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21375 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21376 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21377 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21378 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21379 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21380 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21381 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21382 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21383 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21384 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21385 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21386 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21387 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21388 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21389 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21390 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21391 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21392 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21393 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21394 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21395 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21396 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21397 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21398 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21399 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21400 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21401 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21402 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21403 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21404 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21405 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21406 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21407 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21408 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21409 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21410 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21411 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21412 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21413 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21414 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21415 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21416 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21417 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21418 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21419 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21420 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21421 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21422 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21423 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21424 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21425 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21426 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21427 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21428 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21429 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21431 /* ARMv8-M instructions. */
21433 #define ARM_VARIANT NULL
21434 #undef THUMB_VARIANT
21435 #define THUMB_VARIANT & arm_ext_v8m
21436 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21437 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21438 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21439 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21440 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21441 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21442 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21444 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21445 instructions behave as nop if no VFP is present. */
21446 #undef THUMB_VARIANT
21447 #define THUMB_VARIANT & arm_ext_v8m_main
21448 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21449 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21452 #undef THUMB_VARIANT
21478 /* MD interface: bits in the object file. */
21480 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21481 for use in the a.out file, and stores them in the array pointed to by buf.
21482 This knows about the endian-ness of the target machine and does
21483 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21484 2 (short) and 4 (long) Floating numbers are put out as a series of
21485 LITTLENUMS (shorts, here at least). */
21488 md_number_to_chars (char * buf
, valueT val
, int n
)
21490 if (target_big_endian
)
21491 number_to_chars_bigendian (buf
, val
, n
);
21493 number_to_chars_littleendian (buf
, val
, n
);
21497 md_chars_to_number (char * buf
, int n
)
21500 unsigned char * where
= (unsigned char *) buf
;
21502 if (target_big_endian
)
21507 result
|= (*where
++ & 255);
21515 result
|= (where
[n
] & 255);
21522 /* MD interface: Sections. */
21524 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21525 that an rs_machine_dependent frag may reach. */
21528 arm_frag_max_var (fragS
*fragp
)
21530 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21531 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21533 Note that we generate relaxable instructions even for cases that don't
21534 really need it, like an immediate that's a trivial constant. So we're
21535 overestimating the instruction size for some of those cases. Rather
21536 than putting more intelligence here, it would probably be better to
21537 avoid generating a relaxation frag in the first place when it can be
21538 determined up front that a short instruction will suffice. */
21540 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21544 /* Estimate the size of a frag before relaxing. Assume everything fits in
21548 md_estimate_size_before_relax (fragS
* fragp
,
21549 segT segtype ATTRIBUTE_UNUSED
)
21555 /* Convert a machine dependent frag. */
21558 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21560 unsigned long insn
;
21561 unsigned long old_op
;
21569 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21571 old_op
= bfd_get_16(abfd
, buf
);
21572 if (fragp
->fr_symbol
)
21574 exp
.X_op
= O_symbol
;
21575 exp
.X_add_symbol
= fragp
->fr_symbol
;
21579 exp
.X_op
= O_constant
;
21581 exp
.X_add_number
= fragp
->fr_offset
;
21582 opcode
= fragp
->fr_subtype
;
21585 case T_MNEM_ldr_pc
:
21586 case T_MNEM_ldr_pc2
:
21587 case T_MNEM_ldr_sp
:
21588 case T_MNEM_str_sp
:
21595 if (fragp
->fr_var
== 4)
21597 insn
= THUMB_OP32 (opcode
);
21598 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21600 insn
|= (old_op
& 0x700) << 4;
21604 insn
|= (old_op
& 7) << 12;
21605 insn
|= (old_op
& 0x38) << 13;
21607 insn
|= 0x00000c00;
21608 put_thumb32_insn (buf
, insn
);
21609 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21613 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21615 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21618 if (fragp
->fr_var
== 4)
21620 insn
= THUMB_OP32 (opcode
);
21621 insn
|= (old_op
& 0xf0) << 4;
21622 put_thumb32_insn (buf
, insn
);
21623 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21627 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21628 exp
.X_add_number
-= 4;
21636 if (fragp
->fr_var
== 4)
21638 int r0off
= (opcode
== T_MNEM_mov
21639 || opcode
== T_MNEM_movs
) ? 0 : 8;
21640 insn
= THUMB_OP32 (opcode
);
21641 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21642 insn
|= (old_op
& 0x700) << r0off
;
21643 put_thumb32_insn (buf
, insn
);
21644 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21648 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21653 if (fragp
->fr_var
== 4)
21655 insn
= THUMB_OP32(opcode
);
21656 put_thumb32_insn (buf
, insn
);
21657 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21660 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21664 if (fragp
->fr_var
== 4)
21666 insn
= THUMB_OP32(opcode
);
21667 insn
|= (old_op
& 0xf00) << 14;
21668 put_thumb32_insn (buf
, insn
);
21669 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21672 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21675 case T_MNEM_add_sp
:
21676 case T_MNEM_add_pc
:
21677 case T_MNEM_inc_sp
:
21678 case T_MNEM_dec_sp
:
21679 if (fragp
->fr_var
== 4)
21681 /* ??? Choose between add and addw. */
21682 insn
= THUMB_OP32 (opcode
);
21683 insn
|= (old_op
& 0xf0) << 4;
21684 put_thumb32_insn (buf
, insn
);
21685 if (opcode
== T_MNEM_add_pc
)
21686 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21688 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21691 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21699 if (fragp
->fr_var
== 4)
21701 insn
= THUMB_OP32 (opcode
);
21702 insn
|= (old_op
& 0xf0) << 4;
21703 insn
|= (old_op
& 0xf) << 16;
21704 put_thumb32_insn (buf
, insn
);
21705 if (insn
& (1 << 20))
21706 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21708 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21711 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21717 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21718 (enum bfd_reloc_code_real
) reloc_type
);
21719 fixp
->fx_file
= fragp
->fr_file
;
21720 fixp
->fx_line
= fragp
->fr_line
;
21721 fragp
->fr_fix
+= fragp
->fr_var
;
21723 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21724 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21725 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21726 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21729 /* Return the size of a relaxable immediate operand instruction.
21730 SHIFT and SIZE specify the form of the allowable immediate. */
21732 relax_immediate (fragS
*fragp
, int size
, int shift
)
21738 /* ??? Should be able to do better than this. */
21739 if (fragp
->fr_symbol
)
21742 low
= (1 << shift
) - 1;
21743 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21744 offset
= fragp
->fr_offset
;
21745 /* Force misaligned offsets to 32-bit variant. */
21748 if (offset
& ~mask
)
21753 /* Get the address of a symbol during relaxation. */
21755 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21761 sym
= fragp
->fr_symbol
;
21762 sym_frag
= symbol_get_frag (sym
);
21763 know (S_GET_SEGMENT (sym
) != absolute_section
21764 || sym_frag
== &zero_address_frag
);
21765 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21767 /* If frag has yet to be reached on this pass, assume it will
21768 move by STRETCH just as we did. If this is not so, it will
21769 be because some frag between grows, and that will force
21773 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21777 /* Adjust stretch for any alignment frag. Note that if have
21778 been expanding the earlier code, the symbol may be
21779 defined in what appears to be an earlier frag. FIXME:
21780 This doesn't handle the fr_subtype field, which specifies
21781 a maximum number of bytes to skip when doing an
21783 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21785 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21788 stretch
= - ((- stretch
)
21789 & ~ ((1 << (int) f
->fr_offset
) - 1));
21791 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21803 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21806 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21811 /* Assume worst case for symbols not known to be in the same section. */
21812 if (fragp
->fr_symbol
== NULL
21813 || !S_IS_DEFINED (fragp
->fr_symbol
)
21814 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21815 || S_IS_WEAK (fragp
->fr_symbol
))
21818 val
= relaxed_symbol_addr (fragp
, stretch
);
21819 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21820 addr
= (addr
+ 4) & ~3;
21821 /* Force misaligned targets to 32-bit variant. */
21825 if (val
< 0 || val
> 1020)
21830 /* Return the size of a relaxable add/sub immediate instruction. */
21832 relax_addsub (fragS
*fragp
, asection
*sec
)
21837 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21838 op
= bfd_get_16(sec
->owner
, buf
);
21839 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21840 return relax_immediate (fragp
, 8, 0);
21842 return relax_immediate (fragp
, 3, 0);
21845 /* Return TRUE iff the definition of symbol S could be pre-empted
21846 (overridden) at link or load time. */
21848 symbol_preemptible (symbolS
*s
)
21850 /* Weak symbols can always be pre-empted. */
21854 /* Non-global symbols cannot be pre-empted. */
21855 if (! S_IS_EXTERNAL (s
))
21859 /* In ELF, a global symbol can be marked protected, or private. In that
21860 case it can't be pre-empted (other definitions in the same link unit
21861 would violate the ODR). */
21862 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21866 /* Other global symbols might be pre-empted. */
21870 /* Return the size of a relaxable branch instruction. BITS is the
21871 size of the offset field in the narrow instruction. */
21874 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21880 /* Assume worst case for symbols not known to be in the same section. */
21881 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21882 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21883 || S_IS_WEAK (fragp
->fr_symbol
))
21887 /* A branch to a function in ARM state will require interworking. */
21888 if (S_IS_DEFINED (fragp
->fr_symbol
)
21889 && ARM_IS_FUNC (fragp
->fr_symbol
))
21893 if (symbol_preemptible (fragp
->fr_symbol
))
21896 val
= relaxed_symbol_addr (fragp
, stretch
);
21897 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21900 /* Offset is a signed value *2 */
21902 if (val
>= limit
|| val
< -limit
)
21908 /* Relax a machine dependent frag. This returns the amount by which
21909 the current size of the frag should change. */
21912 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21917 oldsize
= fragp
->fr_var
;
21918 switch (fragp
->fr_subtype
)
21920 case T_MNEM_ldr_pc2
:
21921 newsize
= relax_adr (fragp
, sec
, stretch
);
21923 case T_MNEM_ldr_pc
:
21924 case T_MNEM_ldr_sp
:
21925 case T_MNEM_str_sp
:
21926 newsize
= relax_immediate (fragp
, 8, 2);
21930 newsize
= relax_immediate (fragp
, 5, 2);
21934 newsize
= relax_immediate (fragp
, 5, 1);
21938 newsize
= relax_immediate (fragp
, 5, 0);
21941 newsize
= relax_adr (fragp
, sec
, stretch
);
21947 newsize
= relax_immediate (fragp
, 8, 0);
21950 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21953 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21955 case T_MNEM_add_sp
:
21956 case T_MNEM_add_pc
:
21957 newsize
= relax_immediate (fragp
, 8, 2);
21959 case T_MNEM_inc_sp
:
21960 case T_MNEM_dec_sp
:
21961 newsize
= relax_immediate (fragp
, 7, 2);
21967 newsize
= relax_addsub (fragp
, sec
);
21973 fragp
->fr_var
= newsize
;
21974 /* Freeze wide instructions that are at or before the same location as
21975 in the previous pass. This avoids infinite loops.
21976 Don't freeze them unconditionally because targets may be artificially
21977 misaligned by the expansion of preceding frags. */
21978 if (stretch
<= 0 && newsize
> 2)
21980 md_convert_frag (sec
->owner
, sec
, fragp
);
21984 return newsize
- oldsize
;
21987 /* Round up a section size to the appropriate boundary. */
21990 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21993 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21994 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21996 /* For a.out, force the section size to be aligned. If we don't do
21997 this, BFD will align it for us, but it will not write out the
21998 final bytes of the section. This may be a bug in BFD, but it is
21999 easier to fix it here since that is how the other a.out targets
22003 align
= bfd_get_section_alignment (stdoutput
, segment
);
22004 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
22011 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22012 of an rs_align_code fragment. */
22015 arm_handle_align (fragS
* fragP
)
22017 static unsigned char const arm_noop
[2][2][4] =
22020 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22021 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22024 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22025 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22028 static unsigned char const thumb_noop
[2][2][2] =
22031 {0xc0, 0x46}, /* LE */
22032 {0x46, 0xc0}, /* BE */
22035 {0x00, 0xbf}, /* LE */
22036 {0xbf, 0x00} /* BE */
22039 static unsigned char const wide_thumb_noop
[2][4] =
22040 { /* Wide Thumb-2 */
22041 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22042 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22045 unsigned bytes
, fix
, noop_size
;
22047 const unsigned char * noop
;
22048 const unsigned char *narrow_noop
= NULL
;
22053 if (fragP
->fr_type
!= rs_align_code
)
22056 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22057 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22060 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22061 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22063 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22065 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22067 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22068 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22070 narrow_noop
= thumb_noop
[1][target_big_endian
];
22071 noop
= wide_thumb_noop
[target_big_endian
];
22074 noop
= thumb_noop
[0][target_big_endian
];
22082 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22083 ? selected_cpu
: arm_arch_none
,
22085 [target_big_endian
];
22092 fragP
->fr_var
= noop_size
;
22094 if (bytes
& (noop_size
- 1))
22096 fix
= bytes
& (noop_size
- 1);
22098 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22100 memset (p
, 0, fix
);
22107 if (bytes
& noop_size
)
22109 /* Insert a narrow noop. */
22110 memcpy (p
, narrow_noop
, noop_size
);
22112 bytes
-= noop_size
;
22116 /* Use wide noops for the remainder */
22120 while (bytes
>= noop_size
)
22122 memcpy (p
, noop
, noop_size
);
22124 bytes
-= noop_size
;
22128 fragP
->fr_fix
+= fix
;
22131 /* Called from md_do_align. Used to create an alignment
22132 frag in a code section. */
22135 arm_frag_align_code (int n
, int max
)
22139 /* We assume that there will never be a requirement
22140 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22141 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22146 _("alignments greater than %d bytes not supported in .text sections."),
22147 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22148 as_fatal ("%s", err_msg
);
22151 p
= frag_var (rs_align_code
,
22152 MAX_MEM_FOR_RS_ALIGN_CODE
,
22154 (relax_substateT
) max
,
22161 /* Perform target specific initialisation of a frag.
22162 Note - despite the name this initialisation is not done when the frag
22163 is created, but only when its type is assigned. A frag can be created
22164 and used a long time before its type is set, so beware of assuming that
22165 this initialisation is performed first. */
22169 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22171 /* Record whether this frag is in an ARM or a THUMB area. */
22172 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22175 #else /* OBJ_ELF is defined. */
22177 arm_init_frag (fragS
* fragP
, int max_chars
)
22179 bfd_boolean frag_thumb_mode
;
22181 /* If the current ARM vs THUMB mode has not already
22182 been recorded into this frag then do so now. */
22183 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22184 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22186 /* PR 21809: Do not set a mapping state for debug sections
22187 - it just confuses other tools. */
22188 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22191 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22193 /* Record a mapping symbol for alignment frags. We will delete this
22194 later if the alignment ends up empty. */
22195 switch (fragP
->fr_type
)
22198 case rs_align_test
:
22200 mapping_state_2 (MAP_DATA
, max_chars
);
22202 case rs_align_code
:
22203 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22210 /* When we change sections we need to issue a new mapping symbol. */
22213 arm_elf_change_section (void)
22215 /* Link an unlinked unwind index table section to the .text section. */
22216 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22217 && elf_linked_to_section (now_seg
) == NULL
)
22218 elf_linked_to_section (now_seg
) = text_section
;
22222 arm_elf_section_type (const char * str
, size_t len
)
22224 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22225 return SHT_ARM_EXIDX
;
22230 /* Code to deal with unwinding tables. */
22232 static void add_unwind_adjustsp (offsetT
);
22234 /* Generate any deferred unwind frame offset. */
22237 flush_pending_unwind (void)
22241 offset
= unwind
.pending_offset
;
22242 unwind
.pending_offset
= 0;
22244 add_unwind_adjustsp (offset
);
22247 /* Add an opcode to this list for this function. Two-byte opcodes should
22248 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22252 add_unwind_opcode (valueT op
, int length
)
22254 /* Add any deferred stack adjustment. */
22255 if (unwind
.pending_offset
)
22256 flush_pending_unwind ();
22258 unwind
.sp_restored
= 0;
22260 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22262 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22263 if (unwind
.opcodes
)
22264 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22265 unwind
.opcode_alloc
);
22267 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22272 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22274 unwind
.opcode_count
++;
22278 /* Add unwind opcodes to adjust the stack pointer. */
22281 add_unwind_adjustsp (offsetT offset
)
22285 if (offset
> 0x200)
22287 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22292 /* Long form: 0xb2, uleb128. */
22293 /* This might not fit in a word so add the individual bytes,
22294 remembering the list is built in reverse order. */
22295 o
= (valueT
) ((offset
- 0x204) >> 2);
22297 add_unwind_opcode (0, 1);
22299 /* Calculate the uleb128 encoding of the offset. */
22303 bytes
[n
] = o
& 0x7f;
22309 /* Add the insn. */
22311 add_unwind_opcode (bytes
[n
- 1], 1);
22312 add_unwind_opcode (0xb2, 1);
22314 else if (offset
> 0x100)
22316 /* Two short opcodes. */
22317 add_unwind_opcode (0x3f, 1);
22318 op
= (offset
- 0x104) >> 2;
22319 add_unwind_opcode (op
, 1);
22321 else if (offset
> 0)
22323 /* Short opcode. */
22324 op
= (offset
- 4) >> 2;
22325 add_unwind_opcode (op
, 1);
22327 else if (offset
< 0)
22330 while (offset
> 0x100)
22332 add_unwind_opcode (0x7f, 1);
22335 op
= ((offset
- 4) >> 2) | 0x40;
22336 add_unwind_opcode (op
, 1);
22340 /* Finish the list of unwind opcodes for this function. */
22343 finish_unwind_opcodes (void)
22347 if (unwind
.fp_used
)
22349 /* Adjust sp as necessary. */
22350 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22351 flush_pending_unwind ();
22353 /* After restoring sp from the frame pointer. */
22354 op
= 0x90 | unwind
.fp_reg
;
22355 add_unwind_opcode (op
, 1);
22358 flush_pending_unwind ();
22362 /* Start an exception table entry. If idx is nonzero this is an index table
22366 start_unwind_section (const segT text_seg
, int idx
)
22368 const char * text_name
;
22369 const char * prefix
;
22370 const char * prefix_once
;
22371 const char * group_name
;
22379 prefix
= ELF_STRING_ARM_unwind
;
22380 prefix_once
= ELF_STRING_ARM_unwind_once
;
22381 type
= SHT_ARM_EXIDX
;
22385 prefix
= ELF_STRING_ARM_unwind_info
;
22386 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22387 type
= SHT_PROGBITS
;
22390 text_name
= segment_name (text_seg
);
22391 if (streq (text_name
, ".text"))
22394 if (strncmp (text_name
, ".gnu.linkonce.t.",
22395 strlen (".gnu.linkonce.t.")) == 0)
22397 prefix
= prefix_once
;
22398 text_name
+= strlen (".gnu.linkonce.t.");
22401 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22407 /* Handle COMDAT group. */
22408 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22410 group_name
= elf_group_name (text_seg
);
22411 if (group_name
== NULL
)
22413 as_bad (_("Group section `%s' has no group signature"),
22414 segment_name (text_seg
));
22415 ignore_rest_of_line ();
22418 flags
|= SHF_GROUP
;
22422 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22425 /* Set the section link for index tables. */
22427 elf_linked_to_section (now_seg
) = text_seg
;
22431 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22432 personality routine data. Returns zero, or the index table value for
22433 an inline entry. */
22436 create_unwind_entry (int have_data
)
22441 /* The current word of data. */
22443 /* The number of bytes left in this word. */
22446 finish_unwind_opcodes ();
22448 /* Remember the current text section. */
22449 unwind
.saved_seg
= now_seg
;
22450 unwind
.saved_subseg
= now_subseg
;
22452 start_unwind_section (now_seg
, 0);
22454 if (unwind
.personality_routine
== NULL
)
22456 if (unwind
.personality_index
== -2)
22459 as_bad (_("handlerdata in cantunwind frame"));
22460 return 1; /* EXIDX_CANTUNWIND. */
22463 /* Use a default personality routine if none is specified. */
22464 if (unwind
.personality_index
== -1)
22466 if (unwind
.opcode_count
> 3)
22467 unwind
.personality_index
= 1;
22469 unwind
.personality_index
= 0;
22472 /* Space for the personality routine entry. */
22473 if (unwind
.personality_index
== 0)
22475 if (unwind
.opcode_count
> 3)
22476 as_bad (_("too many unwind opcodes for personality routine 0"));
22480 /* All the data is inline in the index table. */
22483 while (unwind
.opcode_count
> 0)
22485 unwind
.opcode_count
--;
22486 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22490 /* Pad with "finish" opcodes. */
22492 data
= (data
<< 8) | 0xb0;
22499 /* We get two opcodes "free" in the first word. */
22500 size
= unwind
.opcode_count
- 2;
22504 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22505 if (unwind
.personality_index
!= -1)
22507 as_bad (_("attempt to recreate an unwind entry"));
22511 /* An extra byte is required for the opcode count. */
22512 size
= unwind
.opcode_count
+ 1;
22515 size
= (size
+ 3) >> 2;
22517 as_bad (_("too many unwind opcodes"));
22519 frag_align (2, 0, 0);
22520 record_alignment (now_seg
, 2);
22521 unwind
.table_entry
= expr_build_dot ();
22523 /* Allocate the table entry. */
22524 ptr
= frag_more ((size
<< 2) + 4);
22525 /* PR 13449: Zero the table entries in case some of them are not used. */
22526 memset (ptr
, 0, (size
<< 2) + 4);
22527 where
= frag_now_fix () - ((size
<< 2) + 4);
22529 switch (unwind
.personality_index
)
22532 /* ??? Should this be a PLT generating relocation? */
22533 /* Custom personality routine. */
22534 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22535 BFD_RELOC_ARM_PREL31
);
22540 /* Set the first byte to the number of additional words. */
22541 data
= size
> 0 ? size
- 1 : 0;
22545 /* ABI defined personality routines. */
22547 /* Three opcodes bytes are packed into the first word. */
22554 /* The size and first two opcode bytes go in the first word. */
22555 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22560 /* Should never happen. */
22564 /* Pack the opcodes into words (MSB first), reversing the list at the same
22566 while (unwind
.opcode_count
> 0)
22570 md_number_to_chars (ptr
, data
, 4);
22575 unwind
.opcode_count
--;
22577 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22580 /* Finish off the last word. */
22583 /* Pad with "finish" opcodes. */
22585 data
= (data
<< 8) | 0xb0;
22587 md_number_to_chars (ptr
, data
, 4);
22592 /* Add an empty descriptor if there is no user-specified data. */
22593 ptr
= frag_more (4);
22594 md_number_to_chars (ptr
, 0, 4);
22601 /* Initialize the DWARF-2 unwind information for this procedure. */
22604 tc_arm_frame_initial_instructions (void)
22606 cfi_add_CFA_def_cfa (REG_SP
, 0);
22608 #endif /* OBJ_ELF */
22610 /* Convert REGNAME to a DWARF-2 register number. */
22613 tc_arm_regname_to_dw2regnum (char *regname
)
22615 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22619 /* PR 16694: Allow VFP registers as well. */
22620 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22624 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22633 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22637 exp
.X_op
= O_secrel
;
22638 exp
.X_add_symbol
= symbol
;
22639 exp
.X_add_number
= 0;
22640 emit_expr (&exp
, size
);
22644 /* MD interface: Symbol and relocation handling. */
22646 /* Return the address within the segment that a PC-relative fixup is
22647 relative to. For ARM, PC-relative fixups applied to instructions
22648 are generally relative to the location of the fixup plus 8 bytes.
22649 Thumb branches are offset by 4, and Thumb loads relative to PC
22650 require special handling. */
22653 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22655 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22657 /* If this is pc-relative and we are going to emit a relocation
22658 then we just want to put out any pipeline compensation that the linker
22659 will need. Otherwise we want to use the calculated base.
22660 For WinCE we skip the bias for externals as well, since this
22661 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22663 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22664 || (arm_force_relocation (fixP
)
22666 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22672 switch (fixP
->fx_r_type
)
22674 /* PC relative addressing on the Thumb is slightly odd as the
22675 bottom two bits of the PC are forced to zero for the
22676 calculation. This happens *after* application of the
22677 pipeline offset. However, Thumb adrl already adjusts for
22678 this, so we need not do it again. */
22679 case BFD_RELOC_ARM_THUMB_ADD
:
22682 case BFD_RELOC_ARM_THUMB_OFFSET
:
22683 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22684 case BFD_RELOC_ARM_T32_ADD_PC12
:
22685 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22686 return (base
+ 4) & ~3;
22688 /* Thumb branches are simply offset by +4. */
22689 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22690 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22691 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22692 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22693 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22696 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22698 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22699 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22700 && ARM_IS_FUNC (fixP
->fx_addsy
)
22701 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22702 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22705 /* BLX is like branches above, but forces the low two bits of PC to
22707 case BFD_RELOC_THUMB_PCREL_BLX
:
22709 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22710 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22711 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22712 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22713 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22714 return (base
+ 4) & ~3;
22716 /* ARM mode branches are offset by +8. However, the Windows CE
22717 loader expects the relocation not to take this into account. */
22718 case BFD_RELOC_ARM_PCREL_BLX
:
22720 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22721 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22722 && ARM_IS_FUNC (fixP
->fx_addsy
)
22723 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22724 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22727 case BFD_RELOC_ARM_PCREL_CALL
:
22729 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22730 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22731 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22732 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22733 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22736 case BFD_RELOC_ARM_PCREL_BRANCH
:
22737 case BFD_RELOC_ARM_PCREL_JUMP
:
22738 case BFD_RELOC_ARM_PLT32
:
22740 /* When handling fixups immediately, because we have already
22741 discovered the value of a symbol, or the address of the frag involved
22742 we must account for the offset by +8, as the OS loader will never see the reloc.
22743 see fixup_segment() in write.c
22744 The S_IS_EXTERNAL test handles the case of global symbols.
22745 Those need the calculated base, not just the pipe compensation the linker will need. */
22747 && fixP
->fx_addsy
!= NULL
22748 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22749 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22757 /* ARM mode loads relative to PC are also offset by +8. Unlike
22758 branches, the Windows CE loader *does* expect the relocation
22759 to take this into account. */
22760 case BFD_RELOC_ARM_OFFSET_IMM
:
22761 case BFD_RELOC_ARM_OFFSET_IMM8
:
22762 case BFD_RELOC_ARM_HWLITERAL
:
22763 case BFD_RELOC_ARM_LITERAL
:
22764 case BFD_RELOC_ARM_CP_OFF_IMM
:
22768 /* Other PC-relative relocations are un-offset. */
22774 static bfd_boolean flag_warn_syms
= TRUE
;
22777 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22779 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22780 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22781 does mean that the resulting code might be very confusing to the reader.
22782 Also this warning can be triggered if the user omits an operand before
22783 an immediate address, eg:
22787 GAS treats this as an assignment of the value of the symbol foo to a
22788 symbol LDR, and so (without this code) it will not issue any kind of
22789 warning or error message.
22791 Note - ARM instructions are case-insensitive but the strings in the hash
22792 table are all stored in lower case, so we must first ensure that name is
22794 if (flag_warn_syms
&& arm_ops_hsh
)
22796 char * nbuf
= strdup (name
);
22799 for (p
= nbuf
; *p
; p
++)
22801 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22803 static struct hash_control
* already_warned
= NULL
;
22805 if (already_warned
== NULL
)
22806 already_warned
= hash_new ();
22807 /* Only warn about the symbol once. To keep the code
22808 simple we let hash_insert do the lookup for us. */
22809 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22810 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22819 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22820 Otherwise we have no need to default values of symbols. */
22823 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22826 if (name
[0] == '_' && name
[1] == 'G'
22827 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22831 if (symbol_find (name
))
22832 as_bad (_("GOT already in the symbol table"));
22834 GOT_symbol
= symbol_new (name
, undefined_section
,
22835 (valueT
) 0, & zero_address_frag
);
22845 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22846 computed as two separate immediate values, added together. We
22847 already know that this value cannot be computed by just one ARM
22850 static unsigned int
22851 validate_immediate_twopart (unsigned int val
,
22852 unsigned int * highpart
)
22857 for (i
= 0; i
< 32; i
+= 2)
22858 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22864 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22866 else if (a
& 0xff0000)
22868 if (a
& 0xff000000)
22870 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22874 gas_assert (a
& 0xff000000);
22875 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22878 return (a
& 0xff) | (i
<< 7);
22885 validate_offset_imm (unsigned int val
, int hwse
)
22887 if ((hwse
&& val
> 255) || val
> 4095)
22892 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22893 negative immediate constant by altering the instruction. A bit of
22898 by inverting the second operand, and
22901 by negating the second operand. */
22904 negate_data_op (unsigned long * instruction
,
22905 unsigned long value
)
22908 unsigned long negated
, inverted
;
22910 negated
= encode_arm_immediate (-value
);
22911 inverted
= encode_arm_immediate (~value
);
22913 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22916 /* First negates. */
22917 case OPCODE_SUB
: /* ADD <-> SUB */
22918 new_inst
= OPCODE_ADD
;
22923 new_inst
= OPCODE_SUB
;
22927 case OPCODE_CMP
: /* CMP <-> CMN */
22928 new_inst
= OPCODE_CMN
;
22933 new_inst
= OPCODE_CMP
;
22937 /* Now Inverted ops. */
22938 case OPCODE_MOV
: /* MOV <-> MVN */
22939 new_inst
= OPCODE_MVN
;
22944 new_inst
= OPCODE_MOV
;
22948 case OPCODE_AND
: /* AND <-> BIC */
22949 new_inst
= OPCODE_BIC
;
22954 new_inst
= OPCODE_AND
;
22958 case OPCODE_ADC
: /* ADC <-> SBC */
22959 new_inst
= OPCODE_SBC
;
22964 new_inst
= OPCODE_ADC
;
22968 /* We cannot do anything. */
22973 if (value
== (unsigned) FAIL
)
22976 *instruction
&= OPCODE_MASK
;
22977 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22981 /* Like negate_data_op, but for Thumb-2. */
22983 static unsigned int
22984 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22988 unsigned int negated
, inverted
;
22990 negated
= encode_thumb32_immediate (-value
);
22991 inverted
= encode_thumb32_immediate (~value
);
22993 rd
= (*instruction
>> 8) & 0xf;
22994 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22997 /* ADD <-> SUB. Includes CMP <-> CMN. */
22998 case T2_OPCODE_SUB
:
22999 new_inst
= T2_OPCODE_ADD
;
23003 case T2_OPCODE_ADD
:
23004 new_inst
= T2_OPCODE_SUB
;
23008 /* ORR <-> ORN. Includes MOV <-> MVN. */
23009 case T2_OPCODE_ORR
:
23010 new_inst
= T2_OPCODE_ORN
;
23014 case T2_OPCODE_ORN
:
23015 new_inst
= T2_OPCODE_ORR
;
23019 /* AND <-> BIC. TST has no inverted equivalent. */
23020 case T2_OPCODE_AND
:
23021 new_inst
= T2_OPCODE_BIC
;
23028 case T2_OPCODE_BIC
:
23029 new_inst
= T2_OPCODE_AND
;
23034 case T2_OPCODE_ADC
:
23035 new_inst
= T2_OPCODE_SBC
;
23039 case T2_OPCODE_SBC
:
23040 new_inst
= T2_OPCODE_ADC
;
23044 /* We cannot do anything. */
23049 if (value
== (unsigned int)FAIL
)
23052 *instruction
&= T2_OPCODE_MASK
;
23053 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23057 /* Read a 32-bit thumb instruction from buf. */
23059 static unsigned long
23060 get_thumb32_insn (char * buf
)
23062 unsigned long insn
;
23063 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23064 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23069 /* We usually want to set the low bit on the address of thumb function
23070 symbols. In particular .word foo - . should have the low bit set.
23071 Generic code tries to fold the difference of two symbols to
23072 a constant. Prevent this and force a relocation when the first symbols
23073 is a thumb function. */
23076 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23078 if (op
== O_subtract
23079 && l
->X_op
== O_symbol
23080 && r
->X_op
== O_symbol
23081 && THUMB_IS_FUNC (l
->X_add_symbol
))
23083 l
->X_op
= O_subtract
;
23084 l
->X_op_symbol
= r
->X_add_symbol
;
23085 l
->X_add_number
-= r
->X_add_number
;
23089 /* Process as normal. */
23093 /* Encode Thumb2 unconditional branches and calls. The encoding
23094 for the 2 are identical for the immediate values. */
23097 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23099 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23102 addressT S
, I1
, I2
, lo
, hi
;
23104 S
= (value
>> 24) & 0x01;
23105 I1
= (value
>> 23) & 0x01;
23106 I2
= (value
>> 22) & 0x01;
23107 hi
= (value
>> 12) & 0x3ff;
23108 lo
= (value
>> 1) & 0x7ff;
23109 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23110 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23111 newval
|= (S
<< 10) | hi
;
23112 newval2
&= ~T2I1I2MASK
;
23113 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23114 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23115 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23119 md_apply_fix (fixS
* fixP
,
23123 offsetT value
= * valP
;
23125 unsigned int newimm
;
23126 unsigned long temp
;
23128 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23130 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23132 /* Note whether this will delete the relocation. */
23134 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23137 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23138 consistency with the behaviour on 32-bit hosts. Remember value
23140 value
&= 0xffffffff;
23141 value
^= 0x80000000;
23142 value
-= 0x80000000;
23145 fixP
->fx_addnumber
= value
;
23147 /* Same treatment for fixP->fx_offset. */
23148 fixP
->fx_offset
&= 0xffffffff;
23149 fixP
->fx_offset
^= 0x80000000;
23150 fixP
->fx_offset
-= 0x80000000;
23152 switch (fixP
->fx_r_type
)
23154 case BFD_RELOC_NONE
:
23155 /* This will need to go in the object file. */
23159 case BFD_RELOC_ARM_IMMEDIATE
:
23160 /* We claim that this fixup has been processed here,
23161 even if in fact we generate an error because we do
23162 not have a reloc for it, so tc_gen_reloc will reject it. */
23165 if (fixP
->fx_addsy
)
23167 const char *msg
= 0;
23169 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23170 msg
= _("undefined symbol %s used as an immediate value");
23171 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23172 msg
= _("symbol %s is in a different section");
23173 else if (S_IS_WEAK (fixP
->fx_addsy
))
23174 msg
= _("symbol %s is weak and may be overridden later");
23178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23179 msg
, S_GET_NAME (fixP
->fx_addsy
));
23184 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23186 /* If the offset is negative, we should use encoding A2 for ADR. */
23187 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23188 newimm
= negate_data_op (&temp
, value
);
23191 newimm
= encode_arm_immediate (value
);
23193 /* If the instruction will fail, see if we can fix things up by
23194 changing the opcode. */
23195 if (newimm
== (unsigned int) FAIL
)
23196 newimm
= negate_data_op (&temp
, value
);
23197 /* MOV accepts both ARM modified immediate (A1 encoding) and
23198 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23199 When disassembling, MOV is preferred when there is no encoding
23201 if (newimm
== (unsigned int) FAIL
23202 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23203 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23204 && !((temp
>> SBIT_SHIFT
) & 0x1)
23205 && value
>= 0 && value
<= 0xffff)
23207 /* Clear bits[23:20] to change encoding from A1 to A2. */
23208 temp
&= 0xff0fffff;
23209 /* Encoding high 4bits imm. Code below will encode the remaining
23211 temp
|= (value
& 0x0000f000) << 4;
23212 newimm
= value
& 0x00000fff;
23216 if (newimm
== (unsigned int) FAIL
)
23218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23219 _("invalid constant (%lx) after fixup"),
23220 (unsigned long) value
);
23224 newimm
|= (temp
& 0xfffff000);
23225 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23228 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23230 unsigned int highpart
= 0;
23231 unsigned int newinsn
= 0xe1a00000; /* nop. */
23233 if (fixP
->fx_addsy
)
23235 const char *msg
= 0;
23237 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23238 msg
= _("undefined symbol %s used as an immediate value");
23239 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23240 msg
= _("symbol %s is in a different section");
23241 else if (S_IS_WEAK (fixP
->fx_addsy
))
23242 msg
= _("symbol %s is weak and may be overridden later");
23246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23247 msg
, S_GET_NAME (fixP
->fx_addsy
));
23252 newimm
= encode_arm_immediate (value
);
23253 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23255 /* If the instruction will fail, see if we can fix things up by
23256 changing the opcode. */
23257 if (newimm
== (unsigned int) FAIL
23258 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23260 /* No ? OK - try using two ADD instructions to generate
23262 newimm
= validate_immediate_twopart (value
, & highpart
);
23264 /* Yes - then make sure that the second instruction is
23266 if (newimm
!= (unsigned int) FAIL
)
23268 /* Still No ? Try using a negated value. */
23269 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23270 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23271 /* Otherwise - give up. */
23274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23275 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23280 /* Replace the first operand in the 2nd instruction (which
23281 is the PC) with the destination register. We have
23282 already added in the PC in the first instruction and we
23283 do not want to do it again. */
23284 newinsn
&= ~ 0xf0000;
23285 newinsn
|= ((newinsn
& 0x0f000) << 4);
23288 newimm
|= (temp
& 0xfffff000);
23289 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23291 highpart
|= (newinsn
& 0xfffff000);
23292 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23296 case BFD_RELOC_ARM_OFFSET_IMM
:
23297 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23299 /* Fall through. */
23301 case BFD_RELOC_ARM_LITERAL
:
23307 if (validate_offset_imm (value
, 0) == FAIL
)
23309 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23311 _("invalid literal constant: pool needs to be closer"));
23313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23314 _("bad immediate value for offset (%ld)"),
23319 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23321 newval
&= 0xfffff000;
23324 newval
&= 0xff7ff000;
23325 newval
|= value
| (sign
? INDEX_UP
: 0);
23327 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23330 case BFD_RELOC_ARM_OFFSET_IMM8
:
23331 case BFD_RELOC_ARM_HWLITERAL
:
23337 if (validate_offset_imm (value
, 1) == FAIL
)
23339 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23341 _("invalid literal constant: pool needs to be closer"));
23343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23344 _("bad immediate value for 8-bit offset (%ld)"),
23349 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23351 newval
&= 0xfffff0f0;
23354 newval
&= 0xff7ff0f0;
23355 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23357 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23360 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23361 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23363 _("bad immediate value for offset (%ld)"), (long) value
);
23366 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23368 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23371 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23372 /* This is a complicated relocation used for all varieties of Thumb32
23373 load/store instruction with immediate offset:
23375 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23376 *4, optional writeback(W)
23377 (doubleword load/store)
23379 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23380 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23381 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23382 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23383 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23385 Uppercase letters indicate bits that are already encoded at
23386 this point. Lowercase letters are our problem. For the
23387 second block of instructions, the secondary opcode nybble
23388 (bits 8..11) is present, and bit 23 is zero, even if this is
23389 a PC-relative operation. */
23390 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23392 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23394 if ((newval
& 0xf0000000) == 0xe0000000)
23396 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23398 newval
|= (1 << 23);
23401 if (value
% 4 != 0)
23403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23404 _("offset not a multiple of 4"));
23410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23411 _("offset out of range"));
23416 else if ((newval
& 0x000f0000) == 0x000f0000)
23418 /* PC-relative, 12-bit offset. */
23420 newval
|= (1 << 23);
23425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23426 _("offset out of range"));
23431 else if ((newval
& 0x00000100) == 0x00000100)
23433 /* Writeback: 8-bit, +/- offset. */
23435 newval
|= (1 << 9);
23440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23441 _("offset out of range"));
23446 else if ((newval
& 0x00000f00) == 0x00000e00)
23448 /* T-instruction: positive 8-bit offset. */
23449 if (value
< 0 || value
> 0xff)
23451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23452 _("offset out of range"));
23460 /* Positive 12-bit or negative 8-bit offset. */
23464 newval
|= (1 << 23);
23474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23475 _("offset out of range"));
23482 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23483 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23486 case BFD_RELOC_ARM_SHIFT_IMM
:
23487 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23488 if (((unsigned long) value
) > 32
23490 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23493 _("shift expression is too large"));
23498 /* Shifts of zero must be done as lsl. */
23500 else if (value
== 32)
23502 newval
&= 0xfffff07f;
23503 newval
|= (value
& 0x1f) << 7;
23504 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23507 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23508 case BFD_RELOC_ARM_T32_ADD_IMM
:
23509 case BFD_RELOC_ARM_T32_IMM12
:
23510 case BFD_RELOC_ARM_T32_ADD_PC12
:
23511 /* We claim that this fixup has been processed here,
23512 even if in fact we generate an error because we do
23513 not have a reloc for it, so tc_gen_reloc will reject it. */
23517 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23520 _("undefined symbol %s used as an immediate value"),
23521 S_GET_NAME (fixP
->fx_addsy
));
23525 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23527 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23530 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23531 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23532 Thumb2 modified immediate encoding (T2). */
23533 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23534 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23536 newimm
= encode_thumb32_immediate (value
);
23537 if (newimm
== (unsigned int) FAIL
)
23538 newimm
= thumb32_negate_data_op (&newval
, value
);
23540 if (newimm
== (unsigned int) FAIL
)
23542 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23544 /* Turn add/sum into addw/subw. */
23545 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23546 newval
= (newval
& 0xfeffffff) | 0x02000000;
23547 /* No flat 12-bit imm encoding for addsw/subsw. */
23548 if ((newval
& 0x00100000) == 0)
23550 /* 12 bit immediate for addw/subw. */
23554 newval
^= 0x00a00000;
23557 newimm
= (unsigned int) FAIL
;
23564 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23565 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23566 disassembling, MOV is preferred when there is no encoding
23568 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23569 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23570 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23571 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23572 && value
>= 0 && value
<=0xffff)
23574 /* Toggle bit[25] to change encoding from T2 to T3. */
23576 /* Clear bits[19:16]. */
23577 newval
&= 0xfff0ffff;
23578 /* Encoding high 4bits imm. Code below will encode the
23579 remaining low 12bits. */
23580 newval
|= (value
& 0x0000f000) << 4;
23581 newimm
= value
& 0x00000fff;
23586 if (newimm
== (unsigned int)FAIL
)
23588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23589 _("invalid constant (%lx) after fixup"),
23590 (unsigned long) value
);
23594 newval
|= (newimm
& 0x800) << 15;
23595 newval
|= (newimm
& 0x700) << 4;
23596 newval
|= (newimm
& 0x0ff);
23598 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23599 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23602 case BFD_RELOC_ARM_SMC
:
23603 if (((unsigned long) value
) > 0xffff)
23604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23605 _("invalid smc expression"));
23606 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23607 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23608 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23611 case BFD_RELOC_ARM_HVC
:
23612 if (((unsigned long) value
) > 0xffff)
23613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23614 _("invalid hvc expression"));
23615 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23616 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23617 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23620 case BFD_RELOC_ARM_SWI
:
23621 if (fixP
->tc_fix_data
!= 0)
23623 if (((unsigned long) value
) > 0xff)
23624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23625 _("invalid swi expression"));
23626 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23628 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23632 if (((unsigned long) value
) > 0x00ffffff)
23633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23634 _("invalid swi expression"));
23635 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23637 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23641 case BFD_RELOC_ARM_MULTI
:
23642 if (((unsigned long) value
) > 0xffff)
23643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23644 _("invalid expression in load/store multiple"));
23645 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23646 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23650 case BFD_RELOC_ARM_PCREL_CALL
:
23652 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23654 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23655 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23656 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23657 /* Flip the bl to blx. This is a simple flip
23658 bit here because we generate PCREL_CALL for
23659 unconditional bls. */
23661 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23662 newval
= newval
| 0x10000000;
23663 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23669 goto arm_branch_common
;
23671 case BFD_RELOC_ARM_PCREL_JUMP
:
23672 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23674 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23675 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23676 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23678 /* This would map to a bl<cond>, b<cond>,
23679 b<always> to a Thumb function. We
23680 need to force a relocation for this particular
23682 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23685 /* Fall through. */
23687 case BFD_RELOC_ARM_PLT32
:
23689 case BFD_RELOC_ARM_PCREL_BRANCH
:
23691 goto arm_branch_common
;
23693 case BFD_RELOC_ARM_PCREL_BLX
:
23696 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23698 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23699 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23700 && ARM_IS_FUNC (fixP
->fx_addsy
))
23702 /* Flip the blx to a bl and warn. */
23703 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23704 newval
= 0xeb000000;
23705 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23706 _("blx to '%s' an ARM ISA state function changed to bl"),
23708 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23714 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23715 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23719 /* We are going to store value (shifted right by two) in the
23720 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23721 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23725 _("misaligned branch destination"));
23726 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23727 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23730 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23732 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23733 newval
|= (value
>> 2) & 0x00ffffff;
23734 /* Set the H bit on BLX instructions. */
23738 newval
|= 0x01000000;
23740 newval
&= ~0x01000000;
23742 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23746 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23747 /* CBZ can only branch forward. */
23749 /* Attempts to use CBZ to branch to the next instruction
23750 (which, strictly speaking, are prohibited) will be turned into
23753 FIXME: It may be better to remove the instruction completely and
23754 perform relaxation. */
23757 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23758 newval
= 0xbf00; /* NOP encoding T1 */
23759 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23766 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23768 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23769 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23770 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23775 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23776 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23779 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23781 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23782 newval
|= (value
& 0x1ff) >> 1;
23783 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23787 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23788 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23791 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23793 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23794 newval
|= (value
& 0xfff) >> 1;
23795 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23799 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23801 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23802 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23803 && ARM_IS_FUNC (fixP
->fx_addsy
)
23804 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23806 /* Force a relocation for a branch 20 bits wide. */
23809 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23811 _("conditional branch out of range"));
23813 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23816 addressT S
, J1
, J2
, lo
, hi
;
23818 S
= (value
& 0x00100000) >> 20;
23819 J2
= (value
& 0x00080000) >> 19;
23820 J1
= (value
& 0x00040000) >> 18;
23821 hi
= (value
& 0x0003f000) >> 12;
23822 lo
= (value
& 0x00000ffe) >> 1;
23824 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23825 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23826 newval
|= (S
<< 10) | hi
;
23827 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23828 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23829 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23833 case BFD_RELOC_THUMB_PCREL_BLX
:
23834 /* If there is a blx from a thumb state function to
23835 another thumb function flip this to a bl and warn
23839 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23840 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23841 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23843 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23844 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23845 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23847 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23848 newval
= newval
| 0x1000;
23849 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23850 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23855 goto thumb_bl_common
;
23857 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23858 /* A bl from Thumb state ISA to an internal ARM state function
23859 is converted to a blx. */
23861 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23862 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23863 && ARM_IS_FUNC (fixP
->fx_addsy
)
23864 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23866 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23867 newval
= newval
& ~0x1000;
23868 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23869 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23875 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23876 /* For a BLX instruction, make sure that the relocation is rounded up
23877 to a word boundary. This follows the semantics of the instruction
23878 which specifies that bit 1 of the target address will come from bit
23879 1 of the base address. */
23880 value
= (value
+ 3) & ~ 3;
23883 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23884 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23885 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23888 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23890 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23892 else if ((value
& ~0x1ffffff)
23893 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23895 _("Thumb2 branch out of range"));
23898 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23899 encode_thumb2_b_bl_offset (buf
, value
);
23903 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23904 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23908 encode_thumb2_b_bl_offset (buf
, value
);
23913 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23918 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23919 md_number_to_chars (buf
, value
, 2);
23923 case BFD_RELOC_ARM_TLS_CALL
:
23924 case BFD_RELOC_ARM_THM_TLS_CALL
:
23925 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23926 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23927 case BFD_RELOC_ARM_TLS_GOTDESC
:
23928 case BFD_RELOC_ARM_TLS_GD32
:
23929 case BFD_RELOC_ARM_TLS_LE32
:
23930 case BFD_RELOC_ARM_TLS_IE32
:
23931 case BFD_RELOC_ARM_TLS_LDM32
:
23932 case BFD_RELOC_ARM_TLS_LDO32
:
23933 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23936 case BFD_RELOC_ARM_GOT32
:
23937 case BFD_RELOC_ARM_GOTOFF
:
23940 case BFD_RELOC_ARM_GOT_PREL
:
23941 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23942 md_number_to_chars (buf
, value
, 4);
23945 case BFD_RELOC_ARM_TARGET2
:
23946 /* TARGET2 is not partial-inplace, so we need to write the
23947 addend here for REL targets, because it won't be written out
23948 during reloc processing later. */
23949 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23950 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23954 case BFD_RELOC_RVA
:
23956 case BFD_RELOC_ARM_TARGET1
:
23957 case BFD_RELOC_ARM_ROSEGREL32
:
23958 case BFD_RELOC_ARM_SBREL32
:
23959 case BFD_RELOC_32_PCREL
:
23961 case BFD_RELOC_32_SECREL
:
23963 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23965 /* For WinCE we only do this for pcrel fixups. */
23966 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23968 md_number_to_chars (buf
, value
, 4);
23972 case BFD_RELOC_ARM_PREL31
:
23973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23975 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23976 if ((value
^ (value
>> 1)) & 0x40000000)
23978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23979 _("rel31 relocation overflow"));
23981 newval
|= value
& 0x7fffffff;
23982 md_number_to_chars (buf
, newval
, 4);
23987 case BFD_RELOC_ARM_CP_OFF_IMM
:
23988 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23989 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23990 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23992 newval
= get_thumb32_insn (buf
);
23993 if ((newval
& 0x0f200f00) == 0x0d000900)
23995 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23996 has permitted values that are multiples of 2, in the range 0
23998 if (value
< -510 || value
> 510 || (value
& 1))
23999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24000 _("co-processor offset out of range"));
24002 else if (value
< -1023 || value
> 1023 || (value
& 3))
24003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24004 _("co-processor offset out of range"));
24009 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24010 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24011 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24013 newval
= get_thumb32_insn (buf
);
24015 newval
&= 0xffffff00;
24018 newval
&= 0xff7fff00;
24019 if ((newval
& 0x0f200f00) == 0x0d000900)
24021 /* This is a fp16 vstr/vldr.
24023 It requires the immediate offset in the instruction is shifted
24024 left by 1 to be a half-word offset.
24026 Here, left shift by 1 first, and later right shift by 2
24027 should get the right offset. */
24030 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24032 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24033 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24034 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24036 put_thumb32_insn (buf
, newval
);
24039 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24040 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24041 if (value
< -255 || value
> 255)
24042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24043 _("co-processor offset out of range"));
24045 goto cp_off_common
;
24047 case BFD_RELOC_ARM_THUMB_OFFSET
:
24048 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24049 /* Exactly what ranges, and where the offset is inserted depends
24050 on the type of instruction, we can establish this from the
24052 switch (newval
>> 12)
24054 case 4: /* PC load. */
24055 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24056 forced to zero for these loads; md_pcrel_from has already
24057 compensated for this. */
24059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24060 _("invalid offset, target not word aligned (0x%08lX)"),
24061 (((unsigned long) fixP
->fx_frag
->fr_address
24062 + (unsigned long) fixP
->fx_where
) & ~3)
24063 + (unsigned long) value
);
24065 if (value
& ~0x3fc)
24066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24067 _("invalid offset, value too big (0x%08lX)"),
24070 newval
|= value
>> 2;
24073 case 9: /* SP load/store. */
24074 if (value
& ~0x3fc)
24075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24076 _("invalid offset, value too big (0x%08lX)"),
24078 newval
|= value
>> 2;
24081 case 6: /* Word load/store. */
24083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24084 _("invalid offset, value too big (0x%08lX)"),
24086 newval
|= value
<< 4; /* 6 - 2. */
24089 case 7: /* Byte load/store. */
24091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24092 _("invalid offset, value too big (0x%08lX)"),
24094 newval
|= value
<< 6;
24097 case 8: /* Halfword load/store. */
24099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24100 _("invalid offset, value too big (0x%08lX)"),
24102 newval
|= value
<< 5; /* 6 - 1. */
24106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24107 "Unable to process relocation for thumb opcode: %lx",
24108 (unsigned long) newval
);
24111 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24114 case BFD_RELOC_ARM_THUMB_ADD
:
24115 /* This is a complicated relocation, since we use it for all of
24116 the following immediate relocations:
24120 9bit ADD/SUB SP word-aligned
24121 10bit ADD PC/SP word-aligned
24123 The type of instruction being processed is encoded in the
24130 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24132 int rd
= (newval
>> 4) & 0xf;
24133 int rs
= newval
& 0xf;
24134 int subtract
= !!(newval
& 0x8000);
24136 /* Check for HI regs, only very restricted cases allowed:
24137 Adjusting SP, and using PC or SP to get an address. */
24138 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24139 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24141 _("invalid Hi register with immediate"));
24143 /* If value is negative, choose the opposite instruction. */
24147 subtract
= !subtract
;
24149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24150 _("immediate value out of range"));
24155 if (value
& ~0x1fc)
24156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24157 _("invalid immediate for stack address calculation"));
24158 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24159 newval
|= value
>> 2;
24161 else if (rs
== REG_PC
|| rs
== REG_SP
)
24163 /* PR gas/18541. If the addition is for a defined symbol
24164 within range of an ADR instruction then accept it. */
24167 && fixP
->fx_addsy
!= NULL
)
24171 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24172 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24173 || S_IS_WEAK (fixP
->fx_addsy
))
24175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24176 _("address calculation needs a strongly defined nearby symbol"));
24180 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24182 /* Round up to the next 4-byte boundary. */
24187 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24192 _("symbol too far away"));
24202 if (subtract
|| value
& ~0x3fc)
24203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24204 _("invalid immediate for address calculation (value = 0x%08lX)"),
24205 (unsigned long) (subtract
? - value
: value
));
24206 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24208 newval
|= value
>> 2;
24213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24214 _("immediate value out of range"));
24215 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24216 newval
|= (rd
<< 8) | value
;
24221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24222 _("immediate value out of range"));
24223 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24224 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24227 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24230 case BFD_RELOC_ARM_THUMB_IMM
:
24231 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24232 if (value
< 0 || value
> 255)
24233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24234 _("invalid immediate: %ld is out of range"),
24237 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24240 case BFD_RELOC_ARM_THUMB_SHIFT
:
24241 /* 5bit shift value (0..32). LSL cannot take 32. */
24242 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24243 temp
= newval
& 0xf800;
24244 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24246 _("invalid shift value: %ld"), (long) value
);
24247 /* Shifts of zero must be encoded as LSL. */
24249 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24250 /* Shifts of 32 are encoded as zero. */
24251 else if (value
== 32)
24253 newval
|= value
<< 6;
24254 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24257 case BFD_RELOC_VTABLE_INHERIT
:
24258 case BFD_RELOC_VTABLE_ENTRY
:
24262 case BFD_RELOC_ARM_MOVW
:
24263 case BFD_RELOC_ARM_MOVT
:
24264 case BFD_RELOC_ARM_THUMB_MOVW
:
24265 case BFD_RELOC_ARM_THUMB_MOVT
:
24266 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24268 /* REL format relocations are limited to a 16-bit addend. */
24269 if (!fixP
->fx_done
)
24271 if (value
< -0x8000 || value
> 0x7fff)
24272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24273 _("offset out of range"));
24275 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24276 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24281 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24282 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24284 newval
= get_thumb32_insn (buf
);
24285 newval
&= 0xfbf08f00;
24286 newval
|= (value
& 0xf000) << 4;
24287 newval
|= (value
& 0x0800) << 15;
24288 newval
|= (value
& 0x0700) << 4;
24289 newval
|= (value
& 0x00ff);
24290 put_thumb32_insn (buf
, newval
);
24294 newval
= md_chars_to_number (buf
, 4);
24295 newval
&= 0xfff0f000;
24296 newval
|= value
& 0x0fff;
24297 newval
|= (value
& 0xf000) << 4;
24298 md_number_to_chars (buf
, newval
, 4);
24303 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24304 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24305 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24306 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24307 gas_assert (!fixP
->fx_done
);
24310 bfd_boolean is_mov
;
24311 bfd_vma encoded_addend
= value
;
24313 /* Check that addend can be encoded in instruction. */
24314 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24316 _("the offset 0x%08lX is not representable"),
24317 (unsigned long) encoded_addend
);
24319 /* Extract the instruction. */
24320 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24321 is_mov
= (insn
& 0xf800) == 0x2000;
24326 if (!seg
->use_rela_p
)
24327 insn
|= encoded_addend
;
24333 /* Extract the instruction. */
24334 /* Encoding is the following
24339 /* The following conditions must be true :
24344 rd
= (insn
>> 4) & 0xf;
24346 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24348 _("Unable to process relocation for thumb opcode: %lx"),
24349 (unsigned long) insn
);
24351 /* Encode as ADD immediate8 thumb 1 code. */
24352 insn
= 0x3000 | (rd
<< 8);
24354 /* Place the encoded addend into the first 8 bits of the
24356 if (!seg
->use_rela_p
)
24357 insn
|= encoded_addend
;
24360 /* Update the instruction. */
24361 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24365 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24366 case BFD_RELOC_ARM_ALU_PC_G0
:
24367 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24368 case BFD_RELOC_ARM_ALU_PC_G1
:
24369 case BFD_RELOC_ARM_ALU_PC_G2
:
24370 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24371 case BFD_RELOC_ARM_ALU_SB_G0
:
24372 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24373 case BFD_RELOC_ARM_ALU_SB_G1
:
24374 case BFD_RELOC_ARM_ALU_SB_G2
:
24375 gas_assert (!fixP
->fx_done
);
24376 if (!seg
->use_rela_p
)
24379 bfd_vma encoded_addend
;
24380 bfd_vma addend_abs
= abs (value
);
24382 /* Check that the absolute value of the addend can be
24383 expressed as an 8-bit constant plus a rotation. */
24384 encoded_addend
= encode_arm_immediate (addend_abs
);
24385 if (encoded_addend
== (unsigned int) FAIL
)
24386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24387 _("the offset 0x%08lX is not representable"),
24388 (unsigned long) addend_abs
);
24390 /* Extract the instruction. */
24391 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24393 /* If the addend is positive, use an ADD instruction.
24394 Otherwise use a SUB. Take care not to destroy the S bit. */
24395 insn
&= 0xff1fffff;
24401 /* Place the encoded addend into the first 12 bits of the
24403 insn
&= 0xfffff000;
24404 insn
|= encoded_addend
;
24406 /* Update the instruction. */
24407 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24411 case BFD_RELOC_ARM_LDR_PC_G0
:
24412 case BFD_RELOC_ARM_LDR_PC_G1
:
24413 case BFD_RELOC_ARM_LDR_PC_G2
:
24414 case BFD_RELOC_ARM_LDR_SB_G0
:
24415 case BFD_RELOC_ARM_LDR_SB_G1
:
24416 case BFD_RELOC_ARM_LDR_SB_G2
:
24417 gas_assert (!fixP
->fx_done
);
24418 if (!seg
->use_rela_p
)
24421 bfd_vma addend_abs
= abs (value
);
24423 /* Check that the absolute value of the addend can be
24424 encoded in 12 bits. */
24425 if (addend_abs
>= 0x1000)
24426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24427 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24428 (unsigned long) addend_abs
);
24430 /* Extract the instruction. */
24431 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24433 /* If the addend is negative, clear bit 23 of the instruction.
24434 Otherwise set it. */
24436 insn
&= ~(1 << 23);
24440 /* Place the absolute value of the addend into the first 12 bits
24441 of the instruction. */
24442 insn
&= 0xfffff000;
24443 insn
|= addend_abs
;
24445 /* Update the instruction. */
24446 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24450 case BFD_RELOC_ARM_LDRS_PC_G0
:
24451 case BFD_RELOC_ARM_LDRS_PC_G1
:
24452 case BFD_RELOC_ARM_LDRS_PC_G2
:
24453 case BFD_RELOC_ARM_LDRS_SB_G0
:
24454 case BFD_RELOC_ARM_LDRS_SB_G1
:
24455 case BFD_RELOC_ARM_LDRS_SB_G2
:
24456 gas_assert (!fixP
->fx_done
);
24457 if (!seg
->use_rela_p
)
24460 bfd_vma addend_abs
= abs (value
);
24462 /* Check that the absolute value of the addend can be
24463 encoded in 8 bits. */
24464 if (addend_abs
>= 0x100)
24465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24466 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24467 (unsigned long) addend_abs
);
24469 /* Extract the instruction. */
24470 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24472 /* If the addend is negative, clear bit 23 of the instruction.
24473 Otherwise set it. */
24475 insn
&= ~(1 << 23);
24479 /* Place the first four bits of the absolute value of the addend
24480 into the first 4 bits of the instruction, and the remaining
24481 four into bits 8 .. 11. */
24482 insn
&= 0xfffff0f0;
24483 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24485 /* Update the instruction. */
24486 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24490 case BFD_RELOC_ARM_LDC_PC_G0
:
24491 case BFD_RELOC_ARM_LDC_PC_G1
:
24492 case BFD_RELOC_ARM_LDC_PC_G2
:
24493 case BFD_RELOC_ARM_LDC_SB_G0
:
24494 case BFD_RELOC_ARM_LDC_SB_G1
:
24495 case BFD_RELOC_ARM_LDC_SB_G2
:
24496 gas_assert (!fixP
->fx_done
);
24497 if (!seg
->use_rela_p
)
24500 bfd_vma addend_abs
= abs (value
);
24502 /* Check that the absolute value of the addend is a multiple of
24503 four and, when divided by four, fits in 8 bits. */
24504 if (addend_abs
& 0x3)
24505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24506 _("bad offset 0x%08lX (must be word-aligned)"),
24507 (unsigned long) addend_abs
);
24509 if ((addend_abs
>> 2) > 0xff)
24510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24511 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24512 (unsigned long) addend_abs
);
24514 /* Extract the instruction. */
24515 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24517 /* If the addend is negative, clear bit 23 of the instruction.
24518 Otherwise set it. */
24520 insn
&= ~(1 << 23);
24524 /* Place the addend (divided by four) into the first eight
24525 bits of the instruction. */
24526 insn
&= 0xfffffff0;
24527 insn
|= addend_abs
>> 2;
24529 /* Update the instruction. */
24530 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24534 case BFD_RELOC_ARM_V4BX
:
24535 /* This will need to go in the object file. */
24539 case BFD_RELOC_UNUSED
:
24541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24542 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24546 /* Translate internal representation of relocation info to BFD target
24550 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24553 bfd_reloc_code_real_type code
;
24555 reloc
= XNEW (arelent
);
24557 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24558 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24559 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24561 if (fixp
->fx_pcrel
)
24563 if (section
->use_rela_p
)
24564 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24566 fixp
->fx_offset
= reloc
->address
;
24568 reloc
->addend
= fixp
->fx_offset
;
24570 switch (fixp
->fx_r_type
)
24573 if (fixp
->fx_pcrel
)
24575 code
= BFD_RELOC_8_PCREL
;
24578 /* Fall through. */
24581 if (fixp
->fx_pcrel
)
24583 code
= BFD_RELOC_16_PCREL
;
24586 /* Fall through. */
24589 if (fixp
->fx_pcrel
)
24591 code
= BFD_RELOC_32_PCREL
;
24594 /* Fall through. */
24596 case BFD_RELOC_ARM_MOVW
:
24597 if (fixp
->fx_pcrel
)
24599 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24602 /* Fall through. */
24604 case BFD_RELOC_ARM_MOVT
:
24605 if (fixp
->fx_pcrel
)
24607 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24610 /* Fall through. */
24612 case BFD_RELOC_ARM_THUMB_MOVW
:
24613 if (fixp
->fx_pcrel
)
24615 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24618 /* Fall through. */
24620 case BFD_RELOC_ARM_THUMB_MOVT
:
24621 if (fixp
->fx_pcrel
)
24623 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24626 /* Fall through. */
24628 case BFD_RELOC_NONE
:
24629 case BFD_RELOC_ARM_PCREL_BRANCH
:
24630 case BFD_RELOC_ARM_PCREL_BLX
:
24631 case BFD_RELOC_RVA
:
24632 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24633 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24634 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24635 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24636 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24637 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24638 case BFD_RELOC_VTABLE_ENTRY
:
24639 case BFD_RELOC_VTABLE_INHERIT
:
24641 case BFD_RELOC_32_SECREL
:
24643 code
= fixp
->fx_r_type
;
24646 case BFD_RELOC_THUMB_PCREL_BLX
:
24648 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24649 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24652 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24655 case BFD_RELOC_ARM_LITERAL
:
24656 case BFD_RELOC_ARM_HWLITERAL
:
24657 /* If this is called then the a literal has
24658 been referenced across a section boundary. */
24659 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24660 _("literal referenced across section boundary"));
24664 case BFD_RELOC_ARM_TLS_CALL
:
24665 case BFD_RELOC_ARM_THM_TLS_CALL
:
24666 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24667 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24668 case BFD_RELOC_ARM_GOT32
:
24669 case BFD_RELOC_ARM_GOTOFF
:
24670 case BFD_RELOC_ARM_GOT_PREL
:
24671 case BFD_RELOC_ARM_PLT32
:
24672 case BFD_RELOC_ARM_TARGET1
:
24673 case BFD_RELOC_ARM_ROSEGREL32
:
24674 case BFD_RELOC_ARM_SBREL32
:
24675 case BFD_RELOC_ARM_PREL31
:
24676 case BFD_RELOC_ARM_TARGET2
:
24677 case BFD_RELOC_ARM_TLS_LDO32
:
24678 case BFD_RELOC_ARM_PCREL_CALL
:
24679 case BFD_RELOC_ARM_PCREL_JUMP
:
24680 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24681 case BFD_RELOC_ARM_ALU_PC_G0
:
24682 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24683 case BFD_RELOC_ARM_ALU_PC_G1
:
24684 case BFD_RELOC_ARM_ALU_PC_G2
:
24685 case BFD_RELOC_ARM_LDR_PC_G0
:
24686 case BFD_RELOC_ARM_LDR_PC_G1
:
24687 case BFD_RELOC_ARM_LDR_PC_G2
:
24688 case BFD_RELOC_ARM_LDRS_PC_G0
:
24689 case BFD_RELOC_ARM_LDRS_PC_G1
:
24690 case BFD_RELOC_ARM_LDRS_PC_G2
:
24691 case BFD_RELOC_ARM_LDC_PC_G0
:
24692 case BFD_RELOC_ARM_LDC_PC_G1
:
24693 case BFD_RELOC_ARM_LDC_PC_G2
:
24694 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24695 case BFD_RELOC_ARM_ALU_SB_G0
:
24696 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24697 case BFD_RELOC_ARM_ALU_SB_G1
:
24698 case BFD_RELOC_ARM_ALU_SB_G2
:
24699 case BFD_RELOC_ARM_LDR_SB_G0
:
24700 case BFD_RELOC_ARM_LDR_SB_G1
:
24701 case BFD_RELOC_ARM_LDR_SB_G2
:
24702 case BFD_RELOC_ARM_LDRS_SB_G0
:
24703 case BFD_RELOC_ARM_LDRS_SB_G1
:
24704 case BFD_RELOC_ARM_LDRS_SB_G2
:
24705 case BFD_RELOC_ARM_LDC_SB_G0
:
24706 case BFD_RELOC_ARM_LDC_SB_G1
:
24707 case BFD_RELOC_ARM_LDC_SB_G2
:
24708 case BFD_RELOC_ARM_V4BX
:
24709 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24710 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24711 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24712 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24713 code
= fixp
->fx_r_type
;
24716 case BFD_RELOC_ARM_TLS_GOTDESC
:
24717 case BFD_RELOC_ARM_TLS_GD32
:
24718 case BFD_RELOC_ARM_TLS_LE32
:
24719 case BFD_RELOC_ARM_TLS_IE32
:
24720 case BFD_RELOC_ARM_TLS_LDM32
:
24721 /* BFD will include the symbol's address in the addend.
24722 But we don't want that, so subtract it out again here. */
24723 if (!S_IS_COMMON (fixp
->fx_addsy
))
24724 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24725 code
= fixp
->fx_r_type
;
24729 case BFD_RELOC_ARM_IMMEDIATE
:
24730 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24731 _("internal relocation (type: IMMEDIATE) not fixed up"));
24734 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24735 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24736 _("ADRL used for a symbol not defined in the same file"));
24739 case BFD_RELOC_ARM_OFFSET_IMM
:
24740 if (section
->use_rela_p
)
24742 code
= fixp
->fx_r_type
;
24746 if (fixp
->fx_addsy
!= NULL
24747 && !S_IS_DEFINED (fixp
->fx_addsy
)
24748 && S_IS_LOCAL (fixp
->fx_addsy
))
24750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24751 _("undefined local label `%s'"),
24752 S_GET_NAME (fixp
->fx_addsy
));
24756 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24757 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24764 switch (fixp
->fx_r_type
)
24766 case BFD_RELOC_NONE
: type
= "NONE"; break;
24767 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24768 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24769 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24770 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24771 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24772 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24773 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24774 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24775 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24776 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24777 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24778 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24779 default: type
= _("<unknown>"); break;
24781 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24782 _("cannot represent %s relocation in this object file format"),
24789 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24791 && fixp
->fx_addsy
== GOT_symbol
)
24793 code
= BFD_RELOC_ARM_GOTPC
;
24794 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24798 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24800 if (reloc
->howto
== NULL
)
24802 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24803 _("cannot represent %s relocation in this object file format"),
24804 bfd_get_reloc_code_name (code
));
24808 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24809 vtable entry to be used in the relocation's section offset. */
24810 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24811 reloc
->address
= fixp
->fx_offset
;
24816 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24819 cons_fix_new_arm (fragS
* frag
,
24823 bfd_reloc_code_real_type reloc
)
24828 FIXME: @@ Should look at CPU word size. */
24832 reloc
= BFD_RELOC_8
;
24835 reloc
= BFD_RELOC_16
;
24839 reloc
= BFD_RELOC_32
;
24842 reloc
= BFD_RELOC_64
;
24847 if (exp
->X_op
== O_secrel
)
24849 exp
->X_op
= O_symbol
;
24850 reloc
= BFD_RELOC_32_SECREL
;
24854 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24857 #if defined (OBJ_COFF)
24859 arm_validate_fix (fixS
* fixP
)
24861 /* If the destination of the branch is a defined symbol which does not have
24862 the THUMB_FUNC attribute, then we must be calling a function which has
24863 the (interfacearm) attribute. We look for the Thumb entry point to that
24864 function and change the branch to refer to that function instead. */
24865 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24866 && fixP
->fx_addsy
!= NULL
24867 && S_IS_DEFINED (fixP
->fx_addsy
)
24868 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24870 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24877 arm_force_relocation (struct fix
* fixp
)
24879 #if defined (OBJ_COFF) && defined (TE_PE)
24880 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24884 /* In case we have a call or a branch to a function in ARM ISA mode from
24885 a thumb function or vice-versa force the relocation. These relocations
24886 are cleared off for some cores that might have blx and simple transformations
24890 switch (fixp
->fx_r_type
)
24892 case BFD_RELOC_ARM_PCREL_JUMP
:
24893 case BFD_RELOC_ARM_PCREL_CALL
:
24894 case BFD_RELOC_THUMB_PCREL_BLX
:
24895 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24899 case BFD_RELOC_ARM_PCREL_BLX
:
24900 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24901 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24902 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24903 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24912 /* Resolve these relocations even if the symbol is extern or weak.
24913 Technically this is probably wrong due to symbol preemption.
24914 In practice these relocations do not have enough range to be useful
24915 at dynamic link time, and some code (e.g. in the Linux kernel)
24916 expects these references to be resolved. */
24917 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24918 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24919 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24920 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24921 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24922 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24923 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24924 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24925 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24926 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24927 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24928 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24929 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24930 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24933 /* Always leave these relocations for the linker. */
24934 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24935 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24936 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24939 /* Always generate relocations against function symbols. */
24940 if (fixp
->fx_r_type
== BFD_RELOC_32
24942 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24945 return generic_force_reloc (fixp
);
24948 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24949 /* Relocations against function names must be left unadjusted,
24950 so that the linker can use this information to generate interworking
24951 stubs. The MIPS version of this function
24952 also prevents relocations that are mips-16 specific, but I do not
24953 know why it does this.
24956 There is one other problem that ought to be addressed here, but
24957 which currently is not: Taking the address of a label (rather
24958 than a function) and then later jumping to that address. Such
24959 addresses also ought to have their bottom bit set (assuming that
24960 they reside in Thumb code), but at the moment they will not. */
24963 arm_fix_adjustable (fixS
* fixP
)
24965 if (fixP
->fx_addsy
== NULL
)
24968 /* Preserve relocations against symbols with function type. */
24969 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24972 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24973 && fixP
->fx_subsy
== NULL
)
24976 /* We need the symbol name for the VTABLE entries. */
24977 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24978 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24981 /* Don't allow symbols to be discarded on GOT related relocs. */
24982 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24983 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24984 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24985 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24986 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24987 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24988 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24989 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24990 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24991 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24992 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24993 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24994 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24995 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24998 /* Similarly for group relocations. */
24999 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25000 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25001 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25004 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25005 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25006 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25007 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25008 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25009 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25010 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25011 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25012 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25015 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25016 offsets, so keep these symbols. */
25017 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25018 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25023 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25027 elf32_arm_target_format (void)
25030 return (target_big_endian
25031 ? "elf32-bigarm-symbian"
25032 : "elf32-littlearm-symbian");
25033 #elif defined (TE_VXWORKS)
25034 return (target_big_endian
25035 ? "elf32-bigarm-vxworks"
25036 : "elf32-littlearm-vxworks");
25037 #elif defined (TE_NACL)
25038 return (target_big_endian
25039 ? "elf32-bigarm-nacl"
25040 : "elf32-littlearm-nacl");
25042 if (target_big_endian
)
25043 return "elf32-bigarm";
25045 return "elf32-littlearm";
25050 armelf_frob_symbol (symbolS
* symp
,
25053 elf_frob_symbol (symp
, puntp
);
25057 /* MD interface: Finalization. */
25062 literal_pool
* pool
;
25064 /* Ensure that all the IT blocks are properly closed. */
25065 check_it_blocks_finished ();
25067 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25069 /* Put it at the end of the relevant section. */
25070 subseg_set (pool
->section
, pool
->sub_section
);
25072 arm_elf_change_section ();
25079 /* Remove any excess mapping symbols generated for alignment frags in
25080 SEC. We may have created a mapping symbol before a zero byte
25081 alignment; remove it if there's a mapping symbol after the
25084 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25085 void *dummy ATTRIBUTE_UNUSED
)
25087 segment_info_type
*seginfo
= seg_info (sec
);
25090 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25093 for (fragp
= seginfo
->frchainP
->frch_root
;
25095 fragp
= fragp
->fr_next
)
25097 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25098 fragS
*next
= fragp
->fr_next
;
25100 /* Variable-sized frags have been converted to fixed size by
25101 this point. But if this was variable-sized to start with,
25102 there will be a fixed-size frag after it. So don't handle
25104 if (sym
== NULL
|| next
== NULL
)
25107 if (S_GET_VALUE (sym
) < next
->fr_address
)
25108 /* Not at the end of this frag. */
25110 know (S_GET_VALUE (sym
) == next
->fr_address
);
25114 if (next
->tc_frag_data
.first_map
!= NULL
)
25116 /* Next frag starts with a mapping symbol. Discard this
25118 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25122 if (next
->fr_next
== NULL
)
25124 /* This mapping symbol is at the end of the section. Discard
25126 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25127 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25131 /* As long as we have empty frags without any mapping symbols,
25133 /* If the next frag is non-empty and does not start with a
25134 mapping symbol, then this mapping symbol is required. */
25135 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25138 next
= next
->fr_next
;
25140 while (next
!= NULL
);
25145 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25149 arm_adjust_symtab (void)
25154 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25156 if (ARM_IS_THUMB (sym
))
25158 if (THUMB_IS_FUNC (sym
))
25160 /* Mark the symbol as a Thumb function. */
25161 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25162 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25163 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25165 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25166 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25168 as_bad (_("%s: unexpected function type: %d"),
25169 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25171 else switch (S_GET_STORAGE_CLASS (sym
))
25174 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25177 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25180 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25188 if (ARM_IS_INTERWORK (sym
))
25189 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25196 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25198 if (ARM_IS_THUMB (sym
))
25200 elf_symbol_type
* elf_sym
;
25202 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25203 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25205 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25206 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25208 /* If it's a .thumb_func, declare it as so,
25209 otherwise tag label as .code 16. */
25210 if (THUMB_IS_FUNC (sym
))
25211 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25212 ST_BRANCH_TO_THUMB
);
25213 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25214 elf_sym
->internal_elf_sym
.st_info
=
25215 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25220 /* Remove any overlapping mapping symbols generated by alignment frags. */
25221 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25222 /* Now do generic ELF adjustments. */
25223 elf_adjust_symtab ();
25227 /* MD interface: Initialization. */
25230 set_constant_flonums (void)
25234 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25235 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25239 /* Auto-select Thumb mode if it's the only available instruction set for the
25240 given architecture. */
25243 autoselect_thumb_from_cpu_variant (void)
25245 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25246 opcode_select (16);
25255 if ( (arm_ops_hsh
= hash_new ()) == NULL
25256 || (arm_cond_hsh
= hash_new ()) == NULL
25257 || (arm_shift_hsh
= hash_new ()) == NULL
25258 || (arm_psr_hsh
= hash_new ()) == NULL
25259 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25260 || (arm_reg_hsh
= hash_new ()) == NULL
25261 || (arm_reloc_hsh
= hash_new ()) == NULL
25262 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25263 as_fatal (_("virtual memory exhausted"));
25265 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25266 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25267 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25268 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25269 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25270 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25271 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25272 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25273 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25274 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25275 (void *) (v7m_psrs
+ i
));
25276 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25277 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25279 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25281 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25282 (void *) (barrier_opt_names
+ i
));
25284 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25286 struct reloc_entry
* entry
= reloc_names
+ i
;
25288 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25289 /* This makes encode_branch() use the EABI versions of this relocation. */
25290 entry
->reloc
= BFD_RELOC_UNUSED
;
25292 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25296 set_constant_flonums ();
25298 /* Set the cpu variant based on the command-line options. We prefer
25299 -mcpu= over -march= if both are set (as for GCC); and we prefer
25300 -mfpu= over any other way of setting the floating point unit.
25301 Use of legacy options with new options are faulted. */
25304 if (mcpu_cpu_opt
|| march_cpu_opt
)
25305 as_bad (_("use of old and new-style options to set CPU type"));
25307 mcpu_cpu_opt
= legacy_cpu
;
25309 else if (!mcpu_cpu_opt
)
25311 mcpu_cpu_opt
= march_cpu_opt
;
25312 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25313 /* Avoid double free in arm_md_end. */
25314 dyn_march_ext_opt
= NULL
;
25320 as_bad (_("use of old and new-style options to set FPU type"));
25322 mfpu_opt
= legacy_fpu
;
25324 else if (!mfpu_opt
)
25326 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25327 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25328 /* Some environments specify a default FPU. If they don't, infer it
25329 from the processor. */
25331 mfpu_opt
= mcpu_fpu_opt
;
25333 mfpu_opt
= march_fpu_opt
;
25335 mfpu_opt
= &fpu_default
;
25341 if (mcpu_cpu_opt
!= NULL
)
25342 mfpu_opt
= &fpu_default
;
25343 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25344 mfpu_opt
= &fpu_arch_vfp_v2
;
25346 mfpu_opt
= &fpu_arch_fpa
;
25352 mcpu_cpu_opt
= &cpu_default
;
25353 selected_cpu
= cpu_default
;
25355 else if (dyn_mcpu_ext_opt
)
25356 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25358 selected_cpu
= *mcpu_cpu_opt
;
25360 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25361 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25362 else if (mcpu_cpu_opt
)
25363 selected_cpu
= *mcpu_cpu_opt
;
25365 mcpu_cpu_opt
= &arm_arch_any
;
25368 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25369 if (dyn_mcpu_ext_opt
)
25370 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25372 autoselect_thumb_from_cpu_variant ();
25374 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25376 #if defined OBJ_COFF || defined OBJ_ELF
25378 unsigned int flags
= 0;
25380 #if defined OBJ_ELF
25381 flags
= meabi_flags
;
25383 switch (meabi_flags
)
25385 case EF_ARM_EABI_UNKNOWN
:
25387 /* Set the flags in the private structure. */
25388 if (uses_apcs_26
) flags
|= F_APCS26
;
25389 if (support_interwork
) flags
|= F_INTERWORK
;
25390 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25391 if (pic_code
) flags
|= F_PIC
;
25392 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25393 flags
|= F_SOFT_FLOAT
;
25395 switch (mfloat_abi_opt
)
25397 case ARM_FLOAT_ABI_SOFT
:
25398 case ARM_FLOAT_ABI_SOFTFP
:
25399 flags
|= F_SOFT_FLOAT
;
25402 case ARM_FLOAT_ABI_HARD
:
25403 if (flags
& F_SOFT_FLOAT
)
25404 as_bad (_("hard-float conflicts with specified fpu"));
25408 /* Using pure-endian doubles (even if soft-float). */
25409 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25410 flags
|= F_VFP_FLOAT
;
25412 #if defined OBJ_ELF
25413 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25414 flags
|= EF_ARM_MAVERICK_FLOAT
;
25417 case EF_ARM_EABI_VER4
:
25418 case EF_ARM_EABI_VER5
:
25419 /* No additional flags to set. */
25426 bfd_set_private_flags (stdoutput
, flags
);
25428 /* We have run out flags in the COFF header to encode the
25429 status of ATPCS support, so instead we create a dummy,
25430 empty, debug section called .arm.atpcs. */
25435 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25439 bfd_set_section_flags
25440 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25441 bfd_set_section_size (stdoutput
, sec
, 0);
25442 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25448 /* Record the CPU type as well. */
25449 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25450 mach
= bfd_mach_arm_iWMMXt2
;
25451 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25452 mach
= bfd_mach_arm_iWMMXt
;
25453 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25454 mach
= bfd_mach_arm_XScale
;
25455 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25456 mach
= bfd_mach_arm_ep9312
;
25457 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25458 mach
= bfd_mach_arm_5TE
;
25459 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25461 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25462 mach
= bfd_mach_arm_5T
;
25464 mach
= bfd_mach_arm_5
;
25466 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25468 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25469 mach
= bfd_mach_arm_4T
;
25471 mach
= bfd_mach_arm_4
;
25473 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25474 mach
= bfd_mach_arm_3M
;
25475 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25476 mach
= bfd_mach_arm_3
;
25477 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25478 mach
= bfd_mach_arm_2a
;
25479 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25480 mach
= bfd_mach_arm_2
;
25482 mach
= bfd_mach_arm_unknown
;
25484 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25487 /* Command line processing. */
25490 Invocation line includes a switch not recognized by the base assembler.
25491 See if it's a processor-specific option.
25493 This routine is somewhat complicated by the need for backwards
25494 compatibility (since older releases of gcc can't be changed).
25495 The new options try to make the interface as compatible as
25498 New options (supported) are:
25500 -mcpu=<cpu name> Assemble for selected processor
25501 -march=<architecture name> Assemble for selected architecture
25502 -mfpu=<fpu architecture> Assemble for selected FPU.
25503 -EB/-mbig-endian Big-endian
25504 -EL/-mlittle-endian Little-endian
25505 -k Generate PIC code
25506 -mthumb Start in Thumb mode
25507 -mthumb-interwork Code supports ARM/Thumb interworking
25509 -m[no-]warn-deprecated Warn about deprecated features
25510 -m[no-]warn-syms Warn when symbols match instructions
25512 For now we will also provide support for:
25514 -mapcs-32 32-bit Program counter
25515 -mapcs-26 26-bit Program counter
25516 -macps-float Floats passed in FP registers
25517 -mapcs-reentrant Reentrant code
25519 (sometime these will probably be replaced with -mapcs=<list of options>
25520 and -matpcs=<list of options>)
25522 The remaining options are only supported for back-wards compatibility.
25523 Cpu variants, the arm part is optional:
25524 -m[arm]1 Currently not supported.
25525 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25526 -m[arm]3 Arm 3 processor
25527 -m[arm]6[xx], Arm 6 processors
25528 -m[arm]7[xx][t][[d]m] Arm 7 processors
25529 -m[arm]8[10] Arm 8 processors
25530 -m[arm]9[20][tdmi] Arm 9 processors
25531 -mstrongarm[110[0]] StrongARM processors
25532 -mxscale XScale processors
25533 -m[arm]v[2345[t[e]]] Arm architectures
25534 -mall All (except the ARM1)
25536 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25537 -mfpe-old (No float load/store multiples)
25538 -mvfpxd VFP Single precision
25540 -mno-fpu Disable all floating point instructions
25542 The following CPU names are recognized:
25543 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25544 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25545 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25546 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25547 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25548 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25549 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25553 const char * md_shortopts
= "m:k";
25555 #ifdef ARM_BI_ENDIAN
25556 #define OPTION_EB (OPTION_MD_BASE + 0)
25557 #define OPTION_EL (OPTION_MD_BASE + 1)
25559 #if TARGET_BYTES_BIG_ENDIAN
25560 #define OPTION_EB (OPTION_MD_BASE + 0)
25562 #define OPTION_EL (OPTION_MD_BASE + 1)
25565 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25567 struct option md_longopts
[] =
25570 {"EB", no_argument
, NULL
, OPTION_EB
},
25573 {"EL", no_argument
, NULL
, OPTION_EL
},
25575 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25576 {NULL
, no_argument
, NULL
, 0}
25579 size_t md_longopts_size
= sizeof (md_longopts
);
25581 struct arm_option_table
25583 const char * option
; /* Option name to match. */
25584 const char * help
; /* Help information. */
25585 int * var
; /* Variable to change. */
25586 int value
; /* What to change it to. */
25587 const char * deprecated
; /* If non-null, print this message. */
25590 struct arm_option_table arm_opts
[] =
25592 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25593 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25594 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25595 &support_interwork
, 1, NULL
},
25596 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25597 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25598 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25600 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25601 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25602 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25603 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25606 /* These are recognized by the assembler, but have no affect on code. */
25607 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25608 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25610 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25611 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25612 &warn_on_deprecated
, 0, NULL
},
25613 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25614 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25615 {NULL
, NULL
, NULL
, 0, NULL
}
25618 struct arm_legacy_option_table
25620 const char * option
; /* Option name to match. */
25621 const arm_feature_set
** var
; /* Variable to change. */
25622 const arm_feature_set value
; /* What to change it to. */
25623 const char * deprecated
; /* If non-null, print this message. */
25626 const struct arm_legacy_option_table arm_legacy_opts
[] =
25628 /* DON'T add any new processors to this list -- we want the whole list
25629 to go away... Add them to the processors table instead. */
25630 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25631 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25632 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25633 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25634 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25635 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25636 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25637 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25638 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25639 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25640 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25641 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25642 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25643 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25644 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25645 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25646 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25647 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25648 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25649 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25650 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25651 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25652 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25653 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25654 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25655 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25656 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25657 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25658 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25659 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25660 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25661 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25662 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25663 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25664 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25665 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25666 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25667 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25668 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25669 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25670 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25671 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25672 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25673 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25674 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25675 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25676 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25677 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25678 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25679 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25680 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25681 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25682 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25683 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25684 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25685 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25686 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25687 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25688 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25689 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25690 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25691 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25692 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25693 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25694 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25695 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25696 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25697 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25698 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25699 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25700 N_("use -mcpu=strongarm110")},
25701 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25702 N_("use -mcpu=strongarm1100")},
25703 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25704 N_("use -mcpu=strongarm1110")},
25705 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25706 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25707 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25709 /* Architecture variants -- don't add any more to this list either. */
25710 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25711 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25712 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25713 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25714 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25715 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25716 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25717 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25718 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25719 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25720 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25721 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25722 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25723 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25724 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25725 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25726 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25727 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25729 /* Floating point variants -- don't add any more to this list either. */
25730 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25731 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25732 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25733 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25734 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25736 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25739 struct arm_cpu_option_table
25743 const arm_feature_set value
;
25744 const arm_feature_set ext
;
25745 /* For some CPUs we assume an FPU unless the user explicitly sets
25747 const arm_feature_set default_fpu
;
25748 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25750 const char * canonical_name
;
25753 /* This list should, at a minimum, contain all the cpu names
25754 recognized by GCC. */
25755 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25757 static const struct arm_cpu_option_table arm_cpus
[] =
25759 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25762 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25765 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25768 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25771 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25774 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25777 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25780 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25783 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25786 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25789 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25792 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25795 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25798 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25801 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25804 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25807 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25810 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25813 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25816 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25819 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25822 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25825 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25828 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25831 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25834 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25837 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25840 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25843 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25846 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25849 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25852 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25855 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25858 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25861 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25864 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25867 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25870 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25873 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25876 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25879 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25882 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25885 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25888 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25891 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25894 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25898 /* For V5 or later processors we default to using VFP; but the user
25899 should really set the FPU type explicitly. */
25900 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25903 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25906 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25909 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25912 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25915 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25918 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25921 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25924 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25927 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25930 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25933 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25936 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25939 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25942 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25945 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25948 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25951 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25954 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25957 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25960 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25963 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25966 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25969 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25972 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25975 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25978 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25981 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25984 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25987 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25990 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25993 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25996 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25999 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26002 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26005 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26008 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26009 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26011 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26013 FPU_ARCH_NEON_VFP_V4
),
26014 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26015 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26016 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26017 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26018 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26019 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26020 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26022 FPU_ARCH_NEON_VFP_V4
),
26023 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26025 FPU_ARCH_NEON_VFP_V4
),
26026 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26028 FPU_ARCH_NEON_VFP_V4
),
26029 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26030 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26031 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26032 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26033 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26034 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26035 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26036 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26037 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26038 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26039 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26040 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26041 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26042 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26043 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26044 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26045 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26046 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26047 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26048 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26049 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26050 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26051 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26052 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26053 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26056 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26058 FPU_ARCH_VFP_V3D16
),
26059 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26060 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26062 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26063 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26064 FPU_ARCH_VFP_V3D16
),
26065 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26066 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26067 FPU_ARCH_VFP_V3D16
),
26068 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26069 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26070 FPU_ARCH_NEON_VFP_ARMV8
),
26071 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26072 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26074 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26077 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26080 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26083 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26086 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26089 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26092 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26095 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26096 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26097 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26099 /* ??? XSCALE is really an architecture. */
26100 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26104 /* ??? iwmmxt is not a processor. */
26105 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26108 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26111 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26116 ARM_CPU_OPT ("ep9312", "ARM920T",
26117 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26118 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26120 /* Marvell processors. */
26121 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26122 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26123 FPU_ARCH_VFP_V3D16
),
26124 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26125 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26126 FPU_ARCH_NEON_VFP_V4
),
26128 /* APM X-Gene family. */
26129 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26131 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26132 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26133 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26134 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26136 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26140 struct arm_arch_option_table
26144 const arm_feature_set value
;
26145 const arm_feature_set default_fpu
;
26148 /* This list should, at a minimum, contain all the architecture names
26149 recognized by GCC. */
26150 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26152 static const struct arm_arch_option_table arm_archs
[] =
26154 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26155 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26156 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26157 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26158 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26159 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26160 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26161 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26162 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26163 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26164 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26165 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26166 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26167 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26168 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
26169 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
26170 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
26171 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26172 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26173 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26174 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26175 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26176 kept to preserve existing behaviour. */
26177 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26178 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26179 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26180 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26181 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26182 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26183 kept to preserve existing behaviour. */
26184 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26185 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26186 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26187 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26188 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26189 /* The official spelling of the ARMv7 profile variants is the dashed form.
26190 Accept the non-dashed form for compatibility with old toolchains. */
26191 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26192 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26193 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26194 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26195 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26196 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26197 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26198 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26199 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26200 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26201 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26202 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26203 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26204 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26205 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26206 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
),
26207 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26208 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26209 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26210 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26212 #undef ARM_ARCH_OPT
26214 /* ISA extensions in the co-processor and main instruction set space. */
26216 struct arm_option_extension_value_table
26220 const arm_feature_set merge_value
;
26221 const arm_feature_set clear_value
;
26222 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26223 indicates that an extension is available for all architectures while
26224 ARM_ANY marks an empty entry. */
26225 const arm_feature_set allowed_archs
[2];
26228 /* The following table must be in alphabetical order with a NULL last entry. */
26230 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26231 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26233 static const struct arm_option_extension_value_table arm_extensions
[] =
26235 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26236 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26237 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26238 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26239 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26240 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26241 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26243 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26244 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26245 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26246 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26247 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26248 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26251 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26252 | ARM_EXT2_FP16_FML
),
26253 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26254 | ARM_EXT2_FP16_FML
),
26256 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26257 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26258 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26259 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26260 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26261 Thumb divide instruction. Due to this having the same name as the
26262 previous entry, this will be ignored when doing command-line parsing and
26263 only considered by build attribute selection code. */
26264 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26265 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26266 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26267 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26268 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26269 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26270 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26271 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26272 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26273 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26274 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26275 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26276 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26277 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26278 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26279 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26280 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26281 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26282 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26283 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26284 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26286 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26287 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26288 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26289 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26290 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26291 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26292 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26293 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26294 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26295 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26296 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26298 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26299 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26300 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26301 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26302 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26306 /* ISA floating-point and Advanced SIMD extensions. */
26307 struct arm_option_fpu_value_table
26310 const arm_feature_set value
;
26313 /* This list should, at a minimum, contain all the fpu names
26314 recognized by GCC. */
26315 static const struct arm_option_fpu_value_table arm_fpus
[] =
26317 {"softfpa", FPU_NONE
},
26318 {"fpe", FPU_ARCH_FPE
},
26319 {"fpe2", FPU_ARCH_FPE
},
26320 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26321 {"fpa", FPU_ARCH_FPA
},
26322 {"fpa10", FPU_ARCH_FPA
},
26323 {"fpa11", FPU_ARCH_FPA
},
26324 {"arm7500fe", FPU_ARCH_FPA
},
26325 {"softvfp", FPU_ARCH_VFP
},
26326 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26327 {"vfp", FPU_ARCH_VFP_V2
},
26328 {"vfp9", FPU_ARCH_VFP_V2
},
26329 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26330 {"vfp10", FPU_ARCH_VFP_V2
},
26331 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26332 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26333 {"vfpv2", FPU_ARCH_VFP_V2
},
26334 {"vfpv3", FPU_ARCH_VFP_V3
},
26335 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26336 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26337 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26338 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26339 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26340 {"arm1020t", FPU_ARCH_VFP_V1
},
26341 {"arm1020e", FPU_ARCH_VFP_V2
},
26342 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26343 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26344 {"maverick", FPU_ARCH_MAVERICK
},
26345 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26346 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26347 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26348 {"vfpv4", FPU_ARCH_VFP_V4
},
26349 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26350 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26351 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26352 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26353 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26354 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26355 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26356 {"crypto-neon-fp-armv8",
26357 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26358 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26359 {"crypto-neon-fp-armv8.1",
26360 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26361 {NULL
, ARM_ARCH_NONE
}
26364 struct arm_option_value_table
26370 static const struct arm_option_value_table arm_float_abis
[] =
26372 {"hard", ARM_FLOAT_ABI_HARD
},
26373 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26374 {"soft", ARM_FLOAT_ABI_SOFT
},
26379 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26380 static const struct arm_option_value_table arm_eabis
[] =
26382 {"gnu", EF_ARM_EABI_UNKNOWN
},
26383 {"4", EF_ARM_EABI_VER4
},
26384 {"5", EF_ARM_EABI_VER5
},
26389 struct arm_long_option_table
26391 const char * option
; /* Substring to match. */
26392 const char * help
; /* Help information. */
26393 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26394 const char * deprecated
; /* If non-null, print this message. */
26398 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26399 arm_feature_set
**ext_set_p
)
26401 /* We insist on extensions being specified in alphabetical order, and with
26402 extensions being added before being removed. We achieve this by having
26403 the global ARM_EXTENSIONS table in alphabetical order, and using the
26404 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26405 or removing it (0) and only allowing it to change in the order
26407 const struct arm_option_extension_value_table
* opt
= NULL
;
26408 const arm_feature_set arm_any
= ARM_ANY
;
26409 int adding_value
= -1;
26413 *ext_set_p
= XNEW (arm_feature_set
);
26414 **ext_set_p
= arm_arch_none
;
26417 while (str
!= NULL
&& *str
!= 0)
26424 as_bad (_("invalid architectural extension"));
26429 ext
= strchr (str
, '+');
26434 len
= strlen (str
);
26436 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26438 if (adding_value
!= 0)
26441 opt
= arm_extensions
;
26449 if (adding_value
== -1)
26452 opt
= arm_extensions
;
26454 else if (adding_value
!= 1)
26456 as_bad (_("must specify extensions to add before specifying "
26457 "those to remove"));
26464 as_bad (_("missing architectural extension"));
26468 gas_assert (adding_value
!= -1);
26469 gas_assert (opt
!= NULL
);
26471 /* Scan over the options table trying to find an exact match. */
26472 for (; opt
->name
!= NULL
; opt
++)
26473 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26475 int i
, nb_allowed_archs
=
26476 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26477 /* Check we can apply the extension to this architecture. */
26478 for (i
= 0; i
< nb_allowed_archs
; i
++)
26481 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26483 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26486 if (i
== nb_allowed_archs
)
26488 as_bad (_("extension does not apply to the base architecture"));
26492 /* Add or remove the extension. */
26494 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26497 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26499 /* Allowing Thumb division instructions for ARMv7 in autodetection
26500 rely on this break so that duplicate extensions (extensions
26501 with the same name as a previous extension in the list) are not
26502 considered for command-line parsing. */
26506 if (opt
->name
== NULL
)
26508 /* Did we fail to find an extension because it wasn't specified in
26509 alphabetical order, or because it does not exist? */
26511 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26512 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26515 if (opt
->name
== NULL
)
26516 as_bad (_("unknown architectural extension `%s'"), str
);
26518 as_bad (_("architectural extensions must be specified in "
26519 "alphabetical order"));
26525 /* We should skip the extension we've just matched the next time
26537 arm_parse_cpu (const char *str
)
26539 const struct arm_cpu_option_table
*opt
;
26540 const char *ext
= strchr (str
, '+');
26546 len
= strlen (str
);
26550 as_bad (_("missing cpu name `%s'"), str
);
26554 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26555 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26557 mcpu_cpu_opt
= &opt
->value
;
26558 if (!dyn_mcpu_ext_opt
)
26559 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26560 *dyn_mcpu_ext_opt
= opt
->ext
;
26561 mcpu_fpu_opt
= &opt
->default_fpu
;
26562 if (opt
->canonical_name
)
26564 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26565 strcpy (selected_cpu_name
, opt
->canonical_name
);
26571 if (len
>= sizeof selected_cpu_name
)
26572 len
= (sizeof selected_cpu_name
) - 1;
26574 for (i
= 0; i
< len
; i
++)
26575 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26576 selected_cpu_name
[i
] = 0;
26580 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26585 as_bad (_("unknown cpu `%s'"), str
);
26590 arm_parse_arch (const char *str
)
26592 const struct arm_arch_option_table
*opt
;
26593 const char *ext
= strchr (str
, '+');
26599 len
= strlen (str
);
26603 as_bad (_("missing architecture name `%s'"), str
);
26607 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26608 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26610 march_cpu_opt
= &opt
->value
;
26611 march_fpu_opt
= &opt
->default_fpu
;
26612 strcpy (selected_cpu_name
, opt
->name
);
26615 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26620 as_bad (_("unknown architecture `%s'\n"), str
);
26625 arm_parse_fpu (const char * str
)
26627 const struct arm_option_fpu_value_table
* opt
;
26629 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26630 if (streq (opt
->name
, str
))
26632 mfpu_opt
= &opt
->value
;
26636 as_bad (_("unknown floating point format `%s'\n"), str
);
26641 arm_parse_float_abi (const char * str
)
26643 const struct arm_option_value_table
* opt
;
26645 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26646 if (streq (opt
->name
, str
))
26648 mfloat_abi_opt
= opt
->value
;
26652 as_bad (_("unknown floating point abi `%s'\n"), str
);
26658 arm_parse_eabi (const char * str
)
26660 const struct arm_option_value_table
*opt
;
26662 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26663 if (streq (opt
->name
, str
))
26665 meabi_flags
= opt
->value
;
26668 as_bad (_("unknown EABI `%s'\n"), str
);
26674 arm_parse_it_mode (const char * str
)
26676 bfd_boolean ret
= TRUE
;
26678 if (streq ("arm", str
))
26679 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26680 else if (streq ("thumb", str
))
26681 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26682 else if (streq ("always", str
))
26683 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26684 else if (streq ("never", str
))
26685 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26688 as_bad (_("unknown implicit IT mode `%s', should be "\
26689 "arm, thumb, always, or never."), str
);
26697 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26699 codecomposer_syntax
= TRUE
;
26700 arm_comment_chars
[0] = ';';
26701 arm_line_separator_chars
[0] = 0;
26705 struct arm_long_option_table arm_long_opts
[] =
26707 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26708 arm_parse_cpu
, NULL
},
26709 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26710 arm_parse_arch
, NULL
},
26711 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26712 arm_parse_fpu
, NULL
},
26713 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26714 arm_parse_float_abi
, NULL
},
26716 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26717 arm_parse_eabi
, NULL
},
26719 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26720 arm_parse_it_mode
, NULL
},
26721 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26722 arm_ccs_mode
, NULL
},
26723 {NULL
, NULL
, 0, NULL
}
26727 md_parse_option (int c
, const char * arg
)
26729 struct arm_option_table
*opt
;
26730 const struct arm_legacy_option_table
*fopt
;
26731 struct arm_long_option_table
*lopt
;
26737 target_big_endian
= 1;
26743 target_big_endian
= 0;
26747 case OPTION_FIX_V4BX
:
26752 /* Listing option. Just ignore these, we don't support additional
26757 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26759 if (c
== opt
->option
[0]
26760 && ((arg
== NULL
&& opt
->option
[1] == 0)
26761 || streq (arg
, opt
->option
+ 1)))
26763 /* If the option is deprecated, tell the user. */
26764 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26765 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26766 arg
? arg
: "", _(opt
->deprecated
));
26768 if (opt
->var
!= NULL
)
26769 *opt
->var
= opt
->value
;
26775 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26777 if (c
== fopt
->option
[0]
26778 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26779 || streq (arg
, fopt
->option
+ 1)))
26781 /* If the option is deprecated, tell the user. */
26782 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26783 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26784 arg
? arg
: "", _(fopt
->deprecated
));
26786 if (fopt
->var
!= NULL
)
26787 *fopt
->var
= &fopt
->value
;
26793 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26795 /* These options are expected to have an argument. */
26796 if (c
== lopt
->option
[0]
26798 && strncmp (arg
, lopt
->option
+ 1,
26799 strlen (lopt
->option
+ 1)) == 0)
26801 /* If the option is deprecated, tell the user. */
26802 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26803 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26804 _(lopt
->deprecated
));
26806 /* Call the sup-option parser. */
26807 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26818 md_show_usage (FILE * fp
)
26820 struct arm_option_table
*opt
;
26821 struct arm_long_option_table
*lopt
;
26823 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26825 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26826 if (opt
->help
!= NULL
)
26827 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26829 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26830 if (lopt
->help
!= NULL
)
26831 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26835 -EB assemble code for a big-endian cpu\n"));
26840 -EL assemble code for a little-endian cpu\n"));
26844 --fix-v4bx Allow BX in ARMv4 code\n"));
26852 arm_feature_set flags
;
26853 } cpu_arch_ver_table
;
26855 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26856 chronologically for architectures, with an exception for ARMv6-M and
26857 ARMv6S-M due to legacy reasons. No new architecture should have a
26858 special case. This allows for build attribute selection results to be
26859 stable when new architectures are added. */
26860 static const cpu_arch_ver_table cpu_arch_ver
[] =
26867 {1, ARM_ARCH_V4xM
},
26869 {2, ARM_ARCH_V4TxM
},
26871 {3, ARM_ARCH_V5xM
},
26873 {3, ARM_ARCH_V5TxM
},
26875 {4, ARM_ARCH_V5TExP
},
26876 {4, ARM_ARCH_V5TE
},
26877 {5, ARM_ARCH_V5TEJ
},
26880 {7, ARM_ARCH_V6KZ
},
26882 {8, ARM_ARCH_V6T2
},
26883 {8, ARM_ARCH_V6KT2
},
26884 {8, ARM_ARCH_V6ZT2
},
26885 {8, ARM_ARCH_V6KZT2
},
26887 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26888 always selected build attributes to match those of ARMv6-M
26889 (resp. ARMv6S-M). However, due to these architectures being a strict
26890 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26891 would be selected when fully respecting chronology of architectures.
26892 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26893 move them before ARMv7 architectures. */
26894 {11, ARM_ARCH_V6M
},
26895 {12, ARM_ARCH_V6SM
},
26898 {10, ARM_ARCH_V7A
},
26899 {10, ARM_ARCH_V7R
},
26900 {10, ARM_ARCH_V7M
},
26901 {10, ARM_ARCH_V7VE
},
26902 {13, ARM_ARCH_V7EM
},
26903 {14, ARM_ARCH_V8A
},
26904 {14, ARM_ARCH_V8_1A
},
26905 {14, ARM_ARCH_V8_2A
},
26906 {14, ARM_ARCH_V8_3A
},
26907 {16, ARM_ARCH_V8M_BASE
},
26908 {17, ARM_ARCH_V8M_MAIN
},
26909 {15, ARM_ARCH_V8R
},
26910 {16, ARM_ARCH_V8_4A
},
26911 {-1, ARM_ARCH_NONE
}
26914 /* Set an attribute if it has not already been set by the user. */
26917 aeabi_set_attribute_int (int tag
, int value
)
26920 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26921 || !attributes_set_explicitly
[tag
])
26922 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26926 aeabi_set_attribute_string (int tag
, const char *value
)
26929 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26930 || !attributes_set_explicitly
[tag
])
26931 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26934 /* Return whether features in the *NEEDED feature set are available via
26935 extensions for the architecture whose feature set is *ARCH_FSET. */
26938 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26939 const arm_feature_set
*needed
)
26941 int i
, nb_allowed_archs
;
26942 arm_feature_set ext_fset
;
26943 const struct arm_option_extension_value_table
*opt
;
26945 ext_fset
= arm_arch_none
;
26946 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26948 /* Extension does not provide any feature we need. */
26949 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26953 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26954 for (i
= 0; i
< nb_allowed_archs
; i
++)
26957 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26960 /* Extension is available, add it. */
26961 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26962 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26966 /* Can we enable all features in *needed? */
26967 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26970 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26971 a given architecture feature set *ARCH_EXT_FSET including extension feature
26972 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26973 - if true, check for an exact match of the architecture modulo extensions;
26974 - otherwise, select build attribute value of the first superset
26975 architecture released so that results remains stable when new architectures
26977 For -march/-mcpu=all the build attribute value of the most featureful
26978 architecture is returned. Tag_CPU_arch_profile result is returned in
26982 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26983 const arm_feature_set
*ext_fset
,
26984 char *profile
, int exact_match
)
26986 arm_feature_set arch_fset
;
26987 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26989 /* Select most featureful architecture with all its extensions if building
26990 for -march=all as the feature sets used to set build attributes. */
26991 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26993 /* Force revisiting of decision for each new architecture. */
26994 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
26996 return TAG_CPU_ARCH_V8
;
26999 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27001 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27003 arm_feature_set known_arch_fset
;
27005 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27008 /* Base architecture match user-specified architecture and
27009 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27010 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27015 /* Base architecture match user-specified architecture only
27016 (eg. ARMv6-M in the same case as above). Record it in case we
27017 find a match with above condition. */
27018 else if (p_ver_ret
== NULL
27019 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27025 /* Architecture has all features wanted. */
27026 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27028 arm_feature_set added_fset
;
27030 /* Compute features added by this architecture over the one
27031 recorded in p_ver_ret. */
27032 if (p_ver_ret
!= NULL
)
27033 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27035 /* First architecture that match incl. with extensions, or the
27036 only difference in features over the recorded match is
27037 features that were optional and are now mandatory. */
27038 if (p_ver_ret
== NULL
27039 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27045 else if (p_ver_ret
== NULL
)
27047 arm_feature_set needed_ext_fset
;
27049 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27051 /* Architecture has all features needed when using some
27052 extensions. Record it and continue searching in case there
27053 exist an architecture providing all needed features without
27054 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27056 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27063 if (p_ver_ret
== NULL
)
27067 /* Tag_CPU_arch_profile. */
27068 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27069 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27070 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27071 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27073 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27075 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27079 return p_ver_ret
->val
;
27082 /* Set the public EABI object attributes. */
27085 aeabi_set_public_attributes (void)
27090 int fp16_optional
= 0;
27091 int skip_exact_match
= 0;
27092 arm_feature_set flags
, flags_arch
, flags_ext
;
27094 /* Autodetection mode, choose the architecture based the instructions
27096 if (no_cpu_selected ())
27098 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27100 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27101 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27103 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27104 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27106 /* Code run during relaxation relies on selected_cpu being set. */
27107 selected_cpu
= flags
;
27109 /* Otherwise, choose the architecture based on the capabilities of the
27112 flags
= selected_cpu
;
27113 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
27115 /* Allow the user to override the reported architecture. */
27118 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
27119 flags_ext
= arm_arch_none
;
27123 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27124 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
27125 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27128 /* When this function is run again after relaxation has happened there is no
27129 way to determine whether an architecture or CPU was specified by the user:
27130 - selected_cpu is set above for relaxation to work;
27131 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27132 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27133 Therefore, if not in -march=all case we first try an exact match and fall
27134 back to autodetection. */
27135 if (!skip_exact_match
)
27136 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27138 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27140 as_bad (_("no architecture contains all the instructions used\n"));
27142 /* Tag_CPU_name. */
27143 if (selected_cpu_name
[0])
27147 q
= selected_cpu_name
;
27148 if (strncmp (q
, "armv", 4) == 0)
27153 for (i
= 0; q
[i
]; i
++)
27154 q
[i
] = TOUPPER (q
[i
]);
27156 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27159 /* Tag_CPU_arch. */
27160 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27162 /* Tag_CPU_arch_profile. */
27163 if (profile
!= '\0')
27164 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27166 /* Tag_DSP_extension. */
27167 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
27168 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27170 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27171 /* Tag_ARM_ISA_use. */
27172 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27173 || ARM_FEATURE_ZERO (flags_arch
))
27174 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27176 /* Tag_THUMB_ISA_use. */
27177 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27178 || ARM_FEATURE_ZERO (flags_arch
))
27182 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27183 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27185 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27189 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27192 /* Tag_VFP_arch. */
27193 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27194 aeabi_set_attribute_int (Tag_VFP_arch
,
27195 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27197 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27198 aeabi_set_attribute_int (Tag_VFP_arch
,
27199 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27201 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27204 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27206 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27208 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27211 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27212 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27213 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27214 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27215 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27217 /* Tag_ABI_HardFP_use. */
27218 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27219 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27220 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27222 /* Tag_WMMX_arch. */
27223 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27224 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27225 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27226 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27228 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27229 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27230 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27231 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27232 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27233 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27235 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27237 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27241 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27246 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27247 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27248 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27252 We set Tag_DIV_use to two when integer divide instructions have been used
27253 in ARM state, or when Thumb integer divide instructions have been used,
27254 but we have no architecture profile set, nor have we any ARM instructions.
27256 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27257 by the base architecture.
27259 For new architectures we will have to check these tests. */
27260 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27261 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27262 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27263 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27264 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27265 || (profile
== '\0'
27266 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27267 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27268 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27270 /* Tag_MP_extension_use. */
27271 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27272 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27274 /* Tag Virtualization_use. */
27275 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27277 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27280 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27283 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27284 finished and free extension feature bits which will not be used anymore. */
27287 arm_md_post_relax (void)
27289 aeabi_set_public_attributes ();
27290 XDELETE (dyn_mcpu_ext_opt
);
27291 dyn_mcpu_ext_opt
= NULL
;
27292 XDELETE (dyn_march_ext_opt
);
27293 dyn_march_ext_opt
= NULL
;
27296 /* Add the default contents for the .ARM.attributes section. */
27301 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27304 aeabi_set_public_attributes ();
27306 #endif /* OBJ_ELF */
27308 /* Parse a .cpu directive. */
27311 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27313 const struct arm_cpu_option_table
*opt
;
27317 name
= input_line_pointer
;
27318 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27319 input_line_pointer
++;
27320 saved_char
= *input_line_pointer
;
27321 *input_line_pointer
= 0;
27323 /* Skip the first "all" entry. */
27324 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27325 if (streq (opt
->name
, name
))
27327 mcpu_cpu_opt
= &opt
->value
;
27328 if (!dyn_mcpu_ext_opt
)
27329 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27330 *dyn_mcpu_ext_opt
= opt
->ext
;
27331 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27332 if (opt
->canonical_name
)
27333 strcpy (selected_cpu_name
, opt
->canonical_name
);
27337 for (i
= 0; opt
->name
[i
]; i
++)
27338 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27340 selected_cpu_name
[i
] = 0;
27342 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27343 if (dyn_mcpu_ext_opt
)
27344 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27345 *input_line_pointer
= saved_char
;
27346 demand_empty_rest_of_line ();
27349 as_bad (_("unknown cpu `%s'"), name
);
27350 *input_line_pointer
= saved_char
;
27351 ignore_rest_of_line ();
27354 /* Parse a .arch directive. */
27357 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27359 const struct arm_arch_option_table
*opt
;
27363 name
= input_line_pointer
;
27364 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27365 input_line_pointer
++;
27366 saved_char
= *input_line_pointer
;
27367 *input_line_pointer
= 0;
27369 /* Skip the first "all" entry. */
27370 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27371 if (streq (opt
->name
, name
))
27373 mcpu_cpu_opt
= &opt
->value
;
27374 XDELETE (dyn_mcpu_ext_opt
);
27375 dyn_mcpu_ext_opt
= NULL
;
27376 selected_cpu
= *mcpu_cpu_opt
;
27377 strcpy (selected_cpu_name
, opt
->name
);
27378 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27379 *input_line_pointer
= saved_char
;
27380 demand_empty_rest_of_line ();
27384 as_bad (_("unknown architecture `%s'\n"), name
);
27385 *input_line_pointer
= saved_char
;
27386 ignore_rest_of_line ();
27389 /* Parse a .object_arch directive. */
27392 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27394 const struct arm_arch_option_table
*opt
;
27398 name
= input_line_pointer
;
27399 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27400 input_line_pointer
++;
27401 saved_char
= *input_line_pointer
;
27402 *input_line_pointer
= 0;
27404 /* Skip the first "all" entry. */
27405 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27406 if (streq (opt
->name
, name
))
27408 object_arch
= &opt
->value
;
27409 *input_line_pointer
= saved_char
;
27410 demand_empty_rest_of_line ();
27414 as_bad (_("unknown architecture `%s'\n"), name
);
27415 *input_line_pointer
= saved_char
;
27416 ignore_rest_of_line ();
27419 /* Parse a .arch_extension directive. */
27422 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27424 const struct arm_option_extension_value_table
*opt
;
27425 const arm_feature_set arm_any
= ARM_ANY
;
27428 int adding_value
= 1;
27430 name
= input_line_pointer
;
27431 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27432 input_line_pointer
++;
27433 saved_char
= *input_line_pointer
;
27434 *input_line_pointer
= 0;
27436 if (strlen (name
) >= 2
27437 && strncmp (name
, "no", 2) == 0)
27443 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27444 if (streq (opt
->name
, name
))
27446 int i
, nb_allowed_archs
=
27447 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27448 for (i
= 0; i
< nb_allowed_archs
; i
++)
27451 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27453 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27457 if (i
== nb_allowed_archs
)
27459 as_bad (_("architectural extension `%s' is not allowed for the "
27460 "current base architecture"), name
);
27464 if (!dyn_mcpu_ext_opt
)
27466 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27467 *dyn_mcpu_ext_opt
= arm_arch_none
;
27470 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27473 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27476 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27477 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27478 *input_line_pointer
= saved_char
;
27479 demand_empty_rest_of_line ();
27480 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27481 on this return so that duplicate extensions (extensions with the
27482 same name as a previous extension in the list) are not considered
27483 for command-line parsing. */
27487 if (opt
->name
== NULL
)
27488 as_bad (_("unknown architecture extension `%s'\n"), name
);
27490 *input_line_pointer
= saved_char
;
27491 ignore_rest_of_line ();
27494 /* Parse a .fpu directive. */
27497 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27499 const struct arm_option_fpu_value_table
*opt
;
27503 name
= input_line_pointer
;
27504 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27505 input_line_pointer
++;
27506 saved_char
= *input_line_pointer
;
27507 *input_line_pointer
= 0;
27509 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27510 if (streq (opt
->name
, name
))
27512 mfpu_opt
= &opt
->value
;
27513 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27514 if (dyn_mcpu_ext_opt
)
27515 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27516 *input_line_pointer
= saved_char
;
27517 demand_empty_rest_of_line ();
27521 as_bad (_("unknown floating point format `%s'\n"), name
);
27522 *input_line_pointer
= saved_char
;
27523 ignore_rest_of_line ();
27526 /* Copy symbol information. */
27529 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27531 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27535 /* Given a symbolic attribute NAME, return the proper integer value.
27536 Returns -1 if the attribute is not known. */
27539 arm_convert_symbolic_attribute (const char *name
)
27541 static const struct
27546 attribute_table
[] =
27548 /* When you modify this table you should
27549 also modify the list in doc/c-arm.texi. */
27550 #define T(tag) {#tag, tag}
27551 T (Tag_CPU_raw_name
),
27554 T (Tag_CPU_arch_profile
),
27555 T (Tag_ARM_ISA_use
),
27556 T (Tag_THUMB_ISA_use
),
27560 T (Tag_Advanced_SIMD_arch
),
27561 T (Tag_PCS_config
),
27562 T (Tag_ABI_PCS_R9_use
),
27563 T (Tag_ABI_PCS_RW_data
),
27564 T (Tag_ABI_PCS_RO_data
),
27565 T (Tag_ABI_PCS_GOT_use
),
27566 T (Tag_ABI_PCS_wchar_t
),
27567 T (Tag_ABI_FP_rounding
),
27568 T (Tag_ABI_FP_denormal
),
27569 T (Tag_ABI_FP_exceptions
),
27570 T (Tag_ABI_FP_user_exceptions
),
27571 T (Tag_ABI_FP_number_model
),
27572 T (Tag_ABI_align_needed
),
27573 T (Tag_ABI_align8_needed
),
27574 T (Tag_ABI_align_preserved
),
27575 T (Tag_ABI_align8_preserved
),
27576 T (Tag_ABI_enum_size
),
27577 T (Tag_ABI_HardFP_use
),
27578 T (Tag_ABI_VFP_args
),
27579 T (Tag_ABI_WMMX_args
),
27580 T (Tag_ABI_optimization_goals
),
27581 T (Tag_ABI_FP_optimization_goals
),
27582 T (Tag_compatibility
),
27583 T (Tag_CPU_unaligned_access
),
27584 T (Tag_FP_HP_extension
),
27585 T (Tag_VFP_HP_extension
),
27586 T (Tag_ABI_FP_16bit_format
),
27587 T (Tag_MPextension_use
),
27589 T (Tag_nodefaults
),
27590 T (Tag_also_compatible_with
),
27591 T (Tag_conformance
),
27593 T (Tag_Virtualization_use
),
27594 T (Tag_DSP_extension
),
27595 /* We deliberately do not include Tag_MPextension_use_legacy. */
27603 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27604 if (streq (name
, attribute_table
[i
].name
))
27605 return attribute_table
[i
].tag
;
27610 /* Apply sym value for relocations only in the case that they are for
27611 local symbols in the same segment as the fixup and you have the
27612 respective architectural feature for blx and simple switches. */
27615 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27618 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27619 /* PR 17444: If the local symbol is in a different section then a reloc
27620 will always be generated for it, so applying the symbol value now
27621 will result in a double offset being stored in the relocation. */
27622 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27623 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27625 switch (fixP
->fx_r_type
)
27627 case BFD_RELOC_ARM_PCREL_BLX
:
27628 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27629 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27633 case BFD_RELOC_ARM_PCREL_CALL
:
27634 case BFD_RELOC_THUMB_PCREL_BLX
:
27635 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27646 #endif /* OBJ_ELF */