1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
357 unsigned long instruction
;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype
;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type
;
379 enum it_instruction_type it_insn_type
;
385 struct neon_type_el vectype
;
386 unsigned present
: 1; /* Operand present. */
387 unsigned isreg
: 1; /* Operand was a register. */
388 unsigned immisreg
: 1; /* .imm field is a second register. */
389 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
399 unsigned writeback
: 1; /* Operand has trailing ! */
400 unsigned preind
: 1; /* Preindexed address. */
401 unsigned postind
: 1; /* Postindexed address. */
402 unsigned negative
: 1; /* Index register was negated. */
403 unsigned shifted
: 1; /* Shift applied to operation. */
404 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst
;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const
[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name
;
444 #define COND_ALWAYS 0xE
448 const char * template_name
;
452 struct asm_barrier_opt
454 const char * template_name
;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc
;
475 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
476 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
481 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined
;
492 struct neon_type_el eltype
;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin
;
533 struct neon_typed_alias
* neon
;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs
[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name
;
576 /* Parameters to instruction. */
577 unsigned int operands
[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag
: 4;
582 /* Basic instruction code. */
583 unsigned int avalue
: 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set
* avariant
;
590 const arm_feature_set
* tvariant
;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode
) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode
) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
727 #define BAD_RANGE _("branch out of range")
729 static struct hash_control
* arm_ops_hsh
;
730 static struct hash_control
* arm_cond_hsh
;
731 static struct hash_control
* arm_shift_hsh
;
732 static struct hash_control
* arm_psr_hsh
;
733 static struct hash_control
* arm_v7m_psr_hsh
;
734 static struct hash_control
* arm_reg_hsh
;
735 static struct hash_control
* arm_reloc_hsh
;
736 static struct hash_control
* arm_barrier_opt_hsh
;
738 /* Stuff needed to resolve the label ambiguity
747 symbolS
* last_label_seen
;
748 static int label_is_thumb_function_name
= FALSE
;
750 /* Literal pool structure. Held on a per-section
751 and per-sub-section basis. */
753 #define MAX_LITERAL_POOL_SIZE 1024
754 typedef struct literal_pool
756 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
757 unsigned int next_free_entry
;
762 struct literal_pool
* next
;
765 /* Pointer to a linked list of literal pools. */
766 literal_pool
* list_of_pools
= NULL
;
769 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
771 static struct current_it now_it
;
775 now_it_compatible (int cond
)
777 return (cond
& ~1) == (now_it
.cc
& ~1);
781 conditional_insn (void)
783 return inst
.cond
!= COND_ALWAYS
;
786 static int in_it_block (void);
788 static int handle_it_state (void);
790 static void force_automatic_it_block_close (void);
792 static void it_fsm_post_encode (void);
794 #define set_it_insn_type(type) \
797 inst.it_insn_type = type; \
798 if (handle_it_state () == FAIL) \
803 #define set_it_insn_type_nonvoid(type, failret) \
806 inst.it_insn_type = type; \
807 if (handle_it_state () == FAIL) \
812 #define set_it_insn_type_last() \
815 if (inst.cond == COND_ALWAYS) \
816 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
818 set_it_insn_type (INSIDE_IT_LAST_INSN); \
824 /* This array holds the chars that always start a comment. If the
825 pre-processor is disabled, these aren't very useful. */
826 const char comment_chars
[] = "@";
828 /* This array holds the chars that only start a comment at the beginning of
829 a line. If the line seems to have the form '# 123 filename'
830 .line and .file directives will appear in the pre-processed output. */
831 /* Note that input_file.c hand checks for '#' at the beginning of the
832 first line of the input file. This is because the compiler outputs
833 #NO_APP at the beginning of its output. */
834 /* Also note that comments like this one will always work. */
835 const char line_comment_chars
[] = "#";
837 const char line_separator_chars
[] = ";";
839 /* Chars that can be used to separate mant
840 from exp in floating point numbers. */
841 const char EXP_CHARS
[] = "eE";
843 /* Chars that mean this number is a floating point constant. */
847 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
849 /* Prefix characters that indicate the start of an immediate
851 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
853 /* Separator character handling. */
855 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
858 skip_past_char (char ** str
, char c
)
869 #define skip_past_comma(str) skip_past_char (str, ',')
871 /* Arithmetic expressions (possibly involving symbols). */
873 /* Return TRUE if anything in the expression is a bignum. */
876 walk_no_bignums (symbolS
* sp
)
878 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
881 if (symbol_get_value_expression (sp
)->X_add_symbol
)
883 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
884 || (symbol_get_value_expression (sp
)->X_op_symbol
885 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
891 static int in_my_get_expression
= 0;
893 /* Third argument to my_get_expression. */
894 #define GE_NO_PREFIX 0
895 #define GE_IMM_PREFIX 1
896 #define GE_OPT_PREFIX 2
897 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
898 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
899 #define GE_OPT_PREFIX_BIG 3
902 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
907 /* In unified syntax, all prefixes are optional. */
909 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
914 case GE_NO_PREFIX
: break;
916 if (!is_immediate_prefix (**str
))
918 inst
.error
= _("immediate expression requires a # prefix");
924 case GE_OPT_PREFIX_BIG
:
925 if (is_immediate_prefix (**str
))
931 memset (ep
, 0, sizeof (expressionS
));
933 save_in
= input_line_pointer
;
934 input_line_pointer
= *str
;
935 in_my_get_expression
= 1;
936 seg
= expression (ep
);
937 in_my_get_expression
= 0;
939 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
941 /* We found a bad or missing expression in md_operand(). */
942 *str
= input_line_pointer
;
943 input_line_pointer
= save_in
;
944 if (inst
.error
== NULL
)
945 inst
.error
= (ep
->X_op
== O_absent
946 ? _("missing expression") :_("bad expression"));
951 if (seg
!= absolute_section
952 && seg
!= text_section
953 && seg
!= data_section
954 && seg
!= bss_section
955 && seg
!= undefined_section
)
957 inst
.error
= _("bad segment");
958 *str
= input_line_pointer
;
959 input_line_pointer
= save_in
;
966 /* Get rid of any bignums now, so that we don't generate an error for which
967 we can't establish a line number later on. Big numbers are never valid
968 in instructions, which is where this routine is always called. */
969 if (prefix_mode
!= GE_OPT_PREFIX_BIG
970 && (ep
->X_op
== O_big
972 && (walk_no_bignums (ep
->X_add_symbol
)
974 && walk_no_bignums (ep
->X_op_symbol
))))))
976 inst
.error
= _("invalid constant");
977 *str
= input_line_pointer
;
978 input_line_pointer
= save_in
;
982 *str
= input_line_pointer
;
983 input_line_pointer
= save_in
;
987 /* Turn a string in input_line_pointer into a floating point constant
988 of type TYPE, and store the appropriate bytes in *LITP. The number
989 of LITTLENUMS emitted is stored in *SIZEP. An error message is
990 returned, or NULL on OK.
992 Note that fp constants aren't represent in the normal way on the ARM.
993 In big endian mode, things are as expected. However, in little endian
994 mode fp constants are big-endian word-wise, and little-endian byte-wise
995 within the words. For example, (double) 1.1 in big endian mode is
996 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
997 the byte sequence 99 99 f1 3f 9a 99 99 99.
999 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1002 md_atof (int type
, char * litP
, int * sizeP
)
1005 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1037 return _("Unrecognized or unsupported floating point constant");
1040 t
= atof_ieee (input_line_pointer
, type
, words
);
1042 input_line_pointer
= t
;
1043 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1045 if (target_big_endian
)
1047 for (i
= 0; i
< prec
; i
++)
1049 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1050 litP
+= sizeof (LITTLENUM_TYPE
);
1055 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1056 for (i
= prec
- 1; i
>= 0; i
--)
1058 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1059 litP
+= sizeof (LITTLENUM_TYPE
);
1062 /* For a 4 byte float the order of elements in `words' is 1 0.
1063 For an 8 byte float the order is 1 0 3 2. */
1064 for (i
= 0; i
< prec
; i
+= 2)
1066 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1067 sizeof (LITTLENUM_TYPE
));
1068 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1069 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1070 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1077 /* We handle all bad expressions here, so that we can report the faulty
1078 instruction in the error message. */
1080 md_operand (expressionS
* exp
)
1082 if (in_my_get_expression
)
1083 exp
->X_op
= O_illegal
;
1086 /* Immediate values. */
1088 /* Generic immediate-value read function for use in directives.
1089 Accepts anything that 'expression' can fold to a constant.
1090 *val receives the number. */
1093 immediate_for_directive (int *val
)
1096 exp
.X_op
= O_illegal
;
1098 if (is_immediate_prefix (*input_line_pointer
))
1100 input_line_pointer
++;
1104 if (exp
.X_op
!= O_constant
)
1106 as_bad (_("expected #constant"));
1107 ignore_rest_of_line ();
1110 *val
= exp
.X_add_number
;
1115 /* Register parsing. */
1117 /* Generic register parser. CCP points to what should be the
1118 beginning of a register name. If it is indeed a valid register
1119 name, advance CCP over it and return the reg_entry structure;
1120 otherwise return NULL. Does not issue diagnostics. */
1122 static struct reg_entry
*
1123 arm_reg_parse_multi (char **ccp
)
1127 struct reg_entry
*reg
;
1129 #ifdef REGISTER_PREFIX
1130 if (*start
!= REGISTER_PREFIX
)
1134 #ifdef OPTIONAL_REGISTER_PREFIX
1135 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1140 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1145 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1147 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1157 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1158 enum arm_reg_type type
)
1160 /* Alternative syntaxes are accepted for a few register classes. */
1167 /* Generic coprocessor register names are allowed for these. */
1168 if (reg
&& reg
->type
== REG_TYPE_CN
)
1173 /* For backward compatibility, a bare number is valid here. */
1175 unsigned long processor
= strtoul (start
, ccp
, 10);
1176 if (*ccp
!= start
&& processor
<= 15)
1180 case REG_TYPE_MMXWC
:
1181 /* WC includes WCG. ??? I'm not sure this is true for all
1182 instructions that take WC registers. */
1183 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1194 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1195 return value is the register number or FAIL. */
1198 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1201 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1204 /* Do not allow a scalar (reg+index) to parse as a register. */
1205 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1208 if (reg
&& reg
->type
== type
)
1211 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1218 /* Parse a Neon type specifier. *STR should point at the leading '.'
1219 character. Does no verification at this stage that the type fits the opcode
1226 Can all be legally parsed by this function.
1228 Fills in neon_type struct pointer with parsed information, and updates STR
1229 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1230 type, FAIL if not. */
1233 parse_neon_type (struct neon_type
*type
, char **str
)
1240 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1242 enum neon_el_type thistype
= NT_untyped
;
1243 unsigned thissize
= -1u;
1250 /* Just a size without an explicit type. */
1254 switch (TOLOWER (*ptr
))
1256 case 'i': thistype
= NT_integer
; break;
1257 case 'f': thistype
= NT_float
; break;
1258 case 'p': thistype
= NT_poly
; break;
1259 case 's': thistype
= NT_signed
; break;
1260 case 'u': thistype
= NT_unsigned
; break;
1262 thistype
= NT_float
;
1267 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1273 /* .f is an abbreviation for .f32. */
1274 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1279 thissize
= strtoul (ptr
, &ptr
, 10);
1281 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1284 as_bad (_("bad size %d in type specifier"), thissize
);
1292 type
->el
[type
->elems
].type
= thistype
;
1293 type
->el
[type
->elems
].size
= thissize
;
1298 /* Empty/missing type is not a successful parse. */
1299 if (type
->elems
== 0)
1307 /* Errors may be set multiple times during parsing or bit encoding
1308 (particularly in the Neon bits), but usually the earliest error which is set
1309 will be the most meaningful. Avoid overwriting it with later (cascading)
1310 errors by calling this function. */
1313 first_error (const char *err
)
1319 /* Parse a single type, e.g. ".s32", leading period included. */
1321 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1324 struct neon_type optype
;
1328 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1330 if (optype
.elems
== 1)
1331 *vectype
= optype
.el
[0];
1334 first_error (_("only one type should be specified for operand"));
1340 first_error (_("vector type expected"));
1352 /* Special meanings for indices (which have a range of 0-7), which will fit into
1355 #define NEON_ALL_LANES 15
1356 #define NEON_INTERLEAVE_LANES 14
1358 /* Parse either a register or a scalar, with an optional type. Return the
1359 register number, and optionally fill in the actual type of the register
1360 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1361 type/index information in *TYPEINFO. */
1364 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1365 enum arm_reg_type
*rtype
,
1366 struct neon_typed_alias
*typeinfo
)
1369 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1370 struct neon_typed_alias atype
;
1371 struct neon_type_el parsetype
;
1375 atype
.eltype
.type
= NT_invtype
;
1376 atype
.eltype
.size
= -1;
1378 /* Try alternate syntax for some types of register. Note these are mutually
1379 exclusive with the Neon syntax extensions. */
1382 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1390 /* Undo polymorphism when a set of register types may be accepted. */
1391 if ((type
== REG_TYPE_NDQ
1392 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1393 || (type
== REG_TYPE_VFSD
1394 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1395 || (type
== REG_TYPE_NSDQ
1396 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1397 || reg
->type
== REG_TYPE_NQ
))
1398 || (type
== REG_TYPE_MMXWC
1399 && (reg
->type
== REG_TYPE_MMXWCG
)))
1400 type
= (enum arm_reg_type
) reg
->type
;
1402 if (type
!= reg
->type
)
1408 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1410 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1412 first_error (_("can't redefine type for operand"));
1415 atype
.defined
|= NTA_HASTYPE
;
1416 atype
.eltype
= parsetype
;
1419 if (skip_past_char (&str
, '[') == SUCCESS
)
1421 if (type
!= REG_TYPE_VFD
)
1423 first_error (_("only D registers may be indexed"));
1427 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1429 first_error (_("can't change index for operand"));
1433 atype
.defined
|= NTA_HASINDEX
;
1435 if (skip_past_char (&str
, ']') == SUCCESS
)
1436 atype
.index
= NEON_ALL_LANES
;
1441 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1443 if (exp
.X_op
!= O_constant
)
1445 first_error (_("constant expression required"));
1449 if (skip_past_char (&str
, ']') == FAIL
)
1452 atype
.index
= exp
.X_add_number
;
1467 /* Like arm_reg_parse, but allow allow the following extra features:
1468 - If RTYPE is non-zero, return the (possibly restricted) type of the
1469 register (e.g. Neon double or quad reg when either has been requested).
1470 - If this is a Neon vector type with additional type information, fill
1471 in the struct pointed to by VECTYPE (if non-NULL).
1472 This function will fault on encountering a scalar. */
1475 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1476 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1478 struct neon_typed_alias atype
;
1480 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1485 /* Do not allow regname(... to parse as a register. */
1489 /* Do not allow a scalar (reg+index) to parse as a register. */
1490 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1492 first_error (_("register operand expected, but got scalar"));
1497 *vectype
= atype
.eltype
;
1504 #define NEON_SCALAR_REG(X) ((X) >> 4)
1505 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1507 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1508 have enough information to be able to do a good job bounds-checking. So, we
1509 just do easy checks here, and do further checks later. */
1512 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1516 struct neon_typed_alias atype
;
1518 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1520 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1523 if (atype
.index
== NEON_ALL_LANES
)
1525 first_error (_("scalar must have an index"));
1528 else if (atype
.index
>= 64 / elsize
)
1530 first_error (_("scalar index out of range"));
1535 *type
= atype
.eltype
;
1539 return reg
* 16 + atype
.index
;
1542 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1545 parse_reg_list (char ** strp
)
1547 char * str
= * strp
;
1551 /* We come back here if we get ranges concatenated by '+' or '|'. */
1566 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1568 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1578 first_error (_("bad range in register list"));
1582 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1584 if (range
& (1 << i
))
1586 (_("Warning: duplicated register (r%d) in register list"),
1594 if (range
& (1 << reg
))
1595 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1597 else if (reg
<= cur_reg
)
1598 as_tsktsk (_("Warning: register range not in ascending order"));
1603 while (skip_past_comma (&str
) != FAIL
1604 || (in_range
= 1, *str
++ == '-'));
1609 first_error (_("missing `}'"));
1617 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1620 if (exp
.X_op
== O_constant
)
1622 if (exp
.X_add_number
1623 != (exp
.X_add_number
& 0x0000ffff))
1625 inst
.error
= _("invalid register mask");
1629 if ((range
& exp
.X_add_number
) != 0)
1631 int regno
= range
& exp
.X_add_number
;
1634 regno
= (1 << regno
) - 1;
1636 (_("Warning: duplicated register (r%d) in register list"),
1640 range
|= exp
.X_add_number
;
1644 if (inst
.reloc
.type
!= 0)
1646 inst
.error
= _("expression too complex");
1650 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1651 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1652 inst
.reloc
.pc_rel
= 0;
1656 if (*str
== '|' || *str
== '+')
1662 while (another_range
);
1668 /* Types of registers in a list. */
1677 /* Parse a VFP register list. If the string is invalid return FAIL.
1678 Otherwise return the number of registers, and set PBASE to the first
1679 register. Parses registers of type ETYPE.
1680 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1681 - Q registers can be used to specify pairs of D registers
1682 - { } can be omitted from around a singleton register list
1683 FIXME: This is not implemented, as it would require backtracking in
1686 This could be done (the meaning isn't really ambiguous), but doesn't
1687 fit in well with the current parsing framework.
1688 - 32 D registers may be used (also true for VFPv3).
1689 FIXME: Types are ignored in these register lists, which is probably a
1693 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1698 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1702 unsigned long mask
= 0;
1707 inst
.error
= _("expecting {");
1716 regtype
= REG_TYPE_VFS
;
1721 regtype
= REG_TYPE_VFD
;
1724 case REGLIST_NEON_D
:
1725 regtype
= REG_TYPE_NDQ
;
1729 if (etype
!= REGLIST_VFP_S
)
1731 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1732 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1736 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1739 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1746 base_reg
= max_regs
;
1750 int setmask
= 1, addregs
= 1;
1752 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1754 if (new_base
== FAIL
)
1756 first_error (_(reg_expected_msgs
[regtype
]));
1760 if (new_base
>= max_regs
)
1762 first_error (_("register out of range in list"));
1766 /* Note: a value of 2 * n is returned for the register Q<n>. */
1767 if (regtype
== REG_TYPE_NQ
)
1773 if (new_base
< base_reg
)
1774 base_reg
= new_base
;
1776 if (mask
& (setmask
<< new_base
))
1778 first_error (_("invalid register list"));
1782 if ((mask
>> new_base
) != 0 && ! warned
)
1784 as_tsktsk (_("register list not in ascending order"));
1788 mask
|= setmask
<< new_base
;
1791 if (*str
== '-') /* We have the start of a range expression */
1797 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1800 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1804 if (high_range
>= max_regs
)
1806 first_error (_("register out of range in list"));
1810 if (regtype
== REG_TYPE_NQ
)
1811 high_range
= high_range
+ 1;
1813 if (high_range
<= new_base
)
1815 inst
.error
= _("register range not in ascending order");
1819 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1821 if (mask
& (setmask
<< new_base
))
1823 inst
.error
= _("invalid register list");
1827 mask
|= setmask
<< new_base
;
1832 while (skip_past_comma (&str
) != FAIL
);
1836 /* Sanity check -- should have raised a parse error above. */
1837 if (count
== 0 || count
> max_regs
)
1842 /* Final test -- the registers must be consecutive. */
1844 for (i
= 0; i
< count
; i
++)
1846 if ((mask
& (1u << i
)) == 0)
1848 inst
.error
= _("non-contiguous register range");
1858 /* True if two alias types are the same. */
1861 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1869 if (a
->defined
!= b
->defined
)
1872 if ((a
->defined
& NTA_HASTYPE
) != 0
1873 && (a
->eltype
.type
!= b
->eltype
.type
1874 || a
->eltype
.size
!= b
->eltype
.size
))
1877 if ((a
->defined
& NTA_HASINDEX
) != 0
1878 && (a
->index
!= b
->index
))
1884 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1885 The base register is put in *PBASE.
1886 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1888 The register stride (minus one) is put in bit 4 of the return value.
1889 Bits [6:5] encode the list length (minus one).
1890 The type of the list elements is put in *ELTYPE, if non-NULL. */
1892 #define NEON_LANE(X) ((X) & 0xf)
1893 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1894 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1897 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1898 struct neon_type_el
*eltype
)
1905 int leading_brace
= 0;
1906 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1907 const char *const incr_error
= _("register stride must be 1 or 2");
1908 const char *const type_error
= _("mismatched element/structure types in list");
1909 struct neon_typed_alias firsttype
;
1911 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1916 struct neon_typed_alias atype
;
1917 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1921 first_error (_(reg_expected_msgs
[rtype
]));
1928 if (rtype
== REG_TYPE_NQ
)
1934 else if (reg_incr
== -1)
1936 reg_incr
= getreg
- base_reg
;
1937 if (reg_incr
< 1 || reg_incr
> 2)
1939 first_error (_(incr_error
));
1943 else if (getreg
!= base_reg
+ reg_incr
* count
)
1945 first_error (_(incr_error
));
1949 if (! neon_alias_types_same (&atype
, &firsttype
))
1951 first_error (_(type_error
));
1955 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1959 struct neon_typed_alias htype
;
1960 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1962 lane
= NEON_INTERLEAVE_LANES
;
1963 else if (lane
!= NEON_INTERLEAVE_LANES
)
1965 first_error (_(type_error
));
1970 else if (reg_incr
!= 1)
1972 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1976 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1979 first_error (_(reg_expected_msgs
[rtype
]));
1982 if (! neon_alias_types_same (&htype
, &firsttype
))
1984 first_error (_(type_error
));
1987 count
+= hireg
+ dregs
- getreg
;
1991 /* If we're using Q registers, we can't use [] or [n] syntax. */
1992 if (rtype
== REG_TYPE_NQ
)
1998 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2002 else if (lane
!= atype
.index
)
2004 first_error (_(type_error
));
2008 else if (lane
== -1)
2009 lane
= NEON_INTERLEAVE_LANES
;
2010 else if (lane
!= NEON_INTERLEAVE_LANES
)
2012 first_error (_(type_error
));
2017 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2019 /* No lane set by [x]. We must be interleaving structures. */
2021 lane
= NEON_INTERLEAVE_LANES
;
2024 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2025 || (count
> 1 && reg_incr
== -1))
2027 first_error (_("error parsing element/structure list"));
2031 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2033 first_error (_("expected }"));
2041 *eltype
= firsttype
.eltype
;
2046 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2049 /* Parse an explicit relocation suffix on an expression. This is
2050 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2051 arm_reloc_hsh contains no entries, so this function can only
2052 succeed if there is no () after the word. Returns -1 on error,
2053 BFD_RELOC_UNUSED if there wasn't any suffix. */
2055 parse_reloc (char **str
)
2057 struct reloc_entry
*r
;
2061 return BFD_RELOC_UNUSED
;
2066 while (*q
&& *q
!= ')' && *q
!= ',')
2071 if ((r
= (struct reloc_entry
*)
2072 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2079 /* Directives: register aliases. */
2081 static struct reg_entry
*
2082 insert_reg_alias (char *str
, unsigned number
, int type
)
2084 struct reg_entry
*new_reg
;
2087 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2089 if (new_reg
->builtin
)
2090 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2092 /* Only warn about a redefinition if it's not defined as the
2094 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2095 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2100 name
= xstrdup (str
);
2101 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2103 new_reg
->name
= name
;
2104 new_reg
->number
= number
;
2105 new_reg
->type
= type
;
2106 new_reg
->builtin
= FALSE
;
2107 new_reg
->neon
= NULL
;
2109 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2116 insert_neon_reg_alias (char *str
, int number
, int type
,
2117 struct neon_typed_alias
*atype
)
2119 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2123 first_error (_("attempt to redefine typed alias"));
2129 reg
->neon
= (struct neon_typed_alias
*)
2130 xmalloc (sizeof (struct neon_typed_alias
));
2131 *reg
->neon
= *atype
;
2135 /* Look for the .req directive. This is of the form:
2137 new_register_name .req existing_register_name
2139 If we find one, or if it looks sufficiently like one that we want to
2140 handle any error here, return TRUE. Otherwise return FALSE. */
2143 create_register_alias (char * newname
, char *p
)
2145 struct reg_entry
*old
;
2146 char *oldname
, *nbuf
;
2149 /* The input scrubber ensures that whitespace after the mnemonic is
2150 collapsed to single spaces. */
2152 if (strncmp (oldname
, " .req ", 6) != 0)
2156 if (*oldname
== '\0')
2159 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2162 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2166 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2167 the desired alias name, and p points to its end. If not, then
2168 the desired alias name is in the global original_case_string. */
2169 #ifdef TC_CASE_SENSITIVE
2172 newname
= original_case_string
;
2173 nlen
= strlen (newname
);
2176 nbuf
= (char *) alloca (nlen
+ 1);
2177 memcpy (nbuf
, newname
, nlen
);
2180 /* Create aliases under the new name as stated; an all-lowercase
2181 version of the new name; and an all-uppercase version of the new
2183 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2185 for (p
= nbuf
; *p
; p
++)
2188 if (strncmp (nbuf
, newname
, nlen
))
2190 /* If this attempt to create an additional alias fails, do not bother
2191 trying to create the all-lower case alias. We will fail and issue
2192 a second, duplicate error message. This situation arises when the
2193 programmer does something like:
2196 The second .req creates the "Foo" alias but then fails to create
2197 the artificial FOO alias because it has already been created by the
2199 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2203 for (p
= nbuf
; *p
; p
++)
2206 if (strncmp (nbuf
, newname
, nlen
))
2207 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2213 /* Create a Neon typed/indexed register alias using directives, e.g.:
2218 These typed registers can be used instead of the types specified after the
2219 Neon mnemonic, so long as all operands given have types. Types can also be
2220 specified directly, e.g.:
2221 vadd d0.s32, d1.s32, d2.s32 */
2224 create_neon_reg_alias (char *newname
, char *p
)
2226 enum arm_reg_type basetype
;
2227 struct reg_entry
*basereg
;
2228 struct reg_entry mybasereg
;
2229 struct neon_type ntype
;
2230 struct neon_typed_alias typeinfo
;
2231 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2234 typeinfo
.defined
= 0;
2235 typeinfo
.eltype
.type
= NT_invtype
;
2236 typeinfo
.eltype
.size
= -1;
2237 typeinfo
.index
= -1;
2241 if (strncmp (p
, " .dn ", 5) == 0)
2242 basetype
= REG_TYPE_VFD
;
2243 else if (strncmp (p
, " .qn ", 5) == 0)
2244 basetype
= REG_TYPE_NQ
;
2253 basereg
= arm_reg_parse_multi (&p
);
2255 if (basereg
&& basereg
->type
!= basetype
)
2257 as_bad (_("bad type for register"));
2261 if (basereg
== NULL
)
2264 /* Try parsing as an integer. */
2265 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2266 if (exp
.X_op
!= O_constant
)
2268 as_bad (_("expression must be constant"));
2271 basereg
= &mybasereg
;
2272 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2278 typeinfo
= *basereg
->neon
;
2280 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2282 /* We got a type. */
2283 if (typeinfo
.defined
& NTA_HASTYPE
)
2285 as_bad (_("can't redefine the type of a register alias"));
2289 typeinfo
.defined
|= NTA_HASTYPE
;
2290 if (ntype
.elems
!= 1)
2292 as_bad (_("you must specify a single type only"));
2295 typeinfo
.eltype
= ntype
.el
[0];
2298 if (skip_past_char (&p
, '[') == SUCCESS
)
2301 /* We got a scalar index. */
2303 if (typeinfo
.defined
& NTA_HASINDEX
)
2305 as_bad (_("can't redefine the index of a scalar alias"));
2309 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2311 if (exp
.X_op
!= O_constant
)
2313 as_bad (_("scalar index must be constant"));
2317 typeinfo
.defined
|= NTA_HASINDEX
;
2318 typeinfo
.index
= exp
.X_add_number
;
2320 if (skip_past_char (&p
, ']') == FAIL
)
2322 as_bad (_("expecting ]"));
2327 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2328 the desired alias name, and p points to its end. If not, then
2329 the desired alias name is in the global original_case_string. */
2330 #ifdef TC_CASE_SENSITIVE
2331 namelen
= nameend
- newname
;
2333 newname
= original_case_string
;
2334 namelen
= strlen (newname
);
2337 namebuf
= (char *) alloca (namelen
+ 1);
2338 strncpy (namebuf
, newname
, namelen
);
2339 namebuf
[namelen
] = '\0';
2341 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2342 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2344 /* Insert name in all uppercase. */
2345 for (p
= namebuf
; *p
; p
++)
2348 if (strncmp (namebuf
, newname
, namelen
))
2349 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2350 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2352 /* Insert name in all lowercase. */
2353 for (p
= namebuf
; *p
; p
++)
2356 if (strncmp (namebuf
, newname
, namelen
))
2357 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2358 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2363 /* Should never be called, as .req goes between the alias and the
2364 register name, not at the beginning of the line. */
2367 s_req (int a ATTRIBUTE_UNUSED
)
2369 as_bad (_("invalid syntax for .req directive"));
2373 s_dn (int a ATTRIBUTE_UNUSED
)
2375 as_bad (_("invalid syntax for .dn directive"));
2379 s_qn (int a ATTRIBUTE_UNUSED
)
2381 as_bad (_("invalid syntax for .qn directive"));
2384 /* The .unreq directive deletes an alias which was previously defined
2385 by .req. For example:
2391 s_unreq (int a ATTRIBUTE_UNUSED
)
2396 name
= input_line_pointer
;
2398 while (*input_line_pointer
!= 0
2399 && *input_line_pointer
!= ' '
2400 && *input_line_pointer
!= '\n')
2401 ++input_line_pointer
;
2403 saved_char
= *input_line_pointer
;
2404 *input_line_pointer
= 0;
2407 as_bad (_("invalid syntax for .unreq directive"));
2410 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2414 as_bad (_("unknown register alias '%s'"), name
);
2415 else if (reg
->builtin
)
2416 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2423 hash_delete (arm_reg_hsh
, name
, FALSE
);
2424 free ((char *) reg
->name
);
2429 /* Also locate the all upper case and all lower case versions.
2430 Do not complain if we cannot find one or the other as it
2431 was probably deleted above. */
2433 nbuf
= strdup (name
);
2434 for (p
= nbuf
; *p
; p
++)
2436 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2439 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2440 free ((char *) reg
->name
);
2446 for (p
= nbuf
; *p
; p
++)
2448 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2451 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2452 free ((char *) reg
->name
);
2462 *input_line_pointer
= saved_char
;
2463 demand_empty_rest_of_line ();
2466 /* Directives: Instruction set selection. */
2469 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2470 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2471 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2472 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2474 /* Create a new mapping symbol for the transition to STATE. */
2477 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2480 const char * symname
;
2487 type
= BSF_NO_FLAGS
;
2491 type
= BSF_NO_FLAGS
;
2495 type
= BSF_NO_FLAGS
;
2501 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2502 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2507 THUMB_SET_FUNC (symbolP
, 0);
2508 ARM_SET_THUMB (symbolP
, 0);
2509 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2513 THUMB_SET_FUNC (symbolP
, 1);
2514 ARM_SET_THUMB (symbolP
, 1);
2515 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2523 /* Save the mapping symbols for future reference. Also check that
2524 we do not place two mapping symbols at the same offset within a
2525 frag. We'll handle overlap between frags in
2526 check_mapping_symbols.
2528 If .fill or other data filling directive generates zero sized data,
2529 the mapping symbol for the following code will have the same value
2530 as the one generated for the data filling directive. In this case,
2531 we replace the old symbol with the new one at the same address. */
2534 if (frag
->tc_frag_data
.first_map
!= NULL
)
2536 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2537 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2539 frag
->tc_frag_data
.first_map
= symbolP
;
2541 if (frag
->tc_frag_data
.last_map
!= NULL
)
2543 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2544 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2545 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2547 frag
->tc_frag_data
.last_map
= symbolP
;
2550 /* We must sometimes convert a region marked as code to data during
2551 code alignment, if an odd number of bytes have to be padded. The
2552 code mapping symbol is pushed to an aligned address. */
2555 insert_data_mapping_symbol (enum mstate state
,
2556 valueT value
, fragS
*frag
, offsetT bytes
)
2558 /* If there was already a mapping symbol, remove it. */
2559 if (frag
->tc_frag_data
.last_map
!= NULL
2560 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2562 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2566 know (frag
->tc_frag_data
.first_map
== symp
);
2567 frag
->tc_frag_data
.first_map
= NULL
;
2569 frag
->tc_frag_data
.last_map
= NULL
;
2570 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2573 make_mapping_symbol (MAP_DATA
, value
, frag
);
2574 make_mapping_symbol (state
, value
+ bytes
, frag
);
2577 static void mapping_state_2 (enum mstate state
, int max_chars
);
2579 /* Set the mapping state to STATE. Only call this when about to
2580 emit some STATE bytes to the file. */
2583 mapping_state (enum mstate state
)
2585 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2587 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2589 if (mapstate
== state
)
2590 /* The mapping symbol has already been emitted.
2591 There is nothing else to do. */
2594 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2596 All ARM instructions require 4-byte alignment.
2597 (Almost) all Thumb instructions require 2-byte alignment.
2599 When emitting instructions into any section, mark the section
2602 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2603 but themselves require 2-byte alignment; this applies to some
2604 PC- relative forms. However, these cases will invovle implicit
2605 literal pool generation or an explicit .align >=2, both of
2606 which will cause the section to me marked with sufficient
2607 alignment. Thus, we don't handle those cases here. */
2608 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2610 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2611 /* This case will be evaluated later in the next else. */
2613 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2614 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2616 /* Only add the symbol if the offset is > 0:
2617 if we're at the first frag, check it's size > 0;
2618 if we're not at the first frag, then for sure
2619 the offset is > 0. */
2620 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2621 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2624 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2627 mapping_state_2 (state
, 0);
2631 /* Same as mapping_state, but MAX_CHARS bytes have already been
2632 allocated. Put the mapping symbol that far back. */
2635 mapping_state_2 (enum mstate state
, int max_chars
)
2637 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2639 if (!SEG_NORMAL (now_seg
))
2642 if (mapstate
== state
)
2643 /* The mapping symbol has already been emitted.
2644 There is nothing else to do. */
2647 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2648 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2651 #define mapping_state(x) ((void)0)
2652 #define mapping_state_2(x, y) ((void)0)
2655 /* Find the real, Thumb encoded start of a Thumb function. */
2659 find_real_start (symbolS
* symbolP
)
2662 const char * name
= S_GET_NAME (symbolP
);
2663 symbolS
* new_target
;
2665 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2666 #define STUB_NAME ".real_start_of"
2671 /* The compiler may generate BL instructions to local labels because
2672 it needs to perform a branch to a far away location. These labels
2673 do not have a corresponding ".real_start_of" label. We check
2674 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2675 the ".real_start_of" convention for nonlocal branches. */
2676 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2679 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2680 new_target
= symbol_find (real_start
);
2682 if (new_target
== NULL
)
2684 as_warn (_("Failed to find real start of function: %s\n"), name
);
2685 new_target
= symbolP
;
2693 opcode_select (int width
)
2700 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2701 as_bad (_("selected processor does not support THUMB opcodes"));
2704 /* No need to force the alignment, since we will have been
2705 coming from ARM mode, which is word-aligned. */
2706 record_alignment (now_seg
, 1);
2713 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2714 as_bad (_("selected processor does not support ARM opcodes"));
2719 frag_align (2, 0, 0);
2721 record_alignment (now_seg
, 1);
2726 as_bad (_("invalid instruction size selected (%d)"), width
);
2731 s_arm (int ignore ATTRIBUTE_UNUSED
)
2734 demand_empty_rest_of_line ();
2738 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2741 demand_empty_rest_of_line ();
2745 s_code (int unused ATTRIBUTE_UNUSED
)
2749 temp
= get_absolute_expression ();
2754 opcode_select (temp
);
2758 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2763 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2765 /* If we are not already in thumb mode go into it, EVEN if
2766 the target processor does not support thumb instructions.
2767 This is used by gcc/config/arm/lib1funcs.asm for example
2768 to compile interworking support functions even if the
2769 target processor should not support interworking. */
2773 record_alignment (now_seg
, 1);
2776 demand_empty_rest_of_line ();
2780 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2784 /* The following label is the name/address of the start of a Thumb function.
2785 We need to know this for the interworking support. */
2786 label_is_thumb_function_name
= TRUE
;
2789 /* Perform a .set directive, but also mark the alias as
2790 being a thumb function. */
2793 s_thumb_set (int equiv
)
2795 /* XXX the following is a duplicate of the code for s_set() in read.c
2796 We cannot just call that code as we need to get at the symbol that
2803 /* Especial apologies for the random logic:
2804 This just grew, and could be parsed much more simply!
2806 name
= input_line_pointer
;
2807 delim
= get_symbol_end ();
2808 end_name
= input_line_pointer
;
2811 if (*input_line_pointer
!= ',')
2814 as_bad (_("expected comma after name \"%s\""), name
);
2816 ignore_rest_of_line ();
2820 input_line_pointer
++;
2823 if (name
[0] == '.' && name
[1] == '\0')
2825 /* XXX - this should not happen to .thumb_set. */
2829 if ((symbolP
= symbol_find (name
)) == NULL
2830 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2833 /* When doing symbol listings, play games with dummy fragments living
2834 outside the normal fragment chain to record the file and line info
2836 if (listing
& LISTING_SYMBOLS
)
2838 extern struct list_info_struct
* listing_tail
;
2839 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2841 memset (dummy_frag
, 0, sizeof (fragS
));
2842 dummy_frag
->fr_type
= rs_fill
;
2843 dummy_frag
->line
= listing_tail
;
2844 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2845 dummy_frag
->fr_symbol
= symbolP
;
2849 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2852 /* "set" symbols are local unless otherwise specified. */
2853 SF_SET_LOCAL (symbolP
);
2854 #endif /* OBJ_COFF */
2855 } /* Make a new symbol. */
2857 symbol_table_insert (symbolP
);
2862 && S_IS_DEFINED (symbolP
)
2863 && S_GET_SEGMENT (symbolP
) != reg_section
)
2864 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2866 pseudo_set (symbolP
);
2868 demand_empty_rest_of_line ();
2870 /* XXX Now we come to the Thumb specific bit of code. */
2872 THUMB_SET_FUNC (symbolP
, 1);
2873 ARM_SET_THUMB (symbolP
, 1);
2874 #if defined OBJ_ELF || defined OBJ_COFF
2875 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2879 /* Directives: Mode selection. */
2881 /* .syntax [unified|divided] - choose the new unified syntax
2882 (same for Arm and Thumb encoding, modulo slight differences in what
2883 can be represented) or the old divergent syntax for each mode. */
2885 s_syntax (int unused ATTRIBUTE_UNUSED
)
2889 name
= input_line_pointer
;
2890 delim
= get_symbol_end ();
2892 if (!strcasecmp (name
, "unified"))
2893 unified_syntax
= TRUE
;
2894 else if (!strcasecmp (name
, "divided"))
2895 unified_syntax
= FALSE
;
2898 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2901 *input_line_pointer
= delim
;
2902 demand_empty_rest_of_line ();
2905 /* Directives: sectioning and alignment. */
2907 /* Same as s_align_ptwo but align 0 => align 2. */
2910 s_align (int unused ATTRIBUTE_UNUSED
)
2915 long max_alignment
= 15;
2917 temp
= get_absolute_expression ();
2918 if (temp
> max_alignment
)
2919 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2922 as_bad (_("alignment negative. 0 assumed."));
2926 if (*input_line_pointer
== ',')
2928 input_line_pointer
++;
2929 temp_fill
= get_absolute_expression ();
2941 /* Only make a frag if we HAVE to. */
2942 if (temp
&& !need_pass_2
)
2944 if (!fill_p
&& subseg_text_p (now_seg
))
2945 frag_align_code (temp
, 0);
2947 frag_align (temp
, (int) temp_fill
, 0);
2949 demand_empty_rest_of_line ();
2951 record_alignment (now_seg
, temp
);
2955 s_bss (int ignore ATTRIBUTE_UNUSED
)
2957 /* We don't support putting frags in the BSS segment, we fake it by
2958 marking in_bss, then looking at s_skip for clues. */
2959 subseg_set (bss_section
, 0);
2960 demand_empty_rest_of_line ();
2962 #ifdef md_elf_section_change_hook
2963 md_elf_section_change_hook ();
2968 s_even (int ignore ATTRIBUTE_UNUSED
)
2970 /* Never make frag if expect extra pass. */
2972 frag_align (1, 0, 0);
2974 record_alignment (now_seg
, 1);
2976 demand_empty_rest_of_line ();
2979 /* Directives: Literal pools. */
2981 static literal_pool
*
2982 find_literal_pool (void)
2984 literal_pool
* pool
;
2986 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2988 if (pool
->section
== now_seg
2989 && pool
->sub_section
== now_subseg
)
2996 static literal_pool
*
2997 find_or_make_literal_pool (void)
2999 /* Next literal pool ID number. */
3000 static unsigned int latest_pool_num
= 1;
3001 literal_pool
* pool
;
3003 pool
= find_literal_pool ();
3007 /* Create a new pool. */
3008 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3012 pool
->next_free_entry
= 0;
3013 pool
->section
= now_seg
;
3014 pool
->sub_section
= now_subseg
;
3015 pool
->next
= list_of_pools
;
3016 pool
->symbol
= NULL
;
3018 /* Add it to the list. */
3019 list_of_pools
= pool
;
3022 /* New pools, and emptied pools, will have a NULL symbol. */
3023 if (pool
->symbol
== NULL
)
3025 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3026 (valueT
) 0, &zero_address_frag
);
3027 pool
->id
= latest_pool_num
++;
3034 /* Add the literal in the global 'inst'
3035 structure to the relevant literal pool. */
3038 add_to_lit_pool (void)
3040 literal_pool
* pool
;
3043 pool
= find_or_make_literal_pool ();
3045 /* Check if this literal value is already in the pool. */
3046 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3048 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3049 && (inst
.reloc
.exp
.X_op
== O_constant
)
3050 && (pool
->literals
[entry
].X_add_number
3051 == inst
.reloc
.exp
.X_add_number
)
3052 && (pool
->literals
[entry
].X_unsigned
3053 == inst
.reloc
.exp
.X_unsigned
))
3056 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3057 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3058 && (pool
->literals
[entry
].X_add_number
3059 == inst
.reloc
.exp
.X_add_number
)
3060 && (pool
->literals
[entry
].X_add_symbol
3061 == inst
.reloc
.exp
.X_add_symbol
)
3062 && (pool
->literals
[entry
].X_op_symbol
3063 == inst
.reloc
.exp
.X_op_symbol
))
3067 /* Do we need to create a new entry? */
3068 if (entry
== pool
->next_free_entry
)
3070 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3072 inst
.error
= _("literal pool overflow");
3076 pool
->literals
[entry
] = inst
.reloc
.exp
;
3077 pool
->next_free_entry
+= 1;
3080 inst
.reloc
.exp
.X_op
= O_symbol
;
3081 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3082 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3087 /* Can't use symbol_new here, so have to create a symbol and then at
3088 a later date assign it a value. Thats what these functions do. */
3091 symbol_locate (symbolS
* symbolP
,
3092 const char * name
, /* It is copied, the caller can modify. */
3093 segT segment
, /* Segment identifier (SEG_<something>). */
3094 valueT valu
, /* Symbol value. */
3095 fragS
* frag
) /* Associated fragment. */
3097 unsigned int name_length
;
3098 char * preserved_copy_of_name
;
3100 name_length
= strlen (name
) + 1; /* +1 for \0. */
3101 obstack_grow (¬es
, name
, name_length
);
3102 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3104 #ifdef tc_canonicalize_symbol_name
3105 preserved_copy_of_name
=
3106 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3109 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3111 S_SET_SEGMENT (symbolP
, segment
);
3112 S_SET_VALUE (symbolP
, valu
);
3113 symbol_clear_list_pointers (symbolP
);
3115 symbol_set_frag (symbolP
, frag
);
3117 /* Link to end of symbol chain. */
3119 extern int symbol_table_frozen
;
3121 if (symbol_table_frozen
)
3125 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3127 obj_symbol_new_hook (symbolP
);
3129 #ifdef tc_symbol_new_hook
3130 tc_symbol_new_hook (symbolP
);
3134 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3135 #endif /* DEBUG_SYMS */
3140 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3143 literal_pool
* pool
;
3146 pool
= find_literal_pool ();
3148 || pool
->symbol
== NULL
3149 || pool
->next_free_entry
== 0)
3152 mapping_state (MAP_DATA
);
3154 /* Align pool as you have word accesses.
3155 Only make a frag if we have to. */
3157 frag_align (2, 0, 0);
3159 record_alignment (now_seg
, 2);
3161 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3163 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3164 (valueT
) frag_now_fix (), frag_now
);
3165 symbol_table_insert (pool
->symbol
);
3167 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3169 #if defined OBJ_COFF || defined OBJ_ELF
3170 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3173 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3174 /* First output the expression in the instruction to the pool. */
3175 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3177 /* Mark the pool as empty. */
3178 pool
->next_free_entry
= 0;
3179 pool
->symbol
= NULL
;
3183 /* Forward declarations for functions below, in the MD interface
3185 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3186 static valueT
create_unwind_entry (int);
3187 static void start_unwind_section (const segT
, int);
3188 static void add_unwind_opcode (valueT
, int);
3189 static void flush_pending_unwind (void);
3191 /* Directives: Data. */
3194 s_arm_elf_cons (int nbytes
)
3198 #ifdef md_flush_pending_output
3199 md_flush_pending_output ();
3202 if (is_it_end_of_statement ())
3204 demand_empty_rest_of_line ();
3208 #ifdef md_cons_align
3209 md_cons_align (nbytes
);
3212 mapping_state (MAP_DATA
);
3216 char *base
= input_line_pointer
;
3220 if (exp
.X_op
!= O_symbol
)
3221 emit_expr (&exp
, (unsigned int) nbytes
);
3224 char *before_reloc
= input_line_pointer
;
3225 reloc
= parse_reloc (&input_line_pointer
);
3228 as_bad (_("unrecognized relocation suffix"));
3229 ignore_rest_of_line ();
3232 else if (reloc
== BFD_RELOC_UNUSED
)
3233 emit_expr (&exp
, (unsigned int) nbytes
);
3236 reloc_howto_type
*howto
= (reloc_howto_type
*)
3237 bfd_reloc_type_lookup (stdoutput
,
3238 (bfd_reloc_code_real_type
) reloc
);
3239 int size
= bfd_get_reloc_size (howto
);
3241 if (reloc
== BFD_RELOC_ARM_PLT32
)
3243 as_bad (_("(plt) is only valid on branch targets"));
3244 reloc
= BFD_RELOC_UNUSED
;
3249 as_bad (_("%s relocations do not fit in %d bytes"),
3250 howto
->name
, nbytes
);
3253 /* We've parsed an expression stopping at O_symbol.
3254 But there may be more expression left now that we
3255 have parsed the relocation marker. Parse it again.
3256 XXX Surely there is a cleaner way to do this. */
3257 char *p
= input_line_pointer
;
3259 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3260 memcpy (save_buf
, base
, input_line_pointer
- base
);
3261 memmove (base
+ (input_line_pointer
- before_reloc
),
3262 base
, before_reloc
- base
);
3264 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3266 memcpy (base
, save_buf
, p
- base
);
3268 offset
= nbytes
- size
;
3269 p
= frag_more ((int) nbytes
);
3270 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3271 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3276 while (*input_line_pointer
++ == ',');
3278 /* Put terminator back into stream. */
3279 input_line_pointer
--;
3280 demand_empty_rest_of_line ();
3283 /* Emit an expression containing a 32-bit thumb instruction.
3284 Implementation based on put_thumb32_insn. */
3287 emit_thumb32_expr (expressionS
* exp
)
3289 expressionS exp_high
= *exp
;
3291 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3292 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3293 exp
->X_add_number
&= 0xffff;
3294 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3297 /* Guess the instruction size based on the opcode. */
3300 thumb_insn_size (int opcode
)
3302 if ((unsigned int) opcode
< 0xe800u
)
3304 else if ((unsigned int) opcode
>= 0xe8000000u
)
3311 emit_insn (expressionS
*exp
, int nbytes
)
3315 if (exp
->X_op
== O_constant
)
3320 size
= thumb_insn_size (exp
->X_add_number
);
3324 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3326 as_bad (_(".inst.n operand too big. "\
3327 "Use .inst.w instead"));
3332 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3333 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3335 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3337 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3338 emit_thumb32_expr (exp
);
3340 emit_expr (exp
, (unsigned int) size
);
3342 it_fsm_post_encode ();
3346 as_bad (_("cannot determine Thumb instruction size. " \
3347 "Use .inst.n/.inst.w instead"));
3350 as_bad (_("constant expression required"));
3355 /* Like s_arm_elf_cons but do not use md_cons_align and
3356 set the mapping state to MAP_ARM/MAP_THUMB. */
3359 s_arm_elf_inst (int nbytes
)
3361 if (is_it_end_of_statement ())
3363 demand_empty_rest_of_line ();
3367 /* Calling mapping_state () here will not change ARM/THUMB,
3368 but will ensure not to be in DATA state. */
3371 mapping_state (MAP_THUMB
);
3376 as_bad (_("width suffixes are invalid in ARM mode"));
3377 ignore_rest_of_line ();
3383 mapping_state (MAP_ARM
);
3392 if (! emit_insn (& exp
, nbytes
))
3394 ignore_rest_of_line ();
3398 while (*input_line_pointer
++ == ',');
3400 /* Put terminator back into stream. */
3401 input_line_pointer
--;
3402 demand_empty_rest_of_line ();
3405 /* Parse a .rel31 directive. */
3408 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3415 if (*input_line_pointer
== '1')
3416 highbit
= 0x80000000;
3417 else if (*input_line_pointer
!= '0')
3418 as_bad (_("expected 0 or 1"));
3420 input_line_pointer
++;
3421 if (*input_line_pointer
!= ',')
3422 as_bad (_("missing comma"));
3423 input_line_pointer
++;
3425 #ifdef md_flush_pending_output
3426 md_flush_pending_output ();
3429 #ifdef md_cons_align
3433 mapping_state (MAP_DATA
);
3438 md_number_to_chars (p
, highbit
, 4);
3439 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3440 BFD_RELOC_ARM_PREL31
);
3442 demand_empty_rest_of_line ();
3445 /* Directives: AEABI stack-unwind tables. */
3447 /* Parse an unwind_fnstart directive. Simply records the current location. */
3450 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3452 demand_empty_rest_of_line ();
3453 if (unwind
.proc_start
)
3455 as_bad (_("duplicate .fnstart directive"));
3459 /* Mark the start of the function. */
3460 unwind
.proc_start
= expr_build_dot ();
3462 /* Reset the rest of the unwind info. */
3463 unwind
.opcode_count
= 0;
3464 unwind
.table_entry
= NULL
;
3465 unwind
.personality_routine
= NULL
;
3466 unwind
.personality_index
= -1;
3467 unwind
.frame_size
= 0;
3468 unwind
.fp_offset
= 0;
3469 unwind
.fp_reg
= REG_SP
;
3471 unwind
.sp_restored
= 0;
3475 /* Parse a handlerdata directive. Creates the exception handling table entry
3476 for the function. */
3479 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3481 demand_empty_rest_of_line ();
3482 if (!unwind
.proc_start
)
3483 as_bad (MISSING_FNSTART
);
3485 if (unwind
.table_entry
)
3486 as_bad (_("duplicate .handlerdata directive"));
3488 create_unwind_entry (1);
3491 /* Parse an unwind_fnend directive. Generates the index table entry. */
3494 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3499 unsigned int marked_pr_dependency
;
3501 demand_empty_rest_of_line ();
3503 if (!unwind
.proc_start
)
3505 as_bad (_(".fnend directive without .fnstart"));
3509 /* Add eh table entry. */
3510 if (unwind
.table_entry
== NULL
)
3511 val
= create_unwind_entry (0);
3515 /* Add index table entry. This is two words. */
3516 start_unwind_section (unwind
.saved_seg
, 1);
3517 frag_align (2, 0, 0);
3518 record_alignment (now_seg
, 2);
3520 ptr
= frag_more (8);
3521 where
= frag_now_fix () - 8;
3523 /* Self relative offset of the function start. */
3524 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3525 BFD_RELOC_ARM_PREL31
);
3527 /* Indicate dependency on EHABI-defined personality routines to the
3528 linker, if it hasn't been done already. */
3529 marked_pr_dependency
3530 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3531 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3532 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3534 static const char *const name
[] =
3536 "__aeabi_unwind_cpp_pr0",
3537 "__aeabi_unwind_cpp_pr1",
3538 "__aeabi_unwind_cpp_pr2"
3540 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3541 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3542 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3543 |= 1 << unwind
.personality_index
;
3547 /* Inline exception table entry. */
3548 md_number_to_chars (ptr
+ 4, val
, 4);
3550 /* Self relative offset of the table entry. */
3551 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3552 BFD_RELOC_ARM_PREL31
);
3554 /* Restore the original section. */
3555 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3557 unwind
.proc_start
= NULL
;
3561 /* Parse an unwind_cantunwind directive. */
3564 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3566 demand_empty_rest_of_line ();
3567 if (!unwind
.proc_start
)
3568 as_bad (MISSING_FNSTART
);
3570 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3571 as_bad (_("personality routine specified for cantunwind frame"));
3573 unwind
.personality_index
= -2;
3577 /* Parse a personalityindex directive. */
3580 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3584 if (!unwind
.proc_start
)
3585 as_bad (MISSING_FNSTART
);
3587 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3588 as_bad (_("duplicate .personalityindex directive"));
3592 if (exp
.X_op
!= O_constant
3593 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3595 as_bad (_("bad personality routine number"));
3596 ignore_rest_of_line ();
3600 unwind
.personality_index
= exp
.X_add_number
;
3602 demand_empty_rest_of_line ();
3606 /* Parse a personality directive. */
3609 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3613 if (!unwind
.proc_start
)
3614 as_bad (MISSING_FNSTART
);
3616 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3617 as_bad (_("duplicate .personality directive"));
3619 name
= input_line_pointer
;
3620 c
= get_symbol_end ();
3621 p
= input_line_pointer
;
3622 unwind
.personality_routine
= symbol_find_or_make (name
);
3624 demand_empty_rest_of_line ();
3628 /* Parse a directive saving core registers. */
3631 s_arm_unwind_save_core (void)
3637 range
= parse_reg_list (&input_line_pointer
);
3640 as_bad (_("expected register list"));
3641 ignore_rest_of_line ();
3645 demand_empty_rest_of_line ();
3647 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3648 into .unwind_save {..., sp...}. We aren't bothered about the value of
3649 ip because it is clobbered by calls. */
3650 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3651 && (range
& 0x3000) == 0x1000)
3653 unwind
.opcode_count
--;
3654 unwind
.sp_restored
= 0;
3655 range
= (range
| 0x2000) & ~0x1000;
3656 unwind
.pending_offset
= 0;
3662 /* See if we can use the short opcodes. These pop a block of up to 8
3663 registers starting with r4, plus maybe r14. */
3664 for (n
= 0; n
< 8; n
++)
3666 /* Break at the first non-saved register. */
3667 if ((range
& (1 << (n
+ 4))) == 0)
3670 /* See if there are any other bits set. */
3671 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3673 /* Use the long form. */
3674 op
= 0x8000 | ((range
>> 4) & 0xfff);
3675 add_unwind_opcode (op
, 2);
3679 /* Use the short form. */
3681 op
= 0xa8; /* Pop r14. */
3683 op
= 0xa0; /* Do not pop r14. */
3685 add_unwind_opcode (op
, 1);
3692 op
= 0xb100 | (range
& 0xf);
3693 add_unwind_opcode (op
, 2);
3696 /* Record the number of bytes pushed. */
3697 for (n
= 0; n
< 16; n
++)
3699 if (range
& (1 << n
))
3700 unwind
.frame_size
+= 4;
3705 /* Parse a directive saving FPA registers. */
3708 s_arm_unwind_save_fpa (int reg
)
3714 /* Get Number of registers to transfer. */
3715 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3718 exp
.X_op
= O_illegal
;
3720 if (exp
.X_op
!= O_constant
)
3722 as_bad (_("expected , <constant>"));
3723 ignore_rest_of_line ();
3727 num_regs
= exp
.X_add_number
;
3729 if (num_regs
< 1 || num_regs
> 4)
3731 as_bad (_("number of registers must be in the range [1:4]"));
3732 ignore_rest_of_line ();
3736 demand_empty_rest_of_line ();
3741 op
= 0xb4 | (num_regs
- 1);
3742 add_unwind_opcode (op
, 1);
3747 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3748 add_unwind_opcode (op
, 2);
3750 unwind
.frame_size
+= num_regs
* 12;
3754 /* Parse a directive saving VFP registers for ARMv6 and above. */
3757 s_arm_unwind_save_vfp_armv6 (void)
3762 int num_vfpv3_regs
= 0;
3763 int num_regs_below_16
;
3765 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3768 as_bad (_("expected register list"));
3769 ignore_rest_of_line ();
3773 demand_empty_rest_of_line ();
3775 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3776 than FSTMX/FLDMX-style ones). */
3778 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3780 num_vfpv3_regs
= count
;
3781 else if (start
+ count
> 16)
3782 num_vfpv3_regs
= start
+ count
- 16;
3784 if (num_vfpv3_regs
> 0)
3786 int start_offset
= start
> 16 ? start
- 16 : 0;
3787 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3788 add_unwind_opcode (op
, 2);
3791 /* Generate opcode for registers numbered in the range 0 .. 15. */
3792 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3793 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3794 if (num_regs_below_16
> 0)
3796 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3797 add_unwind_opcode (op
, 2);
3800 unwind
.frame_size
+= count
* 8;
3804 /* Parse a directive saving VFP registers for pre-ARMv6. */
3807 s_arm_unwind_save_vfp (void)
3813 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3816 as_bad (_("expected register list"));
3817 ignore_rest_of_line ();
3821 demand_empty_rest_of_line ();
3826 op
= 0xb8 | (count
- 1);
3827 add_unwind_opcode (op
, 1);
3832 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3833 add_unwind_opcode (op
, 2);
3835 unwind
.frame_size
+= count
* 8 + 4;
3839 /* Parse a directive saving iWMMXt data registers. */
3842 s_arm_unwind_save_mmxwr (void)
3850 if (*input_line_pointer
== '{')
3851 input_line_pointer
++;
3855 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3859 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3864 as_tsktsk (_("register list not in ascending order"));
3867 if (*input_line_pointer
== '-')
3869 input_line_pointer
++;
3870 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3873 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3876 else if (reg
>= hi_reg
)
3878 as_bad (_("bad register range"));
3881 for (; reg
< hi_reg
; reg
++)
3885 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3887 if (*input_line_pointer
== '}')
3888 input_line_pointer
++;
3890 demand_empty_rest_of_line ();
3892 /* Generate any deferred opcodes because we're going to be looking at
3894 flush_pending_unwind ();
3896 for (i
= 0; i
< 16; i
++)
3898 if (mask
& (1 << i
))
3899 unwind
.frame_size
+= 8;
3902 /* Attempt to combine with a previous opcode. We do this because gcc
3903 likes to output separate unwind directives for a single block of
3905 if (unwind
.opcode_count
> 0)
3907 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3908 if ((i
& 0xf8) == 0xc0)
3911 /* Only merge if the blocks are contiguous. */
3914 if ((mask
& 0xfe00) == (1 << 9))
3916 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3917 unwind
.opcode_count
--;
3920 else if (i
== 6 && unwind
.opcode_count
>= 2)
3922 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3926 op
= 0xffff << (reg
- 1);
3928 && ((mask
& op
) == (1u << (reg
- 1))))
3930 op
= (1 << (reg
+ i
+ 1)) - 1;
3931 op
&= ~((1 << reg
) - 1);
3933 unwind
.opcode_count
-= 2;
3940 /* We want to generate opcodes in the order the registers have been
3941 saved, ie. descending order. */
3942 for (reg
= 15; reg
>= -1; reg
--)
3944 /* Save registers in blocks. */
3946 || !(mask
& (1 << reg
)))
3948 /* We found an unsaved reg. Generate opcodes to save the
3955 op
= 0xc0 | (hi_reg
- 10);
3956 add_unwind_opcode (op
, 1);
3961 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3962 add_unwind_opcode (op
, 2);
3971 ignore_rest_of_line ();
3975 s_arm_unwind_save_mmxwcg (void)
3982 if (*input_line_pointer
== '{')
3983 input_line_pointer
++;
3987 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3991 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3997 as_tsktsk (_("register list not in ascending order"));
4000 if (*input_line_pointer
== '-')
4002 input_line_pointer
++;
4003 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4006 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4009 else if (reg
>= hi_reg
)
4011 as_bad (_("bad register range"));
4014 for (; reg
< hi_reg
; reg
++)
4018 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4020 if (*input_line_pointer
== '}')
4021 input_line_pointer
++;
4023 demand_empty_rest_of_line ();
4025 /* Generate any deferred opcodes because we're going to be looking at
4027 flush_pending_unwind ();
4029 for (reg
= 0; reg
< 16; reg
++)
4031 if (mask
& (1 << reg
))
4032 unwind
.frame_size
+= 4;
4035 add_unwind_opcode (op
, 2);
4038 ignore_rest_of_line ();
4042 /* Parse an unwind_save directive.
4043 If the argument is non-zero, this is a .vsave directive. */
4046 s_arm_unwind_save (int arch_v6
)
4049 struct reg_entry
*reg
;
4050 bfd_boolean had_brace
= FALSE
;
4052 if (!unwind
.proc_start
)
4053 as_bad (MISSING_FNSTART
);
4055 /* Figure out what sort of save we have. */
4056 peek
= input_line_pointer
;
4064 reg
= arm_reg_parse_multi (&peek
);
4068 as_bad (_("register expected"));
4069 ignore_rest_of_line ();
4078 as_bad (_("FPA .unwind_save does not take a register list"));
4079 ignore_rest_of_line ();
4082 input_line_pointer
= peek
;
4083 s_arm_unwind_save_fpa (reg
->number
);
4086 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4089 s_arm_unwind_save_vfp_armv6 ();
4091 s_arm_unwind_save_vfp ();
4093 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4094 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4097 as_bad (_(".unwind_save does not support this kind of register"));
4098 ignore_rest_of_line ();
4103 /* Parse an unwind_movsp directive. */
4106 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4112 if (!unwind
.proc_start
)
4113 as_bad (MISSING_FNSTART
);
4115 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4118 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4119 ignore_rest_of_line ();
4123 /* Optional constant. */
4124 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4126 if (immediate_for_directive (&offset
) == FAIL
)
4132 demand_empty_rest_of_line ();
4134 if (reg
== REG_SP
|| reg
== REG_PC
)
4136 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4140 if (unwind
.fp_reg
!= REG_SP
)
4141 as_bad (_("unexpected .unwind_movsp directive"));
4143 /* Generate opcode to restore the value. */
4145 add_unwind_opcode (op
, 1);
4147 /* Record the information for later. */
4148 unwind
.fp_reg
= reg
;
4149 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4150 unwind
.sp_restored
= 1;
4153 /* Parse an unwind_pad directive. */
4156 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4160 if (!unwind
.proc_start
)
4161 as_bad (MISSING_FNSTART
);
4163 if (immediate_for_directive (&offset
) == FAIL
)
4168 as_bad (_("stack increment must be multiple of 4"));
4169 ignore_rest_of_line ();
4173 /* Don't generate any opcodes, just record the details for later. */
4174 unwind
.frame_size
+= offset
;
4175 unwind
.pending_offset
+= offset
;
4177 demand_empty_rest_of_line ();
4180 /* Parse an unwind_setfp directive. */
4183 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4189 if (!unwind
.proc_start
)
4190 as_bad (MISSING_FNSTART
);
4192 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4193 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4196 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4198 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4200 as_bad (_("expected <reg>, <reg>"));
4201 ignore_rest_of_line ();
4205 /* Optional constant. */
4206 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4208 if (immediate_for_directive (&offset
) == FAIL
)
4214 demand_empty_rest_of_line ();
4216 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4218 as_bad (_("register must be either sp or set by a previous"
4219 "unwind_movsp directive"));
4223 /* Don't generate any opcodes, just record the information for later. */
4224 unwind
.fp_reg
= fp_reg
;
4226 if (sp_reg
== REG_SP
)
4227 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4229 unwind
.fp_offset
-= offset
;
4232 /* Parse an unwind_raw directive. */
4235 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4238 /* This is an arbitrary limit. */
4239 unsigned char op
[16];
4242 if (!unwind
.proc_start
)
4243 as_bad (MISSING_FNSTART
);
4246 if (exp
.X_op
== O_constant
4247 && skip_past_comma (&input_line_pointer
) != FAIL
)
4249 unwind
.frame_size
+= exp
.X_add_number
;
4253 exp
.X_op
= O_illegal
;
4255 if (exp
.X_op
!= O_constant
)
4257 as_bad (_("expected <offset>, <opcode>"));
4258 ignore_rest_of_line ();
4264 /* Parse the opcode. */
4269 as_bad (_("unwind opcode too long"));
4270 ignore_rest_of_line ();
4272 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4274 as_bad (_("invalid unwind opcode"));
4275 ignore_rest_of_line ();
4278 op
[count
++] = exp
.X_add_number
;
4280 /* Parse the next byte. */
4281 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4287 /* Add the opcode bytes in reverse order. */
4289 add_unwind_opcode (op
[count
], 1);
4291 demand_empty_rest_of_line ();
4295 /* Parse a .eabi_attribute directive. */
4298 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4300 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4302 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4303 attributes_set_explicitly
[tag
] = 1;
4306 /* Emit a tls fix for the symbol. */
4309 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4313 #ifdef md_flush_pending_output
4314 md_flush_pending_output ();
4317 #ifdef md_cons_align
4321 /* Since we're just labelling the code, there's no need to define a
4324 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4325 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4326 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4327 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4329 #endif /* OBJ_ELF */
4331 static void s_arm_arch (int);
4332 static void s_arm_object_arch (int);
4333 static void s_arm_cpu (int);
4334 static void s_arm_fpu (int);
4335 static void s_arm_arch_extension (int);
4340 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4347 if (exp
.X_op
== O_symbol
)
4348 exp
.X_op
= O_secrel
;
4350 emit_expr (&exp
, 4);
4352 while (*input_line_pointer
++ == ',');
4354 input_line_pointer
--;
4355 demand_empty_rest_of_line ();
4359 /* This table describes all the machine specific pseudo-ops the assembler
4360 has to support. The fields are:
4361 pseudo-op name without dot
4362 function to call to execute this pseudo-op
4363 Integer arg to pass to the function. */
4365 const pseudo_typeS md_pseudo_table
[] =
4367 /* Never called because '.req' does not start a line. */
4368 { "req", s_req
, 0 },
4369 /* Following two are likewise never called. */
4372 { "unreq", s_unreq
, 0 },
4373 { "bss", s_bss
, 0 },
4374 { "align", s_align
, 0 },
4375 { "arm", s_arm
, 0 },
4376 { "thumb", s_thumb
, 0 },
4377 { "code", s_code
, 0 },
4378 { "force_thumb", s_force_thumb
, 0 },
4379 { "thumb_func", s_thumb_func
, 0 },
4380 { "thumb_set", s_thumb_set
, 0 },
4381 { "even", s_even
, 0 },
4382 { "ltorg", s_ltorg
, 0 },
4383 { "pool", s_ltorg
, 0 },
4384 { "syntax", s_syntax
, 0 },
4385 { "cpu", s_arm_cpu
, 0 },
4386 { "arch", s_arm_arch
, 0 },
4387 { "object_arch", s_arm_object_arch
, 0 },
4388 { "fpu", s_arm_fpu
, 0 },
4389 { "arch_extension", s_arm_arch_extension
, 0 },
4391 { "word", s_arm_elf_cons
, 4 },
4392 { "long", s_arm_elf_cons
, 4 },
4393 { "inst.n", s_arm_elf_inst
, 2 },
4394 { "inst.w", s_arm_elf_inst
, 4 },
4395 { "inst", s_arm_elf_inst
, 0 },
4396 { "rel31", s_arm_rel31
, 0 },
4397 { "fnstart", s_arm_unwind_fnstart
, 0 },
4398 { "fnend", s_arm_unwind_fnend
, 0 },
4399 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4400 { "personality", s_arm_unwind_personality
, 0 },
4401 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4402 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4403 { "save", s_arm_unwind_save
, 0 },
4404 { "vsave", s_arm_unwind_save
, 1 },
4405 { "movsp", s_arm_unwind_movsp
, 0 },
4406 { "pad", s_arm_unwind_pad
, 0 },
4407 { "setfp", s_arm_unwind_setfp
, 0 },
4408 { "unwind_raw", s_arm_unwind_raw
, 0 },
4409 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4410 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4414 /* These are used for dwarf. */
4418 /* These are used for dwarf2. */
4419 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4420 { "loc", dwarf2_directive_loc
, 0 },
4421 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4423 { "extend", float_cons
, 'x' },
4424 { "ldouble", float_cons
, 'x' },
4425 { "packed", float_cons
, 'p' },
4427 {"secrel32", pe_directive_secrel
, 0},
4432 /* Parser functions used exclusively in instruction operands. */
4434 /* Generic immediate-value read function for use in insn parsing.
4435 STR points to the beginning of the immediate (the leading #);
4436 VAL receives the value; if the value is outside [MIN, MAX]
4437 issue an error. PREFIX_OPT is true if the immediate prefix is
4441 parse_immediate (char **str
, int *val
, int min
, int max
,
4442 bfd_boolean prefix_opt
)
4445 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4446 if (exp
.X_op
!= O_constant
)
4448 inst
.error
= _("constant expression required");
4452 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4454 inst
.error
= _("immediate value out of range");
4458 *val
= exp
.X_add_number
;
4462 /* Less-generic immediate-value read function with the possibility of loading a
4463 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4464 instructions. Puts the result directly in inst.operands[i]. */
4467 parse_big_immediate (char **str
, int i
)
4472 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4474 if (exp
.X_op
== O_constant
)
4476 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4477 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4478 O_constant. We have to be careful not to break compilation for
4479 32-bit X_add_number, though. */
4480 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4482 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4483 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4484 inst
.operands
[i
].regisimm
= 1;
4487 else if (exp
.X_op
== O_big
4488 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4490 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4492 /* Bignums have their least significant bits in
4493 generic_bignum[0]. Make sure we put 32 bits in imm and
4494 32 bits in reg, in a (hopefully) portable way. */
4495 gas_assert (parts
!= 0);
4497 /* Make sure that the number is not too big.
4498 PR 11972: Bignums can now be sign-extended to the
4499 size of a .octa so check that the out of range bits
4500 are all zero or all one. */
4501 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4503 LITTLENUM_TYPE m
= -1;
4505 if (generic_bignum
[parts
* 2] != 0
4506 && generic_bignum
[parts
* 2] != m
)
4509 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4510 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4514 inst
.operands
[i
].imm
= 0;
4515 for (j
= 0; j
< parts
; j
++, idx
++)
4516 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4517 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4518 inst
.operands
[i
].reg
= 0;
4519 for (j
= 0; j
< parts
; j
++, idx
++)
4520 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4521 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4522 inst
.operands
[i
].regisimm
= 1;
4532 /* Returns the pseudo-register number of an FPA immediate constant,
4533 or FAIL if there isn't a valid constant here. */
4536 parse_fpa_immediate (char ** str
)
4538 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4544 /* First try and match exact strings, this is to guarantee
4545 that some formats will work even for cross assembly. */
4547 for (i
= 0; fp_const
[i
]; i
++)
4549 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4553 *str
+= strlen (fp_const
[i
]);
4554 if (is_end_of_line
[(unsigned char) **str
])
4560 /* Just because we didn't get a match doesn't mean that the constant
4561 isn't valid, just that it is in a format that we don't
4562 automatically recognize. Try parsing it with the standard
4563 expression routines. */
4565 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4567 /* Look for a raw floating point number. */
4568 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4569 && is_end_of_line
[(unsigned char) *save_in
])
4571 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4573 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4575 if (words
[j
] != fp_values
[i
][j
])
4579 if (j
== MAX_LITTLENUMS
)
4587 /* Try and parse a more complex expression, this will probably fail
4588 unless the code uses a floating point prefix (eg "0f"). */
4589 save_in
= input_line_pointer
;
4590 input_line_pointer
= *str
;
4591 if (expression (&exp
) == absolute_section
4592 && exp
.X_op
== O_big
4593 && exp
.X_add_number
< 0)
4595 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4597 if (gen_to_words (words
, 5, (long) 15) == 0)
4599 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4601 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4603 if (words
[j
] != fp_values
[i
][j
])
4607 if (j
== MAX_LITTLENUMS
)
4609 *str
= input_line_pointer
;
4610 input_line_pointer
= save_in
;
4617 *str
= input_line_pointer
;
4618 input_line_pointer
= save_in
;
4619 inst
.error
= _("invalid FPA immediate expression");
4623 /* Returns 1 if a number has "quarter-precision" float format
4624 0baBbbbbbc defgh000 00000000 00000000. */
4627 is_quarter_float (unsigned imm
)
4629 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4630 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4633 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4634 0baBbbbbbc defgh000 00000000 00000000.
4635 The zero and minus-zero cases need special handling, since they can't be
4636 encoded in the "quarter-precision" float format, but can nonetheless be
4637 loaded as integer constants. */
4640 parse_qfloat_immediate (char **ccp
, int *immed
)
4644 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4645 int found_fpchar
= 0;
4647 skip_past_char (&str
, '#');
4649 /* We must not accidentally parse an integer as a floating-point number. Make
4650 sure that the value we parse is not an integer by checking for special
4651 characters '.' or 'e'.
4652 FIXME: This is a horrible hack, but doing better is tricky because type
4653 information isn't in a very usable state at parse time. */
4655 skip_whitespace (fpnum
);
4657 if (strncmp (fpnum
, "0x", 2) == 0)
4661 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4662 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4672 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4674 unsigned fpword
= 0;
4677 /* Our FP word must be 32 bits (single-precision FP). */
4678 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4680 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4684 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4697 /* Shift operands. */
4700 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4703 struct asm_shift_name
4706 enum shift_kind kind
;
4709 /* Third argument to parse_shift. */
4710 enum parse_shift_mode
4712 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4713 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4714 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4715 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4716 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4719 /* Parse a <shift> specifier on an ARM data processing instruction.
4720 This has three forms:
4722 (LSL|LSR|ASL|ASR|ROR) Rs
4723 (LSL|LSR|ASL|ASR|ROR) #imm
4726 Note that ASL is assimilated to LSL in the instruction encoding, and
4727 RRX to ROR #0 (which cannot be written as such). */
4730 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4732 const struct asm_shift_name
*shift_name
;
4733 enum shift_kind shift
;
4738 for (p
= *str
; ISALPHA (*p
); p
++)
4743 inst
.error
= _("shift expression expected");
4747 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4750 if (shift_name
== NULL
)
4752 inst
.error
= _("shift expression expected");
4756 shift
= shift_name
->kind
;
4760 case NO_SHIFT_RESTRICT
:
4761 case SHIFT_IMMEDIATE
: break;
4763 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4764 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4766 inst
.error
= _("'LSL' or 'ASR' required");
4771 case SHIFT_LSL_IMMEDIATE
:
4772 if (shift
!= SHIFT_LSL
)
4774 inst
.error
= _("'LSL' required");
4779 case SHIFT_ASR_IMMEDIATE
:
4780 if (shift
!= SHIFT_ASR
)
4782 inst
.error
= _("'ASR' required");
4790 if (shift
!= SHIFT_RRX
)
4792 /* Whitespace can appear here if the next thing is a bare digit. */
4793 skip_whitespace (p
);
4795 if (mode
== NO_SHIFT_RESTRICT
4796 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4798 inst
.operands
[i
].imm
= reg
;
4799 inst
.operands
[i
].immisreg
= 1;
4801 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4804 inst
.operands
[i
].shift_kind
= shift
;
4805 inst
.operands
[i
].shifted
= 1;
4810 /* Parse a <shifter_operand> for an ARM data processing instruction:
4813 #<immediate>, <rotate>
4817 where <shift> is defined by parse_shift above, and <rotate> is a
4818 multiple of 2 between 0 and 30. Validation of immediate operands
4819 is deferred to md_apply_fix. */
4822 parse_shifter_operand (char **str
, int i
)
4827 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4829 inst
.operands
[i
].reg
= value
;
4830 inst
.operands
[i
].isreg
= 1;
4832 /* parse_shift will override this if appropriate */
4833 inst
.reloc
.exp
.X_op
= O_constant
;
4834 inst
.reloc
.exp
.X_add_number
= 0;
4836 if (skip_past_comma (str
) == FAIL
)
4839 /* Shift operation on register. */
4840 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4843 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4846 if (skip_past_comma (str
) == SUCCESS
)
4848 /* #x, y -- ie explicit rotation by Y. */
4849 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4852 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4854 inst
.error
= _("constant expression expected");
4858 value
= exp
.X_add_number
;
4859 if (value
< 0 || value
> 30 || value
% 2 != 0)
4861 inst
.error
= _("invalid rotation");
4864 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4866 inst
.error
= _("invalid constant");
4870 /* Convert to decoded value. md_apply_fix will put it back. */
4871 inst
.reloc
.exp
.X_add_number
4872 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4873 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4876 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4877 inst
.reloc
.pc_rel
= 0;
4881 /* Group relocation information. Each entry in the table contains the
4882 textual name of the relocation as may appear in assembler source
4883 and must end with a colon.
4884 Along with this textual name are the relocation codes to be used if
4885 the corresponding instruction is an ALU instruction (ADD or SUB only),
4886 an LDR, an LDRS, or an LDC. */
4888 struct group_reloc_table_entry
4899 /* Varieties of non-ALU group relocation. */
4906 static struct group_reloc_table_entry group_reloc_table
[] =
4907 { /* Program counter relative: */
4909 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4914 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4915 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4916 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4917 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4919 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4924 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4925 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4926 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4927 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4929 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4930 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4931 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4932 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4933 /* Section base relative */
4935 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4940 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4941 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4942 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4943 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4945 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4950 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4951 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4952 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4953 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4955 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4956 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4957 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4958 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4960 /* Given the address of a pointer pointing to the textual name of a group
4961 relocation as may appear in assembler source, attempt to find its details
4962 in group_reloc_table. The pointer will be updated to the character after
4963 the trailing colon. On failure, FAIL will be returned; SUCCESS
4964 otherwise. On success, *entry will be updated to point at the relevant
4965 group_reloc_table entry. */
4968 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4971 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4973 int length
= strlen (group_reloc_table
[i
].name
);
4975 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4976 && (*str
)[length
] == ':')
4978 *out
= &group_reloc_table
[i
];
4979 *str
+= (length
+ 1);
4987 /* Parse a <shifter_operand> for an ARM data processing instruction
4988 (as for parse_shifter_operand) where group relocations are allowed:
4991 #<immediate>, <rotate>
4992 #:<group_reloc>:<expression>
4996 where <group_reloc> is one of the strings defined in group_reloc_table.
4997 The hashes are optional.
4999 Everything else is as for parse_shifter_operand. */
5001 static parse_operand_result
5002 parse_shifter_operand_group_reloc (char **str
, int i
)
5004 /* Determine if we have the sequence of characters #: or just :
5005 coming next. If we do, then we check for a group relocation.
5006 If we don't, punt the whole lot to parse_shifter_operand. */
5008 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5009 || (*str
)[0] == ':')
5011 struct group_reloc_table_entry
*entry
;
5013 if ((*str
)[0] == '#')
5018 /* Try to parse a group relocation. Anything else is an error. */
5019 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5021 inst
.error
= _("unknown group relocation");
5022 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5025 /* We now have the group relocation table entry corresponding to
5026 the name in the assembler source. Next, we parse the expression. */
5027 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5028 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5030 /* Record the relocation type (always the ALU variant here). */
5031 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5032 gas_assert (inst
.reloc
.type
!= 0);
5034 return PARSE_OPERAND_SUCCESS
;
5037 return parse_shifter_operand (str
, i
) == SUCCESS
5038 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5040 /* Never reached. */
5043 /* Parse a Neon alignment expression. Information is written to
5044 inst.operands[i]. We assume the initial ':' has been skipped.
5046 align .imm = align << 8, .immisalign=1, .preind=0 */
5047 static parse_operand_result
5048 parse_neon_alignment (char **str
, int i
)
5053 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5055 if (exp
.X_op
!= O_constant
)
5057 inst
.error
= _("alignment must be constant");
5058 return PARSE_OPERAND_FAIL
;
5061 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5062 inst
.operands
[i
].immisalign
= 1;
5063 /* Alignments are not pre-indexes. */
5064 inst
.operands
[i
].preind
= 0;
5067 return PARSE_OPERAND_SUCCESS
;
5070 /* Parse all forms of an ARM address expression. Information is written
5071 to inst.operands[i] and/or inst.reloc.
5073 Preindexed addressing (.preind=1):
5075 [Rn, #offset] .reg=Rn .reloc.exp=offset
5076 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5077 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5078 .shift_kind=shift .reloc.exp=shift_imm
5080 These three may have a trailing ! which causes .writeback to be set also.
5082 Postindexed addressing (.postind=1, .writeback=1):
5084 [Rn], #offset .reg=Rn .reloc.exp=offset
5085 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5086 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5087 .shift_kind=shift .reloc.exp=shift_imm
5089 Unindexed addressing (.preind=0, .postind=0):
5091 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5095 [Rn]{!} shorthand for [Rn,#0]{!}
5096 =immediate .isreg=0 .reloc.exp=immediate
5097 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5099 It is the caller's responsibility to check for addressing modes not
5100 supported by the instruction, and to set inst.reloc.type. */
5102 static parse_operand_result
5103 parse_address_main (char **str
, int i
, int group_relocations
,
5104 group_reloc_type group_type
)
5109 if (skip_past_char (&p
, '[') == FAIL
)
5111 if (skip_past_char (&p
, '=') == FAIL
)
5113 /* Bare address - translate to PC-relative offset. */
5114 inst
.reloc
.pc_rel
= 1;
5115 inst
.operands
[i
].reg
= REG_PC
;
5116 inst
.operands
[i
].isreg
= 1;
5117 inst
.operands
[i
].preind
= 1;
5119 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5121 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5122 return PARSE_OPERAND_FAIL
;
5125 return PARSE_OPERAND_SUCCESS
;
5128 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5130 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5131 return PARSE_OPERAND_FAIL
;
5133 inst
.operands
[i
].reg
= reg
;
5134 inst
.operands
[i
].isreg
= 1;
5136 if (skip_past_comma (&p
) == SUCCESS
)
5138 inst
.operands
[i
].preind
= 1;
5141 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5143 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5145 inst
.operands
[i
].imm
= reg
;
5146 inst
.operands
[i
].immisreg
= 1;
5148 if (skip_past_comma (&p
) == SUCCESS
)
5149 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5150 return PARSE_OPERAND_FAIL
;
5152 else if (skip_past_char (&p
, ':') == SUCCESS
)
5154 /* FIXME: '@' should be used here, but it's filtered out by generic
5155 code before we get to see it here. This may be subject to
5157 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5159 if (result
!= PARSE_OPERAND_SUCCESS
)
5164 if (inst
.operands
[i
].negative
)
5166 inst
.operands
[i
].negative
= 0;
5170 if (group_relocations
5171 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5173 struct group_reloc_table_entry
*entry
;
5175 /* Skip over the #: or : sequence. */
5181 /* Try to parse a group relocation. Anything else is an
5183 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5185 inst
.error
= _("unknown group relocation");
5186 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5189 /* We now have the group relocation table entry corresponding to
5190 the name in the assembler source. Next, we parse the
5192 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5193 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5195 /* Record the relocation type. */
5199 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5203 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5207 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5214 if (inst
.reloc
.type
== 0)
5216 inst
.error
= _("this group relocation is not allowed on this instruction");
5217 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5223 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5224 return PARSE_OPERAND_FAIL
;
5225 /* If the offset is 0, find out if it's a +0 or -0. */
5226 if (inst
.reloc
.exp
.X_op
== O_constant
5227 && inst
.reloc
.exp
.X_add_number
== 0)
5229 skip_whitespace (q
);
5233 skip_whitespace (q
);
5236 inst
.operands
[i
].negative
= 1;
5241 else if (skip_past_char (&p
, ':') == SUCCESS
)
5243 /* FIXME: '@' should be used here, but it's filtered out by generic code
5244 before we get to see it here. This may be subject to change. */
5245 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5247 if (result
!= PARSE_OPERAND_SUCCESS
)
5251 if (skip_past_char (&p
, ']') == FAIL
)
5253 inst
.error
= _("']' expected");
5254 return PARSE_OPERAND_FAIL
;
5257 if (skip_past_char (&p
, '!') == SUCCESS
)
5258 inst
.operands
[i
].writeback
= 1;
5260 else if (skip_past_comma (&p
) == SUCCESS
)
5262 if (skip_past_char (&p
, '{') == SUCCESS
)
5264 /* [Rn], {expr} - unindexed, with option */
5265 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5266 0, 255, TRUE
) == FAIL
)
5267 return PARSE_OPERAND_FAIL
;
5269 if (skip_past_char (&p
, '}') == FAIL
)
5271 inst
.error
= _("'}' expected at end of 'option' field");
5272 return PARSE_OPERAND_FAIL
;
5274 if (inst
.operands
[i
].preind
)
5276 inst
.error
= _("cannot combine index with option");
5277 return PARSE_OPERAND_FAIL
;
5280 return PARSE_OPERAND_SUCCESS
;
5284 inst
.operands
[i
].postind
= 1;
5285 inst
.operands
[i
].writeback
= 1;
5287 if (inst
.operands
[i
].preind
)
5289 inst
.error
= _("cannot combine pre- and post-indexing");
5290 return PARSE_OPERAND_FAIL
;
5294 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5296 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5298 /* We might be using the immediate for alignment already. If we
5299 are, OR the register number into the low-order bits. */
5300 if (inst
.operands
[i
].immisalign
)
5301 inst
.operands
[i
].imm
|= reg
;
5303 inst
.operands
[i
].imm
= reg
;
5304 inst
.operands
[i
].immisreg
= 1;
5306 if (skip_past_comma (&p
) == SUCCESS
)
5307 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5308 return PARSE_OPERAND_FAIL
;
5313 if (inst
.operands
[i
].negative
)
5315 inst
.operands
[i
].negative
= 0;
5318 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5319 return PARSE_OPERAND_FAIL
;
5320 /* If the offset is 0, find out if it's a +0 or -0. */
5321 if (inst
.reloc
.exp
.X_op
== O_constant
5322 && inst
.reloc
.exp
.X_add_number
== 0)
5324 skip_whitespace (q
);
5328 skip_whitespace (q
);
5331 inst
.operands
[i
].negative
= 1;
5337 /* If at this point neither .preind nor .postind is set, we have a
5338 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5339 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5341 inst
.operands
[i
].preind
= 1;
5342 inst
.reloc
.exp
.X_op
= O_constant
;
5343 inst
.reloc
.exp
.X_add_number
= 0;
5346 return PARSE_OPERAND_SUCCESS
;
5350 parse_address (char **str
, int i
)
5352 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5356 static parse_operand_result
5357 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5359 return parse_address_main (str
, i
, 1, type
);
5362 /* Parse an operand for a MOVW or MOVT instruction. */
5364 parse_half (char **str
)
5369 skip_past_char (&p
, '#');
5370 if (strncasecmp (p
, ":lower16:", 9) == 0)
5371 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5372 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5373 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5375 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5378 skip_whitespace (p
);
5381 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5384 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5386 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5388 inst
.error
= _("constant expression expected");
5391 if (inst
.reloc
.exp
.X_add_number
< 0
5392 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5394 inst
.error
= _("immediate value out of range");
5402 /* Miscellaneous. */
5404 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5405 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5407 parse_psr (char **str
, bfd_boolean lhs
)
5410 unsigned long psr_field
;
5411 const struct asm_psr
*psr
;
5413 bfd_boolean is_apsr
= FALSE
;
5414 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5416 /* PR gas/12698: If the user has specified -march=all then m_profile will
5417 be TRUE, but we want to ignore it in this case as we are building for any
5418 CPU type, including non-m variants. */
5419 if (selected_cpu
.core
== arm_arch_any
.core
)
5422 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5423 feature for ease of use and backwards compatibility. */
5425 if (strncasecmp (p
, "SPSR", 4) == 0)
5428 goto unsupported_psr
;
5430 psr_field
= SPSR_BIT
;
5432 else if (strncasecmp (p
, "CPSR", 4) == 0)
5435 goto unsupported_psr
;
5439 else if (strncasecmp (p
, "APSR", 4) == 0)
5441 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5442 and ARMv7-R architecture CPUs. */
5451 while (ISALNUM (*p
) || *p
== '_');
5453 if (strncasecmp (start
, "iapsr", 5) == 0
5454 || strncasecmp (start
, "eapsr", 5) == 0
5455 || strncasecmp (start
, "xpsr", 4) == 0
5456 || strncasecmp (start
, "psr", 3) == 0)
5457 p
= start
+ strcspn (start
, "rR") + 1;
5459 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5465 /* If APSR is being written, a bitfield may be specified. Note that
5466 APSR itself is handled above. */
5467 if (psr
->field
<= 3)
5469 psr_field
= psr
->field
;
5475 /* M-profile MSR instructions have the mask field set to "10", except
5476 *PSR variants which modify APSR, which may use a different mask (and
5477 have been handled already). Do that by setting the PSR_f field
5479 return psr
->field
| (lhs
? PSR_f
: 0);
5482 goto unsupported_psr
;
5488 /* A suffix follows. */
5494 while (ISALNUM (*p
) || *p
== '_');
5498 /* APSR uses a notation for bits, rather than fields. */
5499 unsigned int nzcvq_bits
= 0;
5500 unsigned int g_bit
= 0;
5503 for (bit
= start
; bit
!= p
; bit
++)
5505 switch (TOLOWER (*bit
))
5508 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5512 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5516 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5520 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5524 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5528 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5532 inst
.error
= _("unexpected bit specified after APSR");
5537 if (nzcvq_bits
== 0x1f)
5542 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5544 inst
.error
= _("selected processor does not "
5545 "support DSP extension");
5552 if ((nzcvq_bits
& 0x20) != 0
5553 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5554 || (g_bit
& 0x2) != 0)
5556 inst
.error
= _("bad bitmask specified after APSR");
5562 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5567 psr_field
|= psr
->field
;
5573 goto error
; /* Garbage after "[CS]PSR". */
5575 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5576 is deprecated, but allow it anyway. */
5580 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5583 else if (!m_profile
)
5584 /* These bits are never right for M-profile devices: don't set them
5585 (only code paths which read/write APSR reach here). */
5586 psr_field
|= (PSR_c
| PSR_f
);
5592 inst
.error
= _("selected processor does not support requested special "
5593 "purpose register");
5597 inst
.error
= _("flag for {c}psr instruction expected");
5601 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5602 value suitable for splatting into the AIF field of the instruction. */
5605 parse_cps_flags (char **str
)
5614 case '\0': case ',':
5617 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5618 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5619 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5622 inst
.error
= _("unrecognized CPS flag");
5627 if (saw_a_flag
== 0)
5629 inst
.error
= _("missing CPS flags");
5637 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5638 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5641 parse_endian_specifier (char **str
)
5646 if (strncasecmp (s
, "BE", 2))
5648 else if (strncasecmp (s
, "LE", 2))
5652 inst
.error
= _("valid endian specifiers are be or le");
5656 if (ISALNUM (s
[2]) || s
[2] == '_')
5658 inst
.error
= _("valid endian specifiers are be or le");
5663 return little_endian
;
5666 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5667 value suitable for poking into the rotate field of an sxt or sxta
5668 instruction, or FAIL on error. */
5671 parse_ror (char **str
)
5676 if (strncasecmp (s
, "ROR", 3) == 0)
5680 inst
.error
= _("missing rotation field after comma");
5684 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5689 case 0: *str
= s
; return 0x0;
5690 case 8: *str
= s
; return 0x1;
5691 case 16: *str
= s
; return 0x2;
5692 case 24: *str
= s
; return 0x3;
5695 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5700 /* Parse a conditional code (from conds[] below). The value returned is in the
5701 range 0 .. 14, or FAIL. */
5703 parse_cond (char **str
)
5706 const struct asm_cond
*c
;
5708 /* Condition codes are always 2 characters, so matching up to
5709 3 characters is sufficient. */
5714 while (ISALPHA (*q
) && n
< 3)
5716 cond
[n
] = TOLOWER (*q
);
5721 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5724 inst
.error
= _("condition required");
5732 /* Parse an option for a barrier instruction. Returns the encoding for the
5735 parse_barrier (char **str
)
5738 const struct asm_barrier_opt
*o
;
5741 while (ISALPHA (*q
))
5744 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5753 /* Parse the operands of a table branch instruction. Similar to a memory
5756 parse_tb (char **str
)
5761 if (skip_past_char (&p
, '[') == FAIL
)
5763 inst
.error
= _("'[' expected");
5767 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5769 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5772 inst
.operands
[0].reg
= reg
;
5774 if (skip_past_comma (&p
) == FAIL
)
5776 inst
.error
= _("',' expected");
5780 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5782 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5785 inst
.operands
[0].imm
= reg
;
5787 if (skip_past_comma (&p
) == SUCCESS
)
5789 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5791 if (inst
.reloc
.exp
.X_add_number
!= 1)
5793 inst
.error
= _("invalid shift");
5796 inst
.operands
[0].shifted
= 1;
5799 if (skip_past_char (&p
, ']') == FAIL
)
5801 inst
.error
= _("']' expected");
5808 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5809 information on the types the operands can take and how they are encoded.
5810 Up to four operands may be read; this function handles setting the
5811 ".present" field for each read operand itself.
5812 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5813 else returns FAIL. */
5816 parse_neon_mov (char **str
, int *which_operand
)
5818 int i
= *which_operand
, val
;
5819 enum arm_reg_type rtype
;
5821 struct neon_type_el optype
;
5823 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5825 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5826 inst
.operands
[i
].reg
= val
;
5827 inst
.operands
[i
].isscalar
= 1;
5828 inst
.operands
[i
].vectype
= optype
;
5829 inst
.operands
[i
++].present
= 1;
5831 if (skip_past_comma (&ptr
) == FAIL
)
5834 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5837 inst
.operands
[i
].reg
= val
;
5838 inst
.operands
[i
].isreg
= 1;
5839 inst
.operands
[i
].present
= 1;
5841 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5844 /* Cases 0, 1, 2, 3, 5 (D only). */
5845 if (skip_past_comma (&ptr
) == FAIL
)
5848 inst
.operands
[i
].reg
= val
;
5849 inst
.operands
[i
].isreg
= 1;
5850 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5851 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5852 inst
.operands
[i
].isvec
= 1;
5853 inst
.operands
[i
].vectype
= optype
;
5854 inst
.operands
[i
++].present
= 1;
5856 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5858 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5859 Case 13: VMOV <Sd>, <Rm> */
5860 inst
.operands
[i
].reg
= val
;
5861 inst
.operands
[i
].isreg
= 1;
5862 inst
.operands
[i
].present
= 1;
5864 if (rtype
== REG_TYPE_NQ
)
5866 first_error (_("can't use Neon quad register here"));
5869 else if (rtype
!= REG_TYPE_VFS
)
5872 if (skip_past_comma (&ptr
) == FAIL
)
5874 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5876 inst
.operands
[i
].reg
= val
;
5877 inst
.operands
[i
].isreg
= 1;
5878 inst
.operands
[i
].present
= 1;
5881 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5884 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5885 Case 1: VMOV<c><q> <Dd>, <Dm>
5886 Case 8: VMOV.F32 <Sd>, <Sm>
5887 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5889 inst
.operands
[i
].reg
= val
;
5890 inst
.operands
[i
].isreg
= 1;
5891 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5892 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5893 inst
.operands
[i
].isvec
= 1;
5894 inst
.operands
[i
].vectype
= optype
;
5895 inst
.operands
[i
].present
= 1;
5897 if (skip_past_comma (&ptr
) == SUCCESS
)
5902 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5905 inst
.operands
[i
].reg
= val
;
5906 inst
.operands
[i
].isreg
= 1;
5907 inst
.operands
[i
++].present
= 1;
5909 if (skip_past_comma (&ptr
) == FAIL
)
5912 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5915 inst
.operands
[i
].reg
= val
;
5916 inst
.operands
[i
].isreg
= 1;
5917 inst
.operands
[i
++].present
= 1;
5920 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5921 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5922 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5923 Case 10: VMOV.F32 <Sd>, #<imm>
5924 Case 11: VMOV.F64 <Dd>, #<imm> */
5925 inst
.operands
[i
].immisfloat
= 1;
5926 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5927 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5928 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5932 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5936 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5939 inst
.operands
[i
].reg
= val
;
5940 inst
.operands
[i
].isreg
= 1;
5941 inst
.operands
[i
++].present
= 1;
5943 if (skip_past_comma (&ptr
) == FAIL
)
5946 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5948 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5949 inst
.operands
[i
].reg
= val
;
5950 inst
.operands
[i
].isscalar
= 1;
5951 inst
.operands
[i
].present
= 1;
5952 inst
.operands
[i
].vectype
= optype
;
5954 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5956 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5957 inst
.operands
[i
].reg
= val
;
5958 inst
.operands
[i
].isreg
= 1;
5959 inst
.operands
[i
++].present
= 1;
5961 if (skip_past_comma (&ptr
) == FAIL
)
5964 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5967 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5971 inst
.operands
[i
].reg
= val
;
5972 inst
.operands
[i
].isreg
= 1;
5973 inst
.operands
[i
].isvec
= 1;
5974 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5975 inst
.operands
[i
].vectype
= optype
;
5976 inst
.operands
[i
].present
= 1;
5978 if (rtype
== REG_TYPE_VFS
)
5982 if (skip_past_comma (&ptr
) == FAIL
)
5984 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5987 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5990 inst
.operands
[i
].reg
= val
;
5991 inst
.operands
[i
].isreg
= 1;
5992 inst
.operands
[i
].isvec
= 1;
5993 inst
.operands
[i
].issingle
= 1;
5994 inst
.operands
[i
].vectype
= optype
;
5995 inst
.operands
[i
].present
= 1;
5998 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6002 inst
.operands
[i
].reg
= val
;
6003 inst
.operands
[i
].isreg
= 1;
6004 inst
.operands
[i
].isvec
= 1;
6005 inst
.operands
[i
].issingle
= 1;
6006 inst
.operands
[i
].vectype
= optype
;
6007 inst
.operands
[i
++].present
= 1;
6012 first_error (_("parse error"));
6016 /* Successfully parsed the operands. Update args. */
6022 first_error (_("expected comma"));
6026 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6030 /* Use this macro when the operand constraints are different
6031 for ARM and THUMB (e.g. ldrd). */
6032 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6033 ((arm_operand) | ((thumb_operand) << 16))
6035 /* Matcher codes for parse_operands. */
6036 enum operand_parse_code
6038 OP_stop
, /* end of line */
6040 OP_RR
, /* ARM register */
6041 OP_RRnpc
, /* ARM register, not r15 */
6042 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6043 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6044 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6045 optional trailing ! */
6046 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6047 OP_RCP
, /* Coprocessor number */
6048 OP_RCN
, /* Coprocessor register */
6049 OP_RF
, /* FPA register */
6050 OP_RVS
, /* VFP single precision register */
6051 OP_RVD
, /* VFP double precision register (0..15) */
6052 OP_RND
, /* Neon double precision register (0..31) */
6053 OP_RNQ
, /* Neon quad precision register */
6054 OP_RVSD
, /* VFP single or double precision register */
6055 OP_RNDQ
, /* Neon double or quad precision register */
6056 OP_RNSDQ
, /* Neon single, double or quad precision register */
6057 OP_RNSC
, /* Neon scalar D[X] */
6058 OP_RVC
, /* VFP control register */
6059 OP_RMF
, /* Maverick F register */
6060 OP_RMD
, /* Maverick D register */
6061 OP_RMFX
, /* Maverick FX register */
6062 OP_RMDX
, /* Maverick DX register */
6063 OP_RMAX
, /* Maverick AX register */
6064 OP_RMDS
, /* Maverick DSPSC register */
6065 OP_RIWR
, /* iWMMXt wR register */
6066 OP_RIWC
, /* iWMMXt wC register */
6067 OP_RIWG
, /* iWMMXt wCG register */
6068 OP_RXA
, /* XScale accumulator register */
6070 OP_REGLST
, /* ARM register list */
6071 OP_VRSLST
, /* VFP single-precision register list */
6072 OP_VRDLST
, /* VFP double-precision register list */
6073 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6074 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6075 OP_NSTRLST
, /* Neon element/structure list */
6077 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6078 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6079 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6080 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6081 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6082 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6083 OP_VMOV
, /* Neon VMOV operands. */
6084 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6085 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6086 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6088 OP_I0
, /* immediate zero */
6089 OP_I7
, /* immediate value 0 .. 7 */
6090 OP_I15
, /* 0 .. 15 */
6091 OP_I16
, /* 1 .. 16 */
6092 OP_I16z
, /* 0 .. 16 */
6093 OP_I31
, /* 0 .. 31 */
6094 OP_I31w
, /* 0 .. 31, optional trailing ! */
6095 OP_I32
, /* 1 .. 32 */
6096 OP_I32z
, /* 0 .. 32 */
6097 OP_I63
, /* 0 .. 63 */
6098 OP_I63s
, /* -64 .. 63 */
6099 OP_I64
, /* 1 .. 64 */
6100 OP_I64z
, /* 0 .. 64 */
6101 OP_I255
, /* 0 .. 255 */
6103 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6104 OP_I7b
, /* 0 .. 7 */
6105 OP_I15b
, /* 0 .. 15 */
6106 OP_I31b
, /* 0 .. 31 */
6108 OP_SH
, /* shifter operand */
6109 OP_SHG
, /* shifter operand with possible group relocation */
6110 OP_ADDR
, /* Memory address expression (any mode) */
6111 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6112 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6113 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6114 OP_EXP
, /* arbitrary expression */
6115 OP_EXPi
, /* same, with optional immediate prefix */
6116 OP_EXPr
, /* same, with optional relocation suffix */
6117 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6119 OP_CPSF
, /* CPS flags */
6120 OP_ENDI
, /* Endianness specifier */
6121 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6122 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6123 OP_COND
, /* conditional code */
6124 OP_TB
, /* Table branch. */
6126 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6128 OP_RRnpc_I0
, /* ARM register or literal 0 */
6129 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6130 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6131 OP_RF_IF
, /* FPA register or immediate */
6132 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6133 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6135 /* Optional operands. */
6136 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6137 OP_oI31b
, /* 0 .. 31 */
6138 OP_oI32b
, /* 1 .. 32 */
6139 OP_oI32z
, /* 0 .. 32 */
6140 OP_oIffffb
, /* 0 .. 65535 */
6141 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6143 OP_oRR
, /* ARM register */
6144 OP_oRRnpc
, /* ARM register, not the PC */
6145 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6146 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6147 OP_oRND
, /* Optional Neon double precision register */
6148 OP_oRNQ
, /* Optional Neon quad precision register */
6149 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6150 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6151 OP_oSHll
, /* LSL immediate */
6152 OP_oSHar
, /* ASR immediate */
6153 OP_oSHllar
, /* LSL or ASR immediate */
6154 OP_oROR
, /* ROR 0/8/16/24 */
6155 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6157 /* Some pre-defined mixed (ARM/THUMB) operands. */
6158 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6159 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6160 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6162 OP_FIRST_OPTIONAL
= OP_oI7b
6165 /* Generic instruction operand parser. This does no encoding and no
6166 semantic validation; it merely squirrels values away in the inst
6167 structure. Returns SUCCESS or FAIL depending on whether the
6168 specified grammar matched. */
6170 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6172 unsigned const int *upat
= pattern
;
6173 char *backtrack_pos
= 0;
6174 const char *backtrack_error
= 0;
6175 int i
, val
, backtrack_index
= 0;
6176 enum arm_reg_type rtype
;
6177 parse_operand_result result
;
6178 unsigned int op_parse_code
;
6180 #define po_char_or_fail(chr) \
6183 if (skip_past_char (&str, chr) == FAIL) \
6188 #define po_reg_or_fail(regtype) \
6191 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6192 & inst.operands[i].vectype); \
6195 first_error (_(reg_expected_msgs[regtype])); \
6198 inst.operands[i].reg = val; \
6199 inst.operands[i].isreg = 1; \
6200 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6201 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6202 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6203 || rtype == REG_TYPE_VFD \
6204 || rtype == REG_TYPE_NQ); \
6208 #define po_reg_or_goto(regtype, label) \
6211 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6212 & inst.operands[i].vectype); \
6216 inst.operands[i].reg = val; \
6217 inst.operands[i].isreg = 1; \
6218 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6219 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6220 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6221 || rtype == REG_TYPE_VFD \
6222 || rtype == REG_TYPE_NQ); \
6226 #define po_imm_or_fail(min, max, popt) \
6229 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6231 inst.operands[i].imm = val; \
6235 #define po_scalar_or_goto(elsz, label) \
6238 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6241 inst.operands[i].reg = val; \
6242 inst.operands[i].isscalar = 1; \
6246 #define po_misc_or_fail(expr) \
6254 #define po_misc_or_fail_no_backtrack(expr) \
6258 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6259 backtrack_pos = 0; \
6260 if (result != PARSE_OPERAND_SUCCESS) \
6265 #define po_barrier_or_imm(str) \
6268 val = parse_barrier (&str); \
6271 if (ISALPHA (*str)) \
6278 if ((inst.instruction & 0xf0) == 0x60 \
6281 /* ISB can only take SY as an option. */ \
6282 inst.error = _("invalid barrier type"); \
6289 skip_whitespace (str
);
6291 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6293 op_parse_code
= upat
[i
];
6294 if (op_parse_code
>= 1<<16)
6295 op_parse_code
= thumb
? (op_parse_code
>> 16)
6296 : (op_parse_code
& ((1<<16)-1));
6298 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6300 /* Remember where we are in case we need to backtrack. */
6301 gas_assert (!backtrack_pos
);
6302 backtrack_pos
= str
;
6303 backtrack_error
= inst
.error
;
6304 backtrack_index
= i
;
6307 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6308 po_char_or_fail (',');
6310 switch (op_parse_code
)
6318 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6319 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6320 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6321 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6322 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6323 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6325 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6327 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6329 /* Also accept generic coprocessor regs for unknown registers. */
6331 po_reg_or_fail (REG_TYPE_CN
);
6333 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6334 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6335 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6336 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6337 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6338 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6339 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6340 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6341 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6342 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6344 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6346 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6347 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6349 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6351 /* Neon scalar. Using an element size of 8 means that some invalid
6352 scalars are accepted here, so deal with those in later code. */
6353 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6357 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6360 po_imm_or_fail (0, 0, TRUE
);
6365 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6370 po_scalar_or_goto (8, try_rr
);
6373 po_reg_or_fail (REG_TYPE_RN
);
6379 po_scalar_or_goto (8, try_nsdq
);
6382 po_reg_or_fail (REG_TYPE_NSDQ
);
6388 po_scalar_or_goto (8, try_ndq
);
6391 po_reg_or_fail (REG_TYPE_NDQ
);
6397 po_scalar_or_goto (8, try_vfd
);
6400 po_reg_or_fail (REG_TYPE_VFD
);
6405 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6406 not careful then bad things might happen. */
6407 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6412 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6415 /* There's a possibility of getting a 64-bit immediate here, so
6416 we need special handling. */
6417 if (parse_big_immediate (&str
, i
) == FAIL
)
6419 inst
.error
= _("immediate value is out of range");
6427 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6430 po_imm_or_fail (0, 63, TRUE
);
6435 po_char_or_fail ('[');
6436 po_reg_or_fail (REG_TYPE_RN
);
6437 po_char_or_fail (']');
6443 po_reg_or_fail (REG_TYPE_RN
);
6444 if (skip_past_char (&str
, '!') == SUCCESS
)
6445 inst
.operands
[i
].writeback
= 1;
6449 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6450 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6451 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6452 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6453 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6454 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6455 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6456 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6457 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6458 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6459 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6460 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6462 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6464 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6465 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6467 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6468 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6469 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6470 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6472 /* Immediate variants */
6474 po_char_or_fail ('{');
6475 po_imm_or_fail (0, 255, TRUE
);
6476 po_char_or_fail ('}');
6480 /* The expression parser chokes on a trailing !, so we have
6481 to find it first and zap it. */
6484 while (*s
&& *s
!= ',')
6489 inst
.operands
[i
].writeback
= 1;
6491 po_imm_or_fail (0, 31, TRUE
);
6499 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6504 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6509 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6511 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6513 val
= parse_reloc (&str
);
6516 inst
.error
= _("unrecognized relocation suffix");
6519 else if (val
!= BFD_RELOC_UNUSED
)
6521 inst
.operands
[i
].imm
= val
;
6522 inst
.operands
[i
].hasreloc
= 1;
6527 /* Operand for MOVW or MOVT. */
6529 po_misc_or_fail (parse_half (&str
));
6532 /* Register or expression. */
6533 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6534 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6536 /* Register or immediate. */
6537 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6538 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6540 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6542 if (!is_immediate_prefix (*str
))
6545 val
= parse_fpa_immediate (&str
);
6548 /* FPA immediates are encoded as registers 8-15.
6549 parse_fpa_immediate has already applied the offset. */
6550 inst
.operands
[i
].reg
= val
;
6551 inst
.operands
[i
].isreg
= 1;
6554 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6555 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6557 /* Two kinds of register. */
6560 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6562 || (rege
->type
!= REG_TYPE_MMXWR
6563 && rege
->type
!= REG_TYPE_MMXWC
6564 && rege
->type
!= REG_TYPE_MMXWCG
))
6566 inst
.error
= _("iWMMXt data or control register expected");
6569 inst
.operands
[i
].reg
= rege
->number
;
6570 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6576 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6578 || (rege
->type
!= REG_TYPE_MMXWC
6579 && rege
->type
!= REG_TYPE_MMXWCG
))
6581 inst
.error
= _("iWMMXt control register expected");
6584 inst
.operands
[i
].reg
= rege
->number
;
6585 inst
.operands
[i
].isreg
= 1;
6590 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6591 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6592 case OP_oROR
: val
= parse_ror (&str
); break;
6593 case OP_COND
: val
= parse_cond (&str
); break;
6594 case OP_oBARRIER_I15
:
6595 po_barrier_or_imm (str
); break;
6597 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6603 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6604 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6606 inst
.error
= _("Banked registers are not available with this "
6612 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6616 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6619 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6621 if (strncasecmp (str
, "APSR_", 5) == 0)
6628 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6629 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6630 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6631 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6632 default: found
= 16;
6636 inst
.operands
[i
].isvec
= 1;
6637 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6638 inst
.operands
[i
].reg
= REG_PC
;
6645 po_misc_or_fail (parse_tb (&str
));
6648 /* Register lists. */
6650 val
= parse_reg_list (&str
);
6653 inst
.operands
[1].writeback
= 1;
6659 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6663 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6667 /* Allow Q registers too. */
6668 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6673 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6675 inst
.operands
[i
].issingle
= 1;
6680 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6685 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6686 &inst
.operands
[i
].vectype
);
6689 /* Addressing modes */
6691 po_misc_or_fail (parse_address (&str
, i
));
6695 po_misc_or_fail_no_backtrack (
6696 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6700 po_misc_or_fail_no_backtrack (
6701 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6705 po_misc_or_fail_no_backtrack (
6706 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6710 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6714 po_misc_or_fail_no_backtrack (
6715 parse_shifter_operand_group_reloc (&str
, i
));
6719 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6723 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6727 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6731 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6734 /* Various value-based sanity checks and shared operations. We
6735 do not signal immediate failures for the register constraints;
6736 this allows a syntax error to take precedence. */
6737 switch (op_parse_code
)
6745 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6746 inst
.error
= BAD_PC
;
6751 if (inst
.operands
[i
].isreg
)
6753 if (inst
.operands
[i
].reg
== REG_PC
)
6754 inst
.error
= BAD_PC
;
6755 else if (inst
.operands
[i
].reg
== REG_SP
)
6756 inst
.error
= BAD_SP
;
6761 if (inst
.operands
[i
].isreg
6762 && inst
.operands
[i
].reg
== REG_PC
6763 && (inst
.operands
[i
].writeback
|| thumb
))
6764 inst
.error
= BAD_PC
;
6773 case OP_oBARRIER_I15
:
6782 inst
.operands
[i
].imm
= val
;
6789 /* If we get here, this operand was successfully parsed. */
6790 inst
.operands
[i
].present
= 1;
6794 inst
.error
= BAD_ARGS
;
6799 /* The parse routine should already have set inst.error, but set a
6800 default here just in case. */
6802 inst
.error
= _("syntax error");
6806 /* Do not backtrack over a trailing optional argument that
6807 absorbed some text. We will only fail again, with the
6808 'garbage following instruction' error message, which is
6809 probably less helpful than the current one. */
6810 if (backtrack_index
== i
&& backtrack_pos
!= str
6811 && upat
[i
+1] == OP_stop
)
6814 inst
.error
= _("syntax error");
6818 /* Try again, skipping the optional argument at backtrack_pos. */
6819 str
= backtrack_pos
;
6820 inst
.error
= backtrack_error
;
6821 inst
.operands
[backtrack_index
].present
= 0;
6822 i
= backtrack_index
;
6826 /* Check that we have parsed all the arguments. */
6827 if (*str
!= '\0' && !inst
.error
)
6828 inst
.error
= _("garbage following instruction");
6830 return inst
.error
? FAIL
: SUCCESS
;
6833 #undef po_char_or_fail
6834 #undef po_reg_or_fail
6835 #undef po_reg_or_goto
6836 #undef po_imm_or_fail
6837 #undef po_scalar_or_fail
6838 #undef po_barrier_or_imm
6840 /* Shorthand macro for instruction encoding functions issuing errors. */
6841 #define constraint(expr, err) \
6852 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6853 instructions are unpredictable if these registers are used. This
6854 is the BadReg predicate in ARM's Thumb-2 documentation. */
6855 #define reject_bad_reg(reg) \
6857 if (reg == REG_SP || reg == REG_PC) \
6859 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6864 /* If REG is R13 (the stack pointer), warn that its use is
6866 #define warn_deprecated_sp(reg) \
6868 if (warn_on_deprecated && reg == REG_SP) \
6869 as_warn (_("use of r13 is deprecated")); \
6872 /* Functions for operand encoding. ARM, then Thumb. */
6874 #define rotate_left(v, n) (v << n | v >> (32 - n))
6876 /* If VAL can be encoded in the immediate field of an ARM instruction,
6877 return the encoded form. Otherwise, return FAIL. */
6880 encode_arm_immediate (unsigned int val
)
6884 for (i
= 0; i
< 32; i
+= 2)
6885 if ((a
= rotate_left (val
, i
)) <= 0xff)
6886 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6891 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6892 return the encoded form. Otherwise, return FAIL. */
6894 encode_thumb32_immediate (unsigned int val
)
6901 for (i
= 1; i
<= 24; i
++)
6904 if ((val
& ~(0xff << i
)) == 0)
6905 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6909 if (val
== ((a
<< 16) | a
))
6911 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6915 if (val
== ((a
<< 16) | a
))
6916 return 0x200 | (a
>> 8);
6920 /* Encode a VFP SP or DP register number into inst.instruction. */
6923 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6925 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6928 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6931 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6934 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6939 first_error (_("D register out of range for selected VFP version"));
6947 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6951 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6955 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6959 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6963 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6967 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6975 /* Encode a <shift> in an ARM-format instruction. The immediate,
6976 if any, is handled by md_apply_fix. */
6978 encode_arm_shift (int i
)
6980 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6981 inst
.instruction
|= SHIFT_ROR
<< 5;
6984 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6985 if (inst
.operands
[i
].immisreg
)
6987 inst
.instruction
|= SHIFT_BY_REG
;
6988 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6991 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6996 encode_arm_shifter_operand (int i
)
6998 if (inst
.operands
[i
].isreg
)
7000 inst
.instruction
|= inst
.operands
[i
].reg
;
7001 encode_arm_shift (i
);
7004 inst
.instruction
|= INST_IMMEDIATE
;
7007 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7009 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7011 gas_assert (inst
.operands
[i
].isreg
);
7012 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7014 if (inst
.operands
[i
].preind
)
7018 inst
.error
= _("instruction does not accept preindexed addressing");
7021 inst
.instruction
|= PRE_INDEX
;
7022 if (inst
.operands
[i
].writeback
)
7023 inst
.instruction
|= WRITE_BACK
;
7026 else if (inst
.operands
[i
].postind
)
7028 gas_assert (inst
.operands
[i
].writeback
);
7030 inst
.instruction
|= WRITE_BACK
;
7032 else /* unindexed - only for coprocessor */
7034 inst
.error
= _("instruction does not accept unindexed addressing");
7038 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7039 && (((inst
.instruction
& 0x000f0000) >> 16)
7040 == ((inst
.instruction
& 0x0000f000) >> 12)))
7041 as_warn ((inst
.instruction
& LOAD_BIT
)
7042 ? _("destination register same as write-back base")
7043 : _("source register same as write-back base"));
7046 /* inst.operands[i] was set up by parse_address. Encode it into an
7047 ARM-format mode 2 load or store instruction. If is_t is true,
7048 reject forms that cannot be used with a T instruction (i.e. not
7051 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7053 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7055 encode_arm_addr_mode_common (i
, is_t
);
7057 if (inst
.operands
[i
].immisreg
)
7059 constraint ((inst
.operands
[i
].imm
== REG_PC
7060 || (is_pc
&& inst
.operands
[i
].writeback
)),
7062 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7063 inst
.instruction
|= inst
.operands
[i
].imm
;
7064 if (!inst
.operands
[i
].negative
)
7065 inst
.instruction
|= INDEX_UP
;
7066 if (inst
.operands
[i
].shifted
)
7068 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7069 inst
.instruction
|= SHIFT_ROR
<< 5;
7072 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7073 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7077 else /* immediate offset in inst.reloc */
7079 if (is_pc
&& !inst
.reloc
.pc_rel
)
7081 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7083 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7084 cannot use PC in addressing.
7085 PC cannot be used in writeback addressing, either. */
7086 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7089 /* Use of PC in str is deprecated for ARMv7. */
7090 if (warn_on_deprecated
7092 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7093 as_warn (_("use of PC in this instruction is deprecated"));
7096 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7098 /* Prefer + for zero encoded value. */
7099 if (!inst
.operands
[i
].negative
)
7100 inst
.instruction
|= INDEX_UP
;
7101 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7106 /* inst.operands[i] was set up by parse_address. Encode it into an
7107 ARM-format mode 3 load or store instruction. Reject forms that
7108 cannot be used with such instructions. If is_t is true, reject
7109 forms that cannot be used with a T instruction (i.e. not
7112 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7114 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7116 inst
.error
= _("instruction does not accept scaled register index");
7120 encode_arm_addr_mode_common (i
, is_t
);
7122 if (inst
.operands
[i
].immisreg
)
7124 constraint ((inst
.operands
[i
].imm
== REG_PC
7125 || inst
.operands
[i
].reg
== REG_PC
),
7127 inst
.instruction
|= inst
.operands
[i
].imm
;
7128 if (!inst
.operands
[i
].negative
)
7129 inst
.instruction
|= INDEX_UP
;
7131 else /* immediate offset in inst.reloc */
7133 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7134 && inst
.operands
[i
].writeback
),
7136 inst
.instruction
|= HWOFFSET_IMM
;
7137 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7139 /* Prefer + for zero encoded value. */
7140 if (!inst
.operands
[i
].negative
)
7141 inst
.instruction
|= INDEX_UP
;
7143 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7148 /* inst.operands[i] was set up by parse_address. Encode it into an
7149 ARM-format instruction. Reject all forms which cannot be encoded
7150 into a coprocessor load/store instruction. If wb_ok is false,
7151 reject use of writeback; if unind_ok is false, reject use of
7152 unindexed addressing. If reloc_override is not 0, use it instead
7153 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7154 (in which case it is preserved). */
7157 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7159 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7161 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7163 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7165 gas_assert (!inst
.operands
[i
].writeback
);
7168 inst
.error
= _("instruction does not support unindexed addressing");
7171 inst
.instruction
|= inst
.operands
[i
].imm
;
7172 inst
.instruction
|= INDEX_UP
;
7176 if (inst
.operands
[i
].preind
)
7177 inst
.instruction
|= PRE_INDEX
;
7179 if (inst
.operands
[i
].writeback
)
7181 if (inst
.operands
[i
].reg
== REG_PC
)
7183 inst
.error
= _("pc may not be used with write-back");
7188 inst
.error
= _("instruction does not support writeback");
7191 inst
.instruction
|= WRITE_BACK
;
7195 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7196 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7197 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7198 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7201 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7203 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7206 /* Prefer + for zero encoded value. */
7207 if (!inst
.operands
[i
].negative
)
7208 inst
.instruction
|= INDEX_UP
;
7213 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7214 Determine whether it can be performed with a move instruction; if
7215 it can, convert inst.instruction to that move instruction and
7216 return TRUE; if it can't, convert inst.instruction to a literal-pool
7217 load and return FALSE. If this is not a valid thing to do in the
7218 current context, set inst.error and return TRUE.
7220 inst.operands[i] describes the destination register. */
7223 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7228 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7232 if ((inst
.instruction
& tbit
) == 0)
7234 inst
.error
= _("invalid pseudo operation");
7237 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7239 inst
.error
= _("constant expression expected");
7242 if (inst
.reloc
.exp
.X_op
== O_constant
)
7246 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7248 /* This can be done with a mov(1) instruction. */
7249 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7250 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7256 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7259 /* This can be done with a mov instruction. */
7260 inst
.instruction
&= LITERAL_MASK
;
7261 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7262 inst
.instruction
|= value
& 0xfff;
7266 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7269 /* This can be done with a mvn instruction. */
7270 inst
.instruction
&= LITERAL_MASK
;
7271 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7272 inst
.instruction
|= value
& 0xfff;
7278 if (add_to_lit_pool () == FAIL
)
7280 inst
.error
= _("literal pool insertion failed");
7283 inst
.operands
[1].reg
= REG_PC
;
7284 inst
.operands
[1].isreg
= 1;
7285 inst
.operands
[1].preind
= 1;
7286 inst
.reloc
.pc_rel
= 1;
7287 inst
.reloc
.type
= (thumb_p
7288 ? BFD_RELOC_ARM_THUMB_OFFSET
7290 ? BFD_RELOC_ARM_HWLITERAL
7291 : BFD_RELOC_ARM_LITERAL
));
7295 /* Functions for instruction encoding, sorted by sub-architecture.
7296 First some generics; their names are taken from the conventional
7297 bit positions for register arguments in ARM format instructions. */
7307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7314 inst
.instruction
|= inst
.operands
[1].reg
;
7320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7327 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7328 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7334 unsigned Rn
= inst
.operands
[2].reg
;
7335 /* Enforce restrictions on SWP instruction. */
7336 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7338 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7339 _("Rn must not overlap other operands"));
7341 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7342 if (warn_on_deprecated
7343 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7344 as_warn (_("swp{b} use is deprecated for this architecture"));
7347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7348 inst
.instruction
|= inst
.operands
[1].reg
;
7349 inst
.instruction
|= Rn
<< 16;
7355 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7356 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7357 inst
.instruction
|= inst
.operands
[2].reg
;
7363 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7364 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7365 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7366 || inst
.reloc
.exp
.X_add_number
!= 0),
7368 inst
.instruction
|= inst
.operands
[0].reg
;
7369 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7370 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7376 inst
.instruction
|= inst
.operands
[0].imm
;
7382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7383 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7386 /* ARM instructions, in alphabetical order by function name (except
7387 that wrapper functions appear immediately after the function they
7390 /* This is a pseudo-op of the form "adr rd, label" to be converted
7391 into a relative address of the form "add rd, pc, #label-.-8". */
7396 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7398 /* Frag hacking will turn this into a sub instruction if the offset turns
7399 out to be negative. */
7400 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7401 inst
.reloc
.pc_rel
= 1;
7402 inst
.reloc
.exp
.X_add_number
-= 8;
7405 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7406 into a relative address of the form:
7407 add rd, pc, #low(label-.-8)"
7408 add rd, rd, #high(label-.-8)" */
7413 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7415 /* Frag hacking will turn this into a sub instruction if the offset turns
7416 out to be negative. */
7417 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7418 inst
.reloc
.pc_rel
= 1;
7419 inst
.size
= INSN_SIZE
* 2;
7420 inst
.reloc
.exp
.X_add_number
-= 8;
7426 if (!inst
.operands
[1].present
)
7427 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7428 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7429 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7430 encode_arm_shifter_operand (2);
7436 if (inst
.operands
[0].present
)
7438 constraint ((inst
.instruction
& 0xf0) != 0x40
7439 && inst
.operands
[0].imm
> 0xf
7440 && inst
.operands
[0].imm
< 0x0,
7441 _("bad barrier type"));
7442 inst
.instruction
|= inst
.operands
[0].imm
;
7445 inst
.instruction
|= 0xf;
7451 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7452 constraint (msb
> 32, _("bit-field extends past end of register"));
7453 /* The instruction encoding stores the LSB and MSB,
7454 not the LSB and width. */
7455 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7456 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7457 inst
.instruction
|= (msb
- 1) << 16;
7465 /* #0 in second position is alternative syntax for bfc, which is
7466 the same instruction but with REG_PC in the Rm field. */
7467 if (!inst
.operands
[1].isreg
)
7468 inst
.operands
[1].reg
= REG_PC
;
7470 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7471 constraint (msb
> 32, _("bit-field extends past end of register"));
7472 /* The instruction encoding stores the LSB and MSB,
7473 not the LSB and width. */
7474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7475 inst
.instruction
|= inst
.operands
[1].reg
;
7476 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7477 inst
.instruction
|= (msb
- 1) << 16;
7483 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7484 _("bit-field extends past end of register"));
7485 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7486 inst
.instruction
|= inst
.operands
[1].reg
;
7487 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7488 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7491 /* ARM V5 breakpoint instruction (argument parse)
7492 BKPT <16 bit unsigned immediate>
7493 Instruction is not conditional.
7494 The bit pattern given in insns[] has the COND_ALWAYS condition,
7495 and it is an error if the caller tried to override that. */
7500 /* Top 12 of 16 bits to bits 19:8. */
7501 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7503 /* Bottom 4 of 16 bits to bits 3:0. */
7504 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7508 encode_branch (int default_reloc
)
7510 if (inst
.operands
[0].hasreloc
)
7512 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7513 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7514 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7515 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7516 ? BFD_RELOC_ARM_PLT32
7517 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7520 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7521 inst
.reloc
.pc_rel
= 1;
7528 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7529 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7532 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7539 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7541 if (inst
.cond
== COND_ALWAYS
)
7542 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7544 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7548 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7551 /* ARM V5 branch-link-exchange instruction (argument parse)
7552 BLX <target_addr> ie BLX(1)
7553 BLX{<condition>} <Rm> ie BLX(2)
7554 Unfortunately, there are two different opcodes for this mnemonic.
7555 So, the insns[].value is not used, and the code here zaps values
7556 into inst.instruction.
7557 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7562 if (inst
.operands
[0].isreg
)
7564 /* Arg is a register; the opcode provided by insns[] is correct.
7565 It is not illegal to do "blx pc", just useless. */
7566 if (inst
.operands
[0].reg
== REG_PC
)
7567 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7569 inst
.instruction
|= inst
.operands
[0].reg
;
7573 /* Arg is an address; this instruction cannot be executed
7574 conditionally, and the opcode must be adjusted.
7575 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7576 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7577 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7578 inst
.instruction
= 0xfa000000;
7579 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7586 bfd_boolean want_reloc
;
7588 if (inst
.operands
[0].reg
== REG_PC
)
7589 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7591 inst
.instruction
|= inst
.operands
[0].reg
;
7592 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7593 it is for ARMv4t or earlier. */
7594 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7595 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7599 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7604 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7608 /* ARM v5TEJ. Jump to Jazelle code. */
7613 if (inst
.operands
[0].reg
== REG_PC
)
7614 as_tsktsk (_("use of r15 in bxj is not really useful"));
7616 inst
.instruction
|= inst
.operands
[0].reg
;
7619 /* Co-processor data operation:
7620 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7621 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7625 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7626 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7627 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7628 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7629 inst
.instruction
|= inst
.operands
[4].reg
;
7630 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7636 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7637 encode_arm_shifter_operand (1);
7640 /* Transfer between coprocessor and ARM registers.
7641 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7646 No special properties. */
7653 Rd
= inst
.operands
[2].reg
;
7656 if (inst
.instruction
== 0xee000010
7657 || inst
.instruction
== 0xfe000010)
7659 reject_bad_reg (Rd
);
7662 constraint (Rd
== REG_SP
, BAD_SP
);
7667 if (inst
.instruction
== 0xe000010)
7668 constraint (Rd
== REG_PC
, BAD_PC
);
7672 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7673 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7674 inst
.instruction
|= Rd
<< 12;
7675 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7676 inst
.instruction
|= inst
.operands
[4].reg
;
7677 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7680 /* Transfer between coprocessor register and pair of ARM registers.
7681 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7686 Two XScale instructions are special cases of these:
7688 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7689 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7691 Result unpredictable if Rd or Rn is R15. */
7698 Rd
= inst
.operands
[2].reg
;
7699 Rn
= inst
.operands
[3].reg
;
7703 reject_bad_reg (Rd
);
7704 reject_bad_reg (Rn
);
7708 constraint (Rd
== REG_PC
, BAD_PC
);
7709 constraint (Rn
== REG_PC
, BAD_PC
);
7712 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7713 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7714 inst
.instruction
|= Rd
<< 12;
7715 inst
.instruction
|= Rn
<< 16;
7716 inst
.instruction
|= inst
.operands
[4].reg
;
7722 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7723 if (inst
.operands
[1].present
)
7725 inst
.instruction
|= CPSI_MMOD
;
7726 inst
.instruction
|= inst
.operands
[1].imm
;
7733 inst
.instruction
|= inst
.operands
[0].imm
;
7739 unsigned Rd
, Rn
, Rm
;
7741 Rd
= inst
.operands
[0].reg
;
7742 Rn
= (inst
.operands
[1].present
7743 ? inst
.operands
[1].reg
: Rd
);
7744 Rm
= inst
.operands
[2].reg
;
7746 constraint ((Rd
== REG_PC
), BAD_PC
);
7747 constraint ((Rn
== REG_PC
), BAD_PC
);
7748 constraint ((Rm
== REG_PC
), BAD_PC
);
7750 inst
.instruction
|= Rd
<< 16;
7751 inst
.instruction
|= Rn
<< 0;
7752 inst
.instruction
|= Rm
<< 8;
7758 /* There is no IT instruction in ARM mode. We
7759 process it to do the validation as if in
7760 thumb mode, just in case the code gets
7761 assembled for thumb using the unified syntax. */
7766 set_it_insn_type (IT_INSN
);
7767 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7768 now_it
.cc
= inst
.operands
[0].imm
;
7775 int base_reg
= inst
.operands
[0].reg
;
7776 int range
= inst
.operands
[1].imm
;
7778 inst
.instruction
|= base_reg
<< 16;
7779 inst
.instruction
|= range
;
7781 if (inst
.operands
[1].writeback
)
7782 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7784 if (inst
.operands
[0].writeback
)
7786 inst
.instruction
|= WRITE_BACK
;
7787 /* Check for unpredictable uses of writeback. */
7788 if (inst
.instruction
& LOAD_BIT
)
7790 /* Not allowed in LDM type 2. */
7791 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7792 && ((range
& (1 << REG_PC
)) == 0))
7793 as_warn (_("writeback of base register is UNPREDICTABLE"));
7794 /* Only allowed if base reg not in list for other types. */
7795 else if (range
& (1 << base_reg
))
7796 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7800 /* Not allowed for type 2. */
7801 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7802 as_warn (_("writeback of base register is UNPREDICTABLE"));
7803 /* Only allowed if base reg not in list, or first in list. */
7804 else if ((range
& (1 << base_reg
))
7805 && (range
& ((1 << base_reg
) - 1)))
7806 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7811 /* ARMv5TE load-consecutive (argument parse)
7820 constraint (inst
.operands
[0].reg
% 2 != 0,
7821 _("first transfer register must be even"));
7822 constraint (inst
.operands
[1].present
7823 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7824 _("can only transfer two consecutive registers"));
7825 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7826 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7828 if (!inst
.operands
[1].present
)
7829 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7831 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7832 register and the first register written; we have to diagnose
7833 overlap between the base and the second register written here. */
7835 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7836 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7837 as_warn (_("base register written back, and overlaps "
7838 "second transfer register"));
7840 if (!(inst
.instruction
& V4_STR_BIT
))
7842 /* For an index-register load, the index register must not overlap the
7843 destination (even if not write-back). */
7844 if (inst
.operands
[2].immisreg
7845 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7846 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7847 as_warn (_("index register overlaps transfer register"));
7849 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7850 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7856 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7857 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7858 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7859 || inst
.operands
[1].negative
7860 /* This can arise if the programmer has written
7862 or if they have mistakenly used a register name as the last
7865 It is very difficult to distinguish between these two cases
7866 because "rX" might actually be a label. ie the register
7867 name has been occluded by a symbol of the same name. So we
7868 just generate a general 'bad addressing mode' type error
7869 message and leave it up to the programmer to discover the
7870 true cause and fix their mistake. */
7871 || (inst
.operands
[1].reg
== REG_PC
),
7874 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7875 || inst
.reloc
.exp
.X_add_number
!= 0,
7876 _("offset must be zero in ARM encoding"));
7878 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7882 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7888 constraint (inst
.operands
[0].reg
% 2 != 0,
7889 _("even register required"));
7890 constraint (inst
.operands
[1].present
7891 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7892 _("can only load two consecutive registers"));
7893 /* If op 1 were present and equal to PC, this function wouldn't
7894 have been called in the first place. */
7895 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7898 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7905 if (!inst
.operands
[1].isreg
)
7906 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7908 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7914 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7916 if (inst
.operands
[1].preind
)
7918 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7919 || inst
.reloc
.exp
.X_add_number
!= 0,
7920 _("this instruction requires a post-indexed address"));
7922 inst
.operands
[1].preind
= 0;
7923 inst
.operands
[1].postind
= 1;
7924 inst
.operands
[1].writeback
= 1;
7926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7927 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7930 /* Halfword and signed-byte load/store operations. */
7935 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7937 if (!inst
.operands
[1].isreg
)
7938 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7940 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7946 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7948 if (inst
.operands
[1].preind
)
7950 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7951 || inst
.reloc
.exp
.X_add_number
!= 0,
7952 _("this instruction requires a post-indexed address"));
7954 inst
.operands
[1].preind
= 0;
7955 inst
.operands
[1].postind
= 1;
7956 inst
.operands
[1].writeback
= 1;
7958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7959 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7962 /* Co-processor register load/store.
7963 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7967 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7968 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7969 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7975 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7976 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7977 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7978 && !(inst
.instruction
& 0x00400000))
7979 as_tsktsk (_("Rd and Rm should be different in mla"));
7981 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7982 inst
.instruction
|= inst
.operands
[1].reg
;
7983 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7984 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7991 encode_arm_shifter_operand (1);
7994 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8001 top
= (inst
.instruction
& 0x00400000) != 0;
8002 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8003 _(":lower16: not allowed this instruction"));
8004 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8005 _(":upper16: not allowed instruction"));
8006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8007 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8009 imm
= inst
.reloc
.exp
.X_add_number
;
8010 /* The value is in two pieces: 0:11, 16:19. */
8011 inst
.instruction
|= (imm
& 0x00000fff);
8012 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8016 static void do_vfp_nsyn_opcode (const char *);
8019 do_vfp_nsyn_mrs (void)
8021 if (inst
.operands
[0].isvec
)
8023 if (inst
.operands
[1].reg
!= 1)
8024 first_error (_("operand 1 must be FPSCR"));
8025 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8026 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8027 do_vfp_nsyn_opcode ("fmstat");
8029 else if (inst
.operands
[1].isvec
)
8030 do_vfp_nsyn_opcode ("fmrx");
8038 do_vfp_nsyn_msr (void)
8040 if (inst
.operands
[0].isvec
)
8041 do_vfp_nsyn_opcode ("fmxr");
8051 unsigned Rt
= inst
.operands
[0].reg
;
8053 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8055 inst
.error
= BAD_SP
;
8059 /* APSR_ sets isvec. All other refs to PC are illegal. */
8060 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8062 inst
.error
= BAD_PC
;
8066 if (inst
.operands
[1].reg
!= 1)
8067 first_error (_("operand 1 must be FPSCR"));
8069 inst
.instruction
|= (Rt
<< 12);
8075 unsigned Rt
= inst
.operands
[1].reg
;
8078 reject_bad_reg (Rt
);
8079 else if (Rt
== REG_PC
)
8081 inst
.error
= BAD_PC
;
8085 if (inst
.operands
[0].reg
!= 1)
8086 first_error (_("operand 0 must be FPSCR"));
8088 inst
.instruction
|= (Rt
<< 12);
8096 if (do_vfp_nsyn_mrs () == SUCCESS
)
8099 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8102 if (inst
.operands
[1].isreg
)
8104 br
= inst
.operands
[1].reg
;
8105 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8106 as_bad (_("bad register for mrs"));
8110 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8111 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8113 _("'APSR', 'CPSR' or 'SPSR' expected"));
8114 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8117 inst
.instruction
|= br
;
8120 /* Two possible forms:
8121 "{C|S}PSR_<field>, Rm",
8122 "{C|S}PSR_f, #expression". */
8127 if (do_vfp_nsyn_msr () == SUCCESS
)
8130 inst
.instruction
|= inst
.operands
[0].imm
;
8131 if (inst
.operands
[1].isreg
)
8132 inst
.instruction
|= inst
.operands
[1].reg
;
8135 inst
.instruction
|= INST_IMMEDIATE
;
8136 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8137 inst
.reloc
.pc_rel
= 0;
8144 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8146 if (!inst
.operands
[2].present
)
8147 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8149 inst
.instruction
|= inst
.operands
[1].reg
;
8150 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8152 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8153 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8154 as_tsktsk (_("Rd and Rm should be different in mul"));
8157 /* Long Multiply Parser
8158 UMULL RdLo, RdHi, Rm, Rs
8159 SMULL RdLo, RdHi, Rm, Rs
8160 UMLAL RdLo, RdHi, Rm, Rs
8161 SMLAL RdLo, RdHi, Rm, Rs. */
8166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8168 inst
.instruction
|= inst
.operands
[2].reg
;
8169 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8171 /* rdhi and rdlo must be different. */
8172 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8173 as_tsktsk (_("rdhi and rdlo must be different"));
8175 /* rdhi, rdlo and rm must all be different before armv6. */
8176 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8177 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8178 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8179 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8185 if (inst
.operands
[0].present
8186 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8188 /* Architectural NOP hints are CPSR sets with no bits selected. */
8189 inst
.instruction
&= 0xf0000000;
8190 inst
.instruction
|= 0x0320f000;
8191 if (inst
.operands
[0].present
)
8192 inst
.instruction
|= inst
.operands
[0].imm
;
8196 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8197 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8198 Condition defaults to COND_ALWAYS.
8199 Error if Rd, Rn or Rm are R15. */
8204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8205 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8206 inst
.instruction
|= inst
.operands
[2].reg
;
8207 if (inst
.operands
[3].present
)
8208 encode_arm_shift (3);
8211 /* ARM V6 PKHTB (Argument Parse). */
8216 if (!inst
.operands
[3].present
)
8218 /* If the shift specifier is omitted, turn the instruction
8219 into pkhbt rd, rm, rn. */
8220 inst
.instruction
&= 0xfff00010;
8221 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8222 inst
.instruction
|= inst
.operands
[1].reg
;
8223 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8228 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8229 inst
.instruction
|= inst
.operands
[2].reg
;
8230 encode_arm_shift (3);
8234 /* ARMv5TE: Preload-Cache
8235 MP Extensions: Preload for write
8239 Syntactically, like LDR with B=1, W=0, L=1. */
8244 constraint (!inst
.operands
[0].isreg
,
8245 _("'[' expected after PLD mnemonic"));
8246 constraint (inst
.operands
[0].postind
,
8247 _("post-indexed expression used in preload instruction"));
8248 constraint (inst
.operands
[0].writeback
,
8249 _("writeback used in preload instruction"));
8250 constraint (!inst
.operands
[0].preind
,
8251 _("unindexed addressing used in preload instruction"));
8252 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8255 /* ARMv7: PLI <addr_mode> */
8259 constraint (!inst
.operands
[0].isreg
,
8260 _("'[' expected after PLI mnemonic"));
8261 constraint (inst
.operands
[0].postind
,
8262 _("post-indexed expression used in preload instruction"));
8263 constraint (inst
.operands
[0].writeback
,
8264 _("writeback used in preload instruction"));
8265 constraint (!inst
.operands
[0].preind
,
8266 _("unindexed addressing used in preload instruction"));
8267 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8268 inst
.instruction
&= ~PRE_INDEX
;
8274 inst
.operands
[1] = inst
.operands
[0];
8275 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8276 inst
.operands
[0].isreg
= 1;
8277 inst
.operands
[0].writeback
= 1;
8278 inst
.operands
[0].reg
= REG_SP
;
8282 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8283 word at the specified address and the following word
8285 Unconditionally executed.
8286 Error if Rn is R15. */
8291 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8292 if (inst
.operands
[0].writeback
)
8293 inst
.instruction
|= WRITE_BACK
;
8296 /* ARM V6 ssat (argument parse). */
8301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8302 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8303 inst
.instruction
|= inst
.operands
[2].reg
;
8305 if (inst
.operands
[3].present
)
8306 encode_arm_shift (3);
8309 /* ARM V6 usat (argument parse). */
8314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8315 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8316 inst
.instruction
|= inst
.operands
[2].reg
;
8318 if (inst
.operands
[3].present
)
8319 encode_arm_shift (3);
8322 /* ARM V6 ssat16 (argument parse). */
8327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8328 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8329 inst
.instruction
|= inst
.operands
[2].reg
;
8335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8336 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8337 inst
.instruction
|= inst
.operands
[2].reg
;
8340 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8341 preserving the other bits.
8343 setend <endian_specifier>, where <endian_specifier> is either
8349 if (inst
.operands
[0].imm
)
8350 inst
.instruction
|= 0x200;
8356 unsigned int Rm
= (inst
.operands
[1].present
8357 ? inst
.operands
[1].reg
8358 : inst
.operands
[0].reg
);
8360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8361 inst
.instruction
|= Rm
;
8362 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8364 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8365 inst
.instruction
|= SHIFT_BY_REG
;
8366 /* PR 12854: Error on extraneous shifts. */
8367 constraint (inst
.operands
[2].shifted
,
8368 _("extraneous shift as part of operand to shift insn"));
8371 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8377 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8378 inst
.reloc
.pc_rel
= 0;
8384 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8385 inst
.reloc
.pc_rel
= 0;
8391 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8392 inst
.reloc
.pc_rel
= 0;
8395 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8396 SMLAxy{cond} Rd,Rm,Rs,Rn
8397 SMLAWy{cond} Rd,Rm,Rs,Rn
8398 Error if any register is R15. */
8403 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8404 inst
.instruction
|= inst
.operands
[1].reg
;
8405 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8406 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8409 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8410 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8411 Error if any register is R15.
8412 Warning if Rdlo == Rdhi. */
8417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8418 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8419 inst
.instruction
|= inst
.operands
[2].reg
;
8420 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8422 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8423 as_tsktsk (_("rdhi and rdlo must be different"));
8426 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8427 SMULxy{cond} Rd,Rm,Rs
8428 Error if any register is R15. */
8433 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8434 inst
.instruction
|= inst
.operands
[1].reg
;
8435 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8438 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8439 the same for both ARM and Thumb-2. */
8446 if (inst
.operands
[0].present
)
8448 reg
= inst
.operands
[0].reg
;
8449 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8454 inst
.instruction
|= reg
<< 16;
8455 inst
.instruction
|= inst
.operands
[1].imm
;
8456 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8457 inst
.instruction
|= WRITE_BACK
;
8460 /* ARM V6 strex (argument parse). */
8465 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8466 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8467 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8468 || inst
.operands
[2].negative
8469 /* See comment in do_ldrex(). */
8470 || (inst
.operands
[2].reg
== REG_PC
),
8473 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8474 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8476 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8477 || inst
.reloc
.exp
.X_add_number
!= 0,
8478 _("offset must be zero in ARM encoding"));
8480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8481 inst
.instruction
|= inst
.operands
[1].reg
;
8482 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8483 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8489 constraint (inst
.operands
[1].reg
% 2 != 0,
8490 _("even register required"));
8491 constraint (inst
.operands
[2].present
8492 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8493 _("can only store two consecutive registers"));
8494 /* If op 2 were present and equal to PC, this function wouldn't
8495 have been called in the first place. */
8496 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8498 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8499 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8500 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8504 inst
.instruction
|= inst
.operands
[1].reg
;
8505 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8508 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8509 extends it to 32-bits, and adds the result to a value in another
8510 register. You can specify a rotation by 0, 8, 16, or 24 bits
8511 before extracting the 16-bit value.
8512 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8513 Condition defaults to COND_ALWAYS.
8514 Error if any register uses R15. */
8519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8520 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8521 inst
.instruction
|= inst
.operands
[2].reg
;
8522 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8527 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8528 Condition defaults to COND_ALWAYS.
8529 Error if any register uses R15. */
8534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8535 inst
.instruction
|= inst
.operands
[1].reg
;
8536 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8539 /* VFP instructions. In a logical order: SP variant first, monad
8540 before dyad, arithmetic then move then load/store. */
8543 do_vfp_sp_monadic (void)
8545 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8546 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8550 do_vfp_sp_dyadic (void)
8552 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8553 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8554 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8558 do_vfp_sp_compare_z (void)
8560 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8564 do_vfp_dp_sp_cvt (void)
8566 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8567 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8571 do_vfp_sp_dp_cvt (void)
8573 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8574 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8578 do_vfp_reg_from_sp (void)
8580 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8581 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8585 do_vfp_reg2_from_sp2 (void)
8587 constraint (inst
.operands
[2].imm
!= 2,
8588 _("only two consecutive VFP SP registers allowed here"));
8589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8590 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8591 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8595 do_vfp_sp_from_reg (void)
8597 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8598 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8602 do_vfp_sp2_from_reg2 (void)
8604 constraint (inst
.operands
[0].imm
!= 2,
8605 _("only two consecutive VFP SP registers allowed here"));
8606 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8607 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8608 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8612 do_vfp_sp_ldst (void)
8614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8615 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8619 do_vfp_dp_ldst (void)
8621 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8622 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8627 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8629 if (inst
.operands
[0].writeback
)
8630 inst
.instruction
|= WRITE_BACK
;
8632 constraint (ldstm_type
!= VFP_LDSTMIA
,
8633 _("this addressing mode requires base-register writeback"));
8634 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8635 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8636 inst
.instruction
|= inst
.operands
[1].imm
;
8640 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8644 if (inst
.operands
[0].writeback
)
8645 inst
.instruction
|= WRITE_BACK
;
8647 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8648 _("this addressing mode requires base-register writeback"));
8650 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8651 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8653 count
= inst
.operands
[1].imm
<< 1;
8654 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8657 inst
.instruction
|= count
;
8661 do_vfp_sp_ldstmia (void)
8663 vfp_sp_ldstm (VFP_LDSTMIA
);
8667 do_vfp_sp_ldstmdb (void)
8669 vfp_sp_ldstm (VFP_LDSTMDB
);
8673 do_vfp_dp_ldstmia (void)
8675 vfp_dp_ldstm (VFP_LDSTMIA
);
8679 do_vfp_dp_ldstmdb (void)
8681 vfp_dp_ldstm (VFP_LDSTMDB
);
8685 do_vfp_xp_ldstmia (void)
8687 vfp_dp_ldstm (VFP_LDSTMIAX
);
8691 do_vfp_xp_ldstmdb (void)
8693 vfp_dp_ldstm (VFP_LDSTMDBX
);
8697 do_vfp_dp_rd_rm (void)
8699 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8700 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8704 do_vfp_dp_rn_rd (void)
8706 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8707 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8711 do_vfp_dp_rd_rn (void)
8713 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8714 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8718 do_vfp_dp_rd_rn_rm (void)
8720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8721 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8722 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8728 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8732 do_vfp_dp_rm_rd_rn (void)
8734 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8735 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8736 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8739 /* VFPv3 instructions. */
8741 do_vfp_sp_const (void)
8743 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8744 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8745 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8749 do_vfp_dp_const (void)
8751 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8752 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8753 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8757 vfp_conv (int srcsize
)
8759 int immbits
= srcsize
- inst
.operands
[1].imm
;
8761 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
8763 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8764 i.e. immbits must be in range 0 - 16. */
8765 inst
.error
= _("immediate value out of range, expected range [0, 16]");
8768 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
8770 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8771 i.e. immbits must be in range 0 - 31. */
8772 inst
.error
= _("immediate value out of range, expected range [1, 32]");
8776 inst
.instruction
|= (immbits
& 1) << 5;
8777 inst
.instruction
|= (immbits
>> 1);
8781 do_vfp_sp_conv_16 (void)
8783 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8788 do_vfp_dp_conv_16 (void)
8790 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8795 do_vfp_sp_conv_32 (void)
8797 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8802 do_vfp_dp_conv_32 (void)
8804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8808 /* FPA instructions. Also in a logical order. */
8813 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8814 inst
.instruction
|= inst
.operands
[1].reg
;
8818 do_fpa_ldmstm (void)
8820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8821 switch (inst
.operands
[1].imm
)
8823 case 1: inst
.instruction
|= CP_T_X
; break;
8824 case 2: inst
.instruction
|= CP_T_Y
; break;
8825 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8830 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8832 /* The instruction specified "ea" or "fd", so we can only accept
8833 [Rn]{!}. The instruction does not really support stacking or
8834 unstacking, so we have to emulate these by setting appropriate
8835 bits and offsets. */
8836 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8837 || inst
.reloc
.exp
.X_add_number
!= 0,
8838 _("this instruction does not support indexing"));
8840 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8841 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8843 if (!(inst
.instruction
& INDEX_UP
))
8844 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8846 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8848 inst
.operands
[2].preind
= 0;
8849 inst
.operands
[2].postind
= 1;
8853 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8856 /* iWMMXt instructions: strictly in alphabetical order. */
8859 do_iwmmxt_tandorc (void)
8861 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8865 do_iwmmxt_textrc (void)
8867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8868 inst
.instruction
|= inst
.operands
[1].imm
;
8872 do_iwmmxt_textrm (void)
8874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8876 inst
.instruction
|= inst
.operands
[2].imm
;
8880 do_iwmmxt_tinsr (void)
8882 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8883 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8884 inst
.instruction
|= inst
.operands
[2].imm
;
8888 do_iwmmxt_tmia (void)
8890 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8891 inst
.instruction
|= inst
.operands
[1].reg
;
8892 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8896 do_iwmmxt_waligni (void)
8898 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8899 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8900 inst
.instruction
|= inst
.operands
[2].reg
;
8901 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8905 do_iwmmxt_wmerge (void)
8907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8908 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8909 inst
.instruction
|= inst
.operands
[2].reg
;
8910 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8914 do_iwmmxt_wmov (void)
8916 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8919 inst
.instruction
|= inst
.operands
[1].reg
;
8923 do_iwmmxt_wldstbh (void)
8926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8928 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8930 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8931 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8935 do_iwmmxt_wldstw (void)
8937 /* RIWR_RIWC clears .isreg for a control register. */
8938 if (!inst
.operands
[0].isreg
)
8940 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8941 inst
.instruction
|= 0xf0000000;
8944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8945 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8949 do_iwmmxt_wldstd (void)
8951 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8952 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8953 && inst
.operands
[1].immisreg
)
8955 inst
.instruction
&= ~0x1a000ff;
8956 inst
.instruction
|= (0xf << 28);
8957 if (inst
.operands
[1].preind
)
8958 inst
.instruction
|= PRE_INDEX
;
8959 if (!inst
.operands
[1].negative
)
8960 inst
.instruction
|= INDEX_UP
;
8961 if (inst
.operands
[1].writeback
)
8962 inst
.instruction
|= WRITE_BACK
;
8963 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8964 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8965 inst
.instruction
|= inst
.operands
[1].imm
;
8968 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8972 do_iwmmxt_wshufh (void)
8974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8975 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8976 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8977 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8981 do_iwmmxt_wzero (void)
8983 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8984 inst
.instruction
|= inst
.operands
[0].reg
;
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8990 do_iwmmxt_wrwrwr_or_imm5 (void)
8992 if (inst
.operands
[2].isreg
)
8995 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8996 _("immediate operand requires iWMMXt2"));
8998 if (inst
.operands
[2].imm
== 0)
9000 switch ((inst
.instruction
>> 20) & 0xf)
9006 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9007 inst
.operands
[2].imm
= 16;
9008 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9014 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9015 inst
.operands
[2].imm
= 32;
9016 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9023 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9025 wrn
= (inst
.instruction
>> 16) & 0xf;
9026 inst
.instruction
&= 0xff0fff0f;
9027 inst
.instruction
|= wrn
;
9028 /* Bail out here; the instruction is now assembled. */
9033 /* Map 32 -> 0, etc. */
9034 inst
.operands
[2].imm
&= 0x1f;
9035 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9039 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9040 operations first, then control, shift, and load/store. */
9042 /* Insns like "foo X,Y,Z". */
9045 do_mav_triple (void)
9047 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9048 inst
.instruction
|= inst
.operands
[1].reg
;
9049 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9052 /* Insns like "foo W,X,Y,Z".
9053 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9058 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9059 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9060 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9061 inst
.instruction
|= inst
.operands
[3].reg
;
9064 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9068 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9071 /* Maverick shift immediate instructions.
9072 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9073 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9078 int imm
= inst
.operands
[2].imm
;
9080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9083 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9084 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9085 Bit 4 should be 0. */
9086 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9088 inst
.instruction
|= imm
;
9091 /* XScale instructions. Also sorted arithmetic before move. */
9093 /* Xscale multiply-accumulate (argument parse)
9096 MIAxycc acc0,Rm,Rs. */
9101 inst
.instruction
|= inst
.operands
[1].reg
;
9102 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9105 /* Xscale move-accumulator-register (argument parse)
9107 MARcc acc0,RdLo,RdHi. */
9112 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9113 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9116 /* Xscale move-register-accumulator (argument parse)
9118 MRAcc RdLo,RdHi,acc0. */
9123 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9124 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9125 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9128 /* Encoding functions relevant only to Thumb. */
9130 /* inst.operands[i] is a shifted-register operand; encode
9131 it into inst.instruction in the format used by Thumb32. */
9134 encode_thumb32_shifted_operand (int i
)
9136 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9137 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9139 constraint (inst
.operands
[i
].immisreg
,
9140 _("shift by register not allowed in thumb mode"));
9141 inst
.instruction
|= inst
.operands
[i
].reg
;
9142 if (shift
== SHIFT_RRX
)
9143 inst
.instruction
|= SHIFT_ROR
<< 4;
9146 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9147 _("expression too complex"));
9149 constraint (value
> 32
9150 || (value
== 32 && (shift
== SHIFT_LSL
9151 || shift
== SHIFT_ROR
)),
9152 _("shift expression is too large"));
9156 else if (value
== 32)
9159 inst
.instruction
|= shift
<< 4;
9160 inst
.instruction
|= (value
& 0x1c) << 10;
9161 inst
.instruction
|= (value
& 0x03) << 6;
9166 /* inst.operands[i] was set up by parse_address. Encode it into a
9167 Thumb32 format load or store instruction. Reject forms that cannot
9168 be used with such instructions. If is_t is true, reject forms that
9169 cannot be used with a T instruction; if is_d is true, reject forms
9170 that cannot be used with a D instruction. If it is a store insn,
9174 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9176 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9178 constraint (!inst
.operands
[i
].isreg
,
9179 _("Instruction does not support =N addresses"));
9181 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9182 if (inst
.operands
[i
].immisreg
)
9184 constraint (is_pc
, BAD_PC_ADDRESSING
);
9185 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9186 constraint (inst
.operands
[i
].negative
,
9187 _("Thumb does not support negative register indexing"));
9188 constraint (inst
.operands
[i
].postind
,
9189 _("Thumb does not support register post-indexing"));
9190 constraint (inst
.operands
[i
].writeback
,
9191 _("Thumb does not support register indexing with writeback"));
9192 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9193 _("Thumb supports only LSL in shifted register indexing"));
9195 inst
.instruction
|= inst
.operands
[i
].imm
;
9196 if (inst
.operands
[i
].shifted
)
9198 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9199 _("expression too complex"));
9200 constraint (inst
.reloc
.exp
.X_add_number
< 0
9201 || inst
.reloc
.exp
.X_add_number
> 3,
9202 _("shift out of range"));
9203 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9205 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9207 else if (inst
.operands
[i
].preind
)
9209 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9210 constraint (is_t
&& inst
.operands
[i
].writeback
,
9211 _("cannot use writeback with this instruction"));
9212 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9213 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9217 inst
.instruction
|= 0x01000000;
9218 if (inst
.operands
[i
].writeback
)
9219 inst
.instruction
|= 0x00200000;
9223 inst
.instruction
|= 0x00000c00;
9224 if (inst
.operands
[i
].writeback
)
9225 inst
.instruction
|= 0x00000100;
9227 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9229 else if (inst
.operands
[i
].postind
)
9231 gas_assert (inst
.operands
[i
].writeback
);
9232 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9233 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9236 inst
.instruction
|= 0x00200000;
9238 inst
.instruction
|= 0x00000900;
9239 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9241 else /* unindexed - only for coprocessor */
9242 inst
.error
= _("instruction does not accept unindexed addressing");
9245 /* Table of Thumb instructions which exist in both 16- and 32-bit
9246 encodings (the latter only in post-V6T2 cores). The index is the
9247 value used in the insns table below. When there is more than one
9248 possible 16-bit encoding for the instruction, this table always
9250 Also contains several pseudo-instructions used during relaxation. */
9251 #define T16_32_TAB \
9252 X(_adc, 4140, eb400000), \
9253 X(_adcs, 4140, eb500000), \
9254 X(_add, 1c00, eb000000), \
9255 X(_adds, 1c00, eb100000), \
9256 X(_addi, 0000, f1000000), \
9257 X(_addis, 0000, f1100000), \
9258 X(_add_pc,000f, f20f0000), \
9259 X(_add_sp,000d, f10d0000), \
9260 X(_adr, 000f, f20f0000), \
9261 X(_and, 4000, ea000000), \
9262 X(_ands, 4000, ea100000), \
9263 X(_asr, 1000, fa40f000), \
9264 X(_asrs, 1000, fa50f000), \
9265 X(_b, e000, f000b000), \
9266 X(_bcond, d000, f0008000), \
9267 X(_bic, 4380, ea200000), \
9268 X(_bics, 4380, ea300000), \
9269 X(_cmn, 42c0, eb100f00), \
9270 X(_cmp, 2800, ebb00f00), \
9271 X(_cpsie, b660, f3af8400), \
9272 X(_cpsid, b670, f3af8600), \
9273 X(_cpy, 4600, ea4f0000), \
9274 X(_dec_sp,80dd, f1ad0d00), \
9275 X(_eor, 4040, ea800000), \
9276 X(_eors, 4040, ea900000), \
9277 X(_inc_sp,00dd, f10d0d00), \
9278 X(_ldmia, c800, e8900000), \
9279 X(_ldr, 6800, f8500000), \
9280 X(_ldrb, 7800, f8100000), \
9281 X(_ldrh, 8800, f8300000), \
9282 X(_ldrsb, 5600, f9100000), \
9283 X(_ldrsh, 5e00, f9300000), \
9284 X(_ldr_pc,4800, f85f0000), \
9285 X(_ldr_pc2,4800, f85f0000), \
9286 X(_ldr_sp,9800, f85d0000), \
9287 X(_lsl, 0000, fa00f000), \
9288 X(_lsls, 0000, fa10f000), \
9289 X(_lsr, 0800, fa20f000), \
9290 X(_lsrs, 0800, fa30f000), \
9291 X(_mov, 2000, ea4f0000), \
9292 X(_movs, 2000, ea5f0000), \
9293 X(_mul, 4340, fb00f000), \
9294 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9295 X(_mvn, 43c0, ea6f0000), \
9296 X(_mvns, 43c0, ea7f0000), \
9297 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9298 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9299 X(_orr, 4300, ea400000), \
9300 X(_orrs, 4300, ea500000), \
9301 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9302 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9303 X(_rev, ba00, fa90f080), \
9304 X(_rev16, ba40, fa90f090), \
9305 X(_revsh, bac0, fa90f0b0), \
9306 X(_ror, 41c0, fa60f000), \
9307 X(_rors, 41c0, fa70f000), \
9308 X(_sbc, 4180, eb600000), \
9309 X(_sbcs, 4180, eb700000), \
9310 X(_stmia, c000, e8800000), \
9311 X(_str, 6000, f8400000), \
9312 X(_strb, 7000, f8000000), \
9313 X(_strh, 8000, f8200000), \
9314 X(_str_sp,9000, f84d0000), \
9315 X(_sub, 1e00, eba00000), \
9316 X(_subs, 1e00, ebb00000), \
9317 X(_subi, 8000, f1a00000), \
9318 X(_subis, 8000, f1b00000), \
9319 X(_sxtb, b240, fa4ff080), \
9320 X(_sxth, b200, fa0ff080), \
9321 X(_tst, 4200, ea100f00), \
9322 X(_uxtb, b2c0, fa5ff080), \
9323 X(_uxth, b280, fa1ff080), \
9324 X(_nop, bf00, f3af8000), \
9325 X(_yield, bf10, f3af8001), \
9326 X(_wfe, bf20, f3af8002), \
9327 X(_wfi, bf30, f3af8003), \
9328 X(_sev, bf40, f3af8004),
9330 /* To catch errors in encoding functions, the codes are all offset by
9331 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9332 as 16-bit instructions. */
9333 #define X(a,b,c) T_MNEM##a
9334 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9337 #define X(a,b,c) 0x##b
9338 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9339 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9342 #define X(a,b,c) 0x##c
9343 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9344 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9345 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9349 /* Thumb instruction encoders, in alphabetical order. */
9354 do_t_add_sub_w (void)
9358 Rd
= inst
.operands
[0].reg
;
9359 Rn
= inst
.operands
[1].reg
;
9361 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9362 is the SP-{plus,minus}-immediate form of the instruction. */
9364 constraint (Rd
== REG_PC
, BAD_PC
);
9366 reject_bad_reg (Rd
);
9368 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9369 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9372 /* Parse an add or subtract instruction. We get here with inst.instruction
9373 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9380 Rd
= inst
.operands
[0].reg
;
9381 Rs
= (inst
.operands
[1].present
9382 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9383 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9386 set_it_insn_type_last ();
9394 flags
= (inst
.instruction
== T_MNEM_adds
9395 || inst
.instruction
== T_MNEM_subs
);
9397 narrow
= !in_it_block ();
9399 narrow
= in_it_block ();
9400 if (!inst
.operands
[2].isreg
)
9404 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9406 add
= (inst
.instruction
== T_MNEM_add
9407 || inst
.instruction
== T_MNEM_adds
);
9409 if (inst
.size_req
!= 4)
9411 /* Attempt to use a narrow opcode, with relaxation if
9413 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9414 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9415 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9416 opcode
= T_MNEM_add_sp
;
9417 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9418 opcode
= T_MNEM_add_pc
;
9419 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9422 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9424 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9428 inst
.instruction
= THUMB_OP16(opcode
);
9429 inst
.instruction
|= (Rd
<< 4) | Rs
;
9430 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9431 if (inst
.size_req
!= 2)
9432 inst
.relax
= opcode
;
9435 constraint (inst
.size_req
== 2, BAD_HIREG
);
9437 if (inst
.size_req
== 4
9438 || (inst
.size_req
!= 2 && !opcode
))
9442 constraint (add
, BAD_PC
);
9443 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9444 _("only SUBS PC, LR, #const allowed"));
9445 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9446 _("expression too complex"));
9447 constraint (inst
.reloc
.exp
.X_add_number
< 0
9448 || inst
.reloc
.exp
.X_add_number
> 0xff,
9449 _("immediate value out of range"));
9450 inst
.instruction
= T2_SUBS_PC_LR
9451 | inst
.reloc
.exp
.X_add_number
;
9452 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9455 else if (Rs
== REG_PC
)
9457 /* Always use addw/subw. */
9458 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9459 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9463 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9464 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9467 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9469 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9471 inst
.instruction
|= Rd
<< 8;
9472 inst
.instruction
|= Rs
<< 16;
9477 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9478 unsigned int shift
= inst
.operands
[2].shift_kind
;
9480 Rn
= inst
.operands
[2].reg
;
9481 /* See if we can do this with a 16-bit instruction. */
9482 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9484 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9489 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9490 || inst
.instruction
== T_MNEM_add
)
9493 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9497 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9499 /* Thumb-1 cores (except v6-M) require at least one high
9500 register in a narrow non flag setting add. */
9501 if (Rd
> 7 || Rn
> 7
9502 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9503 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9510 inst
.instruction
= T_OPCODE_ADD_HI
;
9511 inst
.instruction
|= (Rd
& 8) << 4;
9512 inst
.instruction
|= (Rd
& 7);
9513 inst
.instruction
|= Rn
<< 3;
9519 constraint (Rd
== REG_PC
, BAD_PC
);
9520 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9521 constraint (Rs
== REG_PC
, BAD_PC
);
9522 reject_bad_reg (Rn
);
9524 /* If we get here, it can't be done in 16 bits. */
9525 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9526 _("shift must be constant"));
9527 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9528 inst
.instruction
|= Rd
<< 8;
9529 inst
.instruction
|= Rs
<< 16;
9530 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9531 _("shift value over 3 not allowed in thumb mode"));
9532 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9533 _("only LSL shift allowed in thumb mode"));
9534 encode_thumb32_shifted_operand (2);
9539 constraint (inst
.instruction
== T_MNEM_adds
9540 || inst
.instruction
== T_MNEM_subs
,
9543 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9545 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9546 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9549 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9551 inst
.instruction
|= (Rd
<< 4) | Rs
;
9552 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9556 Rn
= inst
.operands
[2].reg
;
9557 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9559 /* We now have Rd, Rs, and Rn set to registers. */
9560 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9562 /* Can't do this for SUB. */
9563 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9564 inst
.instruction
= T_OPCODE_ADD_HI
;
9565 inst
.instruction
|= (Rd
& 8) << 4;
9566 inst
.instruction
|= (Rd
& 7);
9568 inst
.instruction
|= Rn
<< 3;
9570 inst
.instruction
|= Rs
<< 3;
9572 constraint (1, _("dest must overlap one source register"));
9576 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9577 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9578 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9588 Rd
= inst
.operands
[0].reg
;
9589 reject_bad_reg (Rd
);
9591 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9593 /* Defer to section relaxation. */
9594 inst
.relax
= inst
.instruction
;
9595 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9596 inst
.instruction
|= Rd
<< 4;
9598 else if (unified_syntax
&& inst
.size_req
!= 2)
9600 /* Generate a 32-bit opcode. */
9601 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9602 inst
.instruction
|= Rd
<< 8;
9603 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9604 inst
.reloc
.pc_rel
= 1;
9608 /* Generate a 16-bit opcode. */
9609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9610 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9611 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9612 inst
.reloc
.pc_rel
= 1;
9614 inst
.instruction
|= Rd
<< 4;
9618 /* Arithmetic instructions for which there is just one 16-bit
9619 instruction encoding, and it allows only two low registers.
9620 For maximal compatibility with ARM syntax, we allow three register
9621 operands even when Thumb-32 instructions are not available, as long
9622 as the first two are identical. For instance, both "sbc r0,r1" and
9623 "sbc r0,r0,r1" are allowed. */
9629 Rd
= inst
.operands
[0].reg
;
9630 Rs
= (inst
.operands
[1].present
9631 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9632 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9633 Rn
= inst
.operands
[2].reg
;
9635 reject_bad_reg (Rd
);
9636 reject_bad_reg (Rs
);
9637 if (inst
.operands
[2].isreg
)
9638 reject_bad_reg (Rn
);
9642 if (!inst
.operands
[2].isreg
)
9644 /* For an immediate, we always generate a 32-bit opcode;
9645 section relaxation will shrink it later if possible. */
9646 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9647 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9648 inst
.instruction
|= Rd
<< 8;
9649 inst
.instruction
|= Rs
<< 16;
9650 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9656 /* See if we can do this with a 16-bit instruction. */
9657 if (THUMB_SETS_FLAGS (inst
.instruction
))
9658 narrow
= !in_it_block ();
9660 narrow
= in_it_block ();
9662 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9664 if (inst
.operands
[2].shifted
)
9666 if (inst
.size_req
== 4)
9672 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9673 inst
.instruction
|= Rd
;
9674 inst
.instruction
|= Rn
<< 3;
9678 /* If we get here, it can't be done in 16 bits. */
9679 constraint (inst
.operands
[2].shifted
9680 && inst
.operands
[2].immisreg
,
9681 _("shift must be constant"));
9682 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9683 inst
.instruction
|= Rd
<< 8;
9684 inst
.instruction
|= Rs
<< 16;
9685 encode_thumb32_shifted_operand (2);
9690 /* On its face this is a lie - the instruction does set the
9691 flags. However, the only supported mnemonic in this mode
9693 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9695 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9696 _("unshifted register required"));
9697 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9698 constraint (Rd
!= Rs
,
9699 _("dest and source1 must be the same register"));
9701 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9702 inst
.instruction
|= Rd
;
9703 inst
.instruction
|= Rn
<< 3;
9707 /* Similarly, but for instructions where the arithmetic operation is
9708 commutative, so we can allow either of them to be different from
9709 the destination operand in a 16-bit instruction. For instance, all
9710 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9717 Rd
= inst
.operands
[0].reg
;
9718 Rs
= (inst
.operands
[1].present
9719 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9720 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9721 Rn
= inst
.operands
[2].reg
;
9723 reject_bad_reg (Rd
);
9724 reject_bad_reg (Rs
);
9725 if (inst
.operands
[2].isreg
)
9726 reject_bad_reg (Rn
);
9730 if (!inst
.operands
[2].isreg
)
9732 /* For an immediate, we always generate a 32-bit opcode;
9733 section relaxation will shrink it later if possible. */
9734 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9735 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9736 inst
.instruction
|= Rd
<< 8;
9737 inst
.instruction
|= Rs
<< 16;
9738 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9744 /* See if we can do this with a 16-bit instruction. */
9745 if (THUMB_SETS_FLAGS (inst
.instruction
))
9746 narrow
= !in_it_block ();
9748 narrow
= in_it_block ();
9750 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9752 if (inst
.operands
[2].shifted
)
9754 if (inst
.size_req
== 4)
9761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9762 inst
.instruction
|= Rd
;
9763 inst
.instruction
|= Rn
<< 3;
9768 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9769 inst
.instruction
|= Rd
;
9770 inst
.instruction
|= Rs
<< 3;
9775 /* If we get here, it can't be done in 16 bits. */
9776 constraint (inst
.operands
[2].shifted
9777 && inst
.operands
[2].immisreg
,
9778 _("shift must be constant"));
9779 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9780 inst
.instruction
|= Rd
<< 8;
9781 inst
.instruction
|= Rs
<< 16;
9782 encode_thumb32_shifted_operand (2);
9787 /* On its face this is a lie - the instruction does set the
9788 flags. However, the only supported mnemonic in this mode
9790 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9792 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9793 _("unshifted register required"));
9794 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9797 inst
.instruction
|= Rd
;
9800 inst
.instruction
|= Rn
<< 3;
9802 inst
.instruction
|= Rs
<< 3;
9804 constraint (1, _("dest must overlap one source register"));
9811 if (inst
.operands
[0].present
)
9813 constraint ((inst
.instruction
& 0xf0) != 0x40
9814 && inst
.operands
[0].imm
> 0xf
9815 && inst
.operands
[0].imm
< 0x0,
9816 _("bad barrier type"));
9817 inst
.instruction
|= inst
.operands
[0].imm
;
9820 inst
.instruction
|= 0xf;
9827 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9828 constraint (msb
> 32, _("bit-field extends past end of register"));
9829 /* The instruction encoding stores the LSB and MSB,
9830 not the LSB and width. */
9831 Rd
= inst
.operands
[0].reg
;
9832 reject_bad_reg (Rd
);
9833 inst
.instruction
|= Rd
<< 8;
9834 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9835 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9836 inst
.instruction
|= msb
- 1;
9845 Rd
= inst
.operands
[0].reg
;
9846 reject_bad_reg (Rd
);
9848 /* #0 in second position is alternative syntax for bfc, which is
9849 the same instruction but with REG_PC in the Rm field. */
9850 if (!inst
.operands
[1].isreg
)
9854 Rn
= inst
.operands
[1].reg
;
9855 reject_bad_reg (Rn
);
9858 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9859 constraint (msb
> 32, _("bit-field extends past end of register"));
9860 /* The instruction encoding stores the LSB and MSB,
9861 not the LSB and width. */
9862 inst
.instruction
|= Rd
<< 8;
9863 inst
.instruction
|= Rn
<< 16;
9864 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9865 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9866 inst
.instruction
|= msb
- 1;
9874 Rd
= inst
.operands
[0].reg
;
9875 Rn
= inst
.operands
[1].reg
;
9877 reject_bad_reg (Rd
);
9878 reject_bad_reg (Rn
);
9880 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9881 _("bit-field extends past end of register"));
9882 inst
.instruction
|= Rd
<< 8;
9883 inst
.instruction
|= Rn
<< 16;
9884 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9885 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9886 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9889 /* ARM V5 Thumb BLX (argument parse)
9890 BLX <target_addr> which is BLX(1)
9891 BLX <Rm> which is BLX(2)
9892 Unfortunately, there are two different opcodes for this mnemonic.
9893 So, the insns[].value is not used, and the code here zaps values
9894 into inst.instruction.
9896 ??? How to take advantage of the additional two bits of displacement
9897 available in Thumb32 mode? Need new relocation? */
9902 set_it_insn_type_last ();
9904 if (inst
.operands
[0].isreg
)
9906 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9907 /* We have a register, so this is BLX(2). */
9908 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9912 /* No register. This must be BLX(1). */
9913 inst
.instruction
= 0xf000e800;
9914 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9926 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9930 /* Conditional branches inside IT blocks are encoded as unconditional
9937 if (cond
!= COND_ALWAYS
)
9938 opcode
= T_MNEM_bcond
;
9940 opcode
= inst
.instruction
;
9943 && (inst
.size_req
== 4
9944 || (inst
.size_req
!= 2
9945 && (inst
.operands
[0].hasreloc
9946 || inst
.reloc
.exp
.X_op
== O_constant
))))
9948 inst
.instruction
= THUMB_OP32(opcode
);
9949 if (cond
== COND_ALWAYS
)
9950 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9953 gas_assert (cond
!= 0xF);
9954 inst
.instruction
|= cond
<< 22;
9955 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9960 inst
.instruction
= THUMB_OP16(opcode
);
9961 if (cond
== COND_ALWAYS
)
9962 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9965 inst
.instruction
|= cond
<< 8;
9966 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9968 /* Allow section relaxation. */
9969 if (unified_syntax
&& inst
.size_req
!= 2)
9970 inst
.relax
= opcode
;
9972 inst
.reloc
.type
= reloc
;
9973 inst
.reloc
.pc_rel
= 1;
9979 constraint (inst
.cond
!= COND_ALWAYS
,
9980 _("instruction is always unconditional"));
9981 if (inst
.operands
[0].present
)
9983 constraint (inst
.operands
[0].imm
> 255,
9984 _("immediate value out of range"));
9985 inst
.instruction
|= inst
.operands
[0].imm
;
9986 set_it_insn_type (NEUTRAL_IT_INSN
);
9991 do_t_branch23 (void)
9993 set_it_insn_type_last ();
9994 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9996 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9997 this file. We used to simply ignore the PLT reloc type here --
9998 the branch encoding is now needed to deal with TLSCALL relocs.
9999 So if we see a PLT reloc now, put it back to how it used to be to
10000 keep the preexisting behaviour. */
10001 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10002 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10004 #if defined(OBJ_COFF)
10005 /* If the destination of the branch is a defined symbol which does not have
10006 the THUMB_FUNC attribute, then we must be calling a function which has
10007 the (interfacearm) attribute. We look for the Thumb entry point to that
10008 function and change the branch to refer to that function instead. */
10009 if ( inst
.reloc
.exp
.X_op
== O_symbol
10010 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10011 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10012 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10013 inst
.reloc
.exp
.X_add_symbol
=
10014 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10021 set_it_insn_type_last ();
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10023 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10024 should cause the alignment to be checked once it is known. This is
10025 because BX PC only works if the instruction is word aligned. */
10033 set_it_insn_type_last ();
10034 Rm
= inst
.operands
[0].reg
;
10035 reject_bad_reg (Rm
);
10036 inst
.instruction
|= Rm
<< 16;
10045 Rd
= inst
.operands
[0].reg
;
10046 Rm
= inst
.operands
[1].reg
;
10048 reject_bad_reg (Rd
);
10049 reject_bad_reg (Rm
);
10051 inst
.instruction
|= Rd
<< 8;
10052 inst
.instruction
|= Rm
<< 16;
10053 inst
.instruction
|= Rm
;
10059 set_it_insn_type (OUTSIDE_IT_INSN
);
10060 inst
.instruction
|= inst
.operands
[0].imm
;
10066 set_it_insn_type (OUTSIDE_IT_INSN
);
10068 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10069 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10071 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10072 inst
.instruction
= 0xf3af8000;
10073 inst
.instruction
|= imod
<< 9;
10074 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10075 if (inst
.operands
[1].present
)
10076 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10080 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10081 && (inst
.operands
[0].imm
& 4),
10082 _("selected processor does not support 'A' form "
10083 "of this instruction"));
10084 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10085 _("Thumb does not support the 2-argument "
10086 "form of this instruction"));
10087 inst
.instruction
|= inst
.operands
[0].imm
;
10091 /* THUMB CPY instruction (argument parse). */
10096 if (inst
.size_req
== 4)
10098 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10099 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10100 inst
.instruction
|= inst
.operands
[1].reg
;
10104 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10105 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10106 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10113 set_it_insn_type (OUTSIDE_IT_INSN
);
10114 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10115 inst
.instruction
|= inst
.operands
[0].reg
;
10116 inst
.reloc
.pc_rel
= 1;
10117 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10123 inst
.instruction
|= inst
.operands
[0].imm
;
10129 unsigned Rd
, Rn
, Rm
;
10131 Rd
= inst
.operands
[0].reg
;
10132 Rn
= (inst
.operands
[1].present
10133 ? inst
.operands
[1].reg
: Rd
);
10134 Rm
= inst
.operands
[2].reg
;
10136 reject_bad_reg (Rd
);
10137 reject_bad_reg (Rn
);
10138 reject_bad_reg (Rm
);
10140 inst
.instruction
|= Rd
<< 8;
10141 inst
.instruction
|= Rn
<< 16;
10142 inst
.instruction
|= Rm
;
10148 if (unified_syntax
&& inst
.size_req
== 4)
10149 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10151 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10157 unsigned int cond
= inst
.operands
[0].imm
;
10159 set_it_insn_type (IT_INSN
);
10160 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10163 /* If the condition is a negative condition, invert the mask. */
10164 if ((cond
& 0x1) == 0x0)
10166 unsigned int mask
= inst
.instruction
& 0x000f;
10168 if ((mask
& 0x7) == 0)
10169 /* no conversion needed */;
10170 else if ((mask
& 0x3) == 0)
10172 else if ((mask
& 0x1) == 0)
10177 inst
.instruction
&= 0xfff0;
10178 inst
.instruction
|= mask
;
10181 inst
.instruction
|= cond
<< 4;
10184 /* Helper function used for both push/pop and ldm/stm. */
10186 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10190 load
= (inst
.instruction
& (1 << 20)) != 0;
10192 if (mask
& (1 << 13))
10193 inst
.error
= _("SP not allowed in register list");
10195 if ((mask
& (1 << base
)) != 0
10197 inst
.error
= _("having the base register in the register list when "
10198 "using write back is UNPREDICTABLE");
10202 if (mask
& (1 << 15))
10204 if (mask
& (1 << 14))
10205 inst
.error
= _("LR and PC should not both be in register list");
10207 set_it_insn_type_last ();
10212 if (mask
& (1 << 15))
10213 inst
.error
= _("PC not allowed in register list");
10216 if ((mask
& (mask
- 1)) == 0)
10218 /* Single register transfers implemented as str/ldr. */
10221 if (inst
.instruction
& (1 << 23))
10222 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10224 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10228 if (inst
.instruction
& (1 << 23))
10229 inst
.instruction
= 0x00800000; /* ia -> [base] */
10231 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10234 inst
.instruction
|= 0xf8400000;
10236 inst
.instruction
|= 0x00100000;
10238 mask
= ffs (mask
) - 1;
10241 else if (writeback
)
10242 inst
.instruction
|= WRITE_BACK
;
10244 inst
.instruction
|= mask
;
10245 inst
.instruction
|= base
<< 16;
10251 /* This really doesn't seem worth it. */
10252 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10253 _("expression too complex"));
10254 constraint (inst
.operands
[1].writeback
,
10255 _("Thumb load/store multiple does not support {reglist}^"));
10257 if (unified_syntax
)
10259 bfd_boolean narrow
;
10263 /* See if we can use a 16-bit instruction. */
10264 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10265 && inst
.size_req
!= 4
10266 && !(inst
.operands
[1].imm
& ~0xff))
10268 mask
= 1 << inst
.operands
[0].reg
;
10270 if (inst
.operands
[0].reg
<= 7)
10272 if (inst
.instruction
== T_MNEM_stmia
10273 ? inst
.operands
[0].writeback
10274 : (inst
.operands
[0].writeback
10275 == !(inst
.operands
[1].imm
& mask
)))
10277 if (inst
.instruction
== T_MNEM_stmia
10278 && (inst
.operands
[1].imm
& mask
)
10279 && (inst
.operands
[1].imm
& (mask
- 1)))
10280 as_warn (_("value stored for r%d is UNKNOWN"),
10281 inst
.operands
[0].reg
);
10283 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10284 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10285 inst
.instruction
|= inst
.operands
[1].imm
;
10288 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10290 /* This means 1 register in reg list one of 3 situations:
10291 1. Instruction is stmia, but without writeback.
10292 2. lmdia without writeback, but with Rn not in
10294 3. ldmia with writeback, but with Rn in reglist.
10295 Case 3 is UNPREDICTABLE behaviour, so we handle
10296 case 1 and 2 which can be converted into a 16-bit
10297 str or ldr. The SP cases are handled below. */
10298 unsigned long opcode
;
10299 /* First, record an error for Case 3. */
10300 if (inst
.operands
[1].imm
& mask
10301 && inst
.operands
[0].writeback
)
10303 _("having the base register in the register list when "
10304 "using write back is UNPREDICTABLE");
10306 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10308 inst
.instruction
= THUMB_OP16 (opcode
);
10309 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10310 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10314 else if (inst
.operands
[0] .reg
== REG_SP
)
10316 if (inst
.operands
[0].writeback
)
10319 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10320 ? T_MNEM_push
: T_MNEM_pop
);
10321 inst
.instruction
|= inst
.operands
[1].imm
;
10324 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10327 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10328 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10329 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10337 if (inst
.instruction
< 0xffff)
10338 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10340 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10341 inst
.operands
[0].writeback
);
10346 constraint (inst
.operands
[0].reg
> 7
10347 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10348 constraint (inst
.instruction
!= T_MNEM_ldmia
10349 && inst
.instruction
!= T_MNEM_stmia
,
10350 _("Thumb-2 instruction only valid in unified syntax"));
10351 if (inst
.instruction
== T_MNEM_stmia
)
10353 if (!inst
.operands
[0].writeback
)
10354 as_warn (_("this instruction will write back the base register"));
10355 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10356 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10357 as_warn (_("value stored for r%d is UNKNOWN"),
10358 inst
.operands
[0].reg
);
10362 if (!inst
.operands
[0].writeback
10363 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10364 as_warn (_("this instruction will write back the base register"));
10365 else if (inst
.operands
[0].writeback
10366 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10367 as_warn (_("this instruction will not write back the base register"));
10370 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10371 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10372 inst
.instruction
|= inst
.operands
[1].imm
;
10379 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10380 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10381 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10382 || inst
.operands
[1].negative
,
10385 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10388 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10389 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10395 if (!inst
.operands
[1].present
)
10397 constraint (inst
.operands
[0].reg
== REG_LR
,
10398 _("r14 not allowed as first register "
10399 "when second register is omitted"));
10400 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10402 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10406 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10407 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10413 unsigned long opcode
;
10416 if (inst
.operands
[0].isreg
10417 && !inst
.operands
[0].preind
10418 && inst
.operands
[0].reg
== REG_PC
)
10419 set_it_insn_type_last ();
10421 opcode
= inst
.instruction
;
10422 if (unified_syntax
)
10424 if (!inst
.operands
[1].isreg
)
10426 if (opcode
<= 0xffff)
10427 inst
.instruction
= THUMB_OP32 (opcode
);
10428 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10431 if (inst
.operands
[1].isreg
10432 && !inst
.operands
[1].writeback
10433 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10434 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10435 && opcode
<= 0xffff
10436 && inst
.size_req
!= 4)
10438 /* Insn may have a 16-bit form. */
10439 Rn
= inst
.operands
[1].reg
;
10440 if (inst
.operands
[1].immisreg
)
10442 inst
.instruction
= THUMB_OP16 (opcode
);
10444 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10446 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10447 reject_bad_reg (inst
.operands
[1].imm
);
10449 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10450 && opcode
!= T_MNEM_ldrsb
)
10451 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10452 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10459 if (inst
.reloc
.pc_rel
)
10460 opcode
= T_MNEM_ldr_pc2
;
10462 opcode
= T_MNEM_ldr_pc
;
10466 if (opcode
== T_MNEM_ldr
)
10467 opcode
= T_MNEM_ldr_sp
;
10469 opcode
= T_MNEM_str_sp
;
10471 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10475 inst
.instruction
= inst
.operands
[0].reg
;
10476 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10478 inst
.instruction
|= THUMB_OP16 (opcode
);
10479 if (inst
.size_req
== 2)
10480 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10482 inst
.relax
= opcode
;
10486 /* Definitely a 32-bit variant. */
10488 /* Warning for Erratum 752419. */
10489 if (opcode
== T_MNEM_ldr
10490 && inst
.operands
[0].reg
== REG_SP
10491 && inst
.operands
[1].writeback
== 1
10492 && !inst
.operands
[1].immisreg
)
10494 if (no_cpu_selected ()
10495 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10496 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10497 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10498 as_warn (_("This instruction may be unpredictable "
10499 "if executed on M-profile cores "
10500 "with interrupts enabled."));
10503 /* Do some validations regarding addressing modes. */
10504 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10505 && opcode
!= T_MNEM_str
)
10506 reject_bad_reg (inst
.operands
[1].imm
);
10508 inst
.instruction
= THUMB_OP32 (opcode
);
10509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10510 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10514 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10516 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10518 /* Only [Rn,Rm] is acceptable. */
10519 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10520 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10521 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10522 || inst
.operands
[1].negative
,
10523 _("Thumb does not support this addressing mode"));
10524 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10528 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10529 if (!inst
.operands
[1].isreg
)
10530 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10533 constraint (!inst
.operands
[1].preind
10534 || inst
.operands
[1].shifted
10535 || inst
.operands
[1].writeback
,
10536 _("Thumb does not support this addressing mode"));
10537 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10539 constraint (inst
.instruction
& 0x0600,
10540 _("byte or halfword not valid for base register"));
10541 constraint (inst
.operands
[1].reg
== REG_PC
10542 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10543 _("r15 based store not allowed"));
10544 constraint (inst
.operands
[1].immisreg
,
10545 _("invalid base register for register offset"));
10547 if (inst
.operands
[1].reg
== REG_PC
)
10548 inst
.instruction
= T_OPCODE_LDR_PC
;
10549 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10550 inst
.instruction
= T_OPCODE_LDR_SP
;
10552 inst
.instruction
= T_OPCODE_STR_SP
;
10554 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10555 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10559 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10560 if (!inst
.operands
[1].immisreg
)
10562 /* Immediate offset. */
10563 inst
.instruction
|= inst
.operands
[0].reg
;
10564 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10565 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10569 /* Register offset. */
10570 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10571 constraint (inst
.operands
[1].negative
,
10572 _("Thumb does not support this addressing mode"));
10575 switch (inst
.instruction
)
10577 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10578 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10579 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10580 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10581 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10582 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10583 case 0x5600 /* ldrsb */:
10584 case 0x5e00 /* ldrsh */: break;
10588 inst
.instruction
|= inst
.operands
[0].reg
;
10589 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10590 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10596 if (!inst
.operands
[1].present
)
10598 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10599 constraint (inst
.operands
[0].reg
== REG_LR
,
10600 _("r14 not allowed here"));
10602 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10603 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10604 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10611 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10617 unsigned Rd
, Rn
, Rm
, Ra
;
10619 Rd
= inst
.operands
[0].reg
;
10620 Rn
= inst
.operands
[1].reg
;
10621 Rm
= inst
.operands
[2].reg
;
10622 Ra
= inst
.operands
[3].reg
;
10624 reject_bad_reg (Rd
);
10625 reject_bad_reg (Rn
);
10626 reject_bad_reg (Rm
);
10627 reject_bad_reg (Ra
);
10629 inst
.instruction
|= Rd
<< 8;
10630 inst
.instruction
|= Rn
<< 16;
10631 inst
.instruction
|= Rm
;
10632 inst
.instruction
|= Ra
<< 12;
10638 unsigned RdLo
, RdHi
, Rn
, Rm
;
10640 RdLo
= inst
.operands
[0].reg
;
10641 RdHi
= inst
.operands
[1].reg
;
10642 Rn
= inst
.operands
[2].reg
;
10643 Rm
= inst
.operands
[3].reg
;
10645 reject_bad_reg (RdLo
);
10646 reject_bad_reg (RdHi
);
10647 reject_bad_reg (Rn
);
10648 reject_bad_reg (Rm
);
10650 inst
.instruction
|= RdLo
<< 12;
10651 inst
.instruction
|= RdHi
<< 8;
10652 inst
.instruction
|= Rn
<< 16;
10653 inst
.instruction
|= Rm
;
10657 do_t_mov_cmp (void)
10661 Rn
= inst
.operands
[0].reg
;
10662 Rm
= inst
.operands
[1].reg
;
10665 set_it_insn_type_last ();
10667 if (unified_syntax
)
10669 int r0off
= (inst
.instruction
== T_MNEM_mov
10670 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10671 unsigned long opcode
;
10672 bfd_boolean narrow
;
10673 bfd_boolean low_regs
;
10675 low_regs
= (Rn
<= 7 && Rm
<= 7);
10676 opcode
= inst
.instruction
;
10677 if (in_it_block ())
10678 narrow
= opcode
!= T_MNEM_movs
;
10680 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10681 if (inst
.size_req
== 4
10682 || inst
.operands
[1].shifted
)
10685 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10686 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10687 && !inst
.operands
[1].shifted
10691 inst
.instruction
= T2_SUBS_PC_LR
;
10695 if (opcode
== T_MNEM_cmp
)
10697 constraint (Rn
== REG_PC
, BAD_PC
);
10700 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10702 warn_deprecated_sp (Rm
);
10703 /* R15 was documented as a valid choice for Rm in ARMv6,
10704 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10705 tools reject R15, so we do too. */
10706 constraint (Rm
== REG_PC
, BAD_PC
);
10709 reject_bad_reg (Rm
);
10711 else if (opcode
== T_MNEM_mov
10712 || opcode
== T_MNEM_movs
)
10714 if (inst
.operands
[1].isreg
)
10716 if (opcode
== T_MNEM_movs
)
10718 reject_bad_reg (Rn
);
10719 reject_bad_reg (Rm
);
10723 /* This is mov.n. */
10724 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10725 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10727 as_warn (_("Use of r%u as a source register is "
10728 "deprecated when r%u is the destination "
10729 "register."), Rm
, Rn
);
10734 /* This is mov.w. */
10735 constraint (Rn
== REG_PC
, BAD_PC
);
10736 constraint (Rm
== REG_PC
, BAD_PC
);
10737 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10741 reject_bad_reg (Rn
);
10744 if (!inst
.operands
[1].isreg
)
10746 /* Immediate operand. */
10747 if (!in_it_block () && opcode
== T_MNEM_mov
)
10749 if (low_regs
&& narrow
)
10751 inst
.instruction
= THUMB_OP16 (opcode
);
10752 inst
.instruction
|= Rn
<< 8;
10753 if (inst
.size_req
== 2)
10754 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10756 inst
.relax
= opcode
;
10760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10761 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10762 inst
.instruction
|= Rn
<< r0off
;
10763 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10766 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10767 && (inst
.instruction
== T_MNEM_mov
10768 || inst
.instruction
== T_MNEM_movs
))
10770 /* Register shifts are encoded as separate shift instructions. */
10771 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10773 if (in_it_block ())
10778 if (inst
.size_req
== 4)
10781 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10787 switch (inst
.operands
[1].shift_kind
)
10790 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10793 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10796 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10799 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10805 inst
.instruction
= opcode
;
10808 inst
.instruction
|= Rn
;
10809 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10814 inst
.instruction
|= CONDS_BIT
;
10816 inst
.instruction
|= Rn
<< 8;
10817 inst
.instruction
|= Rm
<< 16;
10818 inst
.instruction
|= inst
.operands
[1].imm
;
10823 /* Some mov with immediate shift have narrow variants.
10824 Register shifts are handled above. */
10825 if (low_regs
&& inst
.operands
[1].shifted
10826 && (inst
.instruction
== T_MNEM_mov
10827 || inst
.instruction
== T_MNEM_movs
))
10829 if (in_it_block ())
10830 narrow
= (inst
.instruction
== T_MNEM_mov
);
10832 narrow
= (inst
.instruction
== T_MNEM_movs
);
10837 switch (inst
.operands
[1].shift_kind
)
10839 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10840 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10841 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10842 default: narrow
= FALSE
; break;
10848 inst
.instruction
|= Rn
;
10849 inst
.instruction
|= Rm
<< 3;
10850 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10854 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10855 inst
.instruction
|= Rn
<< r0off
;
10856 encode_thumb32_shifted_operand (1);
10860 switch (inst
.instruction
)
10863 inst
.instruction
= T_OPCODE_MOV_HR
;
10864 inst
.instruction
|= (Rn
& 0x8) << 4;
10865 inst
.instruction
|= (Rn
& 0x7);
10866 inst
.instruction
|= Rm
<< 3;
10870 /* We know we have low registers at this point.
10871 Generate LSLS Rd, Rs, #0. */
10872 inst
.instruction
= T_OPCODE_LSL_I
;
10873 inst
.instruction
|= Rn
;
10874 inst
.instruction
|= Rm
<< 3;
10880 inst
.instruction
= T_OPCODE_CMP_LR
;
10881 inst
.instruction
|= Rn
;
10882 inst
.instruction
|= Rm
<< 3;
10886 inst
.instruction
= T_OPCODE_CMP_HR
;
10887 inst
.instruction
|= (Rn
& 0x8) << 4;
10888 inst
.instruction
|= (Rn
& 0x7);
10889 inst
.instruction
|= Rm
<< 3;
10896 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10898 /* PR 10443: Do not silently ignore shifted operands. */
10899 constraint (inst
.operands
[1].shifted
,
10900 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10902 if (inst
.operands
[1].isreg
)
10904 if (Rn
< 8 && Rm
< 8)
10906 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10907 since a MOV instruction produces unpredictable results. */
10908 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10909 inst
.instruction
= T_OPCODE_ADD_I3
;
10911 inst
.instruction
= T_OPCODE_CMP_LR
;
10913 inst
.instruction
|= Rn
;
10914 inst
.instruction
|= Rm
<< 3;
10918 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10919 inst
.instruction
= T_OPCODE_MOV_HR
;
10921 inst
.instruction
= T_OPCODE_CMP_HR
;
10927 constraint (Rn
> 7,
10928 _("only lo regs allowed with immediate"));
10929 inst
.instruction
|= Rn
<< 8;
10930 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10941 top
= (inst
.instruction
& 0x00800000) != 0;
10942 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10944 constraint (top
, _(":lower16: not allowed this instruction"));
10945 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10947 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10949 constraint (!top
, _(":upper16: not allowed this instruction"));
10950 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10953 Rd
= inst
.operands
[0].reg
;
10954 reject_bad_reg (Rd
);
10956 inst
.instruction
|= Rd
<< 8;
10957 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10959 imm
= inst
.reloc
.exp
.X_add_number
;
10960 inst
.instruction
|= (imm
& 0xf000) << 4;
10961 inst
.instruction
|= (imm
& 0x0800) << 15;
10962 inst
.instruction
|= (imm
& 0x0700) << 4;
10963 inst
.instruction
|= (imm
& 0x00ff);
10968 do_t_mvn_tst (void)
10972 Rn
= inst
.operands
[0].reg
;
10973 Rm
= inst
.operands
[1].reg
;
10975 if (inst
.instruction
== T_MNEM_cmp
10976 || inst
.instruction
== T_MNEM_cmn
)
10977 constraint (Rn
== REG_PC
, BAD_PC
);
10979 reject_bad_reg (Rn
);
10980 reject_bad_reg (Rm
);
10982 if (unified_syntax
)
10984 int r0off
= (inst
.instruction
== T_MNEM_mvn
10985 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10986 bfd_boolean narrow
;
10988 if (inst
.size_req
== 4
10989 || inst
.instruction
> 0xffff
10990 || inst
.operands
[1].shifted
10991 || Rn
> 7 || Rm
> 7)
10993 else if (inst
.instruction
== T_MNEM_cmn
)
10995 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10996 narrow
= !in_it_block ();
10998 narrow
= in_it_block ();
11000 if (!inst
.operands
[1].isreg
)
11002 /* For an immediate, we always generate a 32-bit opcode;
11003 section relaxation will shrink it later if possible. */
11004 if (inst
.instruction
< 0xffff)
11005 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11006 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11007 inst
.instruction
|= Rn
<< r0off
;
11008 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11012 /* See if we can do this with a 16-bit instruction. */
11015 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11016 inst
.instruction
|= Rn
;
11017 inst
.instruction
|= Rm
<< 3;
11021 constraint (inst
.operands
[1].shifted
11022 && inst
.operands
[1].immisreg
,
11023 _("shift must be constant"));
11024 if (inst
.instruction
< 0xffff)
11025 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11026 inst
.instruction
|= Rn
<< r0off
;
11027 encode_thumb32_shifted_operand (1);
11033 constraint (inst
.instruction
> 0xffff
11034 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11035 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11036 _("unshifted register required"));
11037 constraint (Rn
> 7 || Rm
> 7,
11040 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11041 inst
.instruction
|= Rn
;
11042 inst
.instruction
|= Rm
<< 3;
11051 if (do_vfp_nsyn_mrs () == SUCCESS
)
11054 Rd
= inst
.operands
[0].reg
;
11055 reject_bad_reg (Rd
);
11056 inst
.instruction
|= Rd
<< 8;
11058 if (inst
.operands
[1].isreg
)
11060 unsigned br
= inst
.operands
[1].reg
;
11061 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11062 as_bad (_("bad register for mrs"));
11064 inst
.instruction
|= br
& (0xf << 16);
11065 inst
.instruction
|= (br
& 0x300) >> 4;
11066 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11070 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11072 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11073 constraint (flags
!= 0, _("selected processor does not support "
11074 "requested special purpose register"));
11076 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11078 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11079 _("'APSR', 'CPSR' or 'SPSR' expected"));
11081 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11082 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11083 inst
.instruction
|= 0xf0000;
11093 if (do_vfp_nsyn_msr () == SUCCESS
)
11096 constraint (!inst
.operands
[1].isreg
,
11097 _("Thumb encoding does not support an immediate here"));
11099 if (inst
.operands
[0].isreg
)
11100 flags
= (int)(inst
.operands
[0].reg
);
11102 flags
= inst
.operands
[0].imm
;
11104 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11106 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11108 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11109 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11110 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11112 _("selected processor does not support requested special "
11113 "purpose register"));
11116 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11117 "requested special purpose register"));
11119 Rn
= inst
.operands
[1].reg
;
11120 reject_bad_reg (Rn
);
11122 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11123 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11124 inst
.instruction
|= (flags
& 0x300) >> 4;
11125 inst
.instruction
|= (flags
& 0xff);
11126 inst
.instruction
|= Rn
<< 16;
11132 bfd_boolean narrow
;
11133 unsigned Rd
, Rn
, Rm
;
11135 if (!inst
.operands
[2].present
)
11136 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11138 Rd
= inst
.operands
[0].reg
;
11139 Rn
= inst
.operands
[1].reg
;
11140 Rm
= inst
.operands
[2].reg
;
11142 if (unified_syntax
)
11144 if (inst
.size_req
== 4
11150 else if (inst
.instruction
== T_MNEM_muls
)
11151 narrow
= !in_it_block ();
11153 narrow
= in_it_block ();
11157 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11158 constraint (Rn
> 7 || Rm
> 7,
11165 /* 16-bit MULS/Conditional MUL. */
11166 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11167 inst
.instruction
|= Rd
;
11170 inst
.instruction
|= Rm
<< 3;
11172 inst
.instruction
|= Rn
<< 3;
11174 constraint (1, _("dest must overlap one source register"));
11178 constraint (inst
.instruction
!= T_MNEM_mul
,
11179 _("Thumb-2 MUL must not set flags"));
11181 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11182 inst
.instruction
|= Rd
<< 8;
11183 inst
.instruction
|= Rn
<< 16;
11184 inst
.instruction
|= Rm
<< 0;
11186 reject_bad_reg (Rd
);
11187 reject_bad_reg (Rn
);
11188 reject_bad_reg (Rm
);
11195 unsigned RdLo
, RdHi
, Rn
, Rm
;
11197 RdLo
= inst
.operands
[0].reg
;
11198 RdHi
= inst
.operands
[1].reg
;
11199 Rn
= inst
.operands
[2].reg
;
11200 Rm
= inst
.operands
[3].reg
;
11202 reject_bad_reg (RdLo
);
11203 reject_bad_reg (RdHi
);
11204 reject_bad_reg (Rn
);
11205 reject_bad_reg (Rm
);
11207 inst
.instruction
|= RdLo
<< 12;
11208 inst
.instruction
|= RdHi
<< 8;
11209 inst
.instruction
|= Rn
<< 16;
11210 inst
.instruction
|= Rm
;
11213 as_tsktsk (_("rdhi and rdlo must be different"));
11219 set_it_insn_type (NEUTRAL_IT_INSN
);
11221 if (unified_syntax
)
11223 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11225 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11226 inst
.instruction
|= inst
.operands
[0].imm
;
11230 /* PR9722: Check for Thumb2 availability before
11231 generating a thumb2 nop instruction. */
11232 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11234 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11235 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11238 inst
.instruction
= 0x46c0;
11243 constraint (inst
.operands
[0].present
,
11244 _("Thumb does not support NOP with hints"));
11245 inst
.instruction
= 0x46c0;
11252 if (unified_syntax
)
11254 bfd_boolean narrow
;
11256 if (THUMB_SETS_FLAGS (inst
.instruction
))
11257 narrow
= !in_it_block ();
11259 narrow
= in_it_block ();
11260 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11262 if (inst
.size_req
== 4)
11267 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11268 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11273 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11274 inst
.instruction
|= inst
.operands
[0].reg
;
11275 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11280 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11282 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11284 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11285 inst
.instruction
|= inst
.operands
[0].reg
;
11286 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11295 Rd
= inst
.operands
[0].reg
;
11296 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11298 reject_bad_reg (Rd
);
11299 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11300 reject_bad_reg (Rn
);
11302 inst
.instruction
|= Rd
<< 8;
11303 inst
.instruction
|= Rn
<< 16;
11305 if (!inst
.operands
[2].isreg
)
11307 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11308 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11314 Rm
= inst
.operands
[2].reg
;
11315 reject_bad_reg (Rm
);
11317 constraint (inst
.operands
[2].shifted
11318 && inst
.operands
[2].immisreg
,
11319 _("shift must be constant"));
11320 encode_thumb32_shifted_operand (2);
11327 unsigned Rd
, Rn
, Rm
;
11329 Rd
= inst
.operands
[0].reg
;
11330 Rn
= inst
.operands
[1].reg
;
11331 Rm
= inst
.operands
[2].reg
;
11333 reject_bad_reg (Rd
);
11334 reject_bad_reg (Rn
);
11335 reject_bad_reg (Rm
);
11337 inst
.instruction
|= Rd
<< 8;
11338 inst
.instruction
|= Rn
<< 16;
11339 inst
.instruction
|= Rm
;
11340 if (inst
.operands
[3].present
)
11342 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11343 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11344 _("expression too complex"));
11345 inst
.instruction
|= (val
& 0x1c) << 10;
11346 inst
.instruction
|= (val
& 0x03) << 6;
11353 if (!inst
.operands
[3].present
)
11357 inst
.instruction
&= ~0x00000020;
11359 /* PR 10168. Swap the Rm and Rn registers. */
11360 Rtmp
= inst
.operands
[1].reg
;
11361 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11362 inst
.operands
[2].reg
= Rtmp
;
11370 if (inst
.operands
[0].immisreg
)
11371 reject_bad_reg (inst
.operands
[0].imm
);
11373 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11377 do_t_push_pop (void)
11381 constraint (inst
.operands
[0].writeback
,
11382 _("push/pop do not support {reglist}^"));
11383 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11384 _("expression too complex"));
11386 mask
= inst
.operands
[0].imm
;
11387 if ((mask
& ~0xff) == 0)
11388 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11389 else if ((inst
.instruction
== T_MNEM_push
11390 && (mask
& ~0xff) == 1 << REG_LR
)
11391 || (inst
.instruction
== T_MNEM_pop
11392 && (mask
& ~0xff) == 1 << REG_PC
))
11394 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11395 inst
.instruction
|= THUMB_PP_PC_LR
;
11396 inst
.instruction
|= mask
& 0xff;
11398 else if (unified_syntax
)
11400 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11401 encode_thumb2_ldmstm (13, mask
, TRUE
);
11405 inst
.error
= _("invalid register list to push/pop instruction");
11415 Rd
= inst
.operands
[0].reg
;
11416 Rm
= inst
.operands
[1].reg
;
11418 reject_bad_reg (Rd
);
11419 reject_bad_reg (Rm
);
11421 inst
.instruction
|= Rd
<< 8;
11422 inst
.instruction
|= Rm
<< 16;
11423 inst
.instruction
|= Rm
;
11431 Rd
= inst
.operands
[0].reg
;
11432 Rm
= inst
.operands
[1].reg
;
11434 reject_bad_reg (Rd
);
11435 reject_bad_reg (Rm
);
11437 if (Rd
<= 7 && Rm
<= 7
11438 && inst
.size_req
!= 4)
11440 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11441 inst
.instruction
|= Rd
;
11442 inst
.instruction
|= Rm
<< 3;
11444 else if (unified_syntax
)
11446 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11447 inst
.instruction
|= Rd
<< 8;
11448 inst
.instruction
|= Rm
<< 16;
11449 inst
.instruction
|= Rm
;
11452 inst
.error
= BAD_HIREG
;
11460 Rd
= inst
.operands
[0].reg
;
11461 Rm
= inst
.operands
[1].reg
;
11463 reject_bad_reg (Rd
);
11464 reject_bad_reg (Rm
);
11466 inst
.instruction
|= Rd
<< 8;
11467 inst
.instruction
|= Rm
;
11475 Rd
= inst
.operands
[0].reg
;
11476 Rs
= (inst
.operands
[1].present
11477 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11478 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11480 reject_bad_reg (Rd
);
11481 reject_bad_reg (Rs
);
11482 if (inst
.operands
[2].isreg
)
11483 reject_bad_reg (inst
.operands
[2].reg
);
11485 inst
.instruction
|= Rd
<< 8;
11486 inst
.instruction
|= Rs
<< 16;
11487 if (!inst
.operands
[2].isreg
)
11489 bfd_boolean narrow
;
11491 if ((inst
.instruction
& 0x00100000) != 0)
11492 narrow
= !in_it_block ();
11494 narrow
= in_it_block ();
11496 if (Rd
> 7 || Rs
> 7)
11499 if (inst
.size_req
== 4 || !unified_syntax
)
11502 if (inst
.reloc
.exp
.X_op
!= O_constant
11503 || inst
.reloc
.exp
.X_add_number
!= 0)
11506 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11507 relaxation, but it doesn't seem worth the hassle. */
11510 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11511 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11512 inst
.instruction
|= Rs
<< 3;
11513 inst
.instruction
|= Rd
;
11517 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11518 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11522 encode_thumb32_shifted_operand (2);
11528 set_it_insn_type (OUTSIDE_IT_INSN
);
11529 if (inst
.operands
[0].imm
)
11530 inst
.instruction
|= 0x8;
11536 if (!inst
.operands
[1].present
)
11537 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11539 if (unified_syntax
)
11541 bfd_boolean narrow
;
11544 switch (inst
.instruction
)
11547 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11549 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11551 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11553 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11557 if (THUMB_SETS_FLAGS (inst
.instruction
))
11558 narrow
= !in_it_block ();
11560 narrow
= in_it_block ();
11561 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11563 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11565 if (inst
.operands
[2].isreg
11566 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11567 || inst
.operands
[2].reg
> 7))
11569 if (inst
.size_req
== 4)
11572 reject_bad_reg (inst
.operands
[0].reg
);
11573 reject_bad_reg (inst
.operands
[1].reg
);
11577 if (inst
.operands
[2].isreg
)
11579 reject_bad_reg (inst
.operands
[2].reg
);
11580 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11581 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11582 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11583 inst
.instruction
|= inst
.operands
[2].reg
;
11585 /* PR 12854: Error on extraneous shifts. */
11586 constraint (inst
.operands
[2].shifted
,
11587 _("extraneous shift as part of operand to shift insn"));
11591 inst
.operands
[1].shifted
= 1;
11592 inst
.operands
[1].shift_kind
= shift_kind
;
11593 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11594 ? T_MNEM_movs
: T_MNEM_mov
);
11595 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11596 encode_thumb32_shifted_operand (1);
11597 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11598 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11603 if (inst
.operands
[2].isreg
)
11605 switch (shift_kind
)
11607 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11608 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11609 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11610 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11614 inst
.instruction
|= inst
.operands
[0].reg
;
11615 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11617 /* PR 12854: Error on extraneous shifts. */
11618 constraint (inst
.operands
[2].shifted
,
11619 _("extraneous shift as part of operand to shift insn"));
11623 switch (shift_kind
)
11625 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11626 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11627 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11630 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11631 inst
.instruction
|= inst
.operands
[0].reg
;
11632 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11638 constraint (inst
.operands
[0].reg
> 7
11639 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11640 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11642 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11644 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11645 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11646 _("source1 and dest must be same register"));
11648 switch (inst
.instruction
)
11650 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11651 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11652 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11653 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11657 inst
.instruction
|= inst
.operands
[0].reg
;
11658 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11660 /* PR 12854: Error on extraneous shifts. */
11661 constraint (inst
.operands
[2].shifted
,
11662 _("extraneous shift as part of operand to shift insn"));
11666 switch (inst
.instruction
)
11668 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11669 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11670 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11671 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11674 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11675 inst
.instruction
|= inst
.operands
[0].reg
;
11676 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11684 unsigned Rd
, Rn
, Rm
;
11686 Rd
= inst
.operands
[0].reg
;
11687 Rn
= inst
.operands
[1].reg
;
11688 Rm
= inst
.operands
[2].reg
;
11690 reject_bad_reg (Rd
);
11691 reject_bad_reg (Rn
);
11692 reject_bad_reg (Rm
);
11694 inst
.instruction
|= Rd
<< 8;
11695 inst
.instruction
|= Rn
<< 16;
11696 inst
.instruction
|= Rm
;
11702 unsigned Rd
, Rn
, Rm
;
11704 Rd
= inst
.operands
[0].reg
;
11705 Rm
= inst
.operands
[1].reg
;
11706 Rn
= inst
.operands
[2].reg
;
11708 reject_bad_reg (Rd
);
11709 reject_bad_reg (Rn
);
11710 reject_bad_reg (Rm
);
11712 inst
.instruction
|= Rd
<< 8;
11713 inst
.instruction
|= Rn
<< 16;
11714 inst
.instruction
|= Rm
;
11720 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11721 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11722 _("SMC is not permitted on this architecture"));
11723 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11724 _("expression too complex"));
11725 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11726 inst
.instruction
|= (value
& 0xf000) >> 12;
11727 inst
.instruction
|= (value
& 0x0ff0);
11728 inst
.instruction
|= (value
& 0x000f) << 16;
11734 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11736 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11737 inst
.instruction
|= (value
& 0x0fff);
11738 inst
.instruction
|= (value
& 0xf000) << 4;
11742 do_t_ssat_usat (int bias
)
11746 Rd
= inst
.operands
[0].reg
;
11747 Rn
= inst
.operands
[2].reg
;
11749 reject_bad_reg (Rd
);
11750 reject_bad_reg (Rn
);
11752 inst
.instruction
|= Rd
<< 8;
11753 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11754 inst
.instruction
|= Rn
<< 16;
11756 if (inst
.operands
[3].present
)
11758 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11760 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11762 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11763 _("expression too complex"));
11765 if (shift_amount
!= 0)
11767 constraint (shift_amount
> 31,
11768 _("shift expression is too large"));
11770 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11771 inst
.instruction
|= 0x00200000; /* sh bit. */
11773 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11774 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11782 do_t_ssat_usat (1);
11790 Rd
= inst
.operands
[0].reg
;
11791 Rn
= inst
.operands
[2].reg
;
11793 reject_bad_reg (Rd
);
11794 reject_bad_reg (Rn
);
11796 inst
.instruction
|= Rd
<< 8;
11797 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11798 inst
.instruction
|= Rn
<< 16;
11804 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11805 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11806 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11807 || inst
.operands
[2].negative
,
11810 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11813 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11814 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11815 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11821 if (!inst
.operands
[2].present
)
11822 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11824 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11825 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11826 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11829 inst
.instruction
|= inst
.operands
[0].reg
;
11830 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11831 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11832 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11838 unsigned Rd
, Rn
, Rm
;
11840 Rd
= inst
.operands
[0].reg
;
11841 Rn
= inst
.operands
[1].reg
;
11842 Rm
= inst
.operands
[2].reg
;
11844 reject_bad_reg (Rd
);
11845 reject_bad_reg (Rn
);
11846 reject_bad_reg (Rm
);
11848 inst
.instruction
|= Rd
<< 8;
11849 inst
.instruction
|= Rn
<< 16;
11850 inst
.instruction
|= Rm
;
11851 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11859 Rd
= inst
.operands
[0].reg
;
11860 Rm
= inst
.operands
[1].reg
;
11862 reject_bad_reg (Rd
);
11863 reject_bad_reg (Rm
);
11865 if (inst
.instruction
<= 0xffff
11866 && inst
.size_req
!= 4
11867 && Rd
<= 7 && Rm
<= 7
11868 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11870 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11871 inst
.instruction
|= Rd
;
11872 inst
.instruction
|= Rm
<< 3;
11874 else if (unified_syntax
)
11876 if (inst
.instruction
<= 0xffff)
11877 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11878 inst
.instruction
|= Rd
<< 8;
11879 inst
.instruction
|= Rm
;
11880 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11884 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11885 _("Thumb encoding does not support rotation"));
11886 constraint (1, BAD_HIREG
);
11893 /* We have to do the following check manually as ARM_EXT_OS only applies
11895 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11897 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11898 /* This only applies to the v6m howver, not later architectures. */
11899 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11900 as_bad (_("SVC is not permitted on this architecture"));
11901 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11904 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11913 half
= (inst
.instruction
& 0x10) != 0;
11914 set_it_insn_type_last ();
11915 constraint (inst
.operands
[0].immisreg
,
11916 _("instruction requires register index"));
11918 Rn
= inst
.operands
[0].reg
;
11919 Rm
= inst
.operands
[0].imm
;
11921 constraint (Rn
== REG_SP
, BAD_SP
);
11922 reject_bad_reg (Rm
);
11924 constraint (!half
&& inst
.operands
[0].shifted
,
11925 _("instruction does not allow shifted index"));
11926 inst
.instruction
|= (Rn
<< 16) | Rm
;
11932 do_t_ssat_usat (0);
11940 Rd
= inst
.operands
[0].reg
;
11941 Rn
= inst
.operands
[2].reg
;
11943 reject_bad_reg (Rd
);
11944 reject_bad_reg (Rn
);
11946 inst
.instruction
|= Rd
<< 8;
11947 inst
.instruction
|= inst
.operands
[1].imm
;
11948 inst
.instruction
|= Rn
<< 16;
11951 /* Neon instruction encoder helpers. */
11953 /* Encodings for the different types for various Neon opcodes. */
11955 /* An "invalid" code for the following tables. */
11958 struct neon_tab_entry
11961 unsigned float_or_poly
;
11962 unsigned scalar_or_imm
;
11965 /* Map overloaded Neon opcodes to their respective encodings. */
11966 #define NEON_ENC_TAB \
11967 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11968 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11969 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11970 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11971 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11972 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11973 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11974 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11975 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11976 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11977 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11978 /* Register variants of the following two instructions are encoded as
11979 vcge / vcgt with the operands reversed. */ \
11980 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11981 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11982 X(vfma, N_INV, 0x0000c10, N_INV), \
11983 X(vfms, N_INV, 0x0200c10, N_INV), \
11984 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11985 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11986 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11987 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11988 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11989 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11990 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11991 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11992 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11993 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11994 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11995 X(vshl, 0x0000400, N_INV, 0x0800510), \
11996 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11997 X(vand, 0x0000110, N_INV, 0x0800030), \
11998 X(vbic, 0x0100110, N_INV, 0x0800030), \
11999 X(veor, 0x1000110, N_INV, N_INV), \
12000 X(vorn, 0x0300110, N_INV, 0x0800010), \
12001 X(vorr, 0x0200110, N_INV, 0x0800010), \
12002 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12003 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12004 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12005 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12006 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12007 X(vst1, 0x0000000, 0x0800000, N_INV), \
12008 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12009 X(vst2, 0x0000100, 0x0800100, N_INV), \
12010 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12011 X(vst3, 0x0000200, 0x0800200, N_INV), \
12012 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12013 X(vst4, 0x0000300, 0x0800300, N_INV), \
12014 X(vmovn, 0x1b20200, N_INV, N_INV), \
12015 X(vtrn, 0x1b20080, N_INV, N_INV), \
12016 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12017 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12018 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12019 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12020 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12021 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12022 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12023 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12024 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12025 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12026 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12030 #define X(OPC,I,F,S) N_MNEM_##OPC
12035 static const struct neon_tab_entry neon_enc_tab
[] =
12037 #define X(OPC,I,F,S) { (I), (F), (S) }
12042 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12043 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12044 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12045 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12046 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12047 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12048 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12049 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12050 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12051 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12052 #define NEON_ENC_SINGLE_(X) \
12053 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12054 #define NEON_ENC_DOUBLE_(X) \
12055 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12057 #define NEON_ENCODE(type, inst) \
12060 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12061 inst.is_neon = 1; \
12065 #define check_neon_suffixes \
12068 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12070 as_bad (_("invalid neon suffix for non neon instruction")); \
12076 /* Define shapes for instruction operands. The following mnemonic characters
12077 are used in this table:
12079 F - VFP S<n> register
12080 D - Neon D<n> register
12081 Q - Neon Q<n> register
12085 L - D<n> register list
12087 This table is used to generate various data:
12088 - enumerations of the form NS_DDR to be used as arguments to
12090 - a table classifying shapes into single, double, quad, mixed.
12091 - a table used to drive neon_select_shape. */
12093 #define NEON_SHAPE_DEF \
12094 X(3, (D, D, D), DOUBLE), \
12095 X(3, (Q, Q, Q), QUAD), \
12096 X(3, (D, D, I), DOUBLE), \
12097 X(3, (Q, Q, I), QUAD), \
12098 X(3, (D, D, S), DOUBLE), \
12099 X(3, (Q, Q, S), QUAD), \
12100 X(2, (D, D), DOUBLE), \
12101 X(2, (Q, Q), QUAD), \
12102 X(2, (D, S), DOUBLE), \
12103 X(2, (Q, S), QUAD), \
12104 X(2, (D, R), DOUBLE), \
12105 X(2, (Q, R), QUAD), \
12106 X(2, (D, I), DOUBLE), \
12107 X(2, (Q, I), QUAD), \
12108 X(3, (D, L, D), DOUBLE), \
12109 X(2, (D, Q), MIXED), \
12110 X(2, (Q, D), MIXED), \
12111 X(3, (D, Q, I), MIXED), \
12112 X(3, (Q, D, I), MIXED), \
12113 X(3, (Q, D, D), MIXED), \
12114 X(3, (D, Q, Q), MIXED), \
12115 X(3, (Q, Q, D), MIXED), \
12116 X(3, (Q, D, S), MIXED), \
12117 X(3, (D, Q, S), MIXED), \
12118 X(4, (D, D, D, I), DOUBLE), \
12119 X(4, (Q, Q, Q, I), QUAD), \
12120 X(2, (F, F), SINGLE), \
12121 X(3, (F, F, F), SINGLE), \
12122 X(2, (F, I), SINGLE), \
12123 X(2, (F, D), MIXED), \
12124 X(2, (D, F), MIXED), \
12125 X(3, (F, F, I), MIXED), \
12126 X(4, (R, R, F, F), SINGLE), \
12127 X(4, (F, F, R, R), SINGLE), \
12128 X(3, (D, R, R), DOUBLE), \
12129 X(3, (R, R, D), DOUBLE), \
12130 X(2, (S, R), SINGLE), \
12131 X(2, (R, S), SINGLE), \
12132 X(2, (F, R), SINGLE), \
12133 X(2, (R, F), SINGLE)
12135 #define S2(A,B) NS_##A##B
12136 #define S3(A,B,C) NS_##A##B##C
12137 #define S4(A,B,C,D) NS_##A##B##C##D
12139 #define X(N, L, C) S##N L
12152 enum neon_shape_class
12160 #define X(N, L, C) SC_##C
12162 static enum neon_shape_class neon_shape_class
[] =
12180 /* Register widths of above. */
12181 static unsigned neon_shape_el_size
[] =
12192 struct neon_shape_info
12195 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12198 #define S2(A,B) { SE_##A, SE_##B }
12199 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12200 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12202 #define X(N, L, C) { N, S##N L }
12204 static struct neon_shape_info neon_shape_tab
[] =
12214 /* Bit masks used in type checking given instructions.
12215 'N_EQK' means the type must be the same as (or based on in some way) the key
12216 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12217 set, various other bits can be set as well in order to modify the meaning of
12218 the type constraint. */
12220 enum neon_type_mask
12243 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12244 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12245 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12246 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12247 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12248 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12249 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12250 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12251 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12252 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12254 N_MAX_NONSPECIAL
= N_F64
12257 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12259 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12260 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12261 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12262 #define N_SUF_32 (N_SU_32 | N_F32)
12263 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12264 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12266 /* Pass this as the first type argument to neon_check_type to ignore types
12268 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12270 /* Select a "shape" for the current instruction (describing register types or
12271 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12272 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12273 function of operand parsing, so this function doesn't need to be called.
12274 Shapes should be listed in order of decreasing length. */
12276 static enum neon_shape
12277 neon_select_shape (enum neon_shape shape
, ...)
12280 enum neon_shape first_shape
= shape
;
12282 /* Fix missing optional operands. FIXME: we don't know at this point how
12283 many arguments we should have, so this makes the assumption that we have
12284 > 1. This is true of all current Neon opcodes, I think, but may not be
12285 true in the future. */
12286 if (!inst
.operands
[1].present
)
12287 inst
.operands
[1] = inst
.operands
[0];
12289 va_start (ap
, shape
);
12291 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12296 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12298 if (!inst
.operands
[j
].present
)
12304 switch (neon_shape_tab
[shape
].el
[j
])
12307 if (!(inst
.operands
[j
].isreg
12308 && inst
.operands
[j
].isvec
12309 && inst
.operands
[j
].issingle
12310 && !inst
.operands
[j
].isquad
))
12315 if (!(inst
.operands
[j
].isreg
12316 && inst
.operands
[j
].isvec
12317 && !inst
.operands
[j
].isquad
12318 && !inst
.operands
[j
].issingle
))
12323 if (!(inst
.operands
[j
].isreg
12324 && !inst
.operands
[j
].isvec
))
12329 if (!(inst
.operands
[j
].isreg
12330 && inst
.operands
[j
].isvec
12331 && inst
.operands
[j
].isquad
12332 && !inst
.operands
[j
].issingle
))
12337 if (!(!inst
.operands
[j
].isreg
12338 && !inst
.operands
[j
].isscalar
))
12343 if (!(!inst
.operands
[j
].isreg
12344 && inst
.operands
[j
].isscalar
))
12360 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12361 first_error (_("invalid instruction shape"));
12366 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12367 means the Q bit should be set). */
12370 neon_quad (enum neon_shape shape
)
12372 return neon_shape_class
[shape
] == SC_QUAD
;
12376 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12379 /* Allow modification to be made to types which are constrained to be
12380 based on the key element, based on bits set alongside N_EQK. */
12381 if ((typebits
& N_EQK
) != 0)
12383 if ((typebits
& N_HLF
) != 0)
12385 else if ((typebits
& N_DBL
) != 0)
12387 if ((typebits
& N_SGN
) != 0)
12388 *g_type
= NT_signed
;
12389 else if ((typebits
& N_UNS
) != 0)
12390 *g_type
= NT_unsigned
;
12391 else if ((typebits
& N_INT
) != 0)
12392 *g_type
= NT_integer
;
12393 else if ((typebits
& N_FLT
) != 0)
12394 *g_type
= NT_float
;
12395 else if ((typebits
& N_SIZ
) != 0)
12396 *g_type
= NT_untyped
;
12400 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12401 operand type, i.e. the single type specified in a Neon instruction when it
12402 is the only one given. */
12404 static struct neon_type_el
12405 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12407 struct neon_type_el dest
= *key
;
12409 gas_assert ((thisarg
& N_EQK
) != 0);
12411 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12416 /* Convert Neon type and size into compact bitmask representation. */
12418 static enum neon_type_mask
12419 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12426 case 8: return N_8
;
12427 case 16: return N_16
;
12428 case 32: return N_32
;
12429 case 64: return N_64
;
12437 case 8: return N_I8
;
12438 case 16: return N_I16
;
12439 case 32: return N_I32
;
12440 case 64: return N_I64
;
12448 case 16: return N_F16
;
12449 case 32: return N_F32
;
12450 case 64: return N_F64
;
12458 case 8: return N_P8
;
12459 case 16: return N_P16
;
12467 case 8: return N_S8
;
12468 case 16: return N_S16
;
12469 case 32: return N_S32
;
12470 case 64: return N_S64
;
12478 case 8: return N_U8
;
12479 case 16: return N_U16
;
12480 case 32: return N_U32
;
12481 case 64: return N_U64
;
12492 /* Convert compact Neon bitmask type representation to a type and size. Only
12493 handles the case where a single bit is set in the mask. */
12496 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12497 enum neon_type_mask mask
)
12499 if ((mask
& N_EQK
) != 0)
12502 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12504 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12506 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12508 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12513 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12515 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12516 *type
= NT_unsigned
;
12517 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12518 *type
= NT_integer
;
12519 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12520 *type
= NT_untyped
;
12521 else if ((mask
& (N_P8
| N_P16
)) != 0)
12523 else if ((mask
& (N_F32
| N_F64
)) != 0)
12531 /* Modify a bitmask of allowed types. This is only needed for type
12535 modify_types_allowed (unsigned allowed
, unsigned mods
)
12538 enum neon_el_type type
;
12544 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12546 if (el_type_of_type_chk (&type
, &size
,
12547 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12549 neon_modify_type_size (mods
, &type
, &size
);
12550 destmask
|= type_chk_of_el_type (type
, size
);
12557 /* Check type and return type classification.
12558 The manual states (paraphrase): If one datatype is given, it indicates the
12560 - the second operand, if there is one
12561 - the operand, if there is no second operand
12562 - the result, if there are no operands.
12563 This isn't quite good enough though, so we use a concept of a "key" datatype
12564 which is set on a per-instruction basis, which is the one which matters when
12565 only one data type is written.
12566 Note: this function has side-effects (e.g. filling in missing operands). All
12567 Neon instructions should call it before performing bit encoding. */
12569 static struct neon_type_el
12570 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12573 unsigned i
, pass
, key_el
= 0;
12574 unsigned types
[NEON_MAX_TYPE_ELS
];
12575 enum neon_el_type k_type
= NT_invtype
;
12576 unsigned k_size
= -1u;
12577 struct neon_type_el badtype
= {NT_invtype
, -1};
12578 unsigned key_allowed
= 0;
12580 /* Optional registers in Neon instructions are always (not) in operand 1.
12581 Fill in the missing operand here, if it was omitted. */
12582 if (els
> 1 && !inst
.operands
[1].present
)
12583 inst
.operands
[1] = inst
.operands
[0];
12585 /* Suck up all the varargs. */
12587 for (i
= 0; i
< els
; i
++)
12589 unsigned thisarg
= va_arg (ap
, unsigned);
12590 if (thisarg
== N_IGNORE_TYPE
)
12595 types
[i
] = thisarg
;
12596 if ((thisarg
& N_KEY
) != 0)
12601 if (inst
.vectype
.elems
> 0)
12602 for (i
= 0; i
< els
; i
++)
12603 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12605 first_error (_("types specified in both the mnemonic and operands"));
12609 /* Duplicate inst.vectype elements here as necessary.
12610 FIXME: No idea if this is exactly the same as the ARM assembler,
12611 particularly when an insn takes one register and one non-register
12613 if (inst
.vectype
.elems
== 1 && els
> 1)
12616 inst
.vectype
.elems
= els
;
12617 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12618 for (j
= 0; j
< els
; j
++)
12620 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12623 else if (inst
.vectype
.elems
== 0 && els
> 0)
12626 /* No types were given after the mnemonic, so look for types specified
12627 after each operand. We allow some flexibility here; as long as the
12628 "key" operand has a type, we can infer the others. */
12629 for (j
= 0; j
< els
; j
++)
12630 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12631 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12633 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12635 for (j
= 0; j
< els
; j
++)
12636 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12637 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12642 first_error (_("operand types can't be inferred"));
12646 else if (inst
.vectype
.elems
!= els
)
12648 first_error (_("type specifier has the wrong number of parts"));
12652 for (pass
= 0; pass
< 2; pass
++)
12654 for (i
= 0; i
< els
; i
++)
12656 unsigned thisarg
= types
[i
];
12657 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12658 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12659 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12660 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12662 /* Decay more-specific signed & unsigned types to sign-insensitive
12663 integer types if sign-specific variants are unavailable. */
12664 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12665 && (types_allowed
& N_SU_ALL
) == 0)
12666 g_type
= NT_integer
;
12668 /* If only untyped args are allowed, decay any more specific types to
12669 them. Some instructions only care about signs for some element
12670 sizes, so handle that properly. */
12671 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12672 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12673 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12674 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12675 g_type
= NT_untyped
;
12679 if ((thisarg
& N_KEY
) != 0)
12683 key_allowed
= thisarg
& ~N_KEY
;
12688 if ((thisarg
& N_VFP
) != 0)
12690 enum neon_shape_el regshape
;
12691 unsigned regwidth
, match
;
12693 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12696 first_error (_("invalid instruction shape"));
12699 regshape
= neon_shape_tab
[ns
].el
[i
];
12700 regwidth
= neon_shape_el_size
[regshape
];
12702 /* In VFP mode, operands must match register widths. If we
12703 have a key operand, use its width, else use the width of
12704 the current operand. */
12710 if (regwidth
!= match
)
12712 first_error (_("operand size must match register width"));
12717 if ((thisarg
& N_EQK
) == 0)
12719 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12721 if ((given_type
& types_allowed
) == 0)
12723 first_error (_("bad type in Neon instruction"));
12729 enum neon_el_type mod_k_type
= k_type
;
12730 unsigned mod_k_size
= k_size
;
12731 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12732 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12734 first_error (_("inconsistent types in Neon instruction"));
12742 return inst
.vectype
.el
[key_el
];
12745 /* Neon-style VFP instruction forwarding. */
12747 /* Thumb VFP instructions have 0xE in the condition field. */
12750 do_vfp_cond_or_thumb (void)
12755 inst
.instruction
|= 0xe0000000;
12757 inst
.instruction
|= inst
.cond
<< 28;
12760 /* Look up and encode a simple mnemonic, for use as a helper function for the
12761 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12762 etc. It is assumed that operand parsing has already been done, and that the
12763 operands are in the form expected by the given opcode (this isn't necessarily
12764 the same as the form in which they were parsed, hence some massaging must
12765 take place before this function is called).
12766 Checks current arch version against that in the looked-up opcode. */
12769 do_vfp_nsyn_opcode (const char *opname
)
12771 const struct asm_opcode
*opcode
;
12773 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12778 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12779 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12786 inst
.instruction
= opcode
->tvalue
;
12787 opcode
->tencode ();
12791 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12792 opcode
->aencode ();
12797 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12799 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12804 do_vfp_nsyn_opcode ("fadds");
12806 do_vfp_nsyn_opcode ("fsubs");
12811 do_vfp_nsyn_opcode ("faddd");
12813 do_vfp_nsyn_opcode ("fsubd");
12817 /* Check operand types to see if this is a VFP instruction, and if so call
12821 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12823 enum neon_shape rs
;
12824 struct neon_type_el et
;
12829 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12830 et
= neon_check_type (2, rs
,
12831 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12835 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12836 et
= neon_check_type (3, rs
,
12837 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12844 if (et
.type
!= NT_invtype
)
12855 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12857 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12862 do_vfp_nsyn_opcode ("fmacs");
12864 do_vfp_nsyn_opcode ("fnmacs");
12869 do_vfp_nsyn_opcode ("fmacd");
12871 do_vfp_nsyn_opcode ("fnmacd");
12876 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12878 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12883 do_vfp_nsyn_opcode ("ffmas");
12885 do_vfp_nsyn_opcode ("ffnmas");
12890 do_vfp_nsyn_opcode ("ffmad");
12892 do_vfp_nsyn_opcode ("ffnmad");
12897 do_vfp_nsyn_mul (enum neon_shape rs
)
12900 do_vfp_nsyn_opcode ("fmuls");
12902 do_vfp_nsyn_opcode ("fmuld");
12906 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12908 int is_neg
= (inst
.instruction
& 0x80) != 0;
12909 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12914 do_vfp_nsyn_opcode ("fnegs");
12916 do_vfp_nsyn_opcode ("fabss");
12921 do_vfp_nsyn_opcode ("fnegd");
12923 do_vfp_nsyn_opcode ("fabsd");
12927 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12928 insns belong to Neon, and are handled elsewhere. */
12931 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12933 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12937 do_vfp_nsyn_opcode ("fldmdbs");
12939 do_vfp_nsyn_opcode ("fldmias");
12944 do_vfp_nsyn_opcode ("fstmdbs");
12946 do_vfp_nsyn_opcode ("fstmias");
12951 do_vfp_nsyn_sqrt (void)
12953 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12954 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12957 do_vfp_nsyn_opcode ("fsqrts");
12959 do_vfp_nsyn_opcode ("fsqrtd");
12963 do_vfp_nsyn_div (void)
12965 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12966 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12967 N_F32
| N_F64
| N_KEY
| N_VFP
);
12970 do_vfp_nsyn_opcode ("fdivs");
12972 do_vfp_nsyn_opcode ("fdivd");
12976 do_vfp_nsyn_nmul (void)
12978 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12979 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12980 N_F32
| N_F64
| N_KEY
| N_VFP
);
12984 NEON_ENCODE (SINGLE
, inst
);
12985 do_vfp_sp_dyadic ();
12989 NEON_ENCODE (DOUBLE
, inst
);
12990 do_vfp_dp_rd_rn_rm ();
12992 do_vfp_cond_or_thumb ();
12996 do_vfp_nsyn_cmp (void)
12998 if (inst
.operands
[1].isreg
)
13000 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13001 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13005 NEON_ENCODE (SINGLE
, inst
);
13006 do_vfp_sp_monadic ();
13010 NEON_ENCODE (DOUBLE
, inst
);
13011 do_vfp_dp_rd_rm ();
13016 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13017 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13019 switch (inst
.instruction
& 0x0fffffff)
13022 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13025 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13033 NEON_ENCODE (SINGLE
, inst
);
13034 do_vfp_sp_compare_z ();
13038 NEON_ENCODE (DOUBLE
, inst
);
13042 do_vfp_cond_or_thumb ();
13046 nsyn_insert_sp (void)
13048 inst
.operands
[1] = inst
.operands
[0];
13049 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13050 inst
.operands
[0].reg
= REG_SP
;
13051 inst
.operands
[0].isreg
= 1;
13052 inst
.operands
[0].writeback
= 1;
13053 inst
.operands
[0].present
= 1;
13057 do_vfp_nsyn_push (void)
13060 if (inst
.operands
[1].issingle
)
13061 do_vfp_nsyn_opcode ("fstmdbs");
13063 do_vfp_nsyn_opcode ("fstmdbd");
13067 do_vfp_nsyn_pop (void)
13070 if (inst
.operands
[1].issingle
)
13071 do_vfp_nsyn_opcode ("fldmias");
13073 do_vfp_nsyn_opcode ("fldmiad");
13076 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13077 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13080 neon_dp_fixup (struct arm_it
* insn
)
13082 unsigned int i
= insn
->instruction
;
13087 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13098 insn
->instruction
= i
;
13101 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13105 neon_logbits (unsigned x
)
13107 return ffs (x
) - 4;
13110 #define LOW4(R) ((R) & 0xf)
13111 #define HI1(R) (((R) >> 4) & 1)
13113 /* Encode insns with bit pattern:
13115 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13116 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13118 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13119 different meaning for some instruction. */
13122 neon_three_same (int isquad
, int ubit
, int size
)
13124 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13125 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13126 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13127 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13128 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13129 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13130 inst
.instruction
|= (isquad
!= 0) << 6;
13131 inst
.instruction
|= (ubit
!= 0) << 24;
13133 inst
.instruction
|= neon_logbits (size
) << 20;
13135 neon_dp_fixup (&inst
);
13138 /* Encode instructions of the form:
13140 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13141 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13143 Don't write size if SIZE == -1. */
13146 neon_two_same (int qbit
, int ubit
, int size
)
13148 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13152 inst
.instruction
|= (qbit
!= 0) << 6;
13153 inst
.instruction
|= (ubit
!= 0) << 24;
13156 inst
.instruction
|= neon_logbits (size
) << 18;
13158 neon_dp_fixup (&inst
);
13161 /* Neon instruction encoders, in approximate order of appearance. */
13164 do_neon_dyadic_i_su (void)
13166 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13167 struct neon_type_el et
= neon_check_type (3, rs
,
13168 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13169 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13173 do_neon_dyadic_i64_su (void)
13175 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13176 struct neon_type_el et
= neon_check_type (3, rs
,
13177 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13178 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13182 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13185 unsigned size
= et
.size
>> 3;
13186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13188 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13190 inst
.instruction
|= (isquad
!= 0) << 6;
13191 inst
.instruction
|= immbits
<< 16;
13192 inst
.instruction
|= (size
>> 3) << 7;
13193 inst
.instruction
|= (size
& 0x7) << 19;
13195 inst
.instruction
|= (uval
!= 0) << 24;
13197 neon_dp_fixup (&inst
);
13201 do_neon_shl_imm (void)
13203 if (!inst
.operands
[2].isreg
)
13205 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13206 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13207 NEON_ENCODE (IMMED
, inst
);
13208 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13212 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13213 struct neon_type_el et
= neon_check_type (3, rs
,
13214 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13217 /* VSHL/VQSHL 3-register variants have syntax such as:
13219 whereas other 3-register operations encoded by neon_three_same have
13222 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13224 tmp
= inst
.operands
[2].reg
;
13225 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13226 inst
.operands
[1].reg
= tmp
;
13227 NEON_ENCODE (INTEGER
, inst
);
13228 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13233 do_neon_qshl_imm (void)
13235 if (!inst
.operands
[2].isreg
)
13237 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13238 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13240 NEON_ENCODE (IMMED
, inst
);
13241 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13242 inst
.operands
[2].imm
);
13246 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13247 struct neon_type_el et
= neon_check_type (3, rs
,
13248 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13251 /* See note in do_neon_shl_imm. */
13252 tmp
= inst
.operands
[2].reg
;
13253 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13254 inst
.operands
[1].reg
= tmp
;
13255 NEON_ENCODE (INTEGER
, inst
);
13256 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13261 do_neon_rshl (void)
13263 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13264 struct neon_type_el et
= neon_check_type (3, rs
,
13265 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13268 tmp
= inst
.operands
[2].reg
;
13269 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13270 inst
.operands
[1].reg
= tmp
;
13271 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13275 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13277 /* Handle .I8 pseudo-instructions. */
13280 /* Unfortunately, this will make everything apart from zero out-of-range.
13281 FIXME is this the intended semantics? There doesn't seem much point in
13282 accepting .I8 if so. */
13283 immediate
|= immediate
<< 8;
13289 if (immediate
== (immediate
& 0x000000ff))
13291 *immbits
= immediate
;
13294 else if (immediate
== (immediate
& 0x0000ff00))
13296 *immbits
= immediate
>> 8;
13299 else if (immediate
== (immediate
& 0x00ff0000))
13301 *immbits
= immediate
>> 16;
13304 else if (immediate
== (immediate
& 0xff000000))
13306 *immbits
= immediate
>> 24;
13309 if ((immediate
& 0xffff) != (immediate
>> 16))
13310 goto bad_immediate
;
13311 immediate
&= 0xffff;
13314 if (immediate
== (immediate
& 0x000000ff))
13316 *immbits
= immediate
;
13319 else if (immediate
== (immediate
& 0x0000ff00))
13321 *immbits
= immediate
>> 8;
13326 first_error (_("immediate value out of range"));
13330 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13334 neon_bits_same_in_bytes (unsigned imm
)
13336 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13337 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13338 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13339 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13342 /* For immediate of above form, return 0bABCD. */
13345 neon_squash_bits (unsigned imm
)
13347 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13348 | ((imm
& 0x01000000) >> 21);
13351 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13354 neon_qfloat_bits (unsigned imm
)
13356 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13359 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13360 the instruction. *OP is passed as the initial value of the op field, and
13361 may be set to a different value depending on the constant (i.e.
13362 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13363 MVN). If the immediate looks like a repeated pattern then also
13364 try smaller element sizes. */
13367 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13368 unsigned *immbits
, int *op
, int size
,
13369 enum neon_el_type type
)
13371 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13373 if (type
== NT_float
&& !float_p
)
13376 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13378 if (size
!= 32 || *op
== 1)
13380 *immbits
= neon_qfloat_bits (immlo
);
13386 if (neon_bits_same_in_bytes (immhi
)
13387 && neon_bits_same_in_bytes (immlo
))
13391 *immbits
= (neon_squash_bits (immhi
) << 4)
13392 | neon_squash_bits (immlo
);
13397 if (immhi
!= immlo
)
13403 if (immlo
== (immlo
& 0x000000ff))
13408 else if (immlo
== (immlo
& 0x0000ff00))
13410 *immbits
= immlo
>> 8;
13413 else if (immlo
== (immlo
& 0x00ff0000))
13415 *immbits
= immlo
>> 16;
13418 else if (immlo
== (immlo
& 0xff000000))
13420 *immbits
= immlo
>> 24;
13423 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13425 *immbits
= (immlo
>> 8) & 0xff;
13428 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13430 *immbits
= (immlo
>> 16) & 0xff;
13434 if ((immlo
& 0xffff) != (immlo
>> 16))
13441 if (immlo
== (immlo
& 0x000000ff))
13446 else if (immlo
== (immlo
& 0x0000ff00))
13448 *immbits
= immlo
>> 8;
13452 if ((immlo
& 0xff) != (immlo
>> 8))
13457 if (immlo
== (immlo
& 0x000000ff))
13459 /* Don't allow MVN with 8-bit immediate. */
13469 /* Write immediate bits [7:0] to the following locations:
13471 |28/24|23 19|18 16|15 4|3 0|
13472 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13474 This function is used by VMOV/VMVN/VORR/VBIC. */
13477 neon_write_immbits (unsigned immbits
)
13479 inst
.instruction
|= immbits
& 0xf;
13480 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13481 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13484 /* Invert low-order SIZE bits of XHI:XLO. */
13487 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13489 unsigned immlo
= xlo
? *xlo
: 0;
13490 unsigned immhi
= xhi
? *xhi
: 0;
13495 immlo
= (~immlo
) & 0xff;
13499 immlo
= (~immlo
) & 0xffff;
13503 immhi
= (~immhi
) & 0xffffffff;
13504 /* fall through. */
13507 immlo
= (~immlo
) & 0xffffffff;
13522 do_neon_logic (void)
13524 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13526 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13527 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13528 /* U bit and size field were set as part of the bitmask. */
13529 NEON_ENCODE (INTEGER
, inst
);
13530 neon_three_same (neon_quad (rs
), 0, -1);
13534 const int three_ops_form
= (inst
.operands
[2].present
13535 && !inst
.operands
[2].isreg
);
13536 const int immoperand
= (three_ops_form
? 2 : 1);
13537 enum neon_shape rs
= (three_ops_form
13538 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13539 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13540 struct neon_type_el et
= neon_check_type (2, rs
,
13541 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13542 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13546 if (et
.type
== NT_invtype
)
13549 if (three_ops_form
)
13550 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13551 _("first and second operands shall be the same register"));
13553 NEON_ENCODE (IMMED
, inst
);
13555 immbits
= inst
.operands
[immoperand
].imm
;
13558 /* .i64 is a pseudo-op, so the immediate must be a repeating
13560 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13561 inst
.operands
[immoperand
].reg
: 0))
13563 /* Set immbits to an invalid constant. */
13564 immbits
= 0xdeadbeef;
13571 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13575 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13579 /* Pseudo-instruction for VBIC. */
13580 neon_invert_size (&immbits
, 0, et
.size
);
13581 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13585 /* Pseudo-instruction for VORR. */
13586 neon_invert_size (&immbits
, 0, et
.size
);
13587 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13597 inst
.instruction
|= neon_quad (rs
) << 6;
13598 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13599 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13600 inst
.instruction
|= cmode
<< 8;
13601 neon_write_immbits (immbits
);
13603 neon_dp_fixup (&inst
);
13608 do_neon_bitfield (void)
13610 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13611 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13612 neon_three_same (neon_quad (rs
), 0, -1);
13616 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13619 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13620 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13622 if (et
.type
== NT_float
)
13624 NEON_ENCODE (FLOAT
, inst
);
13625 neon_three_same (neon_quad (rs
), 0, -1);
13629 NEON_ENCODE (INTEGER
, inst
);
13630 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13635 do_neon_dyadic_if_su (void)
13637 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13641 do_neon_dyadic_if_su_d (void)
13643 /* This version only allow D registers, but that constraint is enforced during
13644 operand parsing so we don't need to do anything extra here. */
13645 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13649 do_neon_dyadic_if_i_d (void)
13651 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13652 affected if we specify unsigned args. */
13653 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13656 enum vfp_or_neon_is_neon_bits
13659 NEON_CHECK_ARCH
= 2
13662 /* Call this function if an instruction which may have belonged to the VFP or
13663 Neon instruction sets, but turned out to be a Neon instruction (due to the
13664 operand types involved, etc.). We have to check and/or fix-up a couple of
13667 - Make sure the user hasn't attempted to make a Neon instruction
13669 - Alter the value in the condition code field if necessary.
13670 - Make sure that the arch supports Neon instructions.
13672 Which of these operations take place depends on bits from enum
13673 vfp_or_neon_is_neon_bits.
13675 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13676 current instruction's condition is COND_ALWAYS, the condition field is
13677 changed to inst.uncond_value. This is necessary because instructions shared
13678 between VFP and Neon may be conditional for the VFP variants only, and the
13679 unconditional Neon version must have, e.g., 0xF in the condition field. */
13682 vfp_or_neon_is_neon (unsigned check
)
13684 /* Conditions are always legal in Thumb mode (IT blocks). */
13685 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13687 if (inst
.cond
!= COND_ALWAYS
)
13689 first_error (_(BAD_COND
));
13692 if (inst
.uncond_value
!= -1)
13693 inst
.instruction
|= inst
.uncond_value
<< 28;
13696 if ((check
& NEON_CHECK_ARCH
)
13697 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13699 first_error (_(BAD_FPU
));
13707 do_neon_addsub_if_i (void)
13709 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13712 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13715 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13716 affected if we specify unsigned args. */
13717 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13720 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13722 V<op> A,B (A is operand 0, B is operand 2)
13727 so handle that case specially. */
13730 neon_exchange_operands (void)
13732 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13733 if (inst
.operands
[1].present
)
13735 /* Swap operands[1] and operands[2]. */
13736 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13737 inst
.operands
[1] = inst
.operands
[2];
13738 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13742 inst
.operands
[1] = inst
.operands
[2];
13743 inst
.operands
[2] = inst
.operands
[0];
13748 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13750 if (inst
.operands
[2].isreg
)
13753 neon_exchange_operands ();
13754 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13758 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13759 struct neon_type_el et
= neon_check_type (2, rs
,
13760 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13762 NEON_ENCODE (IMMED
, inst
);
13763 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13764 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13765 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13766 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13767 inst
.instruction
|= neon_quad (rs
) << 6;
13768 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13769 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13771 neon_dp_fixup (&inst
);
13778 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13782 do_neon_cmp_inv (void)
13784 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13790 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13793 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13794 scalars, which are encoded in 5 bits, M : Rm.
13795 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13796 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13800 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13802 unsigned regno
= NEON_SCALAR_REG (scalar
);
13803 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13808 if (regno
> 7 || elno
> 3)
13810 return regno
| (elno
<< 3);
13813 if (regno
> 15 || elno
> 1)
13815 return regno
| (elno
<< 4);
13819 first_error (_("scalar out of range for multiply instruction"));
13825 /* Encode multiply / multiply-accumulate scalar instructions. */
13828 neon_mul_mac (struct neon_type_el et
, int ubit
)
13832 /* Give a more helpful error message if we have an invalid type. */
13833 if (et
.type
== NT_invtype
)
13836 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13841 inst
.instruction
|= LOW4 (scalar
);
13842 inst
.instruction
|= HI1 (scalar
) << 5;
13843 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13844 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13845 inst
.instruction
|= (ubit
!= 0) << 24;
13847 neon_dp_fixup (&inst
);
13851 do_neon_mac_maybe_scalar (void)
13853 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13856 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13859 if (inst
.operands
[2].isscalar
)
13861 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13862 struct neon_type_el et
= neon_check_type (3, rs
,
13863 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13864 NEON_ENCODE (SCALAR
, inst
);
13865 neon_mul_mac (et
, neon_quad (rs
));
13869 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13870 affected if we specify unsigned args. */
13871 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13876 do_neon_fmac (void)
13878 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13881 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13884 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13890 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13891 struct neon_type_el et
= neon_check_type (3, rs
,
13892 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13893 neon_three_same (neon_quad (rs
), 0, et
.size
);
13896 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13897 same types as the MAC equivalents. The polynomial type for this instruction
13898 is encoded the same as the integer type. */
13903 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13906 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13909 if (inst
.operands
[2].isscalar
)
13910 do_neon_mac_maybe_scalar ();
13912 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13916 do_neon_qdmulh (void)
13918 if (inst
.operands
[2].isscalar
)
13920 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13921 struct neon_type_el et
= neon_check_type (3, rs
,
13922 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13923 NEON_ENCODE (SCALAR
, inst
);
13924 neon_mul_mac (et
, neon_quad (rs
));
13928 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13929 struct neon_type_el et
= neon_check_type (3, rs
,
13930 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13931 NEON_ENCODE (INTEGER
, inst
);
13932 /* The U bit (rounding) comes from bit mask. */
13933 neon_three_same (neon_quad (rs
), 0, et
.size
);
13938 do_neon_fcmp_absolute (void)
13940 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13941 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13942 /* Size field comes from bit mask. */
13943 neon_three_same (neon_quad (rs
), 1, -1);
13947 do_neon_fcmp_absolute_inv (void)
13949 neon_exchange_operands ();
13950 do_neon_fcmp_absolute ();
13954 do_neon_step (void)
13956 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13957 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13958 neon_three_same (neon_quad (rs
), 0, -1);
13962 do_neon_abs_neg (void)
13964 enum neon_shape rs
;
13965 struct neon_type_el et
;
13967 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13970 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13973 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13974 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13976 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13977 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13979 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13980 inst
.instruction
|= neon_quad (rs
) << 6;
13981 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13982 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13984 neon_dp_fixup (&inst
);
13990 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13991 struct neon_type_el et
= neon_check_type (2, rs
,
13992 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13993 int imm
= inst
.operands
[2].imm
;
13994 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13995 _("immediate out of range for insert"));
13996 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14002 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14003 struct neon_type_el et
= neon_check_type (2, rs
,
14004 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14005 int imm
= inst
.operands
[2].imm
;
14006 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14007 _("immediate out of range for insert"));
14008 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14012 do_neon_qshlu_imm (void)
14014 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14015 struct neon_type_el et
= neon_check_type (2, rs
,
14016 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14017 int imm
= inst
.operands
[2].imm
;
14018 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14019 _("immediate out of range for shift"));
14020 /* Only encodes the 'U present' variant of the instruction.
14021 In this case, signed types have OP (bit 8) set to 0.
14022 Unsigned types have OP set to 1. */
14023 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14024 /* The rest of the bits are the same as other immediate shifts. */
14025 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14029 do_neon_qmovn (void)
14031 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14032 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14033 /* Saturating move where operands can be signed or unsigned, and the
14034 destination has the same signedness. */
14035 NEON_ENCODE (INTEGER
, inst
);
14036 if (et
.type
== NT_unsigned
)
14037 inst
.instruction
|= 0xc0;
14039 inst
.instruction
|= 0x80;
14040 neon_two_same (0, 1, et
.size
/ 2);
14044 do_neon_qmovun (void)
14046 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14047 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14048 /* Saturating move with unsigned results. Operands must be signed. */
14049 NEON_ENCODE (INTEGER
, inst
);
14050 neon_two_same (0, 1, et
.size
/ 2);
14054 do_neon_rshift_sat_narrow (void)
14056 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14057 or unsigned. If operands are unsigned, results must also be unsigned. */
14058 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14059 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14060 int imm
= inst
.operands
[2].imm
;
14061 /* This gets the bounds check, size encoding and immediate bits calculation
14065 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14066 VQMOVN.I<size> <Dd>, <Qm>. */
14069 inst
.operands
[2].present
= 0;
14070 inst
.instruction
= N_MNEM_vqmovn
;
14075 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14076 _("immediate out of range"));
14077 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14081 do_neon_rshift_sat_narrow_u (void)
14083 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14084 or unsigned. If operands are unsigned, results must also be unsigned. */
14085 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14086 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14087 int imm
= inst
.operands
[2].imm
;
14088 /* This gets the bounds check, size encoding and immediate bits calculation
14092 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14093 VQMOVUN.I<size> <Dd>, <Qm>. */
14096 inst
.operands
[2].present
= 0;
14097 inst
.instruction
= N_MNEM_vqmovun
;
14102 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14103 _("immediate out of range"));
14104 /* FIXME: The manual is kind of unclear about what value U should have in
14105 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14107 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14111 do_neon_movn (void)
14113 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14114 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14115 NEON_ENCODE (INTEGER
, inst
);
14116 neon_two_same (0, 1, et
.size
/ 2);
14120 do_neon_rshift_narrow (void)
14122 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14123 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14124 int imm
= inst
.operands
[2].imm
;
14125 /* This gets the bounds check, size encoding and immediate bits calculation
14129 /* If immediate is zero then we are a pseudo-instruction for
14130 VMOVN.I<size> <Dd>, <Qm> */
14133 inst
.operands
[2].present
= 0;
14134 inst
.instruction
= N_MNEM_vmovn
;
14139 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14140 _("immediate out of range for narrowing operation"));
14141 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14145 do_neon_shll (void)
14147 /* FIXME: Type checking when lengthening. */
14148 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14149 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14150 unsigned imm
= inst
.operands
[2].imm
;
14152 if (imm
== et
.size
)
14154 /* Maximum shift variant. */
14155 NEON_ENCODE (INTEGER
, inst
);
14156 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14157 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14158 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14159 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14160 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14162 neon_dp_fixup (&inst
);
14166 /* A more-specific type check for non-max versions. */
14167 et
= neon_check_type (2, NS_QDI
,
14168 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14169 NEON_ENCODE (IMMED
, inst
);
14170 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14174 /* Check the various types for the VCVT instruction, and return which version
14175 the current instruction is. */
14178 neon_cvt_flavour (enum neon_shape rs
)
14180 #define CVT_VAR(C,X,Y) \
14181 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14182 if (et.type != NT_invtype) \
14184 inst.error = NULL; \
14187 struct neon_type_el et
;
14188 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14189 || rs
== NS_FF
) ? N_VFP
: 0;
14190 /* The instruction versions which take an immediate take one register
14191 argument, which is extended to the width of the full register. Thus the
14192 "source" and "destination" registers must have the same width. Hack that
14193 here by making the size equal to the key (wider, in this case) operand. */
14194 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14196 CVT_VAR (0, N_S32
, N_F32
);
14197 CVT_VAR (1, N_U32
, N_F32
);
14198 CVT_VAR (2, N_F32
, N_S32
);
14199 CVT_VAR (3, N_F32
, N_U32
);
14200 /* Half-precision conversions. */
14201 CVT_VAR (4, N_F32
, N_F16
);
14202 CVT_VAR (5, N_F16
, N_F32
);
14206 /* VFP instructions. */
14207 CVT_VAR (6, N_F32
, N_F64
);
14208 CVT_VAR (7, N_F64
, N_F32
);
14209 CVT_VAR (8, N_S32
, N_F64
| key
);
14210 CVT_VAR (9, N_U32
, N_F64
| key
);
14211 CVT_VAR (10, N_F64
| key
, N_S32
);
14212 CVT_VAR (11, N_F64
| key
, N_U32
);
14213 /* VFP instructions with bitshift. */
14214 CVT_VAR (12, N_F32
| key
, N_S16
);
14215 CVT_VAR (13, N_F32
| key
, N_U16
);
14216 CVT_VAR (14, N_F64
| key
, N_S16
);
14217 CVT_VAR (15, N_F64
| key
, N_U16
);
14218 CVT_VAR (16, N_S16
, N_F32
| key
);
14219 CVT_VAR (17, N_U16
, N_F32
| key
);
14220 CVT_VAR (18, N_S16
, N_F64
| key
);
14221 CVT_VAR (19, N_U16
, N_F64
| key
);
14227 /* Neon-syntax VFP conversions. */
14230 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14232 const char *opname
= 0;
14234 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14236 /* Conversions with immediate bitshift. */
14237 const char *enc
[] =
14261 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14263 opname
= enc
[flavour
];
14264 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14265 _("operands 0 and 1 must be the same register"));
14266 inst
.operands
[1] = inst
.operands
[2];
14267 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14272 /* Conversions without bitshift. */
14273 const char *enc
[] =
14289 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14290 opname
= enc
[flavour
];
14294 do_vfp_nsyn_opcode (opname
);
14298 do_vfp_nsyn_cvtz (void)
14300 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14301 int flavour
= neon_cvt_flavour (rs
);
14302 const char *enc
[] =
14316 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14317 do_vfp_nsyn_opcode (enc
[flavour
]);
14321 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14323 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14324 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14325 int flavour
= neon_cvt_flavour (rs
);
14327 /* PR11109: Handle round-to-zero for VCVT conversions. */
14329 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14330 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14331 && (rs
== NS_FD
|| rs
== NS_FF
))
14333 do_vfp_nsyn_cvtz ();
14337 /* VFP rather than Neon conversions. */
14340 do_vfp_nsyn_cvt (rs
, flavour
);
14350 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14352 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14355 /* Fixed-point conversion with #0 immediate is encoded as an
14356 integer conversion. */
14357 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14359 immbits
= 32 - inst
.operands
[2].imm
;
14360 NEON_ENCODE (IMMED
, inst
);
14362 inst
.instruction
|= enctab
[flavour
];
14363 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14364 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14365 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14366 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14367 inst
.instruction
|= neon_quad (rs
) << 6;
14368 inst
.instruction
|= 1 << 21;
14369 inst
.instruction
|= immbits
<< 16;
14371 neon_dp_fixup (&inst
);
14379 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14381 NEON_ENCODE (INTEGER
, inst
);
14383 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14387 inst
.instruction
|= enctab
[flavour
];
14389 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14390 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14391 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14392 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14393 inst
.instruction
|= neon_quad (rs
) << 6;
14394 inst
.instruction
|= 2 << 18;
14396 neon_dp_fixup (&inst
);
14400 /* Half-precision conversions for Advanced SIMD -- neon. */
14405 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14407 as_bad (_("operand size must match register width"));
14412 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14414 as_bad (_("operand size must match register width"));
14419 inst
.instruction
= 0x3b60600;
14421 inst
.instruction
= 0x3b60700;
14423 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14424 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14425 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14426 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14427 neon_dp_fixup (&inst
);
14431 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14432 do_vfp_nsyn_cvt (rs
, flavour
);
14437 do_neon_cvtr (void)
14439 do_neon_cvt_1 (FALSE
);
14445 do_neon_cvt_1 (TRUE
);
14449 do_neon_cvtb (void)
14451 inst
.instruction
= 0xeb20a40;
14453 /* The sizes are attached to the mnemonic. */
14454 if (inst
.vectype
.el
[0].type
!= NT_invtype
14455 && inst
.vectype
.el
[0].size
== 16)
14456 inst
.instruction
|= 0x00010000;
14458 /* Programmer's syntax: the sizes are attached to the operands. */
14459 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14460 && inst
.operands
[0].vectype
.size
== 16)
14461 inst
.instruction
|= 0x00010000;
14463 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14464 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14465 do_vfp_cond_or_thumb ();
14470 do_neon_cvtt (void)
14473 inst
.instruction
|= 0x80;
14477 neon_move_immediate (void)
14479 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14480 struct neon_type_el et
= neon_check_type (2, rs
,
14481 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14482 unsigned immlo
, immhi
= 0, immbits
;
14483 int op
, cmode
, float_p
;
14485 constraint (et
.type
== NT_invtype
,
14486 _("operand size must be specified for immediate VMOV"));
14488 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14489 op
= (inst
.instruction
& (1 << 5)) != 0;
14491 immlo
= inst
.operands
[1].imm
;
14492 if (inst
.operands
[1].regisimm
)
14493 immhi
= inst
.operands
[1].reg
;
14495 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14496 _("immediate has bits set outside the operand size"));
14498 float_p
= inst
.operands
[1].immisfloat
;
14500 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14501 et
.size
, et
.type
)) == FAIL
)
14503 /* Invert relevant bits only. */
14504 neon_invert_size (&immlo
, &immhi
, et
.size
);
14505 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14506 with one or the other; those cases are caught by
14507 neon_cmode_for_move_imm. */
14509 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14510 &op
, et
.size
, et
.type
)) == FAIL
)
14512 first_error (_("immediate out of range"));
14517 inst
.instruction
&= ~(1 << 5);
14518 inst
.instruction
|= op
<< 5;
14520 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14521 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14522 inst
.instruction
|= neon_quad (rs
) << 6;
14523 inst
.instruction
|= cmode
<< 8;
14525 neon_write_immbits (immbits
);
14531 if (inst
.operands
[1].isreg
)
14533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14535 NEON_ENCODE (INTEGER
, inst
);
14536 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14537 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14538 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14539 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14540 inst
.instruction
|= neon_quad (rs
) << 6;
14544 NEON_ENCODE (IMMED
, inst
);
14545 neon_move_immediate ();
14548 neon_dp_fixup (&inst
);
14551 /* Encode instructions of form:
14553 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14554 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14557 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14559 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14560 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14561 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14562 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14563 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14564 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14565 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14566 inst
.instruction
|= neon_logbits (size
) << 20;
14568 neon_dp_fixup (&inst
);
14572 do_neon_dyadic_long (void)
14574 /* FIXME: Type checking for lengthening op. */
14575 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14576 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14577 neon_mixed_length (et
, et
.size
);
14581 do_neon_abal (void)
14583 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14584 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14585 neon_mixed_length (et
, et
.size
);
14589 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14591 if (inst
.operands
[2].isscalar
)
14593 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14594 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14595 NEON_ENCODE (SCALAR
, inst
);
14596 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14600 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14601 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14602 NEON_ENCODE (INTEGER
, inst
);
14603 neon_mixed_length (et
, et
.size
);
14608 do_neon_mac_maybe_scalar_long (void)
14610 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14614 do_neon_dyadic_wide (void)
14616 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14617 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14618 neon_mixed_length (et
, et
.size
);
14622 do_neon_dyadic_narrow (void)
14624 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14625 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14626 /* Operand sign is unimportant, and the U bit is part of the opcode,
14627 so force the operand type to integer. */
14628 et
.type
= NT_integer
;
14629 neon_mixed_length (et
, et
.size
/ 2);
14633 do_neon_mul_sat_scalar_long (void)
14635 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14639 do_neon_vmull (void)
14641 if (inst
.operands
[2].isscalar
)
14642 do_neon_mac_maybe_scalar_long ();
14645 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14646 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14647 if (et
.type
== NT_poly
)
14648 NEON_ENCODE (POLY
, inst
);
14650 NEON_ENCODE (INTEGER
, inst
);
14651 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14652 zero. Should be OK as-is. */
14653 neon_mixed_length (et
, et
.size
);
14660 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14661 struct neon_type_el et
= neon_check_type (3, rs
,
14662 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14663 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14665 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14666 _("shift out of range"));
14667 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14668 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14669 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14670 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14671 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14672 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14673 inst
.instruction
|= neon_quad (rs
) << 6;
14674 inst
.instruction
|= imm
<< 8;
14676 neon_dp_fixup (&inst
);
14682 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14683 struct neon_type_el et
= neon_check_type (2, rs
,
14684 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14685 unsigned op
= (inst
.instruction
>> 7) & 3;
14686 /* N (width of reversed regions) is encoded as part of the bitmask. We
14687 extract it here to check the elements to be reversed are smaller.
14688 Otherwise we'd get a reserved instruction. */
14689 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14690 gas_assert (elsize
!= 0);
14691 constraint (et
.size
>= elsize
,
14692 _("elements must be smaller than reversal region"));
14693 neon_two_same (neon_quad (rs
), 1, et
.size
);
14699 if (inst
.operands
[1].isscalar
)
14701 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14702 struct neon_type_el et
= neon_check_type (2, rs
,
14703 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14704 unsigned sizebits
= et
.size
>> 3;
14705 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14706 int logsize
= neon_logbits (et
.size
);
14707 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14709 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14712 NEON_ENCODE (SCALAR
, inst
);
14713 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14714 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14715 inst
.instruction
|= LOW4 (dm
);
14716 inst
.instruction
|= HI1 (dm
) << 5;
14717 inst
.instruction
|= neon_quad (rs
) << 6;
14718 inst
.instruction
|= x
<< 17;
14719 inst
.instruction
|= sizebits
<< 16;
14721 neon_dp_fixup (&inst
);
14725 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14726 struct neon_type_el et
= neon_check_type (2, rs
,
14727 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14728 /* Duplicate ARM register to lanes of vector. */
14729 NEON_ENCODE (ARMREG
, inst
);
14732 case 8: inst
.instruction
|= 0x400000; break;
14733 case 16: inst
.instruction
|= 0x000020; break;
14734 case 32: inst
.instruction
|= 0x000000; break;
14737 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14740 inst
.instruction
|= neon_quad (rs
) << 21;
14741 /* The encoding for this instruction is identical for the ARM and Thumb
14742 variants, except for the condition field. */
14743 do_vfp_cond_or_thumb ();
14747 /* VMOV has particularly many variations. It can be one of:
14748 0. VMOV<c><q> <Qd>, <Qm>
14749 1. VMOV<c><q> <Dd>, <Dm>
14750 (Register operations, which are VORR with Rm = Rn.)
14751 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14752 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14754 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14755 (ARM register to scalar.)
14756 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14757 (Two ARM registers to vector.)
14758 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14759 (Scalar to ARM register.)
14760 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14761 (Vector to two ARM registers.)
14762 8. VMOV.F32 <Sd>, <Sm>
14763 9. VMOV.F64 <Dd>, <Dm>
14764 (VFP register moves.)
14765 10. VMOV.F32 <Sd>, #imm
14766 11. VMOV.F64 <Dd>, #imm
14767 (VFP float immediate load.)
14768 12. VMOV <Rd>, <Sm>
14769 (VFP single to ARM reg.)
14770 13. VMOV <Sd>, <Rm>
14771 (ARM reg to VFP single.)
14772 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14773 (Two ARM regs to two VFP singles.)
14774 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14775 (Two VFP singles to two ARM regs.)
14777 These cases can be disambiguated using neon_select_shape, except cases 1/9
14778 and 3/11 which depend on the operand type too.
14780 All the encoded bits are hardcoded by this function.
14782 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14783 Cases 5, 7 may be used with VFPv2 and above.
14785 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14786 can specify a type where it doesn't make sense to, and is ignored). */
14791 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14792 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14794 struct neon_type_el et
;
14795 const char *ldconst
= 0;
14799 case NS_DD
: /* case 1/9. */
14800 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14801 /* It is not an error here if no type is given. */
14803 if (et
.type
== NT_float
&& et
.size
== 64)
14805 do_vfp_nsyn_opcode ("fcpyd");
14808 /* fall through. */
14810 case NS_QQ
: /* case 0/1. */
14812 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14814 /* The architecture manual I have doesn't explicitly state which
14815 value the U bit should have for register->register moves, but
14816 the equivalent VORR instruction has U = 0, so do that. */
14817 inst
.instruction
= 0x0200110;
14818 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14819 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14820 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14821 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14822 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14823 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14824 inst
.instruction
|= neon_quad (rs
) << 6;
14826 neon_dp_fixup (&inst
);
14830 case NS_DI
: /* case 3/11. */
14831 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14833 if (et
.type
== NT_float
&& et
.size
== 64)
14835 /* case 11 (fconstd). */
14836 ldconst
= "fconstd";
14837 goto encode_fconstd
;
14839 /* fall through. */
14841 case NS_QI
: /* case 2/3. */
14842 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14844 inst
.instruction
= 0x0800010;
14845 neon_move_immediate ();
14846 neon_dp_fixup (&inst
);
14849 case NS_SR
: /* case 4. */
14851 unsigned bcdebits
= 0;
14853 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14854 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14856 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14857 logsize
= neon_logbits (et
.size
);
14859 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14862 && et
.size
!= 32, _(BAD_FPU
));
14863 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14864 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14868 case 8: bcdebits
= 0x8; break;
14869 case 16: bcdebits
= 0x1; break;
14870 case 32: bcdebits
= 0x0; break;
14874 bcdebits
|= x
<< logsize
;
14876 inst
.instruction
= 0xe000b10;
14877 do_vfp_cond_or_thumb ();
14878 inst
.instruction
|= LOW4 (dn
) << 16;
14879 inst
.instruction
|= HI1 (dn
) << 7;
14880 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14881 inst
.instruction
|= (bcdebits
& 3) << 5;
14882 inst
.instruction
|= (bcdebits
>> 2) << 21;
14886 case NS_DRR
: /* case 5 (fmdrr). */
14887 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14890 inst
.instruction
= 0xc400b10;
14891 do_vfp_cond_or_thumb ();
14892 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14893 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14894 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14895 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14898 case NS_RS
: /* case 6. */
14901 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14902 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14903 unsigned abcdebits
= 0;
14905 et
= neon_check_type (2, NS_NULL
,
14906 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14907 logsize
= neon_logbits (et
.size
);
14909 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14911 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14912 && et
.size
!= 32, _(BAD_FPU
));
14913 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14914 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14918 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14919 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14920 case 32: abcdebits
= 0x00; break;
14924 abcdebits
|= x
<< logsize
;
14925 inst
.instruction
= 0xe100b10;
14926 do_vfp_cond_or_thumb ();
14927 inst
.instruction
|= LOW4 (dn
) << 16;
14928 inst
.instruction
|= HI1 (dn
) << 7;
14929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14930 inst
.instruction
|= (abcdebits
& 3) << 5;
14931 inst
.instruction
|= (abcdebits
>> 2) << 21;
14935 case NS_RRD
: /* case 7 (fmrrd). */
14936 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14939 inst
.instruction
= 0xc500b10;
14940 do_vfp_cond_or_thumb ();
14941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14942 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14943 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14944 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14947 case NS_FF
: /* case 8 (fcpys). */
14948 do_vfp_nsyn_opcode ("fcpys");
14951 case NS_FI
: /* case 10 (fconsts). */
14952 ldconst
= "fconsts";
14954 if (is_quarter_float (inst
.operands
[1].imm
))
14956 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14957 do_vfp_nsyn_opcode (ldconst
);
14960 first_error (_("immediate out of range"));
14963 case NS_RF
: /* case 12 (fmrs). */
14964 do_vfp_nsyn_opcode ("fmrs");
14967 case NS_FR
: /* case 13 (fmsr). */
14968 do_vfp_nsyn_opcode ("fmsr");
14971 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14972 (one of which is a list), but we have parsed four. Do some fiddling to
14973 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14975 case NS_RRFF
: /* case 14 (fmrrs). */
14976 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14977 _("VFP registers must be adjacent"));
14978 inst
.operands
[2].imm
= 2;
14979 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14980 do_vfp_nsyn_opcode ("fmrrs");
14983 case NS_FFRR
: /* case 15 (fmsrr). */
14984 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14985 _("VFP registers must be adjacent"));
14986 inst
.operands
[1] = inst
.operands
[2];
14987 inst
.operands
[2] = inst
.operands
[3];
14988 inst
.operands
[0].imm
= 2;
14989 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14990 do_vfp_nsyn_opcode ("fmsrr");
14999 do_neon_rshift_round_imm (void)
15001 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15002 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15003 int imm
= inst
.operands
[2].imm
;
15005 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15008 inst
.operands
[2].present
= 0;
15013 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15014 _("immediate out of range for shift"));
15015 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15020 do_neon_movl (void)
15022 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15023 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15024 unsigned sizebits
= et
.size
>> 3;
15025 inst
.instruction
|= sizebits
<< 19;
15026 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15032 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15033 struct neon_type_el et
= neon_check_type (2, rs
,
15034 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15035 NEON_ENCODE (INTEGER
, inst
);
15036 neon_two_same (neon_quad (rs
), 1, et
.size
);
15040 do_neon_zip_uzp (void)
15042 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15043 struct neon_type_el et
= neon_check_type (2, rs
,
15044 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15045 if (rs
== NS_DD
&& et
.size
== 32)
15047 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15048 inst
.instruction
= N_MNEM_vtrn
;
15052 neon_two_same (neon_quad (rs
), 1, et
.size
);
15056 do_neon_sat_abs_neg (void)
15058 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15059 struct neon_type_el et
= neon_check_type (2, rs
,
15060 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15061 neon_two_same (neon_quad (rs
), 1, et
.size
);
15065 do_neon_pair_long (void)
15067 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15068 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15069 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15070 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15071 neon_two_same (neon_quad (rs
), 1, et
.size
);
15075 do_neon_recip_est (void)
15077 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15078 struct neon_type_el et
= neon_check_type (2, rs
,
15079 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15080 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15081 neon_two_same (neon_quad (rs
), 1, et
.size
);
15087 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15088 struct neon_type_el et
= neon_check_type (2, rs
,
15089 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15090 neon_two_same (neon_quad (rs
), 1, et
.size
);
15096 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15097 struct neon_type_el et
= neon_check_type (2, rs
,
15098 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15099 neon_two_same (neon_quad (rs
), 1, et
.size
);
15105 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15106 struct neon_type_el et
= neon_check_type (2, rs
,
15107 N_EQK
| N_INT
, N_8
| N_KEY
);
15108 neon_two_same (neon_quad (rs
), 1, et
.size
);
15114 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15115 neon_two_same (neon_quad (rs
), 1, -1);
15119 do_neon_tbl_tbx (void)
15121 unsigned listlenbits
;
15122 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15124 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15126 first_error (_("bad list length for table lookup"));
15130 listlenbits
= inst
.operands
[1].imm
- 1;
15131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15133 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15134 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15135 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15136 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15137 inst
.instruction
|= listlenbits
<< 8;
15139 neon_dp_fixup (&inst
);
15143 do_neon_ldm_stm (void)
15145 /* P, U and L bits are part of bitmask. */
15146 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15147 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15149 if (inst
.operands
[1].issingle
)
15151 do_vfp_nsyn_ldm_stm (is_dbmode
);
15155 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15156 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15158 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15159 _("register list must contain at least 1 and at most 16 "
15162 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15163 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15164 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15165 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15167 inst
.instruction
|= offsetbits
;
15169 do_vfp_cond_or_thumb ();
15173 do_neon_ldr_str (void)
15175 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15177 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15178 And is UNPREDICTABLE in thumb mode. */
15180 && inst
.operands
[1].reg
== REG_PC
15181 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15183 if (!thumb_mode
&& warn_on_deprecated
)
15184 as_warn (_("Use of PC here is deprecated"));
15186 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15189 if (inst
.operands
[0].issingle
)
15192 do_vfp_nsyn_opcode ("flds");
15194 do_vfp_nsyn_opcode ("fsts");
15199 do_vfp_nsyn_opcode ("fldd");
15201 do_vfp_nsyn_opcode ("fstd");
15205 /* "interleave" version also handles non-interleaving register VLD1/VST1
15209 do_neon_ld_st_interleave (void)
15211 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15212 N_8
| N_16
| N_32
| N_64
);
15213 unsigned alignbits
= 0;
15215 /* The bits in this table go:
15216 0: register stride of one (0) or two (1)
15217 1,2: register list length, minus one (1, 2, 3, 4).
15218 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15219 We use -1 for invalid entries. */
15220 const int typetable
[] =
15222 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15223 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15224 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15225 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15229 if (et
.type
== NT_invtype
)
15232 if (inst
.operands
[1].immisalign
)
15233 switch (inst
.operands
[1].imm
>> 8)
15235 case 64: alignbits
= 1; break;
15237 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15238 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15239 goto bad_alignment
;
15243 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15244 goto bad_alignment
;
15249 first_error (_("bad alignment"));
15253 inst
.instruction
|= alignbits
<< 4;
15254 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15256 /* Bits [4:6] of the immediate in a list specifier encode register stride
15257 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15258 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15259 up the right value for "type" in a table based on this value and the given
15260 list style, then stick it back. */
15261 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15262 | (((inst
.instruction
>> 8) & 3) << 3);
15264 typebits
= typetable
[idx
];
15266 constraint (typebits
== -1, _("bad list type for instruction"));
15268 inst
.instruction
&= ~0xf00;
15269 inst
.instruction
|= typebits
<< 8;
15272 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15273 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15274 otherwise. The variable arguments are a list of pairs of legal (size, align)
15275 values, terminated with -1. */
15278 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15281 int result
= FAIL
, thissize
, thisalign
;
15283 if (!inst
.operands
[1].immisalign
)
15289 va_start (ap
, do_align
);
15293 thissize
= va_arg (ap
, int);
15294 if (thissize
== -1)
15296 thisalign
= va_arg (ap
, int);
15298 if (size
== thissize
&& align
== thisalign
)
15301 while (result
!= SUCCESS
);
15305 if (result
== SUCCESS
)
15308 first_error (_("unsupported alignment for instruction"));
15314 do_neon_ld_st_lane (void)
15316 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15317 int align_good
, do_align
= 0;
15318 int logsize
= neon_logbits (et
.size
);
15319 int align
= inst
.operands
[1].imm
>> 8;
15320 int n
= (inst
.instruction
>> 8) & 3;
15321 int max_el
= 64 / et
.size
;
15323 if (et
.type
== NT_invtype
)
15326 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15327 _("bad list length"));
15328 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15329 _("scalar index out of range"));
15330 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15332 _("stride of 2 unavailable when element size is 8"));
15336 case 0: /* VLD1 / VST1. */
15337 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15339 if (align_good
== FAIL
)
15343 unsigned alignbits
= 0;
15346 case 16: alignbits
= 0x1; break;
15347 case 32: alignbits
= 0x3; break;
15350 inst
.instruction
|= alignbits
<< 4;
15354 case 1: /* VLD2 / VST2. */
15355 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15357 if (align_good
== FAIL
)
15360 inst
.instruction
|= 1 << 4;
15363 case 2: /* VLD3 / VST3. */
15364 constraint (inst
.operands
[1].immisalign
,
15365 _("can't use alignment with this instruction"));
15368 case 3: /* VLD4 / VST4. */
15369 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15370 16, 64, 32, 64, 32, 128, -1);
15371 if (align_good
== FAIL
)
15375 unsigned alignbits
= 0;
15378 case 8: alignbits
= 0x1; break;
15379 case 16: alignbits
= 0x1; break;
15380 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15383 inst
.instruction
|= alignbits
<< 4;
15390 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15391 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15392 inst
.instruction
|= 1 << (4 + logsize
);
15394 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15395 inst
.instruction
|= logsize
<< 10;
15398 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15401 do_neon_ld_dup (void)
15403 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15404 int align_good
, do_align
= 0;
15406 if (et
.type
== NT_invtype
)
15409 switch ((inst
.instruction
>> 8) & 3)
15411 case 0: /* VLD1. */
15412 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15413 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15414 &do_align
, 16, 16, 32, 32, -1);
15415 if (align_good
== FAIL
)
15417 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15420 case 2: inst
.instruction
|= 1 << 5; break;
15421 default: first_error (_("bad list length")); return;
15423 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15426 case 1: /* VLD2. */
15427 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15428 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15429 if (align_good
== FAIL
)
15431 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15432 _("bad list length"));
15433 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15434 inst
.instruction
|= 1 << 5;
15435 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15438 case 2: /* VLD3. */
15439 constraint (inst
.operands
[1].immisalign
,
15440 _("can't use alignment with this instruction"));
15441 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15442 _("bad list length"));
15443 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15444 inst
.instruction
|= 1 << 5;
15445 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15448 case 3: /* VLD4. */
15450 int align
= inst
.operands
[1].imm
>> 8;
15451 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15452 16, 64, 32, 64, 32, 128, -1);
15453 if (align_good
== FAIL
)
15455 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15456 _("bad list length"));
15457 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15458 inst
.instruction
|= 1 << 5;
15459 if (et
.size
== 32 && align
== 128)
15460 inst
.instruction
|= 0x3 << 6;
15462 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15469 inst
.instruction
|= do_align
<< 4;
15472 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15473 apart from bits [11:4]. */
15476 do_neon_ldx_stx (void)
15478 if (inst
.operands
[1].isreg
)
15479 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15481 switch (NEON_LANE (inst
.operands
[0].imm
))
15483 case NEON_INTERLEAVE_LANES
:
15484 NEON_ENCODE (INTERLV
, inst
);
15485 do_neon_ld_st_interleave ();
15488 case NEON_ALL_LANES
:
15489 NEON_ENCODE (DUP
, inst
);
15494 NEON_ENCODE (LANE
, inst
);
15495 do_neon_ld_st_lane ();
15498 /* L bit comes from bit mask. */
15499 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15500 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15501 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15503 if (inst
.operands
[1].postind
)
15505 int postreg
= inst
.operands
[1].imm
& 0xf;
15506 constraint (!inst
.operands
[1].immisreg
,
15507 _("post-index must be a register"));
15508 constraint (postreg
== 0xd || postreg
== 0xf,
15509 _("bad register for post-index"));
15510 inst
.instruction
|= postreg
;
15512 else if (inst
.operands
[1].writeback
)
15514 inst
.instruction
|= 0xd;
15517 inst
.instruction
|= 0xf;
15520 inst
.instruction
|= 0xf9000000;
15522 inst
.instruction
|= 0xf4000000;
15525 /* Overall per-instruction processing. */
15527 /* We need to be able to fix up arbitrary expressions in some statements.
15528 This is so that we can handle symbols that are an arbitrary distance from
15529 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15530 which returns part of an address in a form which will be valid for
15531 a data instruction. We do this by pushing the expression into a symbol
15532 in the expr_section, and creating a fix for that. */
15535 fix_new_arm (fragS
* frag
,
15549 /* Create an absolute valued symbol, so we have something to
15550 refer to in the object file. Unfortunately for us, gas's
15551 generic expression parsing will already have folded out
15552 any use of .set foo/.type foo %function that may have
15553 been used to set type information of the target location,
15554 that's being specified symbolically. We have to presume
15555 the user knows what they are doing. */
15559 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15561 symbol
= symbol_find_or_make (name
);
15562 S_SET_SEGMENT (symbol
, absolute_section
);
15563 symbol_set_frag (symbol
, &zero_address_frag
);
15564 S_SET_VALUE (symbol
, exp
->X_add_number
);
15565 exp
->X_op
= O_symbol
;
15566 exp
->X_add_symbol
= symbol
;
15567 exp
->X_add_number
= 0;
15573 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15574 (enum bfd_reloc_code_real
) reloc
);
15578 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15579 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15583 /* Mark whether the fix is to a THUMB instruction, or an ARM
15585 new_fix
->tc_fix_data
= thumb_mode
;
15588 /* Create a frg for an instruction requiring relaxation. */
15590 output_relax_insn (void)
15596 /* The size of the instruction is unknown, so tie the debug info to the
15597 start of the instruction. */
15598 dwarf2_emit_insn (0);
15600 switch (inst
.reloc
.exp
.X_op
)
15603 sym
= inst
.reloc
.exp
.X_add_symbol
;
15604 offset
= inst
.reloc
.exp
.X_add_number
;
15608 offset
= inst
.reloc
.exp
.X_add_number
;
15611 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15615 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15616 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15617 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15620 /* Write a 32-bit thumb instruction to buf. */
15622 put_thumb32_insn (char * buf
, unsigned long insn
)
15624 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15625 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15629 output_inst (const char * str
)
15635 as_bad ("%s -- `%s'", inst
.error
, str
);
15640 output_relax_insn ();
15643 if (inst
.size
== 0)
15646 to
= frag_more (inst
.size
);
15647 /* PR 9814: Record the thumb mode into the current frag so that we know
15648 what type of NOP padding to use, if necessary. We override any previous
15649 setting so that if the mode has changed then the NOPS that we use will
15650 match the encoding of the last instruction in the frag. */
15651 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15653 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15655 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15656 put_thumb32_insn (to
, inst
.instruction
);
15658 else if (inst
.size
> INSN_SIZE
)
15660 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15661 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15662 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15665 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15667 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15668 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15669 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15672 dwarf2_emit_insn (inst
.size
);
15676 output_it_inst (int cond
, int mask
, char * to
)
15678 unsigned long instruction
= 0xbf00;
15681 instruction
|= mask
;
15682 instruction
|= cond
<< 4;
15686 to
= frag_more (2);
15688 dwarf2_emit_insn (2);
15692 md_number_to_chars (to
, instruction
, 2);
15697 /* Tag values used in struct asm_opcode's tag field. */
15700 OT_unconditional
, /* Instruction cannot be conditionalized.
15701 The ARM condition field is still 0xE. */
15702 OT_unconditionalF
, /* Instruction cannot be conditionalized
15703 and carries 0xF in its ARM condition field. */
15704 OT_csuffix
, /* Instruction takes a conditional suffix. */
15705 OT_csuffixF
, /* Some forms of the instruction take a conditional
15706 suffix, others place 0xF where the condition field
15708 OT_cinfix3
, /* Instruction takes a conditional infix,
15709 beginning at character index 3. (In
15710 unified mode, it becomes a suffix.) */
15711 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15712 tsts, cmps, cmns, and teqs. */
15713 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15714 character index 3, even in unified mode. Used for
15715 legacy instructions where suffix and infix forms
15716 may be ambiguous. */
15717 OT_csuf_or_in3
, /* Instruction takes either a conditional
15718 suffix or an infix at character index 3. */
15719 OT_odd_infix_unc
, /* This is the unconditional variant of an
15720 instruction that takes a conditional infix
15721 at an unusual position. In unified mode,
15722 this variant will accept a suffix. */
15723 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15724 are the conditional variants of instructions that
15725 take conditional infixes in unusual positions.
15726 The infix appears at character index
15727 (tag - OT_odd_infix_0). These are not accepted
15728 in unified mode. */
15731 /* Subroutine of md_assemble, responsible for looking up the primary
15732 opcode from the mnemonic the user wrote. STR points to the
15733 beginning of the mnemonic.
15735 This is not simply a hash table lookup, because of conditional
15736 variants. Most instructions have conditional variants, which are
15737 expressed with a _conditional affix_ to the mnemonic. If we were
15738 to encode each conditional variant as a literal string in the opcode
15739 table, it would have approximately 20,000 entries.
15741 Most mnemonics take this affix as a suffix, and in unified syntax,
15742 'most' is upgraded to 'all'. However, in the divided syntax, some
15743 instructions take the affix as an infix, notably the s-variants of
15744 the arithmetic instructions. Of those instructions, all but six
15745 have the infix appear after the third character of the mnemonic.
15747 Accordingly, the algorithm for looking up primary opcodes given
15750 1. Look up the identifier in the opcode table.
15751 If we find a match, go to step U.
15753 2. Look up the last two characters of the identifier in the
15754 conditions table. If we find a match, look up the first N-2
15755 characters of the identifier in the opcode table. If we
15756 find a match, go to step CE.
15758 3. Look up the fourth and fifth characters of the identifier in
15759 the conditions table. If we find a match, extract those
15760 characters from the identifier, and look up the remaining
15761 characters in the opcode table. If we find a match, go
15766 U. Examine the tag field of the opcode structure, in case this is
15767 one of the six instructions with its conditional infix in an
15768 unusual place. If it is, the tag tells us where to find the
15769 infix; look it up in the conditions table and set inst.cond
15770 accordingly. Otherwise, this is an unconditional instruction.
15771 Again set inst.cond accordingly. Return the opcode structure.
15773 CE. Examine the tag field to make sure this is an instruction that
15774 should receive a conditional suffix. If it is not, fail.
15775 Otherwise, set inst.cond from the suffix we already looked up,
15776 and return the opcode structure.
15778 CM. Examine the tag field to make sure this is an instruction that
15779 should receive a conditional infix after the third character.
15780 If it is not, fail. Otherwise, undo the edits to the current
15781 line of input and proceed as for case CE. */
15783 static const struct asm_opcode
*
15784 opcode_lookup (char **str
)
15788 const struct asm_opcode
*opcode
;
15789 const struct asm_cond
*cond
;
15792 /* Scan up to the end of the mnemonic, which must end in white space,
15793 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15794 for (base
= end
= *str
; *end
!= '\0'; end
++)
15795 if (*end
== ' ' || *end
== '.')
15801 /* Handle a possible width suffix and/or Neon type suffix. */
15806 /* The .w and .n suffixes are only valid if the unified syntax is in
15808 if (unified_syntax
&& end
[1] == 'w')
15810 else if (unified_syntax
&& end
[1] == 'n')
15815 inst
.vectype
.elems
= 0;
15817 *str
= end
+ offset
;
15819 if (end
[offset
] == '.')
15821 /* See if we have a Neon type suffix (possible in either unified or
15822 non-unified ARM syntax mode). */
15823 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15826 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15832 /* Look for unaffixed or special-case affixed mnemonic. */
15833 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15838 if (opcode
->tag
< OT_odd_infix_0
)
15840 inst
.cond
= COND_ALWAYS
;
15844 if (warn_on_deprecated
&& unified_syntax
)
15845 as_warn (_("conditional infixes are deprecated in unified syntax"));
15846 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15847 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15850 inst
.cond
= cond
->value
;
15854 /* Cannot have a conditional suffix on a mnemonic of less than two
15856 if (end
- base
< 3)
15859 /* Look for suffixed mnemonic. */
15861 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15862 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15864 if (opcode
&& cond
)
15867 switch (opcode
->tag
)
15869 case OT_cinfix3_legacy
:
15870 /* Ignore conditional suffixes matched on infix only mnemonics. */
15874 case OT_cinfix3_deprecated
:
15875 case OT_odd_infix_unc
:
15876 if (!unified_syntax
)
15878 /* else fall through */
15882 case OT_csuf_or_in3
:
15883 inst
.cond
= cond
->value
;
15886 case OT_unconditional
:
15887 case OT_unconditionalF
:
15889 inst
.cond
= cond
->value
;
15892 /* Delayed diagnostic. */
15893 inst
.error
= BAD_COND
;
15894 inst
.cond
= COND_ALWAYS
;
15903 /* Cannot have a usual-position infix on a mnemonic of less than
15904 six characters (five would be a suffix). */
15905 if (end
- base
< 6)
15908 /* Look for infixed mnemonic in the usual position. */
15910 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15914 memcpy (save
, affix
, 2);
15915 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15916 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15918 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15919 memcpy (affix
, save
, 2);
15922 && (opcode
->tag
== OT_cinfix3
15923 || opcode
->tag
== OT_cinfix3_deprecated
15924 || opcode
->tag
== OT_csuf_or_in3
15925 || opcode
->tag
== OT_cinfix3_legacy
))
15928 if (warn_on_deprecated
&& unified_syntax
15929 && (opcode
->tag
== OT_cinfix3
15930 || opcode
->tag
== OT_cinfix3_deprecated
))
15931 as_warn (_("conditional infixes are deprecated in unified syntax"));
15933 inst
.cond
= cond
->value
;
15940 /* This function generates an initial IT instruction, leaving its block
15941 virtually open for the new instructions. Eventually,
15942 the mask will be updated by now_it_add_mask () each time
15943 a new instruction needs to be included in the IT block.
15944 Finally, the block is closed with close_automatic_it_block ().
15945 The block closure can be requested either from md_assemble (),
15946 a tencode (), or due to a label hook. */
15949 new_automatic_it_block (int cond
)
15951 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15952 now_it
.mask
= 0x18;
15954 now_it
.block_length
= 1;
15955 mapping_state (MAP_THUMB
);
15956 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15959 /* Close an automatic IT block.
15960 See comments in new_automatic_it_block (). */
15963 close_automatic_it_block (void)
15965 now_it
.mask
= 0x10;
15966 now_it
.block_length
= 0;
15969 /* Update the mask of the current automatically-generated IT
15970 instruction. See comments in new_automatic_it_block (). */
15973 now_it_add_mask (int cond
)
15975 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15976 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15977 | ((bitvalue) << (nbit)))
15978 const int resulting_bit
= (cond
& 1);
15980 now_it
.mask
&= 0xf;
15981 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15983 (5 - now_it
.block_length
));
15984 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15986 ((5 - now_it
.block_length
) - 1) );
15987 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15990 #undef SET_BIT_VALUE
15993 /* The IT blocks handling machinery is accessed through the these functions:
15994 it_fsm_pre_encode () from md_assemble ()
15995 set_it_insn_type () optional, from the tencode functions
15996 set_it_insn_type_last () ditto
15997 in_it_block () ditto
15998 it_fsm_post_encode () from md_assemble ()
15999 force_automatic_it_block_close () from label habdling functions
16002 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16003 initializing the IT insn type with a generic initial value depending
16004 on the inst.condition.
16005 2) During the tencode function, two things may happen:
16006 a) The tencode function overrides the IT insn type by
16007 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16008 b) The tencode function queries the IT block state by
16009 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16011 Both set_it_insn_type and in_it_block run the internal FSM state
16012 handling function (handle_it_state), because: a) setting the IT insn
16013 type may incur in an invalid state (exiting the function),
16014 and b) querying the state requires the FSM to be updated.
16015 Specifically we want to avoid creating an IT block for conditional
16016 branches, so it_fsm_pre_encode is actually a guess and we can't
16017 determine whether an IT block is required until the tencode () routine
16018 has decided what type of instruction this actually it.
16019 Because of this, if set_it_insn_type and in_it_block have to be used,
16020 set_it_insn_type has to be called first.
16022 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16023 determines the insn IT type depending on the inst.cond code.
16024 When a tencode () routine encodes an instruction that can be
16025 either outside an IT block, or, in the case of being inside, has to be
16026 the last one, set_it_insn_type_last () will determine the proper
16027 IT instruction type based on the inst.cond code. Otherwise,
16028 set_it_insn_type can be called for overriding that logic or
16029 for covering other cases.
16031 Calling handle_it_state () may not transition the IT block state to
16032 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16033 still queried. Instead, if the FSM determines that the state should
16034 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16035 after the tencode () function: that's what it_fsm_post_encode () does.
16037 Since in_it_block () calls the state handling function to get an
16038 updated state, an error may occur (due to invalid insns combination).
16039 In that case, inst.error is set.
16040 Therefore, inst.error has to be checked after the execution of
16041 the tencode () routine.
16043 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16044 any pending state change (if any) that didn't take place in
16045 handle_it_state () as explained above. */
16048 it_fsm_pre_encode (void)
16050 if (inst
.cond
!= COND_ALWAYS
)
16051 inst
.it_insn_type
= INSIDE_IT_INSN
;
16053 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16055 now_it
.state_handled
= 0;
16058 /* IT state FSM handling function. */
16061 handle_it_state (void)
16063 now_it
.state_handled
= 1;
16065 switch (now_it
.state
)
16067 case OUTSIDE_IT_BLOCK
:
16068 switch (inst
.it_insn_type
)
16070 case OUTSIDE_IT_INSN
:
16073 case INSIDE_IT_INSN
:
16074 case INSIDE_IT_LAST_INSN
:
16075 if (thumb_mode
== 0)
16078 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16079 as_tsktsk (_("Warning: conditional outside an IT block"\
16084 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16085 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16087 /* Automatically generate the IT instruction. */
16088 new_automatic_it_block (inst
.cond
);
16089 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16090 close_automatic_it_block ();
16094 inst
.error
= BAD_OUT_IT
;
16100 case IF_INSIDE_IT_LAST_INSN
:
16101 case NEUTRAL_IT_INSN
:
16105 now_it
.state
= MANUAL_IT_BLOCK
;
16106 now_it
.block_length
= 0;
16111 case AUTOMATIC_IT_BLOCK
:
16112 /* Three things may happen now:
16113 a) We should increment current it block size;
16114 b) We should close current it block (closing insn or 4 insns);
16115 c) We should close current it block and start a new one (due
16116 to incompatible conditions or
16117 4 insns-length block reached). */
16119 switch (inst
.it_insn_type
)
16121 case OUTSIDE_IT_INSN
:
16122 /* The closure of the block shall happen immediatelly,
16123 so any in_it_block () call reports the block as closed. */
16124 force_automatic_it_block_close ();
16127 case INSIDE_IT_INSN
:
16128 case INSIDE_IT_LAST_INSN
:
16129 case IF_INSIDE_IT_LAST_INSN
:
16130 now_it
.block_length
++;
16132 if (now_it
.block_length
> 4
16133 || !now_it_compatible (inst
.cond
))
16135 force_automatic_it_block_close ();
16136 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16137 new_automatic_it_block (inst
.cond
);
16141 now_it_add_mask (inst
.cond
);
16144 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16145 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16146 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16147 close_automatic_it_block ();
16150 case NEUTRAL_IT_INSN
:
16151 now_it
.block_length
++;
16153 if (now_it
.block_length
> 4)
16154 force_automatic_it_block_close ();
16156 now_it_add_mask (now_it
.cc
& 1);
16160 close_automatic_it_block ();
16161 now_it
.state
= MANUAL_IT_BLOCK
;
16166 case MANUAL_IT_BLOCK
:
16168 /* Check conditional suffixes. */
16169 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16172 now_it
.mask
&= 0x1f;
16173 is_last
= (now_it
.mask
== 0x10);
16175 switch (inst
.it_insn_type
)
16177 case OUTSIDE_IT_INSN
:
16178 inst
.error
= BAD_NOT_IT
;
16181 case INSIDE_IT_INSN
:
16182 if (cond
!= inst
.cond
)
16184 inst
.error
= BAD_IT_COND
;
16189 case INSIDE_IT_LAST_INSN
:
16190 case IF_INSIDE_IT_LAST_INSN
:
16191 if (cond
!= inst
.cond
)
16193 inst
.error
= BAD_IT_COND
;
16198 inst
.error
= BAD_BRANCH
;
16203 case NEUTRAL_IT_INSN
:
16204 /* The BKPT instruction is unconditional even in an IT block. */
16208 inst
.error
= BAD_IT_IT
;
16219 it_fsm_post_encode (void)
16223 if (!now_it
.state_handled
)
16224 handle_it_state ();
16226 is_last
= (now_it
.mask
== 0x10);
16229 now_it
.state
= OUTSIDE_IT_BLOCK
;
16235 force_automatic_it_block_close (void)
16237 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16239 close_automatic_it_block ();
16240 now_it
.state
= OUTSIDE_IT_BLOCK
;
16248 if (!now_it
.state_handled
)
16249 handle_it_state ();
16251 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16255 md_assemble (char *str
)
16258 const struct asm_opcode
* opcode
;
16260 /* Align the previous label if needed. */
16261 if (last_label_seen
!= NULL
)
16263 symbol_set_frag (last_label_seen
, frag_now
);
16264 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16265 S_SET_SEGMENT (last_label_seen
, now_seg
);
16268 memset (&inst
, '\0', sizeof (inst
));
16269 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16271 opcode
= opcode_lookup (&p
);
16274 /* It wasn't an instruction, but it might be a register alias of
16275 the form alias .req reg, or a Neon .dn/.qn directive. */
16276 if (! create_register_alias (str
, p
)
16277 && ! create_neon_reg_alias (str
, p
))
16278 as_bad (_("bad instruction `%s'"), str
);
16283 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16284 as_warn (_("s suffix on comparison instruction is deprecated"));
16286 /* The value which unconditional instructions should have in place of the
16287 condition field. */
16288 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16292 arm_feature_set variant
;
16294 variant
= cpu_variant
;
16295 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16296 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16297 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16298 /* Check that this instruction is supported for this CPU. */
16299 if (!opcode
->tvariant
16300 || (thumb_mode
== 1
16301 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16303 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16306 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16307 && opcode
->tencode
!= do_t_branch
)
16309 as_bad (_("Thumb does not support conditional execution"));
16313 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16315 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16316 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16317 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16319 /* Two things are addressed here.
16320 1) Implicit require narrow instructions on Thumb-1.
16321 This avoids relaxation accidentally introducing Thumb-2
16323 2) Reject wide instructions in non Thumb-2 cores. */
16324 if (inst
.size_req
== 0)
16326 else if (inst
.size_req
== 4)
16328 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16334 inst
.instruction
= opcode
->tvalue
;
16336 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16338 /* Prepare the it_insn_type for those encodings that don't set
16340 it_fsm_pre_encode ();
16342 opcode
->tencode ();
16344 it_fsm_post_encode ();
16347 if (!(inst
.error
|| inst
.relax
))
16349 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16350 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16351 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16353 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16358 /* Something has gone badly wrong if we try to relax a fixed size
16360 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16362 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16363 *opcode
->tvariant
);
16364 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16365 set those bits when Thumb-2 32-bit instructions are seen. ie.
16366 anything other than bl/blx and v6-M instructions.
16367 This is overly pessimistic for relaxable instructions. */
16368 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16370 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16371 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16372 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16375 check_neon_suffixes
;
16379 mapping_state (MAP_THUMB
);
16382 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16386 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16387 is_bx
= (opcode
->aencode
== do_bx
);
16389 /* Check that this instruction is supported for this CPU. */
16390 if (!(is_bx
&& fix_v4bx
)
16391 && !(opcode
->avariant
&&
16392 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16394 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16399 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16403 inst
.instruction
= opcode
->avalue
;
16404 if (opcode
->tag
== OT_unconditionalF
)
16405 inst
.instruction
|= 0xF << 28;
16407 inst
.instruction
|= inst
.cond
<< 28;
16408 inst
.size
= INSN_SIZE
;
16409 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16411 it_fsm_pre_encode ();
16412 opcode
->aencode ();
16413 it_fsm_post_encode ();
16415 /* Arm mode bx is marked as both v4T and v5 because it's still required
16416 on a hypothetical non-thumb v5 core. */
16418 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16420 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16421 *opcode
->avariant
);
16423 check_neon_suffixes
;
16427 mapping_state (MAP_ARM
);
16432 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16440 check_it_blocks_finished (void)
16445 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16446 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16447 == MANUAL_IT_BLOCK
)
16449 as_warn (_("section '%s' finished with an open IT block."),
16453 if (now_it
.state
== MANUAL_IT_BLOCK
)
16454 as_warn (_("file finished with an open IT block."));
16458 /* Various frobbings of labels and their addresses. */
16461 arm_start_line_hook (void)
16463 last_label_seen
= NULL
;
16467 arm_frob_label (symbolS
* sym
)
16469 last_label_seen
= sym
;
16471 ARM_SET_THUMB (sym
, thumb_mode
);
16473 #if defined OBJ_COFF || defined OBJ_ELF
16474 ARM_SET_INTERWORK (sym
, support_interwork
);
16477 force_automatic_it_block_close ();
16479 /* Note - do not allow local symbols (.Lxxx) to be labelled
16480 as Thumb functions. This is because these labels, whilst
16481 they exist inside Thumb code, are not the entry points for
16482 possible ARM->Thumb calls. Also, these labels can be used
16483 as part of a computed goto or switch statement. eg gcc
16484 can generate code that looks like this:
16486 ldr r2, [pc, .Laaa]
16496 The first instruction loads the address of the jump table.
16497 The second instruction converts a table index into a byte offset.
16498 The third instruction gets the jump address out of the table.
16499 The fourth instruction performs the jump.
16501 If the address stored at .Laaa is that of a symbol which has the
16502 Thumb_Func bit set, then the linker will arrange for this address
16503 to have the bottom bit set, which in turn would mean that the
16504 address computation performed by the third instruction would end
16505 up with the bottom bit set. Since the ARM is capable of unaligned
16506 word loads, the instruction would then load the incorrect address
16507 out of the jump table, and chaos would ensue. */
16508 if (label_is_thumb_function_name
16509 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16510 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16512 /* When the address of a Thumb function is taken the bottom
16513 bit of that address should be set. This will allow
16514 interworking between Arm and Thumb functions to work
16517 THUMB_SET_FUNC (sym
, 1);
16519 label_is_thumb_function_name
= FALSE
;
16522 dwarf2_emit_label (sym
);
16526 arm_data_in_code (void)
16528 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16530 *input_line_pointer
= '/';
16531 input_line_pointer
+= 5;
16532 *input_line_pointer
= 0;
16540 arm_canonicalize_symbol_name (char * name
)
16544 if (thumb_mode
&& (len
= strlen (name
)) > 5
16545 && streq (name
+ len
- 5, "/data"))
16546 *(name
+ len
- 5) = 0;
16551 /* Table of all register names defined by default. The user can
16552 define additional names with .req. Note that all register names
16553 should appear in both upper and lowercase variants. Some registers
16554 also have mixed-case names. */
16556 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16557 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16558 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16559 #define REGSET(p,t) \
16560 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16561 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16562 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16563 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16564 #define REGSETH(p,t) \
16565 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16566 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16567 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16568 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16569 #define REGSET2(p,t) \
16570 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16571 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16572 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16573 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16574 #define SPLRBANK(base,bank,t) \
16575 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16576 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16577 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16578 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16579 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16580 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16582 static const struct reg_entry reg_names
[] =
16584 /* ARM integer registers. */
16585 REGSET(r
, RN
), REGSET(R
, RN
),
16587 /* ATPCS synonyms. */
16588 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16589 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16590 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16592 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16593 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16594 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16596 /* Well-known aliases. */
16597 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16598 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16600 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16601 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16603 /* Coprocessor numbers. */
16604 REGSET(p
, CP
), REGSET(P
, CP
),
16606 /* Coprocessor register numbers. The "cr" variants are for backward
16608 REGSET(c
, CN
), REGSET(C
, CN
),
16609 REGSET(cr
, CN
), REGSET(CR
, CN
),
16611 /* ARM banked registers. */
16612 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16613 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16614 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16615 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16616 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16617 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16618 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16620 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16621 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16622 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16623 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16624 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16625 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16626 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16627 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16629 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16630 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16631 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16632 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16633 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16634 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16635 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16636 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16637 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16639 /* FPA registers. */
16640 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16641 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16643 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16644 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16646 /* VFP SP registers. */
16647 REGSET(s
,VFS
), REGSET(S
,VFS
),
16648 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16650 /* VFP DP Registers. */
16651 REGSET(d
,VFD
), REGSET(D
,VFD
),
16652 /* Extra Neon DP registers. */
16653 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16655 /* Neon QP registers. */
16656 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16658 /* VFP control registers. */
16659 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16660 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16661 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16662 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16663 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16664 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16666 /* Maverick DSP coprocessor registers. */
16667 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16668 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16670 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16671 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16672 REGDEF(dspsc
,0,DSPSC
),
16674 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16675 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16676 REGDEF(DSPSC
,0,DSPSC
),
16678 /* iWMMXt data registers - p0, c0-15. */
16679 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16681 /* iWMMXt control registers - p1, c0-3. */
16682 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16683 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16684 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16685 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16687 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16688 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16689 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16690 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16691 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16693 /* XScale accumulator registers. */
16694 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16700 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16701 within psr_required_here. */
16702 static const struct asm_psr psrs
[] =
16704 /* Backward compatibility notation. Note that "all" is no longer
16705 truly all possible PSR bits. */
16706 {"all", PSR_c
| PSR_f
},
16710 /* Individual flags. */
16716 /* Combinations of flags. */
16717 {"fs", PSR_f
| PSR_s
},
16718 {"fx", PSR_f
| PSR_x
},
16719 {"fc", PSR_f
| PSR_c
},
16720 {"sf", PSR_s
| PSR_f
},
16721 {"sx", PSR_s
| PSR_x
},
16722 {"sc", PSR_s
| PSR_c
},
16723 {"xf", PSR_x
| PSR_f
},
16724 {"xs", PSR_x
| PSR_s
},
16725 {"xc", PSR_x
| PSR_c
},
16726 {"cf", PSR_c
| PSR_f
},
16727 {"cs", PSR_c
| PSR_s
},
16728 {"cx", PSR_c
| PSR_x
},
16729 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16730 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16731 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16732 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16733 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16734 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16735 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16736 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16737 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16738 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16739 {"scf", PSR_s
| PSR_c
| PSR_f
},
16740 {"scx", PSR_s
| PSR_c
| PSR_x
},
16741 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16742 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16743 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16744 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16745 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16746 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16747 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16748 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16749 {"csf", PSR_c
| PSR_s
| PSR_f
},
16750 {"csx", PSR_c
| PSR_s
| PSR_x
},
16751 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16752 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16753 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16754 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16755 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16756 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16757 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16758 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16759 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16760 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16761 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16762 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16763 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16764 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16765 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16766 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16767 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16768 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16769 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16770 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16771 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16772 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16773 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16774 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16775 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16776 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16779 /* Table of V7M psr names. */
16780 static const struct asm_psr v7m_psrs
[] =
16782 {"apsr", 0 }, {"APSR", 0 },
16783 {"iapsr", 1 }, {"IAPSR", 1 },
16784 {"eapsr", 2 }, {"EAPSR", 2 },
16785 {"psr", 3 }, {"PSR", 3 },
16786 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16787 {"ipsr", 5 }, {"IPSR", 5 },
16788 {"epsr", 6 }, {"EPSR", 6 },
16789 {"iepsr", 7 }, {"IEPSR", 7 },
16790 {"msp", 8 }, {"MSP", 8 },
16791 {"psp", 9 }, {"PSP", 9 },
16792 {"primask", 16}, {"PRIMASK", 16},
16793 {"basepri", 17}, {"BASEPRI", 17},
16794 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16795 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16796 {"faultmask", 19}, {"FAULTMASK", 19},
16797 {"control", 20}, {"CONTROL", 20}
16800 /* Table of all shift-in-operand names. */
16801 static const struct asm_shift_name shift_names
[] =
16803 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16804 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16805 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16806 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16807 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16808 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16811 /* Table of all explicit relocation names. */
16813 static struct reloc_entry reloc_names
[] =
16815 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16816 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16817 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16818 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16819 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16820 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16821 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16822 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16823 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16824 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16825 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16826 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16827 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16828 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16829 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16830 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16831 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16832 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16836 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16837 static const struct asm_cond conds
[] =
16841 {"cs", 0x2}, {"hs", 0x2},
16842 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16856 static struct asm_barrier_opt barrier_opt_names
[] =
16858 { "sy", 0xf }, { "SY", 0xf },
16859 { "un", 0x7 }, { "UN", 0x7 },
16860 { "st", 0xe }, { "ST", 0xe },
16861 { "unst", 0x6 }, { "UNST", 0x6 },
16862 { "ish", 0xb }, { "ISH", 0xb },
16863 { "sh", 0xb }, { "SH", 0xb },
16864 { "ishst", 0xa }, { "ISHST", 0xa },
16865 { "shst", 0xa }, { "SHST", 0xa },
16866 { "nsh", 0x7 }, { "NSH", 0x7 },
16867 { "nshst", 0x6 }, { "NSHST", 0x6 },
16868 { "osh", 0x3 }, { "OSH", 0x3 },
16869 { "oshst", 0x2 }, { "OSHST", 0x2 }
16872 /* Table of ARM-format instructions. */
16874 /* Macros for gluing together operand strings. N.B. In all cases
16875 other than OPS0, the trailing OP_stop comes from default
16876 zero-initialization of the unspecified elements of the array. */
16877 #define OPS0() { OP_stop, }
16878 #define OPS1(a) { OP_##a, }
16879 #define OPS2(a,b) { OP_##a,OP_##b, }
16880 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16881 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16882 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16883 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16885 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16886 This is useful when mixing operands for ARM and THUMB, i.e. using the
16887 MIX_ARM_THUMB_OPERANDS macro.
16888 In order to use these macros, prefix the number of operands with _
16890 #define OPS_1(a) { a, }
16891 #define OPS_2(a,b) { a,b, }
16892 #define OPS_3(a,b,c) { a,b,c, }
16893 #define OPS_4(a,b,c,d) { a,b,c,d, }
16894 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16895 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16897 /* These macros abstract out the exact format of the mnemonic table and
16898 save some repeated characters. */
16900 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16901 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16902 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16903 THUMB_VARIANT, do_##ae, do_##te }
16905 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16906 a T_MNEM_xyz enumerator. */
16907 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16908 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16909 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16910 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16912 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16913 infix after the third character. */
16914 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16915 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16916 THUMB_VARIANT, do_##ae, do_##te }
16917 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16918 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16919 THUMB_VARIANT, do_##ae, do_##te }
16920 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16921 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16922 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16923 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16924 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16925 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16926 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16927 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16929 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16930 appear in the condition table. */
16931 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16932 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16933 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16935 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16936 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16937 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16938 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16939 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16940 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16941 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16942 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16943 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16944 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16945 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16946 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16947 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16948 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16949 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16950 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16951 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16952 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16953 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16954 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16956 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16957 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16958 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16959 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16961 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16962 field is still 0xE. Many of the Thumb variants can be executed
16963 conditionally, so this is checked separately. */
16964 #define TUE(mnem, op, top, nops, ops, ae, te) \
16965 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16966 THUMB_VARIANT, do_##ae, do_##te }
16968 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16969 condition code field. */
16970 #define TUF(mnem, op, top, nops, ops, ae, te) \
16971 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16972 THUMB_VARIANT, do_##ae, do_##te }
16974 /* ARM-only variants of all the above. */
16975 #define CE(mnem, op, nops, ops, ae) \
16976 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16978 #define C3(mnem, op, nops, ops, ae) \
16979 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16981 /* Legacy mnemonics that always have conditional infix after the third
16983 #define CL(mnem, op, nops, ops, ae) \
16984 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16985 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16987 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16988 #define cCE(mnem, op, nops, ops, ae) \
16989 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16991 /* Legacy coprocessor instructions where conditional infix and conditional
16992 suffix are ambiguous. For consistency this includes all FPA instructions,
16993 not just the potentially ambiguous ones. */
16994 #define cCL(mnem, op, nops, ops, ae) \
16995 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16996 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16998 /* Coprocessor, takes either a suffix or a position-3 infix
16999 (for an FPA corner case). */
17000 #define C3E(mnem, op, nops, ops, ae) \
17001 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17002 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17004 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17005 { m1 #m2 m3, OPS##nops ops, \
17006 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17007 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17009 #define CM(m1, m2, op, nops, ops, ae) \
17010 xCM_ (m1, , m2, op, nops, ops, ae), \
17011 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17012 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17013 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17014 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17015 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17016 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17017 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17018 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17019 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17020 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17021 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17022 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17023 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17024 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17025 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17026 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17027 xCM_ (m1, le, m2, op, nops, ops, ae), \
17028 xCM_ (m1, al, m2, op, nops, ops, ae)
17030 #define UE(mnem, op, nops, ops, ae) \
17031 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17033 #define UF(mnem, op, nops, ops, ae) \
17034 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17036 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17037 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17038 use the same encoding function for each. */
17039 #define NUF(mnem, op, nops, ops, enc) \
17040 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17041 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17043 /* Neon data processing, version which indirects through neon_enc_tab for
17044 the various overloaded versions of opcodes. */
17045 #define nUF(mnem, op, nops, ops, enc) \
17046 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17047 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17049 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17051 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17052 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17053 THUMB_VARIANT, do_##enc, do_##enc }
17055 #define NCE(mnem, op, nops, ops, enc) \
17056 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17058 #define NCEF(mnem, op, nops, ops, enc) \
17059 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17061 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17062 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17063 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17064 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17066 #define nCE(mnem, op, nops, ops, enc) \
17067 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17069 #define nCEF(mnem, op, nops, ops, enc) \
17070 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17074 static const struct asm_opcode insns
[] =
17076 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17077 #define THUMB_VARIANT &arm_ext_v4t
17078 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17079 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17080 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17081 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17082 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17083 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17084 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17085 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17086 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17087 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17088 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17089 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17090 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17091 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17092 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17093 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17095 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17096 for setting PSR flag bits. They are obsolete in V6 and do not
17097 have Thumb equivalents. */
17098 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17099 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17100 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17101 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17102 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17103 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17104 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17105 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17106 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17108 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17109 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17110 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17111 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17113 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17114 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17115 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17117 OP_ADDRGLDR
),ldst
, t_ldst
),
17118 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17120 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17121 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17122 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17123 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17124 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17125 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17127 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17128 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17129 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17130 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17133 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17134 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17135 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17137 /* Thumb-compatibility pseudo ops. */
17138 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17139 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17140 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17141 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17142 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17143 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17144 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17145 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17146 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17147 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17148 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17149 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17151 /* These may simplify to neg. */
17152 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17153 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17155 #undef THUMB_VARIANT
17156 #define THUMB_VARIANT & arm_ext_v6
17158 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17160 /* V1 instructions with no Thumb analogue prior to V6T2. */
17161 #undef THUMB_VARIANT
17162 #define THUMB_VARIANT & arm_ext_v6t2
17164 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17165 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17166 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17168 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17169 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17170 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17171 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17173 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17174 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17176 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17177 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17179 /* V1 instructions with no Thumb analogue at all. */
17180 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17181 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17183 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17184 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17185 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17186 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17187 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17188 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17189 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17190 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17193 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17194 #undef THUMB_VARIANT
17195 #define THUMB_VARIANT & arm_ext_v4t
17197 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17198 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17200 #undef THUMB_VARIANT
17201 #define THUMB_VARIANT & arm_ext_v6t2
17203 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17204 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17206 /* Generic coprocessor instructions. */
17207 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17208 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17209 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17210 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17211 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17212 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17213 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17216 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17218 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17219 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17222 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17223 #undef THUMB_VARIANT
17224 #define THUMB_VARIANT & arm_ext_msr
17226 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17227 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17230 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17231 #undef THUMB_VARIANT
17232 #define THUMB_VARIANT & arm_ext_v6t2
17234 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17235 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17236 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17237 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17238 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17239 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17240 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17241 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17244 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17245 #undef THUMB_VARIANT
17246 #define THUMB_VARIANT & arm_ext_v4t
17248 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17249 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17250 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17251 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17252 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17253 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17256 #define ARM_VARIANT & arm_ext_v4t_5
17258 /* ARM Architecture 4T. */
17259 /* Note: bx (and blx) are required on V5, even if the processor does
17260 not support Thumb. */
17261 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17264 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17265 #undef THUMB_VARIANT
17266 #define THUMB_VARIANT & arm_ext_v5t
17268 /* Note: blx has 2 variants; the .value coded here is for
17269 BLX(2). Only this variant has conditional execution. */
17270 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17271 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17273 #undef THUMB_VARIANT
17274 #define THUMB_VARIANT & arm_ext_v6t2
17276 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17277 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17278 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17279 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17280 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17281 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17282 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17283 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17286 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17287 #undef THUMB_VARIANT
17288 #define THUMB_VARIANT &arm_ext_v5exp
17290 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17291 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17292 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17293 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17295 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17296 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17298 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17299 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17300 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17301 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17303 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17304 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17305 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17306 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17308 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17309 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17311 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17312 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17313 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17314 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17317 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17318 #undef THUMB_VARIANT
17319 #define THUMB_VARIANT &arm_ext_v6t2
17321 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17322 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17324 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17325 ADDRGLDRS
), ldrd
, t_ldstd
),
17327 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17328 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17331 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17333 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17336 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17337 #undef THUMB_VARIANT
17338 #define THUMB_VARIANT & arm_ext_v6
17340 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17341 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17342 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17343 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17344 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17345 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17346 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17347 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17348 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17349 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17351 #undef THUMB_VARIANT
17352 #define THUMB_VARIANT & arm_ext_v6t2
17354 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17355 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17357 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17358 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17360 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17361 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17363 /* ARM V6 not included in V7M. */
17364 #undef THUMB_VARIANT
17365 #define THUMB_VARIANT & arm_ext_v6_notm
17366 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17367 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17368 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17369 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17370 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17371 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17372 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17373 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17374 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17375 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17376 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17377 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17379 /* ARM V6 not included in V7M (eg. integer SIMD). */
17380 #undef THUMB_VARIANT
17381 #define THUMB_VARIANT & arm_ext_v6_dsp
17382 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17383 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17384 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17385 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17386 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17387 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17388 /* Old name for QASX. */
17389 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17390 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17391 /* Old name for QSAX. */
17392 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17393 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17394 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17395 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17396 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17397 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17398 /* Old name for SASX. */
17399 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17400 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17401 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17402 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17403 /* Old name for SHASX. */
17404 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17405 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17406 /* Old name for SHSAX. */
17407 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17408 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17409 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17410 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17411 /* Old name for SSAX. */
17412 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17413 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17414 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17415 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17416 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17417 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17418 /* Old name for UASX. */
17419 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17420 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17421 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17422 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17423 /* Old name for UHASX. */
17424 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17425 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17426 /* Old name for UHSAX. */
17427 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17428 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17429 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17430 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17431 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17432 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17433 /* Old name for UQASX. */
17434 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17435 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17436 /* Old name for UQSAX. */
17437 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17438 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17439 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17440 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17441 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17442 /* Old name for USAX. */
17443 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17444 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17445 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17446 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17447 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17448 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17449 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17450 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17451 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17452 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17453 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17454 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17455 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17456 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17457 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17458 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17459 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17460 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17461 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17462 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17463 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17464 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17465 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17466 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17467 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17468 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17469 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17470 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17471 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17472 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17473 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17474 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17475 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17476 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17479 #define ARM_VARIANT & arm_ext_v6k
17480 #undef THUMB_VARIANT
17481 #define THUMB_VARIANT & arm_ext_v6k
17483 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17484 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17485 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17486 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17488 #undef THUMB_VARIANT
17489 #define THUMB_VARIANT & arm_ext_v6_notm
17490 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17492 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17493 RRnpcb
), strexd
, t_strexd
),
17495 #undef THUMB_VARIANT
17496 #define THUMB_VARIANT & arm_ext_v6t2
17497 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17499 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17501 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17503 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17505 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17508 #define ARM_VARIANT & arm_ext_sec
17509 #undef THUMB_VARIANT
17510 #define THUMB_VARIANT & arm_ext_sec
17512 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17515 #define ARM_VARIANT & arm_ext_virt
17516 #undef THUMB_VARIANT
17517 #define THUMB_VARIANT & arm_ext_virt
17519 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17520 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17523 #define ARM_VARIANT & arm_ext_v6t2
17524 #undef THUMB_VARIANT
17525 #define THUMB_VARIANT & arm_ext_v6t2
17527 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17528 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17529 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17530 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17532 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17533 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17534 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17535 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17537 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17538 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17539 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17540 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17542 /* Thumb-only instructions. */
17544 #define ARM_VARIANT NULL
17545 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17546 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17548 /* ARM does not really have an IT instruction, so always allow it.
17549 The opcode is copied from Thumb in order to allow warnings in
17550 -mimplicit-it=[never | arm] modes. */
17552 #define ARM_VARIANT & arm_ext_v1
17554 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17555 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17556 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17557 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17558 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17559 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17560 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17561 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17562 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17563 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17564 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17565 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17566 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17567 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17568 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17569 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17570 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17571 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17573 /* Thumb2 only instructions. */
17575 #define ARM_VARIANT NULL
17577 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17578 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17579 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17580 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17581 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17582 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17584 /* Hardware division instructions. */
17586 #define ARM_VARIANT & arm_ext_adiv
17587 #undef THUMB_VARIANT
17588 #define THUMB_VARIANT & arm_ext_div
17590 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17591 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17593 /* ARM V6M/V7 instructions. */
17595 #define ARM_VARIANT & arm_ext_barrier
17596 #undef THUMB_VARIANT
17597 #define THUMB_VARIANT & arm_ext_barrier
17599 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17600 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17601 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17603 /* ARM V7 instructions. */
17605 #define ARM_VARIANT & arm_ext_v7
17606 #undef THUMB_VARIANT
17607 #define THUMB_VARIANT & arm_ext_v7
17609 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17610 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17613 #define ARM_VARIANT & arm_ext_mp
17614 #undef THUMB_VARIANT
17615 #define THUMB_VARIANT & arm_ext_mp
17617 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17620 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17622 cCE("wfs", e200110
, 1, (RR
), rd
),
17623 cCE("rfs", e300110
, 1, (RR
), rd
),
17624 cCE("wfc", e400110
, 1, (RR
), rd
),
17625 cCE("rfc", e500110
, 1, (RR
), rd
),
17627 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17628 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17629 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17630 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17632 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17633 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17634 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17635 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17637 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17641 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17645 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17646 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17650 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17654 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17658 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17659 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17663 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17667 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17671 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17672 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17676 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17680 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17684 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17685 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17686 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17687 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17689 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17690 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17691 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17692 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17693 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17694 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17695 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17696 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17697 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17698 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17699 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17700 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17702 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17703 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17704 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17705 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17706 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17710 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17711 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17713 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17715 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17716 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17717 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17718 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17719 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17720 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17721 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17722 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17723 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17724 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17725 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17726 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17728 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17729 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17730 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17731 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17732 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17733 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17734 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17735 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17736 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17737 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17738 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17739 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17741 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17742 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17743 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17744 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17745 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17746 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17747 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17748 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17749 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17750 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17751 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17752 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17754 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17755 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17756 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17757 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17758 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17759 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17760 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17761 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17762 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17763 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17764 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17765 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17767 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17768 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17769 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17770 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17771 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17772 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17773 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17774 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17775 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17776 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17777 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17778 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17780 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17781 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17782 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17783 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17784 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17785 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17786 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17787 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17788 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17789 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17790 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17791 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17793 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17794 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17795 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17796 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17797 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17798 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17799 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17800 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17801 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17802 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17803 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17804 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17806 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17807 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17808 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17809 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17810 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17811 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17812 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17813 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17814 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17815 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17816 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17817 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17819 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17820 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17821 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17822 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17823 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17824 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17825 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17826 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17827 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17828 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17829 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17830 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17832 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17833 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17834 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17835 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17836 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17837 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17838 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17839 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17840 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17841 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17842 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17843 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17845 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17849 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17853 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17854 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17855 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17856 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17858 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17859 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17860 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17861 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17862 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17863 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17864 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17865 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17866 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17867 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17868 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17869 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17871 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17872 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17873 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17874 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17875 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17876 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17877 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17878 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17879 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17880 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17881 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17882 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17884 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17885 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17886 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17887 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17888 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17889 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17890 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17891 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17892 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17893 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17894 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17895 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17897 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17898 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17899 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17900 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17901 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17902 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17903 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17904 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17905 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17906 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17907 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17908 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17910 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17911 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17912 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17913 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17914 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17915 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17916 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17917 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17918 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17919 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17920 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17921 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17923 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17924 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17925 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17926 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17927 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17928 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17929 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17930 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17931 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17932 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17933 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17934 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17936 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17937 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17938 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17939 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17940 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17941 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17942 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17943 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17944 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17945 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17946 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17947 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17949 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17950 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17951 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17952 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17953 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17954 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17955 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17956 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17957 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17958 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17959 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17960 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17962 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17963 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17964 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17965 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17966 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17967 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17968 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17969 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17970 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17971 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17972 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17973 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17975 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17976 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17977 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17978 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17979 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17980 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17981 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17982 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17983 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17984 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17985 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17986 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17988 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17989 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17990 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17991 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17992 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17993 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17994 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17995 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17996 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17997 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17998 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17999 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18001 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18002 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18003 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18004 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18005 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18006 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18007 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18008 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18009 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18010 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18011 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18012 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18014 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18015 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18016 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18017 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18019 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
18020 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
18021 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
18022 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
18023 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
18024 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
18025 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
18026 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
18027 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
18028 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
18029 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
18030 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
18032 /* The implementation of the FIX instruction is broken on some
18033 assemblers, in that it accepts a precision specifier as well as a
18034 rounding specifier, despite the fact that this is meaningless.
18035 To be more compatible, we accept it as well, though of course it
18036 does not set any bits. */
18037 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
18038 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
18039 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
18040 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
18041 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
18042 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18043 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18044 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18045 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18046 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18047 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18048 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18049 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18051 /* Instructions that were new with the real FPA, call them V2. */
18053 #define ARM_VARIANT & fpu_fpa_ext_v2
18055 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18056 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18057 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18058 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18059 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18060 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18063 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18065 /* Moves and type conversions. */
18066 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18067 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18068 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18069 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18070 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
18071 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
18072 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18073 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18074 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18075 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18076 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18077 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18078 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18079 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
18081 /* Memory operations. */
18082 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18083 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18084 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18085 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18086 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18087 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18088 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18089 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18090 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18091 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18092 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18093 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18094 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18095 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18096 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18097 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18098 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18099 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18101 /* Monadic operations. */
18102 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18103 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18104 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18106 /* Dyadic operations. */
18107 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18108 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18109 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18110 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18111 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18112 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18113 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18114 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18115 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18118 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18119 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18120 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18121 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18123 /* Double precision load/store are still present on single precision
18124 implementations. */
18125 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18126 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18127 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18128 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18129 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18130 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18131 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18132 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18133 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18134 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18137 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18139 /* Moves and type conversions. */
18140 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18141 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18142 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18143 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18144 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18145 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18146 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18147 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18148 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18149 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18150 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18151 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18152 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18154 /* Monadic operations. */
18155 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18156 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18157 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18159 /* Dyadic operations. */
18160 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18161 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18162 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18163 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18164 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18165 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18166 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18167 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18168 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18171 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18172 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18173 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18174 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18177 #define ARM_VARIANT & fpu_vfp_ext_v2
18179 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18180 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18181 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18182 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18184 /* Instructions which may belong to either the Neon or VFP instruction sets.
18185 Individual encoder functions perform additional architecture checks. */
18187 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18188 #undef THUMB_VARIANT
18189 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18191 /* These mnemonics are unique to VFP. */
18192 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18193 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18194 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18195 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18196 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18197 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18198 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18199 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18200 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18201 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18203 /* Mnemonics shared by Neon and VFP. */
18204 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18205 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18206 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18208 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18209 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18211 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18212 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18214 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18215 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18216 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18217 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18218 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18219 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18220 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18221 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18223 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
18224 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18225 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18226 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18229 /* NOTE: All VMOV encoding is special-cased! */
18230 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18231 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18233 #undef THUMB_VARIANT
18234 #define THUMB_VARIANT & fpu_neon_ext_v1
18236 #define ARM_VARIANT & fpu_neon_ext_v1
18238 /* Data processing with three registers of the same length. */
18239 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18240 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18241 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18242 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18243 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18244 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18245 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18246 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18247 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18248 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18249 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18250 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18251 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18252 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18253 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18254 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18255 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18256 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18257 /* If not immediate, fall back to neon_dyadic_i64_su.
18258 shl_imm should accept I8 I16 I32 I64,
18259 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18260 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18261 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18262 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18263 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18264 /* Logic ops, types optional & ignored. */
18265 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18266 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18267 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18268 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18269 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18270 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18271 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18272 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18273 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18274 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18275 /* Bitfield ops, untyped. */
18276 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18277 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18278 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18279 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18280 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18281 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18282 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18283 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18284 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18285 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18286 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18287 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18288 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18289 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18290 back to neon_dyadic_if_su. */
18291 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18292 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18293 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18294 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18295 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18296 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18297 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18298 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18299 /* Comparison. Type I8 I16 I32 F32. */
18300 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18301 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18302 /* As above, D registers only. */
18303 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18304 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18305 /* Int and float variants, signedness unimportant. */
18306 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18307 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18308 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18309 /* Add/sub take types I8 I16 I32 I64 F32. */
18310 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18311 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18312 /* vtst takes sizes 8, 16, 32. */
18313 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18314 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18315 /* VMUL takes I8 I16 I32 F32 P8. */
18316 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18317 /* VQD{R}MULH takes S16 S32. */
18318 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18319 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18320 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18321 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18322 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18323 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18324 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18325 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18326 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18327 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18328 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18329 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18330 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18331 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18332 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18333 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18335 /* Two address, int/float. Types S8 S16 S32 F32. */
18336 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18337 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18339 /* Data processing with two registers and a shift amount. */
18340 /* Right shifts, and variants with rounding.
18341 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18342 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18343 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18344 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18345 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18346 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18347 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18348 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18349 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18350 /* Shift and insert. Sizes accepted 8 16 32 64. */
18351 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18352 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18353 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18354 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18355 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18356 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18357 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18358 /* Right shift immediate, saturating & narrowing, with rounding variants.
18359 Types accepted S16 S32 S64 U16 U32 U64. */
18360 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18361 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18362 /* As above, unsigned. Types accepted S16 S32 S64. */
18363 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18364 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18365 /* Right shift narrowing. Types accepted I16 I32 I64. */
18366 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18367 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18368 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18369 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18370 /* CVT with optional immediate for fixed-point variant. */
18371 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18373 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18374 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18376 /* Data processing, three registers of different lengths. */
18377 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18378 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18379 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18380 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18381 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18382 /* If not scalar, fall back to neon_dyadic_long.
18383 Vector types as above, scalar types S16 S32 U16 U32. */
18384 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18385 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18386 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18387 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18388 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18389 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18390 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18391 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18392 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18393 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18394 /* Saturating doubling multiplies. Types S16 S32. */
18395 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18396 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18397 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18398 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18399 S16 S32 U16 U32. */
18400 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18402 /* Extract. Size 8. */
18403 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18404 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18406 /* Two registers, miscellaneous. */
18407 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18408 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18409 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18410 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18411 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18412 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18413 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18414 /* Vector replicate. Sizes 8 16 32. */
18415 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18416 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18417 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18418 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18419 /* VMOVN. Types I16 I32 I64. */
18420 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18421 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18422 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18423 /* VQMOVUN. Types S16 S32 S64. */
18424 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18425 /* VZIP / VUZP. Sizes 8 16 32. */
18426 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18427 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18428 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18429 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18430 /* VQABS / VQNEG. Types S8 S16 S32. */
18431 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18432 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18433 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18434 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18435 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18436 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18437 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18438 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18439 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18440 /* Reciprocal estimates. Types U32 F32. */
18441 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18442 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18443 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18444 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18445 /* VCLS. Types S8 S16 S32. */
18446 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18447 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18448 /* VCLZ. Types I8 I16 I32. */
18449 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18450 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18451 /* VCNT. Size 8. */
18452 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18453 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18454 /* Two address, untyped. */
18455 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18456 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18457 /* VTRN. Sizes 8 16 32. */
18458 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18459 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18461 /* Table lookup. Size 8. */
18462 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18463 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18465 #undef THUMB_VARIANT
18466 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18468 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18470 /* Neon element/structure load/store. */
18471 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18472 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18473 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18474 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18475 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18476 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18477 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18478 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18480 #undef THUMB_VARIANT
18481 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18483 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18484 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18485 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18486 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18487 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18488 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18489 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18490 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18491 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18492 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18494 #undef THUMB_VARIANT
18495 #define THUMB_VARIANT & fpu_vfp_ext_v3
18497 #define ARM_VARIANT & fpu_vfp_ext_v3
18499 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18500 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18501 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18502 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18503 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18504 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18505 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18506 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18507 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18510 #define ARM_VARIANT &fpu_vfp_ext_fma
18511 #undef THUMB_VARIANT
18512 #define THUMB_VARIANT &fpu_vfp_ext_fma
18513 /* Mnemonics shared by Neon and VFP. These are included in the
18514 VFP FMA variant; NEON and VFP FMA always includes the NEON
18515 FMA instructions. */
18516 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18517 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18518 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18519 the v form should always be used. */
18520 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18521 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18522 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18523 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18524 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18525 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18527 #undef THUMB_VARIANT
18529 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18531 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18532 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18533 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18534 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18535 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18536 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18537 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18538 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18541 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18543 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18544 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18545 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18546 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18547 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18548 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18549 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18550 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18551 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18552 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18553 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18554 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18555 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18556 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18557 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18558 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18559 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18560 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18561 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18562 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18563 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18564 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18565 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18566 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18567 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18568 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18569 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18570 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18571 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18572 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18573 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18574 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18575 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18576 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18577 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18578 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18579 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18580 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18581 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18582 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18583 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18585 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18586 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18587 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18588 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18589 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18590 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18591 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18592 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18597 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18598 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18599 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18600 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18601 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18602 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18603 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18604 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18605 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18606 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18607 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18609 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18610 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18611 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18612 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18613 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18614 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18615 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18616 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18617 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18618 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18619 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18620 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18621 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18622 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18623 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18624 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18625 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18626 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18627 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18628 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18629 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18630 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18631 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18632 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18633 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18634 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18635 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18636 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18637 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18638 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18639 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18640 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18641 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18642 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18643 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18644 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18645 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18646 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18647 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18648 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18649 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18650 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18651 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18652 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18653 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18654 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18655 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18656 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18657 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18658 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18659 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18660 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18661 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18662 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18663 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18664 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18665 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18666 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18667 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18668 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18669 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18670 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18671 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18672 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18673 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18674 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18675 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18676 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18677 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18678 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18679 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18680 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18681 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18682 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18683 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18684 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18685 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18686 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18687 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18688 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18689 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18690 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18691 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18692 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18693 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18694 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18695 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18696 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18697 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18698 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18699 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18700 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18701 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18702 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18703 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18704 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18707 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18709 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18710 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18711 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18712 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18713 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18714 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18715 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18716 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18717 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18718 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18719 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18720 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18721 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18722 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18723 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18724 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18725 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18726 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18727 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18728 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18729 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18730 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18731 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18732 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18733 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18734 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18735 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18736 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18737 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18738 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18739 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18740 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18741 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18742 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18743 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18744 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18745 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18746 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18747 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18748 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18749 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18750 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18751 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18752 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18753 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18754 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18755 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18756 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18757 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18758 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18759 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18760 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18761 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18762 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18763 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18764 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18765 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18768 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18770 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18771 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18772 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18773 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18774 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18775 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18776 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18777 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18778 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18779 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18780 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18781 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18782 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18783 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18784 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18785 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18786 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18787 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18788 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18789 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18790 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18791 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18792 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18793 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18794 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18795 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18796 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18797 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18798 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18799 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18800 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18801 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18802 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18803 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18804 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18805 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18806 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18807 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18808 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18809 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18810 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18811 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18812 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18813 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18814 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18815 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18816 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18817 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18818 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18819 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18820 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18821 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18822 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18823 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18824 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18825 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18826 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18827 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18828 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18829 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18830 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18831 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18832 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18833 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18834 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18835 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18836 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18837 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18838 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18839 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18840 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18841 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18842 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18843 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18844 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18845 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18848 #undef THUMB_VARIANT
18875 /* MD interface: bits in the object file. */
18877 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18878 for use in the a.out file, and stores them in the array pointed to by buf.
18879 This knows about the endian-ness of the target machine and does
18880 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18881 2 (short) and 4 (long) Floating numbers are put out as a series of
18882 LITTLENUMS (shorts, here at least). */
18885 md_number_to_chars (char * buf
, valueT val
, int n
)
18887 if (target_big_endian
)
18888 number_to_chars_bigendian (buf
, val
, n
);
18890 number_to_chars_littleendian (buf
, val
, n
);
18894 md_chars_to_number (char * buf
, int n
)
18897 unsigned char * where
= (unsigned char *) buf
;
18899 if (target_big_endian
)
18904 result
|= (*where
++ & 255);
18912 result
|= (where
[n
] & 255);
18919 /* MD interface: Sections. */
18921 /* Estimate the size of a frag before relaxing. Assume everything fits in
18925 md_estimate_size_before_relax (fragS
* fragp
,
18926 segT segtype ATTRIBUTE_UNUSED
)
18932 /* Convert a machine dependent frag. */
18935 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18937 unsigned long insn
;
18938 unsigned long old_op
;
18946 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18948 old_op
= bfd_get_16(abfd
, buf
);
18949 if (fragp
->fr_symbol
)
18951 exp
.X_op
= O_symbol
;
18952 exp
.X_add_symbol
= fragp
->fr_symbol
;
18956 exp
.X_op
= O_constant
;
18958 exp
.X_add_number
= fragp
->fr_offset
;
18959 opcode
= fragp
->fr_subtype
;
18962 case T_MNEM_ldr_pc
:
18963 case T_MNEM_ldr_pc2
:
18964 case T_MNEM_ldr_sp
:
18965 case T_MNEM_str_sp
:
18972 if (fragp
->fr_var
== 4)
18974 insn
= THUMB_OP32 (opcode
);
18975 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18977 insn
|= (old_op
& 0x700) << 4;
18981 insn
|= (old_op
& 7) << 12;
18982 insn
|= (old_op
& 0x38) << 13;
18984 insn
|= 0x00000c00;
18985 put_thumb32_insn (buf
, insn
);
18986 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18990 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18992 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18995 if (fragp
->fr_var
== 4)
18997 insn
= THUMB_OP32 (opcode
);
18998 insn
|= (old_op
& 0xf0) << 4;
18999 put_thumb32_insn (buf
, insn
);
19000 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
19004 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19005 exp
.X_add_number
-= 4;
19013 if (fragp
->fr_var
== 4)
19015 int r0off
= (opcode
== T_MNEM_mov
19016 || opcode
== T_MNEM_movs
) ? 0 : 8;
19017 insn
= THUMB_OP32 (opcode
);
19018 insn
= (insn
& 0xe1ffffff) | 0x10000000;
19019 insn
|= (old_op
& 0x700) << r0off
;
19020 put_thumb32_insn (buf
, insn
);
19021 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19025 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
19030 if (fragp
->fr_var
== 4)
19032 insn
= THUMB_OP32(opcode
);
19033 put_thumb32_insn (buf
, insn
);
19034 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
19037 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
19041 if (fragp
->fr_var
== 4)
19043 insn
= THUMB_OP32(opcode
);
19044 insn
|= (old_op
& 0xf00) << 14;
19045 put_thumb32_insn (buf
, insn
);
19046 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19049 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19052 case T_MNEM_add_sp
:
19053 case T_MNEM_add_pc
:
19054 case T_MNEM_inc_sp
:
19055 case T_MNEM_dec_sp
:
19056 if (fragp
->fr_var
== 4)
19058 /* ??? Choose between add and addw. */
19059 insn
= THUMB_OP32 (opcode
);
19060 insn
|= (old_op
& 0xf0) << 4;
19061 put_thumb32_insn (buf
, insn
);
19062 if (opcode
== T_MNEM_add_pc
)
19063 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
19065 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19068 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19076 if (fragp
->fr_var
== 4)
19078 insn
= THUMB_OP32 (opcode
);
19079 insn
|= (old_op
& 0xf0) << 4;
19080 insn
|= (old_op
& 0xf) << 16;
19081 put_thumb32_insn (buf
, insn
);
19082 if (insn
& (1 << 20))
19083 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19085 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19088 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19094 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
19095 (enum bfd_reloc_code_real
) reloc_type
);
19096 fixp
->fx_file
= fragp
->fr_file
;
19097 fixp
->fx_line
= fragp
->fr_line
;
19098 fragp
->fr_fix
+= fragp
->fr_var
;
19101 /* Return the size of a relaxable immediate operand instruction.
19102 SHIFT and SIZE specify the form of the allowable immediate. */
19104 relax_immediate (fragS
*fragp
, int size
, int shift
)
19110 /* ??? Should be able to do better than this. */
19111 if (fragp
->fr_symbol
)
19114 low
= (1 << shift
) - 1;
19115 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19116 offset
= fragp
->fr_offset
;
19117 /* Force misaligned offsets to 32-bit variant. */
19120 if (offset
& ~mask
)
19125 /* Get the address of a symbol during relaxation. */
19127 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19133 sym
= fragp
->fr_symbol
;
19134 sym_frag
= symbol_get_frag (sym
);
19135 know (S_GET_SEGMENT (sym
) != absolute_section
19136 || sym_frag
== &zero_address_frag
);
19137 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19139 /* If frag has yet to be reached on this pass, assume it will
19140 move by STRETCH just as we did. If this is not so, it will
19141 be because some frag between grows, and that will force
19145 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19149 /* Adjust stretch for any alignment frag. Note that if have
19150 been expanding the earlier code, the symbol may be
19151 defined in what appears to be an earlier frag. FIXME:
19152 This doesn't handle the fr_subtype field, which specifies
19153 a maximum number of bytes to skip when doing an
19155 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19157 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19160 stretch
= - ((- stretch
)
19161 & ~ ((1 << (int) f
->fr_offset
) - 1));
19163 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19175 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19178 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19183 /* Assume worst case for symbols not known to be in the same section. */
19184 if (fragp
->fr_symbol
== NULL
19185 || !S_IS_DEFINED (fragp
->fr_symbol
)
19186 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19187 || S_IS_WEAK (fragp
->fr_symbol
))
19190 val
= relaxed_symbol_addr (fragp
, stretch
);
19191 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19192 addr
= (addr
+ 4) & ~3;
19193 /* Force misaligned targets to 32-bit variant. */
19197 if (val
< 0 || val
> 1020)
19202 /* Return the size of a relaxable add/sub immediate instruction. */
19204 relax_addsub (fragS
*fragp
, asection
*sec
)
19209 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19210 op
= bfd_get_16(sec
->owner
, buf
);
19211 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19212 return relax_immediate (fragp
, 8, 0);
19214 return relax_immediate (fragp
, 3, 0);
19218 /* Return the size of a relaxable branch instruction. BITS is the
19219 size of the offset field in the narrow instruction. */
19222 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19228 /* Assume worst case for symbols not known to be in the same section. */
19229 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19230 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19231 || S_IS_WEAK (fragp
->fr_symbol
))
19235 if (S_IS_DEFINED (fragp
->fr_symbol
)
19236 && ARM_IS_FUNC (fragp
->fr_symbol
))
19239 /* PR 12532. Global symbols with default visibility might
19240 be preempted, so do not relax relocations to them. */
19241 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19242 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19246 val
= relaxed_symbol_addr (fragp
, stretch
);
19247 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19250 /* Offset is a signed value *2 */
19252 if (val
>= limit
|| val
< -limit
)
19258 /* Relax a machine dependent frag. This returns the amount by which
19259 the current size of the frag should change. */
19262 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19267 oldsize
= fragp
->fr_var
;
19268 switch (fragp
->fr_subtype
)
19270 case T_MNEM_ldr_pc2
:
19271 newsize
= relax_adr (fragp
, sec
, stretch
);
19273 case T_MNEM_ldr_pc
:
19274 case T_MNEM_ldr_sp
:
19275 case T_MNEM_str_sp
:
19276 newsize
= relax_immediate (fragp
, 8, 2);
19280 newsize
= relax_immediate (fragp
, 5, 2);
19284 newsize
= relax_immediate (fragp
, 5, 1);
19288 newsize
= relax_immediate (fragp
, 5, 0);
19291 newsize
= relax_adr (fragp
, sec
, stretch
);
19297 newsize
= relax_immediate (fragp
, 8, 0);
19300 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19303 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19305 case T_MNEM_add_sp
:
19306 case T_MNEM_add_pc
:
19307 newsize
= relax_immediate (fragp
, 8, 2);
19309 case T_MNEM_inc_sp
:
19310 case T_MNEM_dec_sp
:
19311 newsize
= relax_immediate (fragp
, 7, 2);
19317 newsize
= relax_addsub (fragp
, sec
);
19323 fragp
->fr_var
= newsize
;
19324 /* Freeze wide instructions that are at or before the same location as
19325 in the previous pass. This avoids infinite loops.
19326 Don't freeze them unconditionally because targets may be artificially
19327 misaligned by the expansion of preceding frags. */
19328 if (stretch
<= 0 && newsize
> 2)
19330 md_convert_frag (sec
->owner
, sec
, fragp
);
19334 return newsize
- oldsize
;
19337 /* Round up a section size to the appropriate boundary. */
19340 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19343 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19344 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19346 /* For a.out, force the section size to be aligned. If we don't do
19347 this, BFD will align it for us, but it will not write out the
19348 final bytes of the section. This may be a bug in BFD, but it is
19349 easier to fix it here since that is how the other a.out targets
19353 align
= bfd_get_section_alignment (stdoutput
, segment
);
19354 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19361 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19362 of an rs_align_code fragment. */
19365 arm_handle_align (fragS
* fragP
)
19367 static char const arm_noop
[2][2][4] =
19370 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19371 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19374 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19375 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19378 static char const thumb_noop
[2][2][2] =
19381 {0xc0, 0x46}, /* LE */
19382 {0x46, 0xc0}, /* BE */
19385 {0x00, 0xbf}, /* LE */
19386 {0xbf, 0x00} /* BE */
19389 static char const wide_thumb_noop
[2][4] =
19390 { /* Wide Thumb-2 */
19391 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19392 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19395 unsigned bytes
, fix
, noop_size
;
19398 const char *narrow_noop
= NULL
;
19403 if (fragP
->fr_type
!= rs_align_code
)
19406 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19407 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19410 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19411 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19413 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19415 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19417 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19419 narrow_noop
= thumb_noop
[1][target_big_endian
];
19420 noop
= wide_thumb_noop
[target_big_endian
];
19423 noop
= thumb_noop
[0][target_big_endian
];
19431 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19432 [target_big_endian
];
19439 fragP
->fr_var
= noop_size
;
19441 if (bytes
& (noop_size
- 1))
19443 fix
= bytes
& (noop_size
- 1);
19445 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19447 memset (p
, 0, fix
);
19454 if (bytes
& noop_size
)
19456 /* Insert a narrow noop. */
19457 memcpy (p
, narrow_noop
, noop_size
);
19459 bytes
-= noop_size
;
19463 /* Use wide noops for the remainder */
19467 while (bytes
>= noop_size
)
19469 memcpy (p
, noop
, noop_size
);
19471 bytes
-= noop_size
;
19475 fragP
->fr_fix
+= fix
;
19478 /* Called from md_do_align. Used to create an alignment
19479 frag in a code section. */
19482 arm_frag_align_code (int n
, int max
)
19486 /* We assume that there will never be a requirement
19487 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19488 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19493 _("alignments greater than %d bytes not supported in .text sections."),
19494 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19495 as_fatal ("%s", err_msg
);
19498 p
= frag_var (rs_align_code
,
19499 MAX_MEM_FOR_RS_ALIGN_CODE
,
19501 (relax_substateT
) max
,
19508 /* Perform target specific initialisation of a frag.
19509 Note - despite the name this initialisation is not done when the frag
19510 is created, but only when its type is assigned. A frag can be created
19511 and used a long time before its type is set, so beware of assuming that
19512 this initialisationis performed first. */
19516 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19518 /* Record whether this frag is in an ARM or a THUMB area. */
19519 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19522 #else /* OBJ_ELF is defined. */
19524 arm_init_frag (fragS
* fragP
, int max_chars
)
19526 /* If the current ARM vs THUMB mode has not already
19527 been recorded into this frag then do so now. */
19528 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19530 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19532 /* Record a mapping symbol for alignment frags. We will delete this
19533 later if the alignment ends up empty. */
19534 switch (fragP
->fr_type
)
19537 case rs_align_test
:
19539 mapping_state_2 (MAP_DATA
, max_chars
);
19541 case rs_align_code
:
19542 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19550 /* When we change sections we need to issue a new mapping symbol. */
19553 arm_elf_change_section (void)
19555 /* Link an unlinked unwind index table section to the .text section. */
19556 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19557 && elf_linked_to_section (now_seg
) == NULL
)
19558 elf_linked_to_section (now_seg
) = text_section
;
19562 arm_elf_section_type (const char * str
, size_t len
)
19564 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19565 return SHT_ARM_EXIDX
;
19570 /* Code to deal with unwinding tables. */
19572 static void add_unwind_adjustsp (offsetT
);
19574 /* Generate any deferred unwind frame offset. */
19577 flush_pending_unwind (void)
19581 offset
= unwind
.pending_offset
;
19582 unwind
.pending_offset
= 0;
19584 add_unwind_adjustsp (offset
);
19587 /* Add an opcode to this list for this function. Two-byte opcodes should
19588 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19592 add_unwind_opcode (valueT op
, int length
)
19594 /* Add any deferred stack adjustment. */
19595 if (unwind
.pending_offset
)
19596 flush_pending_unwind ();
19598 unwind
.sp_restored
= 0;
19600 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19602 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19603 if (unwind
.opcodes
)
19604 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19605 unwind
.opcode_alloc
);
19607 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19612 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19614 unwind
.opcode_count
++;
19618 /* Add unwind opcodes to adjust the stack pointer. */
19621 add_unwind_adjustsp (offsetT offset
)
19625 if (offset
> 0x200)
19627 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19632 /* Long form: 0xb2, uleb128. */
19633 /* This might not fit in a word so add the individual bytes,
19634 remembering the list is built in reverse order. */
19635 o
= (valueT
) ((offset
- 0x204) >> 2);
19637 add_unwind_opcode (0, 1);
19639 /* Calculate the uleb128 encoding of the offset. */
19643 bytes
[n
] = o
& 0x7f;
19649 /* Add the insn. */
19651 add_unwind_opcode (bytes
[n
- 1], 1);
19652 add_unwind_opcode (0xb2, 1);
19654 else if (offset
> 0x100)
19656 /* Two short opcodes. */
19657 add_unwind_opcode (0x3f, 1);
19658 op
= (offset
- 0x104) >> 2;
19659 add_unwind_opcode (op
, 1);
19661 else if (offset
> 0)
19663 /* Short opcode. */
19664 op
= (offset
- 4) >> 2;
19665 add_unwind_opcode (op
, 1);
19667 else if (offset
< 0)
19670 while (offset
> 0x100)
19672 add_unwind_opcode (0x7f, 1);
19675 op
= ((offset
- 4) >> 2) | 0x40;
19676 add_unwind_opcode (op
, 1);
19680 /* Finish the list of unwind opcodes for this function. */
19682 finish_unwind_opcodes (void)
19686 if (unwind
.fp_used
)
19688 /* Adjust sp as necessary. */
19689 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19690 flush_pending_unwind ();
19692 /* After restoring sp from the frame pointer. */
19693 op
= 0x90 | unwind
.fp_reg
;
19694 add_unwind_opcode (op
, 1);
19697 flush_pending_unwind ();
19701 /* Start an exception table entry. If idx is nonzero this is an index table
19705 start_unwind_section (const segT text_seg
, int idx
)
19707 const char * text_name
;
19708 const char * prefix
;
19709 const char * prefix_once
;
19710 const char * group_name
;
19714 size_t sec_name_len
;
19721 prefix
= ELF_STRING_ARM_unwind
;
19722 prefix_once
= ELF_STRING_ARM_unwind_once
;
19723 type
= SHT_ARM_EXIDX
;
19727 prefix
= ELF_STRING_ARM_unwind_info
;
19728 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19729 type
= SHT_PROGBITS
;
19732 text_name
= segment_name (text_seg
);
19733 if (streq (text_name
, ".text"))
19736 if (strncmp (text_name
, ".gnu.linkonce.t.",
19737 strlen (".gnu.linkonce.t.")) == 0)
19739 prefix
= prefix_once
;
19740 text_name
+= strlen (".gnu.linkonce.t.");
19743 prefix_len
= strlen (prefix
);
19744 text_len
= strlen (text_name
);
19745 sec_name_len
= prefix_len
+ text_len
;
19746 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19747 memcpy (sec_name
, prefix
, prefix_len
);
19748 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19749 sec_name
[prefix_len
+ text_len
] = '\0';
19755 /* Handle COMDAT group. */
19756 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19758 group_name
= elf_group_name (text_seg
);
19759 if (group_name
== NULL
)
19761 as_bad (_("Group section `%s' has no group signature"),
19762 segment_name (text_seg
));
19763 ignore_rest_of_line ();
19766 flags
|= SHF_GROUP
;
19770 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19772 /* Set the section link for index tables. */
19774 elf_linked_to_section (now_seg
) = text_seg
;
19778 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19779 personality routine data. Returns zero, or the index table value for
19780 and inline entry. */
19783 create_unwind_entry (int have_data
)
19788 /* The current word of data. */
19790 /* The number of bytes left in this word. */
19793 finish_unwind_opcodes ();
19795 /* Remember the current text section. */
19796 unwind
.saved_seg
= now_seg
;
19797 unwind
.saved_subseg
= now_subseg
;
19799 start_unwind_section (now_seg
, 0);
19801 if (unwind
.personality_routine
== NULL
)
19803 if (unwind
.personality_index
== -2)
19806 as_bad (_("handlerdata in cantunwind frame"));
19807 return 1; /* EXIDX_CANTUNWIND. */
19810 /* Use a default personality routine if none is specified. */
19811 if (unwind
.personality_index
== -1)
19813 if (unwind
.opcode_count
> 3)
19814 unwind
.personality_index
= 1;
19816 unwind
.personality_index
= 0;
19819 /* Space for the personality routine entry. */
19820 if (unwind
.personality_index
== 0)
19822 if (unwind
.opcode_count
> 3)
19823 as_bad (_("too many unwind opcodes for personality routine 0"));
19827 /* All the data is inline in the index table. */
19830 while (unwind
.opcode_count
> 0)
19832 unwind
.opcode_count
--;
19833 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19837 /* Pad with "finish" opcodes. */
19839 data
= (data
<< 8) | 0xb0;
19846 /* We get two opcodes "free" in the first word. */
19847 size
= unwind
.opcode_count
- 2;
19850 /* An extra byte is required for the opcode count. */
19851 size
= unwind
.opcode_count
+ 1;
19853 size
= (size
+ 3) >> 2;
19855 as_bad (_("too many unwind opcodes"));
19857 frag_align (2, 0, 0);
19858 record_alignment (now_seg
, 2);
19859 unwind
.table_entry
= expr_build_dot ();
19861 /* Allocate the table entry. */
19862 ptr
= frag_more ((size
<< 2) + 4);
19863 where
= frag_now_fix () - ((size
<< 2) + 4);
19865 switch (unwind
.personality_index
)
19868 /* ??? Should this be a PLT generating relocation? */
19869 /* Custom personality routine. */
19870 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19871 BFD_RELOC_ARM_PREL31
);
19876 /* Set the first byte to the number of additional words. */
19881 /* ABI defined personality routines. */
19883 /* Three opcodes bytes are packed into the first word. */
19890 /* The size and first two opcode bytes go in the first word. */
19891 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19896 /* Should never happen. */
19900 /* Pack the opcodes into words (MSB first), reversing the list at the same
19902 while (unwind
.opcode_count
> 0)
19906 md_number_to_chars (ptr
, data
, 4);
19911 unwind
.opcode_count
--;
19913 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19916 /* Finish off the last word. */
19919 /* Pad with "finish" opcodes. */
19921 data
= (data
<< 8) | 0xb0;
19923 md_number_to_chars (ptr
, data
, 4);
19928 /* Add an empty descriptor if there is no user-specified data. */
19929 ptr
= frag_more (4);
19930 md_number_to_chars (ptr
, 0, 4);
19937 /* Initialize the DWARF-2 unwind information for this procedure. */
19940 tc_arm_frame_initial_instructions (void)
19942 cfi_add_CFA_def_cfa (REG_SP
, 0);
19944 #endif /* OBJ_ELF */
19946 /* Convert REGNAME to a DWARF-2 register number. */
19949 tc_arm_regname_to_dw2regnum (char *regname
)
19951 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19961 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19965 exp
.X_op
= O_secrel
;
19966 exp
.X_add_symbol
= symbol
;
19967 exp
.X_add_number
= 0;
19968 emit_expr (&exp
, size
);
19972 /* MD interface: Symbol and relocation handling. */
19974 /* Return the address within the segment that a PC-relative fixup is
19975 relative to. For ARM, PC-relative fixups applied to instructions
19976 are generally relative to the location of the fixup plus 8 bytes.
19977 Thumb branches are offset by 4, and Thumb loads relative to PC
19978 require special handling. */
19981 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19983 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19985 /* If this is pc-relative and we are going to emit a relocation
19986 then we just want to put out any pipeline compensation that the linker
19987 will need. Otherwise we want to use the calculated base.
19988 For WinCE we skip the bias for externals as well, since this
19989 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19991 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19992 || (arm_force_relocation (fixP
)
19994 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20000 switch (fixP
->fx_r_type
)
20002 /* PC relative addressing on the Thumb is slightly odd as the
20003 bottom two bits of the PC are forced to zero for the
20004 calculation. This happens *after* application of the
20005 pipeline offset. However, Thumb adrl already adjusts for
20006 this, so we need not do it again. */
20007 case BFD_RELOC_ARM_THUMB_ADD
:
20010 case BFD_RELOC_ARM_THUMB_OFFSET
:
20011 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20012 case BFD_RELOC_ARM_T32_ADD_PC12
:
20013 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20014 return (base
+ 4) & ~3;
20016 /* Thumb branches are simply offset by +4. */
20017 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20018 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20019 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20020 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20021 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20024 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20026 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20027 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20028 && ARM_IS_FUNC (fixP
->fx_addsy
)
20029 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20030 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20033 /* BLX is like branches above, but forces the low two bits of PC to
20035 case BFD_RELOC_THUMB_PCREL_BLX
:
20037 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20038 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20039 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20040 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20041 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20042 return (base
+ 4) & ~3;
20044 /* ARM mode branches are offset by +8. However, the Windows CE
20045 loader expects the relocation not to take this into account. */
20046 case BFD_RELOC_ARM_PCREL_BLX
:
20048 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20049 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20050 && ARM_IS_FUNC (fixP
->fx_addsy
)
20051 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20052 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20055 case BFD_RELOC_ARM_PCREL_CALL
:
20057 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20058 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20059 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20060 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20061 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20064 case BFD_RELOC_ARM_PCREL_BRANCH
:
20065 case BFD_RELOC_ARM_PCREL_JUMP
:
20066 case BFD_RELOC_ARM_PLT32
:
20068 /* When handling fixups immediately, because we have already
20069 discovered the value of a symbol, or the address of the frag involved
20070 we must account for the offset by +8, as the OS loader will never see the reloc.
20071 see fixup_segment() in write.c
20072 The S_IS_EXTERNAL test handles the case of global symbols.
20073 Those need the calculated base, not just the pipe compensation the linker will need. */
20075 && fixP
->fx_addsy
!= NULL
20076 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20077 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
20085 /* ARM mode loads relative to PC are also offset by +8. Unlike
20086 branches, the Windows CE loader *does* expect the relocation
20087 to take this into account. */
20088 case BFD_RELOC_ARM_OFFSET_IMM
:
20089 case BFD_RELOC_ARM_OFFSET_IMM8
:
20090 case BFD_RELOC_ARM_HWLITERAL
:
20091 case BFD_RELOC_ARM_LITERAL
:
20092 case BFD_RELOC_ARM_CP_OFF_IMM
:
20096 /* Other PC-relative relocations are un-offset. */
20102 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20103 Otherwise we have no need to default values of symbols. */
20106 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20109 if (name
[0] == '_' && name
[1] == 'G'
20110 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20114 if (symbol_find (name
))
20115 as_bad (_("GOT already in the symbol table"));
20117 GOT_symbol
= symbol_new (name
, undefined_section
,
20118 (valueT
) 0, & zero_address_frag
);
20128 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20129 computed as two separate immediate values, added together. We
20130 already know that this value cannot be computed by just one ARM
20133 static unsigned int
20134 validate_immediate_twopart (unsigned int val
,
20135 unsigned int * highpart
)
20140 for (i
= 0; i
< 32; i
+= 2)
20141 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20147 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20149 else if (a
& 0xff0000)
20151 if (a
& 0xff000000)
20153 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20157 gas_assert (a
& 0xff000000);
20158 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20161 return (a
& 0xff) | (i
<< 7);
20168 validate_offset_imm (unsigned int val
, int hwse
)
20170 if ((hwse
&& val
> 255) || val
> 4095)
20175 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20176 negative immediate constant by altering the instruction. A bit of
20181 by inverting the second operand, and
20184 by negating the second operand. */
20187 negate_data_op (unsigned long * instruction
,
20188 unsigned long value
)
20191 unsigned long negated
, inverted
;
20193 negated
= encode_arm_immediate (-value
);
20194 inverted
= encode_arm_immediate (~value
);
20196 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20199 /* First negates. */
20200 case OPCODE_SUB
: /* ADD <-> SUB */
20201 new_inst
= OPCODE_ADD
;
20206 new_inst
= OPCODE_SUB
;
20210 case OPCODE_CMP
: /* CMP <-> CMN */
20211 new_inst
= OPCODE_CMN
;
20216 new_inst
= OPCODE_CMP
;
20220 /* Now Inverted ops. */
20221 case OPCODE_MOV
: /* MOV <-> MVN */
20222 new_inst
= OPCODE_MVN
;
20227 new_inst
= OPCODE_MOV
;
20231 case OPCODE_AND
: /* AND <-> BIC */
20232 new_inst
= OPCODE_BIC
;
20237 new_inst
= OPCODE_AND
;
20241 case OPCODE_ADC
: /* ADC <-> SBC */
20242 new_inst
= OPCODE_SBC
;
20247 new_inst
= OPCODE_ADC
;
20251 /* We cannot do anything. */
20256 if (value
== (unsigned) FAIL
)
20259 *instruction
&= OPCODE_MASK
;
20260 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20264 /* Like negate_data_op, but for Thumb-2. */
20266 static unsigned int
20267 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20271 unsigned int negated
, inverted
;
20273 negated
= encode_thumb32_immediate (-value
);
20274 inverted
= encode_thumb32_immediate (~value
);
20276 rd
= (*instruction
>> 8) & 0xf;
20277 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20280 /* ADD <-> SUB. Includes CMP <-> CMN. */
20281 case T2_OPCODE_SUB
:
20282 new_inst
= T2_OPCODE_ADD
;
20286 case T2_OPCODE_ADD
:
20287 new_inst
= T2_OPCODE_SUB
;
20291 /* ORR <-> ORN. Includes MOV <-> MVN. */
20292 case T2_OPCODE_ORR
:
20293 new_inst
= T2_OPCODE_ORN
;
20297 case T2_OPCODE_ORN
:
20298 new_inst
= T2_OPCODE_ORR
;
20302 /* AND <-> BIC. TST has no inverted equivalent. */
20303 case T2_OPCODE_AND
:
20304 new_inst
= T2_OPCODE_BIC
;
20311 case T2_OPCODE_BIC
:
20312 new_inst
= T2_OPCODE_AND
;
20317 case T2_OPCODE_ADC
:
20318 new_inst
= T2_OPCODE_SBC
;
20322 case T2_OPCODE_SBC
:
20323 new_inst
= T2_OPCODE_ADC
;
20327 /* We cannot do anything. */
20332 if (value
== (unsigned int)FAIL
)
20335 *instruction
&= T2_OPCODE_MASK
;
20336 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20340 /* Read a 32-bit thumb instruction from buf. */
20341 static unsigned long
20342 get_thumb32_insn (char * buf
)
20344 unsigned long insn
;
20345 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20346 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20352 /* We usually want to set the low bit on the address of thumb function
20353 symbols. In particular .word foo - . should have the low bit set.
20354 Generic code tries to fold the difference of two symbols to
20355 a constant. Prevent this and force a relocation when the first symbols
20356 is a thumb function. */
20359 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20361 if (op
== O_subtract
20362 && l
->X_op
== O_symbol
20363 && r
->X_op
== O_symbol
20364 && THUMB_IS_FUNC (l
->X_add_symbol
))
20366 l
->X_op
= O_subtract
;
20367 l
->X_op_symbol
= r
->X_add_symbol
;
20368 l
->X_add_number
-= r
->X_add_number
;
20372 /* Process as normal. */
20376 /* Encode Thumb2 unconditional branches and calls. The encoding
20377 for the 2 are identical for the immediate values. */
20380 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20382 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20385 addressT S
, I1
, I2
, lo
, hi
;
20387 S
= (value
>> 24) & 0x01;
20388 I1
= (value
>> 23) & 0x01;
20389 I2
= (value
>> 22) & 0x01;
20390 hi
= (value
>> 12) & 0x3ff;
20391 lo
= (value
>> 1) & 0x7ff;
20392 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20393 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20394 newval
|= (S
<< 10) | hi
;
20395 newval2
&= ~T2I1I2MASK
;
20396 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20397 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20398 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20402 md_apply_fix (fixS
* fixP
,
20406 offsetT value
= * valP
;
20408 unsigned int newimm
;
20409 unsigned long temp
;
20411 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20413 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20415 /* Note whether this will delete the relocation. */
20417 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20420 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20421 consistency with the behaviour on 32-bit hosts. Remember value
20423 value
&= 0xffffffff;
20424 value
^= 0x80000000;
20425 value
-= 0x80000000;
20428 fixP
->fx_addnumber
= value
;
20430 /* Same treatment for fixP->fx_offset. */
20431 fixP
->fx_offset
&= 0xffffffff;
20432 fixP
->fx_offset
^= 0x80000000;
20433 fixP
->fx_offset
-= 0x80000000;
20435 switch (fixP
->fx_r_type
)
20437 case BFD_RELOC_NONE
:
20438 /* This will need to go in the object file. */
20442 case BFD_RELOC_ARM_IMMEDIATE
:
20443 /* We claim that this fixup has been processed here,
20444 even if in fact we generate an error because we do
20445 not have a reloc for it, so tc_gen_reloc will reject it. */
20448 if (fixP
->fx_addsy
)
20450 const char *msg
= 0;
20452 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20453 msg
= _("undefined symbol %s used as an immediate value");
20454 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20455 msg
= _("symbol %s is in a different section");
20456 else if (S_IS_WEAK (fixP
->fx_addsy
))
20457 msg
= _("symbol %s is weak and may be overridden later");
20461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20462 msg
, S_GET_NAME (fixP
->fx_addsy
));
20467 newimm
= encode_arm_immediate (value
);
20468 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20470 /* If the instruction will fail, see if we can fix things up by
20471 changing the opcode. */
20472 if (newimm
== (unsigned int) FAIL
20473 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20476 _("invalid constant (%lx) after fixup"),
20477 (unsigned long) value
);
20481 newimm
|= (temp
& 0xfffff000);
20482 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20485 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20487 unsigned int highpart
= 0;
20488 unsigned int newinsn
= 0xe1a00000; /* nop. */
20490 if (fixP
->fx_addsy
)
20492 const char *msg
= 0;
20494 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20495 msg
= _("undefined symbol %s used as an immediate value");
20496 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20497 msg
= _("symbol %s is in a different section");
20498 else if (S_IS_WEAK (fixP
->fx_addsy
))
20499 msg
= _("symbol %s is weak and may be overridden later");
20503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20504 msg
, S_GET_NAME (fixP
->fx_addsy
));
20509 newimm
= encode_arm_immediate (value
);
20510 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20512 /* If the instruction will fail, see if we can fix things up by
20513 changing the opcode. */
20514 if (newimm
== (unsigned int) FAIL
20515 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20517 /* No ? OK - try using two ADD instructions to generate
20519 newimm
= validate_immediate_twopart (value
, & highpart
);
20521 /* Yes - then make sure that the second instruction is
20523 if (newimm
!= (unsigned int) FAIL
)
20525 /* Still No ? Try using a negated value. */
20526 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20527 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20528 /* Otherwise - give up. */
20531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20532 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20537 /* Replace the first operand in the 2nd instruction (which
20538 is the PC) with the destination register. We have
20539 already added in the PC in the first instruction and we
20540 do not want to do it again. */
20541 newinsn
&= ~ 0xf0000;
20542 newinsn
|= ((newinsn
& 0x0f000) << 4);
20545 newimm
|= (temp
& 0xfffff000);
20546 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20548 highpart
|= (newinsn
& 0xfffff000);
20549 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20553 case BFD_RELOC_ARM_OFFSET_IMM
:
20554 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20557 case BFD_RELOC_ARM_LITERAL
:
20563 if (validate_offset_imm (value
, 0) == FAIL
)
20565 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20567 _("invalid literal constant: pool needs to be closer"));
20569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20570 _("bad immediate value for offset (%ld)"),
20575 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20577 newval
&= 0xfffff000;
20580 newval
&= 0xff7ff000;
20581 newval
|= value
| (sign
? INDEX_UP
: 0);
20583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20586 case BFD_RELOC_ARM_OFFSET_IMM8
:
20587 case BFD_RELOC_ARM_HWLITERAL
:
20593 if (validate_offset_imm (value
, 1) == FAIL
)
20595 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20597 _("invalid literal constant: pool needs to be closer"));
20599 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20604 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20606 newval
&= 0xfffff0f0;
20609 newval
&= 0xff7ff0f0;
20610 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20612 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20615 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20616 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20618 _("bad immediate value for offset (%ld)"), (long) value
);
20621 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20623 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20626 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20627 /* This is a complicated relocation used for all varieties of Thumb32
20628 load/store instruction with immediate offset:
20630 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20631 *4, optional writeback(W)
20632 (doubleword load/store)
20634 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20635 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20636 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20637 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20638 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20640 Uppercase letters indicate bits that are already encoded at
20641 this point. Lowercase letters are our problem. For the
20642 second block of instructions, the secondary opcode nybble
20643 (bits 8..11) is present, and bit 23 is zero, even if this is
20644 a PC-relative operation. */
20645 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20647 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20649 if ((newval
& 0xf0000000) == 0xe0000000)
20651 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20653 newval
|= (1 << 23);
20656 if (value
% 4 != 0)
20658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20659 _("offset not a multiple of 4"));
20665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20666 _("offset out of range"));
20671 else if ((newval
& 0x000f0000) == 0x000f0000)
20673 /* PC-relative, 12-bit offset. */
20675 newval
|= (1 << 23);
20680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20681 _("offset out of range"));
20686 else if ((newval
& 0x00000100) == 0x00000100)
20688 /* Writeback: 8-bit, +/- offset. */
20690 newval
|= (1 << 9);
20695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20696 _("offset out of range"));
20701 else if ((newval
& 0x00000f00) == 0x00000e00)
20703 /* T-instruction: positive 8-bit offset. */
20704 if (value
< 0 || value
> 0xff)
20706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20707 _("offset out of range"));
20715 /* Positive 12-bit or negative 8-bit offset. */
20719 newval
|= (1 << 23);
20729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20730 _("offset out of range"));
20737 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20738 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20741 case BFD_RELOC_ARM_SHIFT_IMM
:
20742 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20743 if (((unsigned long) value
) > 32
20745 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20748 _("shift expression is too large"));
20753 /* Shifts of zero must be done as lsl. */
20755 else if (value
== 32)
20757 newval
&= 0xfffff07f;
20758 newval
|= (value
& 0x1f) << 7;
20759 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20762 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20763 case BFD_RELOC_ARM_T32_ADD_IMM
:
20764 case BFD_RELOC_ARM_T32_IMM12
:
20765 case BFD_RELOC_ARM_T32_ADD_PC12
:
20766 /* We claim that this fixup has been processed here,
20767 even if in fact we generate an error because we do
20768 not have a reloc for it, so tc_gen_reloc will reject it. */
20772 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20775 _("undefined symbol %s used as an immediate value"),
20776 S_GET_NAME (fixP
->fx_addsy
));
20780 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20782 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20785 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20786 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20788 newimm
= encode_thumb32_immediate (value
);
20789 if (newimm
== (unsigned int) FAIL
)
20790 newimm
= thumb32_negate_data_op (&newval
, value
);
20792 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20793 && newimm
== (unsigned int) FAIL
)
20795 /* Turn add/sum into addw/subw. */
20796 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20797 newval
= (newval
& 0xfeffffff) | 0x02000000;
20798 /* No flat 12-bit imm encoding for addsw/subsw. */
20799 if ((newval
& 0x00100000) == 0)
20801 /* 12 bit immediate for addw/subw. */
20805 newval
^= 0x00a00000;
20808 newimm
= (unsigned int) FAIL
;
20814 if (newimm
== (unsigned int)FAIL
)
20816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20817 _("invalid constant (%lx) after fixup"),
20818 (unsigned long) value
);
20822 newval
|= (newimm
& 0x800) << 15;
20823 newval
|= (newimm
& 0x700) << 4;
20824 newval
|= (newimm
& 0x0ff);
20826 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20827 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20830 case BFD_RELOC_ARM_SMC
:
20831 if (((unsigned long) value
) > 0xffff)
20832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20833 _("invalid smc expression"));
20834 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20835 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20836 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20839 case BFD_RELOC_ARM_HVC
:
20840 if (((unsigned long) value
) > 0xffff)
20841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20842 _("invalid hvc expression"));
20843 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20844 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20845 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20848 case BFD_RELOC_ARM_SWI
:
20849 if (fixP
->tc_fix_data
!= 0)
20851 if (((unsigned long) value
) > 0xff)
20852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20853 _("invalid swi expression"));
20854 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20856 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20860 if (((unsigned long) value
) > 0x00ffffff)
20861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20862 _("invalid swi expression"));
20863 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20865 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20869 case BFD_RELOC_ARM_MULTI
:
20870 if (((unsigned long) value
) > 0xffff)
20871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20872 _("invalid expression in load/store multiple"));
20873 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20874 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20878 case BFD_RELOC_ARM_PCREL_CALL
:
20880 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20882 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20883 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20884 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20885 /* Flip the bl to blx. This is a simple flip
20886 bit here because we generate PCREL_CALL for
20887 unconditional bls. */
20889 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20890 newval
= newval
| 0x10000000;
20891 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20897 goto arm_branch_common
;
20899 case BFD_RELOC_ARM_PCREL_JUMP
:
20900 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20902 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20903 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20904 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20906 /* This would map to a bl<cond>, b<cond>,
20907 b<always> to a Thumb function. We
20908 need to force a relocation for this particular
20910 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20914 case BFD_RELOC_ARM_PLT32
:
20916 case BFD_RELOC_ARM_PCREL_BRANCH
:
20918 goto arm_branch_common
;
20920 case BFD_RELOC_ARM_PCREL_BLX
:
20923 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20925 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20926 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20927 && ARM_IS_FUNC (fixP
->fx_addsy
))
20929 /* Flip the blx to a bl and warn. */
20930 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20931 newval
= 0xeb000000;
20932 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20933 _("blx to '%s' an ARM ISA state function changed to bl"),
20935 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20941 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20942 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20946 /* We are going to store value (shifted right by two) in the
20947 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20948 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20949 also be be clear. */
20951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20952 _("misaligned branch destination"));
20953 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20954 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
20957 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20959 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20960 newval
|= (value
>> 2) & 0x00ffffff;
20961 /* Set the H bit on BLX instructions. */
20965 newval
|= 0x01000000;
20967 newval
&= ~0x01000000;
20969 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20973 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20974 /* CBZ can only branch forward. */
20976 /* Attempts to use CBZ to branch to the next instruction
20977 (which, strictly speaking, are prohibited) will be turned into
20980 FIXME: It may be better to remove the instruction completely and
20981 perform relaxation. */
20984 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20985 newval
= 0xbf00; /* NOP encoding T1 */
20986 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
20993 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20995 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20996 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20997 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21002 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
21003 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
21004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21006 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21008 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21009 newval
|= (value
& 0x1ff) >> 1;
21010 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21014 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
21015 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
21016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21018 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21020 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21021 newval
|= (value
& 0xfff) >> 1;
21022 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21026 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21028 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21029 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21030 && ARM_IS_FUNC (fixP
->fx_addsy
)
21031 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21033 /* Force a relocation for a branch 20 bits wide. */
21036 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
21037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21038 _("conditional branch out of range"));
21040 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21043 addressT S
, J1
, J2
, lo
, hi
;
21045 S
= (value
& 0x00100000) >> 20;
21046 J2
= (value
& 0x00080000) >> 19;
21047 J1
= (value
& 0x00040000) >> 18;
21048 hi
= (value
& 0x0003f000) >> 12;
21049 lo
= (value
& 0x00000ffe) >> 1;
21051 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21052 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21053 newval
|= (S
<< 10) | hi
;
21054 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
21055 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21056 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21060 case BFD_RELOC_THUMB_PCREL_BLX
:
21061 /* If there is a blx from a thumb state function to
21062 another thumb function flip this to a bl and warn
21066 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21067 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21068 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21070 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21071 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21072 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21074 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21075 newval
= newval
| 0x1000;
21076 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21077 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21082 goto thumb_bl_common
;
21084 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21085 /* A bl from Thumb state ISA to an internal ARM state function
21086 is converted to a blx. */
21088 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21089 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21090 && ARM_IS_FUNC (fixP
->fx_addsy
)
21091 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21093 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21094 newval
= newval
& ~0x1000;
21095 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21096 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
21103 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
21104 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21105 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21108 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21109 /* For a BLX instruction, make sure that the relocation is rounded up
21110 to a word boundary. This follows the semantics of the instruction
21111 which specifies that bit 1 of the target address will come from bit
21112 1 of the base address. */
21113 value
= (value
+ 1) & ~ 1;
21115 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21117 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21119 else if ((value
& ~0x1ffffff)
21120 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21122 _("Thumb2 branch out of range"));
21125 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21126 encode_thumb2_b_bl_offset (buf
, value
);
21130 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21131 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
21132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21134 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21135 encode_thumb2_b_bl_offset (buf
, value
);
21140 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21141 md_number_to_chars (buf
, value
, 1);
21145 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21146 md_number_to_chars (buf
, value
, 2);
21150 case BFD_RELOC_ARM_TLS_CALL
:
21151 case BFD_RELOC_ARM_THM_TLS_CALL
:
21152 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21153 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21154 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21157 case BFD_RELOC_ARM_TLS_GOTDESC
:
21158 case BFD_RELOC_ARM_TLS_GD32
:
21159 case BFD_RELOC_ARM_TLS_LE32
:
21160 case BFD_RELOC_ARM_TLS_IE32
:
21161 case BFD_RELOC_ARM_TLS_LDM32
:
21162 case BFD_RELOC_ARM_TLS_LDO32
:
21163 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21166 case BFD_RELOC_ARM_GOT32
:
21167 case BFD_RELOC_ARM_GOTOFF
:
21168 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21169 md_number_to_chars (buf
, 0, 4);
21172 case BFD_RELOC_ARM_GOT_PREL
:
21173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21174 md_number_to_chars (buf
, value
, 4);
21177 case BFD_RELOC_ARM_TARGET2
:
21178 /* TARGET2 is not partial-inplace, so we need to write the
21179 addend here for REL targets, because it won't be written out
21180 during reloc processing later. */
21181 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21182 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21186 case BFD_RELOC_RVA
:
21188 case BFD_RELOC_ARM_TARGET1
:
21189 case BFD_RELOC_ARM_ROSEGREL32
:
21190 case BFD_RELOC_ARM_SBREL32
:
21191 case BFD_RELOC_32_PCREL
:
21193 case BFD_RELOC_32_SECREL
:
21195 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21197 /* For WinCE we only do this for pcrel fixups. */
21198 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21200 md_number_to_chars (buf
, value
, 4);
21204 case BFD_RELOC_ARM_PREL31
:
21205 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21207 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21208 if ((value
^ (value
>> 1)) & 0x40000000)
21210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21211 _("rel31 relocation overflow"));
21213 newval
|= value
& 0x7fffffff;
21214 md_number_to_chars (buf
, newval
, 4);
21219 case BFD_RELOC_ARM_CP_OFF_IMM
:
21220 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21221 if (value
< -1023 || value
> 1023 || (value
& 3))
21222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21223 _("co-processor offset out of range"));
21228 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21229 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21230 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21232 newval
= get_thumb32_insn (buf
);
21234 newval
&= 0xffffff00;
21237 newval
&= 0xff7fff00;
21238 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21240 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21241 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21242 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21244 put_thumb32_insn (buf
, newval
);
21247 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21248 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21249 if (value
< -255 || value
> 255)
21250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21251 _("co-processor offset out of range"));
21253 goto cp_off_common
;
21255 case BFD_RELOC_ARM_THUMB_OFFSET
:
21256 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21257 /* Exactly what ranges, and where the offset is inserted depends
21258 on the type of instruction, we can establish this from the
21260 switch (newval
>> 12)
21262 case 4: /* PC load. */
21263 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21264 forced to zero for these loads; md_pcrel_from has already
21265 compensated for this. */
21267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21268 _("invalid offset, target not word aligned (0x%08lX)"),
21269 (((unsigned long) fixP
->fx_frag
->fr_address
21270 + (unsigned long) fixP
->fx_where
) & ~3)
21271 + (unsigned long) value
);
21273 if (value
& ~0x3fc)
21274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21275 _("invalid offset, value too big (0x%08lX)"),
21278 newval
|= value
>> 2;
21281 case 9: /* SP load/store. */
21282 if (value
& ~0x3fc)
21283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21284 _("invalid offset, value too big (0x%08lX)"),
21286 newval
|= value
>> 2;
21289 case 6: /* Word load/store. */
21291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21292 _("invalid offset, value too big (0x%08lX)"),
21294 newval
|= value
<< 4; /* 6 - 2. */
21297 case 7: /* Byte load/store. */
21299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21300 _("invalid offset, value too big (0x%08lX)"),
21302 newval
|= value
<< 6;
21305 case 8: /* Halfword load/store. */
21307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21308 _("invalid offset, value too big (0x%08lX)"),
21310 newval
|= value
<< 5; /* 6 - 1. */
21314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21315 "Unable to process relocation for thumb opcode: %lx",
21316 (unsigned long) newval
);
21319 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21322 case BFD_RELOC_ARM_THUMB_ADD
:
21323 /* This is a complicated relocation, since we use it for all of
21324 the following immediate relocations:
21328 9bit ADD/SUB SP word-aligned
21329 10bit ADD PC/SP word-aligned
21331 The type of instruction being processed is encoded in the
21338 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21340 int rd
= (newval
>> 4) & 0xf;
21341 int rs
= newval
& 0xf;
21342 int subtract
= !!(newval
& 0x8000);
21344 /* Check for HI regs, only very restricted cases allowed:
21345 Adjusting SP, and using PC or SP to get an address. */
21346 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21347 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21349 _("invalid Hi register with immediate"));
21351 /* If value is negative, choose the opposite instruction. */
21355 subtract
= !subtract
;
21357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21358 _("immediate value out of range"));
21363 if (value
& ~0x1fc)
21364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21365 _("invalid immediate for stack address calculation"));
21366 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21367 newval
|= value
>> 2;
21369 else if (rs
== REG_PC
|| rs
== REG_SP
)
21371 if (subtract
|| value
& ~0x3fc)
21372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21373 _("invalid immediate for address calculation (value = 0x%08lX)"),
21374 (unsigned long) value
);
21375 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21377 newval
|= value
>> 2;
21382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21383 _("immediate value out of range"));
21384 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21385 newval
|= (rd
<< 8) | value
;
21390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21391 _("immediate value out of range"));
21392 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21393 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21396 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21399 case BFD_RELOC_ARM_THUMB_IMM
:
21400 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21401 if (value
< 0 || value
> 255)
21402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21403 _("invalid immediate: %ld is out of range"),
21406 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21409 case BFD_RELOC_ARM_THUMB_SHIFT
:
21410 /* 5bit shift value (0..32). LSL cannot take 32. */
21411 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21412 temp
= newval
& 0xf800;
21413 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21415 _("invalid shift value: %ld"), (long) value
);
21416 /* Shifts of zero must be encoded as LSL. */
21418 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21419 /* Shifts of 32 are encoded as zero. */
21420 else if (value
== 32)
21422 newval
|= value
<< 6;
21423 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21426 case BFD_RELOC_VTABLE_INHERIT
:
21427 case BFD_RELOC_VTABLE_ENTRY
:
21431 case BFD_RELOC_ARM_MOVW
:
21432 case BFD_RELOC_ARM_MOVT
:
21433 case BFD_RELOC_ARM_THUMB_MOVW
:
21434 case BFD_RELOC_ARM_THUMB_MOVT
:
21435 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21437 /* REL format relocations are limited to a 16-bit addend. */
21438 if (!fixP
->fx_done
)
21440 if (value
< -0x8000 || value
> 0x7fff)
21441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21442 _("offset out of range"));
21444 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21445 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21450 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21451 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21453 newval
= get_thumb32_insn (buf
);
21454 newval
&= 0xfbf08f00;
21455 newval
|= (value
& 0xf000) << 4;
21456 newval
|= (value
& 0x0800) << 15;
21457 newval
|= (value
& 0x0700) << 4;
21458 newval
|= (value
& 0x00ff);
21459 put_thumb32_insn (buf
, newval
);
21463 newval
= md_chars_to_number (buf
, 4);
21464 newval
&= 0xfff0f000;
21465 newval
|= value
& 0x0fff;
21466 newval
|= (value
& 0xf000) << 4;
21467 md_number_to_chars (buf
, newval
, 4);
21472 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21473 case BFD_RELOC_ARM_ALU_PC_G0
:
21474 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21475 case BFD_RELOC_ARM_ALU_PC_G1
:
21476 case BFD_RELOC_ARM_ALU_PC_G2
:
21477 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21478 case BFD_RELOC_ARM_ALU_SB_G0
:
21479 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21480 case BFD_RELOC_ARM_ALU_SB_G1
:
21481 case BFD_RELOC_ARM_ALU_SB_G2
:
21482 gas_assert (!fixP
->fx_done
);
21483 if (!seg
->use_rela_p
)
21486 bfd_vma encoded_addend
;
21487 bfd_vma addend_abs
= abs (value
);
21489 /* Check that the absolute value of the addend can be
21490 expressed as an 8-bit constant plus a rotation. */
21491 encoded_addend
= encode_arm_immediate (addend_abs
);
21492 if (encoded_addend
== (unsigned int) FAIL
)
21493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21494 _("the offset 0x%08lX is not representable"),
21495 (unsigned long) addend_abs
);
21497 /* Extract the instruction. */
21498 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21500 /* If the addend is positive, use an ADD instruction.
21501 Otherwise use a SUB. Take care not to destroy the S bit. */
21502 insn
&= 0xff1fffff;
21508 /* Place the encoded addend into the first 12 bits of the
21510 insn
&= 0xfffff000;
21511 insn
|= encoded_addend
;
21513 /* Update the instruction. */
21514 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21518 case BFD_RELOC_ARM_LDR_PC_G0
:
21519 case BFD_RELOC_ARM_LDR_PC_G1
:
21520 case BFD_RELOC_ARM_LDR_PC_G2
:
21521 case BFD_RELOC_ARM_LDR_SB_G0
:
21522 case BFD_RELOC_ARM_LDR_SB_G1
:
21523 case BFD_RELOC_ARM_LDR_SB_G2
:
21524 gas_assert (!fixP
->fx_done
);
21525 if (!seg
->use_rela_p
)
21528 bfd_vma addend_abs
= abs (value
);
21530 /* Check that the absolute value of the addend can be
21531 encoded in 12 bits. */
21532 if (addend_abs
>= 0x1000)
21533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21534 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21535 (unsigned long) addend_abs
);
21537 /* Extract the instruction. */
21538 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21540 /* If the addend is negative, clear bit 23 of the instruction.
21541 Otherwise set it. */
21543 insn
&= ~(1 << 23);
21547 /* Place the absolute value of the addend into the first 12 bits
21548 of the instruction. */
21549 insn
&= 0xfffff000;
21550 insn
|= addend_abs
;
21552 /* Update the instruction. */
21553 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21557 case BFD_RELOC_ARM_LDRS_PC_G0
:
21558 case BFD_RELOC_ARM_LDRS_PC_G1
:
21559 case BFD_RELOC_ARM_LDRS_PC_G2
:
21560 case BFD_RELOC_ARM_LDRS_SB_G0
:
21561 case BFD_RELOC_ARM_LDRS_SB_G1
:
21562 case BFD_RELOC_ARM_LDRS_SB_G2
:
21563 gas_assert (!fixP
->fx_done
);
21564 if (!seg
->use_rela_p
)
21567 bfd_vma addend_abs
= abs (value
);
21569 /* Check that the absolute value of the addend can be
21570 encoded in 8 bits. */
21571 if (addend_abs
>= 0x100)
21572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21573 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21574 (unsigned long) addend_abs
);
21576 /* Extract the instruction. */
21577 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21579 /* If the addend is negative, clear bit 23 of the instruction.
21580 Otherwise set it. */
21582 insn
&= ~(1 << 23);
21586 /* Place the first four bits of the absolute value of the addend
21587 into the first 4 bits of the instruction, and the remaining
21588 four into bits 8 .. 11. */
21589 insn
&= 0xfffff0f0;
21590 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21592 /* Update the instruction. */
21593 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21597 case BFD_RELOC_ARM_LDC_PC_G0
:
21598 case BFD_RELOC_ARM_LDC_PC_G1
:
21599 case BFD_RELOC_ARM_LDC_PC_G2
:
21600 case BFD_RELOC_ARM_LDC_SB_G0
:
21601 case BFD_RELOC_ARM_LDC_SB_G1
:
21602 case BFD_RELOC_ARM_LDC_SB_G2
:
21603 gas_assert (!fixP
->fx_done
);
21604 if (!seg
->use_rela_p
)
21607 bfd_vma addend_abs
= abs (value
);
21609 /* Check that the absolute value of the addend is a multiple of
21610 four and, when divided by four, fits in 8 bits. */
21611 if (addend_abs
& 0x3)
21612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21613 _("bad offset 0x%08lX (must be word-aligned)"),
21614 (unsigned long) addend_abs
);
21616 if ((addend_abs
>> 2) > 0xff)
21617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21618 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21619 (unsigned long) addend_abs
);
21621 /* Extract the instruction. */
21622 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21624 /* If the addend is negative, clear bit 23 of the instruction.
21625 Otherwise set it. */
21627 insn
&= ~(1 << 23);
21631 /* Place the addend (divided by four) into the first eight
21632 bits of the instruction. */
21633 insn
&= 0xfffffff0;
21634 insn
|= addend_abs
>> 2;
21636 /* Update the instruction. */
21637 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21641 case BFD_RELOC_ARM_V4BX
:
21642 /* This will need to go in the object file. */
21646 case BFD_RELOC_UNUSED
:
21648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21649 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21653 /* Translate internal representation of relocation info to BFD target
21657 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21660 bfd_reloc_code_real_type code
;
21662 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21664 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21665 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21666 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21668 if (fixp
->fx_pcrel
)
21670 if (section
->use_rela_p
)
21671 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21673 fixp
->fx_offset
= reloc
->address
;
21675 reloc
->addend
= fixp
->fx_offset
;
21677 switch (fixp
->fx_r_type
)
21680 if (fixp
->fx_pcrel
)
21682 code
= BFD_RELOC_8_PCREL
;
21687 if (fixp
->fx_pcrel
)
21689 code
= BFD_RELOC_16_PCREL
;
21694 if (fixp
->fx_pcrel
)
21696 code
= BFD_RELOC_32_PCREL
;
21700 case BFD_RELOC_ARM_MOVW
:
21701 if (fixp
->fx_pcrel
)
21703 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21707 case BFD_RELOC_ARM_MOVT
:
21708 if (fixp
->fx_pcrel
)
21710 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21714 case BFD_RELOC_ARM_THUMB_MOVW
:
21715 if (fixp
->fx_pcrel
)
21717 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21721 case BFD_RELOC_ARM_THUMB_MOVT
:
21722 if (fixp
->fx_pcrel
)
21724 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21728 case BFD_RELOC_NONE
:
21729 case BFD_RELOC_ARM_PCREL_BRANCH
:
21730 case BFD_RELOC_ARM_PCREL_BLX
:
21731 case BFD_RELOC_RVA
:
21732 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21733 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21734 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21735 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21736 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21737 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21738 case BFD_RELOC_VTABLE_ENTRY
:
21739 case BFD_RELOC_VTABLE_INHERIT
:
21741 case BFD_RELOC_32_SECREL
:
21743 code
= fixp
->fx_r_type
;
21746 case BFD_RELOC_THUMB_PCREL_BLX
:
21748 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21749 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21752 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21755 case BFD_RELOC_ARM_LITERAL
:
21756 case BFD_RELOC_ARM_HWLITERAL
:
21757 /* If this is called then the a literal has
21758 been referenced across a section boundary. */
21759 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21760 _("literal referenced across section boundary"));
21764 case BFD_RELOC_ARM_TLS_CALL
:
21765 case BFD_RELOC_ARM_THM_TLS_CALL
:
21766 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21767 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21768 case BFD_RELOC_ARM_GOT32
:
21769 case BFD_RELOC_ARM_GOTOFF
:
21770 case BFD_RELOC_ARM_GOT_PREL
:
21771 case BFD_RELOC_ARM_PLT32
:
21772 case BFD_RELOC_ARM_TARGET1
:
21773 case BFD_RELOC_ARM_ROSEGREL32
:
21774 case BFD_RELOC_ARM_SBREL32
:
21775 case BFD_RELOC_ARM_PREL31
:
21776 case BFD_RELOC_ARM_TARGET2
:
21777 case BFD_RELOC_ARM_TLS_LE32
:
21778 case BFD_RELOC_ARM_TLS_LDO32
:
21779 case BFD_RELOC_ARM_PCREL_CALL
:
21780 case BFD_RELOC_ARM_PCREL_JUMP
:
21781 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21782 case BFD_RELOC_ARM_ALU_PC_G0
:
21783 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21784 case BFD_RELOC_ARM_ALU_PC_G1
:
21785 case BFD_RELOC_ARM_ALU_PC_G2
:
21786 case BFD_RELOC_ARM_LDR_PC_G0
:
21787 case BFD_RELOC_ARM_LDR_PC_G1
:
21788 case BFD_RELOC_ARM_LDR_PC_G2
:
21789 case BFD_RELOC_ARM_LDRS_PC_G0
:
21790 case BFD_RELOC_ARM_LDRS_PC_G1
:
21791 case BFD_RELOC_ARM_LDRS_PC_G2
:
21792 case BFD_RELOC_ARM_LDC_PC_G0
:
21793 case BFD_RELOC_ARM_LDC_PC_G1
:
21794 case BFD_RELOC_ARM_LDC_PC_G2
:
21795 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21796 case BFD_RELOC_ARM_ALU_SB_G0
:
21797 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21798 case BFD_RELOC_ARM_ALU_SB_G1
:
21799 case BFD_RELOC_ARM_ALU_SB_G2
:
21800 case BFD_RELOC_ARM_LDR_SB_G0
:
21801 case BFD_RELOC_ARM_LDR_SB_G1
:
21802 case BFD_RELOC_ARM_LDR_SB_G2
:
21803 case BFD_RELOC_ARM_LDRS_SB_G0
:
21804 case BFD_RELOC_ARM_LDRS_SB_G1
:
21805 case BFD_RELOC_ARM_LDRS_SB_G2
:
21806 case BFD_RELOC_ARM_LDC_SB_G0
:
21807 case BFD_RELOC_ARM_LDC_SB_G1
:
21808 case BFD_RELOC_ARM_LDC_SB_G2
:
21809 case BFD_RELOC_ARM_V4BX
:
21810 code
= fixp
->fx_r_type
;
21813 case BFD_RELOC_ARM_TLS_GOTDESC
:
21814 case BFD_RELOC_ARM_TLS_GD32
:
21815 case BFD_RELOC_ARM_TLS_IE32
:
21816 case BFD_RELOC_ARM_TLS_LDM32
:
21817 /* BFD will include the symbol's address in the addend.
21818 But we don't want that, so subtract it out again here. */
21819 if (!S_IS_COMMON (fixp
->fx_addsy
))
21820 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21821 code
= fixp
->fx_r_type
;
21825 case BFD_RELOC_ARM_IMMEDIATE
:
21826 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21827 _("internal relocation (type: IMMEDIATE) not fixed up"));
21830 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21831 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21832 _("ADRL used for a symbol not defined in the same file"));
21835 case BFD_RELOC_ARM_OFFSET_IMM
:
21836 if (section
->use_rela_p
)
21838 code
= fixp
->fx_r_type
;
21842 if (fixp
->fx_addsy
!= NULL
21843 && !S_IS_DEFINED (fixp
->fx_addsy
)
21844 && S_IS_LOCAL (fixp
->fx_addsy
))
21846 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21847 _("undefined local label `%s'"),
21848 S_GET_NAME (fixp
->fx_addsy
));
21852 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21853 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21860 switch (fixp
->fx_r_type
)
21862 case BFD_RELOC_NONE
: type
= "NONE"; break;
21863 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21864 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21865 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21866 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21867 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21868 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21869 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21870 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21871 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21872 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21873 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21874 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21875 default: type
= _("<unknown>"); break;
21877 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21878 _("cannot represent %s relocation in this object file format"),
21885 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21887 && fixp
->fx_addsy
== GOT_symbol
)
21889 code
= BFD_RELOC_ARM_GOTPC
;
21890 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21894 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21896 if (reloc
->howto
== NULL
)
21898 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21899 _("cannot represent %s relocation in this object file format"),
21900 bfd_get_reloc_code_name (code
));
21904 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21905 vtable entry to be used in the relocation's section offset. */
21906 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21907 reloc
->address
= fixp
->fx_offset
;
21912 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21915 cons_fix_new_arm (fragS
* frag
,
21920 bfd_reloc_code_real_type type
;
21924 FIXME: @@ Should look at CPU word size. */
21928 type
= BFD_RELOC_8
;
21931 type
= BFD_RELOC_16
;
21935 type
= BFD_RELOC_32
;
21938 type
= BFD_RELOC_64
;
21943 if (exp
->X_op
== O_secrel
)
21945 exp
->X_op
= O_symbol
;
21946 type
= BFD_RELOC_32_SECREL
;
21950 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21953 #if defined (OBJ_COFF)
21955 arm_validate_fix (fixS
* fixP
)
21957 /* If the destination of the branch is a defined symbol which does not have
21958 the THUMB_FUNC attribute, then we must be calling a function which has
21959 the (interfacearm) attribute. We look for the Thumb entry point to that
21960 function and change the branch to refer to that function instead. */
21961 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21962 && fixP
->fx_addsy
!= NULL
21963 && S_IS_DEFINED (fixP
->fx_addsy
)
21964 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21966 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21973 arm_force_relocation (struct fix
* fixp
)
21975 #if defined (OBJ_COFF) && defined (TE_PE)
21976 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21980 /* In case we have a call or a branch to a function in ARM ISA mode from
21981 a thumb function or vice-versa force the relocation. These relocations
21982 are cleared off for some cores that might have blx and simple transformations
21986 switch (fixp
->fx_r_type
)
21988 case BFD_RELOC_ARM_PCREL_JUMP
:
21989 case BFD_RELOC_ARM_PCREL_CALL
:
21990 case BFD_RELOC_THUMB_PCREL_BLX
:
21991 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21995 case BFD_RELOC_ARM_PCREL_BLX
:
21996 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21997 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21998 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21999 if (ARM_IS_FUNC (fixp
->fx_addsy
))
22008 /* Resolve these relocations even if the symbol is extern or weak.
22009 Technically this is probably wrong due to symbol preemption.
22010 In practice these relocations do not have enough range to be useful
22011 at dynamic link time, and some code (e.g. in the Linux kernel)
22012 expects these references to be resolved. */
22013 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
22014 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
22015 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
22016 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
22017 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22018 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
22019 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
22020 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
22021 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22022 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
22023 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
22024 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
22025 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
22026 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
22029 /* Always leave these relocations for the linker. */
22030 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22031 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22032 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22035 /* Always generate relocations against function symbols. */
22036 if (fixp
->fx_r_type
== BFD_RELOC_32
22038 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22041 return generic_force_reloc (fixp
);
22044 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22045 /* Relocations against function names must be left unadjusted,
22046 so that the linker can use this information to generate interworking
22047 stubs. The MIPS version of this function
22048 also prevents relocations that are mips-16 specific, but I do not
22049 know why it does this.
22052 There is one other problem that ought to be addressed here, but
22053 which currently is not: Taking the address of a label (rather
22054 than a function) and then later jumping to that address. Such
22055 addresses also ought to have their bottom bit set (assuming that
22056 they reside in Thumb code), but at the moment they will not. */
22059 arm_fix_adjustable (fixS
* fixP
)
22061 if (fixP
->fx_addsy
== NULL
)
22064 /* Preserve relocations against symbols with function type. */
22065 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
22068 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
22069 && fixP
->fx_subsy
== NULL
)
22072 /* We need the symbol name for the VTABLE entries. */
22073 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
22074 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22077 /* Don't allow symbols to be discarded on GOT related relocs. */
22078 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
22079 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
22080 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
22081 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
22082 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
22083 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
22084 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
22085 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
22086 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
22087 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
22088 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
22089 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
22090 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
22091 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
22094 /* Similarly for group relocations. */
22095 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22096 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22097 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22100 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22101 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
22102 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22103 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
22104 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
22105 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22106 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
22107 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
22108 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22113 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22118 elf32_arm_target_format (void)
22121 return (target_big_endian
22122 ? "elf32-bigarm-symbian"
22123 : "elf32-littlearm-symbian");
22124 #elif defined (TE_VXWORKS)
22125 return (target_big_endian
22126 ? "elf32-bigarm-vxworks"
22127 : "elf32-littlearm-vxworks");
22129 if (target_big_endian
)
22130 return "elf32-bigarm";
22132 return "elf32-littlearm";
22137 armelf_frob_symbol (symbolS
* symp
,
22140 elf_frob_symbol (symp
, puntp
);
22144 /* MD interface: Finalization. */
22149 literal_pool
* pool
;
22151 /* Ensure that all the IT blocks are properly closed. */
22152 check_it_blocks_finished ();
22154 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22156 /* Put it at the end of the relevant section. */
22157 subseg_set (pool
->section
, pool
->sub_section
);
22159 arm_elf_change_section ();
22166 /* Remove any excess mapping symbols generated for alignment frags in
22167 SEC. We may have created a mapping symbol before a zero byte
22168 alignment; remove it if there's a mapping symbol after the
22171 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22172 void *dummy ATTRIBUTE_UNUSED
)
22174 segment_info_type
*seginfo
= seg_info (sec
);
22177 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22180 for (fragp
= seginfo
->frchainP
->frch_root
;
22182 fragp
= fragp
->fr_next
)
22184 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22185 fragS
*next
= fragp
->fr_next
;
22187 /* Variable-sized frags have been converted to fixed size by
22188 this point. But if this was variable-sized to start with,
22189 there will be a fixed-size frag after it. So don't handle
22191 if (sym
== NULL
|| next
== NULL
)
22194 if (S_GET_VALUE (sym
) < next
->fr_address
)
22195 /* Not at the end of this frag. */
22197 know (S_GET_VALUE (sym
) == next
->fr_address
);
22201 if (next
->tc_frag_data
.first_map
!= NULL
)
22203 /* Next frag starts with a mapping symbol. Discard this
22205 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22209 if (next
->fr_next
== NULL
)
22211 /* This mapping symbol is at the end of the section. Discard
22213 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22214 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22218 /* As long as we have empty frags without any mapping symbols,
22220 /* If the next frag is non-empty and does not start with a
22221 mapping symbol, then this mapping symbol is required. */
22222 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22225 next
= next
->fr_next
;
22227 while (next
!= NULL
);
22232 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22236 arm_adjust_symtab (void)
22241 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22243 if (ARM_IS_THUMB (sym
))
22245 if (THUMB_IS_FUNC (sym
))
22247 /* Mark the symbol as a Thumb function. */
22248 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22249 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22250 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22252 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22253 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22255 as_bad (_("%s: unexpected function type: %d"),
22256 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22258 else switch (S_GET_STORAGE_CLASS (sym
))
22261 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22264 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22267 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22275 if (ARM_IS_INTERWORK (sym
))
22276 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22283 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22285 if (ARM_IS_THUMB (sym
))
22287 elf_symbol_type
* elf_sym
;
22289 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22290 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22292 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22293 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22295 /* If it's a .thumb_func, declare it as so,
22296 otherwise tag label as .code 16. */
22297 if (THUMB_IS_FUNC (sym
))
22298 elf_sym
->internal_elf_sym
.st_target_internal
22299 = ST_BRANCH_TO_THUMB
;
22300 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22301 elf_sym
->internal_elf_sym
.st_info
=
22302 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22307 /* Remove any overlapping mapping symbols generated by alignment frags. */
22308 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22309 /* Now do generic ELF adjustments. */
22310 elf_adjust_symtab ();
22314 /* MD interface: Initialization. */
22317 set_constant_flonums (void)
22321 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22322 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22326 /* Auto-select Thumb mode if it's the only available instruction set for the
22327 given architecture. */
22330 autoselect_thumb_from_cpu_variant (void)
22332 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22333 opcode_select (16);
22342 if ( (arm_ops_hsh
= hash_new ()) == NULL
22343 || (arm_cond_hsh
= hash_new ()) == NULL
22344 || (arm_shift_hsh
= hash_new ()) == NULL
22345 || (arm_psr_hsh
= hash_new ()) == NULL
22346 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22347 || (arm_reg_hsh
= hash_new ()) == NULL
22348 || (arm_reloc_hsh
= hash_new ()) == NULL
22349 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22350 as_fatal (_("virtual memory exhausted"));
22352 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22353 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22354 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22355 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22356 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22357 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22358 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22359 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22360 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22361 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22362 (void *) (v7m_psrs
+ i
));
22363 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22364 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22366 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22368 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22369 (void *) (barrier_opt_names
+ i
));
22371 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22372 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22375 set_constant_flonums ();
22377 /* Set the cpu variant based on the command-line options. We prefer
22378 -mcpu= over -march= if both are set (as for GCC); and we prefer
22379 -mfpu= over any other way of setting the floating point unit.
22380 Use of legacy options with new options are faulted. */
22383 if (mcpu_cpu_opt
|| march_cpu_opt
)
22384 as_bad (_("use of old and new-style options to set CPU type"));
22386 mcpu_cpu_opt
= legacy_cpu
;
22388 else if (!mcpu_cpu_opt
)
22389 mcpu_cpu_opt
= march_cpu_opt
;
22394 as_bad (_("use of old and new-style options to set FPU type"));
22396 mfpu_opt
= legacy_fpu
;
22398 else if (!mfpu_opt
)
22400 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22401 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22402 /* Some environments specify a default FPU. If they don't, infer it
22403 from the processor. */
22405 mfpu_opt
= mcpu_fpu_opt
;
22407 mfpu_opt
= march_fpu_opt
;
22409 mfpu_opt
= &fpu_default
;
22415 if (mcpu_cpu_opt
!= NULL
)
22416 mfpu_opt
= &fpu_default
;
22417 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22418 mfpu_opt
= &fpu_arch_vfp_v2
;
22420 mfpu_opt
= &fpu_arch_fpa
;
22426 mcpu_cpu_opt
= &cpu_default
;
22427 selected_cpu
= cpu_default
;
22431 selected_cpu
= *mcpu_cpu_opt
;
22433 mcpu_cpu_opt
= &arm_arch_any
;
22436 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22438 autoselect_thumb_from_cpu_variant ();
22440 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22442 #if defined OBJ_COFF || defined OBJ_ELF
22444 unsigned int flags
= 0;
22446 #if defined OBJ_ELF
22447 flags
= meabi_flags
;
22449 switch (meabi_flags
)
22451 case EF_ARM_EABI_UNKNOWN
:
22453 /* Set the flags in the private structure. */
22454 if (uses_apcs_26
) flags
|= F_APCS26
;
22455 if (support_interwork
) flags
|= F_INTERWORK
;
22456 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22457 if (pic_code
) flags
|= F_PIC
;
22458 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22459 flags
|= F_SOFT_FLOAT
;
22461 switch (mfloat_abi_opt
)
22463 case ARM_FLOAT_ABI_SOFT
:
22464 case ARM_FLOAT_ABI_SOFTFP
:
22465 flags
|= F_SOFT_FLOAT
;
22468 case ARM_FLOAT_ABI_HARD
:
22469 if (flags
& F_SOFT_FLOAT
)
22470 as_bad (_("hard-float conflicts with specified fpu"));
22474 /* Using pure-endian doubles (even if soft-float). */
22475 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22476 flags
|= F_VFP_FLOAT
;
22478 #if defined OBJ_ELF
22479 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22480 flags
|= EF_ARM_MAVERICK_FLOAT
;
22483 case EF_ARM_EABI_VER4
:
22484 case EF_ARM_EABI_VER5
:
22485 /* No additional flags to set. */
22492 bfd_set_private_flags (stdoutput
, flags
);
22494 /* We have run out flags in the COFF header to encode the
22495 status of ATPCS support, so instead we create a dummy,
22496 empty, debug section called .arm.atpcs. */
22501 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22505 bfd_set_section_flags
22506 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22507 bfd_set_section_size (stdoutput
, sec
, 0);
22508 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22514 /* Record the CPU type as well. */
22515 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22516 mach
= bfd_mach_arm_iWMMXt2
;
22517 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22518 mach
= bfd_mach_arm_iWMMXt
;
22519 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22520 mach
= bfd_mach_arm_XScale
;
22521 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22522 mach
= bfd_mach_arm_ep9312
;
22523 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22524 mach
= bfd_mach_arm_5TE
;
22525 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22527 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22528 mach
= bfd_mach_arm_5T
;
22530 mach
= bfd_mach_arm_5
;
22532 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22534 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22535 mach
= bfd_mach_arm_4T
;
22537 mach
= bfd_mach_arm_4
;
22539 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22540 mach
= bfd_mach_arm_3M
;
22541 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22542 mach
= bfd_mach_arm_3
;
22543 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22544 mach
= bfd_mach_arm_2a
;
22545 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22546 mach
= bfd_mach_arm_2
;
22548 mach
= bfd_mach_arm_unknown
;
22550 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22553 /* Command line processing. */
22556 Invocation line includes a switch not recognized by the base assembler.
22557 See if it's a processor-specific option.
22559 This routine is somewhat complicated by the need for backwards
22560 compatibility (since older releases of gcc can't be changed).
22561 The new options try to make the interface as compatible as
22564 New options (supported) are:
22566 -mcpu=<cpu name> Assemble for selected processor
22567 -march=<architecture name> Assemble for selected architecture
22568 -mfpu=<fpu architecture> Assemble for selected FPU.
22569 -EB/-mbig-endian Big-endian
22570 -EL/-mlittle-endian Little-endian
22571 -k Generate PIC code
22572 -mthumb Start in Thumb mode
22573 -mthumb-interwork Code supports ARM/Thumb interworking
22575 -m[no-]warn-deprecated Warn about deprecated features
22577 For now we will also provide support for:
22579 -mapcs-32 32-bit Program counter
22580 -mapcs-26 26-bit Program counter
22581 -macps-float Floats passed in FP registers
22582 -mapcs-reentrant Reentrant code
22584 (sometime these will probably be replaced with -mapcs=<list of options>
22585 and -matpcs=<list of options>)
22587 The remaining options are only supported for back-wards compatibility.
22588 Cpu variants, the arm part is optional:
22589 -m[arm]1 Currently not supported.
22590 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22591 -m[arm]3 Arm 3 processor
22592 -m[arm]6[xx], Arm 6 processors
22593 -m[arm]7[xx][t][[d]m] Arm 7 processors
22594 -m[arm]8[10] Arm 8 processors
22595 -m[arm]9[20][tdmi] Arm 9 processors
22596 -mstrongarm[110[0]] StrongARM processors
22597 -mxscale XScale processors
22598 -m[arm]v[2345[t[e]]] Arm architectures
22599 -mall All (except the ARM1)
22601 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22602 -mfpe-old (No float load/store multiples)
22603 -mvfpxd VFP Single precision
22605 -mno-fpu Disable all floating point instructions
22607 The following CPU names are recognized:
22608 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22609 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22610 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22611 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22612 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22613 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22614 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22618 const char * md_shortopts
= "m:k";
22620 #ifdef ARM_BI_ENDIAN
22621 #define OPTION_EB (OPTION_MD_BASE + 0)
22622 #define OPTION_EL (OPTION_MD_BASE + 1)
22624 #if TARGET_BYTES_BIG_ENDIAN
22625 #define OPTION_EB (OPTION_MD_BASE + 0)
22627 #define OPTION_EL (OPTION_MD_BASE + 1)
22630 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22632 struct option md_longopts
[] =
22635 {"EB", no_argument
, NULL
, OPTION_EB
},
22638 {"EL", no_argument
, NULL
, OPTION_EL
},
22640 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22641 {NULL
, no_argument
, NULL
, 0}
22644 size_t md_longopts_size
= sizeof (md_longopts
);
22646 struct arm_option_table
22648 char *option
; /* Option name to match. */
22649 char *help
; /* Help information. */
22650 int *var
; /* Variable to change. */
22651 int value
; /* What to change it to. */
22652 char *deprecated
; /* If non-null, print this message. */
22655 struct arm_option_table arm_opts
[] =
22657 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22658 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22659 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22660 &support_interwork
, 1, NULL
},
22661 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22662 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22663 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22665 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22666 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22667 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22668 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22671 /* These are recognized by the assembler, but have no affect on code. */
22672 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22673 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22675 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22676 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22677 &warn_on_deprecated
, 0, NULL
},
22678 {NULL
, NULL
, NULL
, 0, NULL
}
22681 struct arm_legacy_option_table
22683 char *option
; /* Option name to match. */
22684 const arm_feature_set
**var
; /* Variable to change. */
22685 const arm_feature_set value
; /* What to change it to. */
22686 char *deprecated
; /* If non-null, print this message. */
22689 const struct arm_legacy_option_table arm_legacy_opts
[] =
22691 /* DON'T add any new processors to this list -- we want the whole list
22692 to go away... Add them to the processors table instead. */
22693 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22694 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22695 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22696 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22697 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22698 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22699 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22700 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22701 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22702 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22703 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22704 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22705 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22706 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22707 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22708 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22709 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22710 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22711 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22712 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22713 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22714 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22715 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22716 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22717 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22718 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22719 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22720 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22721 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22722 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22723 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22724 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22725 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22726 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22727 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22728 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22729 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22730 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22731 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22732 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22733 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22734 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22735 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22736 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22737 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22738 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22739 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22740 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22741 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22742 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22743 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22744 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22745 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22746 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22747 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22748 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22749 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22750 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22751 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22752 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22753 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22754 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22755 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22756 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22757 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22758 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22759 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22760 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22761 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22762 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22763 N_("use -mcpu=strongarm110")},
22764 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22765 N_("use -mcpu=strongarm1100")},
22766 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22767 N_("use -mcpu=strongarm1110")},
22768 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22769 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22770 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22772 /* Architecture variants -- don't add any more to this list either. */
22773 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22774 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22775 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22776 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22777 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22778 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22779 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22780 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22781 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22782 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22783 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22784 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22785 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22786 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22787 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22788 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22789 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22790 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22792 /* Floating point variants -- don't add any more to this list either. */
22793 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22794 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22795 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22796 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22797 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22799 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22802 struct arm_cpu_option_table
22805 const arm_feature_set value
;
22806 /* For some CPUs we assume an FPU unless the user explicitly sets
22808 const arm_feature_set default_fpu
;
22809 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22811 const char *canonical_name
;
22814 /* This list should, at a minimum, contain all the cpu names
22815 recognized by GCC. */
22816 static const struct arm_cpu_option_table arm_cpus
[] =
22818 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22819 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22820 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22821 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22822 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22823 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22824 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22825 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22826 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22827 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22828 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22829 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22830 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22831 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22832 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22833 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22834 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22835 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22836 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22837 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22838 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22839 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22840 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22841 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22842 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22843 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22844 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22845 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22846 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22847 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22848 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22849 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22850 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22851 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22852 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22853 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22854 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22855 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22856 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22857 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22858 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22859 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22860 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22861 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22862 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22863 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22864 /* For V5 or later processors we default to using VFP; but the user
22865 should really set the FPU type explicitly. */
22866 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22867 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22868 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22869 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22870 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22871 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22872 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22873 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22874 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22875 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22876 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22877 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22878 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22879 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22880 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22881 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22882 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22883 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22884 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22885 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22886 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22887 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22888 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22889 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22890 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22891 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22892 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22893 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22894 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22895 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22896 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22897 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22898 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22899 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22900 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22901 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22902 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22903 FPU_NONE
, "Cortex-A5"},
22904 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22905 ARM_FEATURE (0, FPU_VFP_V3
22906 | FPU_NEON_EXT_V1
),
22908 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22909 ARM_FEATURE (0, FPU_VFP_V3
22910 | FPU_NEON_EXT_V1
),
22912 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22913 FPU_ARCH_NEON_VFP_V4
,
22915 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22916 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22918 {"cortex-r5", ARM_ARCH_V7R_IDIV
,
22919 FPU_NONE
, "Cortex-R5"},
22920 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22921 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22922 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22923 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22924 /* ??? XSCALE is really an architecture. */
22925 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22926 /* ??? iwmmxt is not a processor. */
22927 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22928 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22929 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22931 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22932 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22935 struct arm_arch_option_table
22938 const arm_feature_set value
;
22939 const arm_feature_set default_fpu
;
22942 /* This list should, at a minimum, contain all the architecture names
22943 recognized by GCC. */
22944 static const struct arm_arch_option_table arm_archs
[] =
22946 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22947 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22948 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22949 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22950 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22951 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22952 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22953 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22954 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22955 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22956 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22957 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22958 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22959 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22960 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22961 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22962 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22963 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22964 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22965 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22966 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22967 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22968 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22969 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22970 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22971 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22972 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22973 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22974 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22975 /* The official spelling of the ARMv7 profile variants is the dashed form.
22976 Accept the non-dashed form for compatibility with old toolchains. */
22977 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22978 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22979 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22980 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22981 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22982 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22983 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22984 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22985 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22986 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22987 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22990 /* ISA extensions in the co-processor and main instruction set space. */
22991 struct arm_option_extension_value_table
22994 const arm_feature_set value
;
22995 const arm_feature_set allowed_archs
;
22998 /* The following table must be in alphabetical order with a NULL last entry.
23000 static const struct arm_option_extension_value_table arm_extensions
[] =
23002 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23003 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
23004 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
23005 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
23006 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
23007 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
23008 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
23009 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
23010 ARM_FEATURE (ARM_EXT_V6M
, 0)},
23011 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
23012 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
23013 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23014 ARM_FEATURE (ARM_EXT_V7A
, 0)},
23015 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
23016 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23019 /* ISA floating-point and Advanced SIMD extensions. */
23020 struct arm_option_fpu_value_table
23023 const arm_feature_set value
;
23026 /* This list should, at a minimum, contain all the fpu names
23027 recognized by GCC. */
23028 static const struct arm_option_fpu_value_table arm_fpus
[] =
23030 {"softfpa", FPU_NONE
},
23031 {"fpe", FPU_ARCH_FPE
},
23032 {"fpe2", FPU_ARCH_FPE
},
23033 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
23034 {"fpa", FPU_ARCH_FPA
},
23035 {"fpa10", FPU_ARCH_FPA
},
23036 {"fpa11", FPU_ARCH_FPA
},
23037 {"arm7500fe", FPU_ARCH_FPA
},
23038 {"softvfp", FPU_ARCH_VFP
},
23039 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
23040 {"vfp", FPU_ARCH_VFP_V2
},
23041 {"vfp9", FPU_ARCH_VFP_V2
},
23042 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
23043 {"vfp10", FPU_ARCH_VFP_V2
},
23044 {"vfp10-r0", FPU_ARCH_VFP_V1
},
23045 {"vfpxd", FPU_ARCH_VFP_V1xD
},
23046 {"vfpv2", FPU_ARCH_VFP_V2
},
23047 {"vfpv3", FPU_ARCH_VFP_V3
},
23048 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
23049 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
23050 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
23051 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
23052 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
23053 {"arm1020t", FPU_ARCH_VFP_V1
},
23054 {"arm1020e", FPU_ARCH_VFP_V2
},
23055 {"arm1136jfs", FPU_ARCH_VFP_V2
},
23056 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
23057 {"maverick", FPU_ARCH_MAVERICK
},
23058 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
23059 {"neon-fp16", FPU_ARCH_NEON_FP16
},
23060 {"vfpv4", FPU_ARCH_VFP_V4
},
23061 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
23062 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
23063 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
23064 {NULL
, ARM_ARCH_NONE
}
23067 struct arm_option_value_table
23073 static const struct arm_option_value_table arm_float_abis
[] =
23075 {"hard", ARM_FLOAT_ABI_HARD
},
23076 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
23077 {"soft", ARM_FLOAT_ABI_SOFT
},
23082 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23083 static const struct arm_option_value_table arm_eabis
[] =
23085 {"gnu", EF_ARM_EABI_UNKNOWN
},
23086 {"4", EF_ARM_EABI_VER4
},
23087 {"5", EF_ARM_EABI_VER5
},
23092 struct arm_long_option_table
23094 char * option
; /* Substring to match. */
23095 char * help
; /* Help information. */
23096 int (* func
) (char * subopt
); /* Function to decode sub-option. */
23097 char * deprecated
; /* If non-null, print this message. */
23101 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
23103 arm_feature_set
*ext_set
= (arm_feature_set
*)
23104 xmalloc (sizeof (arm_feature_set
));
23106 /* We insist on extensions being specified in alphabetical order, and with
23107 extensions being added before being removed. We achieve this by having
23108 the global ARM_EXTENSIONS table in alphabetical order, and using the
23109 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23110 or removing it (0) and only allowing it to change in the order
23112 const struct arm_option_extension_value_table
* opt
= NULL
;
23113 int adding_value
= -1;
23115 /* Copy the feature set, so that we can modify it. */
23116 *ext_set
= **opt_p
;
23119 while (str
!= NULL
&& *str
!= 0)
23126 as_bad (_("invalid architectural extension"));
23131 ext
= strchr (str
, '+');
23134 optlen
= ext
- str
;
23136 optlen
= strlen (str
);
23139 && strncmp (str
, "no", 2) == 0)
23141 if (adding_value
!= 0)
23144 opt
= arm_extensions
;
23150 else if (optlen
> 0)
23152 if (adding_value
== -1)
23155 opt
= arm_extensions
;
23157 else if (adding_value
!= 1)
23159 as_bad (_("must specify extensions to add before specifying "
23160 "those to remove"));
23167 as_bad (_("missing architectural extension"));
23171 gas_assert (adding_value
!= -1);
23172 gas_assert (opt
!= NULL
);
23174 /* Scan over the options table trying to find an exact match. */
23175 for (; opt
->name
!= NULL
; opt
++)
23176 if (strncmp (opt
->name
, str
, optlen
) == 0
23177 && strlen (opt
->name
) == optlen
)
23179 /* Check we can apply the extension to this architecture. */
23180 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23182 as_bad (_("extension does not apply to the base architecture"));
23186 /* Add or remove the extension. */
23188 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23190 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23195 if (opt
->name
== NULL
)
23197 /* Did we fail to find an extension because it wasn't specified in
23198 alphabetical order, or because it does not exist? */
23200 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23201 if (strncmp (opt
->name
, str
, optlen
) == 0)
23204 if (opt
->name
== NULL
)
23205 as_bad (_("unknown architectural extension `%s'"), str
);
23207 as_bad (_("architectural extensions must be specified in "
23208 "alphabetical order"));
23214 /* We should skip the extension we've just matched the next time
23226 arm_parse_cpu (char * str
)
23228 const struct arm_cpu_option_table
* opt
;
23229 char * ext
= strchr (str
, '+');
23233 optlen
= ext
- str
;
23235 optlen
= strlen (str
);
23239 as_bad (_("missing cpu name `%s'"), str
);
23243 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23244 if (strncmp (opt
->name
, str
, optlen
) == 0)
23246 mcpu_cpu_opt
= &opt
->value
;
23247 mcpu_fpu_opt
= &opt
->default_fpu
;
23248 if (opt
->canonical_name
)
23249 strcpy (selected_cpu_name
, opt
->canonical_name
);
23254 for (i
= 0; i
< optlen
; i
++)
23255 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23256 selected_cpu_name
[i
] = 0;
23260 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23265 as_bad (_("unknown cpu `%s'"), str
);
23270 arm_parse_arch (char * str
)
23272 const struct arm_arch_option_table
*opt
;
23273 char *ext
= strchr (str
, '+');
23277 optlen
= ext
- str
;
23279 optlen
= strlen (str
);
23283 as_bad (_("missing architecture name `%s'"), str
);
23287 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23288 if (strncmp (opt
->name
, str
, optlen
) == 0)
23290 march_cpu_opt
= &opt
->value
;
23291 march_fpu_opt
= &opt
->default_fpu
;
23292 strcpy (selected_cpu_name
, opt
->name
);
23295 return arm_parse_extension (ext
, &march_cpu_opt
);
23300 as_bad (_("unknown architecture `%s'\n"), str
);
23305 arm_parse_fpu (char * str
)
23307 const struct arm_option_fpu_value_table
* opt
;
23309 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23310 if (streq (opt
->name
, str
))
23312 mfpu_opt
= &opt
->value
;
23316 as_bad (_("unknown floating point format `%s'\n"), str
);
23321 arm_parse_float_abi (char * str
)
23323 const struct arm_option_value_table
* opt
;
23325 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23326 if (streq (opt
->name
, str
))
23328 mfloat_abi_opt
= opt
->value
;
23332 as_bad (_("unknown floating point abi `%s'\n"), str
);
23338 arm_parse_eabi (char * str
)
23340 const struct arm_option_value_table
*opt
;
23342 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23343 if (streq (opt
->name
, str
))
23345 meabi_flags
= opt
->value
;
23348 as_bad (_("unknown EABI `%s'\n"), str
);
23354 arm_parse_it_mode (char * str
)
23356 bfd_boolean ret
= TRUE
;
23358 if (streq ("arm", str
))
23359 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23360 else if (streq ("thumb", str
))
23361 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23362 else if (streq ("always", str
))
23363 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23364 else if (streq ("never", str
))
23365 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23368 as_bad (_("unknown implicit IT mode `%s', should be "\
23369 "arm, thumb, always, or never."), str
);
23376 struct arm_long_option_table arm_long_opts
[] =
23378 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23379 arm_parse_cpu
, NULL
},
23380 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23381 arm_parse_arch
, NULL
},
23382 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23383 arm_parse_fpu
, NULL
},
23384 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23385 arm_parse_float_abi
, NULL
},
23387 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23388 arm_parse_eabi
, NULL
},
23390 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23391 arm_parse_it_mode
, NULL
},
23392 {NULL
, NULL
, 0, NULL
}
23396 md_parse_option (int c
, char * arg
)
23398 struct arm_option_table
*opt
;
23399 const struct arm_legacy_option_table
*fopt
;
23400 struct arm_long_option_table
*lopt
;
23406 target_big_endian
= 1;
23412 target_big_endian
= 0;
23416 case OPTION_FIX_V4BX
:
23421 /* Listing option. Just ignore these, we don't support additional
23426 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23428 if (c
== opt
->option
[0]
23429 && ((arg
== NULL
&& opt
->option
[1] == 0)
23430 || streq (arg
, opt
->option
+ 1)))
23432 /* If the option is deprecated, tell the user. */
23433 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23434 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23435 arg
? arg
: "", _(opt
->deprecated
));
23437 if (opt
->var
!= NULL
)
23438 *opt
->var
= opt
->value
;
23444 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23446 if (c
== fopt
->option
[0]
23447 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23448 || streq (arg
, fopt
->option
+ 1)))
23450 /* If the option is deprecated, tell the user. */
23451 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23452 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23453 arg
? arg
: "", _(fopt
->deprecated
));
23455 if (fopt
->var
!= NULL
)
23456 *fopt
->var
= &fopt
->value
;
23462 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23464 /* These options are expected to have an argument. */
23465 if (c
== lopt
->option
[0]
23467 && strncmp (arg
, lopt
->option
+ 1,
23468 strlen (lopt
->option
+ 1)) == 0)
23470 /* If the option is deprecated, tell the user. */
23471 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23472 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23473 _(lopt
->deprecated
));
23475 /* Call the sup-option parser. */
23476 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23487 md_show_usage (FILE * fp
)
23489 struct arm_option_table
*opt
;
23490 struct arm_long_option_table
*lopt
;
23492 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23494 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23495 if (opt
->help
!= NULL
)
23496 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23498 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23499 if (lopt
->help
!= NULL
)
23500 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23504 -EB assemble code for a big-endian cpu\n"));
23509 -EL assemble code for a little-endian cpu\n"));
23513 --fix-v4bx Allow BX in ARMv4 code\n"));
23521 arm_feature_set flags
;
23522 } cpu_arch_ver_table
;
23524 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23525 least features first. */
23526 static const cpu_arch_ver_table cpu_arch_ver
[] =
23532 {4, ARM_ARCH_V5TE
},
23533 {5, ARM_ARCH_V5TEJ
},
23537 {11, ARM_ARCH_V6M
},
23538 {12, ARM_ARCH_V6SM
},
23539 {8, ARM_ARCH_V6T2
},
23540 {10, ARM_ARCH_V7A
},
23541 {10, ARM_ARCH_V7R
},
23542 {10, ARM_ARCH_V7M
},
23546 /* Set an attribute if it has not already been set by the user. */
23548 aeabi_set_attribute_int (int tag
, int value
)
23551 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23552 || !attributes_set_explicitly
[tag
])
23553 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23557 aeabi_set_attribute_string (int tag
, const char *value
)
23560 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23561 || !attributes_set_explicitly
[tag
])
23562 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23565 /* Set the public EABI object attributes. */
23567 aeabi_set_public_attributes (void)
23571 arm_feature_set flags
;
23572 arm_feature_set tmp
;
23573 const cpu_arch_ver_table
*p
;
23575 /* Choose the architecture based on the capabilities of the requested cpu
23576 (if any) and/or the instructions actually used. */
23577 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23578 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23579 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23580 /*Allow the user to override the reported architecture. */
23583 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23584 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23587 /* We need to make sure that the attributes do not identify us as v6S-M
23588 when the only v6S-M feature in use is the Operating System Extensions. */
23589 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23590 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23591 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23595 for (p
= cpu_arch_ver
; p
->val
; p
++)
23597 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23600 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23604 /* The table lookup above finds the last architecture to contribute
23605 a new feature. Unfortunately, Tag13 is a subset of the union of
23606 v6T2 and v7-M, so it is never seen as contributing a new feature.
23607 We can not search for the last entry which is entirely used,
23608 because if no CPU is specified we build up only those flags
23609 actually used. Perhaps we should separate out the specified
23610 and implicit cases. Avoid taking this path for -march=all by
23611 checking for contradictory v7-A / v7-M features. */
23613 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23614 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23615 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23618 /* Tag_CPU_name. */
23619 if (selected_cpu_name
[0])
23623 q
= selected_cpu_name
;
23624 if (strncmp (q
, "armv", 4) == 0)
23629 for (i
= 0; q
[i
]; i
++)
23630 q
[i
] = TOUPPER (q
[i
]);
23632 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23635 /* Tag_CPU_arch. */
23636 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23638 /* Tag_CPU_arch_profile. */
23639 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23640 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23641 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23642 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23643 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23644 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23646 /* Tag_ARM_ISA_use. */
23647 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23649 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23651 /* Tag_THUMB_ISA_use. */
23652 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23654 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23655 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23657 /* Tag_VFP_arch. */
23658 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23659 aeabi_set_attribute_int (Tag_VFP_arch
,
23660 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23662 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23663 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23664 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23665 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23666 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23667 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23668 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23669 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23670 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23672 /* Tag_ABI_HardFP_use. */
23673 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23674 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23675 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23677 /* Tag_WMMX_arch. */
23678 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23679 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23680 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23681 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23683 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23684 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23685 aeabi_set_attribute_int
23686 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23689 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23690 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23691 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23694 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23695 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23696 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23697 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23699 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23701 /* Tag_MP_extension_use. */
23702 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23703 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23705 /* Tag Virtualization_use. */
23706 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23708 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23711 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23714 /* Add the default contents for the .ARM.attributes section. */
23718 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23721 aeabi_set_public_attributes ();
23723 #endif /* OBJ_ELF */
23726 /* Parse a .cpu directive. */
23729 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23731 const struct arm_cpu_option_table
*opt
;
23735 name
= input_line_pointer
;
23736 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23737 input_line_pointer
++;
23738 saved_char
= *input_line_pointer
;
23739 *input_line_pointer
= 0;
23741 /* Skip the first "all" entry. */
23742 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23743 if (streq (opt
->name
, name
))
23745 mcpu_cpu_opt
= &opt
->value
;
23746 selected_cpu
= opt
->value
;
23747 if (opt
->canonical_name
)
23748 strcpy (selected_cpu_name
, opt
->canonical_name
);
23752 for (i
= 0; opt
->name
[i
]; i
++)
23753 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23754 selected_cpu_name
[i
] = 0;
23756 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23757 *input_line_pointer
= saved_char
;
23758 demand_empty_rest_of_line ();
23761 as_bad (_("unknown cpu `%s'"), name
);
23762 *input_line_pointer
= saved_char
;
23763 ignore_rest_of_line ();
23767 /* Parse a .arch directive. */
23770 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23772 const struct arm_arch_option_table
*opt
;
23776 name
= input_line_pointer
;
23777 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23778 input_line_pointer
++;
23779 saved_char
= *input_line_pointer
;
23780 *input_line_pointer
= 0;
23782 /* Skip the first "all" entry. */
23783 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23784 if (streq (opt
->name
, name
))
23786 mcpu_cpu_opt
= &opt
->value
;
23787 selected_cpu
= opt
->value
;
23788 strcpy (selected_cpu_name
, opt
->name
);
23789 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23790 *input_line_pointer
= saved_char
;
23791 demand_empty_rest_of_line ();
23795 as_bad (_("unknown architecture `%s'\n"), name
);
23796 *input_line_pointer
= saved_char
;
23797 ignore_rest_of_line ();
23801 /* Parse a .object_arch directive. */
23804 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23806 const struct arm_arch_option_table
*opt
;
23810 name
= input_line_pointer
;
23811 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23812 input_line_pointer
++;
23813 saved_char
= *input_line_pointer
;
23814 *input_line_pointer
= 0;
23816 /* Skip the first "all" entry. */
23817 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23818 if (streq (opt
->name
, name
))
23820 object_arch
= &opt
->value
;
23821 *input_line_pointer
= saved_char
;
23822 demand_empty_rest_of_line ();
23826 as_bad (_("unknown architecture `%s'\n"), name
);
23827 *input_line_pointer
= saved_char
;
23828 ignore_rest_of_line ();
23831 /* Parse a .arch_extension directive. */
23834 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23836 const struct arm_option_extension_value_table
*opt
;
23839 int adding_value
= 1;
23841 name
= input_line_pointer
;
23842 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23843 input_line_pointer
++;
23844 saved_char
= *input_line_pointer
;
23845 *input_line_pointer
= 0;
23847 if (strlen (name
) >= 2
23848 && strncmp (name
, "no", 2) == 0)
23854 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23855 if (streq (opt
->name
, name
))
23857 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23859 as_bad (_("architectural extension `%s' is not allowed for the "
23860 "current base architecture"), name
);
23865 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23867 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23869 mcpu_cpu_opt
= &selected_cpu
;
23870 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23871 *input_line_pointer
= saved_char
;
23872 demand_empty_rest_of_line ();
23876 if (opt
->name
== NULL
)
23877 as_bad (_("unknown architecture `%s'\n"), name
);
23879 *input_line_pointer
= saved_char
;
23880 ignore_rest_of_line ();
23883 /* Parse a .fpu directive. */
23886 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23888 const struct arm_option_fpu_value_table
*opt
;
23892 name
= input_line_pointer
;
23893 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23894 input_line_pointer
++;
23895 saved_char
= *input_line_pointer
;
23896 *input_line_pointer
= 0;
23898 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23899 if (streq (opt
->name
, name
))
23901 mfpu_opt
= &opt
->value
;
23902 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23903 *input_line_pointer
= saved_char
;
23904 demand_empty_rest_of_line ();
23908 as_bad (_("unknown floating point format `%s'\n"), name
);
23909 *input_line_pointer
= saved_char
;
23910 ignore_rest_of_line ();
23913 /* Copy symbol information. */
23916 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23918 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23922 /* Given a symbolic attribute NAME, return the proper integer value.
23923 Returns -1 if the attribute is not known. */
23926 arm_convert_symbolic_attribute (const char *name
)
23928 static const struct
23933 attribute_table
[] =
23935 /* When you modify this table you should
23936 also modify the list in doc/c-arm.texi. */
23937 #define T(tag) {#tag, tag}
23938 T (Tag_CPU_raw_name
),
23941 T (Tag_CPU_arch_profile
),
23942 T (Tag_ARM_ISA_use
),
23943 T (Tag_THUMB_ISA_use
),
23947 T (Tag_Advanced_SIMD_arch
),
23948 T (Tag_PCS_config
),
23949 T (Tag_ABI_PCS_R9_use
),
23950 T (Tag_ABI_PCS_RW_data
),
23951 T (Tag_ABI_PCS_RO_data
),
23952 T (Tag_ABI_PCS_GOT_use
),
23953 T (Tag_ABI_PCS_wchar_t
),
23954 T (Tag_ABI_FP_rounding
),
23955 T (Tag_ABI_FP_denormal
),
23956 T (Tag_ABI_FP_exceptions
),
23957 T (Tag_ABI_FP_user_exceptions
),
23958 T (Tag_ABI_FP_number_model
),
23959 T (Tag_ABI_align_needed
),
23960 T (Tag_ABI_align8_needed
),
23961 T (Tag_ABI_align_preserved
),
23962 T (Tag_ABI_align8_preserved
),
23963 T (Tag_ABI_enum_size
),
23964 T (Tag_ABI_HardFP_use
),
23965 T (Tag_ABI_VFP_args
),
23966 T (Tag_ABI_WMMX_args
),
23967 T (Tag_ABI_optimization_goals
),
23968 T (Tag_ABI_FP_optimization_goals
),
23969 T (Tag_compatibility
),
23970 T (Tag_CPU_unaligned_access
),
23971 T (Tag_FP_HP_extension
),
23972 T (Tag_VFP_HP_extension
),
23973 T (Tag_ABI_FP_16bit_format
),
23974 T (Tag_MPextension_use
),
23976 T (Tag_nodefaults
),
23977 T (Tag_also_compatible_with
),
23978 T (Tag_conformance
),
23980 T (Tag_Virtualization_use
),
23981 /* We deliberately do not include Tag_MPextension_use_legacy. */
23989 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23990 if (streq (name
, attribute_table
[i
].name
))
23991 return attribute_table
[i
].tag
;
23997 /* Apply sym value for relocations only in the case that
23998 they are for local symbols and you have the respective
23999 architectural feature for blx and simple switches. */
24001 arm_apply_sym_value (struct fix
* fixP
)
24004 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24005 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
24007 switch (fixP
->fx_r_type
)
24009 case BFD_RELOC_ARM_PCREL_BLX
:
24010 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24011 if (ARM_IS_FUNC (fixP
->fx_addsy
))
24015 case BFD_RELOC_ARM_PCREL_CALL
:
24016 case BFD_RELOC_THUMB_PCREL_BLX
:
24017 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
24028 #endif /* OBJ_ELF */