1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[16];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2873 end_name
= input_line_pointer
;
2876 if (*input_line_pointer
!= ',')
2879 as_bad (_("expected comma after name \"%s\""), name
);
2881 ignore_rest_of_line ();
2885 input_line_pointer
++;
2888 if (name
[0] == '.' && name
[1] == '\0')
2890 /* XXX - this should not happen to .thumb_set. */
2894 if ((symbolP
= symbol_find (name
)) == NULL
2895 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2898 /* When doing symbol listings, play games with dummy fragments living
2899 outside the normal fragment chain to record the file and line info
2901 if (listing
& LISTING_SYMBOLS
)
2903 extern struct list_info_struct
* listing_tail
;
2904 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2906 memset (dummy_frag
, 0, sizeof (fragS
));
2907 dummy_frag
->fr_type
= rs_fill
;
2908 dummy_frag
->line
= listing_tail
;
2909 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2910 dummy_frag
->fr_symbol
= symbolP
;
2914 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2917 /* "set" symbols are local unless otherwise specified. */
2918 SF_SET_LOCAL (symbolP
);
2919 #endif /* OBJ_COFF */
2920 } /* Make a new symbol. */
2922 symbol_table_insert (symbolP
);
2927 && S_IS_DEFINED (symbolP
)
2928 && S_GET_SEGMENT (symbolP
) != reg_section
)
2929 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2931 pseudo_set (symbolP
);
2933 demand_empty_rest_of_line ();
2935 /* XXX Now we come to the Thumb specific bit of code. */
2937 THUMB_SET_FUNC (symbolP
, 1);
2938 ARM_SET_THUMB (symbolP
, 1);
2939 #if defined OBJ_ELF || defined OBJ_COFF
2940 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2944 /* Directives: Mode selection. */
2946 /* .syntax [unified|divided] - choose the new unified syntax
2947 (same for Arm and Thumb encoding, modulo slight differences in what
2948 can be represented) or the old divergent syntax for each mode. */
2950 s_syntax (int unused ATTRIBUTE_UNUSED
)
2954 name
= input_line_pointer
;
2955 delim
= get_symbol_end ();
2957 if (!strcasecmp (name
, "unified"))
2958 unified_syntax
= TRUE
;
2959 else if (!strcasecmp (name
, "divided"))
2960 unified_syntax
= FALSE
;
2963 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2966 *input_line_pointer
= delim
;
2967 demand_empty_rest_of_line ();
2970 /* Directives: sectioning and alignment. */
2972 /* Same as s_align_ptwo but align 0 => align 2. */
2975 s_align (int unused ATTRIBUTE_UNUSED
)
2980 long max_alignment
= 15;
2982 temp
= get_absolute_expression ();
2983 if (temp
> max_alignment
)
2984 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2987 as_bad (_("alignment negative. 0 assumed."));
2991 if (*input_line_pointer
== ',')
2993 input_line_pointer
++;
2994 temp_fill
= get_absolute_expression ();
3006 /* Only make a frag if we HAVE to. */
3007 if (temp
&& !need_pass_2
)
3009 if (!fill_p
&& subseg_text_p (now_seg
))
3010 frag_align_code (temp
, 0);
3012 frag_align (temp
, (int) temp_fill
, 0);
3014 demand_empty_rest_of_line ();
3016 record_alignment (now_seg
, temp
);
3020 s_bss (int ignore ATTRIBUTE_UNUSED
)
3022 /* We don't support putting frags in the BSS segment, we fake it by
3023 marking in_bss, then looking at s_skip for clues. */
3024 subseg_set (bss_section
, 0);
3025 demand_empty_rest_of_line ();
3027 #ifdef md_elf_section_change_hook
3028 md_elf_section_change_hook ();
3033 s_even (int ignore ATTRIBUTE_UNUSED
)
3035 /* Never make frag if expect extra pass. */
3037 frag_align (1, 0, 0);
3039 record_alignment (now_seg
, 1);
3041 demand_empty_rest_of_line ();
3044 /* Directives: CodeComposer Studio. */
3046 /* .ref (for CodeComposer Studio syntax only). */
3048 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3050 if (codecomposer_syntax
)
3051 ignore_rest_of_line ();
3053 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3056 /* If name is not NULL, then it is used for marking the beginning of a
3057 function, wherease if it is NULL then it means the function end. */
3059 asmfunc_debug (const char * name
)
3061 static const char * last_name
= NULL
;
3065 gas_assert (last_name
== NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_func (name
, name
);
3073 gas_assert (last_name
!= NULL
);
3075 if (debug_type
== DEBUG_STABS
)
3076 stabs_generate_asm_endfunc (last_name
, last_name
);
3083 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3085 if (codecomposer_syntax
)
3087 switch (asmfunc_state
)
3089 case OUTSIDE_ASMFUNC
:
3090 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3093 case WAITING_ASMFUNC_NAME
:
3094 as_bad (_(".asmfunc repeated."));
3097 case WAITING_ENDASMFUNC
:
3098 as_bad (_(".asmfunc without function."));
3101 demand_empty_rest_of_line ();
3104 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3108 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3110 if (codecomposer_syntax
)
3112 switch (asmfunc_state
)
3114 case OUTSIDE_ASMFUNC
:
3115 as_bad (_(".endasmfunc without a .asmfunc."));
3118 case WAITING_ASMFUNC_NAME
:
3119 as_bad (_(".endasmfunc without function."));
3122 case WAITING_ENDASMFUNC
:
3123 asmfunc_state
= OUTSIDE_ASMFUNC
;
3124 asmfunc_debug (NULL
);
3127 demand_empty_rest_of_line ();
3130 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3134 s_ccs_def (int name
)
3136 if (codecomposer_syntax
)
3139 as_bad (_(".def pseudo-op only available with -mccs flag."));
3142 /* Directives: Literal pools. */
3144 static literal_pool
*
3145 find_literal_pool (void)
3147 literal_pool
* pool
;
3149 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3151 if (pool
->section
== now_seg
3152 && pool
->sub_section
== now_subseg
)
3159 static literal_pool
*
3160 find_or_make_literal_pool (void)
3162 /* Next literal pool ID number. */
3163 static unsigned int latest_pool_num
= 1;
3164 literal_pool
* pool
;
3166 pool
= find_literal_pool ();
3170 /* Create a new pool. */
3171 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3175 pool
->next_free_entry
= 0;
3176 pool
->section
= now_seg
;
3177 pool
->sub_section
= now_subseg
;
3178 pool
->next
= list_of_pools
;
3179 pool
->symbol
= NULL
;
3180 pool
->alignment
= 2;
3182 /* Add it to the list. */
3183 list_of_pools
= pool
;
3186 /* New pools, and emptied pools, will have a NULL symbol. */
3187 if (pool
->symbol
== NULL
)
3189 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3190 (valueT
) 0, &zero_address_frag
);
3191 pool
->id
= latest_pool_num
++;
3198 /* Add the literal in the global 'inst'
3199 structure to the relevant literal pool. */
3202 add_to_lit_pool (unsigned int nbytes
)
3204 #define PADDING_SLOT 0x1
3205 #define LIT_ENTRY_SIZE_MASK 0xFF
3206 literal_pool
* pool
;
3207 unsigned int entry
, pool_size
= 0;
3208 bfd_boolean padding_slot_p
= FALSE
;
3214 imm1
= inst
.operands
[1].imm
;
3215 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3216 : inst
.reloc
.exp
.X_unsigned
? 0
3217 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3218 if (target_big_endian
)
3221 imm2
= inst
.operands
[1].imm
;
3225 pool
= find_or_make_literal_pool ();
3227 /* Check if this literal value is already in the pool. */
3228 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3232 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3233 && (inst
.reloc
.exp
.X_op
== O_constant
)
3234 && (pool
->literals
[entry
].X_add_number
3235 == inst
.reloc
.exp
.X_add_number
)
3236 && (pool
->literals
[entry
].X_md
== nbytes
)
3237 && (pool
->literals
[entry
].X_unsigned
3238 == inst
.reloc
.exp
.X_unsigned
))
3241 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3242 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3243 && (pool
->literals
[entry
].X_add_number
3244 == inst
.reloc
.exp
.X_add_number
)
3245 && (pool
->literals
[entry
].X_add_symbol
3246 == inst
.reloc
.exp
.X_add_symbol
)
3247 && (pool
->literals
[entry
].X_op_symbol
3248 == inst
.reloc
.exp
.X_op_symbol
)
3249 && (pool
->literals
[entry
].X_md
== nbytes
))
3252 else if ((nbytes
== 8)
3253 && !(pool_size
& 0x7)
3254 && ((entry
+ 1) != pool
->next_free_entry
)
3255 && (pool
->literals
[entry
].X_op
== O_constant
)
3256 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3257 && (pool
->literals
[entry
].X_unsigned
3258 == inst
.reloc
.exp
.X_unsigned
)
3259 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3260 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3261 && (pool
->literals
[entry
+ 1].X_unsigned
3262 == inst
.reloc
.exp
.X_unsigned
))
3265 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3266 if (padding_slot_p
&& (nbytes
== 4))
3272 /* Do we need to create a new entry? */
3273 if (entry
== pool
->next_free_entry
)
3275 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3277 inst
.error
= _("literal pool overflow");
3283 /* For 8-byte entries, we align to an 8-byte boundary,
3284 and split it into two 4-byte entries, because on 32-bit
3285 host, 8-byte constants are treated as big num, thus
3286 saved in "generic_bignum" which will be overwritten
3287 by later assignments.
3289 We also need to make sure there is enough space for
3292 We also check to make sure the literal operand is a
3294 if (!(inst
.reloc
.exp
.X_op
== O_constant
3295 || inst
.reloc
.exp
.X_op
== O_big
))
3297 inst
.error
= _("invalid type for literal pool");
3300 else if (pool_size
& 0x7)
3302 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3304 inst
.error
= _("literal pool overflow");
3308 pool
->literals
[entry
] = inst
.reloc
.exp
;
3309 pool
->literals
[entry
].X_add_number
= 0;
3310 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3311 pool
->next_free_entry
+= 1;
3314 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3316 inst
.error
= _("literal pool overflow");
3320 pool
->literals
[entry
] = inst
.reloc
.exp
;
3321 pool
->literals
[entry
].X_op
= O_constant
;
3322 pool
->literals
[entry
].X_add_number
= imm1
;
3323 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3324 pool
->literals
[entry
++].X_md
= 4;
3325 pool
->literals
[entry
] = inst
.reloc
.exp
;
3326 pool
->literals
[entry
].X_op
= O_constant
;
3327 pool
->literals
[entry
].X_add_number
= imm2
;
3328 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3329 pool
->literals
[entry
].X_md
= 4;
3330 pool
->alignment
= 3;
3331 pool
->next_free_entry
+= 1;
3335 pool
->literals
[entry
] = inst
.reloc
.exp
;
3336 pool
->literals
[entry
].X_md
= 4;
3340 /* PR ld/12974: Record the location of the first source line to reference
3341 this entry in the literal pool. If it turns out during linking that the
3342 symbol does not exist we will be able to give an accurate line number for
3343 the (first use of the) missing reference. */
3344 if (debug_type
== DEBUG_DWARF2
)
3345 dwarf2_where (pool
->locs
+ entry
);
3347 pool
->next_free_entry
+= 1;
3349 else if (padding_slot_p
)
3351 pool
->literals
[entry
] = inst
.reloc
.exp
;
3352 pool
->literals
[entry
].X_md
= nbytes
;
3355 inst
.reloc
.exp
.X_op
= O_symbol
;
3356 inst
.reloc
.exp
.X_add_number
= pool_size
;
3357 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3363 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3365 bfd_boolean ret
= TRUE
;
3367 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3369 const char *label
= rest
;
3371 while (!is_end_of_line
[(int) label
[-1]])
3376 as_bad (_("Invalid label '%s'"), label
);
3380 asmfunc_debug (label
);
3382 asmfunc_state
= WAITING_ENDASMFUNC
;
3388 /* Can't use symbol_new here, so have to create a symbol and then at
3389 a later date assign it a value. Thats what these functions do. */
3392 symbol_locate (symbolS
* symbolP
,
3393 const char * name
, /* It is copied, the caller can modify. */
3394 segT segment
, /* Segment identifier (SEG_<something>). */
3395 valueT valu
, /* Symbol value. */
3396 fragS
* frag
) /* Associated fragment. */
3399 char * preserved_copy_of_name
;
3401 name_length
= strlen (name
) + 1; /* +1 for \0. */
3402 obstack_grow (¬es
, name
, name_length
);
3403 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3405 #ifdef tc_canonicalize_symbol_name
3406 preserved_copy_of_name
=
3407 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3410 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3412 S_SET_SEGMENT (symbolP
, segment
);
3413 S_SET_VALUE (symbolP
, valu
);
3414 symbol_clear_list_pointers (symbolP
);
3416 symbol_set_frag (symbolP
, frag
);
3418 /* Link to end of symbol chain. */
3420 extern int symbol_table_frozen
;
3422 if (symbol_table_frozen
)
3426 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3428 obj_symbol_new_hook (symbolP
);
3430 #ifdef tc_symbol_new_hook
3431 tc_symbol_new_hook (symbolP
);
3435 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3436 #endif /* DEBUG_SYMS */
3440 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3443 literal_pool
* pool
;
3446 pool
= find_literal_pool ();
3448 || pool
->symbol
== NULL
3449 || pool
->next_free_entry
== 0)
3452 /* Align pool as you have word accesses.
3453 Only make a frag if we have to. */
3455 frag_align (pool
->alignment
, 0, 0);
3457 record_alignment (now_seg
, 2);
3460 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3461 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3463 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3465 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3466 (valueT
) frag_now_fix (), frag_now
);
3467 symbol_table_insert (pool
->symbol
);
3469 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3471 #if defined OBJ_COFF || defined OBJ_ELF
3472 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3475 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3478 if (debug_type
== DEBUG_DWARF2
)
3479 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3481 /* First output the expression in the instruction to the pool. */
3482 emit_expr (&(pool
->literals
[entry
]),
3483 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3486 /* Mark the pool as empty. */
3487 pool
->next_free_entry
= 0;
3488 pool
->symbol
= NULL
;
3492 /* Forward declarations for functions below, in the MD interface
3494 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3495 static valueT
create_unwind_entry (int);
3496 static void start_unwind_section (const segT
, int);
3497 static void add_unwind_opcode (valueT
, int);
3498 static void flush_pending_unwind (void);
3500 /* Directives: Data. */
3503 s_arm_elf_cons (int nbytes
)
3507 #ifdef md_flush_pending_output
3508 md_flush_pending_output ();
3511 if (is_it_end_of_statement ())
3513 demand_empty_rest_of_line ();
3517 #ifdef md_cons_align
3518 md_cons_align (nbytes
);
3521 mapping_state (MAP_DATA
);
3525 char *base
= input_line_pointer
;
3529 if (exp
.X_op
!= O_symbol
)
3530 emit_expr (&exp
, (unsigned int) nbytes
);
3533 char *before_reloc
= input_line_pointer
;
3534 reloc
= parse_reloc (&input_line_pointer
);
3537 as_bad (_("unrecognized relocation suffix"));
3538 ignore_rest_of_line ();
3541 else if (reloc
== BFD_RELOC_UNUSED
)
3542 emit_expr (&exp
, (unsigned int) nbytes
);
3545 reloc_howto_type
*howto
= (reloc_howto_type
*)
3546 bfd_reloc_type_lookup (stdoutput
,
3547 (bfd_reloc_code_real_type
) reloc
);
3548 int size
= bfd_get_reloc_size (howto
);
3550 if (reloc
== BFD_RELOC_ARM_PLT32
)
3552 as_bad (_("(plt) is only valid on branch targets"));
3553 reloc
= BFD_RELOC_UNUSED
;
3558 as_bad (_("%s relocations do not fit in %d bytes"),
3559 howto
->name
, nbytes
);
3562 /* We've parsed an expression stopping at O_symbol.
3563 But there may be more expression left now that we
3564 have parsed the relocation marker. Parse it again.
3565 XXX Surely there is a cleaner way to do this. */
3566 char *p
= input_line_pointer
;
3568 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3569 memcpy (save_buf
, base
, input_line_pointer
- base
);
3570 memmove (base
+ (input_line_pointer
- before_reloc
),
3571 base
, before_reloc
- base
);
3573 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3575 memcpy (base
, save_buf
, p
- base
);
3577 offset
= nbytes
- size
;
3578 p
= frag_more (nbytes
);
3579 memset (p
, 0, nbytes
);
3580 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3581 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3586 while (*input_line_pointer
++ == ',');
3588 /* Put terminator back into stream. */
3589 input_line_pointer
--;
3590 demand_empty_rest_of_line ();
3593 /* Emit an expression containing a 32-bit thumb instruction.
3594 Implementation based on put_thumb32_insn. */
3597 emit_thumb32_expr (expressionS
* exp
)
3599 expressionS exp_high
= *exp
;
3601 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3602 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3603 exp
->X_add_number
&= 0xffff;
3604 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3607 /* Guess the instruction size based on the opcode. */
3610 thumb_insn_size (int opcode
)
3612 if ((unsigned int) opcode
< 0xe800u
)
3614 else if ((unsigned int) opcode
>= 0xe8000000u
)
3621 emit_insn (expressionS
*exp
, int nbytes
)
3625 if (exp
->X_op
== O_constant
)
3630 size
= thumb_insn_size (exp
->X_add_number
);
3634 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3636 as_bad (_(".inst.n operand too big. "\
3637 "Use .inst.w instead"));
3642 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3643 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3645 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3647 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3648 emit_thumb32_expr (exp
);
3650 emit_expr (exp
, (unsigned int) size
);
3652 it_fsm_post_encode ();
3656 as_bad (_("cannot determine Thumb instruction size. " \
3657 "Use .inst.n/.inst.w instead"));
3660 as_bad (_("constant expression required"));
3665 /* Like s_arm_elf_cons but do not use md_cons_align and
3666 set the mapping state to MAP_ARM/MAP_THUMB. */
3669 s_arm_elf_inst (int nbytes
)
3671 if (is_it_end_of_statement ())
3673 demand_empty_rest_of_line ();
3677 /* Calling mapping_state () here will not change ARM/THUMB,
3678 but will ensure not to be in DATA state. */
3681 mapping_state (MAP_THUMB
);
3686 as_bad (_("width suffixes are invalid in ARM mode"));
3687 ignore_rest_of_line ();
3693 mapping_state (MAP_ARM
);
3702 if (! emit_insn (& exp
, nbytes
))
3704 ignore_rest_of_line ();
3708 while (*input_line_pointer
++ == ',');
3710 /* Put terminator back into stream. */
3711 input_line_pointer
--;
3712 demand_empty_rest_of_line ();
3715 /* Parse a .rel31 directive. */
3718 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3725 if (*input_line_pointer
== '1')
3726 highbit
= 0x80000000;
3727 else if (*input_line_pointer
!= '0')
3728 as_bad (_("expected 0 or 1"));
3730 input_line_pointer
++;
3731 if (*input_line_pointer
!= ',')
3732 as_bad (_("missing comma"));
3733 input_line_pointer
++;
3735 #ifdef md_flush_pending_output
3736 md_flush_pending_output ();
3739 #ifdef md_cons_align
3743 mapping_state (MAP_DATA
);
3748 md_number_to_chars (p
, highbit
, 4);
3749 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3750 BFD_RELOC_ARM_PREL31
);
3752 demand_empty_rest_of_line ();
3755 /* Directives: AEABI stack-unwind tables. */
3757 /* Parse an unwind_fnstart directive. Simply records the current location. */
3760 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3762 demand_empty_rest_of_line ();
3763 if (unwind
.proc_start
)
3765 as_bad (_("duplicate .fnstart directive"));
3769 /* Mark the start of the function. */
3770 unwind
.proc_start
= expr_build_dot ();
3772 /* Reset the rest of the unwind info. */
3773 unwind
.opcode_count
= 0;
3774 unwind
.table_entry
= NULL
;
3775 unwind
.personality_routine
= NULL
;
3776 unwind
.personality_index
= -1;
3777 unwind
.frame_size
= 0;
3778 unwind
.fp_offset
= 0;
3779 unwind
.fp_reg
= REG_SP
;
3781 unwind
.sp_restored
= 0;
3785 /* Parse a handlerdata directive. Creates the exception handling table entry
3786 for the function. */
3789 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3791 demand_empty_rest_of_line ();
3792 if (!unwind
.proc_start
)
3793 as_bad (MISSING_FNSTART
);
3795 if (unwind
.table_entry
)
3796 as_bad (_("duplicate .handlerdata directive"));
3798 create_unwind_entry (1);
3801 /* Parse an unwind_fnend directive. Generates the index table entry. */
3804 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3809 unsigned int marked_pr_dependency
;
3811 demand_empty_rest_of_line ();
3813 if (!unwind
.proc_start
)
3815 as_bad (_(".fnend directive without .fnstart"));
3819 /* Add eh table entry. */
3820 if (unwind
.table_entry
== NULL
)
3821 val
= create_unwind_entry (0);
3825 /* Add index table entry. This is two words. */
3826 start_unwind_section (unwind
.saved_seg
, 1);
3827 frag_align (2, 0, 0);
3828 record_alignment (now_seg
, 2);
3830 ptr
= frag_more (8);
3832 where
= frag_now_fix () - 8;
3834 /* Self relative offset of the function start. */
3835 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3836 BFD_RELOC_ARM_PREL31
);
3838 /* Indicate dependency on EHABI-defined personality routines to the
3839 linker, if it hasn't been done already. */
3840 marked_pr_dependency
3841 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3842 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3843 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3845 static const char *const name
[] =
3847 "__aeabi_unwind_cpp_pr0",
3848 "__aeabi_unwind_cpp_pr1",
3849 "__aeabi_unwind_cpp_pr2"
3851 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3852 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3853 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3854 |= 1 << unwind
.personality_index
;
3858 /* Inline exception table entry. */
3859 md_number_to_chars (ptr
+ 4, val
, 4);
3861 /* Self relative offset of the table entry. */
3862 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3863 BFD_RELOC_ARM_PREL31
);
3865 /* Restore the original section. */
3866 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3868 unwind
.proc_start
= NULL
;
3872 /* Parse an unwind_cantunwind directive. */
3875 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3877 demand_empty_rest_of_line ();
3878 if (!unwind
.proc_start
)
3879 as_bad (MISSING_FNSTART
);
3881 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3882 as_bad (_("personality routine specified for cantunwind frame"));
3884 unwind
.personality_index
= -2;
3888 /* Parse a personalityindex directive. */
3891 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3895 if (!unwind
.proc_start
)
3896 as_bad (MISSING_FNSTART
);
3898 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3899 as_bad (_("duplicate .personalityindex directive"));
3903 if (exp
.X_op
!= O_constant
3904 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3906 as_bad (_("bad personality routine number"));
3907 ignore_rest_of_line ();
3911 unwind
.personality_index
= exp
.X_add_number
;
3913 demand_empty_rest_of_line ();
3917 /* Parse a personality directive. */
3920 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3924 if (!unwind
.proc_start
)
3925 as_bad (MISSING_FNSTART
);
3927 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3928 as_bad (_("duplicate .personality directive"));
3930 name
= input_line_pointer
;
3931 c
= get_symbol_end ();
3932 p
= input_line_pointer
;
3933 unwind
.personality_routine
= symbol_find_or_make (name
);
3935 demand_empty_rest_of_line ();
3939 /* Parse a directive saving core registers. */
3942 s_arm_unwind_save_core (void)
3948 range
= parse_reg_list (&input_line_pointer
);
3951 as_bad (_("expected register list"));
3952 ignore_rest_of_line ();
3956 demand_empty_rest_of_line ();
3958 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3959 into .unwind_save {..., sp...}. We aren't bothered about the value of
3960 ip because it is clobbered by calls. */
3961 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3962 && (range
& 0x3000) == 0x1000)
3964 unwind
.opcode_count
--;
3965 unwind
.sp_restored
= 0;
3966 range
= (range
| 0x2000) & ~0x1000;
3967 unwind
.pending_offset
= 0;
3973 /* See if we can use the short opcodes. These pop a block of up to 8
3974 registers starting with r4, plus maybe r14. */
3975 for (n
= 0; n
< 8; n
++)
3977 /* Break at the first non-saved register. */
3978 if ((range
& (1 << (n
+ 4))) == 0)
3981 /* See if there are any other bits set. */
3982 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3984 /* Use the long form. */
3985 op
= 0x8000 | ((range
>> 4) & 0xfff);
3986 add_unwind_opcode (op
, 2);
3990 /* Use the short form. */
3992 op
= 0xa8; /* Pop r14. */
3994 op
= 0xa0; /* Do not pop r14. */
3996 add_unwind_opcode (op
, 1);
4003 op
= 0xb100 | (range
& 0xf);
4004 add_unwind_opcode (op
, 2);
4007 /* Record the number of bytes pushed. */
4008 for (n
= 0; n
< 16; n
++)
4010 if (range
& (1 << n
))
4011 unwind
.frame_size
+= 4;
4016 /* Parse a directive saving FPA registers. */
4019 s_arm_unwind_save_fpa (int reg
)
4025 /* Get Number of registers to transfer. */
4026 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4029 exp
.X_op
= O_illegal
;
4031 if (exp
.X_op
!= O_constant
)
4033 as_bad (_("expected , <constant>"));
4034 ignore_rest_of_line ();
4038 num_regs
= exp
.X_add_number
;
4040 if (num_regs
< 1 || num_regs
> 4)
4042 as_bad (_("number of registers must be in the range [1:4]"));
4043 ignore_rest_of_line ();
4047 demand_empty_rest_of_line ();
4052 op
= 0xb4 | (num_regs
- 1);
4053 add_unwind_opcode (op
, 1);
4058 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4059 add_unwind_opcode (op
, 2);
4061 unwind
.frame_size
+= num_regs
* 12;
4065 /* Parse a directive saving VFP registers for ARMv6 and above. */
4068 s_arm_unwind_save_vfp_armv6 (void)
4073 int num_vfpv3_regs
= 0;
4074 int num_regs_below_16
;
4076 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4086 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4087 than FSTMX/FLDMX-style ones). */
4089 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4091 num_vfpv3_regs
= count
;
4092 else if (start
+ count
> 16)
4093 num_vfpv3_regs
= start
+ count
- 16;
4095 if (num_vfpv3_regs
> 0)
4097 int start_offset
= start
> 16 ? start
- 16 : 0;
4098 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4099 add_unwind_opcode (op
, 2);
4102 /* Generate opcode for registers numbered in the range 0 .. 15. */
4103 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4104 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4105 if (num_regs_below_16
> 0)
4107 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4108 add_unwind_opcode (op
, 2);
4111 unwind
.frame_size
+= count
* 8;
4115 /* Parse a directive saving VFP registers for pre-ARMv6. */
4118 s_arm_unwind_save_vfp (void)
4124 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4127 as_bad (_("expected register list"));
4128 ignore_rest_of_line ();
4132 demand_empty_rest_of_line ();
4137 op
= 0xb8 | (count
- 1);
4138 add_unwind_opcode (op
, 1);
4143 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4144 add_unwind_opcode (op
, 2);
4146 unwind
.frame_size
+= count
* 8 + 4;
4150 /* Parse a directive saving iWMMXt data registers. */
4153 s_arm_unwind_save_mmxwr (void)
4161 if (*input_line_pointer
== '{')
4162 input_line_pointer
++;
4166 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4170 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4175 as_tsktsk (_("register list not in ascending order"));
4178 if (*input_line_pointer
== '-')
4180 input_line_pointer
++;
4181 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4184 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4187 else if (reg
>= hi_reg
)
4189 as_bad (_("bad register range"));
4192 for (; reg
< hi_reg
; reg
++)
4196 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4198 skip_past_char (&input_line_pointer
, '}');
4200 demand_empty_rest_of_line ();
4202 /* Generate any deferred opcodes because we're going to be looking at
4204 flush_pending_unwind ();
4206 for (i
= 0; i
< 16; i
++)
4208 if (mask
& (1 << i
))
4209 unwind
.frame_size
+= 8;
4212 /* Attempt to combine with a previous opcode. We do this because gcc
4213 likes to output separate unwind directives for a single block of
4215 if (unwind
.opcode_count
> 0)
4217 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4218 if ((i
& 0xf8) == 0xc0)
4221 /* Only merge if the blocks are contiguous. */
4224 if ((mask
& 0xfe00) == (1 << 9))
4226 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4227 unwind
.opcode_count
--;
4230 else if (i
== 6 && unwind
.opcode_count
>= 2)
4232 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4236 op
= 0xffff << (reg
- 1);
4238 && ((mask
& op
) == (1u << (reg
- 1))))
4240 op
= (1 << (reg
+ i
+ 1)) - 1;
4241 op
&= ~((1 << reg
) - 1);
4243 unwind
.opcode_count
-= 2;
4250 /* We want to generate opcodes in the order the registers have been
4251 saved, ie. descending order. */
4252 for (reg
= 15; reg
>= -1; reg
--)
4254 /* Save registers in blocks. */
4256 || !(mask
& (1 << reg
)))
4258 /* We found an unsaved reg. Generate opcodes to save the
4265 op
= 0xc0 | (hi_reg
- 10);
4266 add_unwind_opcode (op
, 1);
4271 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4272 add_unwind_opcode (op
, 2);
4281 ignore_rest_of_line ();
4285 s_arm_unwind_save_mmxwcg (void)
4292 if (*input_line_pointer
== '{')
4293 input_line_pointer
++;
4295 skip_whitespace (input_line_pointer
);
4299 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4303 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4309 as_tsktsk (_("register list not in ascending order"));
4312 if (*input_line_pointer
== '-')
4314 input_line_pointer
++;
4315 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4318 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4321 else if (reg
>= hi_reg
)
4323 as_bad (_("bad register range"));
4326 for (; reg
< hi_reg
; reg
++)
4330 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4332 skip_past_char (&input_line_pointer
, '}');
4334 demand_empty_rest_of_line ();
4336 /* Generate any deferred opcodes because we're going to be looking at
4338 flush_pending_unwind ();
4340 for (reg
= 0; reg
< 16; reg
++)
4342 if (mask
& (1 << reg
))
4343 unwind
.frame_size
+= 4;
4346 add_unwind_opcode (op
, 2);
4349 ignore_rest_of_line ();
4353 /* Parse an unwind_save directive.
4354 If the argument is non-zero, this is a .vsave directive. */
4357 s_arm_unwind_save (int arch_v6
)
4360 struct reg_entry
*reg
;
4361 bfd_boolean had_brace
= FALSE
;
4363 if (!unwind
.proc_start
)
4364 as_bad (MISSING_FNSTART
);
4366 /* Figure out what sort of save we have. */
4367 peek
= input_line_pointer
;
4375 reg
= arm_reg_parse_multi (&peek
);
4379 as_bad (_("register expected"));
4380 ignore_rest_of_line ();
4389 as_bad (_("FPA .unwind_save does not take a register list"));
4390 ignore_rest_of_line ();
4393 input_line_pointer
= peek
;
4394 s_arm_unwind_save_fpa (reg
->number
);
4398 s_arm_unwind_save_core ();
4403 s_arm_unwind_save_vfp_armv6 ();
4405 s_arm_unwind_save_vfp ();
4408 case REG_TYPE_MMXWR
:
4409 s_arm_unwind_save_mmxwr ();
4412 case REG_TYPE_MMXWCG
:
4413 s_arm_unwind_save_mmxwcg ();
4417 as_bad (_(".unwind_save does not support this kind of register"));
4418 ignore_rest_of_line ();
4423 /* Parse an unwind_movsp directive. */
4426 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4438 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4439 ignore_rest_of_line ();
4443 /* Optional constant. */
4444 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4446 if (immediate_for_directive (&offset
) == FAIL
)
4452 demand_empty_rest_of_line ();
4454 if (reg
== REG_SP
|| reg
== REG_PC
)
4456 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4460 if (unwind
.fp_reg
!= REG_SP
)
4461 as_bad (_("unexpected .unwind_movsp directive"));
4463 /* Generate opcode to restore the value. */
4465 add_unwind_opcode (op
, 1);
4467 /* Record the information for later. */
4468 unwind
.fp_reg
= reg
;
4469 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4470 unwind
.sp_restored
= 1;
4473 /* Parse an unwind_pad directive. */
4476 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4480 if (!unwind
.proc_start
)
4481 as_bad (MISSING_FNSTART
);
4483 if (immediate_for_directive (&offset
) == FAIL
)
4488 as_bad (_("stack increment must be multiple of 4"));
4489 ignore_rest_of_line ();
4493 /* Don't generate any opcodes, just record the details for later. */
4494 unwind
.frame_size
+= offset
;
4495 unwind
.pending_offset
+= offset
;
4497 demand_empty_rest_of_line ();
4500 /* Parse an unwind_setfp directive. */
4503 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4509 if (!unwind
.proc_start
)
4510 as_bad (MISSING_FNSTART
);
4512 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4513 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4516 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4518 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4520 as_bad (_("expected <reg>, <reg>"));
4521 ignore_rest_of_line ();
4525 /* Optional constant. */
4526 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4528 if (immediate_for_directive (&offset
) == FAIL
)
4534 demand_empty_rest_of_line ();
4536 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4538 as_bad (_("register must be either sp or set by a previous"
4539 "unwind_movsp directive"));
4543 /* Don't generate any opcodes, just record the information for later. */
4544 unwind
.fp_reg
= fp_reg
;
4546 if (sp_reg
== REG_SP
)
4547 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4549 unwind
.fp_offset
-= offset
;
4552 /* Parse an unwind_raw directive. */
4555 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4558 /* This is an arbitrary limit. */
4559 unsigned char op
[16];
4562 if (!unwind
.proc_start
)
4563 as_bad (MISSING_FNSTART
);
4566 if (exp
.X_op
== O_constant
4567 && skip_past_comma (&input_line_pointer
) != FAIL
)
4569 unwind
.frame_size
+= exp
.X_add_number
;
4573 exp
.X_op
= O_illegal
;
4575 if (exp
.X_op
!= O_constant
)
4577 as_bad (_("expected <offset>, <opcode>"));
4578 ignore_rest_of_line ();
4584 /* Parse the opcode. */
4589 as_bad (_("unwind opcode too long"));
4590 ignore_rest_of_line ();
4592 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4594 as_bad (_("invalid unwind opcode"));
4595 ignore_rest_of_line ();
4598 op
[count
++] = exp
.X_add_number
;
4600 /* Parse the next byte. */
4601 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4607 /* Add the opcode bytes in reverse order. */
4609 add_unwind_opcode (op
[count
], 1);
4611 demand_empty_rest_of_line ();
4615 /* Parse a .eabi_attribute directive. */
4618 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4620 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4622 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4623 attributes_set_explicitly
[tag
] = 1;
4626 /* Emit a tls fix for the symbol. */
4629 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4633 #ifdef md_flush_pending_output
4634 md_flush_pending_output ();
4637 #ifdef md_cons_align
4641 /* Since we're just labelling the code, there's no need to define a
4644 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4645 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4646 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4647 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4649 #endif /* OBJ_ELF */
4651 static void s_arm_arch (int);
4652 static void s_arm_object_arch (int);
4653 static void s_arm_cpu (int);
4654 static void s_arm_fpu (int);
4655 static void s_arm_arch_extension (int);
4660 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4667 if (exp
.X_op
== O_symbol
)
4668 exp
.X_op
= O_secrel
;
4670 emit_expr (&exp
, 4);
4672 while (*input_line_pointer
++ == ',');
4674 input_line_pointer
--;
4675 demand_empty_rest_of_line ();
4679 /* This table describes all the machine specific pseudo-ops the assembler
4680 has to support. The fields are:
4681 pseudo-op name without dot
4682 function to call to execute this pseudo-op
4683 Integer arg to pass to the function. */
4685 const pseudo_typeS md_pseudo_table
[] =
4687 /* Never called because '.req' does not start a line. */
4688 { "req", s_req
, 0 },
4689 /* Following two are likewise never called. */
4692 { "unreq", s_unreq
, 0 },
4693 { "bss", s_bss
, 0 },
4694 { "align", s_align
, 0 },
4695 { "arm", s_arm
, 0 },
4696 { "thumb", s_thumb
, 0 },
4697 { "code", s_code
, 0 },
4698 { "force_thumb", s_force_thumb
, 0 },
4699 { "thumb_func", s_thumb_func
, 0 },
4700 { "thumb_set", s_thumb_set
, 0 },
4701 { "even", s_even
, 0 },
4702 { "ltorg", s_ltorg
, 0 },
4703 { "pool", s_ltorg
, 0 },
4704 { "syntax", s_syntax
, 0 },
4705 { "cpu", s_arm_cpu
, 0 },
4706 { "arch", s_arm_arch
, 0 },
4707 { "object_arch", s_arm_object_arch
, 0 },
4708 { "fpu", s_arm_fpu
, 0 },
4709 { "arch_extension", s_arm_arch_extension
, 0 },
4711 { "word", s_arm_elf_cons
, 4 },
4712 { "long", s_arm_elf_cons
, 4 },
4713 { "inst.n", s_arm_elf_inst
, 2 },
4714 { "inst.w", s_arm_elf_inst
, 4 },
4715 { "inst", s_arm_elf_inst
, 0 },
4716 { "rel31", s_arm_rel31
, 0 },
4717 { "fnstart", s_arm_unwind_fnstart
, 0 },
4718 { "fnend", s_arm_unwind_fnend
, 0 },
4719 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4720 { "personality", s_arm_unwind_personality
, 0 },
4721 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4722 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4723 { "save", s_arm_unwind_save
, 0 },
4724 { "vsave", s_arm_unwind_save
, 1 },
4725 { "movsp", s_arm_unwind_movsp
, 0 },
4726 { "pad", s_arm_unwind_pad
, 0 },
4727 { "setfp", s_arm_unwind_setfp
, 0 },
4728 { "unwind_raw", s_arm_unwind_raw
, 0 },
4729 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4730 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4734 /* These are used for dwarf. */
4738 /* These are used for dwarf2. */
4739 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4740 { "loc", dwarf2_directive_loc
, 0 },
4741 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4743 { "extend", float_cons
, 'x' },
4744 { "ldouble", float_cons
, 'x' },
4745 { "packed", float_cons
, 'p' },
4747 {"secrel32", pe_directive_secrel
, 0},
4750 /* These are for compatibility with CodeComposer Studio. */
4751 {"ref", s_ccs_ref
, 0},
4752 {"def", s_ccs_def
, 0},
4753 {"asmfunc", s_ccs_asmfunc
, 0},
4754 {"endasmfunc", s_ccs_endasmfunc
, 0},
4759 /* Parser functions used exclusively in instruction operands. */
4761 /* Generic immediate-value read function for use in insn parsing.
4762 STR points to the beginning of the immediate (the leading #);
4763 VAL receives the value; if the value is outside [MIN, MAX]
4764 issue an error. PREFIX_OPT is true if the immediate prefix is
4768 parse_immediate (char **str
, int *val
, int min
, int max
,
4769 bfd_boolean prefix_opt
)
4772 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4773 if (exp
.X_op
!= O_constant
)
4775 inst
.error
= _("constant expression required");
4779 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4781 inst
.error
= _("immediate value out of range");
4785 *val
= exp
.X_add_number
;
4789 /* Less-generic immediate-value read function with the possibility of loading a
4790 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4791 instructions. Puts the result directly in inst.operands[i]. */
4794 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4795 bfd_boolean allow_symbol_p
)
4798 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4801 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4803 if (exp_p
->X_op
== O_constant
)
4805 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4806 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4807 O_constant. We have to be careful not to break compilation for
4808 32-bit X_add_number, though. */
4809 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4811 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4812 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4814 inst
.operands
[i
].regisimm
= 1;
4817 else if (exp_p
->X_op
== O_big
4818 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4820 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4822 /* Bignums have their least significant bits in
4823 generic_bignum[0]. Make sure we put 32 bits in imm and
4824 32 bits in reg, in a (hopefully) portable way. */
4825 gas_assert (parts
!= 0);
4827 /* Make sure that the number is not too big.
4828 PR 11972: Bignums can now be sign-extended to the
4829 size of a .octa so check that the out of range bits
4830 are all zero or all one. */
4831 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4833 LITTLENUM_TYPE m
= -1;
4835 if (generic_bignum
[parts
* 2] != 0
4836 && generic_bignum
[parts
* 2] != m
)
4839 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4840 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4844 inst
.operands
[i
].imm
= 0;
4845 for (j
= 0; j
< parts
; j
++, idx
++)
4846 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4847 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4848 inst
.operands
[i
].reg
= 0;
4849 for (j
= 0; j
< parts
; j
++, idx
++)
4850 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4851 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4852 inst
.operands
[i
].regisimm
= 1;
4854 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4862 /* Returns the pseudo-register number of an FPA immediate constant,
4863 or FAIL if there isn't a valid constant here. */
4866 parse_fpa_immediate (char ** str
)
4868 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4874 /* First try and match exact strings, this is to guarantee
4875 that some formats will work even for cross assembly. */
4877 for (i
= 0; fp_const
[i
]; i
++)
4879 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4883 *str
+= strlen (fp_const
[i
]);
4884 if (is_end_of_line
[(unsigned char) **str
])
4890 /* Just because we didn't get a match doesn't mean that the constant
4891 isn't valid, just that it is in a format that we don't
4892 automatically recognize. Try parsing it with the standard
4893 expression routines. */
4895 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4897 /* Look for a raw floating point number. */
4898 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4899 && is_end_of_line
[(unsigned char) *save_in
])
4901 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4903 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4905 if (words
[j
] != fp_values
[i
][j
])
4909 if (j
== MAX_LITTLENUMS
)
4917 /* Try and parse a more complex expression, this will probably fail
4918 unless the code uses a floating point prefix (eg "0f"). */
4919 save_in
= input_line_pointer
;
4920 input_line_pointer
= *str
;
4921 if (expression (&exp
) == absolute_section
4922 && exp
.X_op
== O_big
4923 && exp
.X_add_number
< 0)
4925 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4927 #define X_PRECISION 5
4928 #define E_PRECISION 15L
4929 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4931 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4933 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4935 if (words
[j
] != fp_values
[i
][j
])
4939 if (j
== MAX_LITTLENUMS
)
4941 *str
= input_line_pointer
;
4942 input_line_pointer
= save_in
;
4949 *str
= input_line_pointer
;
4950 input_line_pointer
= save_in
;
4951 inst
.error
= _("invalid FPA immediate expression");
4955 /* Returns 1 if a number has "quarter-precision" float format
4956 0baBbbbbbc defgh000 00000000 00000000. */
4959 is_quarter_float (unsigned imm
)
4961 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4962 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4966 /* Detect the presence of a floating point or integer zero constant,
4970 parse_ifimm_zero (char **in
)
4974 if (!is_immediate_prefix (**in
))
4979 /* Accept #0x0 as a synonym for #0. */
4980 if (strncmp (*in
, "0x", 2) == 0)
4983 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4988 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4989 &generic_floating_point_number
);
4992 && generic_floating_point_number
.sign
== '+'
4993 && (generic_floating_point_number
.low
4994 > generic_floating_point_number
.leader
))
5000 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5001 0baBbbbbbc defgh000 00000000 00000000.
5002 The zero and minus-zero cases need special handling, since they can't be
5003 encoded in the "quarter-precision" float format, but can nonetheless be
5004 loaded as integer constants. */
5007 parse_qfloat_immediate (char **ccp
, int *immed
)
5011 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5012 int found_fpchar
= 0;
5014 skip_past_char (&str
, '#');
5016 /* We must not accidentally parse an integer as a floating-point number. Make
5017 sure that the value we parse is not an integer by checking for special
5018 characters '.' or 'e'.
5019 FIXME: This is a horrible hack, but doing better is tricky because type
5020 information isn't in a very usable state at parse time. */
5022 skip_whitespace (fpnum
);
5024 if (strncmp (fpnum
, "0x", 2) == 0)
5028 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5029 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5039 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5041 unsigned fpword
= 0;
5044 /* Our FP word must be 32 bits (single-precision FP). */
5045 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5047 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5051 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5064 /* Shift operands. */
5067 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5070 struct asm_shift_name
5073 enum shift_kind kind
;
5076 /* Third argument to parse_shift. */
5077 enum parse_shift_mode
5079 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5080 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5081 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5082 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5083 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5086 /* Parse a <shift> specifier on an ARM data processing instruction.
5087 This has three forms:
5089 (LSL|LSR|ASL|ASR|ROR) Rs
5090 (LSL|LSR|ASL|ASR|ROR) #imm
5093 Note that ASL is assimilated to LSL in the instruction encoding, and
5094 RRX to ROR #0 (which cannot be written as such). */
5097 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5099 const struct asm_shift_name
*shift_name
;
5100 enum shift_kind shift
;
5105 for (p
= *str
; ISALPHA (*p
); p
++)
5110 inst
.error
= _("shift expression expected");
5114 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5117 if (shift_name
== NULL
)
5119 inst
.error
= _("shift expression expected");
5123 shift
= shift_name
->kind
;
5127 case NO_SHIFT_RESTRICT
:
5128 case SHIFT_IMMEDIATE
: break;
5130 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5131 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5133 inst
.error
= _("'LSL' or 'ASR' required");
5138 case SHIFT_LSL_IMMEDIATE
:
5139 if (shift
!= SHIFT_LSL
)
5141 inst
.error
= _("'LSL' required");
5146 case SHIFT_ASR_IMMEDIATE
:
5147 if (shift
!= SHIFT_ASR
)
5149 inst
.error
= _("'ASR' required");
5157 if (shift
!= SHIFT_RRX
)
5159 /* Whitespace can appear here if the next thing is a bare digit. */
5160 skip_whitespace (p
);
5162 if (mode
== NO_SHIFT_RESTRICT
5163 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5165 inst
.operands
[i
].imm
= reg
;
5166 inst
.operands
[i
].immisreg
= 1;
5168 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5171 inst
.operands
[i
].shift_kind
= shift
;
5172 inst
.operands
[i
].shifted
= 1;
5177 /* Parse a <shifter_operand> for an ARM data processing instruction:
5180 #<immediate>, <rotate>
5184 where <shift> is defined by parse_shift above, and <rotate> is a
5185 multiple of 2 between 0 and 30. Validation of immediate operands
5186 is deferred to md_apply_fix. */
5189 parse_shifter_operand (char **str
, int i
)
5194 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5196 inst
.operands
[i
].reg
= value
;
5197 inst
.operands
[i
].isreg
= 1;
5199 /* parse_shift will override this if appropriate */
5200 inst
.reloc
.exp
.X_op
= O_constant
;
5201 inst
.reloc
.exp
.X_add_number
= 0;
5203 if (skip_past_comma (str
) == FAIL
)
5206 /* Shift operation on register. */
5207 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5210 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5213 if (skip_past_comma (str
) == SUCCESS
)
5215 /* #x, y -- ie explicit rotation by Y. */
5216 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5219 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5221 inst
.error
= _("constant expression expected");
5225 value
= exp
.X_add_number
;
5226 if (value
< 0 || value
> 30 || value
% 2 != 0)
5228 inst
.error
= _("invalid rotation");
5231 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5233 inst
.error
= _("invalid constant");
5237 /* Encode as specified. */
5238 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5242 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5243 inst
.reloc
.pc_rel
= 0;
5247 /* Group relocation information. Each entry in the table contains the
5248 textual name of the relocation as may appear in assembler source
5249 and must end with a colon.
5250 Along with this textual name are the relocation codes to be used if
5251 the corresponding instruction is an ALU instruction (ADD or SUB only),
5252 an LDR, an LDRS, or an LDC. */
5254 struct group_reloc_table_entry
5265 /* Varieties of non-ALU group relocation. */
5272 static struct group_reloc_table_entry group_reloc_table
[] =
5273 { /* Program counter relative: */
5275 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5280 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5281 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5282 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5283 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5285 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5290 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5291 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5292 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5293 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5295 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5296 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5297 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5298 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5299 /* Section base relative */
5301 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5306 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5307 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5308 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5309 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5311 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5316 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5317 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5318 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5319 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5321 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5322 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5323 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5324 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5326 /* Given the address of a pointer pointing to the textual name of a group
5327 relocation as may appear in assembler source, attempt to find its details
5328 in group_reloc_table. The pointer will be updated to the character after
5329 the trailing colon. On failure, FAIL will be returned; SUCCESS
5330 otherwise. On success, *entry will be updated to point at the relevant
5331 group_reloc_table entry. */
5334 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5337 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5339 int length
= strlen (group_reloc_table
[i
].name
);
5341 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5342 && (*str
)[length
] == ':')
5344 *out
= &group_reloc_table
[i
];
5345 *str
+= (length
+ 1);
5353 /* Parse a <shifter_operand> for an ARM data processing instruction
5354 (as for parse_shifter_operand) where group relocations are allowed:
5357 #<immediate>, <rotate>
5358 #:<group_reloc>:<expression>
5362 where <group_reloc> is one of the strings defined in group_reloc_table.
5363 The hashes are optional.
5365 Everything else is as for parse_shifter_operand. */
5367 static parse_operand_result
5368 parse_shifter_operand_group_reloc (char **str
, int i
)
5370 /* Determine if we have the sequence of characters #: or just :
5371 coming next. If we do, then we check for a group relocation.
5372 If we don't, punt the whole lot to parse_shifter_operand. */
5374 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5375 || (*str
)[0] == ':')
5377 struct group_reloc_table_entry
*entry
;
5379 if ((*str
)[0] == '#')
5384 /* Try to parse a group relocation. Anything else is an error. */
5385 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5387 inst
.error
= _("unknown group relocation");
5388 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5391 /* We now have the group relocation table entry corresponding to
5392 the name in the assembler source. Next, we parse the expression. */
5393 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5394 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5396 /* Record the relocation type (always the ALU variant here). */
5397 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5398 gas_assert (inst
.reloc
.type
!= 0);
5400 return PARSE_OPERAND_SUCCESS
;
5403 return parse_shifter_operand (str
, i
) == SUCCESS
5404 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5406 /* Never reached. */
5409 /* Parse a Neon alignment expression. Information is written to
5410 inst.operands[i]. We assume the initial ':' has been skipped.
5412 align .imm = align << 8, .immisalign=1, .preind=0 */
5413 static parse_operand_result
5414 parse_neon_alignment (char **str
, int i
)
5419 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5421 if (exp
.X_op
!= O_constant
)
5423 inst
.error
= _("alignment must be constant");
5424 return PARSE_OPERAND_FAIL
;
5427 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5428 inst
.operands
[i
].immisalign
= 1;
5429 /* Alignments are not pre-indexes. */
5430 inst
.operands
[i
].preind
= 0;
5433 return PARSE_OPERAND_SUCCESS
;
5436 /* Parse all forms of an ARM address expression. Information is written
5437 to inst.operands[i] and/or inst.reloc.
5439 Preindexed addressing (.preind=1):
5441 [Rn, #offset] .reg=Rn .reloc.exp=offset
5442 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5443 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5444 .shift_kind=shift .reloc.exp=shift_imm
5446 These three may have a trailing ! which causes .writeback to be set also.
5448 Postindexed addressing (.postind=1, .writeback=1):
5450 [Rn], #offset .reg=Rn .reloc.exp=offset
5451 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5452 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5453 .shift_kind=shift .reloc.exp=shift_imm
5455 Unindexed addressing (.preind=0, .postind=0):
5457 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5461 [Rn]{!} shorthand for [Rn,#0]{!}
5462 =immediate .isreg=0 .reloc.exp=immediate
5463 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5465 It is the caller's responsibility to check for addressing modes not
5466 supported by the instruction, and to set inst.reloc.type. */
5468 static parse_operand_result
5469 parse_address_main (char **str
, int i
, int group_relocations
,
5470 group_reloc_type group_type
)
5475 if (skip_past_char (&p
, '[') == FAIL
)
5477 if (skip_past_char (&p
, '=') == FAIL
)
5479 /* Bare address - translate to PC-relative offset. */
5480 inst
.reloc
.pc_rel
= 1;
5481 inst
.operands
[i
].reg
= REG_PC
;
5482 inst
.operands
[i
].isreg
= 1;
5483 inst
.operands
[i
].preind
= 1;
5485 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5486 return PARSE_OPERAND_FAIL
;
5488 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5489 /*allow_symbol_p=*/TRUE
))
5490 return PARSE_OPERAND_FAIL
;
5493 return PARSE_OPERAND_SUCCESS
;
5496 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5497 skip_whitespace (p
);
5499 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5501 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5502 return PARSE_OPERAND_FAIL
;
5504 inst
.operands
[i
].reg
= reg
;
5505 inst
.operands
[i
].isreg
= 1;
5507 if (skip_past_comma (&p
) == SUCCESS
)
5509 inst
.operands
[i
].preind
= 1;
5512 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5516 inst
.operands
[i
].imm
= reg
;
5517 inst
.operands
[i
].immisreg
= 1;
5519 if (skip_past_comma (&p
) == SUCCESS
)
5520 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5521 return PARSE_OPERAND_FAIL
;
5523 else if (skip_past_char (&p
, ':') == SUCCESS
)
5525 /* FIXME: '@' should be used here, but it's filtered out by generic
5526 code before we get to see it here. This may be subject to
5528 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5530 if (result
!= PARSE_OPERAND_SUCCESS
)
5535 if (inst
.operands
[i
].negative
)
5537 inst
.operands
[i
].negative
= 0;
5541 if (group_relocations
5542 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5544 struct group_reloc_table_entry
*entry
;
5546 /* Skip over the #: or : sequence. */
5552 /* Try to parse a group relocation. Anything else is an
5554 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5556 inst
.error
= _("unknown group relocation");
5557 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5560 /* We now have the group relocation table entry corresponding to
5561 the name in the assembler source. Next, we parse the
5563 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5564 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5566 /* Record the relocation type. */
5570 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5574 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5578 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5585 if (inst
.reloc
.type
== 0)
5587 inst
.error
= _("this group relocation is not allowed on this instruction");
5588 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5594 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5595 return PARSE_OPERAND_FAIL
;
5596 /* If the offset is 0, find out if it's a +0 or -0. */
5597 if (inst
.reloc
.exp
.X_op
== O_constant
5598 && inst
.reloc
.exp
.X_add_number
== 0)
5600 skip_whitespace (q
);
5604 skip_whitespace (q
);
5607 inst
.operands
[i
].negative
= 1;
5612 else if (skip_past_char (&p
, ':') == SUCCESS
)
5614 /* FIXME: '@' should be used here, but it's filtered out by generic code
5615 before we get to see it here. This may be subject to change. */
5616 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5618 if (result
!= PARSE_OPERAND_SUCCESS
)
5622 if (skip_past_char (&p
, ']') == FAIL
)
5624 inst
.error
= _("']' expected");
5625 return PARSE_OPERAND_FAIL
;
5628 if (skip_past_char (&p
, '!') == SUCCESS
)
5629 inst
.operands
[i
].writeback
= 1;
5631 else if (skip_past_comma (&p
) == SUCCESS
)
5633 if (skip_past_char (&p
, '{') == SUCCESS
)
5635 /* [Rn], {expr} - unindexed, with option */
5636 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5637 0, 255, TRUE
) == FAIL
)
5638 return PARSE_OPERAND_FAIL
;
5640 if (skip_past_char (&p
, '}') == FAIL
)
5642 inst
.error
= _("'}' expected at end of 'option' field");
5643 return PARSE_OPERAND_FAIL
;
5645 if (inst
.operands
[i
].preind
)
5647 inst
.error
= _("cannot combine index with option");
5648 return PARSE_OPERAND_FAIL
;
5651 return PARSE_OPERAND_SUCCESS
;
5655 inst
.operands
[i
].postind
= 1;
5656 inst
.operands
[i
].writeback
= 1;
5658 if (inst
.operands
[i
].preind
)
5660 inst
.error
= _("cannot combine pre- and post-indexing");
5661 return PARSE_OPERAND_FAIL
;
5665 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5667 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5669 /* We might be using the immediate for alignment already. If we
5670 are, OR the register number into the low-order bits. */
5671 if (inst
.operands
[i
].immisalign
)
5672 inst
.operands
[i
].imm
|= reg
;
5674 inst
.operands
[i
].imm
= reg
;
5675 inst
.operands
[i
].immisreg
= 1;
5677 if (skip_past_comma (&p
) == SUCCESS
)
5678 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5679 return PARSE_OPERAND_FAIL
;
5684 if (inst
.operands
[i
].negative
)
5686 inst
.operands
[i
].negative
= 0;
5689 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5690 return PARSE_OPERAND_FAIL
;
5691 /* If the offset is 0, find out if it's a +0 or -0. */
5692 if (inst
.reloc
.exp
.X_op
== O_constant
5693 && inst
.reloc
.exp
.X_add_number
== 0)
5695 skip_whitespace (q
);
5699 skip_whitespace (q
);
5702 inst
.operands
[i
].negative
= 1;
5708 /* If at this point neither .preind nor .postind is set, we have a
5709 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5710 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5712 inst
.operands
[i
].preind
= 1;
5713 inst
.reloc
.exp
.X_op
= O_constant
;
5714 inst
.reloc
.exp
.X_add_number
= 0;
5717 return PARSE_OPERAND_SUCCESS
;
5721 parse_address (char **str
, int i
)
5723 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5727 static parse_operand_result
5728 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5730 return parse_address_main (str
, i
, 1, type
);
5733 /* Parse an operand for a MOVW or MOVT instruction. */
5735 parse_half (char **str
)
5740 skip_past_char (&p
, '#');
5741 if (strncasecmp (p
, ":lower16:", 9) == 0)
5742 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5743 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5744 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5746 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5749 skip_whitespace (p
);
5752 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5755 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5757 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5759 inst
.error
= _("constant expression expected");
5762 if (inst
.reloc
.exp
.X_add_number
< 0
5763 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5765 inst
.error
= _("immediate value out of range");
5773 /* Miscellaneous. */
5775 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5776 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5778 parse_psr (char **str
, bfd_boolean lhs
)
5781 unsigned long psr_field
;
5782 const struct asm_psr
*psr
;
5784 bfd_boolean is_apsr
= FALSE
;
5785 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5787 /* PR gas/12698: If the user has specified -march=all then m_profile will
5788 be TRUE, but we want to ignore it in this case as we are building for any
5789 CPU type, including non-m variants. */
5790 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5793 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5794 feature for ease of use and backwards compatibility. */
5796 if (strncasecmp (p
, "SPSR", 4) == 0)
5799 goto unsupported_psr
;
5801 psr_field
= SPSR_BIT
;
5803 else if (strncasecmp (p
, "CPSR", 4) == 0)
5806 goto unsupported_psr
;
5810 else if (strncasecmp (p
, "APSR", 4) == 0)
5812 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5813 and ARMv7-R architecture CPUs. */
5822 while (ISALNUM (*p
) || *p
== '_');
5824 if (strncasecmp (start
, "iapsr", 5) == 0
5825 || strncasecmp (start
, "eapsr", 5) == 0
5826 || strncasecmp (start
, "xpsr", 4) == 0
5827 || strncasecmp (start
, "psr", 3) == 0)
5828 p
= start
+ strcspn (start
, "rR") + 1;
5830 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5836 /* If APSR is being written, a bitfield may be specified. Note that
5837 APSR itself is handled above. */
5838 if (psr
->field
<= 3)
5840 psr_field
= psr
->field
;
5846 /* M-profile MSR instructions have the mask field set to "10", except
5847 *PSR variants which modify APSR, which may use a different mask (and
5848 have been handled already). Do that by setting the PSR_f field
5850 return psr
->field
| (lhs
? PSR_f
: 0);
5853 goto unsupported_psr
;
5859 /* A suffix follows. */
5865 while (ISALNUM (*p
) || *p
== '_');
5869 /* APSR uses a notation for bits, rather than fields. */
5870 unsigned int nzcvq_bits
= 0;
5871 unsigned int g_bit
= 0;
5874 for (bit
= start
; bit
!= p
; bit
++)
5876 switch (TOLOWER (*bit
))
5879 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5883 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5887 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5891 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5895 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5899 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5903 inst
.error
= _("unexpected bit specified after APSR");
5908 if (nzcvq_bits
== 0x1f)
5913 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5915 inst
.error
= _("selected processor does not "
5916 "support DSP extension");
5923 if ((nzcvq_bits
& 0x20) != 0
5924 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5925 || (g_bit
& 0x2) != 0)
5927 inst
.error
= _("bad bitmask specified after APSR");
5933 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5938 psr_field
|= psr
->field
;
5944 goto error
; /* Garbage after "[CS]PSR". */
5946 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5947 is deprecated, but allow it anyway. */
5951 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5954 else if (!m_profile
)
5955 /* These bits are never right for M-profile devices: don't set them
5956 (only code paths which read/write APSR reach here). */
5957 psr_field
|= (PSR_c
| PSR_f
);
5963 inst
.error
= _("selected processor does not support requested special "
5964 "purpose register");
5968 inst
.error
= _("flag for {c}psr instruction expected");
5972 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5973 value suitable for splatting into the AIF field of the instruction. */
5976 parse_cps_flags (char **str
)
5985 case '\0': case ',':
5988 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5989 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5990 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5993 inst
.error
= _("unrecognized CPS flag");
5998 if (saw_a_flag
== 0)
6000 inst
.error
= _("missing CPS flags");
6008 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6009 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6012 parse_endian_specifier (char **str
)
6017 if (strncasecmp (s
, "BE", 2))
6019 else if (strncasecmp (s
, "LE", 2))
6023 inst
.error
= _("valid endian specifiers are be or le");
6027 if (ISALNUM (s
[2]) || s
[2] == '_')
6029 inst
.error
= _("valid endian specifiers are be or le");
6034 return little_endian
;
6037 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6038 value suitable for poking into the rotate field of an sxt or sxta
6039 instruction, or FAIL on error. */
6042 parse_ror (char **str
)
6047 if (strncasecmp (s
, "ROR", 3) == 0)
6051 inst
.error
= _("missing rotation field after comma");
6055 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6060 case 0: *str
= s
; return 0x0;
6061 case 8: *str
= s
; return 0x1;
6062 case 16: *str
= s
; return 0x2;
6063 case 24: *str
= s
; return 0x3;
6066 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6071 /* Parse a conditional code (from conds[] below). The value returned is in the
6072 range 0 .. 14, or FAIL. */
6074 parse_cond (char **str
)
6077 const struct asm_cond
*c
;
6079 /* Condition codes are always 2 characters, so matching up to
6080 3 characters is sufficient. */
6085 while (ISALPHA (*q
) && n
< 3)
6087 cond
[n
] = TOLOWER (*q
);
6092 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6095 inst
.error
= _("condition required");
6103 /* If the given feature available in the selected CPU, mark it as used.
6104 Returns TRUE iff feature is available. */
6106 mark_feature_used (const arm_feature_set
*feature
)
6108 /* Ensure the option is valid on the current architecture. */
6109 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6112 /* Add the appropriate architecture feature for the barrier option used.
6115 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6117 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6122 /* Parse an option for a barrier instruction. Returns the encoding for the
6125 parse_barrier (char **str
)
6128 const struct asm_barrier_opt
*o
;
6131 while (ISALPHA (*q
))
6134 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6139 if (!mark_feature_used (&o
->arch
))
6146 /* Parse the operands of a table branch instruction. Similar to a memory
6149 parse_tb (char **str
)
6154 if (skip_past_char (&p
, '[') == FAIL
)
6156 inst
.error
= _("'[' expected");
6160 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6162 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6165 inst
.operands
[0].reg
= reg
;
6167 if (skip_past_comma (&p
) == FAIL
)
6169 inst
.error
= _("',' expected");
6173 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6175 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6178 inst
.operands
[0].imm
= reg
;
6180 if (skip_past_comma (&p
) == SUCCESS
)
6182 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6184 if (inst
.reloc
.exp
.X_add_number
!= 1)
6186 inst
.error
= _("invalid shift");
6189 inst
.operands
[0].shifted
= 1;
6192 if (skip_past_char (&p
, ']') == FAIL
)
6194 inst
.error
= _("']' expected");
6201 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6202 information on the types the operands can take and how they are encoded.
6203 Up to four operands may be read; this function handles setting the
6204 ".present" field for each read operand itself.
6205 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6206 else returns FAIL. */
6209 parse_neon_mov (char **str
, int *which_operand
)
6211 int i
= *which_operand
, val
;
6212 enum arm_reg_type rtype
;
6214 struct neon_type_el optype
;
6216 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6218 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6219 inst
.operands
[i
].reg
= val
;
6220 inst
.operands
[i
].isscalar
= 1;
6221 inst
.operands
[i
].vectype
= optype
;
6222 inst
.operands
[i
++].present
= 1;
6224 if (skip_past_comma (&ptr
) == FAIL
)
6227 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6230 inst
.operands
[i
].reg
= val
;
6231 inst
.operands
[i
].isreg
= 1;
6232 inst
.operands
[i
].present
= 1;
6234 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6237 /* Cases 0, 1, 2, 3, 5 (D only). */
6238 if (skip_past_comma (&ptr
) == FAIL
)
6241 inst
.operands
[i
].reg
= val
;
6242 inst
.operands
[i
].isreg
= 1;
6243 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6244 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6245 inst
.operands
[i
].isvec
= 1;
6246 inst
.operands
[i
].vectype
= optype
;
6247 inst
.operands
[i
++].present
= 1;
6249 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6251 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6252 Case 13: VMOV <Sd>, <Rm> */
6253 inst
.operands
[i
].reg
= val
;
6254 inst
.operands
[i
].isreg
= 1;
6255 inst
.operands
[i
].present
= 1;
6257 if (rtype
== REG_TYPE_NQ
)
6259 first_error (_("can't use Neon quad register here"));
6262 else if (rtype
!= REG_TYPE_VFS
)
6265 if (skip_past_comma (&ptr
) == FAIL
)
6267 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6269 inst
.operands
[i
].reg
= val
;
6270 inst
.operands
[i
].isreg
= 1;
6271 inst
.operands
[i
].present
= 1;
6274 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6277 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6278 Case 1: VMOV<c><q> <Dd>, <Dm>
6279 Case 8: VMOV.F32 <Sd>, <Sm>
6280 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6285 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6286 inst
.operands
[i
].isvec
= 1;
6287 inst
.operands
[i
].vectype
= optype
;
6288 inst
.operands
[i
].present
= 1;
6290 if (skip_past_comma (&ptr
) == SUCCESS
)
6295 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
++].present
= 1;
6302 if (skip_past_comma (&ptr
) == FAIL
)
6305 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6308 inst
.operands
[i
].reg
= val
;
6309 inst
.operands
[i
].isreg
= 1;
6310 inst
.operands
[i
].present
= 1;
6313 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6314 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6315 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6316 Case 10: VMOV.F32 <Sd>, #<imm>
6317 Case 11: VMOV.F64 <Dd>, #<imm> */
6318 inst
.operands
[i
].immisfloat
= 1;
6319 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6321 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6322 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6326 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6330 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
++].present
= 1;
6337 if (skip_past_comma (&ptr
) == FAIL
)
6340 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6342 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6343 inst
.operands
[i
].reg
= val
;
6344 inst
.operands
[i
].isscalar
= 1;
6345 inst
.operands
[i
].present
= 1;
6346 inst
.operands
[i
].vectype
= optype
;
6348 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6350 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6351 inst
.operands
[i
].reg
= val
;
6352 inst
.operands
[i
].isreg
= 1;
6353 inst
.operands
[i
++].present
= 1;
6355 if (skip_past_comma (&ptr
) == FAIL
)
6358 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6361 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
].isvec
= 1;
6368 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6369 inst
.operands
[i
].vectype
= optype
;
6370 inst
.operands
[i
].present
= 1;
6372 if (rtype
== REG_TYPE_VFS
)
6376 if (skip_past_comma (&ptr
) == FAIL
)
6378 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6381 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6384 inst
.operands
[i
].reg
= val
;
6385 inst
.operands
[i
].isreg
= 1;
6386 inst
.operands
[i
].isvec
= 1;
6387 inst
.operands
[i
].issingle
= 1;
6388 inst
.operands
[i
].vectype
= optype
;
6389 inst
.operands
[i
].present
= 1;
6392 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6396 inst
.operands
[i
].reg
= val
;
6397 inst
.operands
[i
].isreg
= 1;
6398 inst
.operands
[i
].isvec
= 1;
6399 inst
.operands
[i
].issingle
= 1;
6400 inst
.operands
[i
].vectype
= optype
;
6401 inst
.operands
[i
].present
= 1;
6406 first_error (_("parse error"));
6410 /* Successfully parsed the operands. Update args. */
6416 first_error (_("expected comma"));
6420 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6424 /* Use this macro when the operand constraints are different
6425 for ARM and THUMB (e.g. ldrd). */
6426 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6427 ((arm_operand) | ((thumb_operand) << 16))
6429 /* Matcher codes for parse_operands. */
6430 enum operand_parse_code
6432 OP_stop
, /* end of line */
6434 OP_RR
, /* ARM register */
6435 OP_RRnpc
, /* ARM register, not r15 */
6436 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6437 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6438 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6439 optional trailing ! */
6440 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6441 OP_RCP
, /* Coprocessor number */
6442 OP_RCN
, /* Coprocessor register */
6443 OP_RF
, /* FPA register */
6444 OP_RVS
, /* VFP single precision register */
6445 OP_RVD
, /* VFP double precision register (0..15) */
6446 OP_RND
, /* Neon double precision register (0..31) */
6447 OP_RNQ
, /* Neon quad precision register */
6448 OP_RVSD
, /* VFP single or double precision register */
6449 OP_RNDQ
, /* Neon double or quad precision register */
6450 OP_RNSDQ
, /* Neon single, double or quad precision register */
6451 OP_RNSC
, /* Neon scalar D[X] */
6452 OP_RVC
, /* VFP control register */
6453 OP_RMF
, /* Maverick F register */
6454 OP_RMD
, /* Maverick D register */
6455 OP_RMFX
, /* Maverick FX register */
6456 OP_RMDX
, /* Maverick DX register */
6457 OP_RMAX
, /* Maverick AX register */
6458 OP_RMDS
, /* Maverick DSPSC register */
6459 OP_RIWR
, /* iWMMXt wR register */
6460 OP_RIWC
, /* iWMMXt wC register */
6461 OP_RIWG
, /* iWMMXt wCG register */
6462 OP_RXA
, /* XScale accumulator register */
6464 OP_REGLST
, /* ARM register list */
6465 OP_VRSLST
, /* VFP single-precision register list */
6466 OP_VRDLST
, /* VFP double-precision register list */
6467 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6468 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6469 OP_NSTRLST
, /* Neon element/structure list */
6471 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6472 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6473 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6474 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6475 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6476 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6477 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6478 OP_VMOV
, /* Neon VMOV operands. */
6479 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6480 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6481 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6483 OP_I0
, /* immediate zero */
6484 OP_I7
, /* immediate value 0 .. 7 */
6485 OP_I15
, /* 0 .. 15 */
6486 OP_I16
, /* 1 .. 16 */
6487 OP_I16z
, /* 0 .. 16 */
6488 OP_I31
, /* 0 .. 31 */
6489 OP_I31w
, /* 0 .. 31, optional trailing ! */
6490 OP_I32
, /* 1 .. 32 */
6491 OP_I32z
, /* 0 .. 32 */
6492 OP_I63
, /* 0 .. 63 */
6493 OP_I63s
, /* -64 .. 63 */
6494 OP_I64
, /* 1 .. 64 */
6495 OP_I64z
, /* 0 .. 64 */
6496 OP_I255
, /* 0 .. 255 */
6498 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6499 OP_I7b
, /* 0 .. 7 */
6500 OP_I15b
, /* 0 .. 15 */
6501 OP_I31b
, /* 0 .. 31 */
6503 OP_SH
, /* shifter operand */
6504 OP_SHG
, /* shifter operand with possible group relocation */
6505 OP_ADDR
, /* Memory address expression (any mode) */
6506 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6507 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6508 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6509 OP_EXP
, /* arbitrary expression */
6510 OP_EXPi
, /* same, with optional immediate prefix */
6511 OP_EXPr
, /* same, with optional relocation suffix */
6512 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6514 OP_CPSF
, /* CPS flags */
6515 OP_ENDI
, /* Endianness specifier */
6516 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6517 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6518 OP_COND
, /* conditional code */
6519 OP_TB
, /* Table branch. */
6521 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6523 OP_RRnpc_I0
, /* ARM register or literal 0 */
6524 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6525 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6526 OP_RF_IF
, /* FPA register or immediate */
6527 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6528 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6530 /* Optional operands. */
6531 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6532 OP_oI31b
, /* 0 .. 31 */
6533 OP_oI32b
, /* 1 .. 32 */
6534 OP_oI32z
, /* 0 .. 32 */
6535 OP_oIffffb
, /* 0 .. 65535 */
6536 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6538 OP_oRR
, /* ARM register */
6539 OP_oRRnpc
, /* ARM register, not the PC */
6540 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6541 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6542 OP_oRND
, /* Optional Neon double precision register */
6543 OP_oRNQ
, /* Optional Neon quad precision register */
6544 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6545 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6546 OP_oSHll
, /* LSL immediate */
6547 OP_oSHar
, /* ASR immediate */
6548 OP_oSHllar
, /* LSL or ASR immediate */
6549 OP_oROR
, /* ROR 0/8/16/24 */
6550 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6552 /* Some pre-defined mixed (ARM/THUMB) operands. */
6553 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6554 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6555 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6557 OP_FIRST_OPTIONAL
= OP_oI7b
6560 /* Generic instruction operand parser. This does no encoding and no
6561 semantic validation; it merely squirrels values away in the inst
6562 structure. Returns SUCCESS or FAIL depending on whether the
6563 specified grammar matched. */
6565 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6567 unsigned const int *upat
= pattern
;
6568 char *backtrack_pos
= 0;
6569 const char *backtrack_error
= 0;
6570 int i
, val
= 0, backtrack_index
= 0;
6571 enum arm_reg_type rtype
;
6572 parse_operand_result result
;
6573 unsigned int op_parse_code
;
6575 #define po_char_or_fail(chr) \
6578 if (skip_past_char (&str, chr) == FAIL) \
6583 #define po_reg_or_fail(regtype) \
6586 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6587 & inst.operands[i].vectype); \
6590 first_error (_(reg_expected_msgs[regtype])); \
6593 inst.operands[i].reg = val; \
6594 inst.operands[i].isreg = 1; \
6595 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6596 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6597 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6598 || rtype == REG_TYPE_VFD \
6599 || rtype == REG_TYPE_NQ); \
6603 #define po_reg_or_goto(regtype, label) \
6606 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6607 & inst.operands[i].vectype); \
6611 inst.operands[i].reg = val; \
6612 inst.operands[i].isreg = 1; \
6613 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6614 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6615 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6616 || rtype == REG_TYPE_VFD \
6617 || rtype == REG_TYPE_NQ); \
6621 #define po_imm_or_fail(min, max, popt) \
6624 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6626 inst.operands[i].imm = val; \
6630 #define po_scalar_or_goto(elsz, label) \
6633 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6636 inst.operands[i].reg = val; \
6637 inst.operands[i].isscalar = 1; \
6641 #define po_misc_or_fail(expr) \
6649 #define po_misc_or_fail_no_backtrack(expr) \
6653 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6654 backtrack_pos = 0; \
6655 if (result != PARSE_OPERAND_SUCCESS) \
6660 #define po_barrier_or_imm(str) \
6663 val = parse_barrier (&str); \
6664 if (val == FAIL && ! ISALPHA (*str)) \
6667 /* ISB can only take SY as an option. */ \
6668 || ((inst.instruction & 0xf0) == 0x60 \
6671 inst.error = _("invalid barrier type"); \
6672 backtrack_pos = 0; \
6678 skip_whitespace (str
);
6680 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6682 op_parse_code
= upat
[i
];
6683 if (op_parse_code
>= 1<<16)
6684 op_parse_code
= thumb
? (op_parse_code
>> 16)
6685 : (op_parse_code
& ((1<<16)-1));
6687 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6689 /* Remember where we are in case we need to backtrack. */
6690 gas_assert (!backtrack_pos
);
6691 backtrack_pos
= str
;
6692 backtrack_error
= inst
.error
;
6693 backtrack_index
= i
;
6696 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6697 po_char_or_fail (',');
6699 switch (op_parse_code
)
6707 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6708 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6709 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6710 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6711 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6712 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6714 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6716 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6718 /* Also accept generic coprocessor regs for unknown registers. */
6720 po_reg_or_fail (REG_TYPE_CN
);
6722 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6723 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6724 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6725 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6726 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6727 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6728 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6729 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6730 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6731 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6733 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6735 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6736 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6738 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6740 /* Neon scalar. Using an element size of 8 means that some invalid
6741 scalars are accepted here, so deal with those in later code. */
6742 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6746 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6749 po_imm_or_fail (0, 0, TRUE
);
6754 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6759 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6762 if (parse_ifimm_zero (&str
))
6763 inst
.operands
[i
].imm
= 0;
6767 = _("only floating point zero is allowed as immediate value");
6775 po_scalar_or_goto (8, try_rr
);
6778 po_reg_or_fail (REG_TYPE_RN
);
6784 po_scalar_or_goto (8, try_nsdq
);
6787 po_reg_or_fail (REG_TYPE_NSDQ
);
6793 po_scalar_or_goto (8, try_ndq
);
6796 po_reg_or_fail (REG_TYPE_NDQ
);
6802 po_scalar_or_goto (8, try_vfd
);
6805 po_reg_or_fail (REG_TYPE_VFD
);
6810 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6811 not careful then bad things might happen. */
6812 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6817 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6820 /* There's a possibility of getting a 64-bit immediate here, so
6821 we need special handling. */
6822 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6825 inst
.error
= _("immediate value is out of range");
6833 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6836 po_imm_or_fail (0, 63, TRUE
);
6841 po_char_or_fail ('[');
6842 po_reg_or_fail (REG_TYPE_RN
);
6843 po_char_or_fail (']');
6849 po_reg_or_fail (REG_TYPE_RN
);
6850 if (skip_past_char (&str
, '!') == SUCCESS
)
6851 inst
.operands
[i
].writeback
= 1;
6855 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6856 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6857 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6858 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6859 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6860 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6861 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6862 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6863 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6864 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6865 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6866 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6868 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6870 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6871 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6873 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6874 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6875 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6876 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6878 /* Immediate variants */
6880 po_char_or_fail ('{');
6881 po_imm_or_fail (0, 255, TRUE
);
6882 po_char_or_fail ('}');
6886 /* The expression parser chokes on a trailing !, so we have
6887 to find it first and zap it. */
6890 while (*s
&& *s
!= ',')
6895 inst
.operands
[i
].writeback
= 1;
6897 po_imm_or_fail (0, 31, TRUE
);
6905 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6910 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6915 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6917 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6919 val
= parse_reloc (&str
);
6922 inst
.error
= _("unrecognized relocation suffix");
6925 else if (val
!= BFD_RELOC_UNUSED
)
6927 inst
.operands
[i
].imm
= val
;
6928 inst
.operands
[i
].hasreloc
= 1;
6933 /* Operand for MOVW or MOVT. */
6935 po_misc_or_fail (parse_half (&str
));
6938 /* Register or expression. */
6939 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6940 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6942 /* Register or immediate. */
6943 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6944 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6946 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6948 if (!is_immediate_prefix (*str
))
6951 val
= parse_fpa_immediate (&str
);
6954 /* FPA immediates are encoded as registers 8-15.
6955 parse_fpa_immediate has already applied the offset. */
6956 inst
.operands
[i
].reg
= val
;
6957 inst
.operands
[i
].isreg
= 1;
6960 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6961 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6963 /* Two kinds of register. */
6966 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6968 || (rege
->type
!= REG_TYPE_MMXWR
6969 && rege
->type
!= REG_TYPE_MMXWC
6970 && rege
->type
!= REG_TYPE_MMXWCG
))
6972 inst
.error
= _("iWMMXt data or control register expected");
6975 inst
.operands
[i
].reg
= rege
->number
;
6976 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6982 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6984 || (rege
->type
!= REG_TYPE_MMXWC
6985 && rege
->type
!= REG_TYPE_MMXWCG
))
6987 inst
.error
= _("iWMMXt control register expected");
6990 inst
.operands
[i
].reg
= rege
->number
;
6991 inst
.operands
[i
].isreg
= 1;
6996 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6997 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6998 case OP_oROR
: val
= parse_ror (&str
); break;
6999 case OP_COND
: val
= parse_cond (&str
); break;
7000 case OP_oBARRIER_I15
:
7001 po_barrier_or_imm (str
); break;
7003 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7009 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7010 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7012 inst
.error
= _("Banked registers are not available with this "
7018 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7022 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7025 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7027 if (strncasecmp (str
, "APSR_", 5) == 0)
7034 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7035 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7036 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7037 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7038 default: found
= 16;
7042 inst
.operands
[i
].isvec
= 1;
7043 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7044 inst
.operands
[i
].reg
= REG_PC
;
7051 po_misc_or_fail (parse_tb (&str
));
7054 /* Register lists. */
7056 val
= parse_reg_list (&str
);
7059 inst
.operands
[i
].writeback
= 1;
7065 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7069 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7073 /* Allow Q registers too. */
7074 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7081 inst
.operands
[i
].issingle
= 1;
7086 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7091 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7092 &inst
.operands
[i
].vectype
);
7095 /* Addressing modes */
7097 po_misc_or_fail (parse_address (&str
, i
));
7101 po_misc_or_fail_no_backtrack (
7102 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7106 po_misc_or_fail_no_backtrack (
7107 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7111 po_misc_or_fail_no_backtrack (
7112 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7116 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7120 po_misc_or_fail_no_backtrack (
7121 parse_shifter_operand_group_reloc (&str
, i
));
7125 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7129 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7133 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7137 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7140 /* Various value-based sanity checks and shared operations. We
7141 do not signal immediate failures for the register constraints;
7142 this allows a syntax error to take precedence. */
7143 switch (op_parse_code
)
7151 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7152 inst
.error
= BAD_PC
;
7157 if (inst
.operands
[i
].isreg
)
7159 if (inst
.operands
[i
].reg
== REG_PC
)
7160 inst
.error
= BAD_PC
;
7161 else if (inst
.operands
[i
].reg
== REG_SP
)
7162 inst
.error
= BAD_SP
;
7167 if (inst
.operands
[i
].isreg
7168 && inst
.operands
[i
].reg
== REG_PC
7169 && (inst
.operands
[i
].writeback
|| thumb
))
7170 inst
.error
= BAD_PC
;
7179 case OP_oBARRIER_I15
:
7188 inst
.operands
[i
].imm
= val
;
7195 /* If we get here, this operand was successfully parsed. */
7196 inst
.operands
[i
].present
= 1;
7200 inst
.error
= BAD_ARGS
;
7205 /* The parse routine should already have set inst.error, but set a
7206 default here just in case. */
7208 inst
.error
= _("syntax error");
7212 /* Do not backtrack over a trailing optional argument that
7213 absorbed some text. We will only fail again, with the
7214 'garbage following instruction' error message, which is
7215 probably less helpful than the current one. */
7216 if (backtrack_index
== i
&& backtrack_pos
!= str
7217 && upat
[i
+1] == OP_stop
)
7220 inst
.error
= _("syntax error");
7224 /* Try again, skipping the optional argument at backtrack_pos. */
7225 str
= backtrack_pos
;
7226 inst
.error
= backtrack_error
;
7227 inst
.operands
[backtrack_index
].present
= 0;
7228 i
= backtrack_index
;
7232 /* Check that we have parsed all the arguments. */
7233 if (*str
!= '\0' && !inst
.error
)
7234 inst
.error
= _("garbage following instruction");
7236 return inst
.error
? FAIL
: SUCCESS
;
7239 #undef po_char_or_fail
7240 #undef po_reg_or_fail
7241 #undef po_reg_or_goto
7242 #undef po_imm_or_fail
7243 #undef po_scalar_or_fail
7244 #undef po_barrier_or_imm
7246 /* Shorthand macro for instruction encoding functions issuing errors. */
7247 #define constraint(expr, err) \
7258 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7259 instructions are unpredictable if these registers are used. This
7260 is the BadReg predicate in ARM's Thumb-2 documentation. */
7261 #define reject_bad_reg(reg) \
7263 if (reg == REG_SP || reg == REG_PC) \
7265 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7270 /* If REG is R13 (the stack pointer), warn that its use is
7272 #define warn_deprecated_sp(reg) \
7274 if (warn_on_deprecated && reg == REG_SP) \
7275 as_tsktsk (_("use of r13 is deprecated")); \
7278 /* Functions for operand encoding. ARM, then Thumb. */
7280 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7282 /* If VAL can be encoded in the immediate field of an ARM instruction,
7283 return the encoded form. Otherwise, return FAIL. */
7286 encode_arm_immediate (unsigned int val
)
7290 for (i
= 0; i
< 32; i
+= 2)
7291 if ((a
= rotate_left (val
, i
)) <= 0xff)
7292 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7297 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7298 return the encoded form. Otherwise, return FAIL. */
7300 encode_thumb32_immediate (unsigned int val
)
7307 for (i
= 1; i
<= 24; i
++)
7310 if ((val
& ~(0xff << i
)) == 0)
7311 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7315 if (val
== ((a
<< 16) | a
))
7317 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7321 if (val
== ((a
<< 16) | a
))
7322 return 0x200 | (a
>> 8);
7326 /* Encode a VFP SP or DP register number into inst.instruction. */
7329 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7331 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7334 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7337 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7340 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7345 first_error (_("D register out of range for selected VFP version"));
7353 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7357 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7361 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7365 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7369 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7373 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7381 /* Encode a <shift> in an ARM-format instruction. The immediate,
7382 if any, is handled by md_apply_fix. */
7384 encode_arm_shift (int i
)
7386 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7387 inst
.instruction
|= SHIFT_ROR
<< 5;
7390 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7391 if (inst
.operands
[i
].immisreg
)
7393 inst
.instruction
|= SHIFT_BY_REG
;
7394 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7397 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7402 encode_arm_shifter_operand (int i
)
7404 if (inst
.operands
[i
].isreg
)
7406 inst
.instruction
|= inst
.operands
[i
].reg
;
7407 encode_arm_shift (i
);
7411 inst
.instruction
|= INST_IMMEDIATE
;
7412 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7413 inst
.instruction
|= inst
.operands
[i
].imm
;
7417 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7419 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7422 Generate an error if the operand is not a register. */
7423 constraint (!inst
.operands
[i
].isreg
,
7424 _("Instruction does not support =N addresses"));
7426 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7428 if (inst
.operands
[i
].preind
)
7432 inst
.error
= _("instruction does not accept preindexed addressing");
7435 inst
.instruction
|= PRE_INDEX
;
7436 if (inst
.operands
[i
].writeback
)
7437 inst
.instruction
|= WRITE_BACK
;
7440 else if (inst
.operands
[i
].postind
)
7442 gas_assert (inst
.operands
[i
].writeback
);
7444 inst
.instruction
|= WRITE_BACK
;
7446 else /* unindexed - only for coprocessor */
7448 inst
.error
= _("instruction does not accept unindexed addressing");
7452 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7453 && (((inst
.instruction
& 0x000f0000) >> 16)
7454 == ((inst
.instruction
& 0x0000f000) >> 12)))
7455 as_warn ((inst
.instruction
& LOAD_BIT
)
7456 ? _("destination register same as write-back base")
7457 : _("source register same as write-back base"));
7460 /* inst.operands[i] was set up by parse_address. Encode it into an
7461 ARM-format mode 2 load or store instruction. If is_t is true,
7462 reject forms that cannot be used with a T instruction (i.e. not
7465 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7467 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7469 encode_arm_addr_mode_common (i
, is_t
);
7471 if (inst
.operands
[i
].immisreg
)
7473 constraint ((inst
.operands
[i
].imm
== REG_PC
7474 || (is_pc
&& inst
.operands
[i
].writeback
)),
7476 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7477 inst
.instruction
|= inst
.operands
[i
].imm
;
7478 if (!inst
.operands
[i
].negative
)
7479 inst
.instruction
|= INDEX_UP
;
7480 if (inst
.operands
[i
].shifted
)
7482 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7483 inst
.instruction
|= SHIFT_ROR
<< 5;
7486 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7487 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7491 else /* immediate offset in inst.reloc */
7493 if (is_pc
&& !inst
.reloc
.pc_rel
)
7495 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7498 cannot use PC in addressing.
7499 PC cannot be used in writeback addressing, either. */
7500 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7503 /* Use of PC in str is deprecated for ARMv7. */
7504 if (warn_on_deprecated
7506 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7507 as_tsktsk (_("use of PC in this instruction is deprecated"));
7510 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7512 /* Prefer + for zero encoded value. */
7513 if (!inst
.operands
[i
].negative
)
7514 inst
.instruction
|= INDEX_UP
;
7515 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7520 /* inst.operands[i] was set up by parse_address. Encode it into an
7521 ARM-format mode 3 load or store instruction. Reject forms that
7522 cannot be used with such instructions. If is_t is true, reject
7523 forms that cannot be used with a T instruction (i.e. not
7526 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7528 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7530 inst
.error
= _("instruction does not accept scaled register index");
7534 encode_arm_addr_mode_common (i
, is_t
);
7536 if (inst
.operands
[i
].immisreg
)
7538 constraint ((inst
.operands
[i
].imm
== REG_PC
7539 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7541 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7543 inst
.instruction
|= inst
.operands
[i
].imm
;
7544 if (!inst
.operands
[i
].negative
)
7545 inst
.instruction
|= INDEX_UP
;
7547 else /* immediate offset in inst.reloc */
7549 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7550 && inst
.operands
[i
].writeback
),
7552 inst
.instruction
|= HWOFFSET_IMM
;
7553 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7555 /* Prefer + for zero encoded value. */
7556 if (!inst
.operands
[i
].negative
)
7557 inst
.instruction
|= INDEX_UP
;
7559 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7564 /* Write immediate bits [7:0] to the following locations:
7566 |28/24|23 19|18 16|15 4|3 0|
7567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7569 This function is used by VMOV/VMVN/VORR/VBIC. */
7572 neon_write_immbits (unsigned immbits
)
7574 inst
.instruction
|= immbits
& 0xf;
7575 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7576 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7579 /* Invert low-order SIZE bits of XHI:XLO. */
7582 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7584 unsigned immlo
= xlo
? *xlo
: 0;
7585 unsigned immhi
= xhi
? *xhi
: 0;
7590 immlo
= (~immlo
) & 0xff;
7594 immlo
= (~immlo
) & 0xffff;
7598 immhi
= (~immhi
) & 0xffffffff;
7602 immlo
= (~immlo
) & 0xffffffff;
7616 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7620 neon_bits_same_in_bytes (unsigned imm
)
7622 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7623 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7624 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7625 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7628 /* For immediate of above form, return 0bABCD. */
7631 neon_squash_bits (unsigned imm
)
7633 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7634 | ((imm
& 0x01000000) >> 21);
7637 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7640 neon_qfloat_bits (unsigned imm
)
7642 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7645 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7646 the instruction. *OP is passed as the initial value of the op field, and
7647 may be set to a different value depending on the constant (i.e.
7648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7649 MVN). If the immediate looks like a repeated pattern then also
7650 try smaller element sizes. */
7653 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7654 unsigned *immbits
, int *op
, int size
,
7655 enum neon_el_type type
)
7657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7659 if (type
== NT_float
&& !float_p
)
7662 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7664 if (size
!= 32 || *op
== 1)
7666 *immbits
= neon_qfloat_bits (immlo
);
7672 if (neon_bits_same_in_bytes (immhi
)
7673 && neon_bits_same_in_bytes (immlo
))
7677 *immbits
= (neon_squash_bits (immhi
) << 4)
7678 | neon_squash_bits (immlo
);
7689 if (immlo
== (immlo
& 0x000000ff))
7694 else if (immlo
== (immlo
& 0x0000ff00))
7696 *immbits
= immlo
>> 8;
7699 else if (immlo
== (immlo
& 0x00ff0000))
7701 *immbits
= immlo
>> 16;
7704 else if (immlo
== (immlo
& 0xff000000))
7706 *immbits
= immlo
>> 24;
7709 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7711 *immbits
= (immlo
>> 8) & 0xff;
7714 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7716 *immbits
= (immlo
>> 16) & 0xff;
7720 if ((immlo
& 0xffff) != (immlo
>> 16))
7727 if (immlo
== (immlo
& 0x000000ff))
7732 else if (immlo
== (immlo
& 0x0000ff00))
7734 *immbits
= immlo
>> 8;
7738 if ((immlo
& 0xff) != (immlo
>> 8))
7743 if (immlo
== (immlo
& 0x000000ff))
7745 /* Don't allow MVN with 8-bit immediate. */
7755 #if defined BFD_HOST_64_BIT
7756 /* Returns TRUE if double precision value V may be cast
7757 to single precision without loss of accuracy. */
7760 is_double_a_single (bfd_int64_t v
)
7762 int exp
= (int)((v
>> 52) & 0x7FF);
7763 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFF);
7765 return (exp
== 0 || exp
== 0x7FF
7766 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7767 && (mantissa
& 0x1FFFFFFFl
) == 0;
7770 /* Returns a double precision value casted to single precision
7771 (ignoring the least significant bits in exponent and mantissa). */
7774 double_to_single (bfd_int64_t v
)
7776 int sign
= (int) ((v
>> 63) & 1l);
7777 int exp
= (int) ((v
>> 52) & 0x7FF);
7778 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFF);
7784 exp
= exp
- 1023 + 127;
7793 /* No denormalized numbers. */
7799 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7801 #endif /* BFD_HOST_64_BIT */
7810 static void do_vfp_nsyn_opcode (const char *);
7812 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7813 Determine whether it can be performed with a move instruction; if
7814 it can, convert inst.instruction to that move instruction and
7815 return TRUE; if it can't, convert inst.instruction to a literal-pool
7816 load and return FALSE. If this is not a valid thing to do in the
7817 current context, set inst.error and return TRUE.
7819 inst.operands[i] describes the destination register. */
7822 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7825 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7826 bfd_boolean arm_p
= (t
== CONST_ARM
);
7829 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7833 if ((inst
.instruction
& tbit
) == 0)
7835 inst
.error
= _("invalid pseudo operation");
7839 if (inst
.reloc
.exp
.X_op
!= O_constant
7840 && inst
.reloc
.exp
.X_op
!= O_symbol
7841 && inst
.reloc
.exp
.X_op
!= O_big
)
7843 inst
.error
= _("constant expression expected");
7847 if (inst
.reloc
.exp
.X_op
== O_constant
7848 || inst
.reloc
.exp
.X_op
== O_big
)
7850 #if defined BFD_HOST_64_BIT
7855 if (inst
.reloc
.exp
.X_op
== O_big
)
7857 LITTLENUM_TYPE w
[X_PRECISION
];
7860 if (inst
.reloc
.exp
.X_add_number
== -1)
7862 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7864 /* FIXME: Should we check words w[2..5] ? */
7869 #if defined BFD_HOST_64_BIT
7871 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7872 << LITTLENUM_NUMBER_OF_BITS
)
7873 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7874 << LITTLENUM_NUMBER_OF_BITS
)
7875 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7876 << LITTLENUM_NUMBER_OF_BITS
)
7877 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7879 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7880 | (l
[0] & LITTLENUM_MASK
);
7884 v
= inst
.reloc
.exp
.X_add_number
;
7886 if (!inst
.operands
[i
].issingle
)
7890 if ((v
& ~0xFF) == 0)
7892 /* This can be done with a mov(1) instruction. */
7893 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7894 inst
.instruction
|= v
;
7898 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)
7899 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7901 /* Check if on thumb2 it can be done with a mov.w or mvn.w instruction. */
7902 unsigned int newimm
;
7903 bfd_boolean isNegated
;
7905 newimm
= encode_thumb32_immediate (v
);
7906 if (newimm
!= (unsigned int) FAIL
)
7910 newimm
= encode_thumb32_immediate (~ v
);
7911 if (newimm
!= (unsigned int) FAIL
)
7915 if (newimm
!= (unsigned int) FAIL
)
7917 inst
.instruction
= 0xf04f0000 | (inst
.operands
[i
].reg
<< 8);
7918 inst
.instruction
|= (isNegated
?0x200000:0);
7919 inst
.instruction
|= (newimm
& 0x800) << 15;
7920 inst
.instruction
|= (newimm
& 0x700) << 4;
7921 inst
.instruction
|= (newimm
& 0x0ff);
7924 else if ((v
& ~0xFFFF) == 0 || (v
& ~0xFFFF0000) == 0)
7926 /* The number may be loaded with a movw/movt instruction. */
7929 if ((inst
.reloc
.exp
.X_add_number
& ~0xFFFF) == 0)
7931 inst
.instruction
= 0xf2400000;
7936 inst
.instruction
= 0xf2c00000;
7940 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7941 inst
.instruction
|= (imm
& 0xf000) << 4;
7942 inst
.instruction
|= (imm
& 0x0800) << 15;
7943 inst
.instruction
|= (imm
& 0x0700) << 4;
7944 inst
.instruction
|= (imm
& 0x00ff);
7951 int value
= encode_arm_immediate (v
);
7955 /* This can be done with a mov instruction. */
7956 inst
.instruction
&= LITERAL_MASK
;
7957 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7958 inst
.instruction
|= value
& 0xfff;
7962 value
= encode_arm_immediate (~ v
);
7965 /* This can be done with a mvn instruction. */
7966 inst
.instruction
&= LITERAL_MASK
;
7967 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7968 inst
.instruction
|= value
& 0xfff;
7972 else if (t
== CONST_VEC
)
7975 unsigned immbits
= 0;
7976 unsigned immlo
= inst
.operands
[1].imm
;
7977 unsigned immhi
= inst
.operands
[1].regisimm
7978 ? inst
.operands
[1].reg
7979 : inst
.reloc
.exp
.X_unsigned
7981 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7982 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7983 &op
, 64, NT_invtype
);
7987 neon_invert_size (&immlo
, &immhi
, 64);
7989 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7990 &op
, 64, NT_invtype
);
7995 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8001 /* Fill other bits in vmov encoding for both thumb and arm. */
8003 inst
.instruction
|= (0x7 << 29) | (0xF << 24);
8005 inst
.instruction
|= (0xF << 28) | (0x1 << 25);
8006 neon_write_immbits (immbits
);
8014 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8015 if (inst
.operands
[i
].issingle
8016 && is_quarter_float (inst
.operands
[1].imm
)
8017 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8019 inst
.operands
[1].imm
=
8020 neon_qfloat_bits (v
);
8021 do_vfp_nsyn_opcode ("fconsts");
8025 /* If our host does not support a 64-bit type then we cannot perform
8026 the following optimization. This mean that there will be a
8027 discrepancy between the output produced by an assembler built for
8028 a 32-bit-only host and the output produced from a 64-bit host, but
8029 this cannot be helped. */
8030 #if defined BFD_HOST_64_BIT
8031 else if (!inst
.operands
[1].issingle
8032 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8034 if (is_double_a_single (v
)
8035 && is_quarter_float (double_to_single (v
)))
8037 inst
.operands
[1].imm
=
8038 neon_qfloat_bits (double_to_single (v
));
8039 do_vfp_nsyn_opcode ("fconstd");
8047 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8048 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8051 inst
.operands
[1].reg
= REG_PC
;
8052 inst
.operands
[1].isreg
= 1;
8053 inst
.operands
[1].preind
= 1;
8054 inst
.reloc
.pc_rel
= 1;
8055 inst
.reloc
.type
= (thumb_p
8056 ? BFD_RELOC_ARM_THUMB_OFFSET
8058 ? BFD_RELOC_ARM_HWLITERAL
8059 : BFD_RELOC_ARM_LITERAL
));
8063 /* inst.operands[i] was set up by parse_address. Encode it into an
8064 ARM-format instruction. Reject all forms which cannot be encoded
8065 into a coprocessor load/store instruction. If wb_ok is false,
8066 reject use of writeback; if unind_ok is false, reject use of
8067 unindexed addressing. If reloc_override is not 0, use it instead
8068 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8069 (in which case it is preserved). */
8072 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8074 if (!inst
.operands
[i
].isreg
)
8077 if (! inst
.operands
[0].isvec
)
8079 inst
.error
= _("invalid co-processor operand");
8082 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8086 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8088 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8090 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8092 gas_assert (!inst
.operands
[i
].writeback
);
8095 inst
.error
= _("instruction does not support unindexed addressing");
8098 inst
.instruction
|= inst
.operands
[i
].imm
;
8099 inst
.instruction
|= INDEX_UP
;
8103 if (inst
.operands
[i
].preind
)
8104 inst
.instruction
|= PRE_INDEX
;
8106 if (inst
.operands
[i
].writeback
)
8108 if (inst
.operands
[i
].reg
== REG_PC
)
8110 inst
.error
= _("pc may not be used with write-back");
8115 inst
.error
= _("instruction does not support writeback");
8118 inst
.instruction
|= WRITE_BACK
;
8122 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8123 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8124 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8125 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8128 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8130 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8133 /* Prefer + for zero encoded value. */
8134 if (!inst
.operands
[i
].negative
)
8135 inst
.instruction
|= INDEX_UP
;
8140 /* Functions for instruction encoding, sorted by sub-architecture.
8141 First some generics; their names are taken from the conventional
8142 bit positions for register arguments in ARM format instructions. */
8152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8159 inst
.instruction
|= inst
.operands
[1].reg
;
8165 inst
.instruction
|= inst
.operands
[0].reg
;
8166 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8179 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8180 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8184 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8186 if (ARM_CPU_IS_ANY (cpu_variant
))
8188 as_tsktsk ("%s", msg
);
8191 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8203 unsigned Rn
= inst
.operands
[2].reg
;
8204 /* Enforce restrictions on SWP instruction. */
8205 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8207 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8208 _("Rn must not overlap other operands"));
8210 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8212 if (!check_obsolete (&arm_ext_v8
,
8213 _("swp{b} use is obsoleted for ARMv8 and later"))
8214 && warn_on_deprecated
8215 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8216 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8220 inst
.instruction
|= inst
.operands
[1].reg
;
8221 inst
.instruction
|= Rn
<< 16;
8227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8228 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8229 inst
.instruction
|= inst
.operands
[2].reg
;
8235 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8236 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8237 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8238 || inst
.reloc
.exp
.X_add_number
!= 0),
8240 inst
.instruction
|= inst
.operands
[0].reg
;
8241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8242 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8248 inst
.instruction
|= inst
.operands
[0].imm
;
8254 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8255 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8258 /* ARM instructions, in alphabetical order by function name (except
8259 that wrapper functions appear immediately after the function they
8262 /* This is a pseudo-op of the form "adr rd, label" to be converted
8263 into a relative address of the form "add rd, pc, #label-.-8". */
8268 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8270 /* Frag hacking will turn this into a sub instruction if the offset turns
8271 out to be negative. */
8272 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8273 inst
.reloc
.pc_rel
= 1;
8274 inst
.reloc
.exp
.X_add_number
-= 8;
8277 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8278 into a relative address of the form:
8279 add rd, pc, #low(label-.-8)"
8280 add rd, rd, #high(label-.-8)" */
8285 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8287 /* Frag hacking will turn this into a sub instruction if the offset turns
8288 out to be negative. */
8289 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8290 inst
.reloc
.pc_rel
= 1;
8291 inst
.size
= INSN_SIZE
* 2;
8292 inst
.reloc
.exp
.X_add_number
-= 8;
8298 if (!inst
.operands
[1].present
)
8299 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8301 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8302 encode_arm_shifter_operand (2);
8308 if (inst
.operands
[0].present
)
8309 inst
.instruction
|= inst
.operands
[0].imm
;
8311 inst
.instruction
|= 0xf;
8317 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8318 constraint (msb
> 32, _("bit-field extends past end of register"));
8319 /* The instruction encoding stores the LSB and MSB,
8320 not the LSB and width. */
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8322 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8323 inst
.instruction
|= (msb
- 1) << 16;
8331 /* #0 in second position is alternative syntax for bfc, which is
8332 the same instruction but with REG_PC in the Rm field. */
8333 if (!inst
.operands
[1].isreg
)
8334 inst
.operands
[1].reg
= REG_PC
;
8336 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8337 constraint (msb
> 32, _("bit-field extends past end of register"));
8338 /* The instruction encoding stores the LSB and MSB,
8339 not the LSB and width. */
8340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8341 inst
.instruction
|= inst
.operands
[1].reg
;
8342 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8343 inst
.instruction
|= (msb
- 1) << 16;
8349 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8350 _("bit-field extends past end of register"));
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8352 inst
.instruction
|= inst
.operands
[1].reg
;
8353 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8354 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8357 /* ARM V5 breakpoint instruction (argument parse)
8358 BKPT <16 bit unsigned immediate>
8359 Instruction is not conditional.
8360 The bit pattern given in insns[] has the COND_ALWAYS condition,
8361 and it is an error if the caller tried to override that. */
8366 /* Top 12 of 16 bits to bits 19:8. */
8367 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8369 /* Bottom 4 of 16 bits to bits 3:0. */
8370 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8374 encode_branch (int default_reloc
)
8376 if (inst
.operands
[0].hasreloc
)
8378 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8379 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8380 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8381 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8382 ? BFD_RELOC_ARM_PLT32
8383 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8386 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8387 inst
.reloc
.pc_rel
= 1;
8394 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8395 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8398 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8405 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8407 if (inst
.cond
== COND_ALWAYS
)
8408 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8410 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8414 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8417 /* ARM V5 branch-link-exchange instruction (argument parse)
8418 BLX <target_addr> ie BLX(1)
8419 BLX{<condition>} <Rm> ie BLX(2)
8420 Unfortunately, there are two different opcodes for this mnemonic.
8421 So, the insns[].value is not used, and the code here zaps values
8422 into inst.instruction.
8423 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8428 if (inst
.operands
[0].isreg
)
8430 /* Arg is a register; the opcode provided by insns[] is correct.
8431 It is not illegal to do "blx pc", just useless. */
8432 if (inst
.operands
[0].reg
== REG_PC
)
8433 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8435 inst
.instruction
|= inst
.operands
[0].reg
;
8439 /* Arg is an address; this instruction cannot be executed
8440 conditionally, and the opcode must be adjusted.
8441 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8442 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8443 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8444 inst
.instruction
= 0xfa000000;
8445 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8452 bfd_boolean want_reloc
;
8454 if (inst
.operands
[0].reg
== REG_PC
)
8455 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8457 inst
.instruction
|= inst
.operands
[0].reg
;
8458 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8459 it is for ARMv4t or earlier. */
8460 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8461 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8465 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8470 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8474 /* ARM v5TEJ. Jump to Jazelle code. */
8479 if (inst
.operands
[0].reg
== REG_PC
)
8480 as_tsktsk (_("use of r15 in bxj is not really useful"));
8482 inst
.instruction
|= inst
.operands
[0].reg
;
8485 /* Co-processor data operation:
8486 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8487 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8491 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8492 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8493 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8494 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8495 inst
.instruction
|= inst
.operands
[4].reg
;
8496 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8502 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8503 encode_arm_shifter_operand (1);
8506 /* Transfer between coprocessor and ARM registers.
8507 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8512 No special properties. */
8514 struct deprecated_coproc_regs_s
8521 arm_feature_set deprecated
;
8522 arm_feature_set obsoleted
;
8523 const char *dep_msg
;
8524 const char *obs_msg
;
8527 #define DEPR_ACCESS_V8 \
8528 N_("This coprocessor register access is deprecated in ARMv8")
8530 /* Table of all deprecated coprocessor registers. */
8531 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8533 {15, 0, 7, 10, 5, /* CP15DMB. */
8534 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8535 DEPR_ACCESS_V8
, NULL
},
8536 {15, 0, 7, 10, 4, /* CP15DSB. */
8537 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8538 DEPR_ACCESS_V8
, NULL
},
8539 {15, 0, 7, 5, 4, /* CP15ISB. */
8540 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8541 DEPR_ACCESS_V8
, NULL
},
8542 {14, 6, 1, 0, 0, /* TEEHBR. */
8543 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8544 DEPR_ACCESS_V8
, NULL
},
8545 {14, 6, 0, 0, 0, /* TEECR. */
8546 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8547 DEPR_ACCESS_V8
, NULL
},
8550 #undef DEPR_ACCESS_V8
8552 static const size_t deprecated_coproc_reg_count
=
8553 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8561 Rd
= inst
.operands
[2].reg
;
8564 if (inst
.instruction
== 0xee000010
8565 || inst
.instruction
== 0xfe000010)
8567 reject_bad_reg (Rd
);
8570 constraint (Rd
== REG_SP
, BAD_SP
);
8575 if (inst
.instruction
== 0xe000010)
8576 constraint (Rd
== REG_PC
, BAD_PC
);
8579 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8581 const struct deprecated_coproc_regs_s
*r
=
8582 deprecated_coproc_regs
+ i
;
8584 if (inst
.operands
[0].reg
== r
->cp
8585 && inst
.operands
[1].imm
== r
->opc1
8586 && inst
.operands
[3].reg
== r
->crn
8587 && inst
.operands
[4].reg
== r
->crm
8588 && inst
.operands
[5].imm
== r
->opc2
)
8590 if (! ARM_CPU_IS_ANY (cpu_variant
)
8591 && warn_on_deprecated
8592 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8593 as_tsktsk ("%s", r
->dep_msg
);
8597 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8598 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8599 inst
.instruction
|= Rd
<< 12;
8600 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8601 inst
.instruction
|= inst
.operands
[4].reg
;
8602 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8605 /* Transfer between coprocessor register and pair of ARM registers.
8606 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8611 Two XScale instructions are special cases of these:
8613 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8614 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8616 Result unpredictable if Rd or Rn is R15. */
8623 Rd
= inst
.operands
[2].reg
;
8624 Rn
= inst
.operands
[3].reg
;
8628 reject_bad_reg (Rd
);
8629 reject_bad_reg (Rn
);
8633 constraint (Rd
== REG_PC
, BAD_PC
);
8634 constraint (Rn
== REG_PC
, BAD_PC
);
8637 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8638 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8639 inst
.instruction
|= Rd
<< 12;
8640 inst
.instruction
|= Rn
<< 16;
8641 inst
.instruction
|= inst
.operands
[4].reg
;
8647 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8648 if (inst
.operands
[1].present
)
8650 inst
.instruction
|= CPSI_MMOD
;
8651 inst
.instruction
|= inst
.operands
[1].imm
;
8658 inst
.instruction
|= inst
.operands
[0].imm
;
8664 unsigned Rd
, Rn
, Rm
;
8666 Rd
= inst
.operands
[0].reg
;
8667 Rn
= (inst
.operands
[1].present
8668 ? inst
.operands
[1].reg
: Rd
);
8669 Rm
= inst
.operands
[2].reg
;
8671 constraint ((Rd
== REG_PC
), BAD_PC
);
8672 constraint ((Rn
== REG_PC
), BAD_PC
);
8673 constraint ((Rm
== REG_PC
), BAD_PC
);
8675 inst
.instruction
|= Rd
<< 16;
8676 inst
.instruction
|= Rn
<< 0;
8677 inst
.instruction
|= Rm
<< 8;
8683 /* There is no IT instruction in ARM mode. We
8684 process it to do the validation as if in
8685 thumb mode, just in case the code gets
8686 assembled for thumb using the unified syntax. */
8691 set_it_insn_type (IT_INSN
);
8692 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8693 now_it
.cc
= inst
.operands
[0].imm
;
8697 /* If there is only one register in the register list,
8698 then return its register number. Otherwise return -1. */
8700 only_one_reg_in_list (int range
)
8702 int i
= ffs (range
) - 1;
8703 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8707 encode_ldmstm(int from_push_pop_mnem
)
8709 int base_reg
= inst
.operands
[0].reg
;
8710 int range
= inst
.operands
[1].imm
;
8713 inst
.instruction
|= base_reg
<< 16;
8714 inst
.instruction
|= range
;
8716 if (inst
.operands
[1].writeback
)
8717 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8719 if (inst
.operands
[0].writeback
)
8721 inst
.instruction
|= WRITE_BACK
;
8722 /* Check for unpredictable uses of writeback. */
8723 if (inst
.instruction
& LOAD_BIT
)
8725 /* Not allowed in LDM type 2. */
8726 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8727 && ((range
& (1 << REG_PC
)) == 0))
8728 as_warn (_("writeback of base register is UNPREDICTABLE"));
8729 /* Only allowed if base reg not in list for other types. */
8730 else if (range
& (1 << base_reg
))
8731 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8735 /* Not allowed for type 2. */
8736 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8737 as_warn (_("writeback of base register is UNPREDICTABLE"));
8738 /* Only allowed if base reg not in list, or first in list. */
8739 else if ((range
& (1 << base_reg
))
8740 && (range
& ((1 << base_reg
) - 1)))
8741 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8745 /* If PUSH/POP has only one register, then use the A2 encoding. */
8746 one_reg
= only_one_reg_in_list (range
);
8747 if (from_push_pop_mnem
&& one_reg
>= 0)
8749 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8751 inst
.instruction
&= A_COND_MASK
;
8752 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8753 inst
.instruction
|= one_reg
<< 12;
8760 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8763 /* ARMv5TE load-consecutive (argument parse)
8772 constraint (inst
.operands
[0].reg
% 2 != 0,
8773 _("first transfer register must be even"));
8774 constraint (inst
.operands
[1].present
8775 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8776 _("can only transfer two consecutive registers"));
8777 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8778 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8780 if (!inst
.operands
[1].present
)
8781 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8783 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8784 register and the first register written; we have to diagnose
8785 overlap between the base and the second register written here. */
8787 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8788 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8789 as_warn (_("base register written back, and overlaps "
8790 "second transfer register"));
8792 if (!(inst
.instruction
& V4_STR_BIT
))
8794 /* For an index-register load, the index register must not overlap the
8795 destination (even if not write-back). */
8796 if (inst
.operands
[2].immisreg
8797 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8798 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8799 as_warn (_("index register overlaps transfer register"));
8801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8802 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8808 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8809 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8810 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8811 || inst
.operands
[1].negative
8812 /* This can arise if the programmer has written
8814 or if they have mistakenly used a register name as the last
8817 It is very difficult to distinguish between these two cases
8818 because "rX" might actually be a label. ie the register
8819 name has been occluded by a symbol of the same name. So we
8820 just generate a general 'bad addressing mode' type error
8821 message and leave it up to the programmer to discover the
8822 true cause and fix their mistake. */
8823 || (inst
.operands
[1].reg
== REG_PC
),
8826 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8827 || inst
.reloc
.exp
.X_add_number
!= 0,
8828 _("offset must be zero in ARM encoding"));
8830 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8833 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8834 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8840 constraint (inst
.operands
[0].reg
% 2 != 0,
8841 _("even register required"));
8842 constraint (inst
.operands
[1].present
8843 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8844 _("can only load two consecutive registers"));
8845 /* If op 1 were present and equal to PC, this function wouldn't
8846 have been called in the first place. */
8847 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8849 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8850 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8853 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8854 which is not a multiple of four is UNPREDICTABLE. */
8856 check_ldr_r15_aligned (void)
8858 constraint (!(inst
.operands
[1].immisreg
)
8859 && (inst
.operands
[0].reg
== REG_PC
8860 && inst
.operands
[1].reg
== REG_PC
8861 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8862 _("ldr to register 15 must be 4-byte alligned"));
8868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8869 if (!inst
.operands
[1].isreg
)
8870 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8872 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8873 check_ldr_r15_aligned ();
8879 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8881 if (inst
.operands
[1].preind
)
8883 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8884 || inst
.reloc
.exp
.X_add_number
!= 0,
8885 _("this instruction requires a post-indexed address"));
8887 inst
.operands
[1].preind
= 0;
8888 inst
.operands
[1].postind
= 1;
8889 inst
.operands
[1].writeback
= 1;
8891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8892 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8895 /* Halfword and signed-byte load/store operations. */
8900 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8901 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8902 if (!inst
.operands
[1].isreg
)
8903 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8905 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8911 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8913 if (inst
.operands
[1].preind
)
8915 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8916 || inst
.reloc
.exp
.X_add_number
!= 0,
8917 _("this instruction requires a post-indexed address"));
8919 inst
.operands
[1].preind
= 0;
8920 inst
.operands
[1].postind
= 1;
8921 inst
.operands
[1].writeback
= 1;
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8927 /* Co-processor register load/store.
8928 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8932 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8933 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8934 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8940 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8941 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8942 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8943 && !(inst
.instruction
& 0x00400000))
8944 as_tsktsk (_("Rd and Rm should be different in mla"));
8946 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8947 inst
.instruction
|= inst
.operands
[1].reg
;
8948 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8949 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8956 encode_arm_shifter_operand (1);
8959 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8966 top
= (inst
.instruction
& 0x00400000) != 0;
8967 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8968 _(":lower16: not allowed this instruction"));
8969 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8970 _(":upper16: not allowed instruction"));
8971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8972 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8974 imm
= inst
.reloc
.exp
.X_add_number
;
8975 /* The value is in two pieces: 0:11, 16:19. */
8976 inst
.instruction
|= (imm
& 0x00000fff);
8977 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8982 do_vfp_nsyn_mrs (void)
8984 if (inst
.operands
[0].isvec
)
8986 if (inst
.operands
[1].reg
!= 1)
8987 first_error (_("operand 1 must be FPSCR"));
8988 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8989 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8990 do_vfp_nsyn_opcode ("fmstat");
8992 else if (inst
.operands
[1].isvec
)
8993 do_vfp_nsyn_opcode ("fmrx");
9001 do_vfp_nsyn_msr (void)
9003 if (inst
.operands
[0].isvec
)
9004 do_vfp_nsyn_opcode ("fmxr");
9014 unsigned Rt
= inst
.operands
[0].reg
;
9016 if (thumb_mode
&& Rt
== REG_SP
)
9018 inst
.error
= BAD_SP
;
9022 /* APSR_ sets isvec. All other refs to PC are illegal. */
9023 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9025 inst
.error
= BAD_PC
;
9029 /* If we get through parsing the register name, we just insert the number
9030 generated into the instruction without further validation. */
9031 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9032 inst
.instruction
|= (Rt
<< 12);
9038 unsigned Rt
= inst
.operands
[1].reg
;
9041 reject_bad_reg (Rt
);
9042 else if (Rt
== REG_PC
)
9044 inst
.error
= BAD_PC
;
9048 /* If we get through parsing the register name, we just insert the number
9049 generated into the instruction without further validation. */
9050 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9051 inst
.instruction
|= (Rt
<< 12);
9059 if (do_vfp_nsyn_mrs () == SUCCESS
)
9062 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9065 if (inst
.operands
[1].isreg
)
9067 br
= inst
.operands
[1].reg
;
9068 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9069 as_bad (_("bad register for mrs"));
9073 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9074 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9076 _("'APSR', 'CPSR' or 'SPSR' expected"));
9077 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9080 inst
.instruction
|= br
;
9083 /* Two possible forms:
9084 "{C|S}PSR_<field>, Rm",
9085 "{C|S}PSR_f, #expression". */
9090 if (do_vfp_nsyn_msr () == SUCCESS
)
9093 inst
.instruction
|= inst
.operands
[0].imm
;
9094 if (inst
.operands
[1].isreg
)
9095 inst
.instruction
|= inst
.operands
[1].reg
;
9098 inst
.instruction
|= INST_IMMEDIATE
;
9099 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9100 inst
.reloc
.pc_rel
= 0;
9107 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9109 if (!inst
.operands
[2].present
)
9110 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9111 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9112 inst
.instruction
|= inst
.operands
[1].reg
;
9113 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9115 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9116 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9117 as_tsktsk (_("Rd and Rm should be different in mul"));
9120 /* Long Multiply Parser
9121 UMULL RdLo, RdHi, Rm, Rs
9122 SMULL RdLo, RdHi, Rm, Rs
9123 UMLAL RdLo, RdHi, Rm, Rs
9124 SMLAL RdLo, RdHi, Rm, Rs. */
9129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9130 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9131 inst
.instruction
|= inst
.operands
[2].reg
;
9132 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9134 /* rdhi and rdlo must be different. */
9135 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9136 as_tsktsk (_("rdhi and rdlo must be different"));
9138 /* rdhi, rdlo and rm must all be different before armv6. */
9139 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9140 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9141 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9142 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9148 if (inst
.operands
[0].present
9149 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9151 /* Architectural NOP hints are CPSR sets with no bits selected. */
9152 inst
.instruction
&= 0xf0000000;
9153 inst
.instruction
|= 0x0320f000;
9154 if (inst
.operands
[0].present
)
9155 inst
.instruction
|= inst
.operands
[0].imm
;
9159 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9160 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9161 Condition defaults to COND_ALWAYS.
9162 Error if Rd, Rn or Rm are R15. */
9167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9168 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9169 inst
.instruction
|= inst
.operands
[2].reg
;
9170 if (inst
.operands
[3].present
)
9171 encode_arm_shift (3);
9174 /* ARM V6 PKHTB (Argument Parse). */
9179 if (!inst
.operands
[3].present
)
9181 /* If the shift specifier is omitted, turn the instruction
9182 into pkhbt rd, rm, rn. */
9183 inst
.instruction
&= 0xfff00010;
9184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9185 inst
.instruction
|= inst
.operands
[1].reg
;
9186 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9190 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9191 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9192 inst
.instruction
|= inst
.operands
[2].reg
;
9193 encode_arm_shift (3);
9197 /* ARMv5TE: Preload-Cache
9198 MP Extensions: Preload for write
9202 Syntactically, like LDR with B=1, W=0, L=1. */
9207 constraint (!inst
.operands
[0].isreg
,
9208 _("'[' expected after PLD mnemonic"));
9209 constraint (inst
.operands
[0].postind
,
9210 _("post-indexed expression used in preload instruction"));
9211 constraint (inst
.operands
[0].writeback
,
9212 _("writeback used in preload instruction"));
9213 constraint (!inst
.operands
[0].preind
,
9214 _("unindexed addressing used in preload instruction"));
9215 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9218 /* ARMv7: PLI <addr_mode> */
9222 constraint (!inst
.operands
[0].isreg
,
9223 _("'[' expected after PLI mnemonic"));
9224 constraint (inst
.operands
[0].postind
,
9225 _("post-indexed expression used in preload instruction"));
9226 constraint (inst
.operands
[0].writeback
,
9227 _("writeback used in preload instruction"));
9228 constraint (!inst
.operands
[0].preind
,
9229 _("unindexed addressing used in preload instruction"));
9230 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9231 inst
.instruction
&= ~PRE_INDEX
;
9237 constraint (inst
.operands
[0].writeback
,
9238 _("push/pop do not support {reglist}^"));
9239 inst
.operands
[1] = inst
.operands
[0];
9240 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9241 inst
.operands
[0].isreg
= 1;
9242 inst
.operands
[0].writeback
= 1;
9243 inst
.operands
[0].reg
= REG_SP
;
9244 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9247 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9248 word at the specified address and the following word
9250 Unconditionally executed.
9251 Error if Rn is R15. */
9256 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9257 if (inst
.operands
[0].writeback
)
9258 inst
.instruction
|= WRITE_BACK
;
9261 /* ARM V6 ssat (argument parse). */
9266 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9267 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9268 inst
.instruction
|= inst
.operands
[2].reg
;
9270 if (inst
.operands
[3].present
)
9271 encode_arm_shift (3);
9274 /* ARM V6 usat (argument parse). */
9279 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9280 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9281 inst
.instruction
|= inst
.operands
[2].reg
;
9283 if (inst
.operands
[3].present
)
9284 encode_arm_shift (3);
9287 /* ARM V6 ssat16 (argument parse). */
9292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9293 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9294 inst
.instruction
|= inst
.operands
[2].reg
;
9300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9301 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9302 inst
.instruction
|= inst
.operands
[2].reg
;
9305 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9306 preserving the other bits.
9308 setend <endian_specifier>, where <endian_specifier> is either
9314 if (warn_on_deprecated
9315 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9316 as_tsktsk (_("setend use is deprecated for ARMv8"));
9318 if (inst
.operands
[0].imm
)
9319 inst
.instruction
|= 0x200;
9325 unsigned int Rm
= (inst
.operands
[1].present
9326 ? inst
.operands
[1].reg
9327 : inst
.operands
[0].reg
);
9329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9330 inst
.instruction
|= Rm
;
9331 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9333 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9334 inst
.instruction
|= SHIFT_BY_REG
;
9335 /* PR 12854: Error on extraneous shifts. */
9336 constraint (inst
.operands
[2].shifted
,
9337 _("extraneous shift as part of operand to shift insn"));
9340 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9346 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9347 inst
.reloc
.pc_rel
= 0;
9353 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9354 inst
.reloc
.pc_rel
= 0;
9360 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9361 inst
.reloc
.pc_rel
= 0;
9367 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9368 _("selected processor does not support SETPAN instruction"));
9370 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9376 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9377 _("selected processor does not support SETPAN instruction"));
9379 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9382 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9383 SMLAxy{cond} Rd,Rm,Rs,Rn
9384 SMLAWy{cond} Rd,Rm,Rs,Rn
9385 Error if any register is R15. */
9390 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9391 inst
.instruction
|= inst
.operands
[1].reg
;
9392 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9393 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9396 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9397 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9398 Error if any register is R15.
9399 Warning if Rdlo == Rdhi. */
9404 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9405 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9406 inst
.instruction
|= inst
.operands
[2].reg
;
9407 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9409 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9410 as_tsktsk (_("rdhi and rdlo must be different"));
9413 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9414 SMULxy{cond} Rd,Rm,Rs
9415 Error if any register is R15. */
9420 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9421 inst
.instruction
|= inst
.operands
[1].reg
;
9422 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9425 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9426 the same for both ARM and Thumb-2. */
9433 if (inst
.operands
[0].present
)
9435 reg
= inst
.operands
[0].reg
;
9436 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9441 inst
.instruction
|= reg
<< 16;
9442 inst
.instruction
|= inst
.operands
[1].imm
;
9443 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9444 inst
.instruction
|= WRITE_BACK
;
9447 /* ARM V6 strex (argument parse). */
9452 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9453 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9454 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9455 || inst
.operands
[2].negative
9456 /* See comment in do_ldrex(). */
9457 || (inst
.operands
[2].reg
== REG_PC
),
9460 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9461 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9463 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9464 || inst
.reloc
.exp
.X_add_number
!= 0,
9465 _("offset must be zero in ARM encoding"));
9467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9468 inst
.instruction
|= inst
.operands
[1].reg
;
9469 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9470 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9476 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9477 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9478 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9479 || inst
.operands
[2].negative
,
9482 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9483 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9491 constraint (inst
.operands
[1].reg
% 2 != 0,
9492 _("even register required"));
9493 constraint (inst
.operands
[2].present
9494 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9495 _("can only store two consecutive registers"));
9496 /* If op 2 were present and equal to PC, this function wouldn't
9497 have been called in the first place. */
9498 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9500 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9501 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9502 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9506 inst
.instruction
|= inst
.operands
[1].reg
;
9507 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9514 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9515 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9523 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9524 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9529 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9530 extends it to 32-bits, and adds the result to a value in another
9531 register. You can specify a rotation by 0, 8, 16, or 24 bits
9532 before extracting the 16-bit value.
9533 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9534 Condition defaults to COND_ALWAYS.
9535 Error if any register uses R15. */
9540 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9541 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9542 inst
.instruction
|= inst
.operands
[2].reg
;
9543 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9548 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9549 Condition defaults to COND_ALWAYS.
9550 Error if any register uses R15. */
9555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9556 inst
.instruction
|= inst
.operands
[1].reg
;
9557 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9560 /* VFP instructions. In a logical order: SP variant first, monad
9561 before dyad, arithmetic then move then load/store. */
9564 do_vfp_sp_monadic (void)
9566 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9567 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9571 do_vfp_sp_dyadic (void)
9573 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9574 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9575 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9579 do_vfp_sp_compare_z (void)
9581 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9585 do_vfp_dp_sp_cvt (void)
9587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9588 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9592 do_vfp_sp_dp_cvt (void)
9594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9595 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9599 do_vfp_reg_from_sp (void)
9601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9602 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9606 do_vfp_reg2_from_sp2 (void)
9608 constraint (inst
.operands
[2].imm
!= 2,
9609 _("only two consecutive VFP SP registers allowed here"));
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9611 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9612 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9616 do_vfp_sp_from_reg (void)
9618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9619 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9623 do_vfp_sp2_from_reg2 (void)
9625 constraint (inst
.operands
[0].imm
!= 2,
9626 _("only two consecutive VFP SP registers allowed here"));
9627 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9628 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9629 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9633 do_vfp_sp_ldst (void)
9635 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9636 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9640 do_vfp_dp_ldst (void)
9642 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9643 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9648 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9650 if (inst
.operands
[0].writeback
)
9651 inst
.instruction
|= WRITE_BACK
;
9653 constraint (ldstm_type
!= VFP_LDSTMIA
,
9654 _("this addressing mode requires base-register writeback"));
9655 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9656 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9657 inst
.instruction
|= inst
.operands
[1].imm
;
9661 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9665 if (inst
.operands
[0].writeback
)
9666 inst
.instruction
|= WRITE_BACK
;
9668 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9669 _("this addressing mode requires base-register writeback"));
9671 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9672 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9674 count
= inst
.operands
[1].imm
<< 1;
9675 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9678 inst
.instruction
|= count
;
9682 do_vfp_sp_ldstmia (void)
9684 vfp_sp_ldstm (VFP_LDSTMIA
);
9688 do_vfp_sp_ldstmdb (void)
9690 vfp_sp_ldstm (VFP_LDSTMDB
);
9694 do_vfp_dp_ldstmia (void)
9696 vfp_dp_ldstm (VFP_LDSTMIA
);
9700 do_vfp_dp_ldstmdb (void)
9702 vfp_dp_ldstm (VFP_LDSTMDB
);
9706 do_vfp_xp_ldstmia (void)
9708 vfp_dp_ldstm (VFP_LDSTMIAX
);
9712 do_vfp_xp_ldstmdb (void)
9714 vfp_dp_ldstm (VFP_LDSTMDBX
);
9718 do_vfp_dp_rd_rm (void)
9720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9721 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9725 do_vfp_dp_rn_rd (void)
9727 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9728 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9732 do_vfp_dp_rd_rn (void)
9734 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9735 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9739 do_vfp_dp_rd_rn_rm (void)
9741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9742 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9743 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9749 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9753 do_vfp_dp_rm_rd_rn (void)
9755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9756 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9757 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9760 /* VFPv3 instructions. */
9762 do_vfp_sp_const (void)
9764 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9765 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9766 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9770 do_vfp_dp_const (void)
9772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9773 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9774 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9778 vfp_conv (int srcsize
)
9780 int immbits
= srcsize
- inst
.operands
[1].imm
;
9782 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9784 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9785 i.e. immbits must be in range 0 - 16. */
9786 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9789 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9791 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9792 i.e. immbits must be in range 0 - 31. */
9793 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9797 inst
.instruction
|= (immbits
& 1) << 5;
9798 inst
.instruction
|= (immbits
>> 1);
9802 do_vfp_sp_conv_16 (void)
9804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9809 do_vfp_dp_conv_16 (void)
9811 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9816 do_vfp_sp_conv_32 (void)
9818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9823 do_vfp_dp_conv_32 (void)
9825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9829 /* FPA instructions. Also in a logical order. */
9834 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9835 inst
.instruction
|= inst
.operands
[1].reg
;
9839 do_fpa_ldmstm (void)
9841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9842 switch (inst
.operands
[1].imm
)
9844 case 1: inst
.instruction
|= CP_T_X
; break;
9845 case 2: inst
.instruction
|= CP_T_Y
; break;
9846 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9851 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9853 /* The instruction specified "ea" or "fd", so we can only accept
9854 [Rn]{!}. The instruction does not really support stacking or
9855 unstacking, so we have to emulate these by setting appropriate
9856 bits and offsets. */
9857 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9858 || inst
.reloc
.exp
.X_add_number
!= 0,
9859 _("this instruction does not support indexing"));
9861 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9862 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9864 if (!(inst
.instruction
& INDEX_UP
))
9865 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9867 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9869 inst
.operands
[2].preind
= 0;
9870 inst
.operands
[2].postind
= 1;
9874 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9877 /* iWMMXt instructions: strictly in alphabetical order. */
9880 do_iwmmxt_tandorc (void)
9882 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9886 do_iwmmxt_textrc (void)
9888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9889 inst
.instruction
|= inst
.operands
[1].imm
;
9893 do_iwmmxt_textrm (void)
9895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9896 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9897 inst
.instruction
|= inst
.operands
[2].imm
;
9901 do_iwmmxt_tinsr (void)
9903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9904 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9905 inst
.instruction
|= inst
.operands
[2].imm
;
9909 do_iwmmxt_tmia (void)
9911 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9912 inst
.instruction
|= inst
.operands
[1].reg
;
9913 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9917 do_iwmmxt_waligni (void)
9919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9920 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9921 inst
.instruction
|= inst
.operands
[2].reg
;
9922 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9926 do_iwmmxt_wmerge (void)
9928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9929 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9930 inst
.instruction
|= inst
.operands
[2].reg
;
9931 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9935 do_iwmmxt_wmov (void)
9937 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9940 inst
.instruction
|= inst
.operands
[1].reg
;
9944 do_iwmmxt_wldstbh (void)
9947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9949 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9951 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9952 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9956 do_iwmmxt_wldstw (void)
9958 /* RIWR_RIWC clears .isreg for a control register. */
9959 if (!inst
.operands
[0].isreg
)
9961 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9962 inst
.instruction
|= 0xf0000000;
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9966 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9970 do_iwmmxt_wldstd (void)
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9973 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9974 && inst
.operands
[1].immisreg
)
9976 inst
.instruction
&= ~0x1a000ff;
9977 inst
.instruction
|= (0xf << 28);
9978 if (inst
.operands
[1].preind
)
9979 inst
.instruction
|= PRE_INDEX
;
9980 if (!inst
.operands
[1].negative
)
9981 inst
.instruction
|= INDEX_UP
;
9982 if (inst
.operands
[1].writeback
)
9983 inst
.instruction
|= WRITE_BACK
;
9984 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9985 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9986 inst
.instruction
|= inst
.operands
[1].imm
;
9989 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9993 do_iwmmxt_wshufh (void)
9995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9996 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9997 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9998 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10002 do_iwmmxt_wzero (void)
10004 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10005 inst
.instruction
|= inst
.operands
[0].reg
;
10006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10011 do_iwmmxt_wrwrwr_or_imm5 (void)
10013 if (inst
.operands
[2].isreg
)
10016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10017 _("immediate operand requires iWMMXt2"));
10019 if (inst
.operands
[2].imm
== 0)
10021 switch ((inst
.instruction
>> 20) & 0xf)
10027 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10028 inst
.operands
[2].imm
= 16;
10029 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10035 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10036 inst
.operands
[2].imm
= 32;
10037 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10044 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10046 wrn
= (inst
.instruction
>> 16) & 0xf;
10047 inst
.instruction
&= 0xff0fff0f;
10048 inst
.instruction
|= wrn
;
10049 /* Bail out here; the instruction is now assembled. */
10054 /* Map 32 -> 0, etc. */
10055 inst
.operands
[2].imm
&= 0x1f;
10056 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10060 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10061 operations first, then control, shift, and load/store. */
10063 /* Insns like "foo X,Y,Z". */
10066 do_mav_triple (void)
10068 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10069 inst
.instruction
|= inst
.operands
[1].reg
;
10070 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10073 /* Insns like "foo W,X,Y,Z".
10074 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10079 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10080 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10081 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10082 inst
.instruction
|= inst
.operands
[3].reg
;
10085 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10087 do_mav_dspsc (void)
10089 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10092 /* Maverick shift immediate instructions.
10093 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10094 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10097 do_mav_shift (void)
10099 int imm
= inst
.operands
[2].imm
;
10101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10102 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10104 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10105 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10106 Bit 4 should be 0. */
10107 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10109 inst
.instruction
|= imm
;
10112 /* XScale instructions. Also sorted arithmetic before move. */
10114 /* Xscale multiply-accumulate (argument parse)
10117 MIAxycc acc0,Rm,Rs. */
10122 inst
.instruction
|= inst
.operands
[1].reg
;
10123 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10126 /* Xscale move-accumulator-register (argument parse)
10128 MARcc acc0,RdLo,RdHi. */
10133 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10134 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10137 /* Xscale move-register-accumulator (argument parse)
10139 MRAcc RdLo,RdHi,acc0. */
10144 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10146 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10149 /* Encoding functions relevant only to Thumb. */
10151 /* inst.operands[i] is a shifted-register operand; encode
10152 it into inst.instruction in the format used by Thumb32. */
10155 encode_thumb32_shifted_operand (int i
)
10157 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10158 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10160 constraint (inst
.operands
[i
].immisreg
,
10161 _("shift by register not allowed in thumb mode"));
10162 inst
.instruction
|= inst
.operands
[i
].reg
;
10163 if (shift
== SHIFT_RRX
)
10164 inst
.instruction
|= SHIFT_ROR
<< 4;
10167 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10168 _("expression too complex"));
10170 constraint (value
> 32
10171 || (value
== 32 && (shift
== SHIFT_LSL
10172 || shift
== SHIFT_ROR
)),
10173 _("shift expression is too large"));
10177 else if (value
== 32)
10180 inst
.instruction
|= shift
<< 4;
10181 inst
.instruction
|= (value
& 0x1c) << 10;
10182 inst
.instruction
|= (value
& 0x03) << 6;
10187 /* inst.operands[i] was set up by parse_address. Encode it into a
10188 Thumb32 format load or store instruction. Reject forms that cannot
10189 be used with such instructions. If is_t is true, reject forms that
10190 cannot be used with a T instruction; if is_d is true, reject forms
10191 that cannot be used with a D instruction. If it is a store insn,
10192 reject PC in Rn. */
10195 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10197 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10199 constraint (!inst
.operands
[i
].isreg
,
10200 _("Instruction does not support =N addresses"));
10202 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10203 if (inst
.operands
[i
].immisreg
)
10205 constraint (is_pc
, BAD_PC_ADDRESSING
);
10206 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10207 constraint (inst
.operands
[i
].negative
,
10208 _("Thumb does not support negative register indexing"));
10209 constraint (inst
.operands
[i
].postind
,
10210 _("Thumb does not support register post-indexing"));
10211 constraint (inst
.operands
[i
].writeback
,
10212 _("Thumb does not support register indexing with writeback"));
10213 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10214 _("Thumb supports only LSL in shifted register indexing"));
10216 inst
.instruction
|= inst
.operands
[i
].imm
;
10217 if (inst
.operands
[i
].shifted
)
10219 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10220 _("expression too complex"));
10221 constraint (inst
.reloc
.exp
.X_add_number
< 0
10222 || inst
.reloc
.exp
.X_add_number
> 3,
10223 _("shift out of range"));
10224 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10226 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10228 else if (inst
.operands
[i
].preind
)
10230 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10231 constraint (is_t
&& inst
.operands
[i
].writeback
,
10232 _("cannot use writeback with this instruction"));
10233 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10234 BAD_PC_ADDRESSING
);
10238 inst
.instruction
|= 0x01000000;
10239 if (inst
.operands
[i
].writeback
)
10240 inst
.instruction
|= 0x00200000;
10244 inst
.instruction
|= 0x00000c00;
10245 if (inst
.operands
[i
].writeback
)
10246 inst
.instruction
|= 0x00000100;
10248 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10250 else if (inst
.operands
[i
].postind
)
10252 gas_assert (inst
.operands
[i
].writeback
);
10253 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10254 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10257 inst
.instruction
|= 0x00200000;
10259 inst
.instruction
|= 0x00000900;
10260 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10262 else /* unindexed - only for coprocessor */
10263 inst
.error
= _("instruction does not accept unindexed addressing");
10266 /* Table of Thumb instructions which exist in both 16- and 32-bit
10267 encodings (the latter only in post-V6T2 cores). The index is the
10268 value used in the insns table below. When there is more than one
10269 possible 16-bit encoding for the instruction, this table always
10271 Also contains several pseudo-instructions used during relaxation. */
10272 #define T16_32_TAB \
10273 X(_adc, 4140, eb400000), \
10274 X(_adcs, 4140, eb500000), \
10275 X(_add, 1c00, eb000000), \
10276 X(_adds, 1c00, eb100000), \
10277 X(_addi, 0000, f1000000), \
10278 X(_addis, 0000, f1100000), \
10279 X(_add_pc,000f, f20f0000), \
10280 X(_add_sp,000d, f10d0000), \
10281 X(_adr, 000f, f20f0000), \
10282 X(_and, 4000, ea000000), \
10283 X(_ands, 4000, ea100000), \
10284 X(_asr, 1000, fa40f000), \
10285 X(_asrs, 1000, fa50f000), \
10286 X(_b, e000, f000b000), \
10287 X(_bcond, d000, f0008000), \
10288 X(_bic, 4380, ea200000), \
10289 X(_bics, 4380, ea300000), \
10290 X(_cmn, 42c0, eb100f00), \
10291 X(_cmp, 2800, ebb00f00), \
10292 X(_cpsie, b660, f3af8400), \
10293 X(_cpsid, b670, f3af8600), \
10294 X(_cpy, 4600, ea4f0000), \
10295 X(_dec_sp,80dd, f1ad0d00), \
10296 X(_eor, 4040, ea800000), \
10297 X(_eors, 4040, ea900000), \
10298 X(_inc_sp,00dd, f10d0d00), \
10299 X(_ldmia, c800, e8900000), \
10300 X(_ldr, 6800, f8500000), \
10301 X(_ldrb, 7800, f8100000), \
10302 X(_ldrh, 8800, f8300000), \
10303 X(_ldrsb, 5600, f9100000), \
10304 X(_ldrsh, 5e00, f9300000), \
10305 X(_ldr_pc,4800, f85f0000), \
10306 X(_ldr_pc2,4800, f85f0000), \
10307 X(_ldr_sp,9800, f85d0000), \
10308 X(_lsl, 0000, fa00f000), \
10309 X(_lsls, 0000, fa10f000), \
10310 X(_lsr, 0800, fa20f000), \
10311 X(_lsrs, 0800, fa30f000), \
10312 X(_mov, 2000, ea4f0000), \
10313 X(_movs, 2000, ea5f0000), \
10314 X(_mul, 4340, fb00f000), \
10315 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10316 X(_mvn, 43c0, ea6f0000), \
10317 X(_mvns, 43c0, ea7f0000), \
10318 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10319 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10320 X(_orr, 4300, ea400000), \
10321 X(_orrs, 4300, ea500000), \
10322 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10323 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10324 X(_rev, ba00, fa90f080), \
10325 X(_rev16, ba40, fa90f090), \
10326 X(_revsh, bac0, fa90f0b0), \
10327 X(_ror, 41c0, fa60f000), \
10328 X(_rors, 41c0, fa70f000), \
10329 X(_sbc, 4180, eb600000), \
10330 X(_sbcs, 4180, eb700000), \
10331 X(_stmia, c000, e8800000), \
10332 X(_str, 6000, f8400000), \
10333 X(_strb, 7000, f8000000), \
10334 X(_strh, 8000, f8200000), \
10335 X(_str_sp,9000, f84d0000), \
10336 X(_sub, 1e00, eba00000), \
10337 X(_subs, 1e00, ebb00000), \
10338 X(_subi, 8000, f1a00000), \
10339 X(_subis, 8000, f1b00000), \
10340 X(_sxtb, b240, fa4ff080), \
10341 X(_sxth, b200, fa0ff080), \
10342 X(_tst, 4200, ea100f00), \
10343 X(_uxtb, b2c0, fa5ff080), \
10344 X(_uxth, b280, fa1ff080), \
10345 X(_nop, bf00, f3af8000), \
10346 X(_yield, bf10, f3af8001), \
10347 X(_wfe, bf20, f3af8002), \
10348 X(_wfi, bf30, f3af8003), \
10349 X(_sev, bf40, f3af8004), \
10350 X(_sevl, bf50, f3af8005), \
10351 X(_udf, de00, f7f0a000)
10353 /* To catch errors in encoding functions, the codes are all offset by
10354 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10355 as 16-bit instructions. */
10356 #define X(a,b,c) T_MNEM##a
10357 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10360 #define X(a,b,c) 0x##b
10361 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10362 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10365 #define X(a,b,c) 0x##c
10366 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10367 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10368 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10372 /* Thumb instruction encoders, in alphabetical order. */
10374 /* ADDW or SUBW. */
10377 do_t_add_sub_w (void)
10381 Rd
= inst
.operands
[0].reg
;
10382 Rn
= inst
.operands
[1].reg
;
10384 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10385 is the SP-{plus,minus}-immediate form of the instruction. */
10387 constraint (Rd
== REG_PC
, BAD_PC
);
10389 reject_bad_reg (Rd
);
10391 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10392 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10395 /* Parse an add or subtract instruction. We get here with inst.instruction
10396 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10399 do_t_add_sub (void)
10403 Rd
= inst
.operands
[0].reg
;
10404 Rs
= (inst
.operands
[1].present
10405 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10406 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10409 set_it_insn_type_last ();
10411 if (unified_syntax
)
10414 bfd_boolean narrow
;
10417 flags
= (inst
.instruction
== T_MNEM_adds
10418 || inst
.instruction
== T_MNEM_subs
);
10420 narrow
= !in_it_block ();
10422 narrow
= in_it_block ();
10423 if (!inst
.operands
[2].isreg
)
10427 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10429 add
= (inst
.instruction
== T_MNEM_add
10430 || inst
.instruction
== T_MNEM_adds
);
10432 if (inst
.size_req
!= 4)
10434 /* Attempt to use a narrow opcode, with relaxation if
10436 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10437 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10438 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10439 opcode
= T_MNEM_add_sp
;
10440 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10441 opcode
= T_MNEM_add_pc
;
10442 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10445 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10447 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10451 inst
.instruction
= THUMB_OP16(opcode
);
10452 inst
.instruction
|= (Rd
<< 4) | Rs
;
10453 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10454 if (inst
.size_req
!= 2)
10455 inst
.relax
= opcode
;
10458 constraint (inst
.size_req
== 2, BAD_HIREG
);
10460 if (inst
.size_req
== 4
10461 || (inst
.size_req
!= 2 && !opcode
))
10465 constraint (add
, BAD_PC
);
10466 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10467 _("only SUBS PC, LR, #const allowed"));
10468 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10469 _("expression too complex"));
10470 constraint (inst
.reloc
.exp
.X_add_number
< 0
10471 || inst
.reloc
.exp
.X_add_number
> 0xff,
10472 _("immediate value out of range"));
10473 inst
.instruction
= T2_SUBS_PC_LR
10474 | inst
.reloc
.exp
.X_add_number
;
10475 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10478 else if (Rs
== REG_PC
)
10480 /* Always use addw/subw. */
10481 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10482 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10486 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10487 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10490 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10492 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10494 inst
.instruction
|= Rd
<< 8;
10495 inst
.instruction
|= Rs
<< 16;
10500 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10501 unsigned int shift
= inst
.operands
[2].shift_kind
;
10503 Rn
= inst
.operands
[2].reg
;
10504 /* See if we can do this with a 16-bit instruction. */
10505 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10507 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10512 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10513 || inst
.instruction
== T_MNEM_add
)
10515 : T_OPCODE_SUB_R3
);
10516 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10520 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10522 /* Thumb-1 cores (except v6-M) require at least one high
10523 register in a narrow non flag setting add. */
10524 if (Rd
> 7 || Rn
> 7
10525 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10526 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10533 inst
.instruction
= T_OPCODE_ADD_HI
;
10534 inst
.instruction
|= (Rd
& 8) << 4;
10535 inst
.instruction
|= (Rd
& 7);
10536 inst
.instruction
|= Rn
<< 3;
10542 constraint (Rd
== REG_PC
, BAD_PC
);
10543 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10544 constraint (Rs
== REG_PC
, BAD_PC
);
10545 reject_bad_reg (Rn
);
10547 /* If we get here, it can't be done in 16 bits. */
10548 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10549 _("shift must be constant"));
10550 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10551 inst
.instruction
|= Rd
<< 8;
10552 inst
.instruction
|= Rs
<< 16;
10553 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10554 _("shift value over 3 not allowed in thumb mode"));
10555 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10556 _("only LSL shift allowed in thumb mode"));
10557 encode_thumb32_shifted_operand (2);
10562 constraint (inst
.instruction
== T_MNEM_adds
10563 || inst
.instruction
== T_MNEM_subs
,
10566 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10568 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10569 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10572 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10573 ? 0x0000 : 0x8000);
10574 inst
.instruction
|= (Rd
<< 4) | Rs
;
10575 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10579 Rn
= inst
.operands
[2].reg
;
10580 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10582 /* We now have Rd, Rs, and Rn set to registers. */
10583 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10585 /* Can't do this for SUB. */
10586 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10587 inst
.instruction
= T_OPCODE_ADD_HI
;
10588 inst
.instruction
|= (Rd
& 8) << 4;
10589 inst
.instruction
|= (Rd
& 7);
10591 inst
.instruction
|= Rn
<< 3;
10593 inst
.instruction
|= Rs
<< 3;
10595 constraint (1, _("dest must overlap one source register"));
10599 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10600 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10601 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10611 Rd
= inst
.operands
[0].reg
;
10612 reject_bad_reg (Rd
);
10614 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10616 /* Defer to section relaxation. */
10617 inst
.relax
= inst
.instruction
;
10618 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10619 inst
.instruction
|= Rd
<< 4;
10621 else if (unified_syntax
&& inst
.size_req
!= 2)
10623 /* Generate a 32-bit opcode. */
10624 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10625 inst
.instruction
|= Rd
<< 8;
10626 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10627 inst
.reloc
.pc_rel
= 1;
10631 /* Generate a 16-bit opcode. */
10632 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10633 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10634 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10635 inst
.reloc
.pc_rel
= 1;
10637 inst
.instruction
|= Rd
<< 4;
10641 /* Arithmetic instructions for which there is just one 16-bit
10642 instruction encoding, and it allows only two low registers.
10643 For maximal compatibility with ARM syntax, we allow three register
10644 operands even when Thumb-32 instructions are not available, as long
10645 as the first two are identical. For instance, both "sbc r0,r1" and
10646 "sbc r0,r0,r1" are allowed. */
10652 Rd
= inst
.operands
[0].reg
;
10653 Rs
= (inst
.operands
[1].present
10654 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10655 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10656 Rn
= inst
.operands
[2].reg
;
10658 reject_bad_reg (Rd
);
10659 reject_bad_reg (Rs
);
10660 if (inst
.operands
[2].isreg
)
10661 reject_bad_reg (Rn
);
10663 if (unified_syntax
)
10665 if (!inst
.operands
[2].isreg
)
10667 /* For an immediate, we always generate a 32-bit opcode;
10668 section relaxation will shrink it later if possible. */
10669 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10670 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10671 inst
.instruction
|= Rd
<< 8;
10672 inst
.instruction
|= Rs
<< 16;
10673 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10677 bfd_boolean narrow
;
10679 /* See if we can do this with a 16-bit instruction. */
10680 if (THUMB_SETS_FLAGS (inst
.instruction
))
10681 narrow
= !in_it_block ();
10683 narrow
= in_it_block ();
10685 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10687 if (inst
.operands
[2].shifted
)
10689 if (inst
.size_req
== 4)
10695 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10696 inst
.instruction
|= Rd
;
10697 inst
.instruction
|= Rn
<< 3;
10701 /* If we get here, it can't be done in 16 bits. */
10702 constraint (inst
.operands
[2].shifted
10703 && inst
.operands
[2].immisreg
,
10704 _("shift must be constant"));
10705 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10706 inst
.instruction
|= Rd
<< 8;
10707 inst
.instruction
|= Rs
<< 16;
10708 encode_thumb32_shifted_operand (2);
10713 /* On its face this is a lie - the instruction does set the
10714 flags. However, the only supported mnemonic in this mode
10715 says it doesn't. */
10716 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10718 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10719 _("unshifted register required"));
10720 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10721 constraint (Rd
!= Rs
,
10722 _("dest and source1 must be the same register"));
10724 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10725 inst
.instruction
|= Rd
;
10726 inst
.instruction
|= Rn
<< 3;
10730 /* Similarly, but for instructions where the arithmetic operation is
10731 commutative, so we can allow either of them to be different from
10732 the destination operand in a 16-bit instruction. For instance, all
10733 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10740 Rd
= inst
.operands
[0].reg
;
10741 Rs
= (inst
.operands
[1].present
10742 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10743 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10744 Rn
= inst
.operands
[2].reg
;
10746 reject_bad_reg (Rd
);
10747 reject_bad_reg (Rs
);
10748 if (inst
.operands
[2].isreg
)
10749 reject_bad_reg (Rn
);
10751 if (unified_syntax
)
10753 if (!inst
.operands
[2].isreg
)
10755 /* For an immediate, we always generate a 32-bit opcode;
10756 section relaxation will shrink it later if possible. */
10757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10758 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10759 inst
.instruction
|= Rd
<< 8;
10760 inst
.instruction
|= Rs
<< 16;
10761 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10765 bfd_boolean narrow
;
10767 /* See if we can do this with a 16-bit instruction. */
10768 if (THUMB_SETS_FLAGS (inst
.instruction
))
10769 narrow
= !in_it_block ();
10771 narrow
= in_it_block ();
10773 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10775 if (inst
.operands
[2].shifted
)
10777 if (inst
.size_req
== 4)
10784 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10785 inst
.instruction
|= Rd
;
10786 inst
.instruction
|= Rn
<< 3;
10791 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10792 inst
.instruction
|= Rd
;
10793 inst
.instruction
|= Rs
<< 3;
10798 /* If we get here, it can't be done in 16 bits. */
10799 constraint (inst
.operands
[2].shifted
10800 && inst
.operands
[2].immisreg
,
10801 _("shift must be constant"));
10802 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10803 inst
.instruction
|= Rd
<< 8;
10804 inst
.instruction
|= Rs
<< 16;
10805 encode_thumb32_shifted_operand (2);
10810 /* On its face this is a lie - the instruction does set the
10811 flags. However, the only supported mnemonic in this mode
10812 says it doesn't. */
10813 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10815 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10816 _("unshifted register required"));
10817 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10819 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10820 inst
.instruction
|= Rd
;
10823 inst
.instruction
|= Rn
<< 3;
10825 inst
.instruction
|= Rs
<< 3;
10827 constraint (1, _("dest must overlap one source register"));
10835 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10836 constraint (msb
> 32, _("bit-field extends past end of register"));
10837 /* The instruction encoding stores the LSB and MSB,
10838 not the LSB and width. */
10839 Rd
= inst
.operands
[0].reg
;
10840 reject_bad_reg (Rd
);
10841 inst
.instruction
|= Rd
<< 8;
10842 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10843 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10844 inst
.instruction
|= msb
- 1;
10853 Rd
= inst
.operands
[0].reg
;
10854 reject_bad_reg (Rd
);
10856 /* #0 in second position is alternative syntax for bfc, which is
10857 the same instruction but with REG_PC in the Rm field. */
10858 if (!inst
.operands
[1].isreg
)
10862 Rn
= inst
.operands
[1].reg
;
10863 reject_bad_reg (Rn
);
10866 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10867 constraint (msb
> 32, _("bit-field extends past end of register"));
10868 /* The instruction encoding stores the LSB and MSB,
10869 not the LSB and width. */
10870 inst
.instruction
|= Rd
<< 8;
10871 inst
.instruction
|= Rn
<< 16;
10872 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10873 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10874 inst
.instruction
|= msb
- 1;
10882 Rd
= inst
.operands
[0].reg
;
10883 Rn
= inst
.operands
[1].reg
;
10885 reject_bad_reg (Rd
);
10886 reject_bad_reg (Rn
);
10888 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10889 _("bit-field extends past end of register"));
10890 inst
.instruction
|= Rd
<< 8;
10891 inst
.instruction
|= Rn
<< 16;
10892 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10893 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10894 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10897 /* ARM V5 Thumb BLX (argument parse)
10898 BLX <target_addr> which is BLX(1)
10899 BLX <Rm> which is BLX(2)
10900 Unfortunately, there are two different opcodes for this mnemonic.
10901 So, the insns[].value is not used, and the code here zaps values
10902 into inst.instruction.
10904 ??? How to take advantage of the additional two bits of displacement
10905 available in Thumb32 mode? Need new relocation? */
10910 set_it_insn_type_last ();
10912 if (inst
.operands
[0].isreg
)
10914 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10915 /* We have a register, so this is BLX(2). */
10916 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10920 /* No register. This must be BLX(1). */
10921 inst
.instruction
= 0xf000e800;
10922 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10934 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10936 if (in_it_block ())
10938 /* Conditional branches inside IT blocks are encoded as unconditional
10940 cond
= COND_ALWAYS
;
10945 if (cond
!= COND_ALWAYS
)
10946 opcode
= T_MNEM_bcond
;
10948 opcode
= inst
.instruction
;
10951 && (inst
.size_req
== 4
10952 || (inst
.size_req
!= 2
10953 && (inst
.operands
[0].hasreloc
10954 || inst
.reloc
.exp
.X_op
== O_constant
))))
10956 inst
.instruction
= THUMB_OP32(opcode
);
10957 if (cond
== COND_ALWAYS
)
10958 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10961 gas_assert (cond
!= 0xF);
10962 inst
.instruction
|= cond
<< 22;
10963 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10968 inst
.instruction
= THUMB_OP16(opcode
);
10969 if (cond
== COND_ALWAYS
)
10970 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10973 inst
.instruction
|= cond
<< 8;
10974 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10976 /* Allow section relaxation. */
10977 if (unified_syntax
&& inst
.size_req
!= 2)
10978 inst
.relax
= opcode
;
10980 inst
.reloc
.type
= reloc
;
10981 inst
.reloc
.pc_rel
= 1;
10984 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10985 between the two is the maximum immediate allowed - which is passed in
10988 do_t_bkpt_hlt1 (int range
)
10990 constraint (inst
.cond
!= COND_ALWAYS
,
10991 _("instruction is always unconditional"));
10992 if (inst
.operands
[0].present
)
10994 constraint (inst
.operands
[0].imm
> range
,
10995 _("immediate value out of range"));
10996 inst
.instruction
|= inst
.operands
[0].imm
;
10999 set_it_insn_type (NEUTRAL_IT_INSN
);
11005 do_t_bkpt_hlt1 (63);
11011 do_t_bkpt_hlt1 (255);
11015 do_t_branch23 (void)
11017 set_it_insn_type_last ();
11018 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11020 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11021 this file. We used to simply ignore the PLT reloc type here --
11022 the branch encoding is now needed to deal with TLSCALL relocs.
11023 So if we see a PLT reloc now, put it back to how it used to be to
11024 keep the preexisting behaviour. */
11025 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11026 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11028 #if defined(OBJ_COFF)
11029 /* If the destination of the branch is a defined symbol which does not have
11030 the THUMB_FUNC attribute, then we must be calling a function which has
11031 the (interfacearm) attribute. We look for the Thumb entry point to that
11032 function and change the branch to refer to that function instead. */
11033 if ( inst
.reloc
.exp
.X_op
== O_symbol
11034 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11035 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11036 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11037 inst
.reloc
.exp
.X_add_symbol
=
11038 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11045 set_it_insn_type_last ();
11046 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11047 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11048 should cause the alignment to be checked once it is known. This is
11049 because BX PC only works if the instruction is word aligned. */
11057 set_it_insn_type_last ();
11058 Rm
= inst
.operands
[0].reg
;
11059 reject_bad_reg (Rm
);
11060 inst
.instruction
|= Rm
<< 16;
11069 Rd
= inst
.operands
[0].reg
;
11070 Rm
= inst
.operands
[1].reg
;
11072 reject_bad_reg (Rd
);
11073 reject_bad_reg (Rm
);
11075 inst
.instruction
|= Rd
<< 8;
11076 inst
.instruction
|= Rm
<< 16;
11077 inst
.instruction
|= Rm
;
11083 set_it_insn_type (OUTSIDE_IT_INSN
);
11084 inst
.instruction
|= inst
.operands
[0].imm
;
11090 set_it_insn_type (OUTSIDE_IT_INSN
);
11092 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11093 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11095 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11096 inst
.instruction
= 0xf3af8000;
11097 inst
.instruction
|= imod
<< 9;
11098 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11099 if (inst
.operands
[1].present
)
11100 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11104 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11105 && (inst
.operands
[0].imm
& 4),
11106 _("selected processor does not support 'A' form "
11107 "of this instruction"));
11108 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11109 _("Thumb does not support the 2-argument "
11110 "form of this instruction"));
11111 inst
.instruction
|= inst
.operands
[0].imm
;
11115 /* THUMB CPY instruction (argument parse). */
11120 if (inst
.size_req
== 4)
11122 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11123 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11124 inst
.instruction
|= inst
.operands
[1].reg
;
11128 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11129 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11130 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11137 set_it_insn_type (OUTSIDE_IT_INSN
);
11138 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11139 inst
.instruction
|= inst
.operands
[0].reg
;
11140 inst
.reloc
.pc_rel
= 1;
11141 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11147 inst
.instruction
|= inst
.operands
[0].imm
;
11153 unsigned Rd
, Rn
, Rm
;
11155 Rd
= inst
.operands
[0].reg
;
11156 Rn
= (inst
.operands
[1].present
11157 ? inst
.operands
[1].reg
: Rd
);
11158 Rm
= inst
.operands
[2].reg
;
11160 reject_bad_reg (Rd
);
11161 reject_bad_reg (Rn
);
11162 reject_bad_reg (Rm
);
11164 inst
.instruction
|= Rd
<< 8;
11165 inst
.instruction
|= Rn
<< 16;
11166 inst
.instruction
|= Rm
;
11172 if (unified_syntax
&& inst
.size_req
== 4)
11173 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11175 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11181 unsigned int cond
= inst
.operands
[0].imm
;
11183 set_it_insn_type (IT_INSN
);
11184 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11186 now_it
.warn_deprecated
= FALSE
;
11188 /* If the condition is a negative condition, invert the mask. */
11189 if ((cond
& 0x1) == 0x0)
11191 unsigned int mask
= inst
.instruction
& 0x000f;
11193 if ((mask
& 0x7) == 0)
11195 /* No conversion needed. */
11196 now_it
.block_length
= 1;
11198 else if ((mask
& 0x3) == 0)
11201 now_it
.block_length
= 2;
11203 else if ((mask
& 0x1) == 0)
11206 now_it
.block_length
= 3;
11211 now_it
.block_length
= 4;
11214 inst
.instruction
&= 0xfff0;
11215 inst
.instruction
|= mask
;
11218 inst
.instruction
|= cond
<< 4;
11221 /* Helper function used for both push/pop and ldm/stm. */
11223 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11227 load
= (inst
.instruction
& (1 << 20)) != 0;
11229 if (mask
& (1 << 13))
11230 inst
.error
= _("SP not allowed in register list");
11232 if ((mask
& (1 << base
)) != 0
11234 inst
.error
= _("having the base register in the register list when "
11235 "using write back is UNPREDICTABLE");
11239 if (mask
& (1 << 15))
11241 if (mask
& (1 << 14))
11242 inst
.error
= _("LR and PC should not both be in register list");
11244 set_it_insn_type_last ();
11249 if (mask
& (1 << 15))
11250 inst
.error
= _("PC not allowed in register list");
11253 if ((mask
& (mask
- 1)) == 0)
11255 /* Single register transfers implemented as str/ldr. */
11258 if (inst
.instruction
& (1 << 23))
11259 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11261 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11265 if (inst
.instruction
& (1 << 23))
11266 inst
.instruction
= 0x00800000; /* ia -> [base] */
11268 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11271 inst
.instruction
|= 0xf8400000;
11273 inst
.instruction
|= 0x00100000;
11275 mask
= ffs (mask
) - 1;
11278 else if (writeback
)
11279 inst
.instruction
|= WRITE_BACK
;
11281 inst
.instruction
|= mask
;
11282 inst
.instruction
|= base
<< 16;
11288 /* This really doesn't seem worth it. */
11289 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11290 _("expression too complex"));
11291 constraint (inst
.operands
[1].writeback
,
11292 _("Thumb load/store multiple does not support {reglist}^"));
11294 if (unified_syntax
)
11296 bfd_boolean narrow
;
11300 /* See if we can use a 16-bit instruction. */
11301 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11302 && inst
.size_req
!= 4
11303 && !(inst
.operands
[1].imm
& ~0xff))
11305 mask
= 1 << inst
.operands
[0].reg
;
11307 if (inst
.operands
[0].reg
<= 7)
11309 if (inst
.instruction
== T_MNEM_stmia
11310 ? inst
.operands
[0].writeback
11311 : (inst
.operands
[0].writeback
11312 == !(inst
.operands
[1].imm
& mask
)))
11314 if (inst
.instruction
== T_MNEM_stmia
11315 && (inst
.operands
[1].imm
& mask
)
11316 && (inst
.operands
[1].imm
& (mask
- 1)))
11317 as_warn (_("value stored for r%d is UNKNOWN"),
11318 inst
.operands
[0].reg
);
11320 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11321 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11322 inst
.instruction
|= inst
.operands
[1].imm
;
11325 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11327 /* This means 1 register in reg list one of 3 situations:
11328 1. Instruction is stmia, but without writeback.
11329 2. lmdia without writeback, but with Rn not in
11331 3. ldmia with writeback, but with Rn in reglist.
11332 Case 3 is UNPREDICTABLE behaviour, so we handle
11333 case 1 and 2 which can be converted into a 16-bit
11334 str or ldr. The SP cases are handled below. */
11335 unsigned long opcode
;
11336 /* First, record an error for Case 3. */
11337 if (inst
.operands
[1].imm
& mask
11338 && inst
.operands
[0].writeback
)
11340 _("having the base register in the register list when "
11341 "using write back is UNPREDICTABLE");
11343 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11345 inst
.instruction
= THUMB_OP16 (opcode
);
11346 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11347 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11351 else if (inst
.operands
[0] .reg
== REG_SP
)
11353 if (inst
.operands
[0].writeback
)
11356 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11357 ? T_MNEM_push
: T_MNEM_pop
);
11358 inst
.instruction
|= inst
.operands
[1].imm
;
11361 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11364 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11365 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11366 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11374 if (inst
.instruction
< 0xffff)
11375 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11377 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11378 inst
.operands
[0].writeback
);
11383 constraint (inst
.operands
[0].reg
> 7
11384 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11385 constraint (inst
.instruction
!= T_MNEM_ldmia
11386 && inst
.instruction
!= T_MNEM_stmia
,
11387 _("Thumb-2 instruction only valid in unified syntax"));
11388 if (inst
.instruction
== T_MNEM_stmia
)
11390 if (!inst
.operands
[0].writeback
)
11391 as_warn (_("this instruction will write back the base register"));
11392 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11393 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11394 as_warn (_("value stored for r%d is UNKNOWN"),
11395 inst
.operands
[0].reg
);
11399 if (!inst
.operands
[0].writeback
11400 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11401 as_warn (_("this instruction will write back the base register"));
11402 else if (inst
.operands
[0].writeback
11403 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11404 as_warn (_("this instruction will not write back the base register"));
11407 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11408 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11409 inst
.instruction
|= inst
.operands
[1].imm
;
11416 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11417 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11418 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11419 || inst
.operands
[1].negative
,
11422 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11424 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11425 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11426 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11432 if (!inst
.operands
[1].present
)
11434 constraint (inst
.operands
[0].reg
== REG_LR
,
11435 _("r14 not allowed as first register "
11436 "when second register is omitted"));
11437 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11439 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11443 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11444 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11450 unsigned long opcode
;
11453 if (inst
.operands
[0].isreg
11454 && !inst
.operands
[0].preind
11455 && inst
.operands
[0].reg
== REG_PC
)
11456 set_it_insn_type_last ();
11458 opcode
= inst
.instruction
;
11459 if (unified_syntax
)
11461 if (!inst
.operands
[1].isreg
)
11463 if (opcode
<= 0xffff)
11464 inst
.instruction
= THUMB_OP32 (opcode
);
11465 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11468 if (inst
.operands
[1].isreg
11469 && !inst
.operands
[1].writeback
11470 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11471 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11472 && opcode
<= 0xffff
11473 && inst
.size_req
!= 4)
11475 /* Insn may have a 16-bit form. */
11476 Rn
= inst
.operands
[1].reg
;
11477 if (inst
.operands
[1].immisreg
)
11479 inst
.instruction
= THUMB_OP16 (opcode
);
11481 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11483 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11484 reject_bad_reg (inst
.operands
[1].imm
);
11486 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11487 && opcode
!= T_MNEM_ldrsb
)
11488 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11489 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11496 if (inst
.reloc
.pc_rel
)
11497 opcode
= T_MNEM_ldr_pc2
;
11499 opcode
= T_MNEM_ldr_pc
;
11503 if (opcode
== T_MNEM_ldr
)
11504 opcode
= T_MNEM_ldr_sp
;
11506 opcode
= T_MNEM_str_sp
;
11508 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11512 inst
.instruction
= inst
.operands
[0].reg
;
11513 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11515 inst
.instruction
|= THUMB_OP16 (opcode
);
11516 if (inst
.size_req
== 2)
11517 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11519 inst
.relax
= opcode
;
11523 /* Definitely a 32-bit variant. */
11525 /* Warning for Erratum 752419. */
11526 if (opcode
== T_MNEM_ldr
11527 && inst
.operands
[0].reg
== REG_SP
11528 && inst
.operands
[1].writeback
== 1
11529 && !inst
.operands
[1].immisreg
)
11531 if (no_cpu_selected ()
11532 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11533 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11534 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11535 as_warn (_("This instruction may be unpredictable "
11536 "if executed on M-profile cores "
11537 "with interrupts enabled."));
11540 /* Do some validations regarding addressing modes. */
11541 if (inst
.operands
[1].immisreg
)
11542 reject_bad_reg (inst
.operands
[1].imm
);
11544 constraint (inst
.operands
[1].writeback
== 1
11545 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11548 inst
.instruction
= THUMB_OP32 (opcode
);
11549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11550 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11551 check_ldr_r15_aligned ();
11555 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11557 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11559 /* Only [Rn,Rm] is acceptable. */
11560 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11561 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11562 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11563 || inst
.operands
[1].negative
,
11564 _("Thumb does not support this addressing mode"));
11565 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11569 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11570 if (!inst
.operands
[1].isreg
)
11571 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11574 constraint (!inst
.operands
[1].preind
11575 || inst
.operands
[1].shifted
11576 || inst
.operands
[1].writeback
,
11577 _("Thumb does not support this addressing mode"));
11578 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11580 constraint (inst
.instruction
& 0x0600,
11581 _("byte or halfword not valid for base register"));
11582 constraint (inst
.operands
[1].reg
== REG_PC
11583 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11584 _("r15 based store not allowed"));
11585 constraint (inst
.operands
[1].immisreg
,
11586 _("invalid base register for register offset"));
11588 if (inst
.operands
[1].reg
== REG_PC
)
11589 inst
.instruction
= T_OPCODE_LDR_PC
;
11590 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11591 inst
.instruction
= T_OPCODE_LDR_SP
;
11593 inst
.instruction
= T_OPCODE_STR_SP
;
11595 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11596 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11600 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11601 if (!inst
.operands
[1].immisreg
)
11603 /* Immediate offset. */
11604 inst
.instruction
|= inst
.operands
[0].reg
;
11605 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11606 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11610 /* Register offset. */
11611 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11612 constraint (inst
.operands
[1].negative
,
11613 _("Thumb does not support this addressing mode"));
11616 switch (inst
.instruction
)
11618 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11619 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11620 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11621 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11622 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11623 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11624 case 0x5600 /* ldrsb */:
11625 case 0x5e00 /* ldrsh */: break;
11629 inst
.instruction
|= inst
.operands
[0].reg
;
11630 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11631 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11637 if (!inst
.operands
[1].present
)
11639 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11640 constraint (inst
.operands
[0].reg
== REG_LR
,
11641 _("r14 not allowed here"));
11642 constraint (inst
.operands
[0].reg
== REG_R12
,
11643 _("r12 not allowed here"));
11646 if (inst
.operands
[2].writeback
11647 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11648 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11649 as_warn (_("base register written back, and overlaps "
11650 "one of transfer registers"));
11652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11653 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11654 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11660 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11661 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11667 unsigned Rd
, Rn
, Rm
, Ra
;
11669 Rd
= inst
.operands
[0].reg
;
11670 Rn
= inst
.operands
[1].reg
;
11671 Rm
= inst
.operands
[2].reg
;
11672 Ra
= inst
.operands
[3].reg
;
11674 reject_bad_reg (Rd
);
11675 reject_bad_reg (Rn
);
11676 reject_bad_reg (Rm
);
11677 reject_bad_reg (Ra
);
11679 inst
.instruction
|= Rd
<< 8;
11680 inst
.instruction
|= Rn
<< 16;
11681 inst
.instruction
|= Rm
;
11682 inst
.instruction
|= Ra
<< 12;
11688 unsigned RdLo
, RdHi
, Rn
, Rm
;
11690 RdLo
= inst
.operands
[0].reg
;
11691 RdHi
= inst
.operands
[1].reg
;
11692 Rn
= inst
.operands
[2].reg
;
11693 Rm
= inst
.operands
[3].reg
;
11695 reject_bad_reg (RdLo
);
11696 reject_bad_reg (RdHi
);
11697 reject_bad_reg (Rn
);
11698 reject_bad_reg (Rm
);
11700 inst
.instruction
|= RdLo
<< 12;
11701 inst
.instruction
|= RdHi
<< 8;
11702 inst
.instruction
|= Rn
<< 16;
11703 inst
.instruction
|= Rm
;
11707 do_t_mov_cmp (void)
11711 Rn
= inst
.operands
[0].reg
;
11712 Rm
= inst
.operands
[1].reg
;
11715 set_it_insn_type_last ();
11717 if (unified_syntax
)
11719 int r0off
= (inst
.instruction
== T_MNEM_mov
11720 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11721 unsigned long opcode
;
11722 bfd_boolean narrow
;
11723 bfd_boolean low_regs
;
11725 low_regs
= (Rn
<= 7 && Rm
<= 7);
11726 opcode
= inst
.instruction
;
11727 if (in_it_block ())
11728 narrow
= opcode
!= T_MNEM_movs
;
11730 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11731 if (inst
.size_req
== 4
11732 || inst
.operands
[1].shifted
)
11735 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11736 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11737 && !inst
.operands
[1].shifted
11741 inst
.instruction
= T2_SUBS_PC_LR
;
11745 if (opcode
== T_MNEM_cmp
)
11747 constraint (Rn
== REG_PC
, BAD_PC
);
11750 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11752 warn_deprecated_sp (Rm
);
11753 /* R15 was documented as a valid choice for Rm in ARMv6,
11754 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11755 tools reject R15, so we do too. */
11756 constraint (Rm
== REG_PC
, BAD_PC
);
11759 reject_bad_reg (Rm
);
11761 else if (opcode
== T_MNEM_mov
11762 || opcode
== T_MNEM_movs
)
11764 if (inst
.operands
[1].isreg
)
11766 if (opcode
== T_MNEM_movs
)
11768 reject_bad_reg (Rn
);
11769 reject_bad_reg (Rm
);
11773 /* This is mov.n. */
11774 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11775 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11777 as_tsktsk (_("Use of r%u as a source register is "
11778 "deprecated when r%u is the destination "
11779 "register."), Rm
, Rn
);
11784 /* This is mov.w. */
11785 constraint (Rn
== REG_PC
, BAD_PC
);
11786 constraint (Rm
== REG_PC
, BAD_PC
);
11787 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11791 reject_bad_reg (Rn
);
11794 if (!inst
.operands
[1].isreg
)
11796 /* Immediate operand. */
11797 if (!in_it_block () && opcode
== T_MNEM_mov
)
11799 if (low_regs
&& narrow
)
11801 inst
.instruction
= THUMB_OP16 (opcode
);
11802 inst
.instruction
|= Rn
<< 8;
11803 if (inst
.size_req
== 2)
11804 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11806 inst
.relax
= opcode
;
11810 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11811 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11812 inst
.instruction
|= Rn
<< r0off
;
11813 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11816 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11817 && (inst
.instruction
== T_MNEM_mov
11818 || inst
.instruction
== T_MNEM_movs
))
11820 /* Register shifts are encoded as separate shift instructions. */
11821 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11823 if (in_it_block ())
11828 if (inst
.size_req
== 4)
11831 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11837 switch (inst
.operands
[1].shift_kind
)
11840 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11843 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11846 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11849 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11855 inst
.instruction
= opcode
;
11858 inst
.instruction
|= Rn
;
11859 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11864 inst
.instruction
|= CONDS_BIT
;
11866 inst
.instruction
|= Rn
<< 8;
11867 inst
.instruction
|= Rm
<< 16;
11868 inst
.instruction
|= inst
.operands
[1].imm
;
11873 /* Some mov with immediate shift have narrow variants.
11874 Register shifts are handled above. */
11875 if (low_regs
&& inst
.operands
[1].shifted
11876 && (inst
.instruction
== T_MNEM_mov
11877 || inst
.instruction
== T_MNEM_movs
))
11879 if (in_it_block ())
11880 narrow
= (inst
.instruction
== T_MNEM_mov
);
11882 narrow
= (inst
.instruction
== T_MNEM_movs
);
11887 switch (inst
.operands
[1].shift_kind
)
11889 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11890 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11891 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11892 default: narrow
= FALSE
; break;
11898 inst
.instruction
|= Rn
;
11899 inst
.instruction
|= Rm
<< 3;
11900 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11904 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11905 inst
.instruction
|= Rn
<< r0off
;
11906 encode_thumb32_shifted_operand (1);
11910 switch (inst
.instruction
)
11913 /* In v4t or v5t a move of two lowregs produces unpredictable
11914 results. Don't allow this. */
11917 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11918 "MOV Rd, Rs with two low registers is not "
11919 "permitted on this architecture");
11920 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11924 inst
.instruction
= T_OPCODE_MOV_HR
;
11925 inst
.instruction
|= (Rn
& 0x8) << 4;
11926 inst
.instruction
|= (Rn
& 0x7);
11927 inst
.instruction
|= Rm
<< 3;
11931 /* We know we have low registers at this point.
11932 Generate LSLS Rd, Rs, #0. */
11933 inst
.instruction
= T_OPCODE_LSL_I
;
11934 inst
.instruction
|= Rn
;
11935 inst
.instruction
|= Rm
<< 3;
11941 inst
.instruction
= T_OPCODE_CMP_LR
;
11942 inst
.instruction
|= Rn
;
11943 inst
.instruction
|= Rm
<< 3;
11947 inst
.instruction
= T_OPCODE_CMP_HR
;
11948 inst
.instruction
|= (Rn
& 0x8) << 4;
11949 inst
.instruction
|= (Rn
& 0x7);
11950 inst
.instruction
|= Rm
<< 3;
11957 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11959 /* PR 10443: Do not silently ignore shifted operands. */
11960 constraint (inst
.operands
[1].shifted
,
11961 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11963 if (inst
.operands
[1].isreg
)
11965 if (Rn
< 8 && Rm
< 8)
11967 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11968 since a MOV instruction produces unpredictable results. */
11969 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11970 inst
.instruction
= T_OPCODE_ADD_I3
;
11972 inst
.instruction
= T_OPCODE_CMP_LR
;
11974 inst
.instruction
|= Rn
;
11975 inst
.instruction
|= Rm
<< 3;
11979 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11980 inst
.instruction
= T_OPCODE_MOV_HR
;
11982 inst
.instruction
= T_OPCODE_CMP_HR
;
11988 constraint (Rn
> 7,
11989 _("only lo regs allowed with immediate"));
11990 inst
.instruction
|= Rn
<< 8;
11991 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12002 top
= (inst
.instruction
& 0x00800000) != 0;
12003 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12005 constraint (top
, _(":lower16: not allowed this instruction"));
12006 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12008 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12010 constraint (!top
, _(":upper16: not allowed this instruction"));
12011 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12014 Rd
= inst
.operands
[0].reg
;
12015 reject_bad_reg (Rd
);
12017 inst
.instruction
|= Rd
<< 8;
12018 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12020 imm
= inst
.reloc
.exp
.X_add_number
;
12021 inst
.instruction
|= (imm
& 0xf000) << 4;
12022 inst
.instruction
|= (imm
& 0x0800) << 15;
12023 inst
.instruction
|= (imm
& 0x0700) << 4;
12024 inst
.instruction
|= (imm
& 0x00ff);
12029 do_t_mvn_tst (void)
12033 Rn
= inst
.operands
[0].reg
;
12034 Rm
= inst
.operands
[1].reg
;
12036 if (inst
.instruction
== T_MNEM_cmp
12037 || inst
.instruction
== T_MNEM_cmn
)
12038 constraint (Rn
== REG_PC
, BAD_PC
);
12040 reject_bad_reg (Rn
);
12041 reject_bad_reg (Rm
);
12043 if (unified_syntax
)
12045 int r0off
= (inst
.instruction
== T_MNEM_mvn
12046 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12047 bfd_boolean narrow
;
12049 if (inst
.size_req
== 4
12050 || inst
.instruction
> 0xffff
12051 || inst
.operands
[1].shifted
12052 || Rn
> 7 || Rm
> 7)
12054 else if (inst
.instruction
== T_MNEM_cmn
12055 || inst
.instruction
== T_MNEM_tst
)
12057 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12058 narrow
= !in_it_block ();
12060 narrow
= in_it_block ();
12062 if (!inst
.operands
[1].isreg
)
12064 /* For an immediate, we always generate a 32-bit opcode;
12065 section relaxation will shrink it later if possible. */
12066 if (inst
.instruction
< 0xffff)
12067 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12068 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12069 inst
.instruction
|= Rn
<< r0off
;
12070 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12074 /* See if we can do this with a 16-bit instruction. */
12077 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12078 inst
.instruction
|= Rn
;
12079 inst
.instruction
|= Rm
<< 3;
12083 constraint (inst
.operands
[1].shifted
12084 && inst
.operands
[1].immisreg
,
12085 _("shift must be constant"));
12086 if (inst
.instruction
< 0xffff)
12087 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12088 inst
.instruction
|= Rn
<< r0off
;
12089 encode_thumb32_shifted_operand (1);
12095 constraint (inst
.instruction
> 0xffff
12096 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12097 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12098 _("unshifted register required"));
12099 constraint (Rn
> 7 || Rm
> 7,
12102 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12103 inst
.instruction
|= Rn
;
12104 inst
.instruction
|= Rm
<< 3;
12113 if (do_vfp_nsyn_mrs () == SUCCESS
)
12116 Rd
= inst
.operands
[0].reg
;
12117 reject_bad_reg (Rd
);
12118 inst
.instruction
|= Rd
<< 8;
12120 if (inst
.operands
[1].isreg
)
12122 unsigned br
= inst
.operands
[1].reg
;
12123 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12124 as_bad (_("bad register for mrs"));
12126 inst
.instruction
|= br
& (0xf << 16);
12127 inst
.instruction
|= (br
& 0x300) >> 4;
12128 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12132 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12134 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12136 /* PR gas/12698: The constraint is only applied for m_profile.
12137 If the user has specified -march=all, we want to ignore it as
12138 we are building for any CPU type, including non-m variants. */
12139 bfd_boolean m_profile
=
12140 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12141 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12142 "not support requested special purpose register"));
12145 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12147 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12148 _("'APSR', 'CPSR' or 'SPSR' expected"));
12150 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12151 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12152 inst
.instruction
|= 0xf0000;
12162 if (do_vfp_nsyn_msr () == SUCCESS
)
12165 constraint (!inst
.operands
[1].isreg
,
12166 _("Thumb encoding does not support an immediate here"));
12168 if (inst
.operands
[0].isreg
)
12169 flags
= (int)(inst
.operands
[0].reg
);
12171 flags
= inst
.operands
[0].imm
;
12173 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12175 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12177 /* PR gas/12698: The constraint is only applied for m_profile.
12178 If the user has specified -march=all, we want to ignore it as
12179 we are building for any CPU type, including non-m variants. */
12180 bfd_boolean m_profile
=
12181 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12182 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12183 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12184 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12185 && bits
!= PSR_f
)) && m_profile
,
12186 _("selected processor does not support requested special "
12187 "purpose register"));
12190 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12191 "requested special purpose register"));
12193 Rn
= inst
.operands
[1].reg
;
12194 reject_bad_reg (Rn
);
12196 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12197 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12198 inst
.instruction
|= (flags
& 0x300) >> 4;
12199 inst
.instruction
|= (flags
& 0xff);
12200 inst
.instruction
|= Rn
<< 16;
12206 bfd_boolean narrow
;
12207 unsigned Rd
, Rn
, Rm
;
12209 if (!inst
.operands
[2].present
)
12210 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12212 Rd
= inst
.operands
[0].reg
;
12213 Rn
= inst
.operands
[1].reg
;
12214 Rm
= inst
.operands
[2].reg
;
12216 if (unified_syntax
)
12218 if (inst
.size_req
== 4
12224 else if (inst
.instruction
== T_MNEM_muls
)
12225 narrow
= !in_it_block ();
12227 narrow
= in_it_block ();
12231 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12232 constraint (Rn
> 7 || Rm
> 7,
12239 /* 16-bit MULS/Conditional MUL. */
12240 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12241 inst
.instruction
|= Rd
;
12244 inst
.instruction
|= Rm
<< 3;
12246 inst
.instruction
|= Rn
<< 3;
12248 constraint (1, _("dest must overlap one source register"));
12252 constraint (inst
.instruction
!= T_MNEM_mul
,
12253 _("Thumb-2 MUL must not set flags"));
12255 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12256 inst
.instruction
|= Rd
<< 8;
12257 inst
.instruction
|= Rn
<< 16;
12258 inst
.instruction
|= Rm
<< 0;
12260 reject_bad_reg (Rd
);
12261 reject_bad_reg (Rn
);
12262 reject_bad_reg (Rm
);
12269 unsigned RdLo
, RdHi
, Rn
, Rm
;
12271 RdLo
= inst
.operands
[0].reg
;
12272 RdHi
= inst
.operands
[1].reg
;
12273 Rn
= inst
.operands
[2].reg
;
12274 Rm
= inst
.operands
[3].reg
;
12276 reject_bad_reg (RdLo
);
12277 reject_bad_reg (RdHi
);
12278 reject_bad_reg (Rn
);
12279 reject_bad_reg (Rm
);
12281 inst
.instruction
|= RdLo
<< 12;
12282 inst
.instruction
|= RdHi
<< 8;
12283 inst
.instruction
|= Rn
<< 16;
12284 inst
.instruction
|= Rm
;
12287 as_tsktsk (_("rdhi and rdlo must be different"));
12293 set_it_insn_type (NEUTRAL_IT_INSN
);
12295 if (unified_syntax
)
12297 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12299 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12300 inst
.instruction
|= inst
.operands
[0].imm
;
12304 /* PR9722: Check for Thumb2 availability before
12305 generating a thumb2 nop instruction. */
12306 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12308 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12309 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12312 inst
.instruction
= 0x46c0;
12317 constraint (inst
.operands
[0].present
,
12318 _("Thumb does not support NOP with hints"));
12319 inst
.instruction
= 0x46c0;
12326 if (unified_syntax
)
12328 bfd_boolean narrow
;
12330 if (THUMB_SETS_FLAGS (inst
.instruction
))
12331 narrow
= !in_it_block ();
12333 narrow
= in_it_block ();
12334 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12336 if (inst
.size_req
== 4)
12341 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12342 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12343 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12347 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12348 inst
.instruction
|= inst
.operands
[0].reg
;
12349 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12354 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12356 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12358 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12359 inst
.instruction
|= inst
.operands
[0].reg
;
12360 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12369 Rd
= inst
.operands
[0].reg
;
12370 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12372 reject_bad_reg (Rd
);
12373 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12374 reject_bad_reg (Rn
);
12376 inst
.instruction
|= Rd
<< 8;
12377 inst
.instruction
|= Rn
<< 16;
12379 if (!inst
.operands
[2].isreg
)
12381 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12382 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12388 Rm
= inst
.operands
[2].reg
;
12389 reject_bad_reg (Rm
);
12391 constraint (inst
.operands
[2].shifted
12392 && inst
.operands
[2].immisreg
,
12393 _("shift must be constant"));
12394 encode_thumb32_shifted_operand (2);
12401 unsigned Rd
, Rn
, Rm
;
12403 Rd
= inst
.operands
[0].reg
;
12404 Rn
= inst
.operands
[1].reg
;
12405 Rm
= inst
.operands
[2].reg
;
12407 reject_bad_reg (Rd
);
12408 reject_bad_reg (Rn
);
12409 reject_bad_reg (Rm
);
12411 inst
.instruction
|= Rd
<< 8;
12412 inst
.instruction
|= Rn
<< 16;
12413 inst
.instruction
|= Rm
;
12414 if (inst
.operands
[3].present
)
12416 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12417 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12418 _("expression too complex"));
12419 inst
.instruction
|= (val
& 0x1c) << 10;
12420 inst
.instruction
|= (val
& 0x03) << 6;
12427 if (!inst
.operands
[3].present
)
12431 inst
.instruction
&= ~0x00000020;
12433 /* PR 10168. Swap the Rm and Rn registers. */
12434 Rtmp
= inst
.operands
[1].reg
;
12435 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12436 inst
.operands
[2].reg
= Rtmp
;
12444 if (inst
.operands
[0].immisreg
)
12445 reject_bad_reg (inst
.operands
[0].imm
);
12447 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12451 do_t_push_pop (void)
12455 constraint (inst
.operands
[0].writeback
,
12456 _("push/pop do not support {reglist}^"));
12457 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12458 _("expression too complex"));
12460 mask
= inst
.operands
[0].imm
;
12461 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12462 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12463 else if (inst
.size_req
!= 4
12464 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12465 ? REG_LR
: REG_PC
)))
12467 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12468 inst
.instruction
|= THUMB_PP_PC_LR
;
12469 inst
.instruction
|= mask
& 0xff;
12471 else if (unified_syntax
)
12473 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12474 encode_thumb2_ldmstm (13, mask
, TRUE
);
12478 inst
.error
= _("invalid register list to push/pop instruction");
12488 Rd
= inst
.operands
[0].reg
;
12489 Rm
= inst
.operands
[1].reg
;
12491 reject_bad_reg (Rd
);
12492 reject_bad_reg (Rm
);
12494 inst
.instruction
|= Rd
<< 8;
12495 inst
.instruction
|= Rm
<< 16;
12496 inst
.instruction
|= Rm
;
12504 Rd
= inst
.operands
[0].reg
;
12505 Rm
= inst
.operands
[1].reg
;
12507 reject_bad_reg (Rd
);
12508 reject_bad_reg (Rm
);
12510 if (Rd
<= 7 && Rm
<= 7
12511 && inst
.size_req
!= 4)
12513 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12514 inst
.instruction
|= Rd
;
12515 inst
.instruction
|= Rm
<< 3;
12517 else if (unified_syntax
)
12519 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12520 inst
.instruction
|= Rd
<< 8;
12521 inst
.instruction
|= Rm
<< 16;
12522 inst
.instruction
|= Rm
;
12525 inst
.error
= BAD_HIREG
;
12533 Rd
= inst
.operands
[0].reg
;
12534 Rm
= inst
.operands
[1].reg
;
12536 reject_bad_reg (Rd
);
12537 reject_bad_reg (Rm
);
12539 inst
.instruction
|= Rd
<< 8;
12540 inst
.instruction
|= Rm
;
12548 Rd
= inst
.operands
[0].reg
;
12549 Rs
= (inst
.operands
[1].present
12550 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12551 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12553 reject_bad_reg (Rd
);
12554 reject_bad_reg (Rs
);
12555 if (inst
.operands
[2].isreg
)
12556 reject_bad_reg (inst
.operands
[2].reg
);
12558 inst
.instruction
|= Rd
<< 8;
12559 inst
.instruction
|= Rs
<< 16;
12560 if (!inst
.operands
[2].isreg
)
12562 bfd_boolean narrow
;
12564 if ((inst
.instruction
& 0x00100000) != 0)
12565 narrow
= !in_it_block ();
12567 narrow
= in_it_block ();
12569 if (Rd
> 7 || Rs
> 7)
12572 if (inst
.size_req
== 4 || !unified_syntax
)
12575 if (inst
.reloc
.exp
.X_op
!= O_constant
12576 || inst
.reloc
.exp
.X_add_number
!= 0)
12579 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12580 relaxation, but it doesn't seem worth the hassle. */
12583 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12584 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12585 inst
.instruction
|= Rs
<< 3;
12586 inst
.instruction
|= Rd
;
12590 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12591 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12595 encode_thumb32_shifted_operand (2);
12601 if (warn_on_deprecated
12602 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12603 as_tsktsk (_("setend use is deprecated for ARMv8"));
12605 set_it_insn_type (OUTSIDE_IT_INSN
);
12606 if (inst
.operands
[0].imm
)
12607 inst
.instruction
|= 0x8;
12613 if (!inst
.operands
[1].present
)
12614 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12616 if (unified_syntax
)
12618 bfd_boolean narrow
;
12621 switch (inst
.instruction
)
12624 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12626 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12628 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12630 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12634 if (THUMB_SETS_FLAGS (inst
.instruction
))
12635 narrow
= !in_it_block ();
12637 narrow
= in_it_block ();
12638 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12640 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12642 if (inst
.operands
[2].isreg
12643 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12644 || inst
.operands
[2].reg
> 7))
12646 if (inst
.size_req
== 4)
12649 reject_bad_reg (inst
.operands
[0].reg
);
12650 reject_bad_reg (inst
.operands
[1].reg
);
12654 if (inst
.operands
[2].isreg
)
12656 reject_bad_reg (inst
.operands
[2].reg
);
12657 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12658 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12659 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12660 inst
.instruction
|= inst
.operands
[2].reg
;
12662 /* PR 12854: Error on extraneous shifts. */
12663 constraint (inst
.operands
[2].shifted
,
12664 _("extraneous shift as part of operand to shift insn"));
12668 inst
.operands
[1].shifted
= 1;
12669 inst
.operands
[1].shift_kind
= shift_kind
;
12670 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12671 ? T_MNEM_movs
: T_MNEM_mov
);
12672 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12673 encode_thumb32_shifted_operand (1);
12674 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12675 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12680 if (inst
.operands
[2].isreg
)
12682 switch (shift_kind
)
12684 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12685 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12686 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12687 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12691 inst
.instruction
|= inst
.operands
[0].reg
;
12692 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12694 /* PR 12854: Error on extraneous shifts. */
12695 constraint (inst
.operands
[2].shifted
,
12696 _("extraneous shift as part of operand to shift insn"));
12700 switch (shift_kind
)
12702 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12703 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12704 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12707 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12708 inst
.instruction
|= inst
.operands
[0].reg
;
12709 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12715 constraint (inst
.operands
[0].reg
> 7
12716 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12717 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12719 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12721 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12722 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12723 _("source1 and dest must be same register"));
12725 switch (inst
.instruction
)
12727 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12728 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12729 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12730 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12734 inst
.instruction
|= inst
.operands
[0].reg
;
12735 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12737 /* PR 12854: Error on extraneous shifts. */
12738 constraint (inst
.operands
[2].shifted
,
12739 _("extraneous shift as part of operand to shift insn"));
12743 switch (inst
.instruction
)
12745 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12746 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12747 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12748 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12751 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12752 inst
.instruction
|= inst
.operands
[0].reg
;
12753 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12761 unsigned Rd
, Rn
, Rm
;
12763 Rd
= inst
.operands
[0].reg
;
12764 Rn
= inst
.operands
[1].reg
;
12765 Rm
= inst
.operands
[2].reg
;
12767 reject_bad_reg (Rd
);
12768 reject_bad_reg (Rn
);
12769 reject_bad_reg (Rm
);
12771 inst
.instruction
|= Rd
<< 8;
12772 inst
.instruction
|= Rn
<< 16;
12773 inst
.instruction
|= Rm
;
12779 unsigned Rd
, Rn
, Rm
;
12781 Rd
= inst
.operands
[0].reg
;
12782 Rm
= inst
.operands
[1].reg
;
12783 Rn
= inst
.operands
[2].reg
;
12785 reject_bad_reg (Rd
);
12786 reject_bad_reg (Rn
);
12787 reject_bad_reg (Rm
);
12789 inst
.instruction
|= Rd
<< 8;
12790 inst
.instruction
|= Rn
<< 16;
12791 inst
.instruction
|= Rm
;
12797 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12799 _("SMC is not permitted on this architecture"));
12800 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12801 _("expression too complex"));
12802 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12803 inst
.instruction
|= (value
& 0xf000) >> 12;
12804 inst
.instruction
|= (value
& 0x0ff0);
12805 inst
.instruction
|= (value
& 0x000f) << 16;
12806 /* PR gas/15623: SMC instructions must be last in an IT block. */
12807 set_it_insn_type_last ();
12813 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12815 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12816 inst
.instruction
|= (value
& 0x0fff);
12817 inst
.instruction
|= (value
& 0xf000) << 4;
12821 do_t_ssat_usat (int bias
)
12825 Rd
= inst
.operands
[0].reg
;
12826 Rn
= inst
.operands
[2].reg
;
12828 reject_bad_reg (Rd
);
12829 reject_bad_reg (Rn
);
12831 inst
.instruction
|= Rd
<< 8;
12832 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12833 inst
.instruction
|= Rn
<< 16;
12835 if (inst
.operands
[3].present
)
12837 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12839 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12841 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12842 _("expression too complex"));
12844 if (shift_amount
!= 0)
12846 constraint (shift_amount
> 31,
12847 _("shift expression is too large"));
12849 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12850 inst
.instruction
|= 0x00200000; /* sh bit. */
12852 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12853 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12861 do_t_ssat_usat (1);
12869 Rd
= inst
.operands
[0].reg
;
12870 Rn
= inst
.operands
[2].reg
;
12872 reject_bad_reg (Rd
);
12873 reject_bad_reg (Rn
);
12875 inst
.instruction
|= Rd
<< 8;
12876 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12877 inst
.instruction
|= Rn
<< 16;
12883 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12884 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12885 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12886 || inst
.operands
[2].negative
,
12889 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12891 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12892 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12893 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12894 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12900 if (!inst
.operands
[2].present
)
12901 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12903 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12904 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12905 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12908 inst
.instruction
|= inst
.operands
[0].reg
;
12909 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12910 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12911 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12917 unsigned Rd
, Rn
, Rm
;
12919 Rd
= inst
.operands
[0].reg
;
12920 Rn
= inst
.operands
[1].reg
;
12921 Rm
= inst
.operands
[2].reg
;
12923 reject_bad_reg (Rd
);
12924 reject_bad_reg (Rn
);
12925 reject_bad_reg (Rm
);
12927 inst
.instruction
|= Rd
<< 8;
12928 inst
.instruction
|= Rn
<< 16;
12929 inst
.instruction
|= Rm
;
12930 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12938 Rd
= inst
.operands
[0].reg
;
12939 Rm
= inst
.operands
[1].reg
;
12941 reject_bad_reg (Rd
);
12942 reject_bad_reg (Rm
);
12944 if (inst
.instruction
<= 0xffff
12945 && inst
.size_req
!= 4
12946 && Rd
<= 7 && Rm
<= 7
12947 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12949 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12950 inst
.instruction
|= Rd
;
12951 inst
.instruction
|= Rm
<< 3;
12953 else if (unified_syntax
)
12955 if (inst
.instruction
<= 0xffff)
12956 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12957 inst
.instruction
|= Rd
<< 8;
12958 inst
.instruction
|= Rm
;
12959 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12963 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12964 _("Thumb encoding does not support rotation"));
12965 constraint (1, BAD_HIREG
);
12972 /* We have to do the following check manually as ARM_EXT_OS only applies
12974 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12976 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12977 /* This only applies to the v6m howver, not later architectures. */
12978 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12979 as_bad (_("SVC is not permitted on this architecture"));
12980 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12983 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12992 half
= (inst
.instruction
& 0x10) != 0;
12993 set_it_insn_type_last ();
12994 constraint (inst
.operands
[0].immisreg
,
12995 _("instruction requires register index"));
12997 Rn
= inst
.operands
[0].reg
;
12998 Rm
= inst
.operands
[0].imm
;
13000 constraint (Rn
== REG_SP
, BAD_SP
);
13001 reject_bad_reg (Rm
);
13003 constraint (!half
&& inst
.operands
[0].shifted
,
13004 _("instruction does not allow shifted index"));
13005 inst
.instruction
|= (Rn
<< 16) | Rm
;
13011 if (!inst
.operands
[0].present
)
13012 inst
.operands
[0].imm
= 0;
13014 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13016 constraint (inst
.size_req
== 2,
13017 _("immediate value out of range"));
13018 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13019 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13020 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13024 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13025 inst
.instruction
|= inst
.operands
[0].imm
;
13028 set_it_insn_type (NEUTRAL_IT_INSN
);
13035 do_t_ssat_usat (0);
13043 Rd
= inst
.operands
[0].reg
;
13044 Rn
= inst
.operands
[2].reg
;
13046 reject_bad_reg (Rd
);
13047 reject_bad_reg (Rn
);
13049 inst
.instruction
|= Rd
<< 8;
13050 inst
.instruction
|= inst
.operands
[1].imm
;
13051 inst
.instruction
|= Rn
<< 16;
13054 /* Neon instruction encoder helpers. */
13056 /* Encodings for the different types for various Neon opcodes. */
13058 /* An "invalid" code for the following tables. */
13061 struct neon_tab_entry
13064 unsigned float_or_poly
;
13065 unsigned scalar_or_imm
;
13068 /* Map overloaded Neon opcodes to their respective encodings. */
13069 #define NEON_ENC_TAB \
13070 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13071 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13072 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13073 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13074 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13075 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13076 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13077 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13078 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13079 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13080 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13081 /* Register variants of the following two instructions are encoded as
13082 vcge / vcgt with the operands reversed. */ \
13083 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13084 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13085 X(vfma, N_INV, 0x0000c10, N_INV), \
13086 X(vfms, N_INV, 0x0200c10, N_INV), \
13087 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13088 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13089 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13090 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13091 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13092 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13093 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13094 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13095 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13096 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13097 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13098 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13099 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13100 X(vshl, 0x0000400, N_INV, 0x0800510), \
13101 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13102 X(vand, 0x0000110, N_INV, 0x0800030), \
13103 X(vbic, 0x0100110, N_INV, 0x0800030), \
13104 X(veor, 0x1000110, N_INV, N_INV), \
13105 X(vorn, 0x0300110, N_INV, 0x0800010), \
13106 X(vorr, 0x0200110, N_INV, 0x0800010), \
13107 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13108 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13109 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13110 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13111 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13112 X(vst1, 0x0000000, 0x0800000, N_INV), \
13113 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13114 X(vst2, 0x0000100, 0x0800100, N_INV), \
13115 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13116 X(vst3, 0x0000200, 0x0800200, N_INV), \
13117 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13118 X(vst4, 0x0000300, 0x0800300, N_INV), \
13119 X(vmovn, 0x1b20200, N_INV, N_INV), \
13120 X(vtrn, 0x1b20080, N_INV, N_INV), \
13121 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13122 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13123 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13124 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13125 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13126 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13127 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13128 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13129 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13130 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13131 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13132 X(vseleq, 0xe000a00, N_INV, N_INV), \
13133 X(vselvs, 0xe100a00, N_INV, N_INV), \
13134 X(vselge, 0xe200a00, N_INV, N_INV), \
13135 X(vselgt, 0xe300a00, N_INV, N_INV), \
13136 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13137 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13138 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13139 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13140 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13141 X(aes, 0x3b00300, N_INV, N_INV), \
13142 X(sha3op, 0x2000c00, N_INV, N_INV), \
13143 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13144 X(sha2op, 0x3ba0380, N_INV, N_INV)
13148 #define X(OPC,I,F,S) N_MNEM_##OPC
13153 static const struct neon_tab_entry neon_enc_tab
[] =
13155 #define X(OPC,I,F,S) { (I), (F), (S) }
13160 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13161 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13162 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13163 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13164 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13165 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13166 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13167 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13168 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13169 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13170 #define NEON_ENC_SINGLE_(X) \
13171 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13172 #define NEON_ENC_DOUBLE_(X) \
13173 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13174 #define NEON_ENC_FPV8_(X) \
13175 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13177 #define NEON_ENCODE(type, inst) \
13180 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13181 inst.is_neon = 1; \
13185 #define check_neon_suffixes \
13188 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13190 as_bad (_("invalid neon suffix for non neon instruction")); \
13196 /* Define shapes for instruction operands. The following mnemonic characters
13197 are used in this table:
13199 F - VFP S<n> register
13200 D - Neon D<n> register
13201 Q - Neon Q<n> register
13205 L - D<n> register list
13207 This table is used to generate various data:
13208 - enumerations of the form NS_DDR to be used as arguments to
13210 - a table classifying shapes into single, double, quad, mixed.
13211 - a table used to drive neon_select_shape. */
13213 #define NEON_SHAPE_DEF \
13214 X(3, (D, D, D), DOUBLE), \
13215 X(3, (Q, Q, Q), QUAD), \
13216 X(3, (D, D, I), DOUBLE), \
13217 X(3, (Q, Q, I), QUAD), \
13218 X(3, (D, D, S), DOUBLE), \
13219 X(3, (Q, Q, S), QUAD), \
13220 X(2, (D, D), DOUBLE), \
13221 X(2, (Q, Q), QUAD), \
13222 X(2, (D, S), DOUBLE), \
13223 X(2, (Q, S), QUAD), \
13224 X(2, (D, R), DOUBLE), \
13225 X(2, (Q, R), QUAD), \
13226 X(2, (D, I), DOUBLE), \
13227 X(2, (Q, I), QUAD), \
13228 X(3, (D, L, D), DOUBLE), \
13229 X(2, (D, Q), MIXED), \
13230 X(2, (Q, D), MIXED), \
13231 X(3, (D, Q, I), MIXED), \
13232 X(3, (Q, D, I), MIXED), \
13233 X(3, (Q, D, D), MIXED), \
13234 X(3, (D, Q, Q), MIXED), \
13235 X(3, (Q, Q, D), MIXED), \
13236 X(3, (Q, D, S), MIXED), \
13237 X(3, (D, Q, S), MIXED), \
13238 X(4, (D, D, D, I), DOUBLE), \
13239 X(4, (Q, Q, Q, I), QUAD), \
13240 X(2, (F, F), SINGLE), \
13241 X(3, (F, F, F), SINGLE), \
13242 X(2, (F, I), SINGLE), \
13243 X(2, (F, D), MIXED), \
13244 X(2, (D, F), MIXED), \
13245 X(3, (F, F, I), MIXED), \
13246 X(4, (R, R, F, F), SINGLE), \
13247 X(4, (F, F, R, R), SINGLE), \
13248 X(3, (D, R, R), DOUBLE), \
13249 X(3, (R, R, D), DOUBLE), \
13250 X(2, (S, R), SINGLE), \
13251 X(2, (R, S), SINGLE), \
13252 X(2, (F, R), SINGLE), \
13253 X(2, (R, F), SINGLE)
13255 #define S2(A,B) NS_##A##B
13256 #define S3(A,B,C) NS_##A##B##C
13257 #define S4(A,B,C,D) NS_##A##B##C##D
13259 #define X(N, L, C) S##N L
13272 enum neon_shape_class
13280 #define X(N, L, C) SC_##C
13282 static enum neon_shape_class neon_shape_class
[] =
13300 /* Register widths of above. */
13301 static unsigned neon_shape_el_size
[] =
13312 struct neon_shape_info
13315 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13318 #define S2(A,B) { SE_##A, SE_##B }
13319 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13320 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13322 #define X(N, L, C) { N, S##N L }
13324 static struct neon_shape_info neon_shape_tab
[] =
13334 /* Bit masks used in type checking given instructions.
13335 'N_EQK' means the type must be the same as (or based on in some way) the key
13336 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13337 set, various other bits can be set as well in order to modify the meaning of
13338 the type constraint. */
13340 enum neon_type_mask
13364 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13365 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13366 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13367 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13368 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13369 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13370 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13371 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13372 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13373 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13374 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13376 N_MAX_NONSPECIAL
= N_P64
13379 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13381 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13382 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13383 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13384 #define N_SUF_32 (N_SU_32 | N_F32)
13385 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13386 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13388 /* Pass this as the first type argument to neon_check_type to ignore types
13390 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13392 /* Select a "shape" for the current instruction (describing register types or
13393 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13394 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13395 function of operand parsing, so this function doesn't need to be called.
13396 Shapes should be listed in order of decreasing length. */
13398 static enum neon_shape
13399 neon_select_shape (enum neon_shape shape
, ...)
13402 enum neon_shape first_shape
= shape
;
13404 /* Fix missing optional operands. FIXME: we don't know at this point how
13405 many arguments we should have, so this makes the assumption that we have
13406 > 1. This is true of all current Neon opcodes, I think, but may not be
13407 true in the future. */
13408 if (!inst
.operands
[1].present
)
13409 inst
.operands
[1] = inst
.operands
[0];
13411 va_start (ap
, shape
);
13413 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13418 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13420 if (!inst
.operands
[j
].present
)
13426 switch (neon_shape_tab
[shape
].el
[j
])
13429 if (!(inst
.operands
[j
].isreg
13430 && inst
.operands
[j
].isvec
13431 && inst
.operands
[j
].issingle
13432 && !inst
.operands
[j
].isquad
))
13437 if (!(inst
.operands
[j
].isreg
13438 && inst
.operands
[j
].isvec
13439 && !inst
.operands
[j
].isquad
13440 && !inst
.operands
[j
].issingle
))
13445 if (!(inst
.operands
[j
].isreg
13446 && !inst
.operands
[j
].isvec
))
13451 if (!(inst
.operands
[j
].isreg
13452 && inst
.operands
[j
].isvec
13453 && inst
.operands
[j
].isquad
13454 && !inst
.operands
[j
].issingle
))
13459 if (!(!inst
.operands
[j
].isreg
13460 && !inst
.operands
[j
].isscalar
))
13465 if (!(!inst
.operands
[j
].isreg
13466 && inst
.operands
[j
].isscalar
))
13476 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13477 /* We've matched all the entries in the shape table, and we don't
13478 have any left over operands which have not been matched. */
13484 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13485 first_error (_("invalid instruction shape"));
13490 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13491 means the Q bit should be set). */
13494 neon_quad (enum neon_shape shape
)
13496 return neon_shape_class
[shape
] == SC_QUAD
;
13500 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13503 /* Allow modification to be made to types which are constrained to be
13504 based on the key element, based on bits set alongside N_EQK. */
13505 if ((typebits
& N_EQK
) != 0)
13507 if ((typebits
& N_HLF
) != 0)
13509 else if ((typebits
& N_DBL
) != 0)
13511 if ((typebits
& N_SGN
) != 0)
13512 *g_type
= NT_signed
;
13513 else if ((typebits
& N_UNS
) != 0)
13514 *g_type
= NT_unsigned
;
13515 else if ((typebits
& N_INT
) != 0)
13516 *g_type
= NT_integer
;
13517 else if ((typebits
& N_FLT
) != 0)
13518 *g_type
= NT_float
;
13519 else if ((typebits
& N_SIZ
) != 0)
13520 *g_type
= NT_untyped
;
13524 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13525 operand type, i.e. the single type specified in a Neon instruction when it
13526 is the only one given. */
13528 static struct neon_type_el
13529 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13531 struct neon_type_el dest
= *key
;
13533 gas_assert ((thisarg
& N_EQK
) != 0);
13535 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13540 /* Convert Neon type and size into compact bitmask representation. */
13542 static enum neon_type_mask
13543 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13550 case 8: return N_8
;
13551 case 16: return N_16
;
13552 case 32: return N_32
;
13553 case 64: return N_64
;
13561 case 8: return N_I8
;
13562 case 16: return N_I16
;
13563 case 32: return N_I32
;
13564 case 64: return N_I64
;
13572 case 16: return N_F16
;
13573 case 32: return N_F32
;
13574 case 64: return N_F64
;
13582 case 8: return N_P8
;
13583 case 16: return N_P16
;
13584 case 64: return N_P64
;
13592 case 8: return N_S8
;
13593 case 16: return N_S16
;
13594 case 32: return N_S32
;
13595 case 64: return N_S64
;
13603 case 8: return N_U8
;
13604 case 16: return N_U16
;
13605 case 32: return N_U32
;
13606 case 64: return N_U64
;
13617 /* Convert compact Neon bitmask type representation to a type and size. Only
13618 handles the case where a single bit is set in the mask. */
13621 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13622 enum neon_type_mask mask
)
13624 if ((mask
& N_EQK
) != 0)
13627 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13629 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13631 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13633 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13638 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13640 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13641 *type
= NT_unsigned
;
13642 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13643 *type
= NT_integer
;
13644 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13645 *type
= NT_untyped
;
13646 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13648 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13656 /* Modify a bitmask of allowed types. This is only needed for type
13660 modify_types_allowed (unsigned allowed
, unsigned mods
)
13663 enum neon_el_type type
;
13669 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13671 if (el_type_of_type_chk (&type
, &size
,
13672 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13674 neon_modify_type_size (mods
, &type
, &size
);
13675 destmask
|= type_chk_of_el_type (type
, size
);
13682 /* Check type and return type classification.
13683 The manual states (paraphrase): If one datatype is given, it indicates the
13685 - the second operand, if there is one
13686 - the operand, if there is no second operand
13687 - the result, if there are no operands.
13688 This isn't quite good enough though, so we use a concept of a "key" datatype
13689 which is set on a per-instruction basis, which is the one which matters when
13690 only one data type is written.
13691 Note: this function has side-effects (e.g. filling in missing operands). All
13692 Neon instructions should call it before performing bit encoding. */
13694 static struct neon_type_el
13695 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13698 unsigned i
, pass
, key_el
= 0;
13699 unsigned types
[NEON_MAX_TYPE_ELS
];
13700 enum neon_el_type k_type
= NT_invtype
;
13701 unsigned k_size
= -1u;
13702 struct neon_type_el badtype
= {NT_invtype
, -1};
13703 unsigned key_allowed
= 0;
13705 /* Optional registers in Neon instructions are always (not) in operand 1.
13706 Fill in the missing operand here, if it was omitted. */
13707 if (els
> 1 && !inst
.operands
[1].present
)
13708 inst
.operands
[1] = inst
.operands
[0];
13710 /* Suck up all the varargs. */
13712 for (i
= 0; i
< els
; i
++)
13714 unsigned thisarg
= va_arg (ap
, unsigned);
13715 if (thisarg
== N_IGNORE_TYPE
)
13720 types
[i
] = thisarg
;
13721 if ((thisarg
& N_KEY
) != 0)
13726 if (inst
.vectype
.elems
> 0)
13727 for (i
= 0; i
< els
; i
++)
13728 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13730 first_error (_("types specified in both the mnemonic and operands"));
13734 /* Duplicate inst.vectype elements here as necessary.
13735 FIXME: No idea if this is exactly the same as the ARM assembler,
13736 particularly when an insn takes one register and one non-register
13738 if (inst
.vectype
.elems
== 1 && els
> 1)
13741 inst
.vectype
.elems
= els
;
13742 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13743 for (j
= 0; j
< els
; j
++)
13745 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13748 else if (inst
.vectype
.elems
== 0 && els
> 0)
13751 /* No types were given after the mnemonic, so look for types specified
13752 after each operand. We allow some flexibility here; as long as the
13753 "key" operand has a type, we can infer the others. */
13754 for (j
= 0; j
< els
; j
++)
13755 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13756 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13758 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13760 for (j
= 0; j
< els
; j
++)
13761 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13762 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13767 first_error (_("operand types can't be inferred"));
13771 else if (inst
.vectype
.elems
!= els
)
13773 first_error (_("type specifier has the wrong number of parts"));
13777 for (pass
= 0; pass
< 2; pass
++)
13779 for (i
= 0; i
< els
; i
++)
13781 unsigned thisarg
= types
[i
];
13782 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13783 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13784 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13785 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13787 /* Decay more-specific signed & unsigned types to sign-insensitive
13788 integer types if sign-specific variants are unavailable. */
13789 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13790 && (types_allowed
& N_SU_ALL
) == 0)
13791 g_type
= NT_integer
;
13793 /* If only untyped args are allowed, decay any more specific types to
13794 them. Some instructions only care about signs for some element
13795 sizes, so handle that properly. */
13796 if (((types_allowed
& N_UNT
) == 0)
13797 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13798 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13799 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13800 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13801 g_type
= NT_untyped
;
13805 if ((thisarg
& N_KEY
) != 0)
13809 key_allowed
= thisarg
& ~N_KEY
;
13814 if ((thisarg
& N_VFP
) != 0)
13816 enum neon_shape_el regshape
;
13817 unsigned regwidth
, match
;
13819 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13822 first_error (_("invalid instruction shape"));
13825 regshape
= neon_shape_tab
[ns
].el
[i
];
13826 regwidth
= neon_shape_el_size
[regshape
];
13828 /* In VFP mode, operands must match register widths. If we
13829 have a key operand, use its width, else use the width of
13830 the current operand. */
13836 if (regwidth
!= match
)
13838 first_error (_("operand size must match register width"));
13843 if ((thisarg
& N_EQK
) == 0)
13845 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13847 if ((given_type
& types_allowed
) == 0)
13849 first_error (_("bad type in Neon instruction"));
13855 enum neon_el_type mod_k_type
= k_type
;
13856 unsigned mod_k_size
= k_size
;
13857 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13858 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13860 first_error (_("inconsistent types in Neon instruction"));
13868 return inst
.vectype
.el
[key_el
];
13871 /* Neon-style VFP instruction forwarding. */
13873 /* Thumb VFP instructions have 0xE in the condition field. */
13876 do_vfp_cond_or_thumb (void)
13881 inst
.instruction
|= 0xe0000000;
13883 inst
.instruction
|= inst
.cond
<< 28;
13886 /* Look up and encode a simple mnemonic, for use as a helper function for the
13887 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13888 etc. It is assumed that operand parsing has already been done, and that the
13889 operands are in the form expected by the given opcode (this isn't necessarily
13890 the same as the form in which they were parsed, hence some massaging must
13891 take place before this function is called).
13892 Checks current arch version against that in the looked-up opcode. */
13895 do_vfp_nsyn_opcode (const char *opname
)
13897 const struct asm_opcode
*opcode
;
13899 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13904 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13905 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13912 inst
.instruction
= opcode
->tvalue
;
13913 opcode
->tencode ();
13917 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13918 opcode
->aencode ();
13923 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13925 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13930 do_vfp_nsyn_opcode ("fadds");
13932 do_vfp_nsyn_opcode ("fsubs");
13937 do_vfp_nsyn_opcode ("faddd");
13939 do_vfp_nsyn_opcode ("fsubd");
13943 /* Check operand types to see if this is a VFP instruction, and if so call
13947 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13949 enum neon_shape rs
;
13950 struct neon_type_el et
;
13955 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13956 et
= neon_check_type (2, rs
,
13957 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13961 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13962 et
= neon_check_type (3, rs
,
13963 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13970 if (et
.type
!= NT_invtype
)
13981 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13983 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13988 do_vfp_nsyn_opcode ("fmacs");
13990 do_vfp_nsyn_opcode ("fnmacs");
13995 do_vfp_nsyn_opcode ("fmacd");
13997 do_vfp_nsyn_opcode ("fnmacd");
14002 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14004 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14009 do_vfp_nsyn_opcode ("ffmas");
14011 do_vfp_nsyn_opcode ("ffnmas");
14016 do_vfp_nsyn_opcode ("ffmad");
14018 do_vfp_nsyn_opcode ("ffnmad");
14023 do_vfp_nsyn_mul (enum neon_shape rs
)
14026 do_vfp_nsyn_opcode ("fmuls");
14028 do_vfp_nsyn_opcode ("fmuld");
14032 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14034 int is_neg
= (inst
.instruction
& 0x80) != 0;
14035 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
14040 do_vfp_nsyn_opcode ("fnegs");
14042 do_vfp_nsyn_opcode ("fabss");
14047 do_vfp_nsyn_opcode ("fnegd");
14049 do_vfp_nsyn_opcode ("fabsd");
14053 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14054 insns belong to Neon, and are handled elsewhere. */
14057 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14059 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14063 do_vfp_nsyn_opcode ("fldmdbs");
14065 do_vfp_nsyn_opcode ("fldmias");
14070 do_vfp_nsyn_opcode ("fstmdbs");
14072 do_vfp_nsyn_opcode ("fstmias");
14077 do_vfp_nsyn_sqrt (void)
14079 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14080 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14083 do_vfp_nsyn_opcode ("fsqrts");
14085 do_vfp_nsyn_opcode ("fsqrtd");
14089 do_vfp_nsyn_div (void)
14091 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14092 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14093 N_F32
| N_F64
| N_KEY
| N_VFP
);
14096 do_vfp_nsyn_opcode ("fdivs");
14098 do_vfp_nsyn_opcode ("fdivd");
14102 do_vfp_nsyn_nmul (void)
14104 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14105 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14106 N_F32
| N_F64
| N_KEY
| N_VFP
);
14110 NEON_ENCODE (SINGLE
, inst
);
14111 do_vfp_sp_dyadic ();
14115 NEON_ENCODE (DOUBLE
, inst
);
14116 do_vfp_dp_rd_rn_rm ();
14118 do_vfp_cond_or_thumb ();
14122 do_vfp_nsyn_cmp (void)
14124 if (inst
.operands
[1].isreg
)
14126 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14127 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14131 NEON_ENCODE (SINGLE
, inst
);
14132 do_vfp_sp_monadic ();
14136 NEON_ENCODE (DOUBLE
, inst
);
14137 do_vfp_dp_rd_rm ();
14142 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14143 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14145 switch (inst
.instruction
& 0x0fffffff)
14148 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14151 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14159 NEON_ENCODE (SINGLE
, inst
);
14160 do_vfp_sp_compare_z ();
14164 NEON_ENCODE (DOUBLE
, inst
);
14168 do_vfp_cond_or_thumb ();
14172 nsyn_insert_sp (void)
14174 inst
.operands
[1] = inst
.operands
[0];
14175 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14176 inst
.operands
[0].reg
= REG_SP
;
14177 inst
.operands
[0].isreg
= 1;
14178 inst
.operands
[0].writeback
= 1;
14179 inst
.operands
[0].present
= 1;
14183 do_vfp_nsyn_push (void)
14186 if (inst
.operands
[1].issingle
)
14187 do_vfp_nsyn_opcode ("fstmdbs");
14189 do_vfp_nsyn_opcode ("fstmdbd");
14193 do_vfp_nsyn_pop (void)
14196 if (inst
.operands
[1].issingle
)
14197 do_vfp_nsyn_opcode ("fldmias");
14199 do_vfp_nsyn_opcode ("fldmiad");
14202 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14203 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14206 neon_dp_fixup (struct arm_it
* insn
)
14208 unsigned int i
= insn
->instruction
;
14213 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14224 insn
->instruction
= i
;
14227 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14231 neon_logbits (unsigned x
)
14233 return ffs (x
) - 4;
14236 #define LOW4(R) ((R) & 0xf)
14237 #define HI1(R) (((R) >> 4) & 1)
14239 /* Encode insns with bit pattern:
14241 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14242 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14244 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14245 different meaning for some instruction. */
14248 neon_three_same (int isquad
, int ubit
, int size
)
14250 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14251 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14252 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14253 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14254 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14255 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14256 inst
.instruction
|= (isquad
!= 0) << 6;
14257 inst
.instruction
|= (ubit
!= 0) << 24;
14259 inst
.instruction
|= neon_logbits (size
) << 20;
14261 neon_dp_fixup (&inst
);
14264 /* Encode instructions of the form:
14266 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14267 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14269 Don't write size if SIZE == -1. */
14272 neon_two_same (int qbit
, int ubit
, int size
)
14274 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14275 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14276 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14277 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14278 inst
.instruction
|= (qbit
!= 0) << 6;
14279 inst
.instruction
|= (ubit
!= 0) << 24;
14282 inst
.instruction
|= neon_logbits (size
) << 18;
14284 neon_dp_fixup (&inst
);
14287 /* Neon instruction encoders, in approximate order of appearance. */
14290 do_neon_dyadic_i_su (void)
14292 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14293 struct neon_type_el et
= neon_check_type (3, rs
,
14294 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14295 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14299 do_neon_dyadic_i64_su (void)
14301 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14302 struct neon_type_el et
= neon_check_type (3, rs
,
14303 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14304 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14308 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14311 unsigned size
= et
.size
>> 3;
14312 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14313 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14314 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14315 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14316 inst
.instruction
|= (isquad
!= 0) << 6;
14317 inst
.instruction
|= immbits
<< 16;
14318 inst
.instruction
|= (size
>> 3) << 7;
14319 inst
.instruction
|= (size
& 0x7) << 19;
14321 inst
.instruction
|= (uval
!= 0) << 24;
14323 neon_dp_fixup (&inst
);
14327 do_neon_shl_imm (void)
14329 if (!inst
.operands
[2].isreg
)
14331 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14332 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14333 int imm
= inst
.operands
[2].imm
;
14335 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14336 _("immediate out of range for shift"));
14337 NEON_ENCODE (IMMED
, inst
);
14338 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14342 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14343 struct neon_type_el et
= neon_check_type (3, rs
,
14344 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14347 /* VSHL/VQSHL 3-register variants have syntax such as:
14349 whereas other 3-register operations encoded by neon_three_same have
14352 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14354 tmp
= inst
.operands
[2].reg
;
14355 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14356 inst
.operands
[1].reg
= tmp
;
14357 NEON_ENCODE (INTEGER
, inst
);
14358 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14363 do_neon_qshl_imm (void)
14365 if (!inst
.operands
[2].isreg
)
14367 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14368 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14369 int imm
= inst
.operands
[2].imm
;
14371 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14372 _("immediate out of range for shift"));
14373 NEON_ENCODE (IMMED
, inst
);
14374 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14378 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14379 struct neon_type_el et
= neon_check_type (3, rs
,
14380 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14383 /* See note in do_neon_shl_imm. */
14384 tmp
= inst
.operands
[2].reg
;
14385 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14386 inst
.operands
[1].reg
= tmp
;
14387 NEON_ENCODE (INTEGER
, inst
);
14388 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14393 do_neon_rshl (void)
14395 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14396 struct neon_type_el et
= neon_check_type (3, rs
,
14397 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14400 tmp
= inst
.operands
[2].reg
;
14401 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14402 inst
.operands
[1].reg
= tmp
;
14403 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14407 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14409 /* Handle .I8 pseudo-instructions. */
14412 /* Unfortunately, this will make everything apart from zero out-of-range.
14413 FIXME is this the intended semantics? There doesn't seem much point in
14414 accepting .I8 if so. */
14415 immediate
|= immediate
<< 8;
14421 if (immediate
== (immediate
& 0x000000ff))
14423 *immbits
= immediate
;
14426 else if (immediate
== (immediate
& 0x0000ff00))
14428 *immbits
= immediate
>> 8;
14431 else if (immediate
== (immediate
& 0x00ff0000))
14433 *immbits
= immediate
>> 16;
14436 else if (immediate
== (immediate
& 0xff000000))
14438 *immbits
= immediate
>> 24;
14441 if ((immediate
& 0xffff) != (immediate
>> 16))
14442 goto bad_immediate
;
14443 immediate
&= 0xffff;
14446 if (immediate
== (immediate
& 0x000000ff))
14448 *immbits
= immediate
;
14451 else if (immediate
== (immediate
& 0x0000ff00))
14453 *immbits
= immediate
>> 8;
14458 first_error (_("immediate value out of range"));
14463 do_neon_logic (void)
14465 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14467 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14468 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14469 /* U bit and size field were set as part of the bitmask. */
14470 NEON_ENCODE (INTEGER
, inst
);
14471 neon_three_same (neon_quad (rs
), 0, -1);
14475 const int three_ops_form
= (inst
.operands
[2].present
14476 && !inst
.operands
[2].isreg
);
14477 const int immoperand
= (three_ops_form
? 2 : 1);
14478 enum neon_shape rs
= (three_ops_form
14479 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14480 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14481 struct neon_type_el et
= neon_check_type (2, rs
,
14482 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14483 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14487 if (et
.type
== NT_invtype
)
14490 if (three_ops_form
)
14491 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14492 _("first and second operands shall be the same register"));
14494 NEON_ENCODE (IMMED
, inst
);
14496 immbits
= inst
.operands
[immoperand
].imm
;
14499 /* .i64 is a pseudo-op, so the immediate must be a repeating
14501 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14502 inst
.operands
[immoperand
].reg
: 0))
14504 /* Set immbits to an invalid constant. */
14505 immbits
= 0xdeadbeef;
14512 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14516 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14520 /* Pseudo-instruction for VBIC. */
14521 neon_invert_size (&immbits
, 0, et
.size
);
14522 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14526 /* Pseudo-instruction for VORR. */
14527 neon_invert_size (&immbits
, 0, et
.size
);
14528 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14538 inst
.instruction
|= neon_quad (rs
) << 6;
14539 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14540 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14541 inst
.instruction
|= cmode
<< 8;
14542 neon_write_immbits (immbits
);
14544 neon_dp_fixup (&inst
);
14549 do_neon_bitfield (void)
14551 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14552 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14553 neon_three_same (neon_quad (rs
), 0, -1);
14557 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14560 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14561 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14563 if (et
.type
== NT_float
)
14565 NEON_ENCODE (FLOAT
, inst
);
14566 neon_three_same (neon_quad (rs
), 0, -1);
14570 NEON_ENCODE (INTEGER
, inst
);
14571 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14576 do_neon_dyadic_if_su (void)
14578 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14582 do_neon_dyadic_if_su_d (void)
14584 /* This version only allow D registers, but that constraint is enforced during
14585 operand parsing so we don't need to do anything extra here. */
14586 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14590 do_neon_dyadic_if_i_d (void)
14592 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14593 affected if we specify unsigned args. */
14594 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14597 enum vfp_or_neon_is_neon_bits
14600 NEON_CHECK_ARCH
= 2,
14601 NEON_CHECK_ARCH8
= 4
14604 /* Call this function if an instruction which may have belonged to the VFP or
14605 Neon instruction sets, but turned out to be a Neon instruction (due to the
14606 operand types involved, etc.). We have to check and/or fix-up a couple of
14609 - Make sure the user hasn't attempted to make a Neon instruction
14611 - Alter the value in the condition code field if necessary.
14612 - Make sure that the arch supports Neon instructions.
14614 Which of these operations take place depends on bits from enum
14615 vfp_or_neon_is_neon_bits.
14617 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14618 current instruction's condition is COND_ALWAYS, the condition field is
14619 changed to inst.uncond_value. This is necessary because instructions shared
14620 between VFP and Neon may be conditional for the VFP variants only, and the
14621 unconditional Neon version must have, e.g., 0xF in the condition field. */
14624 vfp_or_neon_is_neon (unsigned check
)
14626 /* Conditions are always legal in Thumb mode (IT blocks). */
14627 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14629 if (inst
.cond
!= COND_ALWAYS
)
14631 first_error (_(BAD_COND
));
14634 if (inst
.uncond_value
!= -1)
14635 inst
.instruction
|= inst
.uncond_value
<< 28;
14638 if ((check
& NEON_CHECK_ARCH
)
14639 && !mark_feature_used (&fpu_neon_ext_v1
))
14641 first_error (_(BAD_FPU
));
14645 if ((check
& NEON_CHECK_ARCH8
)
14646 && !mark_feature_used (&fpu_neon_ext_armv8
))
14648 first_error (_(BAD_FPU
));
14656 do_neon_addsub_if_i (void)
14658 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14661 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14664 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14665 affected if we specify unsigned args. */
14666 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14669 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14671 V<op> A,B (A is operand 0, B is operand 2)
14676 so handle that case specially. */
14679 neon_exchange_operands (void)
14681 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14682 if (inst
.operands
[1].present
)
14684 /* Swap operands[1] and operands[2]. */
14685 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14686 inst
.operands
[1] = inst
.operands
[2];
14687 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14691 inst
.operands
[1] = inst
.operands
[2];
14692 inst
.operands
[2] = inst
.operands
[0];
14697 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14699 if (inst
.operands
[2].isreg
)
14702 neon_exchange_operands ();
14703 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14707 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14708 struct neon_type_el et
= neon_check_type (2, rs
,
14709 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14711 NEON_ENCODE (IMMED
, inst
);
14712 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14713 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14716 inst
.instruction
|= neon_quad (rs
) << 6;
14717 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14718 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14720 neon_dp_fixup (&inst
);
14727 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14731 do_neon_cmp_inv (void)
14733 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14739 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14742 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14743 scalars, which are encoded in 5 bits, M : Rm.
14744 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14745 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14749 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14751 unsigned regno
= NEON_SCALAR_REG (scalar
);
14752 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14757 if (regno
> 7 || elno
> 3)
14759 return regno
| (elno
<< 3);
14762 if (regno
> 15 || elno
> 1)
14764 return regno
| (elno
<< 4);
14768 first_error (_("scalar out of range for multiply instruction"));
14774 /* Encode multiply / multiply-accumulate scalar instructions. */
14777 neon_mul_mac (struct neon_type_el et
, int ubit
)
14781 /* Give a more helpful error message if we have an invalid type. */
14782 if (et
.type
== NT_invtype
)
14785 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14786 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14787 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14790 inst
.instruction
|= LOW4 (scalar
);
14791 inst
.instruction
|= HI1 (scalar
) << 5;
14792 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14793 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14794 inst
.instruction
|= (ubit
!= 0) << 24;
14796 neon_dp_fixup (&inst
);
14800 do_neon_mac_maybe_scalar (void)
14802 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14805 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14808 if (inst
.operands
[2].isscalar
)
14810 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14811 struct neon_type_el et
= neon_check_type (3, rs
,
14812 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14813 NEON_ENCODE (SCALAR
, inst
);
14814 neon_mul_mac (et
, neon_quad (rs
));
14818 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14819 affected if we specify unsigned args. */
14820 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14825 do_neon_fmac (void)
14827 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14830 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14833 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14839 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14840 struct neon_type_el et
= neon_check_type (3, rs
,
14841 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14842 neon_three_same (neon_quad (rs
), 0, et
.size
);
14845 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14846 same types as the MAC equivalents. The polynomial type for this instruction
14847 is encoded the same as the integer type. */
14852 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14855 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14858 if (inst
.operands
[2].isscalar
)
14859 do_neon_mac_maybe_scalar ();
14861 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14865 do_neon_qdmulh (void)
14867 if (inst
.operands
[2].isscalar
)
14869 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14870 struct neon_type_el et
= neon_check_type (3, rs
,
14871 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14872 NEON_ENCODE (SCALAR
, inst
);
14873 neon_mul_mac (et
, neon_quad (rs
));
14877 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14878 struct neon_type_el et
= neon_check_type (3, rs
,
14879 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14880 NEON_ENCODE (INTEGER
, inst
);
14881 /* The U bit (rounding) comes from bit mask. */
14882 neon_three_same (neon_quad (rs
), 0, et
.size
);
14887 do_neon_fcmp_absolute (void)
14889 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14890 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14891 /* Size field comes from bit mask. */
14892 neon_three_same (neon_quad (rs
), 1, -1);
14896 do_neon_fcmp_absolute_inv (void)
14898 neon_exchange_operands ();
14899 do_neon_fcmp_absolute ();
14903 do_neon_step (void)
14905 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14906 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14907 neon_three_same (neon_quad (rs
), 0, -1);
14911 do_neon_abs_neg (void)
14913 enum neon_shape rs
;
14914 struct neon_type_el et
;
14916 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14919 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14922 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14923 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14925 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14926 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14927 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14928 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14929 inst
.instruction
|= neon_quad (rs
) << 6;
14930 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14931 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14933 neon_dp_fixup (&inst
);
14939 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14940 struct neon_type_el et
= neon_check_type (2, rs
,
14941 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14942 int imm
= inst
.operands
[2].imm
;
14943 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14944 _("immediate out of range for insert"));
14945 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14951 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14952 struct neon_type_el et
= neon_check_type (2, rs
,
14953 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14954 int imm
= inst
.operands
[2].imm
;
14955 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14956 _("immediate out of range for insert"));
14957 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14961 do_neon_qshlu_imm (void)
14963 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14964 struct neon_type_el et
= neon_check_type (2, rs
,
14965 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14966 int imm
= inst
.operands
[2].imm
;
14967 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14968 _("immediate out of range for shift"));
14969 /* Only encodes the 'U present' variant of the instruction.
14970 In this case, signed types have OP (bit 8) set to 0.
14971 Unsigned types have OP set to 1. */
14972 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14973 /* The rest of the bits are the same as other immediate shifts. */
14974 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14978 do_neon_qmovn (void)
14980 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14981 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14982 /* Saturating move where operands can be signed or unsigned, and the
14983 destination has the same signedness. */
14984 NEON_ENCODE (INTEGER
, inst
);
14985 if (et
.type
== NT_unsigned
)
14986 inst
.instruction
|= 0xc0;
14988 inst
.instruction
|= 0x80;
14989 neon_two_same (0, 1, et
.size
/ 2);
14993 do_neon_qmovun (void)
14995 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14996 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14997 /* Saturating move with unsigned results. Operands must be signed. */
14998 NEON_ENCODE (INTEGER
, inst
);
14999 neon_two_same (0, 1, et
.size
/ 2);
15003 do_neon_rshift_sat_narrow (void)
15005 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15006 or unsigned. If operands are unsigned, results must also be unsigned. */
15007 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15008 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15009 int imm
= inst
.operands
[2].imm
;
15010 /* This gets the bounds check, size encoding and immediate bits calculation
15014 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15015 VQMOVN.I<size> <Dd>, <Qm>. */
15018 inst
.operands
[2].present
= 0;
15019 inst
.instruction
= N_MNEM_vqmovn
;
15024 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15025 _("immediate out of range"));
15026 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15030 do_neon_rshift_sat_narrow_u (void)
15032 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15033 or unsigned. If operands are unsigned, results must also be unsigned. */
15034 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15035 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15036 int imm
= inst
.operands
[2].imm
;
15037 /* This gets the bounds check, size encoding and immediate bits calculation
15041 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15042 VQMOVUN.I<size> <Dd>, <Qm>. */
15045 inst
.operands
[2].present
= 0;
15046 inst
.instruction
= N_MNEM_vqmovun
;
15051 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15052 _("immediate out of range"));
15053 /* FIXME: The manual is kind of unclear about what value U should have in
15054 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15056 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15060 do_neon_movn (void)
15062 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15063 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15064 NEON_ENCODE (INTEGER
, inst
);
15065 neon_two_same (0, 1, et
.size
/ 2);
15069 do_neon_rshift_narrow (void)
15071 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15072 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15073 int imm
= inst
.operands
[2].imm
;
15074 /* This gets the bounds check, size encoding and immediate bits calculation
15078 /* If immediate is zero then we are a pseudo-instruction for
15079 VMOVN.I<size> <Dd>, <Qm> */
15082 inst
.operands
[2].present
= 0;
15083 inst
.instruction
= N_MNEM_vmovn
;
15088 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15089 _("immediate out of range for narrowing operation"));
15090 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15094 do_neon_shll (void)
15096 /* FIXME: Type checking when lengthening. */
15097 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15098 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15099 unsigned imm
= inst
.operands
[2].imm
;
15101 if (imm
== et
.size
)
15103 /* Maximum shift variant. */
15104 NEON_ENCODE (INTEGER
, inst
);
15105 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15106 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15107 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15108 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15109 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15111 neon_dp_fixup (&inst
);
15115 /* A more-specific type check for non-max versions. */
15116 et
= neon_check_type (2, NS_QDI
,
15117 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15118 NEON_ENCODE (IMMED
, inst
);
15119 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15123 /* Check the various types for the VCVT instruction, and return which version
15124 the current instruction is. */
15126 #define CVT_FLAVOUR_VAR \
15127 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15128 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15129 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15130 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15131 /* Half-precision conversions. */ \
15132 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15133 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15134 /* VFP instructions. */ \
15135 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15136 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15137 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15138 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15139 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15140 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15141 /* VFP instructions with bitshift. */ \
15142 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15143 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15144 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15145 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15146 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15147 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15148 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15149 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15151 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15152 neon_cvt_flavour_##C,
15154 /* The different types of conversions we can do. */
15155 enum neon_cvt_flavour
15158 neon_cvt_flavour_invalid
,
15159 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15164 static enum neon_cvt_flavour
15165 get_neon_cvt_flavour (enum neon_shape rs
)
15167 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15168 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15169 if (et.type != NT_invtype) \
15171 inst.error = NULL; \
15172 return (neon_cvt_flavour_##C); \
15175 struct neon_type_el et
;
15176 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15177 || rs
== NS_FF
) ? N_VFP
: 0;
15178 /* The instruction versions which take an immediate take one register
15179 argument, which is extended to the width of the full register. Thus the
15180 "source" and "destination" registers must have the same width. Hack that
15181 here by making the size equal to the key (wider, in this case) operand. */
15182 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15186 return neon_cvt_flavour_invalid
;
15201 /* Neon-syntax VFP conversions. */
15204 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15206 const char *opname
= 0;
15208 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15210 /* Conversions with immediate bitshift. */
15211 const char *enc
[] =
15213 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15219 if (flavour
< (int) ARRAY_SIZE (enc
))
15221 opname
= enc
[flavour
];
15222 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15223 _("operands 0 and 1 must be the same register"));
15224 inst
.operands
[1] = inst
.operands
[2];
15225 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15230 /* Conversions without bitshift. */
15231 const char *enc
[] =
15233 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15239 if (flavour
< (int) ARRAY_SIZE (enc
))
15240 opname
= enc
[flavour
];
15244 do_vfp_nsyn_opcode (opname
);
15248 do_vfp_nsyn_cvtz (void)
15250 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15251 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15252 const char *enc
[] =
15254 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15260 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15261 do_vfp_nsyn_opcode (enc
[flavour
]);
15265 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15266 enum neon_cvt_mode mode
)
15271 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15272 D register operands. */
15273 if (flavour
== neon_cvt_flavour_s32_f64
15274 || flavour
== neon_cvt_flavour_u32_f64
)
15275 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15278 set_it_insn_type (OUTSIDE_IT_INSN
);
15282 case neon_cvt_flavour_s32_f64
:
15286 case neon_cvt_flavour_s32_f32
:
15290 case neon_cvt_flavour_u32_f64
:
15294 case neon_cvt_flavour_u32_f32
:
15299 first_error (_("invalid instruction shape"));
15305 case neon_cvt_mode_a
: rm
= 0; break;
15306 case neon_cvt_mode_n
: rm
= 1; break;
15307 case neon_cvt_mode_p
: rm
= 2; break;
15308 case neon_cvt_mode_m
: rm
= 3; break;
15309 default: first_error (_("invalid rounding mode")); return;
15312 NEON_ENCODE (FPV8
, inst
);
15313 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15314 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15315 inst
.instruction
|= sz
<< 8;
15316 inst
.instruction
|= op
<< 7;
15317 inst
.instruction
|= rm
<< 16;
15318 inst
.instruction
|= 0xf0000000;
15319 inst
.is_neon
= TRUE
;
15323 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15325 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15326 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15327 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15329 /* PR11109: Handle round-to-zero for VCVT conversions. */
15330 if (mode
== neon_cvt_mode_z
15331 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15332 && (flavour
== neon_cvt_flavour_s32_f32
15333 || flavour
== neon_cvt_flavour_u32_f32
15334 || flavour
== neon_cvt_flavour_s32_f64
15335 || flavour
== neon_cvt_flavour_u32_f64
)
15336 && (rs
== NS_FD
|| rs
== NS_FF
))
15338 do_vfp_nsyn_cvtz ();
15342 /* VFP rather than Neon conversions. */
15343 if (flavour
>= neon_cvt_flavour_first_fp
)
15345 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15346 do_vfp_nsyn_cvt (rs
, flavour
);
15348 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15359 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15361 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15364 /* Fixed-point conversion with #0 immediate is encoded as an
15365 integer conversion. */
15366 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15368 immbits
= 32 - inst
.operands
[2].imm
;
15369 NEON_ENCODE (IMMED
, inst
);
15370 if (flavour
!= neon_cvt_flavour_invalid
)
15371 inst
.instruction
|= enctab
[flavour
];
15372 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15374 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15375 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15376 inst
.instruction
|= neon_quad (rs
) << 6;
15377 inst
.instruction
|= 1 << 21;
15378 inst
.instruction
|= immbits
<< 16;
15380 neon_dp_fixup (&inst
);
15386 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15388 NEON_ENCODE (FLOAT
, inst
);
15389 set_it_insn_type (OUTSIDE_IT_INSN
);
15391 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15394 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15395 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15396 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15397 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15398 inst
.instruction
|= neon_quad (rs
) << 6;
15399 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15400 inst
.instruction
|= mode
<< 8;
15402 inst
.instruction
|= 0xfc000000;
15404 inst
.instruction
|= 0xf0000000;
15410 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15412 NEON_ENCODE (INTEGER
, inst
);
15414 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15417 if (flavour
!= neon_cvt_flavour_invalid
)
15418 inst
.instruction
|= enctab
[flavour
];
15420 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15421 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15422 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15423 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15424 inst
.instruction
|= neon_quad (rs
) << 6;
15425 inst
.instruction
|= 2 << 18;
15427 neon_dp_fixup (&inst
);
15432 /* Half-precision conversions for Advanced SIMD -- neon. */
15437 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15439 as_bad (_("operand size must match register width"));
15444 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15446 as_bad (_("operand size must match register width"));
15451 inst
.instruction
= 0x3b60600;
15453 inst
.instruction
= 0x3b60700;
15455 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15459 neon_dp_fixup (&inst
);
15463 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15464 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15465 do_vfp_nsyn_cvt (rs
, flavour
);
15467 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15472 do_neon_cvtr (void)
15474 do_neon_cvt_1 (neon_cvt_mode_x
);
15480 do_neon_cvt_1 (neon_cvt_mode_z
);
15484 do_neon_cvta (void)
15486 do_neon_cvt_1 (neon_cvt_mode_a
);
15490 do_neon_cvtn (void)
15492 do_neon_cvt_1 (neon_cvt_mode_n
);
15496 do_neon_cvtp (void)
15498 do_neon_cvt_1 (neon_cvt_mode_p
);
15502 do_neon_cvtm (void)
15504 do_neon_cvt_1 (neon_cvt_mode_m
);
15508 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15511 mark_feature_used (&fpu_vfp_ext_armv8
);
15513 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15514 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15515 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15516 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15517 inst
.instruction
|= to
? 0x10000 : 0;
15518 inst
.instruction
|= t
? 0x80 : 0;
15519 inst
.instruction
|= is_double
? 0x100 : 0;
15520 do_vfp_cond_or_thumb ();
15524 do_neon_cvttb_1 (bfd_boolean t
)
15526 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15530 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15533 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15535 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15538 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15540 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15542 /* The VCVTB and VCVTT instructions with D-register operands
15543 don't work for SP only targets. */
15544 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15548 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15550 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15552 /* The VCVTB and VCVTT instructions with D-register operands
15553 don't work for SP only targets. */
15554 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15558 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15565 do_neon_cvtb (void)
15567 do_neon_cvttb_1 (FALSE
);
15572 do_neon_cvtt (void)
15574 do_neon_cvttb_1 (TRUE
);
15578 neon_move_immediate (void)
15580 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15581 struct neon_type_el et
= neon_check_type (2, rs
,
15582 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15583 unsigned immlo
, immhi
= 0, immbits
;
15584 int op
, cmode
, float_p
;
15586 constraint (et
.type
== NT_invtype
,
15587 _("operand size must be specified for immediate VMOV"));
15589 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15590 op
= (inst
.instruction
& (1 << 5)) != 0;
15592 immlo
= inst
.operands
[1].imm
;
15593 if (inst
.operands
[1].regisimm
)
15594 immhi
= inst
.operands
[1].reg
;
15596 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15597 _("immediate has bits set outside the operand size"));
15599 float_p
= inst
.operands
[1].immisfloat
;
15601 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15602 et
.size
, et
.type
)) == FAIL
)
15604 /* Invert relevant bits only. */
15605 neon_invert_size (&immlo
, &immhi
, et
.size
);
15606 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15607 with one or the other; those cases are caught by
15608 neon_cmode_for_move_imm. */
15610 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15611 &op
, et
.size
, et
.type
)) == FAIL
)
15613 first_error (_("immediate out of range"));
15618 inst
.instruction
&= ~(1 << 5);
15619 inst
.instruction
|= op
<< 5;
15621 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15622 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15623 inst
.instruction
|= neon_quad (rs
) << 6;
15624 inst
.instruction
|= cmode
<< 8;
15626 neon_write_immbits (immbits
);
15632 if (inst
.operands
[1].isreg
)
15634 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15636 NEON_ENCODE (INTEGER
, inst
);
15637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15638 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15639 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15640 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15641 inst
.instruction
|= neon_quad (rs
) << 6;
15645 NEON_ENCODE (IMMED
, inst
);
15646 neon_move_immediate ();
15649 neon_dp_fixup (&inst
);
15652 /* Encode instructions of form:
15654 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15655 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15658 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15660 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15661 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15662 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15663 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15664 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15665 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15666 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15667 inst
.instruction
|= neon_logbits (size
) << 20;
15669 neon_dp_fixup (&inst
);
15673 do_neon_dyadic_long (void)
15675 /* FIXME: Type checking for lengthening op. */
15676 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15677 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15678 neon_mixed_length (et
, et
.size
);
15682 do_neon_abal (void)
15684 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15685 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15686 neon_mixed_length (et
, et
.size
);
15690 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15692 if (inst
.operands
[2].isscalar
)
15694 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15695 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15696 NEON_ENCODE (SCALAR
, inst
);
15697 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15701 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15702 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15703 NEON_ENCODE (INTEGER
, inst
);
15704 neon_mixed_length (et
, et
.size
);
15709 do_neon_mac_maybe_scalar_long (void)
15711 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15715 do_neon_dyadic_wide (void)
15717 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15718 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15719 neon_mixed_length (et
, et
.size
);
15723 do_neon_dyadic_narrow (void)
15725 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15726 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15727 /* Operand sign is unimportant, and the U bit is part of the opcode,
15728 so force the operand type to integer. */
15729 et
.type
= NT_integer
;
15730 neon_mixed_length (et
, et
.size
/ 2);
15734 do_neon_mul_sat_scalar_long (void)
15736 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15740 do_neon_vmull (void)
15742 if (inst
.operands
[2].isscalar
)
15743 do_neon_mac_maybe_scalar_long ();
15746 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15747 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15749 if (et
.type
== NT_poly
)
15750 NEON_ENCODE (POLY
, inst
);
15752 NEON_ENCODE (INTEGER
, inst
);
15754 /* For polynomial encoding the U bit must be zero, and the size must
15755 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15756 obviously, as 0b10). */
15759 /* Check we're on the correct architecture. */
15760 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15762 _("Instruction form not available on this architecture.");
15767 neon_mixed_length (et
, et
.size
);
15774 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15775 struct neon_type_el et
= neon_check_type (3, rs
,
15776 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15777 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15779 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15780 _("shift out of range"));
15781 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15782 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15783 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15784 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15785 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15786 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15787 inst
.instruction
|= neon_quad (rs
) << 6;
15788 inst
.instruction
|= imm
<< 8;
15790 neon_dp_fixup (&inst
);
15796 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15797 struct neon_type_el et
= neon_check_type (2, rs
,
15798 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15799 unsigned op
= (inst
.instruction
>> 7) & 3;
15800 /* N (width of reversed regions) is encoded as part of the bitmask. We
15801 extract it here to check the elements to be reversed are smaller.
15802 Otherwise we'd get a reserved instruction. */
15803 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15804 gas_assert (elsize
!= 0);
15805 constraint (et
.size
>= elsize
,
15806 _("elements must be smaller than reversal region"));
15807 neon_two_same (neon_quad (rs
), 1, et
.size
);
15813 if (inst
.operands
[1].isscalar
)
15815 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15816 struct neon_type_el et
= neon_check_type (2, rs
,
15817 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15818 unsigned sizebits
= et
.size
>> 3;
15819 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15820 int logsize
= neon_logbits (et
.size
);
15821 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15823 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15826 NEON_ENCODE (SCALAR
, inst
);
15827 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15828 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15829 inst
.instruction
|= LOW4 (dm
);
15830 inst
.instruction
|= HI1 (dm
) << 5;
15831 inst
.instruction
|= neon_quad (rs
) << 6;
15832 inst
.instruction
|= x
<< 17;
15833 inst
.instruction
|= sizebits
<< 16;
15835 neon_dp_fixup (&inst
);
15839 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15840 struct neon_type_el et
= neon_check_type (2, rs
,
15841 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15842 /* Duplicate ARM register to lanes of vector. */
15843 NEON_ENCODE (ARMREG
, inst
);
15846 case 8: inst
.instruction
|= 0x400000; break;
15847 case 16: inst
.instruction
|= 0x000020; break;
15848 case 32: inst
.instruction
|= 0x000000; break;
15851 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15852 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15853 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15854 inst
.instruction
|= neon_quad (rs
) << 21;
15855 /* The encoding for this instruction is identical for the ARM and Thumb
15856 variants, except for the condition field. */
15857 do_vfp_cond_or_thumb ();
15861 /* VMOV has particularly many variations. It can be one of:
15862 0. VMOV<c><q> <Qd>, <Qm>
15863 1. VMOV<c><q> <Dd>, <Dm>
15864 (Register operations, which are VORR with Rm = Rn.)
15865 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15866 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15868 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15869 (ARM register to scalar.)
15870 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15871 (Two ARM registers to vector.)
15872 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15873 (Scalar to ARM register.)
15874 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15875 (Vector to two ARM registers.)
15876 8. VMOV.F32 <Sd>, <Sm>
15877 9. VMOV.F64 <Dd>, <Dm>
15878 (VFP register moves.)
15879 10. VMOV.F32 <Sd>, #imm
15880 11. VMOV.F64 <Dd>, #imm
15881 (VFP float immediate load.)
15882 12. VMOV <Rd>, <Sm>
15883 (VFP single to ARM reg.)
15884 13. VMOV <Sd>, <Rm>
15885 (ARM reg to VFP single.)
15886 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15887 (Two ARM regs to two VFP singles.)
15888 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15889 (Two VFP singles to two ARM regs.)
15891 These cases can be disambiguated using neon_select_shape, except cases 1/9
15892 and 3/11 which depend on the operand type too.
15894 All the encoded bits are hardcoded by this function.
15896 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15897 Cases 5, 7 may be used with VFPv2 and above.
15899 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15900 can specify a type where it doesn't make sense to, and is ignored). */
15905 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15906 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15908 struct neon_type_el et
;
15909 const char *ldconst
= 0;
15913 case NS_DD
: /* case 1/9. */
15914 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15915 /* It is not an error here if no type is given. */
15917 if (et
.type
== NT_float
&& et
.size
== 64)
15919 do_vfp_nsyn_opcode ("fcpyd");
15922 /* fall through. */
15924 case NS_QQ
: /* case 0/1. */
15926 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15928 /* The architecture manual I have doesn't explicitly state which
15929 value the U bit should have for register->register moves, but
15930 the equivalent VORR instruction has U = 0, so do that. */
15931 inst
.instruction
= 0x0200110;
15932 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15933 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15934 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15935 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15936 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15937 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15938 inst
.instruction
|= neon_quad (rs
) << 6;
15940 neon_dp_fixup (&inst
);
15944 case NS_DI
: /* case 3/11. */
15945 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15947 if (et
.type
== NT_float
&& et
.size
== 64)
15949 /* case 11 (fconstd). */
15950 ldconst
= "fconstd";
15951 goto encode_fconstd
;
15953 /* fall through. */
15955 case NS_QI
: /* case 2/3. */
15956 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15958 inst
.instruction
= 0x0800010;
15959 neon_move_immediate ();
15960 neon_dp_fixup (&inst
);
15963 case NS_SR
: /* case 4. */
15965 unsigned bcdebits
= 0;
15967 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15968 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15970 /* .<size> is optional here, defaulting to .32. */
15971 if (inst
.vectype
.elems
== 0
15972 && inst
.operands
[0].vectype
.type
== NT_invtype
15973 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15975 inst
.vectype
.el
[0].type
= NT_untyped
;
15976 inst
.vectype
.el
[0].size
= 32;
15977 inst
.vectype
.elems
= 1;
15980 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15981 logsize
= neon_logbits (et
.size
);
15983 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15985 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15986 && et
.size
!= 32, _(BAD_FPU
));
15987 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15988 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15992 case 8: bcdebits
= 0x8; break;
15993 case 16: bcdebits
= 0x1; break;
15994 case 32: bcdebits
= 0x0; break;
15998 bcdebits
|= x
<< logsize
;
16000 inst
.instruction
= 0xe000b10;
16001 do_vfp_cond_or_thumb ();
16002 inst
.instruction
|= LOW4 (dn
) << 16;
16003 inst
.instruction
|= HI1 (dn
) << 7;
16004 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16005 inst
.instruction
|= (bcdebits
& 3) << 5;
16006 inst
.instruction
|= (bcdebits
>> 2) << 21;
16010 case NS_DRR
: /* case 5 (fmdrr). */
16011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16014 inst
.instruction
= 0xc400b10;
16015 do_vfp_cond_or_thumb ();
16016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16017 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16018 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16019 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16022 case NS_RS
: /* case 6. */
16025 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16026 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16027 unsigned abcdebits
= 0;
16029 /* .<dt> is optional here, defaulting to .32. */
16030 if (inst
.vectype
.elems
== 0
16031 && inst
.operands
[0].vectype
.type
== NT_invtype
16032 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16034 inst
.vectype
.el
[0].type
= NT_untyped
;
16035 inst
.vectype
.el
[0].size
= 32;
16036 inst
.vectype
.elems
= 1;
16039 et
= neon_check_type (2, NS_NULL
,
16040 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16041 logsize
= neon_logbits (et
.size
);
16043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16045 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16046 && et
.size
!= 32, _(BAD_FPU
));
16047 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16048 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16052 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16053 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16054 case 32: abcdebits
= 0x00; break;
16058 abcdebits
|= x
<< logsize
;
16059 inst
.instruction
= 0xe100b10;
16060 do_vfp_cond_or_thumb ();
16061 inst
.instruction
|= LOW4 (dn
) << 16;
16062 inst
.instruction
|= HI1 (dn
) << 7;
16063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16064 inst
.instruction
|= (abcdebits
& 3) << 5;
16065 inst
.instruction
|= (abcdebits
>> 2) << 21;
16069 case NS_RRD
: /* case 7 (fmrrd). */
16070 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16073 inst
.instruction
= 0xc500b10;
16074 do_vfp_cond_or_thumb ();
16075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16077 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16078 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16081 case NS_FF
: /* case 8 (fcpys). */
16082 do_vfp_nsyn_opcode ("fcpys");
16085 case NS_FI
: /* case 10 (fconsts). */
16086 ldconst
= "fconsts";
16088 if (is_quarter_float (inst
.operands
[1].imm
))
16090 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16091 do_vfp_nsyn_opcode (ldconst
);
16094 first_error (_("immediate out of range"));
16097 case NS_RF
: /* case 12 (fmrs). */
16098 do_vfp_nsyn_opcode ("fmrs");
16101 case NS_FR
: /* case 13 (fmsr). */
16102 do_vfp_nsyn_opcode ("fmsr");
16105 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16106 (one of which is a list), but we have parsed four. Do some fiddling to
16107 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16109 case NS_RRFF
: /* case 14 (fmrrs). */
16110 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16111 _("VFP registers must be adjacent"));
16112 inst
.operands
[2].imm
= 2;
16113 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16114 do_vfp_nsyn_opcode ("fmrrs");
16117 case NS_FFRR
: /* case 15 (fmsrr). */
16118 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16119 _("VFP registers must be adjacent"));
16120 inst
.operands
[1] = inst
.operands
[2];
16121 inst
.operands
[2] = inst
.operands
[3];
16122 inst
.operands
[0].imm
= 2;
16123 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16124 do_vfp_nsyn_opcode ("fmsrr");
16128 /* neon_select_shape has determined that the instruction
16129 shape is wrong and has already set the error message. */
16138 do_neon_rshift_round_imm (void)
16140 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16141 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16142 int imm
= inst
.operands
[2].imm
;
16144 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16147 inst
.operands
[2].present
= 0;
16152 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16153 _("immediate out of range for shift"));
16154 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16159 do_neon_movl (void)
16161 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16162 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16163 unsigned sizebits
= et
.size
>> 3;
16164 inst
.instruction
|= sizebits
<< 19;
16165 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16171 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16172 struct neon_type_el et
= neon_check_type (2, rs
,
16173 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16174 NEON_ENCODE (INTEGER
, inst
);
16175 neon_two_same (neon_quad (rs
), 1, et
.size
);
16179 do_neon_zip_uzp (void)
16181 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16182 struct neon_type_el et
= neon_check_type (2, rs
,
16183 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16184 if (rs
== NS_DD
&& et
.size
== 32)
16186 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16187 inst
.instruction
= N_MNEM_vtrn
;
16191 neon_two_same (neon_quad (rs
), 1, et
.size
);
16195 do_neon_sat_abs_neg (void)
16197 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16198 struct neon_type_el et
= neon_check_type (2, rs
,
16199 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16200 neon_two_same (neon_quad (rs
), 1, et
.size
);
16204 do_neon_pair_long (void)
16206 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16207 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16208 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16209 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16210 neon_two_same (neon_quad (rs
), 1, et
.size
);
16214 do_neon_recip_est (void)
16216 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16217 struct neon_type_el et
= neon_check_type (2, rs
,
16218 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16219 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16220 neon_two_same (neon_quad (rs
), 1, et
.size
);
16226 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16227 struct neon_type_el et
= neon_check_type (2, rs
,
16228 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16229 neon_two_same (neon_quad (rs
), 1, et
.size
);
16235 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16236 struct neon_type_el et
= neon_check_type (2, rs
,
16237 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16238 neon_two_same (neon_quad (rs
), 1, et
.size
);
16244 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16245 struct neon_type_el et
= neon_check_type (2, rs
,
16246 N_EQK
| N_INT
, N_8
| N_KEY
);
16247 neon_two_same (neon_quad (rs
), 1, et
.size
);
16253 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16254 neon_two_same (neon_quad (rs
), 1, -1);
16258 do_neon_tbl_tbx (void)
16260 unsigned listlenbits
;
16261 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16263 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16265 first_error (_("bad list length for table lookup"));
16269 listlenbits
= inst
.operands
[1].imm
- 1;
16270 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16271 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16272 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16273 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16274 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16275 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16276 inst
.instruction
|= listlenbits
<< 8;
16278 neon_dp_fixup (&inst
);
16282 do_neon_ldm_stm (void)
16284 /* P, U and L bits are part of bitmask. */
16285 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16286 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16288 if (inst
.operands
[1].issingle
)
16290 do_vfp_nsyn_ldm_stm (is_dbmode
);
16294 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16295 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16297 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16298 _("register list must contain at least 1 and at most 16 "
16301 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16302 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16303 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16304 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16306 inst
.instruction
|= offsetbits
;
16308 do_vfp_cond_or_thumb ();
16312 do_neon_ldr_str (void)
16314 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16316 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16317 And is UNPREDICTABLE in thumb mode. */
16319 && inst
.operands
[1].reg
== REG_PC
16320 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16323 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16324 else if (warn_on_deprecated
)
16325 as_tsktsk (_("Use of PC here is deprecated"));
16328 if (inst
.operands
[0].issingle
)
16331 do_vfp_nsyn_opcode ("flds");
16333 do_vfp_nsyn_opcode ("fsts");
16338 do_vfp_nsyn_opcode ("fldd");
16340 do_vfp_nsyn_opcode ("fstd");
16344 /* "interleave" version also handles non-interleaving register VLD1/VST1
16348 do_neon_ld_st_interleave (void)
16350 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16351 N_8
| N_16
| N_32
| N_64
);
16352 unsigned alignbits
= 0;
16354 /* The bits in this table go:
16355 0: register stride of one (0) or two (1)
16356 1,2: register list length, minus one (1, 2, 3, 4).
16357 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16358 We use -1 for invalid entries. */
16359 const int typetable
[] =
16361 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16362 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16363 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16364 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16368 if (et
.type
== NT_invtype
)
16371 if (inst
.operands
[1].immisalign
)
16372 switch (inst
.operands
[1].imm
>> 8)
16374 case 64: alignbits
= 1; break;
16376 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16377 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16378 goto bad_alignment
;
16382 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16383 goto bad_alignment
;
16388 first_error (_("bad alignment"));
16392 inst
.instruction
|= alignbits
<< 4;
16393 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16395 /* Bits [4:6] of the immediate in a list specifier encode register stride
16396 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16397 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16398 up the right value for "type" in a table based on this value and the given
16399 list style, then stick it back. */
16400 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16401 | (((inst
.instruction
>> 8) & 3) << 3);
16403 typebits
= typetable
[idx
];
16405 constraint (typebits
== -1, _("bad list type for instruction"));
16406 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16407 _("bad element type for instruction"));
16409 inst
.instruction
&= ~0xf00;
16410 inst
.instruction
|= typebits
<< 8;
16413 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16414 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16415 otherwise. The variable arguments are a list of pairs of legal (size, align)
16416 values, terminated with -1. */
16419 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16422 int result
= FAIL
, thissize
, thisalign
;
16424 if (!inst
.operands
[1].immisalign
)
16430 va_start (ap
, do_align
);
16434 thissize
= va_arg (ap
, int);
16435 if (thissize
== -1)
16437 thisalign
= va_arg (ap
, int);
16439 if (size
== thissize
&& align
== thisalign
)
16442 while (result
!= SUCCESS
);
16446 if (result
== SUCCESS
)
16449 first_error (_("unsupported alignment for instruction"));
16455 do_neon_ld_st_lane (void)
16457 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16458 int align_good
, do_align
= 0;
16459 int logsize
= neon_logbits (et
.size
);
16460 int align
= inst
.operands
[1].imm
>> 8;
16461 int n
= (inst
.instruction
>> 8) & 3;
16462 int max_el
= 64 / et
.size
;
16464 if (et
.type
== NT_invtype
)
16467 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16468 _("bad list length"));
16469 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16470 _("scalar index out of range"));
16471 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16473 _("stride of 2 unavailable when element size is 8"));
16477 case 0: /* VLD1 / VST1. */
16478 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16480 if (align_good
== FAIL
)
16484 unsigned alignbits
= 0;
16487 case 16: alignbits
= 0x1; break;
16488 case 32: alignbits
= 0x3; break;
16491 inst
.instruction
|= alignbits
<< 4;
16495 case 1: /* VLD2 / VST2. */
16496 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16498 if (align_good
== FAIL
)
16501 inst
.instruction
|= 1 << 4;
16504 case 2: /* VLD3 / VST3. */
16505 constraint (inst
.operands
[1].immisalign
,
16506 _("can't use alignment with this instruction"));
16509 case 3: /* VLD4 / VST4. */
16510 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16511 16, 64, 32, 64, 32, 128, -1);
16512 if (align_good
== FAIL
)
16516 unsigned alignbits
= 0;
16519 case 8: alignbits
= 0x1; break;
16520 case 16: alignbits
= 0x1; break;
16521 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16524 inst
.instruction
|= alignbits
<< 4;
16531 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16532 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16533 inst
.instruction
|= 1 << (4 + logsize
);
16535 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16536 inst
.instruction
|= logsize
<< 10;
16539 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16542 do_neon_ld_dup (void)
16544 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16545 int align_good
, do_align
= 0;
16547 if (et
.type
== NT_invtype
)
16550 switch ((inst
.instruction
>> 8) & 3)
16552 case 0: /* VLD1. */
16553 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16554 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16555 &do_align
, 16, 16, 32, 32, -1);
16556 if (align_good
== FAIL
)
16558 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16561 case 2: inst
.instruction
|= 1 << 5; break;
16562 default: first_error (_("bad list length")); return;
16564 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16567 case 1: /* VLD2. */
16568 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16569 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16570 if (align_good
== FAIL
)
16572 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16573 _("bad list length"));
16574 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16575 inst
.instruction
|= 1 << 5;
16576 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16579 case 2: /* VLD3. */
16580 constraint (inst
.operands
[1].immisalign
,
16581 _("can't use alignment with this instruction"));
16582 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16583 _("bad list length"));
16584 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16585 inst
.instruction
|= 1 << 5;
16586 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16589 case 3: /* VLD4. */
16591 int align
= inst
.operands
[1].imm
>> 8;
16592 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16593 16, 64, 32, 64, 32, 128, -1);
16594 if (align_good
== FAIL
)
16596 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16597 _("bad list length"));
16598 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16599 inst
.instruction
|= 1 << 5;
16600 if (et
.size
== 32 && align
== 128)
16601 inst
.instruction
|= 0x3 << 6;
16603 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16610 inst
.instruction
|= do_align
<< 4;
16613 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16614 apart from bits [11:4]. */
16617 do_neon_ldx_stx (void)
16619 if (inst
.operands
[1].isreg
)
16620 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16622 switch (NEON_LANE (inst
.operands
[0].imm
))
16624 case NEON_INTERLEAVE_LANES
:
16625 NEON_ENCODE (INTERLV
, inst
);
16626 do_neon_ld_st_interleave ();
16629 case NEON_ALL_LANES
:
16630 NEON_ENCODE (DUP
, inst
);
16631 if (inst
.instruction
== N_INV
)
16633 first_error ("only loads support such operands");
16640 NEON_ENCODE (LANE
, inst
);
16641 do_neon_ld_st_lane ();
16644 /* L bit comes from bit mask. */
16645 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16646 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16647 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16649 if (inst
.operands
[1].postind
)
16651 int postreg
= inst
.operands
[1].imm
& 0xf;
16652 constraint (!inst
.operands
[1].immisreg
,
16653 _("post-index must be a register"));
16654 constraint (postreg
== 0xd || postreg
== 0xf,
16655 _("bad register for post-index"));
16656 inst
.instruction
|= postreg
;
16660 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16661 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16662 || inst
.reloc
.exp
.X_add_number
!= 0,
16665 if (inst
.operands
[1].writeback
)
16667 inst
.instruction
|= 0xd;
16670 inst
.instruction
|= 0xf;
16674 inst
.instruction
|= 0xf9000000;
16676 inst
.instruction
|= 0xf4000000;
16681 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16683 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16684 D register operands. */
16685 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16686 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16689 NEON_ENCODE (FPV8
, inst
);
16692 do_vfp_sp_dyadic ();
16694 do_vfp_dp_rd_rn_rm ();
16697 inst
.instruction
|= 0x100;
16699 inst
.instruction
|= 0xf0000000;
16705 set_it_insn_type (OUTSIDE_IT_INSN
);
16707 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16708 first_error (_("invalid instruction shape"));
16714 set_it_insn_type (OUTSIDE_IT_INSN
);
16716 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16719 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16722 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16726 do_vrint_1 (enum neon_cvt_mode mode
)
16728 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16729 struct neon_type_el et
;
16734 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16735 D register operands. */
16736 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16737 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16740 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16741 if (et
.type
!= NT_invtype
)
16743 /* VFP encodings. */
16744 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16745 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16746 set_it_insn_type (OUTSIDE_IT_INSN
);
16748 NEON_ENCODE (FPV8
, inst
);
16750 do_vfp_sp_monadic ();
16752 do_vfp_dp_rd_rm ();
16756 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16757 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16758 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16759 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16760 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16761 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16762 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16766 inst
.instruction
|= (rs
== NS_DD
) << 8;
16767 do_vfp_cond_or_thumb ();
16771 /* Neon encodings (or something broken...). */
16773 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16775 if (et
.type
== NT_invtype
)
16778 set_it_insn_type (OUTSIDE_IT_INSN
);
16779 NEON_ENCODE (FLOAT
, inst
);
16781 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16784 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16785 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16786 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16787 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16788 inst
.instruction
|= neon_quad (rs
) << 6;
16791 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16792 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16793 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16794 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16795 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16796 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16797 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16802 inst
.instruction
|= 0xfc000000;
16804 inst
.instruction
|= 0xf0000000;
16811 do_vrint_1 (neon_cvt_mode_x
);
16817 do_vrint_1 (neon_cvt_mode_z
);
16823 do_vrint_1 (neon_cvt_mode_r
);
16829 do_vrint_1 (neon_cvt_mode_a
);
16835 do_vrint_1 (neon_cvt_mode_n
);
16841 do_vrint_1 (neon_cvt_mode_p
);
16847 do_vrint_1 (neon_cvt_mode_m
);
16850 /* Crypto v1 instructions. */
16852 do_crypto_2op_1 (unsigned elttype
, int op
)
16854 set_it_insn_type (OUTSIDE_IT_INSN
);
16856 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16862 NEON_ENCODE (INTEGER
, inst
);
16863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16864 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16865 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16866 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16868 inst
.instruction
|= op
<< 6;
16871 inst
.instruction
|= 0xfc000000;
16873 inst
.instruction
|= 0xf0000000;
16877 do_crypto_3op_1 (int u
, int op
)
16879 set_it_insn_type (OUTSIDE_IT_INSN
);
16881 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16882 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16887 NEON_ENCODE (INTEGER
, inst
);
16888 neon_three_same (1, u
, 8 << op
);
16894 do_crypto_2op_1 (N_8
, 0);
16900 do_crypto_2op_1 (N_8
, 1);
16906 do_crypto_2op_1 (N_8
, 2);
16912 do_crypto_2op_1 (N_8
, 3);
16918 do_crypto_3op_1 (0, 0);
16924 do_crypto_3op_1 (0, 1);
16930 do_crypto_3op_1 (0, 2);
16936 do_crypto_3op_1 (0, 3);
16942 do_crypto_3op_1 (1, 0);
16948 do_crypto_3op_1 (1, 1);
16952 do_sha256su1 (void)
16954 do_crypto_3op_1 (1, 2);
16960 do_crypto_2op_1 (N_32
, -1);
16966 do_crypto_2op_1 (N_32
, 0);
16970 do_sha256su0 (void)
16972 do_crypto_2op_1 (N_32
, 1);
16976 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16978 unsigned int Rd
= inst
.operands
[0].reg
;
16979 unsigned int Rn
= inst
.operands
[1].reg
;
16980 unsigned int Rm
= inst
.operands
[2].reg
;
16982 set_it_insn_type (OUTSIDE_IT_INSN
);
16983 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16984 inst
.instruction
|= LOW4 (Rn
) << 16;
16985 inst
.instruction
|= LOW4 (Rm
);
16986 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16987 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16989 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16990 as_warn (UNPRED_REG ("r15"));
16991 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16992 as_warn (UNPRED_REG ("r13"));
17032 /* Overall per-instruction processing. */
17034 /* We need to be able to fix up arbitrary expressions in some statements.
17035 This is so that we can handle symbols that are an arbitrary distance from
17036 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17037 which returns part of an address in a form which will be valid for
17038 a data instruction. We do this by pushing the expression into a symbol
17039 in the expr_section, and creating a fix for that. */
17042 fix_new_arm (fragS
* frag
,
17056 /* Create an absolute valued symbol, so we have something to
17057 refer to in the object file. Unfortunately for us, gas's
17058 generic expression parsing will already have folded out
17059 any use of .set foo/.type foo %function that may have
17060 been used to set type information of the target location,
17061 that's being specified symbolically. We have to presume
17062 the user knows what they are doing. */
17066 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17068 symbol
= symbol_find_or_make (name
);
17069 S_SET_SEGMENT (symbol
, absolute_section
);
17070 symbol_set_frag (symbol
, &zero_address_frag
);
17071 S_SET_VALUE (symbol
, exp
->X_add_number
);
17072 exp
->X_op
= O_symbol
;
17073 exp
->X_add_symbol
= symbol
;
17074 exp
->X_add_number
= 0;
17080 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17081 (enum bfd_reloc_code_real
) reloc
);
17085 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17086 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17090 /* Mark whether the fix is to a THUMB instruction, or an ARM
17092 new_fix
->tc_fix_data
= thumb_mode
;
17095 /* Create a frg for an instruction requiring relaxation. */
17097 output_relax_insn (void)
17103 /* The size of the instruction is unknown, so tie the debug info to the
17104 start of the instruction. */
17105 dwarf2_emit_insn (0);
17107 switch (inst
.reloc
.exp
.X_op
)
17110 sym
= inst
.reloc
.exp
.X_add_symbol
;
17111 offset
= inst
.reloc
.exp
.X_add_number
;
17115 offset
= inst
.reloc
.exp
.X_add_number
;
17118 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17122 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17123 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17124 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17127 /* Write a 32-bit thumb instruction to buf. */
17129 put_thumb32_insn (char * buf
, unsigned long insn
)
17131 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17132 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17136 output_inst (const char * str
)
17142 as_bad ("%s -- `%s'", inst
.error
, str
);
17147 output_relax_insn ();
17150 if (inst
.size
== 0)
17153 to
= frag_more (inst
.size
);
17154 /* PR 9814: Record the thumb mode into the current frag so that we know
17155 what type of NOP padding to use, if necessary. We override any previous
17156 setting so that if the mode has changed then the NOPS that we use will
17157 match the encoding of the last instruction in the frag. */
17158 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17160 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17162 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17163 put_thumb32_insn (to
, inst
.instruction
);
17165 else if (inst
.size
> INSN_SIZE
)
17167 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17168 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17169 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17172 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17174 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17175 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17176 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17179 dwarf2_emit_insn (inst
.size
);
17183 output_it_inst (int cond
, int mask
, char * to
)
17185 unsigned long instruction
= 0xbf00;
17188 instruction
|= mask
;
17189 instruction
|= cond
<< 4;
17193 to
= frag_more (2);
17195 dwarf2_emit_insn (2);
17199 md_number_to_chars (to
, instruction
, 2);
17204 /* Tag values used in struct asm_opcode's tag field. */
17207 OT_unconditional
, /* Instruction cannot be conditionalized.
17208 The ARM condition field is still 0xE. */
17209 OT_unconditionalF
, /* Instruction cannot be conditionalized
17210 and carries 0xF in its ARM condition field. */
17211 OT_csuffix
, /* Instruction takes a conditional suffix. */
17212 OT_csuffixF
, /* Some forms of the instruction take a conditional
17213 suffix, others place 0xF where the condition field
17215 OT_cinfix3
, /* Instruction takes a conditional infix,
17216 beginning at character index 3. (In
17217 unified mode, it becomes a suffix.) */
17218 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17219 tsts, cmps, cmns, and teqs. */
17220 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17221 character index 3, even in unified mode. Used for
17222 legacy instructions where suffix and infix forms
17223 may be ambiguous. */
17224 OT_csuf_or_in3
, /* Instruction takes either a conditional
17225 suffix or an infix at character index 3. */
17226 OT_odd_infix_unc
, /* This is the unconditional variant of an
17227 instruction that takes a conditional infix
17228 at an unusual position. In unified mode,
17229 this variant will accept a suffix. */
17230 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17231 are the conditional variants of instructions that
17232 take conditional infixes in unusual positions.
17233 The infix appears at character index
17234 (tag - OT_odd_infix_0). These are not accepted
17235 in unified mode. */
17238 /* Subroutine of md_assemble, responsible for looking up the primary
17239 opcode from the mnemonic the user wrote. STR points to the
17240 beginning of the mnemonic.
17242 This is not simply a hash table lookup, because of conditional
17243 variants. Most instructions have conditional variants, which are
17244 expressed with a _conditional affix_ to the mnemonic. If we were
17245 to encode each conditional variant as a literal string in the opcode
17246 table, it would have approximately 20,000 entries.
17248 Most mnemonics take this affix as a suffix, and in unified syntax,
17249 'most' is upgraded to 'all'. However, in the divided syntax, some
17250 instructions take the affix as an infix, notably the s-variants of
17251 the arithmetic instructions. Of those instructions, all but six
17252 have the infix appear after the third character of the mnemonic.
17254 Accordingly, the algorithm for looking up primary opcodes given
17257 1. Look up the identifier in the opcode table.
17258 If we find a match, go to step U.
17260 2. Look up the last two characters of the identifier in the
17261 conditions table. If we find a match, look up the first N-2
17262 characters of the identifier in the opcode table. If we
17263 find a match, go to step CE.
17265 3. Look up the fourth and fifth characters of the identifier in
17266 the conditions table. If we find a match, extract those
17267 characters from the identifier, and look up the remaining
17268 characters in the opcode table. If we find a match, go
17273 U. Examine the tag field of the opcode structure, in case this is
17274 one of the six instructions with its conditional infix in an
17275 unusual place. If it is, the tag tells us where to find the
17276 infix; look it up in the conditions table and set inst.cond
17277 accordingly. Otherwise, this is an unconditional instruction.
17278 Again set inst.cond accordingly. Return the opcode structure.
17280 CE. Examine the tag field to make sure this is an instruction that
17281 should receive a conditional suffix. If it is not, fail.
17282 Otherwise, set inst.cond from the suffix we already looked up,
17283 and return the opcode structure.
17285 CM. Examine the tag field to make sure this is an instruction that
17286 should receive a conditional infix after the third character.
17287 If it is not, fail. Otherwise, undo the edits to the current
17288 line of input and proceed as for case CE. */
17290 static const struct asm_opcode
*
17291 opcode_lookup (char **str
)
17295 const struct asm_opcode
*opcode
;
17296 const struct asm_cond
*cond
;
17299 /* Scan up to the end of the mnemonic, which must end in white space,
17300 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17301 for (base
= end
= *str
; *end
!= '\0'; end
++)
17302 if (*end
== ' ' || *end
== '.')
17308 /* Handle a possible width suffix and/or Neon type suffix. */
17313 /* The .w and .n suffixes are only valid if the unified syntax is in
17315 if (unified_syntax
&& end
[1] == 'w')
17317 else if (unified_syntax
&& end
[1] == 'n')
17322 inst
.vectype
.elems
= 0;
17324 *str
= end
+ offset
;
17326 if (end
[offset
] == '.')
17328 /* See if we have a Neon type suffix (possible in either unified or
17329 non-unified ARM syntax mode). */
17330 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17333 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17339 /* Look for unaffixed or special-case affixed mnemonic. */
17340 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17345 if (opcode
->tag
< OT_odd_infix_0
)
17347 inst
.cond
= COND_ALWAYS
;
17351 if (warn_on_deprecated
&& unified_syntax
)
17352 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17353 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17354 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17357 inst
.cond
= cond
->value
;
17361 /* Cannot have a conditional suffix on a mnemonic of less than two
17363 if (end
- base
< 3)
17366 /* Look for suffixed mnemonic. */
17368 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17369 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17371 if (opcode
&& cond
)
17374 switch (opcode
->tag
)
17376 case OT_cinfix3_legacy
:
17377 /* Ignore conditional suffixes matched on infix only mnemonics. */
17381 case OT_cinfix3_deprecated
:
17382 case OT_odd_infix_unc
:
17383 if (!unified_syntax
)
17385 /* else fall through */
17389 case OT_csuf_or_in3
:
17390 inst
.cond
= cond
->value
;
17393 case OT_unconditional
:
17394 case OT_unconditionalF
:
17396 inst
.cond
= cond
->value
;
17399 /* Delayed diagnostic. */
17400 inst
.error
= BAD_COND
;
17401 inst
.cond
= COND_ALWAYS
;
17410 /* Cannot have a usual-position infix on a mnemonic of less than
17411 six characters (five would be a suffix). */
17412 if (end
- base
< 6)
17415 /* Look for infixed mnemonic in the usual position. */
17417 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17421 memcpy (save
, affix
, 2);
17422 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17423 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17425 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17426 memcpy (affix
, save
, 2);
17429 && (opcode
->tag
== OT_cinfix3
17430 || opcode
->tag
== OT_cinfix3_deprecated
17431 || opcode
->tag
== OT_csuf_or_in3
17432 || opcode
->tag
== OT_cinfix3_legacy
))
17435 if (warn_on_deprecated
&& unified_syntax
17436 && (opcode
->tag
== OT_cinfix3
17437 || opcode
->tag
== OT_cinfix3_deprecated
))
17438 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17440 inst
.cond
= cond
->value
;
17447 /* This function generates an initial IT instruction, leaving its block
17448 virtually open for the new instructions. Eventually,
17449 the mask will be updated by now_it_add_mask () each time
17450 a new instruction needs to be included in the IT block.
17451 Finally, the block is closed with close_automatic_it_block ().
17452 The block closure can be requested either from md_assemble (),
17453 a tencode (), or due to a label hook. */
17456 new_automatic_it_block (int cond
)
17458 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17459 now_it
.mask
= 0x18;
17461 now_it
.block_length
= 1;
17462 mapping_state (MAP_THUMB
);
17463 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17464 now_it
.warn_deprecated
= FALSE
;
17465 now_it
.insn_cond
= TRUE
;
17468 /* Close an automatic IT block.
17469 See comments in new_automatic_it_block (). */
17472 close_automatic_it_block (void)
17474 now_it
.mask
= 0x10;
17475 now_it
.block_length
= 0;
17478 /* Update the mask of the current automatically-generated IT
17479 instruction. See comments in new_automatic_it_block (). */
17482 now_it_add_mask (int cond
)
17484 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17485 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17486 | ((bitvalue) << (nbit)))
17487 const int resulting_bit
= (cond
& 1);
17489 now_it
.mask
&= 0xf;
17490 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17492 (5 - now_it
.block_length
));
17493 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17495 ((5 - now_it
.block_length
) - 1) );
17496 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17499 #undef SET_BIT_VALUE
17502 /* The IT blocks handling machinery is accessed through the these functions:
17503 it_fsm_pre_encode () from md_assemble ()
17504 set_it_insn_type () optional, from the tencode functions
17505 set_it_insn_type_last () ditto
17506 in_it_block () ditto
17507 it_fsm_post_encode () from md_assemble ()
17508 force_automatic_it_block_close () from label habdling functions
17511 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17512 initializing the IT insn type with a generic initial value depending
17513 on the inst.condition.
17514 2) During the tencode function, two things may happen:
17515 a) The tencode function overrides the IT insn type by
17516 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17517 b) The tencode function queries the IT block state by
17518 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17520 Both set_it_insn_type and in_it_block run the internal FSM state
17521 handling function (handle_it_state), because: a) setting the IT insn
17522 type may incur in an invalid state (exiting the function),
17523 and b) querying the state requires the FSM to be updated.
17524 Specifically we want to avoid creating an IT block for conditional
17525 branches, so it_fsm_pre_encode is actually a guess and we can't
17526 determine whether an IT block is required until the tencode () routine
17527 has decided what type of instruction this actually it.
17528 Because of this, if set_it_insn_type and in_it_block have to be used,
17529 set_it_insn_type has to be called first.
17531 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17532 determines the insn IT type depending on the inst.cond code.
17533 When a tencode () routine encodes an instruction that can be
17534 either outside an IT block, or, in the case of being inside, has to be
17535 the last one, set_it_insn_type_last () will determine the proper
17536 IT instruction type based on the inst.cond code. Otherwise,
17537 set_it_insn_type can be called for overriding that logic or
17538 for covering other cases.
17540 Calling handle_it_state () may not transition the IT block state to
17541 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17542 still queried. Instead, if the FSM determines that the state should
17543 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17544 after the tencode () function: that's what it_fsm_post_encode () does.
17546 Since in_it_block () calls the state handling function to get an
17547 updated state, an error may occur (due to invalid insns combination).
17548 In that case, inst.error is set.
17549 Therefore, inst.error has to be checked after the execution of
17550 the tencode () routine.
17552 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17553 any pending state change (if any) that didn't take place in
17554 handle_it_state () as explained above. */
17557 it_fsm_pre_encode (void)
17559 if (inst
.cond
!= COND_ALWAYS
)
17560 inst
.it_insn_type
= INSIDE_IT_INSN
;
17562 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17564 now_it
.state_handled
= 0;
17567 /* IT state FSM handling function. */
17570 handle_it_state (void)
17572 now_it
.state_handled
= 1;
17573 now_it
.insn_cond
= FALSE
;
17575 switch (now_it
.state
)
17577 case OUTSIDE_IT_BLOCK
:
17578 switch (inst
.it_insn_type
)
17580 case OUTSIDE_IT_INSN
:
17583 case INSIDE_IT_INSN
:
17584 case INSIDE_IT_LAST_INSN
:
17585 if (thumb_mode
== 0)
17588 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17589 as_tsktsk (_("Warning: conditional outside an IT block"\
17594 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17595 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17597 /* Automatically generate the IT instruction. */
17598 new_automatic_it_block (inst
.cond
);
17599 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17600 close_automatic_it_block ();
17604 inst
.error
= BAD_OUT_IT
;
17610 case IF_INSIDE_IT_LAST_INSN
:
17611 case NEUTRAL_IT_INSN
:
17615 now_it
.state
= MANUAL_IT_BLOCK
;
17616 now_it
.block_length
= 0;
17621 case AUTOMATIC_IT_BLOCK
:
17622 /* Three things may happen now:
17623 a) We should increment current it block size;
17624 b) We should close current it block (closing insn or 4 insns);
17625 c) We should close current it block and start a new one (due
17626 to incompatible conditions or
17627 4 insns-length block reached). */
17629 switch (inst
.it_insn_type
)
17631 case OUTSIDE_IT_INSN
:
17632 /* The closure of the block shall happen immediatelly,
17633 so any in_it_block () call reports the block as closed. */
17634 force_automatic_it_block_close ();
17637 case INSIDE_IT_INSN
:
17638 case INSIDE_IT_LAST_INSN
:
17639 case IF_INSIDE_IT_LAST_INSN
:
17640 now_it
.block_length
++;
17642 if (now_it
.block_length
> 4
17643 || !now_it_compatible (inst
.cond
))
17645 force_automatic_it_block_close ();
17646 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17647 new_automatic_it_block (inst
.cond
);
17651 now_it
.insn_cond
= TRUE
;
17652 now_it_add_mask (inst
.cond
);
17655 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17656 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17657 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17658 close_automatic_it_block ();
17661 case NEUTRAL_IT_INSN
:
17662 now_it
.block_length
++;
17663 now_it
.insn_cond
= TRUE
;
17665 if (now_it
.block_length
> 4)
17666 force_automatic_it_block_close ();
17668 now_it_add_mask (now_it
.cc
& 1);
17672 close_automatic_it_block ();
17673 now_it
.state
= MANUAL_IT_BLOCK
;
17678 case MANUAL_IT_BLOCK
:
17680 /* Check conditional suffixes. */
17681 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17684 now_it
.mask
&= 0x1f;
17685 is_last
= (now_it
.mask
== 0x10);
17686 now_it
.insn_cond
= TRUE
;
17688 switch (inst
.it_insn_type
)
17690 case OUTSIDE_IT_INSN
:
17691 inst
.error
= BAD_NOT_IT
;
17694 case INSIDE_IT_INSN
:
17695 if (cond
!= inst
.cond
)
17697 inst
.error
= BAD_IT_COND
;
17702 case INSIDE_IT_LAST_INSN
:
17703 case IF_INSIDE_IT_LAST_INSN
:
17704 if (cond
!= inst
.cond
)
17706 inst
.error
= BAD_IT_COND
;
17711 inst
.error
= BAD_BRANCH
;
17716 case NEUTRAL_IT_INSN
:
17717 /* The BKPT instruction is unconditional even in an IT block. */
17721 inst
.error
= BAD_IT_IT
;
17731 struct depr_insn_mask
17733 unsigned long pattern
;
17734 unsigned long mask
;
17735 const char* description
;
17738 /* List of 16-bit instruction patterns deprecated in an IT block in
17740 static const struct depr_insn_mask depr_it_insns
[] = {
17741 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17742 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17743 { 0xa000, 0xb800, N_("ADR") },
17744 { 0x4800, 0xf800, N_("Literal loads") },
17745 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17746 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17747 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17748 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17749 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17754 it_fsm_post_encode (void)
17758 if (!now_it
.state_handled
)
17759 handle_it_state ();
17761 if (now_it
.insn_cond
17762 && !now_it
.warn_deprecated
17763 && warn_on_deprecated
17764 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17766 if (inst
.instruction
>= 0x10000)
17768 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17769 "deprecated in ARMv8"));
17770 now_it
.warn_deprecated
= TRUE
;
17774 const struct depr_insn_mask
*p
= depr_it_insns
;
17776 while (p
->mask
!= 0)
17778 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17780 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17781 "of the following class are deprecated in ARMv8: "
17782 "%s"), p
->description
);
17783 now_it
.warn_deprecated
= TRUE
;
17791 if (now_it
.block_length
> 1)
17793 as_tsktsk (_("IT blocks containing more than one conditional "
17794 "instruction are deprecated in ARMv8"));
17795 now_it
.warn_deprecated
= TRUE
;
17799 is_last
= (now_it
.mask
== 0x10);
17802 now_it
.state
= OUTSIDE_IT_BLOCK
;
17808 force_automatic_it_block_close (void)
17810 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17812 close_automatic_it_block ();
17813 now_it
.state
= OUTSIDE_IT_BLOCK
;
17821 if (!now_it
.state_handled
)
17822 handle_it_state ();
17824 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17828 md_assemble (char *str
)
17831 const struct asm_opcode
* opcode
;
17833 /* Align the previous label if needed. */
17834 if (last_label_seen
!= NULL
)
17836 symbol_set_frag (last_label_seen
, frag_now
);
17837 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17838 S_SET_SEGMENT (last_label_seen
, now_seg
);
17841 memset (&inst
, '\0', sizeof (inst
));
17842 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17844 opcode
= opcode_lookup (&p
);
17847 /* It wasn't an instruction, but it might be a register alias of
17848 the form alias .req reg, or a Neon .dn/.qn directive. */
17849 if (! create_register_alias (str
, p
)
17850 && ! create_neon_reg_alias (str
, p
))
17851 as_bad (_("bad instruction `%s'"), str
);
17856 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17857 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17859 /* The value which unconditional instructions should have in place of the
17860 condition field. */
17861 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17865 arm_feature_set variant
;
17867 variant
= cpu_variant
;
17868 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17869 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17870 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17871 /* Check that this instruction is supported for this CPU. */
17872 if (!opcode
->tvariant
17873 || (thumb_mode
== 1
17874 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17876 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17879 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17880 && opcode
->tencode
!= do_t_branch
)
17882 as_bad (_("Thumb does not support conditional execution"));
17886 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17888 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17889 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17890 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17892 /* Two things are addressed here.
17893 1) Implicit require narrow instructions on Thumb-1.
17894 This avoids relaxation accidentally introducing Thumb-2
17896 2) Reject wide instructions in non Thumb-2 cores. */
17897 if (inst
.size_req
== 0)
17899 else if (inst
.size_req
== 4)
17901 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17907 inst
.instruction
= opcode
->tvalue
;
17909 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17911 /* Prepare the it_insn_type for those encodings that don't set
17913 it_fsm_pre_encode ();
17915 opcode
->tencode ();
17917 it_fsm_post_encode ();
17920 if (!(inst
.error
|| inst
.relax
))
17922 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17923 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17924 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17926 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17931 /* Something has gone badly wrong if we try to relax a fixed size
17933 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17935 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17936 *opcode
->tvariant
);
17937 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17938 set those bits when Thumb-2 32-bit instructions are seen. ie.
17939 anything other than bl/blx and v6-M instructions.
17940 The impact of relaxable instructions will be considered later after we
17941 finish all relaxation. */
17942 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17943 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17944 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17945 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17948 check_neon_suffixes
;
17952 mapping_state (MAP_THUMB
);
17955 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17959 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17960 is_bx
= (opcode
->aencode
== do_bx
);
17962 /* Check that this instruction is supported for this CPU. */
17963 if (!(is_bx
&& fix_v4bx
)
17964 && !(opcode
->avariant
&&
17965 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17967 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17972 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17976 inst
.instruction
= opcode
->avalue
;
17977 if (opcode
->tag
== OT_unconditionalF
)
17978 inst
.instruction
|= 0xF << 28;
17980 inst
.instruction
|= inst
.cond
<< 28;
17981 inst
.size
= INSN_SIZE
;
17982 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17984 it_fsm_pre_encode ();
17985 opcode
->aencode ();
17986 it_fsm_post_encode ();
17988 /* Arm mode bx is marked as both v4T and v5 because it's still required
17989 on a hypothetical non-thumb v5 core. */
17991 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17993 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17994 *opcode
->avariant
);
17996 check_neon_suffixes
;
18000 mapping_state (MAP_ARM
);
18005 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18013 check_it_blocks_finished (void)
18018 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18019 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18020 == MANUAL_IT_BLOCK
)
18022 as_warn (_("section '%s' finished with an open IT block."),
18026 if (now_it
.state
== MANUAL_IT_BLOCK
)
18027 as_warn (_("file finished with an open IT block."));
18031 /* Various frobbings of labels and their addresses. */
18034 arm_start_line_hook (void)
18036 last_label_seen
= NULL
;
18040 arm_frob_label (symbolS
* sym
)
18042 last_label_seen
= sym
;
18044 ARM_SET_THUMB (sym
, thumb_mode
);
18046 #if defined OBJ_COFF || defined OBJ_ELF
18047 ARM_SET_INTERWORK (sym
, support_interwork
);
18050 force_automatic_it_block_close ();
18052 /* Note - do not allow local symbols (.Lxxx) to be labelled
18053 as Thumb functions. This is because these labels, whilst
18054 they exist inside Thumb code, are not the entry points for
18055 possible ARM->Thumb calls. Also, these labels can be used
18056 as part of a computed goto or switch statement. eg gcc
18057 can generate code that looks like this:
18059 ldr r2, [pc, .Laaa]
18069 The first instruction loads the address of the jump table.
18070 The second instruction converts a table index into a byte offset.
18071 The third instruction gets the jump address out of the table.
18072 The fourth instruction performs the jump.
18074 If the address stored at .Laaa is that of a symbol which has the
18075 Thumb_Func bit set, then the linker will arrange for this address
18076 to have the bottom bit set, which in turn would mean that the
18077 address computation performed by the third instruction would end
18078 up with the bottom bit set. Since the ARM is capable of unaligned
18079 word loads, the instruction would then load the incorrect address
18080 out of the jump table, and chaos would ensue. */
18081 if (label_is_thumb_function_name
18082 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18083 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18085 /* When the address of a Thumb function is taken the bottom
18086 bit of that address should be set. This will allow
18087 interworking between Arm and Thumb functions to work
18090 THUMB_SET_FUNC (sym
, 1);
18092 label_is_thumb_function_name
= FALSE
;
18095 dwarf2_emit_label (sym
);
18099 arm_data_in_code (void)
18101 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18103 *input_line_pointer
= '/';
18104 input_line_pointer
+= 5;
18105 *input_line_pointer
= 0;
18113 arm_canonicalize_symbol_name (char * name
)
18117 if (thumb_mode
&& (len
= strlen (name
)) > 5
18118 && streq (name
+ len
- 5, "/data"))
18119 *(name
+ len
- 5) = 0;
18124 /* Table of all register names defined by default. The user can
18125 define additional names with .req. Note that all register names
18126 should appear in both upper and lowercase variants. Some registers
18127 also have mixed-case names. */
18129 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18130 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18131 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18132 #define REGSET(p,t) \
18133 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18134 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18135 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18136 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18137 #define REGSETH(p,t) \
18138 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18139 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18140 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18141 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18142 #define REGSET2(p,t) \
18143 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18144 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18145 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18146 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18147 #define SPLRBANK(base,bank,t) \
18148 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18149 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18150 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18151 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18152 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18153 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18155 static const struct reg_entry reg_names
[] =
18157 /* ARM integer registers. */
18158 REGSET(r
, RN
), REGSET(R
, RN
),
18160 /* ATPCS synonyms. */
18161 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18162 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18163 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18165 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18166 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18167 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18169 /* Well-known aliases. */
18170 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18171 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18173 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18174 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18176 /* Coprocessor numbers. */
18177 REGSET(p
, CP
), REGSET(P
, CP
),
18179 /* Coprocessor register numbers. The "cr" variants are for backward
18181 REGSET(c
, CN
), REGSET(C
, CN
),
18182 REGSET(cr
, CN
), REGSET(CR
, CN
),
18184 /* ARM banked registers. */
18185 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18186 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18187 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18188 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18189 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18190 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18191 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18193 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18194 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18195 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18196 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18197 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18198 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18199 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18200 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18202 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18203 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18204 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18205 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18206 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18207 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18208 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18209 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18210 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18212 /* FPA registers. */
18213 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18214 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18216 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18217 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18219 /* VFP SP registers. */
18220 REGSET(s
,VFS
), REGSET(S
,VFS
),
18221 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18223 /* VFP DP Registers. */
18224 REGSET(d
,VFD
), REGSET(D
,VFD
),
18225 /* Extra Neon DP registers. */
18226 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18228 /* Neon QP registers. */
18229 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18231 /* VFP control registers. */
18232 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18233 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18234 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18235 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18236 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18237 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18239 /* Maverick DSP coprocessor registers. */
18240 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18241 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18243 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18244 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18245 REGDEF(dspsc
,0,DSPSC
),
18247 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18248 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18249 REGDEF(DSPSC
,0,DSPSC
),
18251 /* iWMMXt data registers - p0, c0-15. */
18252 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18254 /* iWMMXt control registers - p1, c0-3. */
18255 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18256 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18257 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18258 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18260 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18261 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18262 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18263 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18264 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18266 /* XScale accumulator registers. */
18267 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18273 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18274 within psr_required_here. */
18275 static const struct asm_psr psrs
[] =
18277 /* Backward compatibility notation. Note that "all" is no longer
18278 truly all possible PSR bits. */
18279 {"all", PSR_c
| PSR_f
},
18283 /* Individual flags. */
18289 /* Combinations of flags. */
18290 {"fs", PSR_f
| PSR_s
},
18291 {"fx", PSR_f
| PSR_x
},
18292 {"fc", PSR_f
| PSR_c
},
18293 {"sf", PSR_s
| PSR_f
},
18294 {"sx", PSR_s
| PSR_x
},
18295 {"sc", PSR_s
| PSR_c
},
18296 {"xf", PSR_x
| PSR_f
},
18297 {"xs", PSR_x
| PSR_s
},
18298 {"xc", PSR_x
| PSR_c
},
18299 {"cf", PSR_c
| PSR_f
},
18300 {"cs", PSR_c
| PSR_s
},
18301 {"cx", PSR_c
| PSR_x
},
18302 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18303 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18304 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18305 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18306 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18307 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18308 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18309 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18310 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18311 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18312 {"scf", PSR_s
| PSR_c
| PSR_f
},
18313 {"scx", PSR_s
| PSR_c
| PSR_x
},
18314 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18315 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18316 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18317 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18318 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18319 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18320 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18321 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18322 {"csf", PSR_c
| PSR_s
| PSR_f
},
18323 {"csx", PSR_c
| PSR_s
| PSR_x
},
18324 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18325 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18326 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18327 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18328 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18329 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18330 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18331 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18332 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18333 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18334 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18335 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18336 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18337 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18338 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18339 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18340 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18341 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18342 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18343 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18344 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18345 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18346 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18347 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18348 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18349 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18352 /* Table of V7M psr names. */
18353 static const struct asm_psr v7m_psrs
[] =
18355 {"apsr", 0 }, {"APSR", 0 },
18356 {"iapsr", 1 }, {"IAPSR", 1 },
18357 {"eapsr", 2 }, {"EAPSR", 2 },
18358 {"psr", 3 }, {"PSR", 3 },
18359 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18360 {"ipsr", 5 }, {"IPSR", 5 },
18361 {"epsr", 6 }, {"EPSR", 6 },
18362 {"iepsr", 7 }, {"IEPSR", 7 },
18363 {"msp", 8 }, {"MSP", 8 },
18364 {"psp", 9 }, {"PSP", 9 },
18365 {"primask", 16}, {"PRIMASK", 16},
18366 {"basepri", 17}, {"BASEPRI", 17},
18367 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18368 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18369 {"faultmask", 19}, {"FAULTMASK", 19},
18370 {"control", 20}, {"CONTROL", 20}
18373 /* Table of all shift-in-operand names. */
18374 static const struct asm_shift_name shift_names
[] =
18376 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18377 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18378 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18379 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18380 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18381 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18384 /* Table of all explicit relocation names. */
18386 static struct reloc_entry reloc_names
[] =
18388 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18389 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18390 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18391 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18392 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18393 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18394 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18395 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18396 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18397 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18398 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18399 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18400 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18401 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18402 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18403 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18404 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18405 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18409 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18410 static const struct asm_cond conds
[] =
18414 {"cs", 0x2}, {"hs", 0x2},
18415 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18429 #define UL_BARRIER(L,U,CODE,FEAT) \
18430 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18431 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18433 static struct asm_barrier_opt barrier_opt_names
[] =
18435 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18436 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18437 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18438 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18439 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18440 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18441 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18442 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18443 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18444 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18445 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18446 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18447 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18448 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18449 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18450 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18455 /* Table of ARM-format instructions. */
18457 /* Macros for gluing together operand strings. N.B. In all cases
18458 other than OPS0, the trailing OP_stop comes from default
18459 zero-initialization of the unspecified elements of the array. */
18460 #define OPS0() { OP_stop, }
18461 #define OPS1(a) { OP_##a, }
18462 #define OPS2(a,b) { OP_##a,OP_##b, }
18463 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18464 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18465 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18466 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18468 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18469 This is useful when mixing operands for ARM and THUMB, i.e. using the
18470 MIX_ARM_THUMB_OPERANDS macro.
18471 In order to use these macros, prefix the number of operands with _
18473 #define OPS_1(a) { a, }
18474 #define OPS_2(a,b) { a,b, }
18475 #define OPS_3(a,b,c) { a,b,c, }
18476 #define OPS_4(a,b,c,d) { a,b,c,d, }
18477 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18478 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18480 /* These macros abstract out the exact format of the mnemonic table and
18481 save some repeated characters. */
18483 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18484 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18485 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18486 THUMB_VARIANT, do_##ae, do_##te }
18488 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18489 a T_MNEM_xyz enumerator. */
18490 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18491 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18492 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18493 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18495 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18496 infix after the third character. */
18497 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18498 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18499 THUMB_VARIANT, do_##ae, do_##te }
18500 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18501 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18502 THUMB_VARIANT, do_##ae, do_##te }
18503 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18504 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18505 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18506 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18507 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18508 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18509 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18510 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18512 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18513 field is still 0xE. Many of the Thumb variants can be executed
18514 conditionally, so this is checked separately. */
18515 #define TUE(mnem, op, top, nops, ops, ae, te) \
18516 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18517 THUMB_VARIANT, do_##ae, do_##te }
18519 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18520 Used by mnemonics that have very minimal differences in the encoding for
18521 ARM and Thumb variants and can be handled in a common function. */
18522 #define TUEc(mnem, op, top, nops, ops, en) \
18523 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18524 THUMB_VARIANT, do_##en, do_##en }
18526 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18527 condition code field. */
18528 #define TUF(mnem, op, top, nops, ops, ae, te) \
18529 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18530 THUMB_VARIANT, do_##ae, do_##te }
18532 /* ARM-only variants of all the above. */
18533 #define CE(mnem, op, nops, ops, ae) \
18534 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18536 #define C3(mnem, op, nops, ops, ae) \
18537 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18539 /* Legacy mnemonics that always have conditional infix after the third
18541 #define CL(mnem, op, nops, ops, ae) \
18542 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18543 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18545 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18546 #define cCE(mnem, op, nops, ops, ae) \
18547 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18549 /* Legacy coprocessor instructions where conditional infix and conditional
18550 suffix are ambiguous. For consistency this includes all FPA instructions,
18551 not just the potentially ambiguous ones. */
18552 #define cCL(mnem, op, nops, ops, ae) \
18553 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18554 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18556 /* Coprocessor, takes either a suffix or a position-3 infix
18557 (for an FPA corner case). */
18558 #define C3E(mnem, op, nops, ops, ae) \
18559 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18560 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18562 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18563 { m1 #m2 m3, OPS##nops ops, \
18564 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18565 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18567 #define CM(m1, m2, op, nops, ops, ae) \
18568 xCM_ (m1, , m2, op, nops, ops, ae), \
18569 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18570 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18571 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18572 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18573 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18574 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18575 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18576 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18577 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18578 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18579 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18580 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18581 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18582 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18583 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18584 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18585 xCM_ (m1, le, m2, op, nops, ops, ae), \
18586 xCM_ (m1, al, m2, op, nops, ops, ae)
18588 #define UE(mnem, op, nops, ops, ae) \
18589 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18591 #define UF(mnem, op, nops, ops, ae) \
18592 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18594 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18595 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18596 use the same encoding function for each. */
18597 #define NUF(mnem, op, nops, ops, enc) \
18598 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18599 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18601 /* Neon data processing, version which indirects through neon_enc_tab for
18602 the various overloaded versions of opcodes. */
18603 #define nUF(mnem, op, nops, ops, enc) \
18604 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18605 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18607 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18609 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18610 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18611 THUMB_VARIANT, do_##enc, do_##enc }
18613 #define NCE(mnem, op, nops, ops, enc) \
18614 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18616 #define NCEF(mnem, op, nops, ops, enc) \
18617 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18619 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18620 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18621 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18622 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18624 #define nCE(mnem, op, nops, ops, enc) \
18625 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18627 #define nCEF(mnem, op, nops, ops, enc) \
18628 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18632 static const struct asm_opcode insns
[] =
18634 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18635 #define THUMB_VARIANT & arm_ext_v4t
18636 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18637 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18638 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18639 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18640 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18641 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18642 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18643 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18644 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18645 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18646 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18647 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18648 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18649 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18650 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18651 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18653 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18654 for setting PSR flag bits. They are obsolete in V6 and do not
18655 have Thumb equivalents. */
18656 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18657 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18658 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18659 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18660 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18661 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18662 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18663 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18664 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18666 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18667 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18668 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18669 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18671 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18672 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18673 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18675 OP_ADDRGLDR
),ldst
, t_ldst
),
18676 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18678 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18679 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18680 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18681 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18682 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18683 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18685 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18686 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18687 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18688 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18691 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18692 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18693 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18694 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18696 /* Thumb-compatibility pseudo ops. */
18697 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18698 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18699 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18700 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18701 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18702 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18703 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18704 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18705 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18706 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18707 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18708 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18710 /* These may simplify to neg. */
18711 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18712 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18714 #undef THUMB_VARIANT
18715 #define THUMB_VARIANT & arm_ext_v6
18717 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18719 /* V1 instructions with no Thumb analogue prior to V6T2. */
18720 #undef THUMB_VARIANT
18721 #define THUMB_VARIANT & arm_ext_v6t2
18723 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18724 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18725 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18727 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18728 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18729 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18730 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18732 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18733 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18735 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18736 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18738 /* V1 instructions with no Thumb analogue at all. */
18739 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18740 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18742 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18743 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18744 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18745 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18746 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18747 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18748 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18749 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18752 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18753 #undef THUMB_VARIANT
18754 #define THUMB_VARIANT & arm_ext_v4t
18756 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18757 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18759 #undef THUMB_VARIANT
18760 #define THUMB_VARIANT & arm_ext_v6t2
18762 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18763 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18765 /* Generic coprocessor instructions. */
18766 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18767 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18768 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18769 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18770 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18771 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18772 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18775 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18777 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18778 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18781 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18782 #undef THUMB_VARIANT
18783 #define THUMB_VARIANT & arm_ext_msr
18785 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18786 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18789 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18790 #undef THUMB_VARIANT
18791 #define THUMB_VARIANT & arm_ext_v6t2
18793 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18794 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18795 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18796 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18797 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18798 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18799 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18800 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18803 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18804 #undef THUMB_VARIANT
18805 #define THUMB_VARIANT & arm_ext_v4t
18807 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18808 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18809 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18810 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18811 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18812 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18815 #define ARM_VARIANT & arm_ext_v4t_5
18817 /* ARM Architecture 4T. */
18818 /* Note: bx (and blx) are required on V5, even if the processor does
18819 not support Thumb. */
18820 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18823 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18824 #undef THUMB_VARIANT
18825 #define THUMB_VARIANT & arm_ext_v5t
18827 /* Note: blx has 2 variants; the .value coded here is for
18828 BLX(2). Only this variant has conditional execution. */
18829 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18830 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18832 #undef THUMB_VARIANT
18833 #define THUMB_VARIANT & arm_ext_v6t2
18835 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18836 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18837 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18838 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18839 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18840 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18841 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18842 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18845 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18846 #undef THUMB_VARIANT
18847 #define THUMB_VARIANT & arm_ext_v5exp
18849 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18850 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18851 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18852 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18854 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18855 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18857 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18858 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18859 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18860 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18862 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18863 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18864 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18865 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18867 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18868 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18870 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18871 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18872 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18873 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18876 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18877 #undef THUMB_VARIANT
18878 #define THUMB_VARIANT & arm_ext_v6t2
18880 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18881 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18883 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18884 ADDRGLDRS
), ldrd
, t_ldstd
),
18886 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18887 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18890 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18892 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18895 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18896 #undef THUMB_VARIANT
18897 #define THUMB_VARIANT & arm_ext_v6
18899 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18900 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18901 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18902 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18903 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18904 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18905 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18906 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18907 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18908 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18910 #undef THUMB_VARIANT
18911 #define THUMB_VARIANT & arm_ext_v6t2
18913 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18914 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18916 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18917 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18919 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18920 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18922 /* ARM V6 not included in V7M. */
18923 #undef THUMB_VARIANT
18924 #define THUMB_VARIANT & arm_ext_v6_notm
18925 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18926 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18927 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18928 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18929 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18930 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18931 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18932 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18933 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18934 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18935 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18936 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18937 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18938 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18939 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18940 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18941 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18942 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18944 /* ARM V6 not included in V7M (eg. integer SIMD). */
18945 #undef THUMB_VARIANT
18946 #define THUMB_VARIANT & arm_ext_v6_dsp
18947 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18948 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18949 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18950 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18951 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18952 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 /* Old name for QASX. */
18954 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18955 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18956 /* Old name for QSAX. */
18957 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18958 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18959 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18960 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18961 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18963 /* Old name for SASX. */
18964 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18965 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18966 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18967 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18968 /* Old name for SHASX. */
18969 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18970 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18971 /* Old name for SHSAX. */
18972 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18973 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18974 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18975 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18976 /* Old name for SSAX. */
18977 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18978 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18979 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18980 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18981 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18982 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18983 /* Old name for UASX. */
18984 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18985 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18986 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18987 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18988 /* Old name for UHASX. */
18989 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18990 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18991 /* Old name for UHSAX. */
18992 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18993 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18994 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18995 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18996 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18997 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18998 /* Old name for UQASX. */
18999 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19000 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19001 /* Old name for UQSAX. */
19002 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19003 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19004 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19005 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19006 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19007 /* Old name for USAX. */
19008 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19009 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19010 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19011 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19012 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19013 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19014 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19015 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19016 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19017 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19018 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19019 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19020 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19021 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19022 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19023 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19024 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19025 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19026 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19027 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19028 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19029 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19030 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19031 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19032 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19033 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19034 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19035 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19036 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19037 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19038 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19039 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19040 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19041 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19044 #define ARM_VARIANT & arm_ext_v6k
19045 #undef THUMB_VARIANT
19046 #define THUMB_VARIANT & arm_ext_v6k
19048 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19049 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19050 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19051 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19053 #undef THUMB_VARIANT
19054 #define THUMB_VARIANT & arm_ext_v6_notm
19055 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19057 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19058 RRnpcb
), strexd
, t_strexd
),
19060 #undef THUMB_VARIANT
19061 #define THUMB_VARIANT & arm_ext_v6t2
19062 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19064 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19066 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19068 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19070 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19073 #define ARM_VARIANT & arm_ext_sec
19074 #undef THUMB_VARIANT
19075 #define THUMB_VARIANT & arm_ext_sec
19077 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19080 #define ARM_VARIANT & arm_ext_virt
19081 #undef THUMB_VARIANT
19082 #define THUMB_VARIANT & arm_ext_virt
19084 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19085 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19088 #define ARM_VARIANT & arm_ext_pan
19089 #undef THUMB_VARIANT
19090 #define THUMB_VARIANT & arm_ext_pan
19092 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19095 #define ARM_VARIANT & arm_ext_v6t2
19096 #undef THUMB_VARIANT
19097 #define THUMB_VARIANT & arm_ext_v6t2
19099 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19100 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19101 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19102 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19104 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19105 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19106 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19107 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19109 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19110 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19111 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19112 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19114 /* Thumb-only instructions. */
19116 #define ARM_VARIANT NULL
19117 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19118 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19120 /* ARM does not really have an IT instruction, so always allow it.
19121 The opcode is copied from Thumb in order to allow warnings in
19122 -mimplicit-it=[never | arm] modes. */
19124 #define ARM_VARIANT & arm_ext_v1
19126 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19127 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19128 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19129 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19130 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19131 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19132 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19133 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19134 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19135 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19136 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19137 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19138 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19139 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19140 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19141 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19142 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19143 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19145 /* Thumb2 only instructions. */
19147 #define ARM_VARIANT NULL
19149 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19150 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19151 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19152 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19153 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19154 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19156 /* Hardware division instructions. */
19158 #define ARM_VARIANT & arm_ext_adiv
19159 #undef THUMB_VARIANT
19160 #define THUMB_VARIANT & arm_ext_div
19162 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19163 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19165 /* ARM V6M/V7 instructions. */
19167 #define ARM_VARIANT & arm_ext_barrier
19168 #undef THUMB_VARIANT
19169 #define THUMB_VARIANT & arm_ext_barrier
19171 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19172 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19173 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19175 /* ARM V7 instructions. */
19177 #define ARM_VARIANT & arm_ext_v7
19178 #undef THUMB_VARIANT
19179 #define THUMB_VARIANT & arm_ext_v7
19181 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19182 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19185 #define ARM_VARIANT & arm_ext_mp
19186 #undef THUMB_VARIANT
19187 #define THUMB_VARIANT & arm_ext_mp
19189 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19191 /* AArchv8 instructions. */
19193 #define ARM_VARIANT & arm_ext_v8
19194 #undef THUMB_VARIANT
19195 #define THUMB_VARIANT & arm_ext_v8
19197 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19198 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19199 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19200 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19202 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19203 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19204 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19206 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19208 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19210 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19212 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19213 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19214 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19215 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19216 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19217 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19219 /* ARMv8 T32 only. */
19221 #define ARM_VARIANT NULL
19222 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19223 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19224 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19226 /* FP for ARMv8. */
19228 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19229 #undef THUMB_VARIANT
19230 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19232 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19233 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19234 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19235 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19236 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19237 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19238 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19239 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19240 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19241 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19242 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19243 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19244 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19245 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19246 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19247 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19248 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19250 /* Crypto v1 extensions. */
19252 #define ARM_VARIANT & fpu_crypto_ext_armv8
19253 #undef THUMB_VARIANT
19254 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19256 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19257 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19258 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19259 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19260 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19261 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19262 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19263 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19264 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19265 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19266 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19267 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19268 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19269 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19272 #define ARM_VARIANT & crc_ext_armv8
19273 #undef THUMB_VARIANT
19274 #define THUMB_VARIANT & crc_ext_armv8
19275 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19276 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19277 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19278 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19279 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19280 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19283 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19284 #undef THUMB_VARIANT
19285 #define THUMB_VARIANT NULL
19287 cCE("wfs", e200110
, 1, (RR
), rd
),
19288 cCE("rfs", e300110
, 1, (RR
), rd
),
19289 cCE("wfc", e400110
, 1, (RR
), rd
),
19290 cCE("rfc", e500110
, 1, (RR
), rd
),
19292 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19293 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19294 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19295 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19297 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19298 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19299 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19300 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19302 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19454 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19455 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19456 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19458 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19459 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19460 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19461 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19462 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19463 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19464 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19465 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19466 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19467 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19468 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19469 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19471 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19472 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19473 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19474 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19475 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19476 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19477 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19478 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19479 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19480 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19481 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19482 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19484 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19485 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19486 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19487 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19488 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19489 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19490 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19491 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19492 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19493 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19494 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19495 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19497 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19498 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19499 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19500 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19501 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19502 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19503 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19504 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19505 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19506 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19507 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19508 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19510 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19623 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19624 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19625 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19627 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19628 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19629 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19630 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19631 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19632 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19633 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19634 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19635 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19636 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19637 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19638 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19640 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19641 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19642 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19643 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19644 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19645 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19646 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19647 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19648 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19649 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19650 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19651 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19653 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19654 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19655 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19656 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19657 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19658 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19659 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19660 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19661 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19662 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19663 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19664 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19666 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19667 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19668 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19669 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19670 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19671 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19672 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19673 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19674 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19675 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19676 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19677 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19679 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19680 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19681 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19682 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19684 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19685 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19686 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19687 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19688 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19689 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19690 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19691 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19692 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19693 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19694 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19695 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19697 /* The implementation of the FIX instruction is broken on some
19698 assemblers, in that it accepts a precision specifier as well as a
19699 rounding specifier, despite the fact that this is meaningless.
19700 To be more compatible, we accept it as well, though of course it
19701 does not set any bits. */
19702 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19703 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19704 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19705 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19706 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19707 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19708 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19709 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19710 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19711 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19712 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19713 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19714 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19716 /* Instructions that were new with the real FPA, call them V2. */
19718 #define ARM_VARIANT & fpu_fpa_ext_v2
19720 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19721 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19722 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19723 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19724 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19725 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19728 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19730 /* Moves and type conversions. */
19731 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19732 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19733 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19734 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19735 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19736 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19737 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19738 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19739 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19740 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19741 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19742 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19743 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19744 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19746 /* Memory operations. */
19747 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19748 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19749 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19750 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19751 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19752 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19753 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19754 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19755 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19756 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19757 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19758 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19759 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19760 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19761 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19762 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19763 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19764 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19766 /* Monadic operations. */
19767 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19768 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19769 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19771 /* Dyadic operations. */
19772 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19773 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19774 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19775 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19776 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19777 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19778 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19779 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19780 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19783 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19784 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19785 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19786 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19788 /* Double precision load/store are still present on single precision
19789 implementations. */
19790 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19791 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19792 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19793 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19794 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19795 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19796 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19797 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19798 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19799 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19802 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19804 /* Moves and type conversions. */
19805 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19806 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19807 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19808 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19809 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19810 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19811 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19812 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19813 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19814 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19815 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19816 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19817 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19819 /* Monadic operations. */
19820 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19821 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19822 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19824 /* Dyadic operations. */
19825 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19826 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19827 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19828 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19829 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19830 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19831 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19832 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19833 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19836 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19837 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19838 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19839 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19842 #define ARM_VARIANT & fpu_vfp_ext_v2
19844 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19845 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19846 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19847 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19849 /* Instructions which may belong to either the Neon or VFP instruction sets.
19850 Individual encoder functions perform additional architecture checks. */
19852 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19853 #undef THUMB_VARIANT
19854 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19856 /* These mnemonics are unique to VFP. */
19857 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19858 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19859 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19860 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19861 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19862 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19863 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19864 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19865 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19866 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19868 /* Mnemonics shared by Neon and VFP. */
19869 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19870 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19871 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19873 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19874 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19876 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19877 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19879 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19880 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19881 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19882 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19883 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19884 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19885 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19886 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19888 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19889 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19890 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19891 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19894 /* NOTE: All VMOV encoding is special-cased! */
19895 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19896 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19898 #undef THUMB_VARIANT
19899 #define THUMB_VARIANT & fpu_neon_ext_v1
19901 #define ARM_VARIANT & fpu_neon_ext_v1
19903 /* Data processing with three registers of the same length. */
19904 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19905 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19906 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19907 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19908 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19909 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19910 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19911 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19912 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19913 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19914 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19915 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19916 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19917 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19918 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19919 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19920 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19921 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19922 /* If not immediate, fall back to neon_dyadic_i64_su.
19923 shl_imm should accept I8 I16 I32 I64,
19924 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19925 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19926 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19927 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19928 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19929 /* Logic ops, types optional & ignored. */
19930 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19931 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19932 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19933 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19934 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19935 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19936 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19937 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19938 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19939 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19940 /* Bitfield ops, untyped. */
19941 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19942 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19943 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19944 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19945 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19946 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19947 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19948 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19949 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19950 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19951 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19952 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19953 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19954 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19955 back to neon_dyadic_if_su. */
19956 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19957 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19958 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19959 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19960 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19961 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19962 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19963 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19964 /* Comparison. Type I8 I16 I32 F32. */
19965 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19966 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19967 /* As above, D registers only. */
19968 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19969 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19970 /* Int and float variants, signedness unimportant. */
19971 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19972 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19973 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19974 /* Add/sub take types I8 I16 I32 I64 F32. */
19975 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19976 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19977 /* vtst takes sizes 8, 16, 32. */
19978 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19979 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19980 /* VMUL takes I8 I16 I32 F32 P8. */
19981 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19982 /* VQD{R}MULH takes S16 S32. */
19983 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19984 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19985 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19986 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19987 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19988 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19989 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19990 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19991 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19992 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19993 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19994 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19995 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19996 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19997 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19998 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19999 /* ARM v8.1 extension. */
20000 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20001 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20002 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20003 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20005 /* Two address, int/float. Types S8 S16 S32 F32. */
20006 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20007 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20009 /* Data processing with two registers and a shift amount. */
20010 /* Right shifts, and variants with rounding.
20011 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20012 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20013 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20014 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20015 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20016 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20017 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20018 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20019 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20020 /* Shift and insert. Sizes accepted 8 16 32 64. */
20021 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20022 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20023 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20024 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20025 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20026 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20027 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20028 /* Right shift immediate, saturating & narrowing, with rounding variants.
20029 Types accepted S16 S32 S64 U16 U32 U64. */
20030 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20031 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20032 /* As above, unsigned. Types accepted S16 S32 S64. */
20033 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20034 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20035 /* Right shift narrowing. Types accepted I16 I32 I64. */
20036 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20037 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20038 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20039 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20040 /* CVT with optional immediate for fixed-point variant. */
20041 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20043 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20044 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20046 /* Data processing, three registers of different lengths. */
20047 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20048 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20049 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20050 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20051 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20052 /* If not scalar, fall back to neon_dyadic_long.
20053 Vector types as above, scalar types S16 S32 U16 U32. */
20054 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20055 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20056 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20057 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20058 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20059 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20060 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20061 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20062 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20063 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20064 /* Saturating doubling multiplies. Types S16 S32. */
20065 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20066 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20067 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20068 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20069 S16 S32 U16 U32. */
20070 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20072 /* Extract. Size 8. */
20073 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20074 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20076 /* Two registers, miscellaneous. */
20077 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20078 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20079 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20080 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20081 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20082 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20083 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20084 /* Vector replicate. Sizes 8 16 32. */
20085 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20086 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20087 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20088 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20089 /* VMOVN. Types I16 I32 I64. */
20090 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20091 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20092 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20093 /* VQMOVUN. Types S16 S32 S64. */
20094 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20095 /* VZIP / VUZP. Sizes 8 16 32. */
20096 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20097 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20098 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20099 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20100 /* VQABS / VQNEG. Types S8 S16 S32. */
20101 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20102 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20103 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20104 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20105 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20106 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20107 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20108 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20109 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20110 /* Reciprocal estimates. Types U32 F32. */
20111 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20112 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20113 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20114 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20115 /* VCLS. Types S8 S16 S32. */
20116 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20117 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20118 /* VCLZ. Types I8 I16 I32. */
20119 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20120 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20121 /* VCNT. Size 8. */
20122 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20123 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20124 /* Two address, untyped. */
20125 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20126 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20127 /* VTRN. Sizes 8 16 32. */
20128 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20129 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20131 /* Table lookup. Size 8. */
20132 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20133 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20135 #undef THUMB_VARIANT
20136 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20138 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20140 /* Neon element/structure load/store. */
20141 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20142 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20143 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20144 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20145 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20146 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20147 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20148 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20150 #undef THUMB_VARIANT
20151 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20153 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20154 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20155 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20156 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20157 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20158 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20159 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20160 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20161 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20162 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20164 #undef THUMB_VARIANT
20165 #define THUMB_VARIANT & fpu_vfp_ext_v3
20167 #define ARM_VARIANT & fpu_vfp_ext_v3
20169 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20170 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20171 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20172 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20173 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20174 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20175 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20176 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20177 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20180 #define ARM_VARIANT & fpu_vfp_ext_fma
20181 #undef THUMB_VARIANT
20182 #define THUMB_VARIANT & fpu_vfp_ext_fma
20183 /* Mnemonics shared by Neon and VFP. These are included in the
20184 VFP FMA variant; NEON and VFP FMA always includes the NEON
20185 FMA instructions. */
20186 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20187 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20188 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20189 the v form should always be used. */
20190 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20191 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20192 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20193 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20194 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20195 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20197 #undef THUMB_VARIANT
20199 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20201 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20202 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20203 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20204 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20205 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20206 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20207 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20208 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20211 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20213 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20214 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20215 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20216 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20217 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20218 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20219 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20220 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20221 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20222 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20223 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20224 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20225 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20226 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20227 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20228 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20229 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20230 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20231 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20232 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20233 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20234 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20235 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20236 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20237 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20238 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20239 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20240 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20241 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20242 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20243 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20244 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20245 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20246 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20247 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20248 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20249 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20250 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20254 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20257 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20258 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20259 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20260 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20261 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20262 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20267 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20268 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20269 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20270 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20271 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20272 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20273 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20274 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20275 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20276 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20277 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20278 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20279 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20280 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20281 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20282 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20283 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20284 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20285 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20286 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20287 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20288 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20289 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20290 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20291 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20292 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20293 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20294 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20295 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20296 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20297 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20298 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20299 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20300 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20301 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20302 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20303 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20304 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20305 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20306 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20307 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20308 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20309 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20310 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20311 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20312 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20313 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20314 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20315 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20316 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20317 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20318 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20319 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20320 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20321 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20322 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20323 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20324 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20325 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20326 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20327 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20328 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20329 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20330 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20331 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20332 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20333 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20334 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20335 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20336 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20337 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20338 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20339 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20340 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20341 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20342 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20343 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20344 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20345 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20346 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20347 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20348 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20351 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20352 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20353 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20354 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20355 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20356 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20357 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20358 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20359 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20360 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20361 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20365 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20366 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20367 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20368 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20369 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20370 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20371 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20377 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20379 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20380 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20381 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20382 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20383 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20384 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20385 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20386 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20387 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20388 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20389 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20390 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20391 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20392 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20393 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20394 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20395 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20396 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20397 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20398 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20399 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20400 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20401 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20402 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20403 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20404 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20405 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20406 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20407 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20408 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20409 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20410 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20411 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20412 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20413 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20414 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20415 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20416 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20417 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20418 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20419 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20420 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20421 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20422 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20423 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20424 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20425 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20426 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20427 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20428 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20429 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20430 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20431 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20432 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20433 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20434 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20435 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20438 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20440 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20441 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20442 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20443 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20444 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20445 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20446 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20447 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20448 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20449 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20450 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20451 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20452 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20453 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20454 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20455 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20456 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20457 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20458 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20459 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20460 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20461 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20462 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20463 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20464 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20465 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20466 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20467 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20468 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20469 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20470 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20471 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20472 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20473 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20474 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20475 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20476 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20477 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20478 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20479 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20480 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20481 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20482 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20483 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20484 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20485 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20486 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20487 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20488 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20489 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20490 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20491 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20492 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20493 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20494 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20495 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20496 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20497 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20498 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20499 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20500 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20501 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20502 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20503 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20504 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20505 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20506 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20507 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20508 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20509 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20510 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20511 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20512 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20513 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20514 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20515 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20518 #undef THUMB_VARIANT
20544 /* MD interface: bits in the object file. */
20546 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20547 for use in the a.out file, and stores them in the array pointed to by buf.
20548 This knows about the endian-ness of the target machine and does
20549 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20550 2 (short) and 4 (long) Floating numbers are put out as a series of
20551 LITTLENUMS (shorts, here at least). */
20554 md_number_to_chars (char * buf
, valueT val
, int n
)
20556 if (target_big_endian
)
20557 number_to_chars_bigendian (buf
, val
, n
);
20559 number_to_chars_littleendian (buf
, val
, n
);
20563 md_chars_to_number (char * buf
, int n
)
20566 unsigned char * where
= (unsigned char *) buf
;
20568 if (target_big_endian
)
20573 result
|= (*where
++ & 255);
20581 result
|= (where
[n
] & 255);
20588 /* MD interface: Sections. */
20590 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20591 that an rs_machine_dependent frag may reach. */
20594 arm_frag_max_var (fragS
*fragp
)
20596 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20597 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20599 Note that we generate relaxable instructions even for cases that don't
20600 really need it, like an immediate that's a trivial constant. So we're
20601 overestimating the instruction size for some of those cases. Rather
20602 than putting more intelligence here, it would probably be better to
20603 avoid generating a relaxation frag in the first place when it can be
20604 determined up front that a short instruction will suffice. */
20606 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20610 /* Estimate the size of a frag before relaxing. Assume everything fits in
20614 md_estimate_size_before_relax (fragS
* fragp
,
20615 segT segtype ATTRIBUTE_UNUSED
)
20621 /* Convert a machine dependent frag. */
20624 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20626 unsigned long insn
;
20627 unsigned long old_op
;
20635 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20637 old_op
= bfd_get_16(abfd
, buf
);
20638 if (fragp
->fr_symbol
)
20640 exp
.X_op
= O_symbol
;
20641 exp
.X_add_symbol
= fragp
->fr_symbol
;
20645 exp
.X_op
= O_constant
;
20647 exp
.X_add_number
= fragp
->fr_offset
;
20648 opcode
= fragp
->fr_subtype
;
20651 case T_MNEM_ldr_pc
:
20652 case T_MNEM_ldr_pc2
:
20653 case T_MNEM_ldr_sp
:
20654 case T_MNEM_str_sp
:
20661 if (fragp
->fr_var
== 4)
20663 insn
= THUMB_OP32 (opcode
);
20664 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20666 insn
|= (old_op
& 0x700) << 4;
20670 insn
|= (old_op
& 7) << 12;
20671 insn
|= (old_op
& 0x38) << 13;
20673 insn
|= 0x00000c00;
20674 put_thumb32_insn (buf
, insn
);
20675 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20679 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20681 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20684 if (fragp
->fr_var
== 4)
20686 insn
= THUMB_OP32 (opcode
);
20687 insn
|= (old_op
& 0xf0) << 4;
20688 put_thumb32_insn (buf
, insn
);
20689 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20693 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20694 exp
.X_add_number
-= 4;
20702 if (fragp
->fr_var
== 4)
20704 int r0off
= (opcode
== T_MNEM_mov
20705 || opcode
== T_MNEM_movs
) ? 0 : 8;
20706 insn
= THUMB_OP32 (opcode
);
20707 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20708 insn
|= (old_op
& 0x700) << r0off
;
20709 put_thumb32_insn (buf
, insn
);
20710 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20714 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20719 if (fragp
->fr_var
== 4)
20721 insn
= THUMB_OP32(opcode
);
20722 put_thumb32_insn (buf
, insn
);
20723 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20726 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20730 if (fragp
->fr_var
== 4)
20732 insn
= THUMB_OP32(opcode
);
20733 insn
|= (old_op
& 0xf00) << 14;
20734 put_thumb32_insn (buf
, insn
);
20735 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20738 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20741 case T_MNEM_add_sp
:
20742 case T_MNEM_add_pc
:
20743 case T_MNEM_inc_sp
:
20744 case T_MNEM_dec_sp
:
20745 if (fragp
->fr_var
== 4)
20747 /* ??? Choose between add and addw. */
20748 insn
= THUMB_OP32 (opcode
);
20749 insn
|= (old_op
& 0xf0) << 4;
20750 put_thumb32_insn (buf
, insn
);
20751 if (opcode
== T_MNEM_add_pc
)
20752 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20754 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20757 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20765 if (fragp
->fr_var
== 4)
20767 insn
= THUMB_OP32 (opcode
);
20768 insn
|= (old_op
& 0xf0) << 4;
20769 insn
|= (old_op
& 0xf) << 16;
20770 put_thumb32_insn (buf
, insn
);
20771 if (insn
& (1 << 20))
20772 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20774 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20777 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20783 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20784 (enum bfd_reloc_code_real
) reloc_type
);
20785 fixp
->fx_file
= fragp
->fr_file
;
20786 fixp
->fx_line
= fragp
->fr_line
;
20787 fragp
->fr_fix
+= fragp
->fr_var
;
20789 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20790 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20791 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20792 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20795 /* Return the size of a relaxable immediate operand instruction.
20796 SHIFT and SIZE specify the form of the allowable immediate. */
20798 relax_immediate (fragS
*fragp
, int size
, int shift
)
20804 /* ??? Should be able to do better than this. */
20805 if (fragp
->fr_symbol
)
20808 low
= (1 << shift
) - 1;
20809 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20810 offset
= fragp
->fr_offset
;
20811 /* Force misaligned offsets to 32-bit variant. */
20814 if (offset
& ~mask
)
20819 /* Get the address of a symbol during relaxation. */
20821 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20827 sym
= fragp
->fr_symbol
;
20828 sym_frag
= symbol_get_frag (sym
);
20829 know (S_GET_SEGMENT (sym
) != absolute_section
20830 || sym_frag
== &zero_address_frag
);
20831 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20833 /* If frag has yet to be reached on this pass, assume it will
20834 move by STRETCH just as we did. If this is not so, it will
20835 be because some frag between grows, and that will force
20839 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20843 /* Adjust stretch for any alignment frag. Note that if have
20844 been expanding the earlier code, the symbol may be
20845 defined in what appears to be an earlier frag. FIXME:
20846 This doesn't handle the fr_subtype field, which specifies
20847 a maximum number of bytes to skip when doing an
20849 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20851 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20854 stretch
= - ((- stretch
)
20855 & ~ ((1 << (int) f
->fr_offset
) - 1));
20857 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20869 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20872 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20877 /* Assume worst case for symbols not known to be in the same section. */
20878 if (fragp
->fr_symbol
== NULL
20879 || !S_IS_DEFINED (fragp
->fr_symbol
)
20880 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20881 || S_IS_WEAK (fragp
->fr_symbol
))
20884 val
= relaxed_symbol_addr (fragp
, stretch
);
20885 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20886 addr
= (addr
+ 4) & ~3;
20887 /* Force misaligned targets to 32-bit variant. */
20891 if (val
< 0 || val
> 1020)
20896 /* Return the size of a relaxable add/sub immediate instruction. */
20898 relax_addsub (fragS
*fragp
, asection
*sec
)
20903 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20904 op
= bfd_get_16(sec
->owner
, buf
);
20905 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20906 return relax_immediate (fragp
, 8, 0);
20908 return relax_immediate (fragp
, 3, 0);
20911 /* Return TRUE iff the definition of symbol S could be pre-empted
20912 (overridden) at link or load time. */
20914 symbol_preemptible (symbolS
*s
)
20916 /* Weak symbols can always be pre-empted. */
20920 /* Non-global symbols cannot be pre-empted. */
20921 if (! S_IS_EXTERNAL (s
))
20925 /* In ELF, a global symbol can be marked protected, or private. In that
20926 case it can't be pre-empted (other definitions in the same link unit
20927 would violate the ODR). */
20928 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20932 /* Other global symbols might be pre-empted. */
20936 /* Return the size of a relaxable branch instruction. BITS is the
20937 size of the offset field in the narrow instruction. */
20940 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20946 /* Assume worst case for symbols not known to be in the same section. */
20947 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20948 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20949 || S_IS_WEAK (fragp
->fr_symbol
))
20953 /* A branch to a function in ARM state will require interworking. */
20954 if (S_IS_DEFINED (fragp
->fr_symbol
)
20955 && ARM_IS_FUNC (fragp
->fr_symbol
))
20959 if (symbol_preemptible (fragp
->fr_symbol
))
20962 val
= relaxed_symbol_addr (fragp
, stretch
);
20963 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20966 /* Offset is a signed value *2 */
20968 if (val
>= limit
|| val
< -limit
)
20974 /* Relax a machine dependent frag. This returns the amount by which
20975 the current size of the frag should change. */
20978 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20983 oldsize
= fragp
->fr_var
;
20984 switch (fragp
->fr_subtype
)
20986 case T_MNEM_ldr_pc2
:
20987 newsize
= relax_adr (fragp
, sec
, stretch
);
20989 case T_MNEM_ldr_pc
:
20990 case T_MNEM_ldr_sp
:
20991 case T_MNEM_str_sp
:
20992 newsize
= relax_immediate (fragp
, 8, 2);
20996 newsize
= relax_immediate (fragp
, 5, 2);
21000 newsize
= relax_immediate (fragp
, 5, 1);
21004 newsize
= relax_immediate (fragp
, 5, 0);
21007 newsize
= relax_adr (fragp
, sec
, stretch
);
21013 newsize
= relax_immediate (fragp
, 8, 0);
21016 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21019 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21021 case T_MNEM_add_sp
:
21022 case T_MNEM_add_pc
:
21023 newsize
= relax_immediate (fragp
, 8, 2);
21025 case T_MNEM_inc_sp
:
21026 case T_MNEM_dec_sp
:
21027 newsize
= relax_immediate (fragp
, 7, 2);
21033 newsize
= relax_addsub (fragp
, sec
);
21039 fragp
->fr_var
= newsize
;
21040 /* Freeze wide instructions that are at or before the same location as
21041 in the previous pass. This avoids infinite loops.
21042 Don't freeze them unconditionally because targets may be artificially
21043 misaligned by the expansion of preceding frags. */
21044 if (stretch
<= 0 && newsize
> 2)
21046 md_convert_frag (sec
->owner
, sec
, fragp
);
21050 return newsize
- oldsize
;
21053 /* Round up a section size to the appropriate boundary. */
21056 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21059 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21060 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21062 /* For a.out, force the section size to be aligned. If we don't do
21063 this, BFD will align it for us, but it will not write out the
21064 final bytes of the section. This may be a bug in BFD, but it is
21065 easier to fix it here since that is how the other a.out targets
21069 align
= bfd_get_section_alignment (stdoutput
, segment
);
21070 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
21077 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21078 of an rs_align_code fragment. */
21081 arm_handle_align (fragS
* fragP
)
21083 static char const arm_noop
[2][2][4] =
21086 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21087 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21090 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21091 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21094 static char const thumb_noop
[2][2][2] =
21097 {0xc0, 0x46}, /* LE */
21098 {0x46, 0xc0}, /* BE */
21101 {0x00, 0xbf}, /* LE */
21102 {0xbf, 0x00} /* BE */
21105 static char const wide_thumb_noop
[2][4] =
21106 { /* Wide Thumb-2 */
21107 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21108 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21111 unsigned bytes
, fix
, noop_size
;
21114 const char *narrow_noop
= NULL
;
21119 if (fragP
->fr_type
!= rs_align_code
)
21122 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21123 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21126 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21127 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21129 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21131 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21133 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21134 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21136 narrow_noop
= thumb_noop
[1][target_big_endian
];
21137 noop
= wide_thumb_noop
[target_big_endian
];
21140 noop
= thumb_noop
[0][target_big_endian
];
21148 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21149 ? selected_cpu
: arm_arch_none
,
21151 [target_big_endian
];
21158 fragP
->fr_var
= noop_size
;
21160 if (bytes
& (noop_size
- 1))
21162 fix
= bytes
& (noop_size
- 1);
21164 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21166 memset (p
, 0, fix
);
21173 if (bytes
& noop_size
)
21175 /* Insert a narrow noop. */
21176 memcpy (p
, narrow_noop
, noop_size
);
21178 bytes
-= noop_size
;
21182 /* Use wide noops for the remainder */
21186 while (bytes
>= noop_size
)
21188 memcpy (p
, noop
, noop_size
);
21190 bytes
-= noop_size
;
21194 fragP
->fr_fix
+= fix
;
21197 /* Called from md_do_align. Used to create an alignment
21198 frag in a code section. */
21201 arm_frag_align_code (int n
, int max
)
21205 /* We assume that there will never be a requirement
21206 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21207 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21212 _("alignments greater than %d bytes not supported in .text sections."),
21213 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21214 as_fatal ("%s", err_msg
);
21217 p
= frag_var (rs_align_code
,
21218 MAX_MEM_FOR_RS_ALIGN_CODE
,
21220 (relax_substateT
) max
,
21227 /* Perform target specific initialisation of a frag.
21228 Note - despite the name this initialisation is not done when the frag
21229 is created, but only when its type is assigned. A frag can be created
21230 and used a long time before its type is set, so beware of assuming that
21231 this initialisationis performed first. */
21235 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21237 /* Record whether this frag is in an ARM or a THUMB area. */
21238 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21241 #else /* OBJ_ELF is defined. */
21243 arm_init_frag (fragS
* fragP
, int max_chars
)
21245 int frag_thumb_mode
;
21247 /* If the current ARM vs THUMB mode has not already
21248 been recorded into this frag then do so now. */
21249 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21250 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21252 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21254 /* Record a mapping symbol for alignment frags. We will delete this
21255 later if the alignment ends up empty. */
21256 switch (fragP
->fr_type
)
21259 case rs_align_test
:
21261 mapping_state_2 (MAP_DATA
, max_chars
);
21263 case rs_align_code
:
21264 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21271 /* When we change sections we need to issue a new mapping symbol. */
21274 arm_elf_change_section (void)
21276 /* Link an unlinked unwind index table section to the .text section. */
21277 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21278 && elf_linked_to_section (now_seg
) == NULL
)
21279 elf_linked_to_section (now_seg
) = text_section
;
21283 arm_elf_section_type (const char * str
, size_t len
)
21285 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21286 return SHT_ARM_EXIDX
;
21291 /* Code to deal with unwinding tables. */
21293 static void add_unwind_adjustsp (offsetT
);
21295 /* Generate any deferred unwind frame offset. */
21298 flush_pending_unwind (void)
21302 offset
= unwind
.pending_offset
;
21303 unwind
.pending_offset
= 0;
21305 add_unwind_adjustsp (offset
);
21308 /* Add an opcode to this list for this function. Two-byte opcodes should
21309 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21313 add_unwind_opcode (valueT op
, int length
)
21315 /* Add any deferred stack adjustment. */
21316 if (unwind
.pending_offset
)
21317 flush_pending_unwind ();
21319 unwind
.sp_restored
= 0;
21321 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21323 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21324 if (unwind
.opcodes
)
21325 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21326 unwind
.opcode_alloc
);
21328 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21333 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21335 unwind
.opcode_count
++;
21339 /* Add unwind opcodes to adjust the stack pointer. */
21342 add_unwind_adjustsp (offsetT offset
)
21346 if (offset
> 0x200)
21348 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21353 /* Long form: 0xb2, uleb128. */
21354 /* This might not fit in a word so add the individual bytes,
21355 remembering the list is built in reverse order. */
21356 o
= (valueT
) ((offset
- 0x204) >> 2);
21358 add_unwind_opcode (0, 1);
21360 /* Calculate the uleb128 encoding of the offset. */
21364 bytes
[n
] = o
& 0x7f;
21370 /* Add the insn. */
21372 add_unwind_opcode (bytes
[n
- 1], 1);
21373 add_unwind_opcode (0xb2, 1);
21375 else if (offset
> 0x100)
21377 /* Two short opcodes. */
21378 add_unwind_opcode (0x3f, 1);
21379 op
= (offset
- 0x104) >> 2;
21380 add_unwind_opcode (op
, 1);
21382 else if (offset
> 0)
21384 /* Short opcode. */
21385 op
= (offset
- 4) >> 2;
21386 add_unwind_opcode (op
, 1);
21388 else if (offset
< 0)
21391 while (offset
> 0x100)
21393 add_unwind_opcode (0x7f, 1);
21396 op
= ((offset
- 4) >> 2) | 0x40;
21397 add_unwind_opcode (op
, 1);
21401 /* Finish the list of unwind opcodes for this function. */
21403 finish_unwind_opcodes (void)
21407 if (unwind
.fp_used
)
21409 /* Adjust sp as necessary. */
21410 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21411 flush_pending_unwind ();
21413 /* After restoring sp from the frame pointer. */
21414 op
= 0x90 | unwind
.fp_reg
;
21415 add_unwind_opcode (op
, 1);
21418 flush_pending_unwind ();
21422 /* Start an exception table entry. If idx is nonzero this is an index table
21426 start_unwind_section (const segT text_seg
, int idx
)
21428 const char * text_name
;
21429 const char * prefix
;
21430 const char * prefix_once
;
21431 const char * group_name
;
21435 size_t sec_name_len
;
21442 prefix
= ELF_STRING_ARM_unwind
;
21443 prefix_once
= ELF_STRING_ARM_unwind_once
;
21444 type
= SHT_ARM_EXIDX
;
21448 prefix
= ELF_STRING_ARM_unwind_info
;
21449 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21450 type
= SHT_PROGBITS
;
21453 text_name
= segment_name (text_seg
);
21454 if (streq (text_name
, ".text"))
21457 if (strncmp (text_name
, ".gnu.linkonce.t.",
21458 strlen (".gnu.linkonce.t.")) == 0)
21460 prefix
= prefix_once
;
21461 text_name
+= strlen (".gnu.linkonce.t.");
21464 prefix_len
= strlen (prefix
);
21465 text_len
= strlen (text_name
);
21466 sec_name_len
= prefix_len
+ text_len
;
21467 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21468 memcpy (sec_name
, prefix
, prefix_len
);
21469 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21470 sec_name
[prefix_len
+ text_len
] = '\0';
21476 /* Handle COMDAT group. */
21477 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21479 group_name
= elf_group_name (text_seg
);
21480 if (group_name
== NULL
)
21482 as_bad (_("Group section `%s' has no group signature"),
21483 segment_name (text_seg
));
21484 ignore_rest_of_line ();
21487 flags
|= SHF_GROUP
;
21491 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21493 /* Set the section link for index tables. */
21495 elf_linked_to_section (now_seg
) = text_seg
;
21499 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21500 personality routine data. Returns zero, or the index table value for
21501 an inline entry. */
21504 create_unwind_entry (int have_data
)
21509 /* The current word of data. */
21511 /* The number of bytes left in this word. */
21514 finish_unwind_opcodes ();
21516 /* Remember the current text section. */
21517 unwind
.saved_seg
= now_seg
;
21518 unwind
.saved_subseg
= now_subseg
;
21520 start_unwind_section (now_seg
, 0);
21522 if (unwind
.personality_routine
== NULL
)
21524 if (unwind
.personality_index
== -2)
21527 as_bad (_("handlerdata in cantunwind frame"));
21528 return 1; /* EXIDX_CANTUNWIND. */
21531 /* Use a default personality routine if none is specified. */
21532 if (unwind
.personality_index
== -1)
21534 if (unwind
.opcode_count
> 3)
21535 unwind
.personality_index
= 1;
21537 unwind
.personality_index
= 0;
21540 /* Space for the personality routine entry. */
21541 if (unwind
.personality_index
== 0)
21543 if (unwind
.opcode_count
> 3)
21544 as_bad (_("too many unwind opcodes for personality routine 0"));
21548 /* All the data is inline in the index table. */
21551 while (unwind
.opcode_count
> 0)
21553 unwind
.opcode_count
--;
21554 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21558 /* Pad with "finish" opcodes. */
21560 data
= (data
<< 8) | 0xb0;
21567 /* We get two opcodes "free" in the first word. */
21568 size
= unwind
.opcode_count
- 2;
21572 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21573 if (unwind
.personality_index
!= -1)
21575 as_bad (_("attempt to recreate an unwind entry"));
21579 /* An extra byte is required for the opcode count. */
21580 size
= unwind
.opcode_count
+ 1;
21583 size
= (size
+ 3) >> 2;
21585 as_bad (_("too many unwind opcodes"));
21587 frag_align (2, 0, 0);
21588 record_alignment (now_seg
, 2);
21589 unwind
.table_entry
= expr_build_dot ();
21591 /* Allocate the table entry. */
21592 ptr
= frag_more ((size
<< 2) + 4);
21593 /* PR 13449: Zero the table entries in case some of them are not used. */
21594 memset (ptr
, 0, (size
<< 2) + 4);
21595 where
= frag_now_fix () - ((size
<< 2) + 4);
21597 switch (unwind
.personality_index
)
21600 /* ??? Should this be a PLT generating relocation? */
21601 /* Custom personality routine. */
21602 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21603 BFD_RELOC_ARM_PREL31
);
21608 /* Set the first byte to the number of additional words. */
21609 data
= size
> 0 ? size
- 1 : 0;
21613 /* ABI defined personality routines. */
21615 /* Three opcodes bytes are packed into the first word. */
21622 /* The size and first two opcode bytes go in the first word. */
21623 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21628 /* Should never happen. */
21632 /* Pack the opcodes into words (MSB first), reversing the list at the same
21634 while (unwind
.opcode_count
> 0)
21638 md_number_to_chars (ptr
, data
, 4);
21643 unwind
.opcode_count
--;
21645 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21648 /* Finish off the last word. */
21651 /* Pad with "finish" opcodes. */
21653 data
= (data
<< 8) | 0xb0;
21655 md_number_to_chars (ptr
, data
, 4);
21660 /* Add an empty descriptor if there is no user-specified data. */
21661 ptr
= frag_more (4);
21662 md_number_to_chars (ptr
, 0, 4);
21669 /* Initialize the DWARF-2 unwind information for this procedure. */
21672 tc_arm_frame_initial_instructions (void)
21674 cfi_add_CFA_def_cfa (REG_SP
, 0);
21676 #endif /* OBJ_ELF */
21678 /* Convert REGNAME to a DWARF-2 register number. */
21681 tc_arm_regname_to_dw2regnum (char *regname
)
21683 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21687 /* PR 16694: Allow VFP registers as well. */
21688 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21692 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21701 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21705 exp
.X_op
= O_secrel
;
21706 exp
.X_add_symbol
= symbol
;
21707 exp
.X_add_number
= 0;
21708 emit_expr (&exp
, size
);
21712 /* MD interface: Symbol and relocation handling. */
21714 /* Return the address within the segment that a PC-relative fixup is
21715 relative to. For ARM, PC-relative fixups applied to instructions
21716 are generally relative to the location of the fixup plus 8 bytes.
21717 Thumb branches are offset by 4, and Thumb loads relative to PC
21718 require special handling. */
21721 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21723 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21725 /* If this is pc-relative and we are going to emit a relocation
21726 then we just want to put out any pipeline compensation that the linker
21727 will need. Otherwise we want to use the calculated base.
21728 For WinCE we skip the bias for externals as well, since this
21729 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21731 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21732 || (arm_force_relocation (fixP
)
21734 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21740 switch (fixP
->fx_r_type
)
21742 /* PC relative addressing on the Thumb is slightly odd as the
21743 bottom two bits of the PC are forced to zero for the
21744 calculation. This happens *after* application of the
21745 pipeline offset. However, Thumb adrl already adjusts for
21746 this, so we need not do it again. */
21747 case BFD_RELOC_ARM_THUMB_ADD
:
21750 case BFD_RELOC_ARM_THUMB_OFFSET
:
21751 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21752 case BFD_RELOC_ARM_T32_ADD_PC12
:
21753 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21754 return (base
+ 4) & ~3;
21756 /* Thumb branches are simply offset by +4. */
21757 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21758 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21759 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21760 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21761 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21764 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21766 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21767 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21768 && ARM_IS_FUNC (fixP
->fx_addsy
)
21769 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21770 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21773 /* BLX is like branches above, but forces the low two bits of PC to
21775 case BFD_RELOC_THUMB_PCREL_BLX
:
21777 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21778 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21779 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21780 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21781 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21782 return (base
+ 4) & ~3;
21784 /* ARM mode branches are offset by +8. However, the Windows CE
21785 loader expects the relocation not to take this into account. */
21786 case BFD_RELOC_ARM_PCREL_BLX
:
21788 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21789 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21790 && ARM_IS_FUNC (fixP
->fx_addsy
)
21791 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21792 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21795 case BFD_RELOC_ARM_PCREL_CALL
:
21797 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21798 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21799 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21800 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21801 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21804 case BFD_RELOC_ARM_PCREL_BRANCH
:
21805 case BFD_RELOC_ARM_PCREL_JUMP
:
21806 case BFD_RELOC_ARM_PLT32
:
21808 /* When handling fixups immediately, because we have already
21809 discovered the value of a symbol, or the address of the frag involved
21810 we must account for the offset by +8, as the OS loader will never see the reloc.
21811 see fixup_segment() in write.c
21812 The S_IS_EXTERNAL test handles the case of global symbols.
21813 Those need the calculated base, not just the pipe compensation the linker will need. */
21815 && fixP
->fx_addsy
!= NULL
21816 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21817 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21825 /* ARM mode loads relative to PC are also offset by +8. Unlike
21826 branches, the Windows CE loader *does* expect the relocation
21827 to take this into account. */
21828 case BFD_RELOC_ARM_OFFSET_IMM
:
21829 case BFD_RELOC_ARM_OFFSET_IMM8
:
21830 case BFD_RELOC_ARM_HWLITERAL
:
21831 case BFD_RELOC_ARM_LITERAL
:
21832 case BFD_RELOC_ARM_CP_OFF_IMM
:
21836 /* Other PC-relative relocations are un-offset. */
21842 static bfd_boolean flag_warn_syms
= TRUE
;
21845 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21847 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21848 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21849 does mean that the resulting code might be very confusing to the reader.
21850 Also this warning can be triggered if the user omits an operand before
21851 an immediate address, eg:
21855 GAS treats this as an assignment of the value of the symbol foo to a
21856 symbol LDR, and so (without this code) it will not issue any kind of
21857 warning or error message.
21859 Note - ARM instructions are case-insensitive but the strings in the hash
21860 table are all stored in lower case, so we must first ensure that name is
21862 if (flag_warn_syms
&& arm_ops_hsh
)
21864 char * nbuf
= strdup (name
);
21867 for (p
= nbuf
; *p
; p
++)
21869 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21871 static struct hash_control
* already_warned
= NULL
;
21873 if (already_warned
== NULL
)
21874 already_warned
= hash_new ();
21875 /* Only warn about the symbol once. To keep the code
21876 simple we let hash_insert do the lookup for us. */
21877 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21878 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21887 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21888 Otherwise we have no need to default values of symbols. */
21891 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21894 if (name
[0] == '_' && name
[1] == 'G'
21895 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21899 if (symbol_find (name
))
21900 as_bad (_("GOT already in the symbol table"));
21902 GOT_symbol
= symbol_new (name
, undefined_section
,
21903 (valueT
) 0, & zero_address_frag
);
21913 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21914 computed as two separate immediate values, added together. We
21915 already know that this value cannot be computed by just one ARM
21918 static unsigned int
21919 validate_immediate_twopart (unsigned int val
,
21920 unsigned int * highpart
)
21925 for (i
= 0; i
< 32; i
+= 2)
21926 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21932 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21934 else if (a
& 0xff0000)
21936 if (a
& 0xff000000)
21938 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21942 gas_assert (a
& 0xff000000);
21943 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21946 return (a
& 0xff) | (i
<< 7);
21953 validate_offset_imm (unsigned int val
, int hwse
)
21955 if ((hwse
&& val
> 255) || val
> 4095)
21960 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21961 negative immediate constant by altering the instruction. A bit of
21966 by inverting the second operand, and
21969 by negating the second operand. */
21972 negate_data_op (unsigned long * instruction
,
21973 unsigned long value
)
21976 unsigned long negated
, inverted
;
21978 negated
= encode_arm_immediate (-value
);
21979 inverted
= encode_arm_immediate (~value
);
21981 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21984 /* First negates. */
21985 case OPCODE_SUB
: /* ADD <-> SUB */
21986 new_inst
= OPCODE_ADD
;
21991 new_inst
= OPCODE_SUB
;
21995 case OPCODE_CMP
: /* CMP <-> CMN */
21996 new_inst
= OPCODE_CMN
;
22001 new_inst
= OPCODE_CMP
;
22005 /* Now Inverted ops. */
22006 case OPCODE_MOV
: /* MOV <-> MVN */
22007 new_inst
= OPCODE_MVN
;
22012 new_inst
= OPCODE_MOV
;
22016 case OPCODE_AND
: /* AND <-> BIC */
22017 new_inst
= OPCODE_BIC
;
22022 new_inst
= OPCODE_AND
;
22026 case OPCODE_ADC
: /* ADC <-> SBC */
22027 new_inst
= OPCODE_SBC
;
22032 new_inst
= OPCODE_ADC
;
22036 /* We cannot do anything. */
22041 if (value
== (unsigned) FAIL
)
22044 *instruction
&= OPCODE_MASK
;
22045 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22049 /* Like negate_data_op, but for Thumb-2. */
22051 static unsigned int
22052 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22056 unsigned int negated
, inverted
;
22058 negated
= encode_thumb32_immediate (-value
);
22059 inverted
= encode_thumb32_immediate (~value
);
22061 rd
= (*instruction
>> 8) & 0xf;
22062 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22065 /* ADD <-> SUB. Includes CMP <-> CMN. */
22066 case T2_OPCODE_SUB
:
22067 new_inst
= T2_OPCODE_ADD
;
22071 case T2_OPCODE_ADD
:
22072 new_inst
= T2_OPCODE_SUB
;
22076 /* ORR <-> ORN. Includes MOV <-> MVN. */
22077 case T2_OPCODE_ORR
:
22078 new_inst
= T2_OPCODE_ORN
;
22082 case T2_OPCODE_ORN
:
22083 new_inst
= T2_OPCODE_ORR
;
22087 /* AND <-> BIC. TST has no inverted equivalent. */
22088 case T2_OPCODE_AND
:
22089 new_inst
= T2_OPCODE_BIC
;
22096 case T2_OPCODE_BIC
:
22097 new_inst
= T2_OPCODE_AND
;
22102 case T2_OPCODE_ADC
:
22103 new_inst
= T2_OPCODE_SBC
;
22107 case T2_OPCODE_SBC
:
22108 new_inst
= T2_OPCODE_ADC
;
22112 /* We cannot do anything. */
22117 if (value
== (unsigned int)FAIL
)
22120 *instruction
&= T2_OPCODE_MASK
;
22121 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22125 /* Read a 32-bit thumb instruction from buf. */
22126 static unsigned long
22127 get_thumb32_insn (char * buf
)
22129 unsigned long insn
;
22130 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22131 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22137 /* We usually want to set the low bit on the address of thumb function
22138 symbols. In particular .word foo - . should have the low bit set.
22139 Generic code tries to fold the difference of two symbols to
22140 a constant. Prevent this and force a relocation when the first symbols
22141 is a thumb function. */
22144 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22146 if (op
== O_subtract
22147 && l
->X_op
== O_symbol
22148 && r
->X_op
== O_symbol
22149 && THUMB_IS_FUNC (l
->X_add_symbol
))
22151 l
->X_op
= O_subtract
;
22152 l
->X_op_symbol
= r
->X_add_symbol
;
22153 l
->X_add_number
-= r
->X_add_number
;
22157 /* Process as normal. */
22161 /* Encode Thumb2 unconditional branches and calls. The encoding
22162 for the 2 are identical for the immediate values. */
22165 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22167 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22170 addressT S
, I1
, I2
, lo
, hi
;
22172 S
= (value
>> 24) & 0x01;
22173 I1
= (value
>> 23) & 0x01;
22174 I2
= (value
>> 22) & 0x01;
22175 hi
= (value
>> 12) & 0x3ff;
22176 lo
= (value
>> 1) & 0x7ff;
22177 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22178 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22179 newval
|= (S
<< 10) | hi
;
22180 newval2
&= ~T2I1I2MASK
;
22181 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22182 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22183 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22187 md_apply_fix (fixS
* fixP
,
22191 offsetT value
= * valP
;
22193 unsigned int newimm
;
22194 unsigned long temp
;
22196 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22198 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22200 /* Note whether this will delete the relocation. */
22202 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22205 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22206 consistency with the behaviour on 32-bit hosts. Remember value
22208 value
&= 0xffffffff;
22209 value
^= 0x80000000;
22210 value
-= 0x80000000;
22213 fixP
->fx_addnumber
= value
;
22215 /* Same treatment for fixP->fx_offset. */
22216 fixP
->fx_offset
&= 0xffffffff;
22217 fixP
->fx_offset
^= 0x80000000;
22218 fixP
->fx_offset
-= 0x80000000;
22220 switch (fixP
->fx_r_type
)
22222 case BFD_RELOC_NONE
:
22223 /* This will need to go in the object file. */
22227 case BFD_RELOC_ARM_IMMEDIATE
:
22228 /* We claim that this fixup has been processed here,
22229 even if in fact we generate an error because we do
22230 not have a reloc for it, so tc_gen_reloc will reject it. */
22233 if (fixP
->fx_addsy
)
22235 const char *msg
= 0;
22237 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22238 msg
= _("undefined symbol %s used as an immediate value");
22239 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22240 msg
= _("symbol %s is in a different section");
22241 else if (S_IS_WEAK (fixP
->fx_addsy
))
22242 msg
= _("symbol %s is weak and may be overridden later");
22246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22247 msg
, S_GET_NAME (fixP
->fx_addsy
));
22252 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22254 /* If the offset is negative, we should use encoding A2 for ADR. */
22255 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22256 newimm
= negate_data_op (&temp
, value
);
22259 newimm
= encode_arm_immediate (value
);
22261 /* If the instruction will fail, see if we can fix things up by
22262 changing the opcode. */
22263 if (newimm
== (unsigned int) FAIL
)
22264 newimm
= negate_data_op (&temp
, value
);
22267 if (newimm
== (unsigned int) FAIL
)
22269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22270 _("invalid constant (%lx) after fixup"),
22271 (unsigned long) value
);
22275 newimm
|= (temp
& 0xfffff000);
22276 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22279 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22281 unsigned int highpart
= 0;
22282 unsigned int newinsn
= 0xe1a00000; /* nop. */
22284 if (fixP
->fx_addsy
)
22286 const char *msg
= 0;
22288 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22289 msg
= _("undefined symbol %s used as an immediate value");
22290 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22291 msg
= _("symbol %s is in a different section");
22292 else if (S_IS_WEAK (fixP
->fx_addsy
))
22293 msg
= _("symbol %s is weak and may be overridden later");
22297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22298 msg
, S_GET_NAME (fixP
->fx_addsy
));
22303 newimm
= encode_arm_immediate (value
);
22304 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22306 /* If the instruction will fail, see if we can fix things up by
22307 changing the opcode. */
22308 if (newimm
== (unsigned int) FAIL
22309 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22311 /* No ? OK - try using two ADD instructions to generate
22313 newimm
= validate_immediate_twopart (value
, & highpart
);
22315 /* Yes - then make sure that the second instruction is
22317 if (newimm
!= (unsigned int) FAIL
)
22319 /* Still No ? Try using a negated value. */
22320 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22321 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22322 /* Otherwise - give up. */
22325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22326 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22331 /* Replace the first operand in the 2nd instruction (which
22332 is the PC) with the destination register. We have
22333 already added in the PC in the first instruction and we
22334 do not want to do it again. */
22335 newinsn
&= ~ 0xf0000;
22336 newinsn
|= ((newinsn
& 0x0f000) << 4);
22339 newimm
|= (temp
& 0xfffff000);
22340 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22342 highpart
|= (newinsn
& 0xfffff000);
22343 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22347 case BFD_RELOC_ARM_OFFSET_IMM
:
22348 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22351 case BFD_RELOC_ARM_LITERAL
:
22357 if (validate_offset_imm (value
, 0) == FAIL
)
22359 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22361 _("invalid literal constant: pool needs to be closer"));
22363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22364 _("bad immediate value for offset (%ld)"),
22369 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22371 newval
&= 0xfffff000;
22374 newval
&= 0xff7ff000;
22375 newval
|= value
| (sign
? INDEX_UP
: 0);
22377 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22380 case BFD_RELOC_ARM_OFFSET_IMM8
:
22381 case BFD_RELOC_ARM_HWLITERAL
:
22387 if (validate_offset_imm (value
, 1) == FAIL
)
22389 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22391 _("invalid literal constant: pool needs to be closer"));
22393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22394 _("bad immediate value for 8-bit offset (%ld)"),
22399 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22401 newval
&= 0xfffff0f0;
22404 newval
&= 0xff7ff0f0;
22405 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22407 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22410 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22411 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22413 _("bad immediate value for offset (%ld)"), (long) value
);
22416 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22418 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22421 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22422 /* This is a complicated relocation used for all varieties of Thumb32
22423 load/store instruction with immediate offset:
22425 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22426 *4, optional writeback(W)
22427 (doubleword load/store)
22429 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22430 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22431 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22432 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22433 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22435 Uppercase letters indicate bits that are already encoded at
22436 this point. Lowercase letters are our problem. For the
22437 second block of instructions, the secondary opcode nybble
22438 (bits 8..11) is present, and bit 23 is zero, even if this is
22439 a PC-relative operation. */
22440 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22442 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22444 if ((newval
& 0xf0000000) == 0xe0000000)
22446 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22448 newval
|= (1 << 23);
22451 if (value
% 4 != 0)
22453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22454 _("offset not a multiple of 4"));
22460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22461 _("offset out of range"));
22466 else if ((newval
& 0x000f0000) == 0x000f0000)
22468 /* PC-relative, 12-bit offset. */
22470 newval
|= (1 << 23);
22475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22476 _("offset out of range"));
22481 else if ((newval
& 0x00000100) == 0x00000100)
22483 /* Writeback: 8-bit, +/- offset. */
22485 newval
|= (1 << 9);
22490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22491 _("offset out of range"));
22496 else if ((newval
& 0x00000f00) == 0x00000e00)
22498 /* T-instruction: positive 8-bit offset. */
22499 if (value
< 0 || value
> 0xff)
22501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22502 _("offset out of range"));
22510 /* Positive 12-bit or negative 8-bit offset. */
22514 newval
|= (1 << 23);
22524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22525 _("offset out of range"));
22532 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22533 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22536 case BFD_RELOC_ARM_SHIFT_IMM
:
22537 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22538 if (((unsigned long) value
) > 32
22540 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22543 _("shift expression is too large"));
22548 /* Shifts of zero must be done as lsl. */
22550 else if (value
== 32)
22552 newval
&= 0xfffff07f;
22553 newval
|= (value
& 0x1f) << 7;
22554 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22557 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22558 case BFD_RELOC_ARM_T32_ADD_IMM
:
22559 case BFD_RELOC_ARM_T32_IMM12
:
22560 case BFD_RELOC_ARM_T32_ADD_PC12
:
22561 /* We claim that this fixup has been processed here,
22562 even if in fact we generate an error because we do
22563 not have a reloc for it, so tc_gen_reloc will reject it. */
22567 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22570 _("undefined symbol %s used as an immediate value"),
22571 S_GET_NAME (fixP
->fx_addsy
));
22575 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22577 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22580 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22581 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22583 newimm
= encode_thumb32_immediate (value
);
22584 if (newimm
== (unsigned int) FAIL
)
22585 newimm
= thumb32_negate_data_op (&newval
, value
);
22587 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22588 && newimm
== (unsigned int) FAIL
)
22590 /* Turn add/sum into addw/subw. */
22591 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22592 newval
= (newval
& 0xfeffffff) | 0x02000000;
22593 /* No flat 12-bit imm encoding for addsw/subsw. */
22594 if ((newval
& 0x00100000) == 0)
22596 /* 12 bit immediate for addw/subw. */
22600 newval
^= 0x00a00000;
22603 newimm
= (unsigned int) FAIL
;
22609 if (newimm
== (unsigned int)FAIL
)
22611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22612 _("invalid constant (%lx) after fixup"),
22613 (unsigned long) value
);
22617 newval
|= (newimm
& 0x800) << 15;
22618 newval
|= (newimm
& 0x700) << 4;
22619 newval
|= (newimm
& 0x0ff);
22621 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22622 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22625 case BFD_RELOC_ARM_SMC
:
22626 if (((unsigned long) value
) > 0xffff)
22627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22628 _("invalid smc expression"));
22629 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22630 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22631 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22634 case BFD_RELOC_ARM_HVC
:
22635 if (((unsigned long) value
) > 0xffff)
22636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22637 _("invalid hvc expression"));
22638 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22639 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22640 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22643 case BFD_RELOC_ARM_SWI
:
22644 if (fixP
->tc_fix_data
!= 0)
22646 if (((unsigned long) value
) > 0xff)
22647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22648 _("invalid swi expression"));
22649 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22651 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22655 if (((unsigned long) value
) > 0x00ffffff)
22656 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22657 _("invalid swi expression"));
22658 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22660 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22664 case BFD_RELOC_ARM_MULTI
:
22665 if (((unsigned long) value
) > 0xffff)
22666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22667 _("invalid expression in load/store multiple"));
22668 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22669 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22673 case BFD_RELOC_ARM_PCREL_CALL
:
22675 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22677 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22678 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22679 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22680 /* Flip the bl to blx. This is a simple flip
22681 bit here because we generate PCREL_CALL for
22682 unconditional bls. */
22684 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22685 newval
= newval
| 0x10000000;
22686 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22692 goto arm_branch_common
;
22694 case BFD_RELOC_ARM_PCREL_JUMP
:
22695 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22697 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22698 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22699 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22701 /* This would map to a bl<cond>, b<cond>,
22702 b<always> to a Thumb function. We
22703 need to force a relocation for this particular
22705 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22709 case BFD_RELOC_ARM_PLT32
:
22711 case BFD_RELOC_ARM_PCREL_BRANCH
:
22713 goto arm_branch_common
;
22715 case BFD_RELOC_ARM_PCREL_BLX
:
22718 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22720 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22721 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22722 && ARM_IS_FUNC (fixP
->fx_addsy
))
22724 /* Flip the blx to a bl and warn. */
22725 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22726 newval
= 0xeb000000;
22727 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22728 _("blx to '%s' an ARM ISA state function changed to bl"),
22730 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22736 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22737 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22741 /* We are going to store value (shifted right by two) in the
22742 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22743 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22744 also be be clear. */
22746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22747 _("misaligned branch destination"));
22748 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22749 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22752 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22754 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22755 newval
|= (value
>> 2) & 0x00ffffff;
22756 /* Set the H bit on BLX instructions. */
22760 newval
|= 0x01000000;
22762 newval
&= ~0x01000000;
22764 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22768 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22769 /* CBZ can only branch forward. */
22771 /* Attempts to use CBZ to branch to the next instruction
22772 (which, strictly speaking, are prohibited) will be turned into
22775 FIXME: It may be better to remove the instruction completely and
22776 perform relaxation. */
22779 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22780 newval
= 0xbf00; /* NOP encoding T1 */
22781 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22788 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22790 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22791 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22792 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22797 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22798 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22801 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22803 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22804 newval
|= (value
& 0x1ff) >> 1;
22805 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22809 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22810 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22813 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22815 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22816 newval
|= (value
& 0xfff) >> 1;
22817 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22821 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22823 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22824 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22825 && ARM_IS_FUNC (fixP
->fx_addsy
)
22826 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22828 /* Force a relocation for a branch 20 bits wide. */
22831 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22833 _("conditional branch out of range"));
22835 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22838 addressT S
, J1
, J2
, lo
, hi
;
22840 S
= (value
& 0x00100000) >> 20;
22841 J2
= (value
& 0x00080000) >> 19;
22842 J1
= (value
& 0x00040000) >> 18;
22843 hi
= (value
& 0x0003f000) >> 12;
22844 lo
= (value
& 0x00000ffe) >> 1;
22846 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22847 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22848 newval
|= (S
<< 10) | hi
;
22849 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22850 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22851 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22855 case BFD_RELOC_THUMB_PCREL_BLX
:
22856 /* If there is a blx from a thumb state function to
22857 another thumb function flip this to a bl and warn
22861 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22862 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22863 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22865 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22866 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22867 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22869 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22870 newval
= newval
| 0x1000;
22871 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22872 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22877 goto thumb_bl_common
;
22879 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22880 /* A bl from Thumb state ISA to an internal ARM state function
22881 is converted to a blx. */
22883 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22884 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22885 && ARM_IS_FUNC (fixP
->fx_addsy
)
22886 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22888 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22889 newval
= newval
& ~0x1000;
22890 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22891 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22897 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22898 /* For a BLX instruction, make sure that the relocation is rounded up
22899 to a word boundary. This follows the semantics of the instruction
22900 which specifies that bit 1 of the target address will come from bit
22901 1 of the base address. */
22902 value
= (value
+ 3) & ~ 3;
22905 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22906 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22907 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22910 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22912 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22914 else if ((value
& ~0x1ffffff)
22915 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22917 _("Thumb2 branch out of range"));
22920 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22921 encode_thumb2_b_bl_offset (buf
, value
);
22925 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22926 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22929 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22930 encode_thumb2_b_bl_offset (buf
, value
);
22935 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22940 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22941 md_number_to_chars (buf
, value
, 2);
22945 case BFD_RELOC_ARM_TLS_CALL
:
22946 case BFD_RELOC_ARM_THM_TLS_CALL
:
22947 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22948 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22949 case BFD_RELOC_ARM_TLS_GOTDESC
:
22950 case BFD_RELOC_ARM_TLS_GD32
:
22951 case BFD_RELOC_ARM_TLS_LE32
:
22952 case BFD_RELOC_ARM_TLS_IE32
:
22953 case BFD_RELOC_ARM_TLS_LDM32
:
22954 case BFD_RELOC_ARM_TLS_LDO32
:
22955 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22958 case BFD_RELOC_ARM_GOT32
:
22959 case BFD_RELOC_ARM_GOTOFF
:
22962 case BFD_RELOC_ARM_GOT_PREL
:
22963 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22964 md_number_to_chars (buf
, value
, 4);
22967 case BFD_RELOC_ARM_TARGET2
:
22968 /* TARGET2 is not partial-inplace, so we need to write the
22969 addend here for REL targets, because it won't be written out
22970 during reloc processing later. */
22971 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22972 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22976 case BFD_RELOC_RVA
:
22978 case BFD_RELOC_ARM_TARGET1
:
22979 case BFD_RELOC_ARM_ROSEGREL32
:
22980 case BFD_RELOC_ARM_SBREL32
:
22981 case BFD_RELOC_32_PCREL
:
22983 case BFD_RELOC_32_SECREL
:
22985 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22987 /* For WinCE we only do this for pcrel fixups. */
22988 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22990 md_number_to_chars (buf
, value
, 4);
22994 case BFD_RELOC_ARM_PREL31
:
22995 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22997 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22998 if ((value
^ (value
>> 1)) & 0x40000000)
23000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23001 _("rel31 relocation overflow"));
23003 newval
|= value
& 0x7fffffff;
23004 md_number_to_chars (buf
, newval
, 4);
23009 case BFD_RELOC_ARM_CP_OFF_IMM
:
23010 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23011 if (value
< -1023 || value
> 1023 || (value
& 3))
23012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23013 _("co-processor offset out of range"));
23018 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23019 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23020 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23022 newval
= get_thumb32_insn (buf
);
23024 newval
&= 0xffffff00;
23027 newval
&= 0xff7fff00;
23028 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23030 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23031 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23032 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23034 put_thumb32_insn (buf
, newval
);
23037 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23038 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23039 if (value
< -255 || value
> 255)
23040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23041 _("co-processor offset out of range"));
23043 goto cp_off_common
;
23045 case BFD_RELOC_ARM_THUMB_OFFSET
:
23046 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23047 /* Exactly what ranges, and where the offset is inserted depends
23048 on the type of instruction, we can establish this from the
23050 switch (newval
>> 12)
23052 case 4: /* PC load. */
23053 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23054 forced to zero for these loads; md_pcrel_from has already
23055 compensated for this. */
23057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23058 _("invalid offset, target not word aligned (0x%08lX)"),
23059 (((unsigned long) fixP
->fx_frag
->fr_address
23060 + (unsigned long) fixP
->fx_where
) & ~3)
23061 + (unsigned long) value
);
23063 if (value
& ~0x3fc)
23064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23065 _("invalid offset, value too big (0x%08lX)"),
23068 newval
|= value
>> 2;
23071 case 9: /* SP load/store. */
23072 if (value
& ~0x3fc)
23073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23074 _("invalid offset, value too big (0x%08lX)"),
23076 newval
|= value
>> 2;
23079 case 6: /* Word load/store. */
23081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23082 _("invalid offset, value too big (0x%08lX)"),
23084 newval
|= value
<< 4; /* 6 - 2. */
23087 case 7: /* Byte load/store. */
23089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23090 _("invalid offset, value too big (0x%08lX)"),
23092 newval
|= value
<< 6;
23095 case 8: /* Halfword load/store. */
23097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23098 _("invalid offset, value too big (0x%08lX)"),
23100 newval
|= value
<< 5; /* 6 - 1. */
23104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23105 "Unable to process relocation for thumb opcode: %lx",
23106 (unsigned long) newval
);
23109 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23112 case BFD_RELOC_ARM_THUMB_ADD
:
23113 /* This is a complicated relocation, since we use it for all of
23114 the following immediate relocations:
23118 9bit ADD/SUB SP word-aligned
23119 10bit ADD PC/SP word-aligned
23121 The type of instruction being processed is encoded in the
23128 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23130 int rd
= (newval
>> 4) & 0xf;
23131 int rs
= newval
& 0xf;
23132 int subtract
= !!(newval
& 0x8000);
23134 /* Check for HI regs, only very restricted cases allowed:
23135 Adjusting SP, and using PC or SP to get an address. */
23136 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23137 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23139 _("invalid Hi register with immediate"));
23141 /* If value is negative, choose the opposite instruction. */
23145 subtract
= !subtract
;
23147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23148 _("immediate value out of range"));
23153 if (value
& ~0x1fc)
23154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23155 _("invalid immediate for stack address calculation"));
23156 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23157 newval
|= value
>> 2;
23159 else if (rs
== REG_PC
|| rs
== REG_SP
)
23161 /* PR gas/18541. If the addition is for a defined symbol
23162 within range of an ADR instruction then accept it. */
23165 && fixP
->fx_addsy
!= NULL
)
23169 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23170 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23171 || S_IS_WEAK (fixP
->fx_addsy
))
23173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23174 _("address calculation needs a strongly defined nearby symbol"));
23178 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23180 /* Round up to the next 4-byte boundary. */
23185 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23190 _("symbol too far away"));
23200 if (subtract
|| value
& ~0x3fc)
23201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23202 _("invalid immediate for address calculation (value = 0x%08lX)"),
23203 (unsigned long) (subtract
? - value
: value
));
23204 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23206 newval
|= value
>> 2;
23211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23212 _("immediate value out of range"));
23213 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23214 newval
|= (rd
<< 8) | value
;
23219 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23220 _("immediate value out of range"));
23221 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23222 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23225 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23228 case BFD_RELOC_ARM_THUMB_IMM
:
23229 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23230 if (value
< 0 || value
> 255)
23231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23232 _("invalid immediate: %ld is out of range"),
23235 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23238 case BFD_RELOC_ARM_THUMB_SHIFT
:
23239 /* 5bit shift value (0..32). LSL cannot take 32. */
23240 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23241 temp
= newval
& 0xf800;
23242 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23244 _("invalid shift value: %ld"), (long) value
);
23245 /* Shifts of zero must be encoded as LSL. */
23247 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23248 /* Shifts of 32 are encoded as zero. */
23249 else if (value
== 32)
23251 newval
|= value
<< 6;
23252 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23255 case BFD_RELOC_VTABLE_INHERIT
:
23256 case BFD_RELOC_VTABLE_ENTRY
:
23260 case BFD_RELOC_ARM_MOVW
:
23261 case BFD_RELOC_ARM_MOVT
:
23262 case BFD_RELOC_ARM_THUMB_MOVW
:
23263 case BFD_RELOC_ARM_THUMB_MOVT
:
23264 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23266 /* REL format relocations are limited to a 16-bit addend. */
23267 if (!fixP
->fx_done
)
23269 if (value
< -0x8000 || value
> 0x7fff)
23270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23271 _("offset out of range"));
23273 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23274 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23279 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23280 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23282 newval
= get_thumb32_insn (buf
);
23283 newval
&= 0xfbf08f00;
23284 newval
|= (value
& 0xf000) << 4;
23285 newval
|= (value
& 0x0800) << 15;
23286 newval
|= (value
& 0x0700) << 4;
23287 newval
|= (value
& 0x00ff);
23288 put_thumb32_insn (buf
, newval
);
23292 newval
= md_chars_to_number (buf
, 4);
23293 newval
&= 0xfff0f000;
23294 newval
|= value
& 0x0fff;
23295 newval
|= (value
& 0xf000) << 4;
23296 md_number_to_chars (buf
, newval
, 4);
23301 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23302 case BFD_RELOC_ARM_ALU_PC_G0
:
23303 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23304 case BFD_RELOC_ARM_ALU_PC_G1
:
23305 case BFD_RELOC_ARM_ALU_PC_G2
:
23306 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23307 case BFD_RELOC_ARM_ALU_SB_G0
:
23308 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23309 case BFD_RELOC_ARM_ALU_SB_G1
:
23310 case BFD_RELOC_ARM_ALU_SB_G2
:
23311 gas_assert (!fixP
->fx_done
);
23312 if (!seg
->use_rela_p
)
23315 bfd_vma encoded_addend
;
23316 bfd_vma addend_abs
= abs (value
);
23318 /* Check that the absolute value of the addend can be
23319 expressed as an 8-bit constant plus a rotation. */
23320 encoded_addend
= encode_arm_immediate (addend_abs
);
23321 if (encoded_addend
== (unsigned int) FAIL
)
23322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23323 _("the offset 0x%08lX is not representable"),
23324 (unsigned long) addend_abs
);
23326 /* Extract the instruction. */
23327 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23329 /* If the addend is positive, use an ADD instruction.
23330 Otherwise use a SUB. Take care not to destroy the S bit. */
23331 insn
&= 0xff1fffff;
23337 /* Place the encoded addend into the first 12 bits of the
23339 insn
&= 0xfffff000;
23340 insn
|= encoded_addend
;
23342 /* Update the instruction. */
23343 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23347 case BFD_RELOC_ARM_LDR_PC_G0
:
23348 case BFD_RELOC_ARM_LDR_PC_G1
:
23349 case BFD_RELOC_ARM_LDR_PC_G2
:
23350 case BFD_RELOC_ARM_LDR_SB_G0
:
23351 case BFD_RELOC_ARM_LDR_SB_G1
:
23352 case BFD_RELOC_ARM_LDR_SB_G2
:
23353 gas_assert (!fixP
->fx_done
);
23354 if (!seg
->use_rela_p
)
23357 bfd_vma addend_abs
= abs (value
);
23359 /* Check that the absolute value of the addend can be
23360 encoded in 12 bits. */
23361 if (addend_abs
>= 0x1000)
23362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23363 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23364 (unsigned long) addend_abs
);
23366 /* Extract the instruction. */
23367 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23369 /* If the addend is negative, clear bit 23 of the instruction.
23370 Otherwise set it. */
23372 insn
&= ~(1 << 23);
23376 /* Place the absolute value of the addend into the first 12 bits
23377 of the instruction. */
23378 insn
&= 0xfffff000;
23379 insn
|= addend_abs
;
23381 /* Update the instruction. */
23382 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23386 case BFD_RELOC_ARM_LDRS_PC_G0
:
23387 case BFD_RELOC_ARM_LDRS_PC_G1
:
23388 case BFD_RELOC_ARM_LDRS_PC_G2
:
23389 case BFD_RELOC_ARM_LDRS_SB_G0
:
23390 case BFD_RELOC_ARM_LDRS_SB_G1
:
23391 case BFD_RELOC_ARM_LDRS_SB_G2
:
23392 gas_assert (!fixP
->fx_done
);
23393 if (!seg
->use_rela_p
)
23396 bfd_vma addend_abs
= abs (value
);
23398 /* Check that the absolute value of the addend can be
23399 encoded in 8 bits. */
23400 if (addend_abs
>= 0x100)
23401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23402 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23403 (unsigned long) addend_abs
);
23405 /* Extract the instruction. */
23406 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23408 /* If the addend is negative, clear bit 23 of the instruction.
23409 Otherwise set it. */
23411 insn
&= ~(1 << 23);
23415 /* Place the first four bits of the absolute value of the addend
23416 into the first 4 bits of the instruction, and the remaining
23417 four into bits 8 .. 11. */
23418 insn
&= 0xfffff0f0;
23419 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23421 /* Update the instruction. */
23422 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23426 case BFD_RELOC_ARM_LDC_PC_G0
:
23427 case BFD_RELOC_ARM_LDC_PC_G1
:
23428 case BFD_RELOC_ARM_LDC_PC_G2
:
23429 case BFD_RELOC_ARM_LDC_SB_G0
:
23430 case BFD_RELOC_ARM_LDC_SB_G1
:
23431 case BFD_RELOC_ARM_LDC_SB_G2
:
23432 gas_assert (!fixP
->fx_done
);
23433 if (!seg
->use_rela_p
)
23436 bfd_vma addend_abs
= abs (value
);
23438 /* Check that the absolute value of the addend is a multiple of
23439 four and, when divided by four, fits in 8 bits. */
23440 if (addend_abs
& 0x3)
23441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23442 _("bad offset 0x%08lX (must be word-aligned)"),
23443 (unsigned long) addend_abs
);
23445 if ((addend_abs
>> 2) > 0xff)
23446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23447 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23448 (unsigned long) addend_abs
);
23450 /* Extract the instruction. */
23451 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23453 /* If the addend is negative, clear bit 23 of the instruction.
23454 Otherwise set it. */
23456 insn
&= ~(1 << 23);
23460 /* Place the addend (divided by four) into the first eight
23461 bits of the instruction. */
23462 insn
&= 0xfffffff0;
23463 insn
|= addend_abs
>> 2;
23465 /* Update the instruction. */
23466 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23470 case BFD_RELOC_ARM_V4BX
:
23471 /* This will need to go in the object file. */
23475 case BFD_RELOC_UNUSED
:
23477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23478 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23482 /* Translate internal representation of relocation info to BFD target
23486 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23489 bfd_reloc_code_real_type code
;
23491 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23493 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23494 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23495 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23497 if (fixp
->fx_pcrel
)
23499 if (section
->use_rela_p
)
23500 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23502 fixp
->fx_offset
= reloc
->address
;
23504 reloc
->addend
= fixp
->fx_offset
;
23506 switch (fixp
->fx_r_type
)
23509 if (fixp
->fx_pcrel
)
23511 code
= BFD_RELOC_8_PCREL
;
23516 if (fixp
->fx_pcrel
)
23518 code
= BFD_RELOC_16_PCREL
;
23523 if (fixp
->fx_pcrel
)
23525 code
= BFD_RELOC_32_PCREL
;
23529 case BFD_RELOC_ARM_MOVW
:
23530 if (fixp
->fx_pcrel
)
23532 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23536 case BFD_RELOC_ARM_MOVT
:
23537 if (fixp
->fx_pcrel
)
23539 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23543 case BFD_RELOC_ARM_THUMB_MOVW
:
23544 if (fixp
->fx_pcrel
)
23546 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23550 case BFD_RELOC_ARM_THUMB_MOVT
:
23551 if (fixp
->fx_pcrel
)
23553 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23557 case BFD_RELOC_NONE
:
23558 case BFD_RELOC_ARM_PCREL_BRANCH
:
23559 case BFD_RELOC_ARM_PCREL_BLX
:
23560 case BFD_RELOC_RVA
:
23561 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23562 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23563 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23564 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23565 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23566 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23567 case BFD_RELOC_VTABLE_ENTRY
:
23568 case BFD_RELOC_VTABLE_INHERIT
:
23570 case BFD_RELOC_32_SECREL
:
23572 code
= fixp
->fx_r_type
;
23575 case BFD_RELOC_THUMB_PCREL_BLX
:
23577 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23578 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23581 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23584 case BFD_RELOC_ARM_LITERAL
:
23585 case BFD_RELOC_ARM_HWLITERAL
:
23586 /* If this is called then the a literal has
23587 been referenced across a section boundary. */
23588 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23589 _("literal referenced across section boundary"));
23593 case BFD_RELOC_ARM_TLS_CALL
:
23594 case BFD_RELOC_ARM_THM_TLS_CALL
:
23595 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23596 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23597 case BFD_RELOC_ARM_GOT32
:
23598 case BFD_RELOC_ARM_GOTOFF
:
23599 case BFD_RELOC_ARM_GOT_PREL
:
23600 case BFD_RELOC_ARM_PLT32
:
23601 case BFD_RELOC_ARM_TARGET1
:
23602 case BFD_RELOC_ARM_ROSEGREL32
:
23603 case BFD_RELOC_ARM_SBREL32
:
23604 case BFD_RELOC_ARM_PREL31
:
23605 case BFD_RELOC_ARM_TARGET2
:
23606 case BFD_RELOC_ARM_TLS_LDO32
:
23607 case BFD_RELOC_ARM_PCREL_CALL
:
23608 case BFD_RELOC_ARM_PCREL_JUMP
:
23609 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23610 case BFD_RELOC_ARM_ALU_PC_G0
:
23611 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23612 case BFD_RELOC_ARM_ALU_PC_G1
:
23613 case BFD_RELOC_ARM_ALU_PC_G2
:
23614 case BFD_RELOC_ARM_LDR_PC_G0
:
23615 case BFD_RELOC_ARM_LDR_PC_G1
:
23616 case BFD_RELOC_ARM_LDR_PC_G2
:
23617 case BFD_RELOC_ARM_LDRS_PC_G0
:
23618 case BFD_RELOC_ARM_LDRS_PC_G1
:
23619 case BFD_RELOC_ARM_LDRS_PC_G2
:
23620 case BFD_RELOC_ARM_LDC_PC_G0
:
23621 case BFD_RELOC_ARM_LDC_PC_G1
:
23622 case BFD_RELOC_ARM_LDC_PC_G2
:
23623 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23624 case BFD_RELOC_ARM_ALU_SB_G0
:
23625 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23626 case BFD_RELOC_ARM_ALU_SB_G1
:
23627 case BFD_RELOC_ARM_ALU_SB_G2
:
23628 case BFD_RELOC_ARM_LDR_SB_G0
:
23629 case BFD_RELOC_ARM_LDR_SB_G1
:
23630 case BFD_RELOC_ARM_LDR_SB_G2
:
23631 case BFD_RELOC_ARM_LDRS_SB_G0
:
23632 case BFD_RELOC_ARM_LDRS_SB_G1
:
23633 case BFD_RELOC_ARM_LDRS_SB_G2
:
23634 case BFD_RELOC_ARM_LDC_SB_G0
:
23635 case BFD_RELOC_ARM_LDC_SB_G1
:
23636 case BFD_RELOC_ARM_LDC_SB_G2
:
23637 case BFD_RELOC_ARM_V4BX
:
23638 code
= fixp
->fx_r_type
;
23641 case BFD_RELOC_ARM_TLS_GOTDESC
:
23642 case BFD_RELOC_ARM_TLS_GD32
:
23643 case BFD_RELOC_ARM_TLS_LE32
:
23644 case BFD_RELOC_ARM_TLS_IE32
:
23645 case BFD_RELOC_ARM_TLS_LDM32
:
23646 /* BFD will include the symbol's address in the addend.
23647 But we don't want that, so subtract it out again here. */
23648 if (!S_IS_COMMON (fixp
->fx_addsy
))
23649 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23650 code
= fixp
->fx_r_type
;
23654 case BFD_RELOC_ARM_IMMEDIATE
:
23655 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23656 _("internal relocation (type: IMMEDIATE) not fixed up"));
23659 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23660 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23661 _("ADRL used for a symbol not defined in the same file"));
23664 case BFD_RELOC_ARM_OFFSET_IMM
:
23665 if (section
->use_rela_p
)
23667 code
= fixp
->fx_r_type
;
23671 if (fixp
->fx_addsy
!= NULL
23672 && !S_IS_DEFINED (fixp
->fx_addsy
)
23673 && S_IS_LOCAL (fixp
->fx_addsy
))
23675 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23676 _("undefined local label `%s'"),
23677 S_GET_NAME (fixp
->fx_addsy
));
23681 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23682 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23689 switch (fixp
->fx_r_type
)
23691 case BFD_RELOC_NONE
: type
= "NONE"; break;
23692 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23693 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23694 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23695 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23696 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23697 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23698 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23699 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23700 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23701 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23702 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23703 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23704 default: type
= _("<unknown>"); break;
23706 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23707 _("cannot represent %s relocation in this object file format"),
23714 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23716 && fixp
->fx_addsy
== GOT_symbol
)
23718 code
= BFD_RELOC_ARM_GOTPC
;
23719 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23723 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23725 if (reloc
->howto
== NULL
)
23727 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23728 _("cannot represent %s relocation in this object file format"),
23729 bfd_get_reloc_code_name (code
));
23733 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23734 vtable entry to be used in the relocation's section offset. */
23735 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23736 reloc
->address
= fixp
->fx_offset
;
23741 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23744 cons_fix_new_arm (fragS
* frag
,
23748 bfd_reloc_code_real_type reloc
)
23753 FIXME: @@ Should look at CPU word size. */
23757 reloc
= BFD_RELOC_8
;
23760 reloc
= BFD_RELOC_16
;
23764 reloc
= BFD_RELOC_32
;
23767 reloc
= BFD_RELOC_64
;
23772 if (exp
->X_op
== O_secrel
)
23774 exp
->X_op
= O_symbol
;
23775 reloc
= BFD_RELOC_32_SECREL
;
23779 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23782 #if defined (OBJ_COFF)
23784 arm_validate_fix (fixS
* fixP
)
23786 /* If the destination of the branch is a defined symbol which does not have
23787 the THUMB_FUNC attribute, then we must be calling a function which has
23788 the (interfacearm) attribute. We look for the Thumb entry point to that
23789 function and change the branch to refer to that function instead. */
23790 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23791 && fixP
->fx_addsy
!= NULL
23792 && S_IS_DEFINED (fixP
->fx_addsy
)
23793 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23795 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23802 arm_force_relocation (struct fix
* fixp
)
23804 #if defined (OBJ_COFF) && defined (TE_PE)
23805 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23809 /* In case we have a call or a branch to a function in ARM ISA mode from
23810 a thumb function or vice-versa force the relocation. These relocations
23811 are cleared off for some cores that might have blx and simple transformations
23815 switch (fixp
->fx_r_type
)
23817 case BFD_RELOC_ARM_PCREL_JUMP
:
23818 case BFD_RELOC_ARM_PCREL_CALL
:
23819 case BFD_RELOC_THUMB_PCREL_BLX
:
23820 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23824 case BFD_RELOC_ARM_PCREL_BLX
:
23825 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23826 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23827 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23828 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23837 /* Resolve these relocations even if the symbol is extern or weak.
23838 Technically this is probably wrong due to symbol preemption.
23839 In practice these relocations do not have enough range to be useful
23840 at dynamic link time, and some code (e.g. in the Linux kernel)
23841 expects these references to be resolved. */
23842 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23843 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23844 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23845 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23846 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23847 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23848 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23849 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23850 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23851 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23852 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23853 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23854 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23855 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23858 /* Always leave these relocations for the linker. */
23859 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23860 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23861 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23864 /* Always generate relocations against function symbols. */
23865 if (fixp
->fx_r_type
== BFD_RELOC_32
23867 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23870 return generic_force_reloc (fixp
);
23873 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23874 /* Relocations against function names must be left unadjusted,
23875 so that the linker can use this information to generate interworking
23876 stubs. The MIPS version of this function
23877 also prevents relocations that are mips-16 specific, but I do not
23878 know why it does this.
23881 There is one other problem that ought to be addressed here, but
23882 which currently is not: Taking the address of a label (rather
23883 than a function) and then later jumping to that address. Such
23884 addresses also ought to have their bottom bit set (assuming that
23885 they reside in Thumb code), but at the moment they will not. */
23888 arm_fix_adjustable (fixS
* fixP
)
23890 if (fixP
->fx_addsy
== NULL
)
23893 /* Preserve relocations against symbols with function type. */
23894 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23897 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23898 && fixP
->fx_subsy
== NULL
)
23901 /* We need the symbol name for the VTABLE entries. */
23902 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23903 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23906 /* Don't allow symbols to be discarded on GOT related relocs. */
23907 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23908 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23909 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23910 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23911 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23912 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23913 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23914 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23915 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23916 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23917 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23918 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23919 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23920 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23923 /* Similarly for group relocations. */
23924 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23925 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23926 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23929 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23930 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23931 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23932 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23933 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23934 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23935 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23936 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23937 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23942 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23947 elf32_arm_target_format (void)
23950 return (target_big_endian
23951 ? "elf32-bigarm-symbian"
23952 : "elf32-littlearm-symbian");
23953 #elif defined (TE_VXWORKS)
23954 return (target_big_endian
23955 ? "elf32-bigarm-vxworks"
23956 : "elf32-littlearm-vxworks");
23957 #elif defined (TE_NACL)
23958 return (target_big_endian
23959 ? "elf32-bigarm-nacl"
23960 : "elf32-littlearm-nacl");
23962 if (target_big_endian
)
23963 return "elf32-bigarm";
23965 return "elf32-littlearm";
23970 armelf_frob_symbol (symbolS
* symp
,
23973 elf_frob_symbol (symp
, puntp
);
23977 /* MD interface: Finalization. */
23982 literal_pool
* pool
;
23984 /* Ensure that all the IT blocks are properly closed. */
23985 check_it_blocks_finished ();
23987 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23989 /* Put it at the end of the relevant section. */
23990 subseg_set (pool
->section
, pool
->sub_section
);
23992 arm_elf_change_section ();
23999 /* Remove any excess mapping symbols generated for alignment frags in
24000 SEC. We may have created a mapping symbol before a zero byte
24001 alignment; remove it if there's a mapping symbol after the
24004 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24005 void *dummy ATTRIBUTE_UNUSED
)
24007 segment_info_type
*seginfo
= seg_info (sec
);
24010 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24013 for (fragp
= seginfo
->frchainP
->frch_root
;
24015 fragp
= fragp
->fr_next
)
24017 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24018 fragS
*next
= fragp
->fr_next
;
24020 /* Variable-sized frags have been converted to fixed size by
24021 this point. But if this was variable-sized to start with,
24022 there will be a fixed-size frag after it. So don't handle
24024 if (sym
== NULL
|| next
== NULL
)
24027 if (S_GET_VALUE (sym
) < next
->fr_address
)
24028 /* Not at the end of this frag. */
24030 know (S_GET_VALUE (sym
) == next
->fr_address
);
24034 if (next
->tc_frag_data
.first_map
!= NULL
)
24036 /* Next frag starts with a mapping symbol. Discard this
24038 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24042 if (next
->fr_next
== NULL
)
24044 /* This mapping symbol is at the end of the section. Discard
24046 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24047 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24051 /* As long as we have empty frags without any mapping symbols,
24053 /* If the next frag is non-empty and does not start with a
24054 mapping symbol, then this mapping symbol is required. */
24055 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24058 next
= next
->fr_next
;
24060 while (next
!= NULL
);
24065 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24069 arm_adjust_symtab (void)
24074 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24076 if (ARM_IS_THUMB (sym
))
24078 if (THUMB_IS_FUNC (sym
))
24080 /* Mark the symbol as a Thumb function. */
24081 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24082 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24083 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24085 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24086 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24088 as_bad (_("%s: unexpected function type: %d"),
24089 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24091 else switch (S_GET_STORAGE_CLASS (sym
))
24094 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24097 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24100 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24108 if (ARM_IS_INTERWORK (sym
))
24109 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24116 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24118 if (ARM_IS_THUMB (sym
))
24120 elf_symbol_type
* elf_sym
;
24122 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24123 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24125 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24126 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24128 /* If it's a .thumb_func, declare it as so,
24129 otherwise tag label as .code 16. */
24130 if (THUMB_IS_FUNC (sym
))
24131 elf_sym
->internal_elf_sym
.st_target_internal
24132 = ST_BRANCH_TO_THUMB
;
24133 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24134 elf_sym
->internal_elf_sym
.st_info
=
24135 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24140 /* Remove any overlapping mapping symbols generated by alignment frags. */
24141 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24142 /* Now do generic ELF adjustments. */
24143 elf_adjust_symtab ();
24147 /* MD interface: Initialization. */
24150 set_constant_flonums (void)
24154 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24155 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24159 /* Auto-select Thumb mode if it's the only available instruction set for the
24160 given architecture. */
24163 autoselect_thumb_from_cpu_variant (void)
24165 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24166 opcode_select (16);
24175 if ( (arm_ops_hsh
= hash_new ()) == NULL
24176 || (arm_cond_hsh
= hash_new ()) == NULL
24177 || (arm_shift_hsh
= hash_new ()) == NULL
24178 || (arm_psr_hsh
= hash_new ()) == NULL
24179 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24180 || (arm_reg_hsh
= hash_new ()) == NULL
24181 || (arm_reloc_hsh
= hash_new ()) == NULL
24182 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24183 as_fatal (_("virtual memory exhausted"));
24185 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24186 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24187 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24188 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24189 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24190 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24191 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24192 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24193 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24194 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24195 (void *) (v7m_psrs
+ i
));
24196 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24197 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24199 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24201 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24202 (void *) (barrier_opt_names
+ i
));
24204 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24206 struct reloc_entry
* entry
= reloc_names
+ i
;
24208 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24209 /* This makes encode_branch() use the EABI versions of this relocation. */
24210 entry
->reloc
= BFD_RELOC_UNUSED
;
24212 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24216 set_constant_flonums ();
24218 /* Set the cpu variant based on the command-line options. We prefer
24219 -mcpu= over -march= if both are set (as for GCC); and we prefer
24220 -mfpu= over any other way of setting the floating point unit.
24221 Use of legacy options with new options are faulted. */
24224 if (mcpu_cpu_opt
|| march_cpu_opt
)
24225 as_bad (_("use of old and new-style options to set CPU type"));
24227 mcpu_cpu_opt
= legacy_cpu
;
24229 else if (!mcpu_cpu_opt
)
24230 mcpu_cpu_opt
= march_cpu_opt
;
24235 as_bad (_("use of old and new-style options to set FPU type"));
24237 mfpu_opt
= legacy_fpu
;
24239 else if (!mfpu_opt
)
24241 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24242 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24243 /* Some environments specify a default FPU. If they don't, infer it
24244 from the processor. */
24246 mfpu_opt
= mcpu_fpu_opt
;
24248 mfpu_opt
= march_fpu_opt
;
24250 mfpu_opt
= &fpu_default
;
24256 if (mcpu_cpu_opt
!= NULL
)
24257 mfpu_opt
= &fpu_default
;
24258 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24259 mfpu_opt
= &fpu_arch_vfp_v2
;
24261 mfpu_opt
= &fpu_arch_fpa
;
24267 mcpu_cpu_opt
= &cpu_default
;
24268 selected_cpu
= cpu_default
;
24270 else if (no_cpu_selected ())
24271 selected_cpu
= cpu_default
;
24274 selected_cpu
= *mcpu_cpu_opt
;
24276 mcpu_cpu_opt
= &arm_arch_any
;
24279 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24281 autoselect_thumb_from_cpu_variant ();
24283 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24285 #if defined OBJ_COFF || defined OBJ_ELF
24287 unsigned int flags
= 0;
24289 #if defined OBJ_ELF
24290 flags
= meabi_flags
;
24292 switch (meabi_flags
)
24294 case EF_ARM_EABI_UNKNOWN
:
24296 /* Set the flags in the private structure. */
24297 if (uses_apcs_26
) flags
|= F_APCS26
;
24298 if (support_interwork
) flags
|= F_INTERWORK
;
24299 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24300 if (pic_code
) flags
|= F_PIC
;
24301 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24302 flags
|= F_SOFT_FLOAT
;
24304 switch (mfloat_abi_opt
)
24306 case ARM_FLOAT_ABI_SOFT
:
24307 case ARM_FLOAT_ABI_SOFTFP
:
24308 flags
|= F_SOFT_FLOAT
;
24311 case ARM_FLOAT_ABI_HARD
:
24312 if (flags
& F_SOFT_FLOAT
)
24313 as_bad (_("hard-float conflicts with specified fpu"));
24317 /* Using pure-endian doubles (even if soft-float). */
24318 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24319 flags
|= F_VFP_FLOAT
;
24321 #if defined OBJ_ELF
24322 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24323 flags
|= EF_ARM_MAVERICK_FLOAT
;
24326 case EF_ARM_EABI_VER4
:
24327 case EF_ARM_EABI_VER5
:
24328 /* No additional flags to set. */
24335 bfd_set_private_flags (stdoutput
, flags
);
24337 /* We have run out flags in the COFF header to encode the
24338 status of ATPCS support, so instead we create a dummy,
24339 empty, debug section called .arm.atpcs. */
24344 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24348 bfd_set_section_flags
24349 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24350 bfd_set_section_size (stdoutput
, sec
, 0);
24351 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24357 /* Record the CPU type as well. */
24358 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24359 mach
= bfd_mach_arm_iWMMXt2
;
24360 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24361 mach
= bfd_mach_arm_iWMMXt
;
24362 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24363 mach
= bfd_mach_arm_XScale
;
24364 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24365 mach
= bfd_mach_arm_ep9312
;
24366 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24367 mach
= bfd_mach_arm_5TE
;
24368 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24370 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24371 mach
= bfd_mach_arm_5T
;
24373 mach
= bfd_mach_arm_5
;
24375 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24377 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24378 mach
= bfd_mach_arm_4T
;
24380 mach
= bfd_mach_arm_4
;
24382 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24383 mach
= bfd_mach_arm_3M
;
24384 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24385 mach
= bfd_mach_arm_3
;
24386 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24387 mach
= bfd_mach_arm_2a
;
24388 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24389 mach
= bfd_mach_arm_2
;
24391 mach
= bfd_mach_arm_unknown
;
24393 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24396 /* Command line processing. */
24399 Invocation line includes a switch not recognized by the base assembler.
24400 See if it's a processor-specific option.
24402 This routine is somewhat complicated by the need for backwards
24403 compatibility (since older releases of gcc can't be changed).
24404 The new options try to make the interface as compatible as
24407 New options (supported) are:
24409 -mcpu=<cpu name> Assemble for selected processor
24410 -march=<architecture name> Assemble for selected architecture
24411 -mfpu=<fpu architecture> Assemble for selected FPU.
24412 -EB/-mbig-endian Big-endian
24413 -EL/-mlittle-endian Little-endian
24414 -k Generate PIC code
24415 -mthumb Start in Thumb mode
24416 -mthumb-interwork Code supports ARM/Thumb interworking
24418 -m[no-]warn-deprecated Warn about deprecated features
24419 -m[no-]warn-syms Warn when symbols match instructions
24421 For now we will also provide support for:
24423 -mapcs-32 32-bit Program counter
24424 -mapcs-26 26-bit Program counter
24425 -macps-float Floats passed in FP registers
24426 -mapcs-reentrant Reentrant code
24428 (sometime these will probably be replaced with -mapcs=<list of options>
24429 and -matpcs=<list of options>)
24431 The remaining options are only supported for back-wards compatibility.
24432 Cpu variants, the arm part is optional:
24433 -m[arm]1 Currently not supported.
24434 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24435 -m[arm]3 Arm 3 processor
24436 -m[arm]6[xx], Arm 6 processors
24437 -m[arm]7[xx][t][[d]m] Arm 7 processors
24438 -m[arm]8[10] Arm 8 processors
24439 -m[arm]9[20][tdmi] Arm 9 processors
24440 -mstrongarm[110[0]] StrongARM processors
24441 -mxscale XScale processors
24442 -m[arm]v[2345[t[e]]] Arm architectures
24443 -mall All (except the ARM1)
24445 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24446 -mfpe-old (No float load/store multiples)
24447 -mvfpxd VFP Single precision
24449 -mno-fpu Disable all floating point instructions
24451 The following CPU names are recognized:
24452 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24453 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24454 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24455 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24456 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24457 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24458 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24462 const char * md_shortopts
= "m:k";
24464 #ifdef ARM_BI_ENDIAN
24465 #define OPTION_EB (OPTION_MD_BASE + 0)
24466 #define OPTION_EL (OPTION_MD_BASE + 1)
24468 #if TARGET_BYTES_BIG_ENDIAN
24469 #define OPTION_EB (OPTION_MD_BASE + 0)
24471 #define OPTION_EL (OPTION_MD_BASE + 1)
24474 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24476 struct option md_longopts
[] =
24479 {"EB", no_argument
, NULL
, OPTION_EB
},
24482 {"EL", no_argument
, NULL
, OPTION_EL
},
24484 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24485 {NULL
, no_argument
, NULL
, 0}
24489 size_t md_longopts_size
= sizeof (md_longopts
);
24491 struct arm_option_table
24493 char *option
; /* Option name to match. */
24494 char *help
; /* Help information. */
24495 int *var
; /* Variable to change. */
24496 int value
; /* What to change it to. */
24497 char *deprecated
; /* If non-null, print this message. */
24500 struct arm_option_table arm_opts
[] =
24502 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24503 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24504 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24505 &support_interwork
, 1, NULL
},
24506 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24507 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24508 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24510 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24511 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24512 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24513 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24516 /* These are recognized by the assembler, but have no affect on code. */
24517 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24518 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24520 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24521 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24522 &warn_on_deprecated
, 0, NULL
},
24523 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24524 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24525 {NULL
, NULL
, NULL
, 0, NULL
}
24528 struct arm_legacy_option_table
24530 char *option
; /* Option name to match. */
24531 const arm_feature_set
**var
; /* Variable to change. */
24532 const arm_feature_set value
; /* What to change it to. */
24533 char *deprecated
; /* If non-null, print this message. */
24536 const struct arm_legacy_option_table arm_legacy_opts
[] =
24538 /* DON'T add any new processors to this list -- we want the whole list
24539 to go away... Add them to the processors table instead. */
24540 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24541 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24542 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24543 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24544 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24545 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24546 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24547 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24548 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24549 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24550 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24551 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24552 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24553 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24554 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24555 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24556 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24557 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24558 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24559 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24560 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24561 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24562 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24563 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24564 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24565 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24566 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24567 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24568 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24569 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24570 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24571 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24572 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24573 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24574 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24575 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24576 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24577 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24578 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24579 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24580 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24581 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24582 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24583 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24584 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24585 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24586 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24587 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24588 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24589 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24590 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24591 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24592 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24593 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24594 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24595 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24596 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24597 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24598 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24599 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24600 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24601 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24602 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24603 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24604 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24605 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24606 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24607 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24608 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24609 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24610 N_("use -mcpu=strongarm110")},
24611 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24612 N_("use -mcpu=strongarm1100")},
24613 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24614 N_("use -mcpu=strongarm1110")},
24615 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24616 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24617 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24619 /* Architecture variants -- don't add any more to this list either. */
24620 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24621 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24622 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24623 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24624 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24625 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24626 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24627 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24628 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24629 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24630 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24631 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24632 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24633 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24634 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24635 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24636 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24637 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24639 /* Floating point variants -- don't add any more to this list either. */
24640 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24641 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24642 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24643 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24644 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24646 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24649 struct arm_cpu_option_table
24653 const arm_feature_set value
;
24654 /* For some CPUs we assume an FPU unless the user explicitly sets
24656 const arm_feature_set default_fpu
;
24657 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24659 const char *canonical_name
;
24662 /* This list should, at a minimum, contain all the cpu names
24663 recognized by GCC. */
24664 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24665 static const struct arm_cpu_option_table arm_cpus
[] =
24667 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24668 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24669 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24670 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24671 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24672 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24673 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24674 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24675 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24676 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24677 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24678 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24679 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24680 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24681 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24682 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24683 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24684 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24685 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24686 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24687 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24688 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24689 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24690 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24691 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24692 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24693 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24694 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24695 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24696 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24697 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24698 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24699 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24700 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24701 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24702 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24703 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24704 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24705 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24706 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24707 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24708 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24709 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24710 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24711 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24712 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24713 /* For V5 or later processors we default to using VFP; but the user
24714 should really set the FPU type explicitly. */
24715 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24716 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24717 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24718 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24719 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24720 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24721 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24722 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24723 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24724 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24725 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24726 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24727 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24728 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24729 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24730 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24731 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24732 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24733 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24734 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24736 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24737 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24738 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24739 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24740 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24741 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24742 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24743 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24744 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24746 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24747 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24748 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24749 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24750 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24751 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24752 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24753 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24754 FPU_NONE
, "Cortex-A5"),
24755 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24757 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24758 ARM_FEATURE_COPROC (FPU_VFP_V3
24759 | FPU_NEON_EXT_V1
),
24761 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24762 ARM_FEATURE_COPROC (FPU_VFP_V3
24763 | FPU_NEON_EXT_V1
),
24765 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24767 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24769 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24771 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24773 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24775 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24777 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24778 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24780 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24781 FPU_NONE
, "Cortex-R5"),
24782 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24783 FPU_ARCH_VFP_V3D16
,
24785 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24786 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24787 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24788 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24789 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24790 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24791 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24794 /* ??? XSCALE is really an architecture. */
24795 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24796 /* ??? iwmmxt is not a processor. */
24797 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24798 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24799 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24801 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24802 FPU_ARCH_MAVERICK
, "ARM920T"),
24803 /* Marvell processors. */
24804 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24806 FPU_ARCH_VFP_V3D16
, NULL
),
24807 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24809 FPU_ARCH_NEON_VFP_V4
, NULL
),
24810 /* APM X-Gene family. */
24811 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24813 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24816 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24820 struct arm_arch_option_table
24824 const arm_feature_set value
;
24825 const arm_feature_set default_fpu
;
24828 /* This list should, at a minimum, contain all the architecture names
24829 recognized by GCC. */
24830 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24831 static const struct arm_arch_option_table arm_archs
[] =
24833 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24834 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24835 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24836 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24837 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24838 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24839 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24840 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24841 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24842 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24843 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24844 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24845 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24846 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24847 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24848 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24849 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24850 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24851 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24852 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24853 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24854 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24855 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24856 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24857 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24858 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24859 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24860 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24861 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24862 /* The official spelling of the ARMv7 profile variants is the dashed form.
24863 Accept the non-dashed form for compatibility with old toolchains. */
24864 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24865 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24866 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24867 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24868 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24869 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24870 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24871 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24872 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24873 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24874 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24875 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24876 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24877 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24879 #undef ARM_ARCH_OPT
24881 /* ISA extensions in the co-processor and main instruction set space. */
24882 struct arm_option_extension_value_table
24886 const arm_feature_set merge_value
;
24887 const arm_feature_set clear_value
;
24888 const arm_feature_set allowed_archs
;
24891 /* The following table must be in alphabetical order with a NULL last entry.
24893 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24894 static const struct arm_option_extension_value_table arm_extensions
[] =
24896 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24897 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24898 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24899 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24900 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24901 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24902 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24903 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24904 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24905 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24906 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24907 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24908 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24909 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24910 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24911 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24912 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24913 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24914 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24915 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24916 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24917 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24918 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24919 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24920 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24921 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24922 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24923 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24924 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24925 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24926 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24927 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24929 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24930 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24931 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24932 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24933 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24934 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24935 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24936 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24940 /* ISA floating-point and Advanced SIMD extensions. */
24941 struct arm_option_fpu_value_table
24944 const arm_feature_set value
;
24947 /* This list should, at a minimum, contain all the fpu names
24948 recognized by GCC. */
24949 static const struct arm_option_fpu_value_table arm_fpus
[] =
24951 {"softfpa", FPU_NONE
},
24952 {"fpe", FPU_ARCH_FPE
},
24953 {"fpe2", FPU_ARCH_FPE
},
24954 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24955 {"fpa", FPU_ARCH_FPA
},
24956 {"fpa10", FPU_ARCH_FPA
},
24957 {"fpa11", FPU_ARCH_FPA
},
24958 {"arm7500fe", FPU_ARCH_FPA
},
24959 {"softvfp", FPU_ARCH_VFP
},
24960 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24961 {"vfp", FPU_ARCH_VFP_V2
},
24962 {"vfp9", FPU_ARCH_VFP_V2
},
24963 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24964 {"vfp10", FPU_ARCH_VFP_V2
},
24965 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24966 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24967 {"vfpv2", FPU_ARCH_VFP_V2
},
24968 {"vfpv3", FPU_ARCH_VFP_V3
},
24969 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24970 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24971 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24972 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24973 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24974 {"arm1020t", FPU_ARCH_VFP_V1
},
24975 {"arm1020e", FPU_ARCH_VFP_V2
},
24976 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24977 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24978 {"maverick", FPU_ARCH_MAVERICK
},
24979 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24980 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24981 {"vfpv4", FPU_ARCH_VFP_V4
},
24982 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24983 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24984 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24985 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24986 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24987 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24988 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24989 {"crypto-neon-fp-armv8",
24990 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24991 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
24992 {NULL
, ARM_ARCH_NONE
}
24995 struct arm_option_value_table
25001 static const struct arm_option_value_table arm_float_abis
[] =
25003 {"hard", ARM_FLOAT_ABI_HARD
},
25004 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25005 {"soft", ARM_FLOAT_ABI_SOFT
},
25010 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25011 static const struct arm_option_value_table arm_eabis
[] =
25013 {"gnu", EF_ARM_EABI_UNKNOWN
},
25014 {"4", EF_ARM_EABI_VER4
},
25015 {"5", EF_ARM_EABI_VER5
},
25020 struct arm_long_option_table
25022 char * option
; /* Substring to match. */
25023 char * help
; /* Help information. */
25024 int (* func
) (char * subopt
); /* Function to decode sub-option. */
25025 char * deprecated
; /* If non-null, print this message. */
25029 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
25031 arm_feature_set
*ext_set
= (arm_feature_set
*)
25032 xmalloc (sizeof (arm_feature_set
));
25034 /* We insist on extensions being specified in alphabetical order, and with
25035 extensions being added before being removed. We achieve this by having
25036 the global ARM_EXTENSIONS table in alphabetical order, and using the
25037 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25038 or removing it (0) and only allowing it to change in the order
25040 const struct arm_option_extension_value_table
* opt
= NULL
;
25041 int adding_value
= -1;
25043 /* Copy the feature set, so that we can modify it. */
25044 *ext_set
= **opt_p
;
25047 while (str
!= NULL
&& *str
!= 0)
25054 as_bad (_("invalid architectural extension"));
25059 ext
= strchr (str
, '+');
25064 len
= strlen (str
);
25066 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25068 if (adding_value
!= 0)
25071 opt
= arm_extensions
;
25079 if (adding_value
== -1)
25082 opt
= arm_extensions
;
25084 else if (adding_value
!= 1)
25086 as_bad (_("must specify extensions to add before specifying "
25087 "those to remove"));
25094 as_bad (_("missing architectural extension"));
25098 gas_assert (adding_value
!= -1);
25099 gas_assert (opt
!= NULL
);
25101 /* Scan over the options table trying to find an exact match. */
25102 for (; opt
->name
!= NULL
; opt
++)
25103 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25105 /* Check we can apply the extension to this architecture. */
25106 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25108 as_bad (_("extension does not apply to the base architecture"));
25112 /* Add or remove the extension. */
25114 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25116 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25121 if (opt
->name
== NULL
)
25123 /* Did we fail to find an extension because it wasn't specified in
25124 alphabetical order, or because it does not exist? */
25126 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25127 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25130 if (opt
->name
== NULL
)
25131 as_bad (_("unknown architectural extension `%s'"), str
);
25133 as_bad (_("architectural extensions must be specified in "
25134 "alphabetical order"));
25140 /* We should skip the extension we've just matched the next time
25152 arm_parse_cpu (char *str
)
25154 const struct arm_cpu_option_table
*opt
;
25155 char *ext
= strchr (str
, '+');
25161 len
= strlen (str
);
25165 as_bad (_("missing cpu name `%s'"), str
);
25169 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25170 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25172 mcpu_cpu_opt
= &opt
->value
;
25173 mcpu_fpu_opt
= &opt
->default_fpu
;
25174 if (opt
->canonical_name
)
25175 strcpy (selected_cpu_name
, opt
->canonical_name
);
25180 for (i
= 0; i
< len
; i
++)
25181 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25182 selected_cpu_name
[i
] = 0;
25186 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25191 as_bad (_("unknown cpu `%s'"), str
);
25196 arm_parse_arch (char *str
)
25198 const struct arm_arch_option_table
*opt
;
25199 char *ext
= strchr (str
, '+');
25205 len
= strlen (str
);
25209 as_bad (_("missing architecture name `%s'"), str
);
25213 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25214 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25216 march_cpu_opt
= &opt
->value
;
25217 march_fpu_opt
= &opt
->default_fpu
;
25218 strcpy (selected_cpu_name
, opt
->name
);
25221 return arm_parse_extension (ext
, &march_cpu_opt
);
25226 as_bad (_("unknown architecture `%s'\n"), str
);
25231 arm_parse_fpu (char * str
)
25233 const struct arm_option_fpu_value_table
* opt
;
25235 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25236 if (streq (opt
->name
, str
))
25238 mfpu_opt
= &opt
->value
;
25242 as_bad (_("unknown floating point format `%s'\n"), str
);
25247 arm_parse_float_abi (char * str
)
25249 const struct arm_option_value_table
* opt
;
25251 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25252 if (streq (opt
->name
, str
))
25254 mfloat_abi_opt
= opt
->value
;
25258 as_bad (_("unknown floating point abi `%s'\n"), str
);
25264 arm_parse_eabi (char * str
)
25266 const struct arm_option_value_table
*opt
;
25268 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25269 if (streq (opt
->name
, str
))
25271 meabi_flags
= opt
->value
;
25274 as_bad (_("unknown EABI `%s'\n"), str
);
25280 arm_parse_it_mode (char * str
)
25282 bfd_boolean ret
= TRUE
;
25284 if (streq ("arm", str
))
25285 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25286 else if (streq ("thumb", str
))
25287 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25288 else if (streq ("always", str
))
25289 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25290 else if (streq ("never", str
))
25291 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25294 as_bad (_("unknown implicit IT mode `%s', should be "\
25295 "arm, thumb, always, or never."), str
);
25303 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25305 codecomposer_syntax
= TRUE
;
25306 arm_comment_chars
[0] = ';';
25307 arm_line_separator_chars
[0] = 0;
25311 struct arm_long_option_table arm_long_opts
[] =
25313 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25314 arm_parse_cpu
, NULL
},
25315 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25316 arm_parse_arch
, NULL
},
25317 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25318 arm_parse_fpu
, NULL
},
25319 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25320 arm_parse_float_abi
, NULL
},
25322 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25323 arm_parse_eabi
, NULL
},
25325 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25326 arm_parse_it_mode
, NULL
},
25327 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25328 arm_ccs_mode
, NULL
},
25329 {NULL
, NULL
, 0, NULL
}
25333 md_parse_option (int c
, char * arg
)
25335 struct arm_option_table
*opt
;
25336 const struct arm_legacy_option_table
*fopt
;
25337 struct arm_long_option_table
*lopt
;
25343 target_big_endian
= 1;
25349 target_big_endian
= 0;
25353 case OPTION_FIX_V4BX
:
25358 /* Listing option. Just ignore these, we don't support additional
25363 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25365 if (c
== opt
->option
[0]
25366 && ((arg
== NULL
&& opt
->option
[1] == 0)
25367 || streq (arg
, opt
->option
+ 1)))
25369 /* If the option is deprecated, tell the user. */
25370 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25371 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25372 arg
? arg
: "", _(opt
->deprecated
));
25374 if (opt
->var
!= NULL
)
25375 *opt
->var
= opt
->value
;
25381 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25383 if (c
== fopt
->option
[0]
25384 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25385 || streq (arg
, fopt
->option
+ 1)))
25387 /* If the option is deprecated, tell the user. */
25388 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25389 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25390 arg
? arg
: "", _(fopt
->deprecated
));
25392 if (fopt
->var
!= NULL
)
25393 *fopt
->var
= &fopt
->value
;
25399 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25401 /* These options are expected to have an argument. */
25402 if (c
== lopt
->option
[0]
25404 && strncmp (arg
, lopt
->option
+ 1,
25405 strlen (lopt
->option
+ 1)) == 0)
25407 /* If the option is deprecated, tell the user. */
25408 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25409 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25410 _(lopt
->deprecated
));
25412 /* Call the sup-option parser. */
25413 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25424 md_show_usage (FILE * fp
)
25426 struct arm_option_table
*opt
;
25427 struct arm_long_option_table
*lopt
;
25429 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25431 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25432 if (opt
->help
!= NULL
)
25433 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25435 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25436 if (lopt
->help
!= NULL
)
25437 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25441 -EB assemble code for a big-endian cpu\n"));
25446 -EL assemble code for a little-endian cpu\n"));
25450 --fix-v4bx Allow BX in ARMv4 code\n"));
25458 arm_feature_set flags
;
25459 } cpu_arch_ver_table
;
25461 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25462 least features first. */
25463 static const cpu_arch_ver_table cpu_arch_ver
[] =
25469 {4, ARM_ARCH_V5TE
},
25470 {5, ARM_ARCH_V5TEJ
},
25474 {11, ARM_ARCH_V6M
},
25475 {12, ARM_ARCH_V6SM
},
25476 {8, ARM_ARCH_V6T2
},
25477 {10, ARM_ARCH_V7VE
},
25478 {10, ARM_ARCH_V7R
},
25479 {10, ARM_ARCH_V7M
},
25480 {14, ARM_ARCH_V8A
},
25484 /* Set an attribute if it has not already been set by the user. */
25486 aeabi_set_attribute_int (int tag
, int value
)
25489 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25490 || !attributes_set_explicitly
[tag
])
25491 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25495 aeabi_set_attribute_string (int tag
, const char *value
)
25498 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25499 || !attributes_set_explicitly
[tag
])
25500 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25503 /* Set the public EABI object attributes. */
25505 aeabi_set_public_attributes (void)
25510 int fp16_optional
= 0;
25511 arm_feature_set flags
;
25512 arm_feature_set tmp
;
25513 const cpu_arch_ver_table
*p
;
25515 /* Choose the architecture based on the capabilities of the requested cpu
25516 (if any) and/or the instructions actually used. */
25517 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25518 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25519 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25521 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25522 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25524 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25525 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25527 selected_cpu
= flags
;
25529 /* Allow the user to override the reported architecture. */
25532 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25533 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25536 /* We need to make sure that the attributes do not identify us as v6S-M
25537 when the only v6S-M feature in use is the Operating System Extensions. */
25538 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25539 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25540 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25544 for (p
= cpu_arch_ver
; p
->val
; p
++)
25546 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25549 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25553 /* The table lookup above finds the last architecture to contribute
25554 a new feature. Unfortunately, Tag13 is a subset of the union of
25555 v6T2 and v7-M, so it is never seen as contributing a new feature.
25556 We can not search for the last entry which is entirely used,
25557 because if no CPU is specified we build up only those flags
25558 actually used. Perhaps we should separate out the specified
25559 and implicit cases. Avoid taking this path for -march=all by
25560 checking for contradictory v7-A / v7-M features. */
25562 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25563 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25564 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25567 /* Tag_CPU_name. */
25568 if (selected_cpu_name
[0])
25572 q
= selected_cpu_name
;
25573 if (strncmp (q
, "armv", 4) == 0)
25578 for (i
= 0; q
[i
]; i
++)
25579 q
[i
] = TOUPPER (q
[i
]);
25581 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25584 /* Tag_CPU_arch. */
25585 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25587 /* Tag_CPU_arch_profile. */
25588 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25590 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25592 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25597 if (profile
!= '\0')
25598 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25600 /* Tag_ARM_ISA_use. */
25601 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25603 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25605 /* Tag_THUMB_ISA_use. */
25606 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25608 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25609 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25611 /* Tag_VFP_arch. */
25612 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25613 aeabi_set_attribute_int (Tag_VFP_arch
,
25614 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25616 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25617 aeabi_set_attribute_int (Tag_VFP_arch
,
25618 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25620 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25623 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25625 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25627 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25630 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25631 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25632 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25633 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25634 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25636 /* Tag_ABI_HardFP_use. */
25637 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25638 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25639 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25641 /* Tag_WMMX_arch. */
25642 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25643 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25644 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25645 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25647 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25648 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25649 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25650 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25652 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25654 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25658 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25663 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25664 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25665 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25669 We set Tag_DIV_use to two when integer divide instructions have been used
25670 in ARM state, or when Thumb integer divide instructions have been used,
25671 but we have no architecture profile set, nor have we any ARM instructions.
25673 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25676 For new architectures we will have to check these tests. */
25677 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25678 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25679 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25680 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25681 || (profile
== '\0'
25682 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25683 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25684 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25686 /* Tag_MP_extension_use. */
25687 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25688 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25690 /* Tag Virtualization_use. */
25691 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25693 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25696 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25699 /* Add the default contents for the .ARM.attributes section. */
25703 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25706 aeabi_set_public_attributes ();
25708 #endif /* OBJ_ELF */
25711 /* Parse a .cpu directive. */
25714 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25716 const struct arm_cpu_option_table
*opt
;
25720 name
= input_line_pointer
;
25721 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25722 input_line_pointer
++;
25723 saved_char
= *input_line_pointer
;
25724 *input_line_pointer
= 0;
25726 /* Skip the first "all" entry. */
25727 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25728 if (streq (opt
->name
, name
))
25730 mcpu_cpu_opt
= &opt
->value
;
25731 selected_cpu
= opt
->value
;
25732 if (opt
->canonical_name
)
25733 strcpy (selected_cpu_name
, opt
->canonical_name
);
25737 for (i
= 0; opt
->name
[i
]; i
++)
25738 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25740 selected_cpu_name
[i
] = 0;
25742 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25743 *input_line_pointer
= saved_char
;
25744 demand_empty_rest_of_line ();
25747 as_bad (_("unknown cpu `%s'"), name
);
25748 *input_line_pointer
= saved_char
;
25749 ignore_rest_of_line ();
25753 /* Parse a .arch directive. */
25756 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25758 const struct arm_arch_option_table
*opt
;
25762 name
= input_line_pointer
;
25763 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25764 input_line_pointer
++;
25765 saved_char
= *input_line_pointer
;
25766 *input_line_pointer
= 0;
25768 /* Skip the first "all" entry. */
25769 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25770 if (streq (opt
->name
, name
))
25772 mcpu_cpu_opt
= &opt
->value
;
25773 selected_cpu
= opt
->value
;
25774 strcpy (selected_cpu_name
, opt
->name
);
25775 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25776 *input_line_pointer
= saved_char
;
25777 demand_empty_rest_of_line ();
25781 as_bad (_("unknown architecture `%s'\n"), name
);
25782 *input_line_pointer
= saved_char
;
25783 ignore_rest_of_line ();
25787 /* Parse a .object_arch directive. */
25790 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25792 const struct arm_arch_option_table
*opt
;
25796 name
= input_line_pointer
;
25797 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25798 input_line_pointer
++;
25799 saved_char
= *input_line_pointer
;
25800 *input_line_pointer
= 0;
25802 /* Skip the first "all" entry. */
25803 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25804 if (streq (opt
->name
, name
))
25806 object_arch
= &opt
->value
;
25807 *input_line_pointer
= saved_char
;
25808 demand_empty_rest_of_line ();
25812 as_bad (_("unknown architecture `%s'\n"), name
);
25813 *input_line_pointer
= saved_char
;
25814 ignore_rest_of_line ();
25817 /* Parse a .arch_extension directive. */
25820 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25822 const struct arm_option_extension_value_table
*opt
;
25825 int adding_value
= 1;
25827 name
= input_line_pointer
;
25828 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25829 input_line_pointer
++;
25830 saved_char
= *input_line_pointer
;
25831 *input_line_pointer
= 0;
25833 if (strlen (name
) >= 2
25834 && strncmp (name
, "no", 2) == 0)
25840 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25841 if (streq (opt
->name
, name
))
25843 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25845 as_bad (_("architectural extension `%s' is not allowed for the "
25846 "current base architecture"), name
);
25851 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25854 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25856 mcpu_cpu_opt
= &selected_cpu
;
25857 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25858 *input_line_pointer
= saved_char
;
25859 demand_empty_rest_of_line ();
25863 if (opt
->name
== NULL
)
25864 as_bad (_("unknown architecture extension `%s'\n"), name
);
25866 *input_line_pointer
= saved_char
;
25867 ignore_rest_of_line ();
25870 /* Parse a .fpu directive. */
25873 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25875 const struct arm_option_fpu_value_table
*opt
;
25879 name
= input_line_pointer
;
25880 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25881 input_line_pointer
++;
25882 saved_char
= *input_line_pointer
;
25883 *input_line_pointer
= 0;
25885 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25886 if (streq (opt
->name
, name
))
25888 mfpu_opt
= &opt
->value
;
25889 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25890 *input_line_pointer
= saved_char
;
25891 demand_empty_rest_of_line ();
25895 as_bad (_("unknown floating point format `%s'\n"), name
);
25896 *input_line_pointer
= saved_char
;
25897 ignore_rest_of_line ();
25900 /* Copy symbol information. */
25903 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25905 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25909 /* Given a symbolic attribute NAME, return the proper integer value.
25910 Returns -1 if the attribute is not known. */
25913 arm_convert_symbolic_attribute (const char *name
)
25915 static const struct
25920 attribute_table
[] =
25922 /* When you modify this table you should
25923 also modify the list in doc/c-arm.texi. */
25924 #define T(tag) {#tag, tag}
25925 T (Tag_CPU_raw_name
),
25928 T (Tag_CPU_arch_profile
),
25929 T (Tag_ARM_ISA_use
),
25930 T (Tag_THUMB_ISA_use
),
25934 T (Tag_Advanced_SIMD_arch
),
25935 T (Tag_PCS_config
),
25936 T (Tag_ABI_PCS_R9_use
),
25937 T (Tag_ABI_PCS_RW_data
),
25938 T (Tag_ABI_PCS_RO_data
),
25939 T (Tag_ABI_PCS_GOT_use
),
25940 T (Tag_ABI_PCS_wchar_t
),
25941 T (Tag_ABI_FP_rounding
),
25942 T (Tag_ABI_FP_denormal
),
25943 T (Tag_ABI_FP_exceptions
),
25944 T (Tag_ABI_FP_user_exceptions
),
25945 T (Tag_ABI_FP_number_model
),
25946 T (Tag_ABI_align_needed
),
25947 T (Tag_ABI_align8_needed
),
25948 T (Tag_ABI_align_preserved
),
25949 T (Tag_ABI_align8_preserved
),
25950 T (Tag_ABI_enum_size
),
25951 T (Tag_ABI_HardFP_use
),
25952 T (Tag_ABI_VFP_args
),
25953 T (Tag_ABI_WMMX_args
),
25954 T (Tag_ABI_optimization_goals
),
25955 T (Tag_ABI_FP_optimization_goals
),
25956 T (Tag_compatibility
),
25957 T (Tag_CPU_unaligned_access
),
25958 T (Tag_FP_HP_extension
),
25959 T (Tag_VFP_HP_extension
),
25960 T (Tag_ABI_FP_16bit_format
),
25961 T (Tag_MPextension_use
),
25963 T (Tag_nodefaults
),
25964 T (Tag_also_compatible_with
),
25965 T (Tag_conformance
),
25967 T (Tag_Virtualization_use
),
25968 /* We deliberately do not include Tag_MPextension_use_legacy. */
25976 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25977 if (streq (name
, attribute_table
[i
].name
))
25978 return attribute_table
[i
].tag
;
25984 /* Apply sym value for relocations only in the case that they are for
25985 local symbols in the same segment as the fixup and you have the
25986 respective architectural feature for blx and simple switches. */
25988 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25991 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25992 /* PR 17444: If the local symbol is in a different section then a reloc
25993 will always be generated for it, so applying the symbol value now
25994 will result in a double offset being stored in the relocation. */
25995 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25996 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25998 switch (fixP
->fx_r_type
)
26000 case BFD_RELOC_ARM_PCREL_BLX
:
26001 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26002 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26006 case BFD_RELOC_ARM_PCREL_CALL
:
26007 case BFD_RELOC_THUMB_PCREL_BLX
:
26008 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26019 #endif /* OBJ_ELF */