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[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <ctype.h>
24 #include <string.h>
25 #define NO_RELOC 0
26 #include "as.h"
27
28 /* need TARGET_CPU */
29 #include "config.h"
30 #include "subsegs.h"
31 #include "obstack.h"
32 #include "symbols.h"
33 #include "listing.h"
34
35 #ifdef OBJ_ELF
36 #include "elf/arm.h"
37 #endif
38
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
43 #define ARM_250 ARM_3
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
49
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55 #define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
56
57 /* Architectures are the sum of the base and extensions */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
62
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
69
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
73 #define FPU_NONE 0
74
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
78
79
80 #ifndef CPU_DEFAULT
81 #if defined __thumb__
82 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
83 #else
84 #define CPU_DEFAULT ARM_ALL
85 #endif
86 #endif
87
88 #ifndef FPU_DEFAULT
89 #define FPU_DEFAULT FPU_ALL
90 #endif
91
92 #define streq(a, b) (strcmp (a, b) == 0)
93 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
94
95 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
96 static int target_oabi = 0;
97
98 #if defined OBJ_COFF || defined OBJ_ELF
99 /* Flags stored in private area of BFD structure */
100 static boolean uses_apcs_26 = false;
101 static boolean support_interwork = false;
102 static boolean uses_apcs_float = false;
103 static boolean pic_code = false;
104 #endif
105
106 /* This array holds the chars that always start a comment. If the
107 pre-processor is disabled, these aren't very useful */
108 CONST char comment_chars[] = "@";
109
110 /* This array holds the chars that only start a comment at the beginning of
111 a line. If the line seems to have the form '# 123 filename'
112 .line and .file directives will appear in the pre-processed output */
113 /* Note that input_file.c hand checks for '#' at the beginning of the
114 first line of the input file. This is because the compiler outputs
115 #NO_APP at the beginning of its output. */
116 /* Also note that comments like this one will always work. */
117 CONST char line_comment_chars[] = "#";
118
119 #ifdef TE_LINUX
120 CONST char line_separator_chars[] = ";";
121 #else
122 CONST char line_separator_chars[] = "";
123 #endif
124
125 /* Chars that can be used to separate mant from exp in floating point nums */
126 CONST char EXP_CHARS[] = "eE";
127
128 /* Chars that mean this number is a floating point constant */
129 /* As in 0f12.456 */
130 /* or 0d1.2345e12 */
131
132 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
133
134 /* Prefix characters that indicate the start of an immediate
135 value. */
136 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
137
138 #ifdef OBJ_ELF
139 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
140 #endif
141
142 CONST int md_reloc_size = 8; /* Size of relocation record */
143
144 static int thumb_mode = 0; /* 0: assemble for ARM, 1: assemble for Thumb,
145 2: assemble for Thumb even though target cpu
146 does not support thumb instructions */
147 typedef struct arm_fix
148 {
149 int thumb_mode;
150 } arm_fix_data;
151
152 struct arm_it
153 {
154 CONST char * error;
155 unsigned long instruction;
156 int suffix;
157 int size;
158 struct
159 {
160 bfd_reloc_code_real_type type;
161 expressionS exp;
162 int pc_rel;
163 } reloc;
164 };
165
166 struct arm_it inst;
167
168 struct asm_shift
169 {
170 CONST char * template;
171 unsigned long value;
172 };
173
174 static CONST struct asm_shift shift[] =
175 {
176 {"asl", 0},
177 {"lsl", 0},
178 {"lsr", 0x00000020},
179 {"asr", 0x00000040},
180 {"ror", 0x00000060},
181 {"rrx", 0x00000060},
182 {"ASL", 0},
183 {"LSL", 0},
184 {"LSR", 0x00000020},
185 {"ASR", 0x00000040},
186 {"ROR", 0x00000060},
187 {"RRX", 0x00000060}
188 };
189
190 #define NO_SHIFT_RESTRICT 1
191 #define SHIFT_RESTRICT 0
192
193 #define NUM_FLOAT_VALS 8
194
195 CONST char * fp_const[] =
196 {
197 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
198 };
199
200 /* Number of littlenums required to hold an extended precision number */
201 #define MAX_LITTLENUMS 6
202
203 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
204
205 #define FAIL (-1)
206 #define SUCCESS (0)
207
208 #define SUFF_S 1
209 #define SUFF_D 2
210 #define SUFF_E 3
211 #define SUFF_P 4
212
213 #define CP_T_X 0x00008000
214 #define CP_T_Y 0x00400000
215 #define CP_T_Pre 0x01000000
216 #define CP_T_UD 0x00800000
217 #define CP_T_WB 0x00200000
218
219 #define CONDS_BIT (0x00100000)
220 #define LOAD_BIT (0x00100000)
221 #define TRANS_BIT (0x00200000)
222
223 struct asm_cond
224 {
225 CONST char * template;
226 unsigned long value;
227 };
228
229 /* This is to save a hash look-up in the common case */
230 #define COND_ALWAYS 0xe0000000
231
232 static CONST struct asm_cond conds[] =
233 {
234 {"eq", 0x00000000},
235 {"ne", 0x10000000},
236 {"cs", 0x20000000}, {"hs", 0x20000000},
237 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
238 {"mi", 0x40000000},
239 {"pl", 0x50000000},
240 {"vs", 0x60000000},
241 {"vc", 0x70000000},
242 {"hi", 0x80000000},
243 {"ls", 0x90000000},
244 {"ge", 0xa0000000},
245 {"lt", 0xb0000000},
246 {"gt", 0xc0000000},
247 {"le", 0xd0000000},
248 {"al", 0xe0000000},
249 {"nv", 0xf0000000}
250 };
251
252 /* Warning: If the top bit of the set_bits is set, then the standard
253 instruction bitmask is ignored, and the new bitmask is taken from
254 the set_bits: */
255 struct asm_flg
256 {
257 CONST char * template; /* Basic flag string */
258 unsigned long set_bits; /* Bits to set */
259 };
260
261 static CONST struct asm_flg s_flag[] =
262 {
263 {"s", CONDS_BIT},
264 {NULL, 0}
265 };
266
267 static CONST struct asm_flg ldr_flags[] =
268 {
269 {"b", 0x00400000},
270 {"t", TRANS_BIT},
271 {"bt", 0x00400000 | TRANS_BIT},
272 {"h", 0x801000b0},
273 {"sh", 0x801000f0},
274 {"sb", 0x801000d0},
275 {NULL, 0}
276 };
277
278 static CONST struct asm_flg str_flags[] =
279 {
280 {"b", 0x00400000},
281 {"t", TRANS_BIT},
282 {"bt", 0x00400000 | TRANS_BIT},
283 {"h", 0x800000b0},
284 {NULL, 0}
285 };
286
287 static CONST struct asm_flg byte_flag[] =
288 {
289 {"b", 0x00400000},
290 {NULL, 0}
291 };
292
293 static CONST struct asm_flg cmp_flags[] =
294 {
295 {"s", CONDS_BIT},
296 {"p", 0x0010f000},
297 {NULL, 0}
298 };
299
300 static CONST struct asm_flg ldm_flags[] =
301 {
302 {"ed", 0x01800000},
303 {"fd", 0x00800000},
304 {"ea", 0x01000000},
305 {"fa", 0x08000000},
306 {"ib", 0x01800000},
307 {"ia", 0x00800000},
308 {"db", 0x01000000},
309 {"da", 0x08000000},
310 {NULL, 0}
311 };
312
313 static CONST struct asm_flg stm_flags[] =
314 {
315 {"ed", 0x08000000},
316 {"fd", 0x01000000},
317 {"ea", 0x00800000},
318 {"fa", 0x01800000},
319 {"ib", 0x01800000},
320 {"ia", 0x00800000},
321 {"db", 0x01000000},
322 {"da", 0x08000000},
323 {NULL, 0}
324 };
325
326 static CONST struct asm_flg lfm_flags[] =
327 {
328 {"fd", 0x00800000},
329 {"ea", 0x01000000},
330 {NULL, 0}
331 };
332
333 static CONST struct asm_flg sfm_flags[] =
334 {
335 {"fd", 0x01000000},
336 {"ea", 0x00800000},
337 {NULL, 0}
338 };
339
340 static CONST struct asm_flg round_flags[] =
341 {
342 {"p", 0x00000020},
343 {"m", 0x00000040},
344 {"z", 0x00000060},
345 {NULL, 0}
346 };
347
348 /* The implementation of the FIX instruction is broken on some assemblers,
349 in that it accepts a precision specifier as well as a rounding specifier,
350 despite the fact that this is meaningless. To be more compatible, we
351 accept it as well, though of course it does not set any bits. */
352 static CONST struct asm_flg fix_flags[] =
353 {
354 {"p", 0x00000020},
355 {"m", 0x00000040},
356 {"z", 0x00000060},
357 {"sp", 0x00000020},
358 {"sm", 0x00000040},
359 {"sz", 0x00000060},
360 {"dp", 0x00000020},
361 {"dm", 0x00000040},
362 {"dz", 0x00000060},
363 {"ep", 0x00000020},
364 {"em", 0x00000040},
365 {"ez", 0x00000060},
366 {NULL, 0}
367 };
368
369 static CONST struct asm_flg except_flag[] =
370 {
371 {"e", 0x00400000},
372 {NULL, 0}
373 };
374
375 static CONST struct asm_flg cplong_flag[] =
376 {
377 {"l", 0x00400000},
378 {NULL, 0}
379 };
380
381 struct asm_psr
382 {
383 CONST char * template;
384 unsigned long number;
385 };
386
387 #define PSR_FIELD_MASK 0x000f0000
388
389 #define PSR_FLAGS 0x00080000
390 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
391 #define PSR_ALL 0x00090000
392
393 #define CPSR_ALL 0
394 #define SPSR_ALL 1
395 #define CPSR_FLG 2
396 #define SPSR_FLG 3
397 #define CPSR_CTL 4
398 #define SPSR_CTL 5
399
400 static CONST struct asm_psr psrs[] =
401 {
402 /* Valid <psr>'s */
403 {"cpsr", CPSR_ALL},
404 {"cpsr_all", CPSR_ALL},
405 {"spsr", SPSR_ALL},
406 {"spsr_all", SPSR_ALL},
407
408 /* Valid <psrf>'s */
409 {"cpsr_flg", CPSR_FLG},
410 {"spsr_flg", SPSR_FLG},
411
412 /* Valid <psrc>'s */
413 {"cpsr_c", CPSR_CTL},
414 {"cpsr_ctl", CPSR_CTL},
415 {"spsr_c", SPSR_CTL},
416 {"spsr_ctl", SPSR_CTL}
417 };
418
419 /* Functions called by parser */
420 /* ARM instructions */
421 static void do_arit PARAMS ((char *, unsigned long));
422 static void do_cmp PARAMS ((char *, unsigned long));
423 static void do_mov PARAMS ((char *, unsigned long));
424 static void do_ldst PARAMS ((char *, unsigned long));
425 static void do_ldmstm PARAMS ((char *, unsigned long));
426 static void do_branch PARAMS ((char *, unsigned long));
427 static void do_swi PARAMS ((char *, unsigned long));
428 /* Pseudo Op codes */
429 static void do_adr PARAMS ((char *, unsigned long));
430 static void do_adrl PARAMS ((char *, unsigned long));
431 static void do_nop PARAMS ((char *, unsigned long));
432 /* ARM 2 */
433 static void do_mul PARAMS ((char *, unsigned long));
434 static void do_mla PARAMS ((char *, unsigned long));
435 /* ARM 3 */
436 static void do_swap PARAMS ((char *, unsigned long));
437 /* ARM 6 */
438 static void do_msr PARAMS ((char *, unsigned long));
439 static void do_mrs PARAMS ((char *, unsigned long));
440 /* ARM 7M */
441 static void do_mull PARAMS ((char *, unsigned long));
442 /* ARM THUMB */
443 static void do_bx PARAMS ((char *, unsigned long));
444
445
446 /* Coprocessor Instructions */
447 static void do_cdp PARAMS ((char *, unsigned long));
448 static void do_lstc PARAMS ((char *, unsigned long));
449 static void do_co_reg PARAMS ((char *, unsigned long));
450 static void do_fp_ctrl PARAMS ((char *, unsigned long));
451 static void do_fp_ldst PARAMS ((char *, unsigned long));
452 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
453 static void do_fp_dyadic PARAMS ((char *, unsigned long));
454 static void do_fp_monadic PARAMS ((char *, unsigned long));
455 static void do_fp_cmp PARAMS ((char *, unsigned long));
456 static void do_fp_from_reg PARAMS ((char *, unsigned long));
457 static void do_fp_to_reg PARAMS ((char *, unsigned long));
458
459 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
460 static int arm_reg_parse PARAMS ((char **));
461 static int arm_psr_parse PARAMS ((char **));
462 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
463 static int add_to_lit_pool PARAMS ((void));
464 static unsigned validate_immediate PARAMS ((unsigned));
465 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
466 static int validate_offset_imm PARAMS ((unsigned int, int));
467 static void opcode_select PARAMS ((int));
468 static void end_of_line PARAMS ((char *));
469 static int reg_required_here PARAMS ((char **, int));
470 static int psr_required_here PARAMS ((char **, int, int));
471 static int co_proc_number PARAMS ((char **));
472 static int cp_opc_expr PARAMS ((char **, int, int));
473 static int cp_reg_required_here PARAMS ((char **, int));
474 static int fp_reg_required_here PARAMS ((char **, int));
475 static int cp_address_offset PARAMS ((char **));
476 static int cp_address_required_here PARAMS ((char **));
477 static int my_get_float_expression PARAMS ((char **));
478 static int skip_past_comma PARAMS ((char **));
479 static int walk_no_bignums PARAMS ((symbolS *));
480 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
481 static int data_op2 PARAMS ((char **));
482 static int fp_op2 PARAMS ((char **));
483 static long reg_list PARAMS ((char **));
484 static void thumb_load_store PARAMS ((char *, int, int));
485 static int decode_shift PARAMS ((char **, int));
486 static int ldst_extend PARAMS ((char **, int));
487 static void thumb_add_sub PARAMS ((char *, int));
488 static void insert_reg PARAMS ((int));
489 static void thumb_shift PARAMS ((char *, int));
490 static void thumb_mov_compare PARAMS ((char *, int));
491 static void set_constant_flonums PARAMS ((void));
492 static valueT md_chars_to_number PARAMS ((char *, int));
493 static void insert_reg_alias PARAMS ((char *, int));
494 static void output_inst PARAMS ((void));
495 #ifdef OBJ_ELF
496 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
497 #endif
498
499 /* ARM instructions take 4bytes in the object file, Thumb instructions
500 take 2: */
501 #define INSN_SIZE 4
502
503 /* LONGEST_INST is the longest basic instruction name without conditions or
504 * flags.
505 * ARM7M has 4 of length 5
506 */
507
508 #define LONGEST_INST 5
509
510
511 struct asm_opcode
512 {
513 CONST char * template; /* Basic string to match */
514 unsigned long value; /* Basic instruction code */
515
516 /* Compulsory suffix that must follow conds. If "", then the
517 instruction is not conditional and must have no suffix. */
518 CONST char * comp_suffix;
519
520 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
521 unsigned long variants; /* Which CPU variants this exists for */
522 /* Function to call to parse args */
523 void (* parms) PARAMS ((char *, unsigned long));
524 };
525
526 static CONST struct asm_opcode insns[] =
527 {
528 /* ARM Instructions */
529 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
530 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
531 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
532 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
533 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
534 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
535 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
536 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
537 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
538 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
539 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
540 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
541 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
542 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
543 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
544 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
545 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
546 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
547 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
548 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
549 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
550 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
551 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
552
553 /* Pseudo ops */
554 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
555 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
556 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
557
558 /* ARM 2 multiplies */
559 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
560 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
561
562 /* ARM 3 - swp instructions */
563 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
564
565 /* ARM 6 Coprocessor instructions */
566 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
567 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
568 /* ScottB: our code uses 0x0128f000 for msr.
569 NickC: but this is wrong because the bits 16 and 19 are handled
570 by the PSR_xxx defines above. */
571
572 /* ARM 7M long multiplies - need signed/unsigned flags! */
573 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
574 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
575 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
576 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
577
578 /* ARM THUMB interworking */
579 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
580
581 /* Floating point instructions */
582 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
583 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
584 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
585 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
586 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
587 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
588 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
589 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
590 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
591 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
592 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
593 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
594 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
595 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
596 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
597 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
598 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
599 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
600 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
602 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
603 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
604 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
605 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
606 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
607 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
608 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
609 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
610 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
611 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
612 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
613 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
614 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
615 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
616 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
617 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
618 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
619 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
620 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
621 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
622 be an optional suffix, but part of the instruction. To be compatible,
623 we accept either. */
624 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
625 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
626 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
627 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
628
629 /* Generic copressor instructions */
630 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
631 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
632 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
633 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
634 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
635 };
636
637 /* defines for various bits that we will want to toggle */
638
639 #define INST_IMMEDIATE 0x02000000
640 #define OFFSET_REG 0x02000000
641 #define HWOFFSET_IMM 0x00400000
642 #define SHIFT_BY_REG 0x00000010
643 #define PRE_INDEX 0x01000000
644 #define INDEX_UP 0x00800000
645 #define WRITE_BACK 0x00200000
646 #define LDM_TYPE_2_OR_3 0x00400000
647
648 #define LITERAL_MASK 0xf000f000
649 #define COND_MASK 0xf0000000
650 #define OPCODE_MASK 0xfe1fffff
651 #define DATA_OP_SHIFT 21
652
653 /* Codes to distinguish the arithmetic instructions */
654
655 #define OPCODE_AND 0
656 #define OPCODE_EOR 1
657 #define OPCODE_SUB 2
658 #define OPCODE_RSB 3
659 #define OPCODE_ADD 4
660 #define OPCODE_ADC 5
661 #define OPCODE_SBC 6
662 #define OPCODE_RSC 7
663 #define OPCODE_TST 8
664 #define OPCODE_TEQ 9
665 #define OPCODE_CMP 10
666 #define OPCODE_CMN 11
667 #define OPCODE_ORR 12
668 #define OPCODE_MOV 13
669 #define OPCODE_BIC 14
670 #define OPCODE_MVN 15
671
672 static void do_t_nop PARAMS ((char *));
673 static void do_t_arit PARAMS ((char *));
674 static void do_t_add PARAMS ((char *));
675 static void do_t_asr PARAMS ((char *));
676 static void do_t_branch9 PARAMS ((char *));
677 static void do_t_branch12 PARAMS ((char *));
678 static void do_t_branch23 PARAMS ((char *));
679 static void do_t_bx PARAMS ((char *));
680 static void do_t_compare PARAMS ((char *));
681 static void do_t_ldmstm PARAMS ((char *));
682 static void do_t_ldr PARAMS ((char *));
683 static void do_t_ldrb PARAMS ((char *));
684 static void do_t_ldrh PARAMS ((char *));
685 static void do_t_lds PARAMS ((char *));
686 static void do_t_lsl PARAMS ((char *));
687 static void do_t_lsr PARAMS ((char *));
688 static void do_t_mov PARAMS ((char *));
689 static void do_t_push_pop PARAMS ((char *));
690 static void do_t_str PARAMS ((char *));
691 static void do_t_strb PARAMS ((char *));
692 static void do_t_strh PARAMS ((char *));
693 static void do_t_sub PARAMS ((char *));
694 static void do_t_swi PARAMS ((char *));
695 static void do_t_adr PARAMS ((char *));
696
697 #define T_OPCODE_MUL 0x4340
698 #define T_OPCODE_TST 0x4200
699 #define T_OPCODE_CMN 0x42c0
700 #define T_OPCODE_NEG 0x4240
701 #define T_OPCODE_MVN 0x43c0
702
703 #define T_OPCODE_ADD_R3 0x1800
704 #define T_OPCODE_SUB_R3 0x1a00
705 #define T_OPCODE_ADD_HI 0x4400
706 #define T_OPCODE_ADD_ST 0xb000
707 #define T_OPCODE_SUB_ST 0xb080
708 #define T_OPCODE_ADD_SP 0xa800
709 #define T_OPCODE_ADD_PC 0xa000
710 #define T_OPCODE_ADD_I8 0x3000
711 #define T_OPCODE_SUB_I8 0x3800
712 #define T_OPCODE_ADD_I3 0x1c00
713 #define T_OPCODE_SUB_I3 0x1e00
714
715 #define T_OPCODE_ASR_R 0x4100
716 #define T_OPCODE_LSL_R 0x4080
717 #define T_OPCODE_LSR_R 0x40c0
718 #define T_OPCODE_ASR_I 0x1000
719 #define T_OPCODE_LSL_I 0x0000
720 #define T_OPCODE_LSR_I 0x0800
721
722 #define T_OPCODE_MOV_I8 0x2000
723 #define T_OPCODE_CMP_I8 0x2800
724 #define T_OPCODE_CMP_LR 0x4280
725 #define T_OPCODE_MOV_HR 0x4600
726 #define T_OPCODE_CMP_HR 0x4500
727
728 #define T_OPCODE_LDR_PC 0x4800
729 #define T_OPCODE_LDR_SP 0x9800
730 #define T_OPCODE_STR_SP 0x9000
731 #define T_OPCODE_LDR_IW 0x6800
732 #define T_OPCODE_STR_IW 0x6000
733 #define T_OPCODE_LDR_IH 0x8800
734 #define T_OPCODE_STR_IH 0x8000
735 #define T_OPCODE_LDR_IB 0x7800
736 #define T_OPCODE_STR_IB 0x7000
737 #define T_OPCODE_LDR_RW 0x5800
738 #define T_OPCODE_STR_RW 0x5000
739 #define T_OPCODE_LDR_RH 0x5a00
740 #define T_OPCODE_STR_RH 0x5200
741 #define T_OPCODE_LDR_RB 0x5c00
742 #define T_OPCODE_STR_RB 0x5400
743
744 #define T_OPCODE_PUSH 0xb400
745 #define T_OPCODE_POP 0xbc00
746
747 #define T_OPCODE_BRANCH 0xe7fe
748
749 static int thumb_reg PARAMS ((char ** str, int hi_lo));
750
751 #define THUMB_SIZE 2 /* Size of thumb instruction */
752 #define THUMB_REG_LO 0x1
753 #define THUMB_REG_HI 0x2
754 #define THUMB_REG_ANY 0x3
755
756 #define THUMB_H1 0x0080
757 #define THUMB_H2 0x0040
758
759 #define THUMB_ASR 0
760 #define THUMB_LSL 1
761 #define THUMB_LSR 2
762
763 #define THUMB_MOVE 0
764 #define THUMB_COMPARE 1
765
766 #define THUMB_LOAD 0
767 #define THUMB_STORE 1
768
769 #define THUMB_PP_PC_LR 0x0100
770
771 /* These three are used for immediate shifts, do not alter */
772 #define THUMB_WORD 2
773 #define THUMB_HALFWORD 1
774 #define THUMB_BYTE 0
775
776 struct thumb_opcode
777 {
778 CONST char * template; /* Basic string to match */
779 unsigned long value; /* Basic instruction code */
780 int size;
781 unsigned long variants; /* Which CPU variants this exists for */
782 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
783 };
784
785 static CONST struct thumb_opcode tinsns[] =
786 {
787 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
788 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
789 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
790 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
791 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
792 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
793 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
794 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
795 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
796 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
797 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
798 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
799 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
800 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
801 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
802 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
803 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
804 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
805 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
806 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
807 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
808 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
809 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
810 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
811 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
812 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
813 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
814 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
815 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
816 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
817 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
818 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
819 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
820 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
821 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
822 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
823 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
824 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
825 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
826 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
827 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
828 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
829 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
830 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
831 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
832 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
833 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
834 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
835 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
836 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
837 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
838 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
839 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
840 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
841 /* Pseudo ops: */
842 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
843 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
844 };
845
846 struct reg_entry
847 {
848 CONST char * name;
849 int number;
850 };
851
852 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
853 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
854 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
855
856 #define REG_PC 15
857 #define REG_LR 14
858 #define REG_SP 13
859
860 /* These are the standard names; Users can add aliases with .req */
861 static CONST struct reg_entry reg_table[] =
862 {
863 /* Processor Register Numbers */
864 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
865 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
866 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
867 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
868 /* APCS conventions */
869 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
870 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
871 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
872 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
873 /* FP Registers */
874 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
875 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
876 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
877 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
878 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
879 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
880 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
881 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
882 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
883 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
884 {NULL, 0}
885 };
886
887 #define BAD_ARGS _("Bad arguments to instruction")
888 #define BAD_PC _("r15 not allowed here")
889 #define BAD_FLAGS _("Instruction should not have flags")
890 #define BAD_COND _("Instruction is not conditional")
891
892 static struct hash_control * arm_ops_hsh = NULL;
893 static struct hash_control * arm_tops_hsh = NULL;
894 static struct hash_control * arm_cond_hsh = NULL;
895 static struct hash_control * arm_shift_hsh = NULL;
896 static struct hash_control * arm_reg_hsh = NULL;
897 static struct hash_control * arm_psr_hsh = NULL;
898
899 /* This table describes all the machine specific pseudo-ops the assembler
900 has to support. The fields are:
901 pseudo-op name without dot
902 function to call to execute this pseudo-op
903 Integer arg to pass to the function
904 */
905
906 static void s_req PARAMS ((int));
907 static void s_align PARAMS ((int));
908 static void s_bss PARAMS ((int));
909 static void s_even PARAMS ((int));
910 static void s_ltorg PARAMS ((int));
911 static void s_arm PARAMS ((int));
912 static void s_thumb PARAMS ((int));
913 static void s_code PARAMS ((int));
914 static void s_force_thumb PARAMS ((int));
915 static void s_thumb_func PARAMS ((int));
916 static void s_thumb_set PARAMS ((int));
917 static void arm_s_text PARAMS ((int));
918 static void arm_s_data PARAMS ((int));
919 #ifdef OBJ_ELF
920 static void arm_s_section PARAMS ((int));
921 static void s_arm_elf_cons PARAMS ((int));
922 #endif
923
924 static int my_get_expression PARAMS ((expressionS *, char **));
925
926 CONST pseudo_typeS md_pseudo_table[] =
927 {
928 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
929 { "bss", s_bss, 0 },
930 { "align", s_align, 0 },
931 { "arm", s_arm, 0 },
932 { "thumb", s_thumb, 0 },
933 { "code", s_code, 0 },
934 { "force_thumb", s_force_thumb, 0 },
935 { "thumb_func", s_thumb_func, 0 },
936 { "thumb_set", s_thumb_set, 0 },
937 { "even", s_even, 0 },
938 { "ltorg", s_ltorg, 0 },
939 { "pool", s_ltorg, 0 },
940 /* Allow for the effect of section changes. */
941 { "text", arm_s_text, 0 },
942 { "data", arm_s_data, 0 },
943 #ifdef OBJ_ELF
944 { "section", arm_s_section, 0 },
945 { "section.s", arm_s_section, 0 },
946 { "sect", arm_s_section, 0 },
947 { "sect.s", arm_s_section, 0 },
948 { "word", s_arm_elf_cons, 4 },
949 { "long", s_arm_elf_cons, 4 },
950 #else
951 { "word", cons, 4},
952 #endif
953 { "extend", float_cons, 'x' },
954 { "ldouble", float_cons, 'x' },
955 { "packed", float_cons, 'p' },
956 { 0, 0, 0 }
957 };
958
959 /* Stuff needed to resolve the label ambiguity
960 As:
961 ...
962 label: <insn>
963 may differ from:
964 ...
965 label:
966 <insn>
967 */
968
969 symbolS * last_label_seen;
970 static int label_is_thumb_function_name = false;
971
972 /* Literal stuff */
973
974 #define MAX_LITERAL_POOL_SIZE 1024
975
976 typedef struct literalS
977 {
978 struct expressionS exp;
979 struct arm_it * inst;
980 } literalT;
981
982 literalT literals[MAX_LITERAL_POOL_SIZE];
983 int next_literal_pool_place = 0; /* Next free entry in the pool */
984 int lit_pool_num = 1; /* Next literal pool number */
985 symbolS * current_poolP = NULL;
986
987 static int
988 add_to_lit_pool ()
989 {
990 int lit_count = 0;
991
992 if (current_poolP == NULL)
993 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
994 (valueT) 0, &zero_address_frag);
995
996 /* Check if this literal value is already in the pool: */
997 while (lit_count < next_literal_pool_place)
998 {
999 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1000 && inst.reloc.exp.X_op == O_constant
1001 && literals[lit_count].exp.X_add_number == inst.reloc.exp.X_add_number
1002 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1003 break;
1004 lit_count++;
1005 }
1006
1007 if (lit_count == next_literal_pool_place) /* new entry */
1008 {
1009 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1010 {
1011 inst.error = _("Literal Pool Overflow");
1012 return FAIL;
1013 }
1014
1015 literals[next_literal_pool_place].exp = inst.reloc.exp;
1016 lit_count = next_literal_pool_place++;
1017 }
1018
1019 inst.reloc.exp.X_op = O_symbol;
1020 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1021 inst.reloc.exp.X_add_symbol = current_poolP;
1022
1023 return SUCCESS;
1024 }
1025
1026 /* Can't use symbol_new here, so have to create a symbol and then at
1027 a later date assign it a value. Thats what these functions do. */
1028 static void
1029 symbol_locate (symbolP, name, segment, valu, frag)
1030 symbolS * symbolP;
1031 CONST char * name; /* It is copied, the caller can modify */
1032 segT segment; /* Segment identifier (SEG_<something>) */
1033 valueT valu; /* Symbol value */
1034 fragS * frag; /* Associated fragment */
1035 {
1036 unsigned int name_length;
1037 char * preserved_copy_of_name;
1038
1039 name_length = strlen (name) + 1; /* +1 for \0 */
1040 obstack_grow (&notes, name, name_length);
1041 preserved_copy_of_name = obstack_finish (&notes);
1042 #ifdef STRIP_UNDERSCORE
1043 if (preserved_copy_of_name[0] == '_')
1044 preserved_copy_of_name++;
1045 #endif
1046
1047 #ifdef tc_canonicalize_symbol_name
1048 preserved_copy_of_name =
1049 tc_canonicalize_symbol_name (preserved_copy_of_name);
1050 #endif
1051
1052 S_SET_NAME (symbolP, preserved_copy_of_name);
1053
1054 S_SET_SEGMENT (symbolP, segment);
1055 S_SET_VALUE (symbolP, valu);
1056 symbol_clear_list_pointers(symbolP);
1057
1058 symbol_set_frag (symbolP, frag);
1059
1060 /* Link to end of symbol chain. */
1061 {
1062 extern int symbol_table_frozen;
1063 if (symbol_table_frozen)
1064 abort ();
1065 }
1066
1067 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1068
1069 obj_symbol_new_hook (symbolP);
1070
1071 #ifdef tc_symbol_new_hook
1072 tc_symbol_new_hook (symbolP);
1073 #endif
1074
1075 #ifdef DEBUG_SYMS
1076 verify_symbol_chain (symbol_rootP, symbol_lastP);
1077 #endif /* DEBUG_SYMS */
1078 }
1079
1080 /* Check that an immediate is valid, and if so, convert it to the right format. */
1081
1082 static unsigned int
1083 validate_immediate (val)
1084 unsigned int val;
1085 {
1086 unsigned int a;
1087 unsigned int i;
1088
1089 #define rotate_left(v, n) (v << n | v >> (32 - n))
1090
1091 for (i = 0; i < 32; i += 2)
1092 if ((a = rotate_left (val, i)) <= 0xff)
1093 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1094
1095 return FAIL;
1096 }
1097
1098 /* Check to see if an immediate can be computed as two seperate immediate
1099 values, added together. We already know that this value cannot be
1100 computed by just one ARM instruction. */
1101
1102 static unsigned int
1103 validate_immediate_twopart (val, highpart)
1104 unsigned int val;
1105 unsigned int * highpart;
1106 {
1107 unsigned int a;
1108 unsigned int i;
1109
1110 for (i = 0; i < 32; i += 2)
1111 if (((a = rotate_left (val, i)) & 0xff) != 0)
1112 {
1113 if (a & 0xff00)
1114 {
1115 if (a & ~ 0xffff)
1116 continue;
1117 * highpart = (a >> 8) | ((i + 24) << 7);
1118 }
1119 else if (a & 0xff0000)
1120 {
1121 if (a & 0xff000000)
1122 continue;
1123
1124 * highpart = (a >> 16) | ((i + 16) << 7);
1125 }
1126 else
1127 {
1128 assert (a & 0xff000000);
1129
1130 * highpart = (a >> 24) | ((i + 8) << 7);
1131 }
1132
1133 return (a & 0xff) | (i << 7);
1134 }
1135
1136 return FAIL;
1137 }
1138
1139 static int
1140 validate_offset_imm (val, hwse)
1141 unsigned int val;
1142 int hwse;
1143 {
1144 if ((hwse && val > 255) || val > 4095)
1145 return FAIL;
1146 return val;
1147 }
1148
1149
1150 static void
1151 s_req (a)
1152 int a;
1153 {
1154 as_bad (_("Invalid syntax for .req directive."));
1155 }
1156
1157 static void
1158 s_bss (ignore)
1159 int ignore;
1160 {
1161 /* We don't support putting frags in the BSS segment, we fake it by
1162 marking in_bss, then looking at s_skip for clues?.. */
1163 subseg_set (bss_section, 0);
1164 demand_empty_rest_of_line ();
1165 }
1166
1167 static void
1168 s_even (ignore)
1169 int ignore;
1170 {
1171 if (!need_pass_2) /* Never make frag if expect extra pass. */
1172 frag_align (1, 0, 0);
1173
1174 record_alignment (now_seg, 1);
1175
1176 demand_empty_rest_of_line ();
1177 }
1178
1179 static void
1180 s_ltorg (ignored)
1181 int ignored;
1182 {
1183 int lit_count = 0;
1184 char sym_name[20];
1185
1186 if (current_poolP == NULL)
1187 return;
1188
1189 /* Align pool as you have word accesses */
1190 /* Only make a frag if we have to ... */
1191 if (!need_pass_2)
1192 frag_align (2, 0, 0);
1193
1194 record_alignment (now_seg, 2);
1195
1196 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1197
1198 symbol_locate (current_poolP, sym_name, now_seg,
1199 (valueT) frag_now_fix (), frag_now);
1200 symbol_table_insert (current_poolP);
1201
1202 ARM_SET_THUMB (current_poolP, thumb_mode);
1203
1204 #if defined OBJ_COFF || defined OBJ_ELF
1205 ARM_SET_INTERWORK (current_poolP, support_interwork);
1206 #endif
1207
1208 while (lit_count < next_literal_pool_place)
1209 /* First output the expression in the instruction to the pool */
1210 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1211
1212 next_literal_pool_place = 0;
1213 current_poolP = NULL;
1214 }
1215
1216 static void
1217 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1218 int unused;
1219 {
1220 register int temp;
1221 register long temp_fill;
1222 long max_alignment = 15;
1223
1224 temp = get_absolute_expression ();
1225 if (temp > max_alignment)
1226 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1227 else if (temp < 0)
1228 {
1229 as_bad (_("Alignment negative. 0 assumed."));
1230 temp = 0;
1231 }
1232
1233 if (*input_line_pointer == ',')
1234 {
1235 input_line_pointer++;
1236 temp_fill = get_absolute_expression ();
1237 }
1238 else
1239 temp_fill = 0;
1240
1241 if (!temp)
1242 temp = 2;
1243
1244 /* Only make a frag if we HAVE to. . . */
1245 if (temp && !need_pass_2)
1246 frag_align (temp, (int) temp_fill, 0);
1247 demand_empty_rest_of_line ();
1248
1249 record_alignment (now_seg, temp);
1250 }
1251
1252 static void
1253 s_force_thumb (ignore)
1254 int ignore;
1255 {
1256 /* If we are not already in thumb mode go into it, EVEN if
1257 the target processor does not support thumb instructions.
1258 This is used by gcc/config/arm/lib1funcs.asm for example
1259 to compile interworking support functions even if the
1260 target processor should not support interworking. */
1261
1262 if (! thumb_mode)
1263 {
1264 thumb_mode = 2;
1265
1266 record_alignment (now_seg, 1);
1267 }
1268
1269 demand_empty_rest_of_line ();
1270 }
1271
1272 static void
1273 s_thumb_func (ignore)
1274 int ignore;
1275 {
1276 /* The following label is the name/address of the start of a Thumb function.
1277 We need to know this for the interworking support. */
1278
1279 label_is_thumb_function_name = true;
1280
1281 demand_empty_rest_of_line ();
1282 }
1283
1284 /* Perform a .set directive, but also mark the alias as
1285 being a thumb function. */
1286
1287 static void
1288 s_thumb_set (equiv)
1289 int equiv;
1290 {
1291 /* XXX the following is a duplicate of the code for s_set() in read.c
1292 We cannot just call that code as we need to get at the symbol that
1293 is created. */
1294 register char * name;
1295 register char delim;
1296 register char * end_name;
1297 register symbolS * symbolP;
1298
1299 /*
1300 * Especial apologies for the random logic:
1301 * this just grew, and could be parsed much more simply!
1302 * Dean in haste.
1303 */
1304 name = input_line_pointer;
1305 delim = get_symbol_end ();
1306 end_name = input_line_pointer;
1307 *end_name = delim;
1308
1309 SKIP_WHITESPACE ();
1310
1311 if (*input_line_pointer != ',')
1312 {
1313 *end_name = 0;
1314 as_bad (_("Expected comma after name \"%s\""), name);
1315 *end_name = delim;
1316 ignore_rest_of_line ();
1317 return;
1318 }
1319
1320 input_line_pointer++;
1321 *end_name = 0;
1322
1323 if (name[0] == '.' && name[1] == '\0')
1324 {
1325 /* XXX - this should not happen to .thumb_set */
1326 abort ();
1327 }
1328
1329 if ((symbolP = symbol_find (name)) == NULL
1330 && (symbolP = md_undefined_symbol (name)) == NULL)
1331 {
1332 #ifndef NO_LISTING
1333 /* When doing symbol listings, play games with dummy fragments living
1334 outside the normal fragment chain to record the file and line info
1335 for this symbol. */
1336 if (listing & LISTING_SYMBOLS)
1337 {
1338 extern struct list_info_struct * listing_tail;
1339 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1340 memset (dummy_frag, 0, sizeof(fragS));
1341 dummy_frag->fr_type = rs_fill;
1342 dummy_frag->line = listing_tail;
1343 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1344 dummy_frag->fr_symbol = symbolP;
1345 }
1346 else
1347 #endif
1348 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1349
1350 #ifdef OBJ_COFF
1351 /* "set" symbols are local unless otherwise specified. */
1352 SF_SET_LOCAL (symbolP);
1353 #endif /* OBJ_COFF */
1354 } /* make a new symbol */
1355
1356 symbol_table_insert (symbolP);
1357
1358 * end_name = delim;
1359
1360 if (equiv
1361 && S_IS_DEFINED (symbolP)
1362 && S_GET_SEGMENT (symbolP) != reg_section)
1363 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1364
1365 pseudo_set (symbolP);
1366
1367 demand_empty_rest_of_line ();
1368
1369 /* XXX Now we come to the Thumb specific bit of code. */
1370
1371 THUMB_SET_FUNC (symbolP, 1);
1372 ARM_SET_THUMB (symbolP, 1);
1373 #if defined OBJ_ELF || defined OBJ_COFF
1374 ARM_SET_INTERWORK (symbolP, support_interwork);
1375 #endif
1376 }
1377
1378 /* If we change section we must dump the literal pool first. */
1379 static void
1380 arm_s_text (ignore)
1381 int ignore;
1382 {
1383 if (now_seg != text_section)
1384 s_ltorg (0);
1385
1386 #ifdef OBJ_ELF
1387 obj_elf_text (ignore);
1388 #else
1389 s_text (ignore);
1390 #endif
1391 }
1392
1393 static void
1394 arm_s_data (ignore)
1395 int ignore;
1396 {
1397 if (flag_readonly_data_in_text)
1398 {
1399 if (now_seg != text_section)
1400 s_ltorg (0);
1401 }
1402 else if (now_seg != data_section)
1403 s_ltorg (0);
1404
1405 #ifdef OBJ_ELF
1406 obj_elf_data (ignore);
1407 #else
1408 s_data (ignore);
1409 #endif
1410 }
1411
1412 #ifdef OBJ_ELF
1413 static void
1414 arm_s_section (ignore)
1415 int ignore;
1416 {
1417 s_ltorg (0);
1418
1419 obj_elf_section (ignore);
1420 }
1421 #endif
1422
1423 static void
1424 opcode_select (width)
1425 int width;
1426 {
1427 switch (width)
1428 {
1429 case 16:
1430 if (! thumb_mode)
1431 {
1432 if (! (cpu_variant & ARM_THUMB))
1433 as_bad (_("selected processor does not support THUMB opcodes"));
1434 thumb_mode = 1;
1435 /* No need to force the alignment, since we will have been
1436 coming from ARM mode, which is word-aligned. */
1437 record_alignment (now_seg, 1);
1438 }
1439 break;
1440
1441 case 32:
1442 if (thumb_mode)
1443 {
1444 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1445 as_bad (_("selected processor does not support ARM opcodes"));
1446 thumb_mode = 0;
1447 if (!need_pass_2)
1448 frag_align (2, 0, 0);
1449 record_alignment (now_seg, 1);
1450 }
1451 break;
1452
1453 default:
1454 as_bad (_("invalid instruction size selected (%d)"), width);
1455 }
1456 }
1457
1458 static void
1459 s_arm (ignore)
1460 int ignore;
1461 {
1462 opcode_select (32);
1463 demand_empty_rest_of_line ();
1464 }
1465
1466 static void
1467 s_thumb (ignore)
1468 int ignore;
1469 {
1470 opcode_select (16);
1471 demand_empty_rest_of_line ();
1472 }
1473
1474 static void
1475 s_code (unused)
1476 int unused;
1477 {
1478 register int temp;
1479
1480 temp = get_absolute_expression ();
1481 switch (temp)
1482 {
1483 case 16:
1484 case 32:
1485 opcode_select (temp);
1486 break;
1487
1488 default:
1489 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1490 }
1491 }
1492
1493 static void
1494 end_of_line (str)
1495 char * str;
1496 {
1497 skip_whitespace (str);
1498
1499 if (* str != '\0')
1500 inst.error = _("Garbage following instruction");
1501 }
1502
1503 static int
1504 skip_past_comma (str)
1505 char ** str;
1506 {
1507 char *p = *str, c;
1508 int comma = 0;
1509
1510 while ((c = *p) == ' ' || c == ',')
1511 {
1512 p++;
1513 if (c == ',' && comma++)
1514 return FAIL;
1515 }
1516
1517 if (c == '\0')
1518 return FAIL;
1519
1520 *str = p;
1521 return comma ? SUCCESS : FAIL;
1522 }
1523
1524 /* A standard register must be given at this point.
1525 Shift is the place to put it in inst.instruction.
1526 Restores input start point on err.
1527 Returns the reg#, or FAIL. */
1528
1529 static int
1530 reg_required_here (str, shift)
1531 char ** str;
1532 int shift;
1533 {
1534 static char buff [128]; /* XXX */
1535 int reg;
1536 char * start = *str;
1537
1538 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1539 {
1540 if (shift >= 0)
1541 inst.instruction |= reg << shift;
1542 return reg;
1543 }
1544
1545 /* Restore the start point, we may have got a reg of the wrong class. */
1546 *str = start;
1547
1548 /* In the few cases where we might be able to accept something else
1549 this error can be overridden. */
1550 sprintf (buff, _("Register expected, not '%.100s'"), start);
1551 inst.error = buff;
1552
1553 return FAIL;
1554 }
1555
1556 static int
1557 psr_required_here (str, cpsr, spsr)
1558 char ** str;
1559 int cpsr;
1560 int spsr;
1561 {
1562 int psr;
1563 char * start = *str;
1564 psr = arm_psr_parse (str);
1565
1566 if (psr == cpsr || psr == spsr)
1567 {
1568 if (psr == spsr)
1569 inst.instruction |= 1 << 22;
1570
1571 return SUCCESS;
1572 }
1573
1574 /* In the few cases where we might be able to accept something else
1575 this error can be overridden. */
1576 inst.error = _("<psr(f)> expected");
1577
1578 /* Restore the start point. */
1579 *str = start;
1580 return FAIL;
1581 }
1582
1583 static int
1584 co_proc_number (str)
1585 char ** str;
1586 {
1587 int processor, pchar;
1588
1589 skip_whitespace (* str);
1590
1591 /* The data sheet seems to imply that just a number on its own is valid
1592 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1593 accept either. */
1594 if (**str == 'p' || **str == 'P')
1595 (*str)++;
1596
1597 pchar = *(*str)++;
1598 if (pchar >= '0' && pchar <= '9')
1599 {
1600 processor = pchar - '0';
1601 if (**str >= '0' && **str <= '9')
1602 {
1603 processor = processor * 10 + *(*str)++ - '0';
1604 if (processor > 15)
1605 {
1606 inst.error = _("Illegal co-processor number");
1607 return FAIL;
1608 }
1609 }
1610 }
1611 else
1612 {
1613 inst.error = _("Bad or missing co-processor number");
1614 return FAIL;
1615 }
1616
1617 inst.instruction |= processor << 8;
1618 return SUCCESS;
1619 }
1620
1621 static int
1622 cp_opc_expr (str, where, length)
1623 char ** str;
1624 int where;
1625 int length;
1626 {
1627 expressionS expr;
1628
1629 skip_whitespace (* str);
1630
1631 memset (&expr, '\0', sizeof (expr));
1632
1633 if (my_get_expression (&expr, str))
1634 return FAIL;
1635 if (expr.X_op != O_constant)
1636 {
1637 inst.error = _("bad or missing expression");
1638 return FAIL;
1639 }
1640
1641 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1642 {
1643 inst.error = _("immediate co-processor expression too large");
1644 return FAIL;
1645 }
1646
1647 inst.instruction |= expr.X_add_number << where;
1648 return SUCCESS;
1649 }
1650
1651 static int
1652 cp_reg_required_here (str, where)
1653 char ** str;
1654 int where;
1655 {
1656 int reg;
1657 char * start = *str;
1658
1659 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1660 {
1661 reg &= 15;
1662 inst.instruction |= reg << where;
1663 return reg;
1664 }
1665
1666 /* In the few cases where we might be able to accept something else
1667 this error can be overridden. */
1668 inst.error = _("Co-processor register expected");
1669
1670 /* Restore the start point. */
1671 *str = start;
1672 return FAIL;
1673 }
1674
1675 static int
1676 fp_reg_required_here (str, where)
1677 char ** str;
1678 int where;
1679 {
1680 int reg;
1681 char * start = *str;
1682
1683 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1684 {
1685 reg &= 7;
1686 inst.instruction |= reg << where;
1687 return reg;
1688 }
1689
1690 /* In the few cases where we might be able to accept something else
1691 this error can be overridden. */
1692 inst.error = _("Floating point register expected");
1693
1694 /* Restore the start point. */
1695 *str = start;
1696 return FAIL;
1697 }
1698
1699 static int
1700 cp_address_offset (str)
1701 char ** str;
1702 {
1703 int offset;
1704
1705 skip_whitespace (* str);
1706
1707 if (! is_immediate_prefix (**str))
1708 {
1709 inst.error = _("immediate expression expected");
1710 return FAIL;
1711 }
1712
1713 (*str)++;
1714
1715 if (my_get_expression (& inst.reloc.exp, str))
1716 return FAIL;
1717
1718 if (inst.reloc.exp.X_op == O_constant)
1719 {
1720 offset = inst.reloc.exp.X_add_number;
1721
1722 if (offset & 3)
1723 {
1724 inst.error = _("co-processor address must be word aligned");
1725 return FAIL;
1726 }
1727
1728 if (offset > 1023 || offset < -1023)
1729 {
1730 inst.error = _("offset too large");
1731 return FAIL;
1732 }
1733
1734 if (offset >= 0)
1735 inst.instruction |= INDEX_UP;
1736 else
1737 offset = -offset;
1738
1739 inst.instruction |= offset >> 2;
1740 }
1741 else
1742 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1743
1744 return SUCCESS;
1745 }
1746
1747 static int
1748 cp_address_required_here (str)
1749 char ** str;
1750 {
1751 char * p = * str;
1752 int pre_inc = 0;
1753 int write_back = 0;
1754
1755 if (*p == '[')
1756 {
1757 int reg;
1758
1759 p++;
1760 skip_whitespace (p);
1761
1762 if ((reg = reg_required_here (& p, 16)) == FAIL)
1763 return FAIL;
1764
1765 skip_whitespace (p);
1766
1767 if (*p == ']')
1768 {
1769 p++;
1770
1771 if (skip_past_comma (& p) == SUCCESS)
1772 {
1773 /* [Rn], #expr */
1774 write_back = WRITE_BACK;
1775
1776 if (reg == REG_PC)
1777 {
1778 inst.error = _("pc may not be used in post-increment");
1779 return FAIL;
1780 }
1781
1782 if (cp_address_offset (& p) == FAIL)
1783 return FAIL;
1784 }
1785 else
1786 pre_inc = PRE_INDEX | INDEX_UP;
1787 }
1788 else
1789 {
1790 /* '['Rn, #expr']'[!] */
1791
1792 if (skip_past_comma (& p) == FAIL)
1793 {
1794 inst.error = _("pre-indexed expression expected");
1795 return FAIL;
1796 }
1797
1798 pre_inc = PRE_INDEX;
1799
1800 if (cp_address_offset (& p) == FAIL)
1801 return FAIL;
1802
1803 skip_whitespace (p);
1804
1805 if (*p++ != ']')
1806 {
1807 inst.error = _("missing ]");
1808 return FAIL;
1809 }
1810
1811 skip_whitespace (p);
1812
1813 if (*p == '!')
1814 {
1815 if (reg == REG_PC)
1816 {
1817 inst.error = _("pc may not be used with write-back");
1818 return FAIL;
1819 }
1820
1821 p++;
1822 write_back = WRITE_BACK;
1823 }
1824 }
1825 }
1826 else
1827 {
1828 if (my_get_expression (&inst.reloc.exp, &p))
1829 return FAIL;
1830
1831 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1832 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1833 inst.reloc.pc_rel = 1;
1834 inst.instruction |= (REG_PC << 16);
1835 pre_inc = PRE_INDEX;
1836 }
1837
1838 inst.instruction |= write_back | pre_inc;
1839 *str = p;
1840 return SUCCESS;
1841 }
1842
1843 static void
1844 do_nop (str, flags)
1845 char * str;
1846 unsigned long flags;
1847 {
1848 /* Do nothing really. */
1849 inst.instruction |= flags; /* This is pointless. */
1850 end_of_line (str);
1851 return;
1852 }
1853
1854 static void
1855 do_mrs (str, flags)
1856 char *str;
1857 unsigned long flags;
1858 {
1859 /* Only one syntax. */
1860 skip_whitespace (str);
1861
1862 if (reg_required_here (&str, 12) == FAIL)
1863 {
1864 inst.error = BAD_ARGS;
1865 return;
1866 }
1867
1868 if (skip_past_comma (&str) == FAIL
1869 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1870 {
1871 inst.error = _("<psr> expected");
1872 return;
1873 }
1874
1875 inst.instruction |= flags;
1876 end_of_line (str);
1877 return;
1878 }
1879
1880 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
1881 static void
1882 do_msr (str, flags)
1883 char * str;
1884 unsigned long flags;
1885 {
1886 int reg;
1887
1888 skip_whitespace (str);
1889
1890 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1891 {
1892 inst.instruction |= PSR_ALL;
1893
1894 /* Sytax should be "<psr>, Rm" */
1895 if (skip_past_comma (&str) == FAIL
1896 || (reg = reg_required_here (&str, 0)) == FAIL)
1897 {
1898 inst.error = BAD_ARGS;
1899 return;
1900 }
1901 }
1902 else
1903 {
1904 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1905 inst.instruction |= PSR_FLAGS;
1906 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1907 inst.instruction |= PSR_CONTROL;
1908 else
1909 {
1910 inst.error = BAD_ARGS;
1911 return;
1912 }
1913
1914 if (skip_past_comma (&str) == FAIL)
1915 {
1916 inst.error = BAD_ARGS;
1917 return;
1918 }
1919
1920 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1921
1922 if ((reg = reg_required_here (& str, 0)) != FAIL)
1923 ;
1924 /* Immediate expression. */
1925 else if (is_immediate_prefix (* str))
1926 {
1927 str ++;
1928 inst.error = NULL;
1929
1930 if (my_get_expression (& inst.reloc.exp, & str))
1931 {
1932 inst.error = _("Register or shift expression expected");
1933 return;
1934 }
1935
1936 if (inst.reloc.exp.X_add_symbol)
1937 {
1938 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1939 inst.reloc.pc_rel = 0;
1940 }
1941 else
1942 {
1943 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1944 if (value == FAIL)
1945 {
1946 inst.error = _("Invalid constant");
1947 return;
1948 }
1949
1950 inst.instruction |= value;
1951 }
1952
1953 flags |= INST_IMMEDIATE;
1954 }
1955 else
1956 {
1957 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1958 return;
1959 }
1960 }
1961
1962 inst.error = NULL;
1963 inst.instruction |= flags;
1964 end_of_line (str);
1965 return;
1966 }
1967
1968 /* Long Multiply Parser
1969 UMULL RdLo, RdHi, Rm, Rs
1970 SMULL RdLo, RdHi, Rm, Rs
1971 UMLAL RdLo, RdHi, Rm, Rs
1972 SMLAL RdLo, RdHi, Rm, Rs
1973 */
1974 static void
1975 do_mull (str, flags)
1976 char * str;
1977 unsigned long flags;
1978 {
1979 int rdlo, rdhi, rm, rs;
1980
1981 /* Only one format "rdlo, rdhi, rm, rs" */
1982 skip_whitespace (str);
1983
1984 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1985 {
1986 inst.error = BAD_ARGS;
1987 return;
1988 }
1989
1990 if (skip_past_comma (&str) == FAIL
1991 || (rdhi = reg_required_here (&str, 16)) == FAIL)
1992 {
1993 inst.error = BAD_ARGS;
1994 return;
1995 }
1996
1997 if (skip_past_comma (&str) == FAIL
1998 || (rm = reg_required_here (&str, 0)) == FAIL)
1999 {
2000 inst.error = BAD_ARGS;
2001 return;
2002 }
2003
2004 /* rdhi, rdlo and rm must all be different */
2005 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2006 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2007
2008 if (skip_past_comma (&str) == FAIL
2009 || (rs = reg_required_here (&str, 8)) == FAIL)
2010 {
2011 inst.error = BAD_ARGS;
2012 return;
2013 }
2014
2015 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2016 {
2017 inst.error = BAD_PC;
2018 return;
2019 }
2020
2021 inst.instruction |= flags;
2022 end_of_line (str);
2023 return;
2024 }
2025
2026 static void
2027 do_mul (str, flags)
2028 char * str;
2029 unsigned long flags;
2030 {
2031 int rd, rm;
2032
2033 /* Only one format "rd, rm, rs" */
2034 skip_whitespace (str);
2035
2036 if ((rd = reg_required_here (&str, 16)) == FAIL)
2037 {
2038 inst.error = BAD_ARGS;
2039 return;
2040 }
2041
2042 if (rd == REG_PC)
2043 {
2044 inst.error = BAD_PC;
2045 return;
2046 }
2047
2048 if (skip_past_comma (&str) == FAIL
2049 || (rm = reg_required_here (&str, 0)) == FAIL)
2050 {
2051 inst.error = BAD_ARGS;
2052 return;
2053 }
2054
2055 if (rm == REG_PC)
2056 {
2057 inst.error = BAD_PC;
2058 return;
2059 }
2060
2061 if (rm == rd)
2062 as_tsktsk (_("rd and rm should be different in mul"));
2063
2064 if (skip_past_comma (&str) == FAIL
2065 || (rm = reg_required_here (&str, 8)) == FAIL)
2066 {
2067 inst.error = BAD_ARGS;
2068 return;
2069 }
2070
2071 if (rm == REG_PC)
2072 {
2073 inst.error = BAD_PC;
2074 return;
2075 }
2076
2077 inst.instruction |= flags;
2078 end_of_line (str);
2079 return;
2080 }
2081
2082 static void
2083 do_mla (str, flags)
2084 char * str;
2085 unsigned long flags;
2086 {
2087 int rd, rm;
2088
2089 /* Only one format "rd, rm, rs, rn" */
2090 skip_whitespace (str);
2091
2092 if ((rd = reg_required_here (&str, 16)) == FAIL)
2093 {
2094 inst.error = BAD_ARGS;
2095 return;
2096 }
2097
2098 if (rd == REG_PC)
2099 {
2100 inst.error = BAD_PC;
2101 return;
2102 }
2103
2104 if (skip_past_comma (&str) == FAIL
2105 || (rm = reg_required_here (&str, 0)) == FAIL)
2106 {
2107 inst.error = BAD_ARGS;
2108 return;
2109 }
2110
2111 if (rm == REG_PC)
2112 {
2113 inst.error = BAD_PC;
2114 return;
2115 }
2116
2117 if (rm == rd)
2118 as_tsktsk (_("rd and rm should be different in mla"));
2119
2120 if (skip_past_comma (&str) == FAIL
2121 || (rd = reg_required_here (&str, 8)) == FAIL
2122 || skip_past_comma (&str) == FAIL
2123 || (rm = reg_required_here (&str, 12)) == FAIL)
2124 {
2125 inst.error = BAD_ARGS;
2126 return;
2127 }
2128
2129 if (rd == REG_PC || rm == REG_PC)
2130 {
2131 inst.error = BAD_PC;
2132 return;
2133 }
2134
2135 inst.instruction |= flags;
2136 end_of_line (str);
2137 return;
2138 }
2139
2140 /* Returns the index into fp_values of a floating point number, or -1 if
2141 not in the table. */
2142 static int
2143 my_get_float_expression (str)
2144 char ** str;
2145 {
2146 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2147 char * save_in;
2148 expressionS exp;
2149 int i;
2150 int j;
2151
2152 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2153 /* Look for a raw floating point number */
2154 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2155 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
2156 {
2157 for (i = 0; i < NUM_FLOAT_VALS; i++)
2158 {
2159 for (j = 0; j < MAX_LITTLENUMS; j++)
2160 {
2161 if (words[j] != fp_values[i][j])
2162 break;
2163 }
2164
2165 if (j == MAX_LITTLENUMS)
2166 {
2167 *str = save_in;
2168 return i;
2169 }
2170 }
2171 }
2172
2173 /* Try and parse a more complex expression, this will probably fail
2174 unless the code uses a floating point prefix (eg "0f") */
2175 save_in = input_line_pointer;
2176 input_line_pointer = *str;
2177 if (expression (&exp) == absolute_section
2178 && exp.X_op == O_big
2179 && exp.X_add_number < 0)
2180 {
2181 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2182 Ditto for 15. */
2183 if (gen_to_words (words, 5, (long)15) == 0)
2184 {
2185 for (i = 0; i < NUM_FLOAT_VALS; i++)
2186 {
2187 for (j = 0; j < MAX_LITTLENUMS; j++)
2188 {
2189 if (words[j] != fp_values[i][j])
2190 break;
2191 }
2192
2193 if (j == MAX_LITTLENUMS)
2194 {
2195 *str = input_line_pointer;
2196 input_line_pointer = save_in;
2197 return i;
2198 }
2199 }
2200 }
2201 }
2202
2203 *str = input_line_pointer;
2204 input_line_pointer = save_in;
2205 return -1;
2206 }
2207
2208 /* Return true if anything in the expression is a bignum */
2209 static int
2210 walk_no_bignums (sp)
2211 symbolS * sp;
2212 {
2213 if (symbol_get_value_expression (sp)->X_op == O_big)
2214 return 1;
2215
2216 if (symbol_get_value_expression (sp)->X_add_symbol)
2217 {
2218 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2219 || (symbol_get_value_expression (sp)->X_op_symbol
2220 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2221 }
2222
2223 return 0;
2224 }
2225
2226 static int
2227 my_get_expression (ep, str)
2228 expressionS * ep;
2229 char ** str;
2230 {
2231 char * save_in;
2232 segT seg;
2233
2234 save_in = input_line_pointer;
2235 input_line_pointer = *str;
2236 seg = expression (ep);
2237
2238 #ifdef OBJ_AOUT
2239 if (seg != absolute_section
2240 && seg != text_section
2241 && seg != data_section
2242 && seg != bss_section
2243 && seg != undefined_section)
2244 {
2245 inst.error = _("bad_segment");
2246 *str = input_line_pointer;
2247 input_line_pointer = save_in;
2248 return 1;
2249 }
2250 #endif
2251
2252 /* Get rid of any bignums now, so that we don't generate an error for which
2253 we can't establish a line number later on. Big numbers are never valid
2254 in instructions, which is where this routine is always called. */
2255 if (ep->X_op == O_big
2256 || (ep->X_add_symbol
2257 && (walk_no_bignums (ep->X_add_symbol)
2258 || (ep->X_op_symbol
2259 && walk_no_bignums (ep->X_op_symbol)))))
2260 {
2261 inst.error = _("Invalid constant");
2262 *str = input_line_pointer;
2263 input_line_pointer = save_in;
2264 return 1;
2265 }
2266
2267 *str = input_line_pointer;
2268 input_line_pointer = save_in;
2269 return 0;
2270 }
2271
2272 /* unrestrict should be one if <shift> <register> is permitted for this
2273 instruction */
2274
2275 static int
2276 decode_shift (str, unrestrict)
2277 char ** str;
2278 int unrestrict;
2279 {
2280 struct asm_shift * shft;
2281 char * p;
2282 char c;
2283
2284 skip_whitespace (* str);
2285
2286 for (p = *str; isalpha (*p); p++)
2287 ;
2288
2289 if (p == *str)
2290 {
2291 inst.error = _("Shift expression expected");
2292 return FAIL;
2293 }
2294
2295 c = *p;
2296 *p = '\0';
2297 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2298 *p = c;
2299 if (shft)
2300 {
2301 if (!strncmp (*str, "rrx", 3)
2302 || !strncmp (*str, "RRX", 3))
2303 {
2304 *str = p;
2305 inst.instruction |= shft->value;
2306 return SUCCESS;
2307 }
2308
2309 skip_whitespace (p);
2310
2311 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2312 {
2313 inst.instruction |= shft->value | SHIFT_BY_REG;
2314 *str = p;
2315 return SUCCESS;
2316 }
2317 else if (is_immediate_prefix (* p))
2318 {
2319 inst.error = NULL;
2320 p++;
2321 if (my_get_expression (&inst.reloc.exp, &p))
2322 return FAIL;
2323
2324 /* Validate some simple #expressions */
2325 if (inst.reloc.exp.X_op == O_constant)
2326 {
2327 unsigned num = inst.reloc.exp.X_add_number;
2328
2329 /* Reject operations greater than 32, or lsl #32 */
2330 if (num > 32 || (num == 32 && shft->value == 0))
2331 {
2332 inst.error = _("Invalid immediate shift");
2333 return FAIL;
2334 }
2335
2336 /* Shifts of zero should be converted to lsl (which is zero)*/
2337 if (num == 0)
2338 {
2339 *str = p;
2340 return SUCCESS;
2341 }
2342
2343 /* Shifts of 32 are encoded as 0, for those shifts that
2344 support it. */
2345 if (num == 32)
2346 num = 0;
2347
2348 inst.instruction |= (num << 7) | shft->value;
2349 *str = p;
2350 return SUCCESS;
2351 }
2352
2353 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2354 inst.reloc.pc_rel = 0;
2355 inst.instruction |= shft->value;
2356 *str = p;
2357 return SUCCESS;
2358 }
2359 else
2360 {
2361 inst.error = unrestrict ? _("shift requires register or #expression")
2362 : _("shift requires #expression");
2363 *str = p;
2364 return FAIL;
2365 }
2366 }
2367
2368 inst.error = _("Shift expression expected");
2369 return FAIL;
2370 }
2371
2372 /* Do those data_ops which can take a negative immediate constant */
2373 /* by altering the instuction. A bit of a hack really */
2374 /* MOV <-> MVN
2375 AND <-> BIC
2376 ADC <-> SBC
2377 by inverting the second operand, and
2378 ADD <-> SUB
2379 CMP <-> CMN
2380 by negating the second operand.
2381 */
2382 static int
2383 negate_data_op (instruction, value)
2384 unsigned long * instruction;
2385 unsigned long value;
2386 {
2387 int op, new_inst;
2388 unsigned long negated, inverted;
2389
2390 negated = validate_immediate (-value);
2391 inverted = validate_immediate (~value);
2392
2393 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2394 switch (op)
2395 {
2396 /* First negates */
2397 case OPCODE_SUB: /* ADD <-> SUB */
2398 new_inst = OPCODE_ADD;
2399 value = negated;
2400 break;
2401
2402 case OPCODE_ADD:
2403 new_inst = OPCODE_SUB;
2404 value = negated;
2405 break;
2406
2407 case OPCODE_CMP: /* CMP <-> CMN */
2408 new_inst = OPCODE_CMN;
2409 value = negated;
2410 break;
2411
2412 case OPCODE_CMN:
2413 new_inst = OPCODE_CMP;
2414 value = negated;
2415 break;
2416
2417 /* Now Inverted ops */
2418 case OPCODE_MOV: /* MOV <-> MVN */
2419 new_inst = OPCODE_MVN;
2420 value = inverted;
2421 break;
2422
2423 case OPCODE_MVN:
2424 new_inst = OPCODE_MOV;
2425 value = inverted;
2426 break;
2427
2428 case OPCODE_AND: /* AND <-> BIC */
2429 new_inst = OPCODE_BIC;
2430 value = inverted;
2431 break;
2432
2433 case OPCODE_BIC:
2434 new_inst = OPCODE_AND;
2435 value = inverted;
2436 break;
2437
2438 case OPCODE_ADC: /* ADC <-> SBC */
2439 new_inst = OPCODE_SBC;
2440 value = inverted;
2441 break;
2442
2443 case OPCODE_SBC:
2444 new_inst = OPCODE_ADC;
2445 value = inverted;
2446 break;
2447
2448 /* We cannot do anything */
2449 default:
2450 return FAIL;
2451 }
2452
2453 if (value == FAIL)
2454 return FAIL;
2455
2456 *instruction &= OPCODE_MASK;
2457 *instruction |= new_inst << DATA_OP_SHIFT;
2458 return value;
2459 }
2460
2461 static int
2462 data_op2 (str)
2463 char ** str;
2464 {
2465 int value;
2466 expressionS expr;
2467
2468 skip_whitespace (* str);
2469
2470 if (reg_required_here (str, 0) != FAIL)
2471 {
2472 if (skip_past_comma (str) == SUCCESS)
2473 /* Shift operation on register. */
2474 return decode_shift (str, NO_SHIFT_RESTRICT);
2475
2476 return SUCCESS;
2477 }
2478 else
2479 {
2480 /* Immediate expression */
2481 if (is_immediate_prefix (**str))
2482 {
2483 (*str)++;
2484 inst.error = NULL;
2485
2486 if (my_get_expression (&inst.reloc.exp, str))
2487 return FAIL;
2488
2489 if (inst.reloc.exp.X_add_symbol)
2490 {
2491 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2492 inst.reloc.pc_rel = 0;
2493 }
2494 else
2495 {
2496 if (skip_past_comma (str) == SUCCESS)
2497 {
2498 /* #x, y -- ie explicit rotation by Y */
2499 if (my_get_expression (&expr, str))
2500 return FAIL;
2501
2502 if (expr.X_op != O_constant)
2503 {
2504 inst.error = _("Constant expression expected");
2505 return FAIL;
2506 }
2507
2508 /* Rotate must be a multiple of 2 */
2509 if (((unsigned) expr.X_add_number) > 30
2510 || (expr.X_add_number & 1) != 0
2511 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2512 {
2513 inst.error = _("Invalid constant");
2514 return FAIL;
2515 }
2516 inst.instruction |= INST_IMMEDIATE;
2517 inst.instruction |= inst.reloc.exp.X_add_number;
2518 inst.instruction |= expr.X_add_number << 7;
2519 return SUCCESS;
2520 }
2521
2522 /* Implicit rotation, select a suitable one */
2523 value = validate_immediate (inst.reloc.exp.X_add_number);
2524
2525 if (value == FAIL)
2526 {
2527 /* Can't be done, perhaps the code reads something like
2528 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2529 if ((value = negate_data_op (&inst.instruction,
2530 inst.reloc.exp.X_add_number))
2531 == FAIL)
2532 {
2533 inst.error = _("Invalid constant");
2534 return FAIL;
2535 }
2536 }
2537
2538 inst.instruction |= value;
2539 }
2540
2541 inst.instruction |= INST_IMMEDIATE;
2542 return SUCCESS;
2543 }
2544
2545 (*str)++;
2546 inst.error = _("Register or shift expression expected");
2547 return FAIL;
2548 }
2549 }
2550
2551 static int
2552 fp_op2 (str)
2553 char ** str;
2554 {
2555 skip_whitespace (* str);
2556
2557 if (fp_reg_required_here (str, 0) != FAIL)
2558 return SUCCESS;
2559 else
2560 {
2561 /* Immediate expression */
2562 if (*((*str)++) == '#')
2563 {
2564 int i;
2565
2566 inst.error = NULL;
2567
2568 skip_whitespace (* str);
2569
2570 /* First try and match exact strings, this is to guarantee that
2571 some formats will work even for cross assembly */
2572
2573 for (i = 0; fp_const[i]; i++)
2574 {
2575 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2576 {
2577 char *start = *str;
2578
2579 *str += strlen (fp_const[i]);
2580 if (is_end_of_line[(int)**str] || **str == '\0')
2581 {
2582 inst.instruction |= i + 8;
2583 return SUCCESS;
2584 }
2585 *str = start;
2586 }
2587 }
2588
2589 /* Just because we didn't get a match doesn't mean that the
2590 constant isn't valid, just that it is in a format that we
2591 don't automatically recognize. Try parsing it with
2592 the standard expression routines. */
2593 if ((i = my_get_float_expression (str)) >= 0)
2594 {
2595 inst.instruction |= i + 8;
2596 return SUCCESS;
2597 }
2598
2599 inst.error = _("Invalid floating point immediate expression");
2600 return FAIL;
2601 }
2602 inst.error = _("Floating point register or immediate expression expected");
2603 return FAIL;
2604 }
2605 }
2606
2607 static void
2608 do_arit (str, flags)
2609 char * str;
2610 unsigned long flags;
2611 {
2612 skip_whitespace (str);
2613
2614 if (reg_required_here (&str, 12) == FAIL
2615 || skip_past_comma (&str) == FAIL
2616 || reg_required_here (&str, 16) == FAIL
2617 || skip_past_comma (&str) == FAIL
2618 || data_op2 (&str) == FAIL)
2619 {
2620 if (!inst.error)
2621 inst.error = BAD_ARGS;
2622 return;
2623 }
2624
2625 inst.instruction |= flags;
2626 end_of_line (str);
2627 return;
2628 }
2629
2630 static void
2631 do_adr (str, flags)
2632 char * str;
2633 unsigned long flags;
2634 {
2635 /* This is a pseudo-op of the form "adr rd, label" to be converted
2636 into a relative address of the form "add rd, pc, #label-.-8" */
2637
2638 skip_whitespace (str);
2639
2640 if (reg_required_here (&str, 12) == FAIL
2641 || skip_past_comma (&str) == FAIL
2642 || my_get_expression (&inst.reloc.exp, &str))
2643 {
2644 if (!inst.error)
2645 inst.error = BAD_ARGS;
2646 return;
2647 }
2648 /* Frag hacking will turn this into a sub instruction if the offset turns
2649 out to be negative. */
2650 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2651 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2652 inst.reloc.pc_rel = 1;
2653 inst.instruction |= flags;
2654 end_of_line (str);
2655 return;
2656 }
2657
2658 static void
2659 do_adrl (str, flags)
2660 char * str;
2661 unsigned long flags;
2662 {
2663 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2664 into a relative address of the form:
2665 add rd, pc, #low(label-.-8)"
2666 add rd, rd, #high(label-.-8)" */
2667
2668 skip_whitespace (str);
2669
2670 if (reg_required_here (& str, 12) == FAIL
2671 || skip_past_comma (& str) == FAIL
2672 || my_get_expression (& inst.reloc.exp, & str))
2673 {
2674 if (!inst.error)
2675 inst.error = BAD_ARGS;
2676 return;
2677 }
2678
2679 end_of_line (str);
2680
2681 /* Frag hacking will turn this into a sub instruction if the offset turns
2682 out to be negative. */
2683 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2684 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2685 inst.reloc.pc_rel = 1;
2686 inst.instruction |= flags;
2687 inst.size = INSN_SIZE * 2;
2688
2689 return;
2690 }
2691
2692 static void
2693 do_cmp (str, flags)
2694 char * str;
2695 unsigned long flags;
2696 {
2697 skip_whitespace (str);
2698
2699 if (reg_required_here (&str, 16) == FAIL)
2700 {
2701 if (!inst.error)
2702 inst.error = BAD_ARGS;
2703 return;
2704 }
2705
2706 if (skip_past_comma (&str) == FAIL
2707 || data_op2 (&str) == FAIL)
2708 {
2709 if (!inst.error)
2710 inst.error = BAD_ARGS;
2711 return;
2712 }
2713
2714 inst.instruction |= flags;
2715 if ((flags & 0x0000f000) == 0)
2716 inst.instruction |= CONDS_BIT;
2717
2718 end_of_line (str);
2719 return;
2720 }
2721
2722 static void
2723 do_mov (str, flags)
2724 char * str;
2725 unsigned long flags;
2726 {
2727 skip_whitespace (str);
2728
2729 if (reg_required_here (&str, 12) == FAIL)
2730 {
2731 if (!inst.error)
2732 inst.error = BAD_ARGS;
2733 return;
2734 }
2735
2736 if (skip_past_comma (&str) == FAIL
2737 || data_op2 (&str) == FAIL)
2738 {
2739 if (!inst.error)
2740 inst.error = BAD_ARGS;
2741 return;
2742 }
2743
2744 inst.instruction |= flags;
2745 end_of_line (str);
2746 return;
2747 }
2748
2749 static int
2750 ldst_extend (str, hwse)
2751 char ** str;
2752 int hwse;
2753 {
2754 int add = INDEX_UP;
2755
2756 switch (**str)
2757 {
2758 case '#':
2759 case '$':
2760 (*str)++;
2761 if (my_get_expression (& inst.reloc.exp, str))
2762 return FAIL;
2763
2764 if (inst.reloc.exp.X_op == O_constant)
2765 {
2766 int value = inst.reloc.exp.X_add_number;
2767
2768 if ((hwse && (value < -255 || value > 255))
2769 || (value < -4095 || value > 4095))
2770 {
2771 inst.error = _("address offset too large");
2772 return FAIL;
2773 }
2774
2775 if (value < 0)
2776 {
2777 value = -value;
2778 add = 0;
2779 }
2780
2781 /* Halfword and signextension instructions have the
2782 immediate value split across bits 11..8 and bits 3..0 */
2783 if (hwse)
2784 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2785 else
2786 inst.instruction |= add | value;
2787 }
2788 else
2789 {
2790 if (hwse)
2791 {
2792 inst.instruction |= HWOFFSET_IMM;
2793 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2794 }
2795 else
2796 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2797 inst.reloc.pc_rel = 0;
2798 }
2799 return SUCCESS;
2800
2801 case '-':
2802 add = 0; /* and fall through */
2803 case '+':
2804 (*str)++; /* and fall through */
2805 default:
2806 if (reg_required_here (str, 0) == FAIL)
2807 return FAIL;
2808
2809 if (hwse)
2810 inst.instruction |= add;
2811 else
2812 {
2813 inst.instruction |= add | OFFSET_REG;
2814 if (skip_past_comma (str) == SUCCESS)
2815 return decode_shift (str, SHIFT_RESTRICT);
2816 }
2817
2818 return SUCCESS;
2819 }
2820 }
2821
2822 static void
2823 do_ldst (str, flags)
2824 char * str;
2825 unsigned long flags;
2826 {
2827 int halfword = 0;
2828 int pre_inc = 0;
2829 int conflict_reg;
2830 int value;
2831
2832 /* This is not ideal, but it is the simplest way of dealing with the
2833 ARM7T halfword instructions (since they use a different
2834 encoding, but the same mnemonic): */
2835 halfword = (flags & 0x80000000) != 0;
2836 if (halfword)
2837 {
2838 /* This is actually a load/store of a halfword, or a
2839 signed-extension load */
2840 if ((cpu_variant & ARM_HALFWORD) == 0)
2841 {
2842 inst.error
2843 = _("Processor does not support halfwords or signed bytes");
2844 return;
2845 }
2846
2847 inst.instruction = (inst.instruction & COND_MASK)
2848 | (flags & ~COND_MASK);
2849
2850 flags = 0;
2851 }
2852
2853 skip_whitespace (str);
2854
2855 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2856 {
2857 if (!inst.error)
2858 inst.error = BAD_ARGS;
2859 return;
2860 }
2861
2862 if (skip_past_comma (& str) == FAIL)
2863 {
2864 inst.error = _("Address expected");
2865 return;
2866 }
2867
2868 if (*str == '[')
2869 {
2870 int reg;
2871
2872 str++;
2873
2874 skip_whitespace (str);
2875
2876 if ((reg = reg_required_here (&str, 16)) == FAIL)
2877 return;
2878
2879 /* Conflicts can occur on stores as well as loads. */
2880 conflict_reg = (conflict_reg == reg);
2881
2882 skip_whitespace (str);
2883
2884 if (*str == ']')
2885 {
2886 str ++;
2887
2888 if (skip_past_comma (&str) == SUCCESS)
2889 {
2890 /* [Rn],... (post inc) */
2891 if (ldst_extend (&str, halfword) == FAIL)
2892 return;
2893 if (conflict_reg)
2894 as_warn (_("%s register same as write-back base"),
2895 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2896 }
2897 else
2898 {
2899 /* [Rn] */
2900 if (halfword)
2901 inst.instruction |= HWOFFSET_IMM;
2902
2903 skip_whitespace (str);
2904
2905 if (*str == '!')
2906 {
2907 if (conflict_reg)
2908 as_warn (_("%s register same as write-back base"),
2909 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2910 str++;
2911 inst.instruction |= WRITE_BACK;
2912 }
2913
2914 flags |= INDEX_UP;
2915 if (! (flags & TRANS_BIT))
2916 pre_inc = 1;
2917 }
2918 }
2919 else
2920 {
2921 /* [Rn,...] */
2922 if (skip_past_comma (&str) == FAIL)
2923 {
2924 inst.error = _("pre-indexed expression expected");
2925 return;
2926 }
2927
2928 pre_inc = 1;
2929 if (ldst_extend (&str, halfword) == FAIL)
2930 return;
2931
2932 skip_whitespace (str);
2933
2934 if (*str++ != ']')
2935 {
2936 inst.error = _("missing ]");
2937 return;
2938 }
2939
2940 skip_whitespace (str);
2941
2942 if (*str == '!')
2943 {
2944 if (conflict_reg)
2945 as_warn (_("%s register same as write-back base"),
2946 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2947 str++;
2948 inst.instruction |= WRITE_BACK;
2949 }
2950 }
2951 }
2952 else if (*str == '=')
2953 {
2954 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2955 str++;
2956
2957 skip_whitespace (str);
2958
2959 if (my_get_expression (&inst.reloc.exp, &str))
2960 return;
2961
2962 if (inst.reloc.exp.X_op != O_constant
2963 && inst.reloc.exp.X_op != O_symbol)
2964 {
2965 inst.error = _("Constant expression expected");
2966 return;
2967 }
2968
2969 if (inst.reloc.exp.X_op == O_constant
2970 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2971 {
2972 /* This can be done with a mov instruction */
2973 inst.instruction &= LITERAL_MASK;
2974 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2975 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2976 end_of_line(str);
2977 return;
2978 }
2979 else
2980 {
2981 /* Insert into literal pool */
2982 if (add_to_lit_pool () == FAIL)
2983 {
2984 if (!inst.error)
2985 inst.error = _("literal pool insertion failed");
2986 return;
2987 }
2988
2989 /* Change the instruction exp to point to the pool */
2990 if (halfword)
2991 {
2992 inst.instruction |= HWOFFSET_IMM;
2993 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
2994 }
2995 else
2996 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
2997 inst.reloc.pc_rel = 1;
2998 inst.instruction |= (REG_PC << 16);
2999 pre_inc = 1;
3000 }
3001 }
3002 else
3003 {
3004 if (my_get_expression (&inst.reloc.exp, &str))
3005 return;
3006
3007 if (halfword)
3008 {
3009 inst.instruction |= HWOFFSET_IMM;
3010 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3011 }
3012 else
3013 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3014 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3015 inst.reloc.pc_rel = 1;
3016 inst.instruction |= (REG_PC << 16);
3017 pre_inc = 1;
3018 }
3019
3020 if (pre_inc && (flags & TRANS_BIT))
3021 inst.error = _("Pre-increment instruction with translate");
3022
3023 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3024 end_of_line (str);
3025 return;
3026 }
3027
3028 static long
3029 reg_list (strp)
3030 char ** strp;
3031 {
3032 char * str = *strp;
3033 long range = 0;
3034 int another_range;
3035
3036 /* We come back here if we get ranges concatenated by '+' or '|' */
3037 do
3038 {
3039 another_range = 0;
3040
3041 if (*str == '{')
3042 {
3043 int in_range = 0;
3044 int cur_reg = -1;
3045
3046 str++;
3047 do
3048 {
3049 int reg;
3050
3051 skip_whitespace (str);
3052
3053 if ((reg = reg_required_here (& str, -1)) == FAIL)
3054 return FAIL;
3055
3056 if (in_range)
3057 {
3058 int i;
3059
3060 if (reg <= cur_reg)
3061 {
3062 inst.error = _("Bad range in register list");
3063 return FAIL;
3064 }
3065
3066 for (i = cur_reg + 1; i < reg; i++)
3067 {
3068 if (range & (1 << i))
3069 as_tsktsk
3070 (_("Warning: Duplicated register (r%d) in register list"),
3071 i);
3072 else
3073 range |= 1 << i;
3074 }
3075 in_range = 0;
3076 }
3077
3078 if (range & (1 << reg))
3079 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3080 reg);
3081 else if (reg <= cur_reg)
3082 as_tsktsk (_("Warning: Register range not in ascending order"));
3083
3084 range |= 1 << reg;
3085 cur_reg = reg;
3086 } while (skip_past_comma (&str) != FAIL
3087 || (in_range = 1, *str++ == '-'));
3088 str--;
3089 skip_whitespace (str);
3090
3091 if (*str++ != '}')
3092 {
3093 inst.error = _("Missing `}'");
3094 return FAIL;
3095 }
3096 }
3097 else
3098 {
3099 expressionS expr;
3100
3101 if (my_get_expression (&expr, &str))
3102 return FAIL;
3103
3104 if (expr.X_op == O_constant)
3105 {
3106 if (expr.X_add_number
3107 != (expr.X_add_number & 0x0000ffff))
3108 {
3109 inst.error = _("invalid register mask");
3110 return FAIL;
3111 }
3112
3113 if ((range & expr.X_add_number) != 0)
3114 {
3115 int regno = range & expr.X_add_number;
3116
3117 regno &= -regno;
3118 regno = (1 << regno) - 1;
3119 as_tsktsk
3120 (_("Warning: Duplicated register (r%d) in register list"),
3121 regno);
3122 }
3123
3124 range |= expr.X_add_number;
3125 }
3126 else
3127 {
3128 if (inst.reloc.type != 0)
3129 {
3130 inst.error = _("expression too complex");
3131 return FAIL;
3132 }
3133
3134 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3135 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3136 inst.reloc.pc_rel = 0;
3137 }
3138 }
3139
3140 skip_whitespace (str);
3141
3142 if (*str == '|' || *str == '+')
3143 {
3144 str++;
3145 another_range = 1;
3146 }
3147 } while (another_range);
3148
3149 *strp = str;
3150 return range;
3151 }
3152
3153 static void
3154 do_ldmstm (str, flags)
3155 char * str;
3156 unsigned long flags;
3157 {
3158 int base_reg;
3159 long range;
3160
3161 skip_whitespace (str);
3162
3163 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3164 return;
3165
3166 if (base_reg == REG_PC)
3167 {
3168 inst.error = _("r15 not allowed as base register");
3169 return;
3170 }
3171
3172 skip_whitespace (str);
3173
3174 if (*str == '!')
3175 {
3176 flags |= WRITE_BACK;
3177 str++;
3178 }
3179
3180 if (skip_past_comma (&str) == FAIL
3181 || (range = reg_list (&str)) == FAIL)
3182 {
3183 if (! inst.error)
3184 inst.error = BAD_ARGS;
3185 return;
3186 }
3187
3188 if (*str == '^')
3189 {
3190 str++;
3191 flags |= LDM_TYPE_2_OR_3;
3192 }
3193
3194 inst.instruction |= flags | range;
3195 end_of_line (str);
3196 return;
3197 }
3198
3199 static void
3200 do_swi (str, flags)
3201 char * str;
3202 unsigned long flags;
3203 {
3204 skip_whitespace (str);
3205
3206 /* Allow optional leading '#'. */
3207 if (is_immediate_prefix (*str))
3208 str++;
3209
3210 if (my_get_expression (& inst.reloc.exp, & str))
3211 return;
3212
3213 inst.reloc.type = BFD_RELOC_ARM_SWI;
3214 inst.reloc.pc_rel = 0;
3215 inst.instruction |= flags;
3216
3217 end_of_line (str);
3218
3219 return;
3220 }
3221
3222 static void
3223 do_swap (str, flags)
3224 char * str;
3225 unsigned long flags;
3226 {
3227 int reg;
3228
3229 skip_whitespace (str);
3230
3231 if ((reg = reg_required_here (&str, 12)) == FAIL)
3232 return;
3233
3234 if (reg == REG_PC)
3235 {
3236 inst.error = _("r15 not allowed in swap");
3237 return;
3238 }
3239
3240 if (skip_past_comma (&str) == FAIL
3241 || (reg = reg_required_here (&str, 0)) == FAIL)
3242 {
3243 if (!inst.error)
3244 inst.error = BAD_ARGS;
3245 return;
3246 }
3247
3248 if (reg == REG_PC)
3249 {
3250 inst.error = _("r15 not allowed in swap");
3251 return;
3252 }
3253
3254 if (skip_past_comma (&str) == FAIL
3255 || *str++ != '[')
3256 {
3257 inst.error = BAD_ARGS;
3258 return;
3259 }
3260
3261 skip_whitespace (str);
3262
3263 if ((reg = reg_required_here (&str, 16)) == FAIL)
3264 return;
3265
3266 if (reg == REG_PC)
3267 {
3268 inst.error = BAD_PC;
3269 return;
3270 }
3271
3272 skip_whitespace (str);
3273
3274 if (*str++ != ']')
3275 {
3276 inst.error = _("missing ]");
3277 return;
3278 }
3279
3280 inst.instruction |= flags;
3281 end_of_line (str);
3282 return;
3283 }
3284
3285 static void
3286 do_branch (str, flags)
3287 char * str;
3288 unsigned long flags;
3289 {
3290 if (my_get_expression (&inst.reloc.exp, &str))
3291 return;
3292
3293 #ifdef OBJ_ELF
3294 {
3295 char * save_in;
3296
3297 /* ScottB: February 5, 1998 */
3298 /* Check to see of PLT32 reloc required for the instruction. */
3299
3300 /* arm_parse_reloc() works on input_line_pointer.
3301 We actually want to parse the operands to the branch instruction
3302 passed in 'str'. Save the input pointer and restore it later. */
3303 save_in = input_line_pointer;
3304 input_line_pointer = str;
3305 if (inst.reloc.exp.X_op == O_symbol
3306 && *str == '('
3307 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3308 {
3309 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3310 inst.reloc.pc_rel = 0;
3311 /* Modify str to point to after parsed operands, otherwise
3312 end_of_line() will complain about the (PLT) left in str. */
3313 str = input_line_pointer;
3314 }
3315 else
3316 {
3317 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3318 inst.reloc.pc_rel = 1;
3319 }
3320 input_line_pointer = save_in;
3321 }
3322 #else
3323 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3324 inst.reloc.pc_rel = 1;
3325 #endif /* OBJ_ELF */
3326
3327 end_of_line (str);
3328 return;
3329 }
3330
3331 static void
3332 do_bx (str, flags)
3333 char * str;
3334 unsigned long flags;
3335 {
3336 int reg;
3337
3338 skip_whitespace (str);
3339
3340 if ((reg = reg_required_here (&str, 0)) == FAIL)
3341 {
3342 inst.error = BAD_ARGS;
3343 return;
3344 }
3345
3346 if (reg == REG_PC)
3347 inst.error = BAD_PC;
3348
3349 end_of_line (str);
3350 }
3351
3352 static void
3353 do_cdp (str, flags)
3354 char * str;
3355 unsigned long flags;
3356 {
3357 /* Co-processor data operation.
3358 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3359 skip_whitespace (str);
3360
3361 if (co_proc_number (&str) == FAIL)
3362 {
3363 if (!inst.error)
3364 inst.error = BAD_ARGS;
3365 return;
3366 }
3367
3368 if (skip_past_comma (&str) == FAIL
3369 || cp_opc_expr (&str, 20,4) == FAIL)
3370 {
3371 if (!inst.error)
3372 inst.error = BAD_ARGS;
3373 return;
3374 }
3375
3376 if (skip_past_comma (&str) == FAIL
3377 || cp_reg_required_here (&str, 12) == FAIL)
3378 {
3379 if (!inst.error)
3380 inst.error = BAD_ARGS;
3381 return;
3382 }
3383
3384 if (skip_past_comma (&str) == FAIL
3385 || cp_reg_required_here (&str, 16) == FAIL)
3386 {
3387 if (!inst.error)
3388 inst.error = BAD_ARGS;
3389 return;
3390 }
3391
3392 if (skip_past_comma (&str) == FAIL
3393 || cp_reg_required_here (&str, 0) == FAIL)
3394 {
3395 if (!inst.error)
3396 inst.error = BAD_ARGS;
3397 return;
3398 }
3399
3400 if (skip_past_comma (&str) == SUCCESS)
3401 {
3402 if (cp_opc_expr (&str, 5, 3) == FAIL)
3403 {
3404 if (!inst.error)
3405 inst.error = BAD_ARGS;
3406 return;
3407 }
3408 }
3409
3410 end_of_line (str);
3411 return;
3412 }
3413
3414 static void
3415 do_lstc (str, flags)
3416 char * str;
3417 unsigned long flags;
3418 {
3419 /* Co-processor register load/store.
3420 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3421
3422 skip_whitespace (str);
3423
3424 if (co_proc_number (&str) == FAIL)
3425 {
3426 if (!inst.error)
3427 inst.error = BAD_ARGS;
3428 return;
3429 }
3430
3431 if (skip_past_comma (&str) == FAIL
3432 || cp_reg_required_here (&str, 12) == FAIL)
3433 {
3434 if (!inst.error)
3435 inst.error = BAD_ARGS;
3436 return;
3437 }
3438
3439 if (skip_past_comma (&str) == FAIL
3440 || cp_address_required_here (&str) == FAIL)
3441 {
3442 if (! inst.error)
3443 inst.error = BAD_ARGS;
3444 return;
3445 }
3446
3447 inst.instruction |= flags;
3448 end_of_line (str);
3449 return;
3450 }
3451
3452 static void
3453 do_co_reg (str, flags)
3454 char * str;
3455 unsigned long flags;
3456 {
3457 /* Co-processor register transfer.
3458 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3459
3460 skip_whitespace (str);
3461
3462 if (co_proc_number (&str) == FAIL)
3463 {
3464 if (!inst.error)
3465 inst.error = BAD_ARGS;
3466 return;
3467 }
3468
3469 if (skip_past_comma (&str) == FAIL
3470 || cp_opc_expr (&str, 21, 3) == FAIL)
3471 {
3472 if (!inst.error)
3473 inst.error = BAD_ARGS;
3474 return;
3475 }
3476
3477 if (skip_past_comma (&str) == FAIL
3478 || reg_required_here (&str, 12) == FAIL)
3479 {
3480 if (!inst.error)
3481 inst.error = BAD_ARGS;
3482 return;
3483 }
3484
3485 if (skip_past_comma (&str) == FAIL
3486 || cp_reg_required_here (&str, 16) == FAIL)
3487 {
3488 if (!inst.error)
3489 inst.error = BAD_ARGS;
3490 return;
3491 }
3492
3493 if (skip_past_comma (&str) == FAIL
3494 || cp_reg_required_here (&str, 0) == FAIL)
3495 {
3496 if (!inst.error)
3497 inst.error = BAD_ARGS;
3498 return;
3499 }
3500
3501 if (skip_past_comma (&str) == SUCCESS)
3502 {
3503 if (cp_opc_expr (&str, 5, 3) == FAIL)
3504 {
3505 if (!inst.error)
3506 inst.error = BAD_ARGS;
3507 return;
3508 }
3509 }
3510 if (flags)
3511 {
3512 inst.error = BAD_COND;
3513 }
3514
3515 end_of_line (str);
3516 return;
3517 }
3518
3519 static void
3520 do_fp_ctrl (str, flags)
3521 char * str;
3522 unsigned long flags;
3523 {
3524 /* FP control registers.
3525 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3526
3527 skip_whitespace (str);
3528
3529 if (reg_required_here (&str, 12) == FAIL)
3530 {
3531 if (!inst.error)
3532 inst.error = BAD_ARGS;
3533 return;
3534 }
3535
3536 end_of_line (str);
3537 return;
3538 }
3539
3540 static void
3541 do_fp_ldst (str, flags)
3542 char * str;
3543 unsigned long flags;
3544 {
3545 skip_whitespace (str);
3546
3547 switch (inst.suffix)
3548 {
3549 case SUFF_S:
3550 break;
3551 case SUFF_D:
3552 inst.instruction |= CP_T_X;
3553 break;
3554 case SUFF_E:
3555 inst.instruction |= CP_T_Y;
3556 break;
3557 case SUFF_P:
3558 inst.instruction |= CP_T_X | CP_T_Y;
3559 break;
3560 default:
3561 abort ();
3562 }
3563
3564 if (fp_reg_required_here (&str, 12) == FAIL)
3565 {
3566 if (!inst.error)
3567 inst.error = BAD_ARGS;
3568 return;
3569 }
3570
3571 if (skip_past_comma (&str) == FAIL
3572 || cp_address_required_here (&str) == FAIL)
3573 {
3574 if (!inst.error)
3575 inst.error = BAD_ARGS;
3576 return;
3577 }
3578
3579 end_of_line (str);
3580 }
3581
3582 static void
3583 do_fp_ldmstm (str, flags)
3584 char * str;
3585 unsigned long flags;
3586 {
3587 int num_regs;
3588
3589 skip_whitespace (str);
3590
3591 if (fp_reg_required_here (&str, 12) == FAIL)
3592 {
3593 if (! inst.error)
3594 inst.error = BAD_ARGS;
3595 return;
3596 }
3597
3598 /* Get Number of registers to transfer */
3599 if (skip_past_comma (&str) == FAIL
3600 || my_get_expression (&inst.reloc.exp, &str))
3601 {
3602 if (! inst.error)
3603 inst.error = _("constant expression expected");
3604 return;
3605 }
3606
3607 if (inst.reloc.exp.X_op != O_constant)
3608 {
3609 inst.error = _("Constant value required for number of registers");
3610 return;
3611 }
3612
3613 num_regs = inst.reloc.exp.X_add_number;
3614
3615 if (num_regs < 1 || num_regs > 4)
3616 {
3617 inst.error = _("number of registers must be in the range [1:4]");
3618 return;
3619 }
3620
3621 switch (num_regs)
3622 {
3623 case 1:
3624 inst.instruction |= CP_T_X;
3625 break;
3626 case 2:
3627 inst.instruction |= CP_T_Y;
3628 break;
3629 case 3:
3630 inst.instruction |= CP_T_Y | CP_T_X;
3631 break;
3632 case 4:
3633 break;
3634 default:
3635 abort ();
3636 }
3637
3638 if (flags)
3639 {
3640 int reg;
3641 int write_back;
3642 int offset;
3643
3644 /* The instruction specified "ea" or "fd", so we can only accept
3645 [Rn]{!}. The instruction does not really support stacking or
3646 unstacking, so we have to emulate these by setting appropriate
3647 bits and offsets. */
3648 if (skip_past_comma (&str) == FAIL
3649 || *str != '[')
3650 {
3651 if (! inst.error)
3652 inst.error = BAD_ARGS;
3653 return;
3654 }
3655
3656 str++;
3657 skip_whitespace (str);
3658
3659 if ((reg = reg_required_here (&str, 16)) == FAIL)
3660 return;
3661
3662 skip_whitespace (str);
3663
3664 if (*str != ']')
3665 {
3666 inst.error = BAD_ARGS;
3667 return;
3668 }
3669
3670 str++;
3671 if (*str == '!')
3672 {
3673 write_back = 1;
3674 str++;
3675 if (reg == REG_PC)
3676 {
3677 inst.error = _("R15 not allowed as base register with write-back");
3678 return;
3679 }
3680 }
3681 else
3682 write_back = 0;
3683
3684 if (flags & CP_T_Pre)
3685 {
3686 /* Pre-decrement */
3687 offset = 3 * num_regs;
3688 if (write_back)
3689 flags |= CP_T_WB;
3690 }
3691 else
3692 {
3693 /* Post-increment */
3694 if (write_back)
3695 {
3696 flags |= CP_T_WB;
3697 offset = 3 * num_regs;
3698 }
3699 else
3700 {
3701 /* No write-back, so convert this into a standard pre-increment
3702 instruction -- aesthetically more pleasing. */
3703 flags = CP_T_Pre | CP_T_UD;
3704 offset = 0;
3705 }
3706 }
3707
3708 inst.instruction |= flags | offset;
3709 }
3710 else if (skip_past_comma (&str) == FAIL
3711 || cp_address_required_here (&str) == FAIL)
3712 {
3713 if (! inst.error)
3714 inst.error = BAD_ARGS;
3715 return;
3716 }
3717
3718 end_of_line (str);
3719 }
3720
3721 static void
3722 do_fp_dyadic (str, flags)
3723 char * str;
3724 unsigned long flags;
3725 {
3726 skip_whitespace (str);
3727
3728 switch (inst.suffix)
3729 {
3730 case SUFF_S:
3731 break;
3732 case SUFF_D:
3733 inst.instruction |= 0x00000080;
3734 break;
3735 case SUFF_E:
3736 inst.instruction |= 0x00080000;
3737 break;
3738 default:
3739 abort ();
3740 }
3741
3742 if (fp_reg_required_here (&str, 12) == FAIL)
3743 {
3744 if (! inst.error)
3745 inst.error = BAD_ARGS;
3746 return;
3747 }
3748
3749 if (skip_past_comma (&str) == FAIL
3750 || fp_reg_required_here (&str, 16) == FAIL)
3751 {
3752 if (! inst.error)
3753 inst.error = BAD_ARGS;
3754 return;
3755 }
3756
3757 if (skip_past_comma (&str) == FAIL
3758 || fp_op2 (&str) == FAIL)
3759 {
3760 if (! inst.error)
3761 inst.error = BAD_ARGS;
3762 return;
3763 }
3764
3765 inst.instruction |= flags;
3766 end_of_line (str);
3767 return;
3768 }
3769
3770 static void
3771 do_fp_monadic (str, flags)
3772 char * str;
3773 unsigned long flags;
3774 {
3775 skip_whitespace (str);
3776
3777 switch (inst.suffix)
3778 {
3779 case SUFF_S:
3780 break;
3781 case SUFF_D:
3782 inst.instruction |= 0x00000080;
3783 break;
3784 case SUFF_E:
3785 inst.instruction |= 0x00080000;
3786 break;
3787 default:
3788 abort ();
3789 }
3790
3791 if (fp_reg_required_here (&str, 12) == FAIL)
3792 {
3793 if (! inst.error)
3794 inst.error = BAD_ARGS;
3795 return;
3796 }
3797
3798 if (skip_past_comma (&str) == FAIL
3799 || fp_op2 (&str) == FAIL)
3800 {
3801 if (! inst.error)
3802 inst.error = BAD_ARGS;
3803 return;
3804 }
3805
3806 inst.instruction |= flags;
3807 end_of_line (str);
3808 return;
3809 }
3810
3811 static void
3812 do_fp_cmp (str, flags)
3813 char * str;
3814 unsigned long flags;
3815 {
3816 skip_whitespace (str);
3817
3818 if (fp_reg_required_here (&str, 16) == FAIL)
3819 {
3820 if (! inst.error)
3821 inst.error = BAD_ARGS;
3822 return;
3823 }
3824
3825 if (skip_past_comma (&str) == FAIL
3826 || fp_op2 (&str) == FAIL)
3827 {
3828 if (! inst.error)
3829 inst.error = BAD_ARGS;
3830 return;
3831 }
3832
3833 inst.instruction |= flags;
3834 end_of_line (str);
3835 return;
3836 }
3837
3838 static void
3839 do_fp_from_reg (str, flags)
3840 char * str;
3841 unsigned long flags;
3842 {
3843 skip_whitespace (str);
3844
3845 switch (inst.suffix)
3846 {
3847 case SUFF_S:
3848 break;
3849 case SUFF_D:
3850 inst.instruction |= 0x00000080;
3851 break;
3852 case SUFF_E:
3853 inst.instruction |= 0x00080000;
3854 break;
3855 default:
3856 abort ();
3857 }
3858
3859 if (fp_reg_required_here (&str, 16) == FAIL)
3860 {
3861 if (! inst.error)
3862 inst.error = BAD_ARGS;
3863 return;
3864 }
3865
3866 if (skip_past_comma (&str) == FAIL
3867 || reg_required_here (&str, 12) == FAIL)
3868 {
3869 if (! inst.error)
3870 inst.error = BAD_ARGS;
3871 return;
3872 }
3873
3874 inst.instruction |= flags;
3875 end_of_line (str);
3876 return;
3877 }
3878
3879 static void
3880 do_fp_to_reg (str, flags)
3881 char * str;
3882 unsigned long flags;
3883 {
3884 skip_whitespace (str);
3885
3886 if (reg_required_here (&str, 12) == FAIL)
3887 return;
3888
3889 if (skip_past_comma (&str) == FAIL
3890 || fp_reg_required_here (&str, 0) == FAIL)
3891 {
3892 if (! inst.error)
3893 inst.error = BAD_ARGS;
3894 return;
3895 }
3896
3897 inst.instruction |= flags;
3898 end_of_line (str);
3899 return;
3900 }
3901
3902 /* Thumb specific routines */
3903
3904 /* Parse and validate that a register is of the right form, this saves
3905 repeated checking of this information in many similar cases.
3906 Unlike the 32-bit case we do not insert the register into the opcode
3907 here, since the position is often unknown until the full instruction
3908 has been parsed. */
3909 static int
3910 thumb_reg (strp, hi_lo)
3911 char ** strp;
3912 int hi_lo;
3913 {
3914 int reg;
3915
3916 if ((reg = reg_required_here (strp, -1)) == FAIL)
3917 return FAIL;
3918
3919 switch (hi_lo)
3920 {
3921 case THUMB_REG_LO:
3922 if (reg > 7)
3923 {
3924 inst.error = _("lo register required");
3925 return FAIL;
3926 }
3927 break;
3928
3929 case THUMB_REG_HI:
3930 if (reg < 8)
3931 {
3932 inst.error = _("hi register required");
3933 return FAIL;
3934 }
3935 break;
3936
3937 default:
3938 break;
3939 }
3940
3941 return reg;
3942 }
3943
3944 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3945 was SUB. */
3946 static void
3947 thumb_add_sub (str, subtract)
3948 char * str;
3949 int subtract;
3950 {
3951 int Rd, Rs, Rn = FAIL;
3952
3953 skip_whitespace (str);
3954
3955 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3956 || skip_past_comma (&str) == FAIL)
3957 {
3958 if (! inst.error)
3959 inst.error = BAD_ARGS;
3960 return;
3961 }
3962
3963 if (is_immediate_prefix (*str))
3964 {
3965 Rs = Rd;
3966 str++;
3967 if (my_get_expression (&inst.reloc.exp, &str))
3968 return;
3969 }
3970 else
3971 {
3972 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3973 return;
3974
3975 if (skip_past_comma (&str) == FAIL)
3976 {
3977 /* Two operand format, shuffle the registers and pretend there
3978 are 3 */
3979 Rn = Rs;
3980 Rs = Rd;
3981 }
3982 else if (is_immediate_prefix (*str))
3983 {
3984 str++;
3985 if (my_get_expression (&inst.reloc.exp, &str))
3986 return;
3987 }
3988 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3989 return;
3990 }
3991
3992 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3993 for the latter case, EXPR contains the immediate that was found. */
3994 if (Rn != FAIL)
3995 {
3996 /* All register format. */
3997 if (Rd > 7 || Rs > 7 || Rn > 7)
3998 {
3999 if (Rs != Rd)
4000 {
4001 inst.error = _("dest and source1 must be the same register");
4002 return;
4003 }
4004
4005 /* Can't do this for SUB */
4006 if (subtract)
4007 {
4008 inst.error = _("subtract valid only on lo regs");
4009 return;
4010 }
4011
4012 inst.instruction = (T_OPCODE_ADD_HI
4013 | (Rd > 7 ? THUMB_H1 : 0)
4014 | (Rn > 7 ? THUMB_H2 : 0));
4015 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4016 }
4017 else
4018 {
4019 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4020 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4021 }
4022 }
4023 else
4024 {
4025 /* Immediate expression, now things start to get nasty. */
4026
4027 /* First deal with HI regs, only very restricted cases allowed:
4028 Adjusting SP, and using PC or SP to get an address. */
4029 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4030 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4031 {
4032 inst.error = _("invalid Hi register with immediate");
4033 return;
4034 }
4035
4036 if (inst.reloc.exp.X_op != O_constant)
4037 {
4038 /* Value isn't known yet, all we can do is store all the fragments
4039 we know about in the instruction and let the reloc hacking
4040 work it all out. */
4041 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4042 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4043 }
4044 else
4045 {
4046 int offset = inst.reloc.exp.X_add_number;
4047
4048 if (subtract)
4049 offset = -offset;
4050
4051 if (offset < 0)
4052 {
4053 offset = -offset;
4054 subtract = 1;
4055
4056 /* Quick check, in case offset is MIN_INT */
4057 if (offset < 0)
4058 {
4059 inst.error = _("immediate value out of range");
4060 return;
4061 }
4062 }
4063 else
4064 subtract = 0;
4065
4066 if (Rd == REG_SP)
4067 {
4068 if (offset & ~0x1fc)
4069 {
4070 inst.error = _("invalid immediate value for stack adjust");
4071 return;
4072 }
4073 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4074 inst.instruction |= offset >> 2;
4075 }
4076 else if (Rs == REG_PC || Rs == REG_SP)
4077 {
4078 if (subtract
4079 || (offset & ~0x3fc))
4080 {
4081 inst.error = _("invalid immediate for address calculation");
4082 return;
4083 }
4084 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4085 : T_OPCODE_ADD_SP);
4086 inst.instruction |= (Rd << 8) | (offset >> 2);
4087 }
4088 else if (Rs == Rd)
4089 {
4090 if (offset & ~0xff)
4091 {
4092 inst.error = _("immediate value out of range");
4093 return;
4094 }
4095 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4096 inst.instruction |= (Rd << 8) | offset;
4097 }
4098 else
4099 {
4100 if (offset & ~0x7)
4101 {
4102 inst.error = _("immediate value out of range");
4103 return;
4104 }
4105 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4106 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4107 }
4108 }
4109 }
4110 end_of_line (str);
4111 }
4112
4113 static void
4114 thumb_shift (str, shift)
4115 char * str;
4116 int shift;
4117 {
4118 int Rd, Rs, Rn = FAIL;
4119
4120 skip_whitespace (str);
4121
4122 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4123 || skip_past_comma (&str) == FAIL)
4124 {
4125 if (! inst.error)
4126 inst.error = BAD_ARGS;
4127 return;
4128 }
4129
4130 if (is_immediate_prefix (*str))
4131 {
4132 /* Two operand immediate format, set Rs to Rd. */
4133 Rs = Rd;
4134 str++;
4135 if (my_get_expression (&inst.reloc.exp, &str))
4136 return;
4137 }
4138 else
4139 {
4140 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4141 return;
4142
4143 if (skip_past_comma (&str) == FAIL)
4144 {
4145 /* Two operand format, shuffle the registers and pretend there
4146 are 3 */
4147 Rn = Rs;
4148 Rs = Rd;
4149 }
4150 else if (is_immediate_prefix (*str))
4151 {
4152 str++;
4153 if (my_get_expression (&inst.reloc.exp, &str))
4154 return;
4155 }
4156 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4157 return;
4158 }
4159
4160 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4161 for the latter case, EXPR contains the immediate that was found. */
4162
4163 if (Rn != FAIL)
4164 {
4165 if (Rs != Rd)
4166 {
4167 inst.error = _("source1 and dest must be same register");
4168 return;
4169 }
4170
4171 switch (shift)
4172 {
4173 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4174 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4175 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4176 }
4177
4178 inst.instruction |= Rd | (Rn << 3);
4179 }
4180 else
4181 {
4182 switch (shift)
4183 {
4184 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4185 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4186 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4187 }
4188
4189 if (inst.reloc.exp.X_op != O_constant)
4190 {
4191 /* Value isn't known yet, create a dummy reloc and let reloc
4192 hacking fix it up */
4193
4194 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4195 }
4196 else
4197 {
4198 unsigned shift_value = inst.reloc.exp.X_add_number;
4199
4200 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4201 {
4202 inst.error = _("Invalid immediate for shift");
4203 return;
4204 }
4205
4206 /* Shifts of zero are handled by converting to LSL */
4207 if (shift_value == 0)
4208 inst.instruction = T_OPCODE_LSL_I;
4209
4210 /* Shifts of 32 are encoded as a shift of zero */
4211 if (shift_value == 32)
4212 shift_value = 0;
4213
4214 inst.instruction |= shift_value << 6;
4215 }
4216
4217 inst.instruction |= Rd | (Rs << 3);
4218 }
4219 end_of_line (str);
4220 }
4221
4222 static void
4223 thumb_mov_compare (str, move)
4224 char * str;
4225 int move;
4226 {
4227 int Rd, Rs = FAIL;
4228
4229 skip_whitespace (str);
4230
4231 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4232 || skip_past_comma (&str) == FAIL)
4233 {
4234 if (! inst.error)
4235 inst.error = BAD_ARGS;
4236 return;
4237 }
4238
4239 if (is_immediate_prefix (*str))
4240 {
4241 str++;
4242 if (my_get_expression (&inst.reloc.exp, &str))
4243 return;
4244 }
4245 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4246 return;
4247
4248 if (Rs != FAIL)
4249 {
4250 if (Rs < 8 && Rd < 8)
4251 {
4252 if (move == THUMB_MOVE)
4253 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4254 since a MOV instruction produces unpredictable results */
4255 inst.instruction = T_OPCODE_ADD_I3;
4256 else
4257 inst.instruction = T_OPCODE_CMP_LR;
4258 inst.instruction |= Rd | (Rs << 3);
4259 }
4260 else
4261 {
4262 if (move == THUMB_MOVE)
4263 inst.instruction = T_OPCODE_MOV_HR;
4264 else
4265 inst.instruction = T_OPCODE_CMP_HR;
4266
4267 if (Rd > 7)
4268 inst.instruction |= THUMB_H1;
4269
4270 if (Rs > 7)
4271 inst.instruction |= THUMB_H2;
4272
4273 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4274 }
4275 }
4276 else
4277 {
4278 if (Rd > 7)
4279 {
4280 inst.error = _("only lo regs allowed with immediate");
4281 return;
4282 }
4283
4284 if (move == THUMB_MOVE)
4285 inst.instruction = T_OPCODE_MOV_I8;
4286 else
4287 inst.instruction = T_OPCODE_CMP_I8;
4288
4289 inst.instruction |= Rd << 8;
4290
4291 if (inst.reloc.exp.X_op != O_constant)
4292 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4293 else
4294 {
4295 unsigned value = inst.reloc.exp.X_add_number;
4296
4297 if (value > 255)
4298 {
4299 inst.error = _("invalid immediate");
4300 return;
4301 }
4302
4303 inst.instruction |= value;
4304 }
4305 }
4306
4307 end_of_line (str);
4308 }
4309
4310 static void
4311 thumb_load_store (str, load_store, size)
4312 char * str;
4313 int load_store;
4314 int size;
4315 {
4316 int Rd, Rb, Ro = FAIL;
4317
4318 skip_whitespace (str);
4319
4320 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4321 || skip_past_comma (&str) == FAIL)
4322 {
4323 if (! inst.error)
4324 inst.error = BAD_ARGS;
4325 return;
4326 }
4327
4328 if (*str == '[')
4329 {
4330 str++;
4331 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4332 return;
4333
4334 if (skip_past_comma (&str) != FAIL)
4335 {
4336 if (is_immediate_prefix (*str))
4337 {
4338 str++;
4339 if (my_get_expression (&inst.reloc.exp, &str))
4340 return;
4341 }
4342 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4343 return;
4344 }
4345 else
4346 {
4347 inst.reloc.exp.X_op = O_constant;
4348 inst.reloc.exp.X_add_number = 0;
4349 }
4350
4351 if (*str != ']')
4352 {
4353 inst.error = _("expected ']'");
4354 return;
4355 }
4356 str++;
4357 }
4358 else if (*str == '=')
4359 {
4360 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4361 str++;
4362
4363 skip_whitespace (str);
4364
4365 if (my_get_expression (& inst.reloc.exp, & str))
4366 return;
4367
4368 end_of_line (str);
4369
4370 if ( inst.reloc.exp.X_op != O_constant
4371 && inst.reloc.exp.X_op != O_symbol)
4372 {
4373 inst.error = "Constant expression expected";
4374 return;
4375 }
4376
4377 if (inst.reloc.exp.X_op == O_constant
4378 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4379 {
4380 /* This can be done with a mov instruction */
4381
4382 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4383 inst.instruction |= inst.reloc.exp.X_add_number;
4384 return;
4385 }
4386
4387 /* Insert into literal pool */
4388 if (add_to_lit_pool () == FAIL)
4389 {
4390 if (!inst.error)
4391 inst.error = "literal pool insertion failed";
4392 return;
4393 }
4394
4395 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4396 inst.reloc.pc_rel = 1;
4397 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4398 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4399
4400 return;
4401 }
4402 else
4403 {
4404 if (my_get_expression (&inst.reloc.exp, &str))
4405 return;
4406
4407 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4408 inst.reloc.pc_rel = 1;
4409 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4410 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4411 end_of_line (str);
4412 return;
4413 }
4414
4415 if (Rb == REG_PC || Rb == REG_SP)
4416 {
4417 if (size != THUMB_WORD)
4418 {
4419 inst.error = _("byte or halfword not valid for base register");
4420 return;
4421 }
4422 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4423 {
4424 inst.error = _("R15 based store not allowed");
4425 return;
4426 }
4427 else if (Ro != FAIL)
4428 {
4429 inst.error = _("Invalid base register for register offset");
4430 return;
4431 }
4432
4433 if (Rb == REG_PC)
4434 inst.instruction = T_OPCODE_LDR_PC;
4435 else if (load_store == THUMB_LOAD)
4436 inst.instruction = T_OPCODE_LDR_SP;
4437 else
4438 inst.instruction = T_OPCODE_STR_SP;
4439
4440 inst.instruction |= Rd << 8;
4441 if (inst.reloc.exp.X_op == O_constant)
4442 {
4443 unsigned offset = inst.reloc.exp.X_add_number;
4444
4445 if (offset & ~0x3fc)
4446 {
4447 inst.error = _("invalid offset");
4448 return;
4449 }
4450
4451 inst.instruction |= offset >> 2;
4452 }
4453 else
4454 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4455 }
4456 else if (Rb > 7)
4457 {
4458 inst.error = _("invalid base register in load/store");
4459 return;
4460 }
4461 else if (Ro == FAIL)
4462 {
4463 /* Immediate offset */
4464 if (size == THUMB_WORD)
4465 inst.instruction = (load_store == THUMB_LOAD
4466 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4467 else if (size == THUMB_HALFWORD)
4468 inst.instruction = (load_store == THUMB_LOAD
4469 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4470 else
4471 inst.instruction = (load_store == THUMB_LOAD
4472 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4473
4474 inst.instruction |= Rd | (Rb << 3);
4475
4476 if (inst.reloc.exp.X_op == O_constant)
4477 {
4478 unsigned offset = inst.reloc.exp.X_add_number;
4479
4480 if (offset & ~(0x1f << size))
4481 {
4482 inst.error = _("Invalid offset");
4483 return;
4484 }
4485 inst.instruction |= (offset >> size) << 6;
4486 }
4487 else
4488 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4489 }
4490 else
4491 {
4492 /* Register offset */
4493 if (size == THUMB_WORD)
4494 inst.instruction = (load_store == THUMB_LOAD
4495 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4496 else if (size == THUMB_HALFWORD)
4497 inst.instruction = (load_store == THUMB_LOAD
4498 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4499 else
4500 inst.instruction = (load_store == THUMB_LOAD
4501 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4502
4503 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4504 }
4505
4506 end_of_line (str);
4507 }
4508
4509 static void
4510 do_t_nop (str)
4511 char * str;
4512 {
4513 /* Do nothing */
4514 end_of_line (str);
4515 return;
4516 }
4517
4518 /* Handle the Format 4 instructions that do not have equivalents in other
4519 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4520 BIC and MVN. */
4521 static void
4522 do_t_arit (str)
4523 char * str;
4524 {
4525 int Rd, Rs, Rn;
4526
4527 skip_whitespace (str);
4528
4529 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4530 || skip_past_comma (&str) == FAIL
4531 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4532 {
4533 inst.error = BAD_ARGS;
4534 return;
4535 }
4536
4537 if (skip_past_comma (&str) != FAIL)
4538 {
4539 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4540 (It isn't allowed for CMP either, but that isn't handled by this
4541 function.) */
4542 if (inst.instruction == T_OPCODE_TST
4543 || inst.instruction == T_OPCODE_CMN
4544 || inst.instruction == T_OPCODE_NEG
4545 || inst.instruction == T_OPCODE_MVN)
4546 {
4547 inst.error = BAD_ARGS;
4548 return;
4549 }
4550
4551 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4552 return;
4553
4554 if (Rs != Rd)
4555 {
4556 inst.error = _("dest and source1 one must be the same register");
4557 return;
4558 }
4559 Rs = Rn;
4560 }
4561
4562 if (inst.instruction == T_OPCODE_MUL
4563 && Rs == Rd)
4564 as_tsktsk (_("Rs and Rd must be different in MUL"));
4565
4566 inst.instruction |= Rd | (Rs << 3);
4567 end_of_line (str);
4568 }
4569
4570 static void
4571 do_t_add (str)
4572 char * str;
4573 {
4574 thumb_add_sub (str, 0);
4575 }
4576
4577 static void
4578 do_t_asr (str)
4579 char * str;
4580 {
4581 thumb_shift (str, THUMB_ASR);
4582 }
4583
4584 static void
4585 do_t_branch9 (str)
4586 char * str;
4587 {
4588 if (my_get_expression (&inst.reloc.exp, &str))
4589 return;
4590 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4591 inst.reloc.pc_rel = 1;
4592 end_of_line (str);
4593 }
4594
4595 static void
4596 do_t_branch12 (str)
4597 char * str;
4598 {
4599 if (my_get_expression (&inst.reloc.exp, &str))
4600 return;
4601 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4602 inst.reloc.pc_rel = 1;
4603 end_of_line (str);
4604 }
4605
4606 /* Find the real, Thumb encoded start of a Thumb function. */
4607
4608 static symbolS *
4609 find_real_start (symbolP)
4610 symbolS * symbolP;
4611 {
4612 char * real_start;
4613 const char * name = S_GET_NAME (symbolP);
4614 symbolS * new_target;
4615
4616 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4617 #define STUB_NAME ".real_start_of"
4618
4619 if (name == NULL)
4620 abort();
4621
4622 /* Names that start with '.' are local labels, not function entry points.
4623 The compiler may generate BL instructions to these labels because it
4624 needs to perform a branch to a far away location. */
4625 if (name[0] == '.')
4626 return symbolP;
4627
4628 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4629 sprintf (real_start, "%s%s", STUB_NAME, name);
4630
4631 new_target = symbol_find (real_start);
4632
4633 if (new_target == NULL)
4634 {
4635 as_warn ("Failed to find real start of function: %s\n", name);
4636 new_target = symbolP;
4637 }
4638
4639 free (real_start);
4640
4641 return new_target;
4642 }
4643
4644
4645 static void
4646 do_t_branch23 (str)
4647 char * str;
4648 {
4649 if (my_get_expression (& inst.reloc.exp, & str))
4650 return;
4651
4652 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4653 inst.reloc.pc_rel = 1;
4654 end_of_line (str);
4655
4656 /* If the destination of the branch is a defined symbol which does not have
4657 the THUMB_FUNC attribute, then we must be calling a function which has
4658 the (interfacearm) attribute. We look for the Thumb entry point to that
4659 function and change the branch to refer to that function instead. */
4660 if ( inst.reloc.exp.X_op == O_symbol
4661 && inst.reloc.exp.X_add_symbol != NULL
4662 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4663 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4664 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4665 }
4666
4667 static void
4668 do_t_bx (str)
4669 char * str;
4670 {
4671 int reg;
4672
4673 skip_whitespace (str);
4674
4675 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4676 return;
4677
4678 /* This sets THUMB_H2 from the top bit of reg. */
4679 inst.instruction |= reg << 3;
4680
4681 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4682 should cause the alignment to be checked once it is known. This is
4683 because BX PC only works if the instruction is word aligned. */
4684
4685 end_of_line (str);
4686 }
4687
4688 static void
4689 do_t_compare (str)
4690 char * str;
4691 {
4692 thumb_mov_compare (str, THUMB_COMPARE);
4693 }
4694
4695 static void
4696 do_t_ldmstm (str)
4697 char * str;
4698 {
4699 int Rb;
4700 long range;
4701
4702 skip_whitespace (str);
4703
4704 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4705 return;
4706
4707 if (*str != '!')
4708 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4709 else
4710 str++;
4711
4712 if (skip_past_comma (&str) == FAIL
4713 || (range = reg_list (&str)) == FAIL)
4714 {
4715 if (! inst.error)
4716 inst.error = BAD_ARGS;
4717 return;
4718 }
4719
4720 if (inst.reloc.type != BFD_RELOC_NONE)
4721 {
4722 /* This really doesn't seem worth it. */
4723 inst.reloc.type = BFD_RELOC_NONE;
4724 inst.error = _("Expression too complex");
4725 return;
4726 }
4727
4728 if (range & ~0xff)
4729 {
4730 inst.error = _("only lo-regs valid in load/store multiple");
4731 return;
4732 }
4733
4734 inst.instruction |= (Rb << 8) | range;
4735 end_of_line (str);
4736 }
4737
4738 static void
4739 do_t_ldr (str)
4740 char * str;
4741 {
4742 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4743 }
4744
4745 static void
4746 do_t_ldrb (str)
4747 char * str;
4748 {
4749 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4750 }
4751
4752 static void
4753 do_t_ldrh (str)
4754 char * str;
4755 {
4756 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4757 }
4758
4759 static void
4760 do_t_lds (str)
4761 char * str;
4762 {
4763 int Rd, Rb, Ro;
4764
4765 skip_whitespace (str);
4766
4767 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4768 || skip_past_comma (&str) == FAIL
4769 || *str++ != '['
4770 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4771 || skip_past_comma (&str) == FAIL
4772 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4773 || *str++ != ']')
4774 {
4775 if (! inst.error)
4776 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4777 return;
4778 }
4779
4780 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4781 end_of_line (str);
4782 }
4783
4784 static void
4785 do_t_lsl (str)
4786 char * str;
4787 {
4788 thumb_shift (str, THUMB_LSL);
4789 }
4790
4791 static void
4792 do_t_lsr (str)
4793 char * str;
4794 {
4795 thumb_shift (str, THUMB_LSR);
4796 }
4797
4798 static void
4799 do_t_mov (str)
4800 char * str;
4801 {
4802 thumb_mov_compare (str, THUMB_MOVE);
4803 }
4804
4805 static void
4806 do_t_push_pop (str)
4807 char * str;
4808 {
4809 long range;
4810
4811 skip_whitespace (str);
4812
4813 if ((range = reg_list (&str)) == FAIL)
4814 {
4815 if (! inst.error)
4816 inst.error = BAD_ARGS;
4817 return;
4818 }
4819
4820 if (inst.reloc.type != BFD_RELOC_NONE)
4821 {
4822 /* This really doesn't seem worth it. */
4823 inst.reloc.type = BFD_RELOC_NONE;
4824 inst.error = _("Expression too complex");
4825 return;
4826 }
4827
4828 if (range & ~0xff)
4829 {
4830 if ((inst.instruction == T_OPCODE_PUSH
4831 && (range & ~0xff) == 1 << REG_LR)
4832 || (inst.instruction == T_OPCODE_POP
4833 && (range & ~0xff) == 1 << REG_PC))
4834 {
4835 inst.instruction |= THUMB_PP_PC_LR;
4836 range &= 0xff;
4837 }
4838 else
4839 {
4840 inst.error = _("invalid register list to push/pop instruction");
4841 return;
4842 }
4843 }
4844
4845 inst.instruction |= range;
4846 end_of_line (str);
4847 }
4848
4849 static void
4850 do_t_str (str)
4851 char * str;
4852 {
4853 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4854 }
4855
4856 static void
4857 do_t_strb (str)
4858 char * str;
4859 {
4860 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4861 }
4862
4863 static void
4864 do_t_strh (str)
4865 char * str;
4866 {
4867 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4868 }
4869
4870 static void
4871 do_t_sub (str)
4872 char * str;
4873 {
4874 thumb_add_sub (str, 1);
4875 }
4876
4877 static void
4878 do_t_swi (str)
4879 char * str;
4880 {
4881 skip_whitespace (str);
4882
4883 if (my_get_expression (&inst.reloc.exp, &str))
4884 return;
4885
4886 inst.reloc.type = BFD_RELOC_ARM_SWI;
4887 end_of_line (str);
4888 return;
4889 }
4890
4891 static void
4892 do_t_adr (str)
4893 char * str;
4894 {
4895 /* This is a pseudo-op of the form "adr rd, label" to be converted
4896 into a relative address of the form "add rd, pc, #label-.-4" */
4897 skip_whitespace (str);
4898
4899 if (reg_required_here (&str, 4) == FAIL /* Store Rd in temporary location inside instruction. */
4900 || skip_past_comma (&str) == FAIL
4901 || my_get_expression (&inst.reloc.exp, &str))
4902 {
4903 if (!inst.error)
4904 inst.error = BAD_ARGS;
4905 return;
4906 }
4907
4908 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4909 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust */
4910 inst.reloc.pc_rel = 1;
4911 inst.instruction |= REG_PC; /* Rd is already placed into the instruction */
4912 end_of_line (str);
4913 }
4914
4915 static void
4916 insert_reg (entry)
4917 int entry;
4918 {
4919 int len = strlen (reg_table[entry].name) + 2;
4920 char * buf = (char *) xmalloc (len);
4921 char * buf2 = (char *) xmalloc (len);
4922 int i = 0;
4923
4924 #ifdef REGISTER_PREFIX
4925 buf[i++] = REGISTER_PREFIX;
4926 #endif
4927
4928 strcpy (buf + i, reg_table[entry].name);
4929
4930 for (i = 0; buf[i]; i++)
4931 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4932
4933 buf2[i] = '\0';
4934
4935 hash_insert (arm_reg_hsh, buf, (PTR) &reg_table[entry]);
4936 hash_insert (arm_reg_hsh, buf2, (PTR) &reg_table[entry]);
4937 }
4938
4939 static void
4940 insert_reg_alias (str, regnum)
4941 char *str;
4942 int regnum;
4943 {
4944 struct reg_entry *new =
4945 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4946 char *name = xmalloc (strlen (str) + 1);
4947 strcpy (name, str);
4948
4949 new->name = name;
4950 new->number = regnum;
4951
4952 hash_insert (arm_reg_hsh, name, (PTR) new);
4953 }
4954
4955 static void
4956 set_constant_flonums ()
4957 {
4958 int i;
4959
4960 for (i = 0; i < NUM_FLOAT_VALS; i++)
4961 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4962 abort ();
4963 }
4964
4965 void
4966 md_begin ()
4967 {
4968 int i;
4969
4970 if ( (arm_ops_hsh = hash_new ()) == NULL
4971 || (arm_tops_hsh = hash_new ()) == NULL
4972 || (arm_cond_hsh = hash_new ()) == NULL
4973 || (arm_shift_hsh = hash_new ()) == NULL
4974 || (arm_reg_hsh = hash_new ()) == NULL
4975 || (arm_psr_hsh = hash_new ()) == NULL)
4976 as_fatal (_("Virtual memory exhausted"));
4977
4978 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4979 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
4980 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
4981 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
4982 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
4983 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
4984 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
4985 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
4986 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
4987 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
4988
4989 for (i = 0; reg_table[i].name; i++)
4990 insert_reg (i);
4991
4992 set_constant_flonums ();
4993
4994 #if defined OBJ_COFF || defined OBJ_ELF
4995 {
4996 unsigned int flags = 0;
4997
4998 /* Set the flags in the private structure */
4999 if (uses_apcs_26) flags |= F_APCS26;
5000 if (support_interwork) flags |= F_INTERWORK;
5001 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5002 if (pic_code) flags |= F_PIC;
5003 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5004
5005 bfd_set_private_flags (stdoutput, flags);
5006 }
5007 #endif
5008
5009 {
5010 unsigned mach;
5011
5012 /* Record the CPU type as well */
5013 switch (cpu_variant & ARM_CPU_MASK)
5014 {
5015 case ARM_2:
5016 mach = bfd_mach_arm_2;
5017 break;
5018
5019 case ARM_3: /* also ARM_250 */
5020 mach = bfd_mach_arm_2a;
5021 break;
5022
5023 default:
5024 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined */
5025 mach = bfd_mach_arm_4;
5026 break;
5027
5028 case ARM_7: /* also ARM_6 */
5029 mach = bfd_mach_arm_3;
5030 break;
5031 }
5032
5033 /* Catch special cases. */
5034 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5035 {
5036 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5037 mach = bfd_mach_arm_5T;
5038 else if (cpu_variant & ARM_EXT_V5)
5039 mach = bfd_mach_arm_5;
5040 else if (cpu_variant & ARM_THUMB)
5041 mach = bfd_mach_arm_4T;
5042 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5043 mach = bfd_mach_arm_4;
5044 else if (cpu_variant & ARM_LONGMUL)
5045 mach = bfd_mach_arm_3M;
5046 }
5047
5048 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5049 }
5050 }
5051
5052 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5053 for use in the a.out file, and stores them in the array pointed to by buf.
5054 This knows about the endian-ness of the target machine and does
5055 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5056 2 (short) and 4 (long) Floating numbers are put out as a series of
5057 LITTLENUMS (shorts, here at least). */
5058 void
5059 md_number_to_chars (buf, val, n)
5060 char * buf;
5061 valueT val;
5062 int n;
5063 {
5064 if (target_big_endian)
5065 number_to_chars_bigendian (buf, val, n);
5066 else
5067 number_to_chars_littleendian (buf, val, n);
5068 }
5069
5070 static valueT
5071 md_chars_to_number (buf, n)
5072 char * buf;
5073 int n;
5074 {
5075 valueT result = 0;
5076 unsigned char * where = (unsigned char *) buf;
5077
5078 if (target_big_endian)
5079 {
5080 while (n--)
5081 {
5082 result <<= 8;
5083 result |= (*where++ & 255);
5084 }
5085 }
5086 else
5087 {
5088 while (n--)
5089 {
5090 result <<= 8;
5091 result |= (where[n] & 255);
5092 }
5093 }
5094
5095 return result;
5096 }
5097
5098 /* Turn a string in input_line_pointer into a floating point constant
5099 of type TYPE, and store the appropriate bytes in *litP. The number
5100 of LITTLENUMS emitted is stored in *sizeP . An error message is
5101 returned, or NULL on OK.
5102
5103 Note that fp constants aren't represent in the normal way on the ARM.
5104 In big endian mode, things are as expected. However, in little endian
5105 mode fp constants are big-endian word-wise, and little-endian byte-wise
5106 within the words. For example, (double) 1.1 in big endian mode is
5107 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5108 the byte sequence 99 99 f1 3f 9a 99 99 99.
5109
5110 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5111
5112 char *
5113 md_atof (type, litP, sizeP)
5114 char type;
5115 char * litP;
5116 int * sizeP;
5117 {
5118 int prec;
5119 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5120 char *t;
5121 int i;
5122
5123 switch (type)
5124 {
5125 case 'f':
5126 case 'F':
5127 case 's':
5128 case 'S':
5129 prec = 2;
5130 break;
5131
5132 case 'd':
5133 case 'D':
5134 case 'r':
5135 case 'R':
5136 prec = 4;
5137 break;
5138
5139 case 'x':
5140 case 'X':
5141 prec = 6;
5142 break;
5143
5144 case 'p':
5145 case 'P':
5146 prec = 6;
5147 break;
5148
5149 default:
5150 *sizeP = 0;
5151 return _("Bad call to MD_ATOF()");
5152 }
5153
5154 t = atof_ieee (input_line_pointer, type, words);
5155 if (t)
5156 input_line_pointer = t;
5157 *sizeP = prec * 2;
5158
5159 if (target_big_endian)
5160 {
5161 for (i = 0; i < prec; i++)
5162 {
5163 md_number_to_chars (litP, (valueT) words[i], 2);
5164 litP += 2;
5165 }
5166 }
5167 else
5168 {
5169 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5170 8 byte float the order is 1 0 3 2. */
5171 for (i = 0; i < prec; i += 2)
5172 {
5173 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5174 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5175 litP += 4;
5176 }
5177 }
5178
5179 return 0;
5180 }
5181
5182 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5183 long
5184 md_pcrel_from (fixP)
5185 fixS * fixP;
5186 {
5187 if ( fixP->fx_addsy
5188 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5189 && fixP->fx_subsy == NULL)
5190 return 0;
5191
5192 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5193 {
5194 /* PC relative addressing on the Thumb is slightly odd
5195 as the bottom two bits of the PC are forced to zero
5196 for the calculation. */
5197 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5198 }
5199
5200 return fixP->fx_where + fixP->fx_frag->fr_address;
5201 }
5202
5203 /* Round up a section size to the appropriate boundary. */
5204 valueT
5205 md_section_align (segment, size)
5206 segT segment;
5207 valueT size;
5208 {
5209 #ifdef OBJ_ELF
5210 return size;
5211 #else
5212 /* Round all sects to multiple of 4 */
5213 return (size + 3) & ~3;
5214 #endif
5215 }
5216
5217 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5218 we have no need to default values of symbols. */
5219
5220 /* ARGSUSED */
5221 symbolS *
5222 md_undefined_symbol (name)
5223 char * name;
5224 {
5225 #ifdef OBJ_ELF
5226 if (name[0] == '_' && name[1] == 'G'
5227 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5228 {
5229 if (!GOT_symbol)
5230 {
5231 if (symbol_find (name))
5232 as_bad ("GOT already in the symbol table");
5233
5234 GOT_symbol = symbol_new (name, undefined_section,
5235 (valueT)0, & zero_address_frag);
5236 }
5237
5238 return GOT_symbol;
5239 }
5240 #endif
5241
5242 return 0;
5243 }
5244
5245 /* arm_reg_parse () := if it looks like a register, return its token and
5246 advance the pointer. */
5247
5248 static int
5249 arm_reg_parse (ccp)
5250 register char ** ccp;
5251 {
5252 char * start = * ccp;
5253 char c;
5254 char * p;
5255 struct reg_entry * reg;
5256
5257 #ifdef REGISTER_PREFIX
5258 if (*start != REGISTER_PREFIX)
5259 return FAIL;
5260 p = start + 1;
5261 #else
5262 p = start;
5263 #ifdef OPTIONAL_REGISTER_PREFIX
5264 if (*p == OPTIONAL_REGISTER_PREFIX)
5265 p++, start++;
5266 #endif
5267 #endif
5268 if (!isalpha (*p) || !is_name_beginner (*p))
5269 return FAIL;
5270
5271 c = *p++;
5272 while (isalpha (c) || isdigit (c) || c == '_')
5273 c = *p++;
5274
5275 *--p = 0;
5276 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5277 *p = c;
5278
5279 if (reg)
5280 {
5281 *ccp = p;
5282 return reg->number;
5283 }
5284
5285 return FAIL;
5286 }
5287
5288 static int
5289 arm_psr_parse (ccp)
5290 register char ** ccp;
5291 {
5292 char * start = * ccp;
5293 char c;
5294 char * p;
5295 CONST struct asm_psr * psr;
5296
5297 p = start;
5298 c = *p++;
5299 while (isalpha (c) || c == '_')
5300 c = *p++;
5301
5302 *--p = 0;
5303 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5304 *p = c;
5305
5306 if (psr)
5307 {
5308 *ccp = p;
5309 return psr->number;
5310 }
5311
5312 return FAIL;
5313 }
5314
5315 int
5316 md_apply_fix3 (fixP, val, seg)
5317 fixS * fixP;
5318 valueT * val;
5319 segT seg;
5320 {
5321 offsetT value = * val;
5322 offsetT newval;
5323 unsigned int newimm;
5324 unsigned long temp;
5325 int sign;
5326 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5327 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5328
5329 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5330
5331 /* Note whether this will delete the relocation. */
5332 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5333 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5334 && !fixP->fx_pcrel)
5335 #else
5336 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5337 #endif
5338 fixP->fx_done = 1;
5339
5340 /* If this symbol is in a different section then we need to leave it for
5341 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5342 so we have to undo it's effects here. */
5343 if (fixP->fx_pcrel)
5344 {
5345 if (fixP->fx_addsy != NULL
5346 && S_IS_DEFINED (fixP->fx_addsy)
5347 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5348 {
5349 if (target_oabi
5350 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5351 ))
5352 value = 0;
5353 else
5354 value += md_pcrel_from (fixP);
5355 }
5356 }
5357
5358 fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
5359
5360 switch (fixP->fx_r_type)
5361 {
5362 case BFD_RELOC_ARM_IMMEDIATE:
5363 newimm = validate_immediate (value);
5364 temp = md_chars_to_number (buf, INSN_SIZE);
5365
5366 /* If the instruction will fail, see if we can fix things up by
5367 changing the opcode. */
5368 if (newimm == (unsigned int) FAIL
5369 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5370 {
5371 as_bad_where (fixP->fx_file, fixP->fx_line,
5372 _("invalid constant (%lx) after fixup"),
5373 (unsigned long) value);
5374 break;
5375 }
5376
5377 newimm |= (temp & 0xfffff000);
5378 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5379 break;
5380
5381 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5382 {
5383 unsigned int highpart = 0;
5384 unsigned int newinsn = 0xe1a00000; /* nop */
5385 newimm = validate_immediate (value);
5386 temp = md_chars_to_number (buf, INSN_SIZE);
5387
5388 /* If the instruction will fail, see if we can fix things up by
5389 changing the opcode. */
5390 if (newimm == (unsigned int) FAIL
5391 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5392 {
5393 /* No ? OK - try using two ADD instructions to generate the value. */
5394 newimm = validate_immediate_twopart (value, & highpart);
5395
5396 /* Yes - then make sure that the second instruction is also an add. */
5397 if (newimm != (unsigned int) FAIL)
5398 newinsn = temp;
5399 /* Still No ? Try using a negated value. */
5400 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5401 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5402 /* Otherwise - give up. */
5403 else
5404 {
5405 as_bad_where (fixP->fx_file, fixP->fx_line,
5406 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
5407 break;
5408 }
5409
5410 /* Replace the first operand in the 2nd instruction (which is the PC)
5411 with the destination register. We have already added in the PC in the
5412 first instruction and we do not want to do it again. */
5413 newinsn &= ~ 0xf0000;
5414 newinsn |= ((newinsn & 0x0f000) << 4);
5415 }
5416
5417 newimm |= (temp & 0xfffff000);
5418 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5419
5420 highpart |= (newinsn & 0xfffff000);
5421 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5422 }
5423 break;
5424
5425 case BFD_RELOC_ARM_OFFSET_IMM:
5426 sign = value >= 0;
5427
5428 if (value < 0)
5429 value = - value;
5430
5431 if (validate_offset_imm (value, 0) == FAIL)
5432 {
5433 as_bad_where (fixP->fx_file, fixP->fx_line,
5434 _("bad immediate value for offset (%ld)"), (long) value);
5435 break;
5436 }
5437
5438 newval = md_chars_to_number (buf, INSN_SIZE);
5439 newval &= 0xff7ff000;
5440 newval |= value | (sign ? INDEX_UP : 0);
5441 md_number_to_chars (buf, newval, INSN_SIZE);
5442 break;
5443
5444 case BFD_RELOC_ARM_OFFSET_IMM8:
5445 case BFD_RELOC_ARM_HWLITERAL:
5446 sign = value >= 0;
5447
5448 if (value < 0)
5449 value = - value;
5450
5451 if (validate_offset_imm (value, 1) == FAIL)
5452 {
5453 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5454 as_bad_where (fixP->fx_file, fixP->fx_line,
5455 _("invalid literal constant: pool needs to be closer"));
5456 else
5457 as_bad (_("bad immediate value for half-word offset (%ld)"),
5458 (long) value);
5459 break;
5460 }
5461
5462 newval = md_chars_to_number (buf, INSN_SIZE);
5463 newval &= 0xff7ff0f0;
5464 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5465 md_number_to_chars (buf, newval, INSN_SIZE);
5466 break;
5467
5468 case BFD_RELOC_ARM_LITERAL:
5469 sign = value >= 0;
5470
5471 if (value < 0)
5472 value = - value;
5473
5474 if (validate_offset_imm (value, 0) == FAIL)
5475 {
5476 as_bad_where (fixP->fx_file, fixP->fx_line,
5477 _("invalid literal constant: pool needs to be closer"));
5478 break;
5479 }
5480
5481 newval = md_chars_to_number (buf, INSN_SIZE);
5482 newval &= 0xff7ff000;
5483 newval |= value | (sign ? INDEX_UP : 0);
5484 md_number_to_chars (buf, newval, INSN_SIZE);
5485 break;
5486
5487 case BFD_RELOC_ARM_SHIFT_IMM:
5488 newval = md_chars_to_number (buf, INSN_SIZE);
5489 if (((unsigned long) value) > 32
5490 || (value == 32
5491 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5492 {
5493 as_bad_where (fixP->fx_file, fixP->fx_line,
5494 _("shift expression is too large"));
5495 break;
5496 }
5497
5498 if (value == 0)
5499 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5500 else if (value == 32)
5501 value = 0;
5502 newval &= 0xfffff07f;
5503 newval |= (value & 0x1f) << 7;
5504 md_number_to_chars (buf, newval , INSN_SIZE);
5505 break;
5506
5507 case BFD_RELOC_ARM_SWI:
5508 if (arm_data->thumb_mode)
5509 {
5510 if (((unsigned long) value) > 0xff)
5511 as_bad_where (fixP->fx_file, fixP->fx_line,
5512 _("Invalid swi expression"));
5513 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5514 newval |= value;
5515 md_number_to_chars (buf, newval, THUMB_SIZE);
5516 }
5517 else
5518 {
5519 if (((unsigned long) value) > 0x00ffffff)
5520 as_bad_where (fixP->fx_file, fixP->fx_line,
5521 _("Invalid swi expression"));
5522 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5523 newval |= value;
5524 md_number_to_chars (buf, newval , INSN_SIZE);
5525 }
5526 break;
5527
5528 case BFD_RELOC_ARM_MULTI:
5529 if (((unsigned long) value) > 0xffff)
5530 as_bad_where (fixP->fx_file, fixP->fx_line,
5531 _("Invalid expression in load/store multiple"));
5532 newval = value | md_chars_to_number (buf, INSN_SIZE);
5533 md_number_to_chars (buf, newval, INSN_SIZE);
5534 break;
5535
5536 case BFD_RELOC_ARM_PCREL_BRANCH:
5537 newval = md_chars_to_number (buf, INSN_SIZE);
5538
5539 #ifdef OBJ_ELF
5540 if (! target_oabi)
5541 value = fixP->fx_offset;
5542 #endif
5543 value = (value >> 2) & 0x00ffffff;
5544 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5545 newval = value | (newval & 0xff000000);
5546 md_number_to_chars (buf, newval, INSN_SIZE);
5547 break;
5548
5549
5550 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5551 newval = md_chars_to_number (buf, THUMB_SIZE);
5552 {
5553 addressT diff = (newval & 0xff) << 1;
5554 if (diff & 0x100)
5555 diff |= ~0xff;
5556
5557 value += diff;
5558 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5559 as_bad_where (fixP->fx_file, fixP->fx_line,
5560 _("Branch out of range"));
5561 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5562 }
5563 md_number_to_chars (buf, newval, THUMB_SIZE);
5564 break;
5565
5566 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5567 newval = md_chars_to_number (buf, THUMB_SIZE);
5568 {
5569 addressT diff = (newval & 0x7ff) << 1;
5570 if (diff & 0x800)
5571 diff |= ~0x7ff;
5572
5573 value += diff;
5574 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5575 as_bad_where (fixP->fx_file, fixP->fx_line,
5576 _("Branch out of range"));
5577 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5578 }
5579 md_number_to_chars (buf, newval, THUMB_SIZE);
5580 break;
5581
5582 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5583 {
5584 offsetT newval2;
5585 addressT diff;
5586
5587 newval = md_chars_to_number (buf, THUMB_SIZE);
5588 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5589 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5590 if (diff & 0x400000)
5591 diff |= ~0x3fffff;
5592 #ifdef OBJ_ELF
5593 value = fixP->fx_offset;
5594 #endif
5595 value += diff;
5596 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5597 as_bad_where (fixP->fx_file, fixP->fx_line,
5598 _("Branch with link out of range"));
5599
5600 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5601 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5602 md_number_to_chars (buf, newval, THUMB_SIZE);
5603 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5604 }
5605 break;
5606
5607 case BFD_RELOC_8:
5608 if (fixP->fx_done || fixP->fx_pcrel)
5609 md_number_to_chars (buf, value, 1);
5610 #ifdef OBJ_ELF
5611 else if (!target_oabi)
5612 {
5613 value = fixP->fx_offset;
5614 md_number_to_chars (buf, value, 1);
5615 }
5616 #endif
5617 break;
5618
5619 case BFD_RELOC_16:
5620 if (fixP->fx_done || fixP->fx_pcrel)
5621 md_number_to_chars (buf, value, 2);
5622 #ifdef OBJ_ELF
5623 else if (!target_oabi)
5624 {
5625 value = fixP->fx_offset;
5626 md_number_to_chars (buf, value, 2);
5627 }
5628 #endif
5629 break;
5630
5631 #ifdef OBJ_ELF
5632 case BFD_RELOC_ARM_GOT32:
5633 case BFD_RELOC_ARM_GOTOFF:
5634 md_number_to_chars (buf, 0, 4);
5635 break;
5636 #endif
5637
5638 case BFD_RELOC_RVA:
5639 case BFD_RELOC_32:
5640 if (fixP->fx_done || fixP->fx_pcrel)
5641 md_number_to_chars (buf, value, 4);
5642 #ifdef OBJ_ELF
5643 else if (!target_oabi)
5644 {
5645 value = fixP->fx_offset;
5646 md_number_to_chars (buf, value, 4);
5647 }
5648 #endif
5649 break;
5650
5651 #ifdef OBJ_ELF
5652 case BFD_RELOC_ARM_PLT32:
5653 /* It appears the instruction is fully prepared at this point. */
5654 break;
5655 #endif
5656
5657 case BFD_RELOC_ARM_GOTPC:
5658 md_number_to_chars (buf, value, 4);
5659 break;
5660
5661 case BFD_RELOC_ARM_CP_OFF_IMM:
5662 sign = value >= 0;
5663 if (value < -1023 || value > 1023 || (value & 3))
5664 as_bad_where (fixP->fx_file, fixP->fx_line,
5665 _("Illegal value for co-processor offset"));
5666 if (value < 0)
5667 value = -value;
5668 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5669 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5670 md_number_to_chars (buf, newval , INSN_SIZE);
5671 break;
5672
5673 case BFD_RELOC_ARM_THUMB_OFFSET:
5674 newval = md_chars_to_number (buf, THUMB_SIZE);
5675 /* Exactly what ranges, and where the offset is inserted depends on
5676 the type of instruction, we can establish this from the top 4 bits */
5677 switch (newval >> 12)
5678 {
5679 case 4: /* PC load */
5680 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5681 forced to zero for these loads, so we will need to round
5682 up the offset if the instruction address is not word
5683 aligned (since the final address produced must be, and
5684 we can only describe word-aligned immediate offsets). */
5685
5686 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5687 as_bad_where (fixP->fx_file, fixP->fx_line,
5688 _("Invalid offset, target not word aligned (0x%08X)"),
5689 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5690
5691 if ((value + 2) & ~0x3fe)
5692 as_bad_where (fixP->fx_file, fixP->fx_line,
5693 _("Invalid offset, value too big (0x%08X)"), value);
5694
5695 /* Round up, since pc will be rounded down. */
5696 newval |= (value + 2) >> 2;
5697 break;
5698
5699 case 9: /* SP load/store */
5700 if (value & ~0x3fc)
5701 as_bad_where (fixP->fx_file, fixP->fx_line,
5702 _("Invalid offset, value too big (0x%08X)"), value);
5703 newval |= value >> 2;
5704 break;
5705
5706 case 6: /* Word load/store */
5707 if (value & ~0x7c)
5708 as_bad_where (fixP->fx_file, fixP->fx_line,
5709 _("Invalid offset, value too big (0x%08X)"), value);
5710 newval |= value << 4; /* 6 - 2 */
5711 break;
5712
5713 case 7: /* Byte load/store */
5714 if (value & ~0x1f)
5715 as_bad_where (fixP->fx_file, fixP->fx_line,
5716 _("Invalid offset, value too big (0x%08X)"), value);
5717 newval |= value << 6;
5718 break;
5719
5720 case 8: /* Halfword load/store */
5721 if (value & ~0x3e)
5722 as_bad_where (fixP->fx_file, fixP->fx_line,
5723 _("Invalid offset, value too big (0x%08X)"), value);
5724 newval |= value << 5; /* 6 - 1 */
5725 break;
5726
5727 default:
5728 as_bad_where (fixP->fx_file, fixP->fx_line,
5729 "Unable to process relocation for thumb opcode: %lx",
5730 (unsigned long) newval);
5731 break;
5732 }
5733 md_number_to_chars (buf, newval, THUMB_SIZE);
5734 break;
5735
5736 case BFD_RELOC_ARM_THUMB_ADD:
5737 /* This is a complicated relocation, since we use it for all of
5738 the following immediate relocations:
5739 3bit ADD/SUB
5740 8bit ADD/SUB
5741 9bit ADD/SUB SP word-aligned
5742 10bit ADD PC/SP word-aligned
5743
5744 The type of instruction being processed is encoded in the
5745 instruction field:
5746 0x8000 SUB
5747 0x00F0 Rd
5748 0x000F Rs
5749 */
5750 newval = md_chars_to_number (buf, THUMB_SIZE);
5751 {
5752 int rd = (newval >> 4) & 0xf;
5753 int rs = newval & 0xf;
5754 int subtract = newval & 0x8000;
5755
5756 if (rd == REG_SP)
5757 {
5758 if (value & ~0x1fc)
5759 as_bad_where (fixP->fx_file, fixP->fx_line,
5760 _("Invalid immediate for stack address calculation"));
5761 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5762 newval |= value >> 2;
5763 }
5764 else if (rs == REG_PC || rs == REG_SP)
5765 {
5766 if (subtract ||
5767 value & ~0x3fc)
5768 as_bad_where (fixP->fx_file, fixP->fx_line,
5769 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5770 (unsigned long) value);
5771 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5772 newval |= rd << 8;
5773 newval |= value >> 2;
5774 }
5775 else if (rs == rd)
5776 {
5777 if (value & ~0xff)
5778 as_bad_where (fixP->fx_file, fixP->fx_line,
5779 _("Invalid 8bit immediate"));
5780 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5781 newval |= (rd << 8) | value;
5782 }
5783 else
5784 {
5785 if (value & ~0x7)
5786 as_bad_where (fixP->fx_file, fixP->fx_line,
5787 _("Invalid 3bit immediate"));
5788 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5789 newval |= rd | (rs << 3) | (value << 6);
5790 }
5791 }
5792 md_number_to_chars (buf, newval , THUMB_SIZE);
5793 break;
5794
5795 case BFD_RELOC_ARM_THUMB_IMM:
5796 newval = md_chars_to_number (buf, THUMB_SIZE);
5797 switch (newval >> 11)
5798 {
5799 case 0x04: /* 8bit immediate MOV */
5800 case 0x05: /* 8bit immediate CMP */
5801 if (value < 0 || value > 255)
5802 as_bad_where (fixP->fx_file, fixP->fx_line,
5803 _("Invalid immediate: %ld is too large"),
5804 (long) value);
5805 newval |= value;
5806 break;
5807
5808 default:
5809 abort ();
5810 }
5811 md_number_to_chars (buf, newval , THUMB_SIZE);
5812 break;
5813
5814 case BFD_RELOC_ARM_THUMB_SHIFT:
5815 /* 5bit shift value (0..31) */
5816 if (value < 0 || value > 31)
5817 as_bad_where (fixP->fx_file, fixP->fx_line,
5818 _("Illegal Thumb shift value: %ld"), (long) value);
5819 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5820 newval |= value << 6;
5821 md_number_to_chars (buf, newval , THUMB_SIZE);
5822 break;
5823
5824 case BFD_RELOC_VTABLE_INHERIT:
5825 case BFD_RELOC_VTABLE_ENTRY:
5826 fixP->fx_done = 0;
5827 return 1;
5828
5829 case BFD_RELOC_NONE:
5830 default:
5831 as_bad_where (fixP->fx_file, fixP->fx_line,
5832 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
5833 }
5834
5835 return 1;
5836 }
5837
5838 /* Translate internal representation of relocation info to BFD target
5839 format. */
5840 arelent *
5841 tc_gen_reloc (section, fixp)
5842 asection * section;
5843 fixS * fixp;
5844 {
5845 arelent * reloc;
5846 bfd_reloc_code_real_type code;
5847
5848 reloc = (arelent *) xmalloc (sizeof (arelent));
5849
5850 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5851 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5852 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5853
5854 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5855 #ifndef OBJ_ELF
5856 if (fixp->fx_pcrel == 0)
5857 reloc->addend = fixp->fx_offset;
5858 else
5859 reloc->addend = fixp->fx_offset = reloc->address;
5860 #else /* OBJ_ELF */
5861 reloc->addend = fixp->fx_offset;
5862 #endif
5863
5864 switch (fixp->fx_r_type)
5865 {
5866 case BFD_RELOC_8:
5867 if (fixp->fx_pcrel)
5868 {
5869 code = BFD_RELOC_8_PCREL;
5870 break;
5871 }
5872
5873 case BFD_RELOC_16:
5874 if (fixp->fx_pcrel)
5875 {
5876 code = BFD_RELOC_16_PCREL;
5877 break;
5878 }
5879
5880 case BFD_RELOC_32:
5881 if (fixp->fx_pcrel)
5882 {
5883 code = BFD_RELOC_32_PCREL;
5884 break;
5885 }
5886
5887 case BFD_RELOC_ARM_PCREL_BRANCH:
5888 case BFD_RELOC_RVA:
5889 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5890 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5891 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5892 case BFD_RELOC_VTABLE_ENTRY:
5893 case BFD_RELOC_VTABLE_INHERIT:
5894 code = fixp->fx_r_type;
5895 break;
5896
5897 case BFD_RELOC_ARM_LITERAL:
5898 case BFD_RELOC_ARM_HWLITERAL:
5899 /* If this is called then the a literal has been referenced across
5900 a section boundary - possibly due to an implicit dump */
5901 as_bad_where (fixp->fx_file, fixp->fx_line,
5902 _("Literal referenced across section boundary (Implicit dump?)"));
5903 return NULL;
5904
5905 #ifdef OBJ_ELF
5906 case BFD_RELOC_ARM_GOT32:
5907 case BFD_RELOC_ARM_GOTOFF:
5908 case BFD_RELOC_ARM_PLT32:
5909 code = fixp->fx_r_type;
5910 break;
5911 #endif
5912
5913 case BFD_RELOC_ARM_IMMEDIATE:
5914 as_bad_where (fixp->fx_file, fixp->fx_line,
5915 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5916 fixp->fx_r_type);
5917 return NULL;
5918
5919 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5920 as_bad_where (fixp->fx_file, fixp->fx_line,
5921 _("ADRL used for a symbol not defined in the same file"),
5922 fixp->fx_r_type);
5923 return NULL;
5924
5925 case BFD_RELOC_ARM_OFFSET_IMM:
5926 as_bad_where (fixp->fx_file, fixp->fx_line,
5927 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
5928 fixp->fx_r_type);
5929 return NULL;
5930
5931 default:
5932 {
5933 char * type;
5934 switch (fixp->fx_r_type)
5935 {
5936 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
5937 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
5938 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
5939 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
5940 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
5941 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
5942 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
5943 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
5944 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
5945 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
5946 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
5947 default: type = _("<unknown>"); break;
5948 }
5949 as_bad_where (fixp->fx_file, fixp->fx_line,
5950 _("Can not represent %s relocation in this object file format (%d)"),
5951 type, fixp->fx_pcrel);
5952 return NULL;
5953 }
5954 }
5955
5956 #ifdef OBJ_ELF
5957 if (code == BFD_RELOC_32_PCREL
5958 && GOT_symbol
5959 && fixp->fx_addsy == GOT_symbol)
5960 {
5961 code = BFD_RELOC_ARM_GOTPC;
5962 reloc->addend = fixp->fx_offset = reloc->address;
5963 }
5964 #endif
5965
5966 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
5967
5968 if (reloc->howto == NULL)
5969 {
5970 as_bad_where (fixp->fx_file, fixp->fx_line,
5971 _("Can not represent %s relocation in this object file format"),
5972 bfd_get_reloc_code_name (code));
5973 return NULL;
5974 }
5975
5976 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
5977 vtable entry to be used in the relocation's section offset. */
5978 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5979 reloc->address = fixp->fx_offset;
5980
5981 return reloc;
5982 }
5983
5984 int
5985 md_estimate_size_before_relax (fragP, segtype)
5986 fragS * fragP;
5987 segT segtype;
5988 {
5989 as_fatal (_("md_estimate_size_before_relax\n"));
5990 return 1;
5991 }
5992
5993 static void
5994 output_inst PARAMS ((void))
5995 {
5996 char * to = NULL;
5997
5998 if (inst.error)
5999 {
6000 as_bad (inst.error);
6001 return;
6002 }
6003
6004 to = frag_more (inst.size);
6005
6006 if (thumb_mode && (inst.size > THUMB_SIZE))
6007 {
6008 assert (inst.size == (2 * THUMB_SIZE));
6009 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6010 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6011 }
6012 else if (inst.size > INSN_SIZE)
6013 {
6014 assert (inst.size == (2 * INSN_SIZE));
6015 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6016 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6017 }
6018 else
6019 md_number_to_chars (to, inst.instruction, inst.size);
6020
6021 if (inst.reloc.type != BFD_RELOC_NONE)
6022 fix_new_arm (frag_now, to - frag_now->fr_literal,
6023 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6024 inst.reloc.type);
6025
6026 return;
6027 }
6028
6029 void
6030 md_assemble (str)
6031 char * str;
6032 {
6033 char c;
6034 char * p;
6035 char * q;
6036 char * start;
6037
6038 /* Align the instruction.
6039 This may not be the right thing to do but ... */
6040 /* arm_align (2, 0); */
6041 listing_prev_line (); /* Defined in listing.h */
6042
6043 /* Align the previous label if needed. */
6044 if (last_label_seen != NULL)
6045 {
6046 symbol_set_frag (last_label_seen, frag_now);
6047 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6048 S_SET_SEGMENT (last_label_seen, now_seg);
6049 }
6050
6051 memset (&inst, '\0', sizeof (inst));
6052 inst.reloc.type = BFD_RELOC_NONE;
6053
6054 skip_whitespace (str);
6055
6056 /* Scan up to the end of the op-code, which must end in white space or
6057 end of string. */
6058 for (start = p = str; *p != '\0'; p++)
6059 if (*p == ' ')
6060 break;
6061
6062 if (p == str)
6063 {
6064 as_bad (_("No operator -- statement `%s'\n"), str);
6065 return;
6066 }
6067
6068 if (thumb_mode)
6069 {
6070 CONST struct thumb_opcode * opcode;
6071
6072 c = *p;
6073 *p = '\0';
6074 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6075 *p = c;
6076
6077 if (opcode)
6078 {
6079 /* Check that this instruction is supported for this CPU. */
6080 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6081 {
6082 as_bad (_("selected processor does not support this opcode"));
6083 return;
6084 }
6085
6086 inst.instruction = opcode->value;
6087 inst.size = opcode->size;
6088 (*opcode->parms)(p);
6089 output_inst ();
6090 return;
6091 }
6092 }
6093 else
6094 {
6095 CONST struct asm_opcode * opcode;
6096 unsigned long cond_code;
6097
6098 inst.size = INSN_SIZE;
6099 /* p now points to the end of the opcode, probably white space, but we
6100 have to break the opcode up in case it contains condionals and flags;
6101 keep trying with progressively smaller basic instructions until one
6102 matches, or we run out of opcode. */
6103 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6104 for (; q != str; q--)
6105 {
6106 c = *q;
6107 *q = '\0';
6108 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6109 *q = c;
6110
6111 if (opcode && opcode->template)
6112 {
6113 unsigned long flag_bits = 0;
6114 char * r;
6115
6116 /* Check that this instruction is supported for this CPU. */
6117 if ((opcode->variants & cpu_variant) == 0)
6118 goto try_shorter;
6119
6120 inst.instruction = opcode->value;
6121 if (q == p) /* Just a simple opcode. */
6122 {
6123 if (opcode->comp_suffix)
6124 {
6125 if (*opcode->comp_suffix != '\0')
6126 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6127 str, opcode->comp_suffix);
6128 else
6129 /* Not a conditional instruction. */
6130 (*opcode->parms)(q, 0);
6131 }
6132 else
6133 {
6134 /* A conditional instruction with default condition. */
6135 inst.instruction |= COND_ALWAYS;
6136 (*opcode->parms)(q, 0);
6137 }
6138 output_inst ();
6139 return;
6140 }
6141
6142 /* Not just a simple opcode. Check if extra is a conditional. */
6143 r = q;
6144 if (p - r >= 2)
6145 {
6146 CONST struct asm_cond *cond;
6147 char d = *(r + 2);
6148
6149 *(r + 2) = '\0';
6150 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6151 *(r + 2) = d;
6152 if (cond)
6153 {
6154 if (cond->value == 0xf0000000)
6155 as_tsktsk (
6156 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6157
6158 cond_code = cond->value;
6159 r += 2;
6160 }
6161 else
6162 cond_code = COND_ALWAYS;
6163 }
6164 else
6165 cond_code = COND_ALWAYS;
6166
6167 /* Apply the conditional, or complain it's not allowed. */
6168 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6169 {
6170 /* Instruction isn't conditional */
6171 if (cond_code != COND_ALWAYS)
6172 {
6173 as_bad (_("Opcode `%s' is unconditional\n"), str);
6174 return;
6175 }
6176 }
6177 else
6178 /* Instruction is conditional: set the condition into it. */
6179 inst.instruction |= cond_code;
6180
6181
6182 /* If there is a compulsory suffix, it should come here, before
6183 any optional flags. */
6184 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6185 {
6186 CONST char *s = opcode->comp_suffix;
6187
6188 while (*s)
6189 {
6190 inst.suffix++;
6191 if (*r == *s)
6192 break;
6193 s++;
6194 }
6195
6196 if (*s == '\0')
6197 {
6198 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6199 opcode->comp_suffix);
6200 return;
6201 }
6202
6203 r++;
6204 }
6205
6206 /* The remainder, if any should now be flags for the instruction;
6207 Scan these checking each one found with the opcode. */
6208 if (r != p)
6209 {
6210 char d;
6211 CONST struct asm_flg *flag = opcode->flags;
6212
6213 if (flag)
6214 {
6215 int flagno;
6216
6217 d = *p;
6218 *p = '\0';
6219
6220 for (flagno = 0; flag[flagno].template; flagno++)
6221 {
6222 if (streq (r, flag[flagno].template))
6223 {
6224 flag_bits |= flag[flagno].set_bits;
6225 break;
6226 }
6227 }
6228
6229 *p = d;
6230 if (! flag[flagno].template)
6231 goto try_shorter;
6232 }
6233 else
6234 goto try_shorter;
6235 }
6236
6237 (*opcode->parms) (p, flag_bits);
6238 output_inst ();
6239 return;
6240 }
6241
6242 try_shorter:
6243 ;
6244 }
6245 }
6246
6247 /* It wasn't an instruction, but it might be a register alias of the form
6248 alias .req reg */
6249 q = p;
6250 skip_whitespace (q);
6251
6252 c = *p;
6253 *p = '\0';
6254
6255 if (*q && !strncmp (q, ".req ", 4))
6256 {
6257 int reg;
6258 char * copy_of_str = str;
6259 char * r;
6260
6261 q += 4;
6262 skip_whitespace (q);
6263
6264 for (r = q; *r != '\0'; r++)
6265 if (*r == ' ')
6266 break;
6267
6268 if (r != q)
6269 {
6270 int regnum;
6271 char d = *r;
6272
6273 *r = '\0';
6274 regnum = arm_reg_parse (& q);
6275 *r = d;
6276
6277 reg = arm_reg_parse (& str);
6278
6279 if (reg == FAIL)
6280 {
6281 if (regnum != FAIL)
6282 insert_reg_alias (str, regnum);
6283 else
6284 as_warn (_("register '%s' does not exist\n"), q);
6285 }
6286 else if (regnum != FAIL)
6287 {
6288 if (reg != regnum)
6289 as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str );
6290
6291 /* Do not warn about redefinitions to the same alias. */
6292 }
6293 else
6294 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6295 copy_of_str, q);
6296 }
6297 else
6298 as_warn (_("ignoring incomplete .req pseuso op"));
6299
6300 *p = c;
6301 return;
6302 }
6303
6304 *p = c;
6305 as_bad (_("bad instruction `%s'"), start);
6306 }
6307
6308 /*
6309 * md_parse_option
6310 * Invocation line includes a switch not recognized by the base assembler.
6311 * See if it's a processor-specific option. These are:
6312 * Cpu variants, the arm part is optional:
6313 * -m[arm]1 Currently not supported.
6314 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6315 * -m[arm]3 Arm 3 processor
6316 * -m[arm]6[xx], Arm 6 processors
6317 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6318 * -m[arm]8[10] Arm 8 processors
6319 * -m[arm]9[20][tdmi] Arm 9 processors
6320 * -mstrongarm[110[0]] StrongARM processors
6321 * -m[arm]v[2345] Arm architectures
6322 * -mall All (except the ARM1)
6323 * FP variants:
6324 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6325 * -mfpe-old (No float load/store multiples)
6326 * -mno-fpu Disable all floating point instructions
6327 * Run-time endian selection:
6328 * -EB big endian cpu
6329 * -EL little endian cpu
6330 * ARM Procedure Calling Standard:
6331 * -mapcs-32 32 bit APCS
6332 * -mapcs-26 26 bit APCS
6333 * -mapcs-float Pass floats in float regs
6334 * -mapcs-reentrant Position independent code
6335 * -mthumb-interwork Code supports Arm/Thumb interworking
6336 * -moabi Old ELF ABI
6337 */
6338
6339 CONST char * md_shortopts = "m:k";
6340 struct option md_longopts[] =
6341 {
6342 #ifdef ARM_BI_ENDIAN
6343 #define OPTION_EB (OPTION_MD_BASE + 0)
6344 {"EB", no_argument, NULL, OPTION_EB},
6345 #define OPTION_EL (OPTION_MD_BASE + 1)
6346 {"EL", no_argument, NULL, OPTION_EL},
6347 #ifdef OBJ_ELF
6348 #define OPTION_OABI (OPTION_MD_BASE +2)
6349 {"oabi", no_argument, NULL, OPTION_OABI},
6350 #endif
6351 #endif
6352 {NULL, no_argument, NULL, 0}
6353 };
6354 size_t md_longopts_size = sizeof (md_longopts);
6355
6356 int
6357 md_parse_option (c, arg)
6358 int c;
6359 char * arg;
6360 {
6361 char * str = arg;
6362
6363 switch (c)
6364 {
6365 #ifdef ARM_BI_ENDIAN
6366 case OPTION_EB:
6367 target_big_endian = 1;
6368 break;
6369 case OPTION_EL:
6370 target_big_endian = 0;
6371 break;
6372 #endif
6373
6374 case 'm':
6375 switch (*str)
6376 {
6377 case 'f':
6378 if (streq (str, "fpa10"))
6379 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6380 else if (streq (str, "fpa11"))
6381 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6382 else if (streq (str, "fpe-old"))
6383 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6384 else
6385 goto bad;
6386 break;
6387
6388 case 'n':
6389 if (streq (str, "no-fpu"))
6390 cpu_variant &= ~FPU_ALL;
6391 break;
6392
6393 #ifdef OBJ_ELF
6394 case 'o':
6395 if (streq (str, "oabi"))
6396 target_oabi = true;
6397 break;
6398 #endif
6399
6400 case 't':
6401 /* Limit assembler to generating only Thumb instructions: */
6402 if (streq (str, "thumb"))
6403 {
6404 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6405 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6406 thumb_mode = 1;
6407 }
6408 else if (streq (str, "thumb-interwork"))
6409 {
6410 if ((cpu_variant & ARM_THUMB) == 0)
6411 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6412 #if defined OBJ_COFF || defined OBJ_ELF
6413 support_interwork = true;
6414 #endif
6415 }
6416 else
6417 goto bad;
6418 break;
6419
6420 default:
6421 if (streq (str, "all"))
6422 {
6423 cpu_variant = ARM_ALL | FPU_ALL;
6424 return 1;
6425 }
6426 #if defined OBJ_COFF || defined OBJ_ELF
6427 if (! strncmp (str, "apcs-", 5))
6428 {
6429 /* GCC passes on all command line options starting "-mapcs-..."
6430 to us, so we must parse them here. */
6431
6432 str += 5;
6433
6434 if (streq (str, "32"))
6435 {
6436 uses_apcs_26 = false;
6437 return 1;
6438 }
6439 else if (streq (str, "26"))
6440 {
6441 uses_apcs_26 = true;
6442 return 1;
6443 }
6444 else if (streq (str, "frame"))
6445 {
6446 /* Stack frames are being generated - does not affect
6447 linkage of code. */
6448 return 1;
6449 }
6450 else if (streq (str, "stack-check"))
6451 {
6452 /* Stack checking is being performed - does not affect
6453 linkage, but does require that the functions
6454 __rt_stkovf_split_small and __rt_stkovf_split_big be
6455 present in the final link. */
6456
6457 return 1;
6458 }
6459 else if (streq (str, "float"))
6460 {
6461 /* Floating point arguments are being passed in the floating
6462 point registers. This does affect linking, since this
6463 version of the APCS is incompatible with the version that
6464 passes floating points in the integer registers. */
6465
6466 uses_apcs_float = true;
6467 return 1;
6468 }
6469 else if (streq (str, "reentrant"))
6470 {
6471 /* Reentrant code has been generated. This does affect
6472 linking, since there is no point in linking reentrant/
6473 position independent code with absolute position code. */
6474 pic_code = true;
6475 return 1;
6476 }
6477
6478 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6479 return 0;
6480 }
6481 #endif
6482 /* Strip off optional "arm" */
6483 if (! strncmp (str, "arm", 3))
6484 str += 3;
6485
6486 switch (*str)
6487 {
6488 case '1':
6489 if (streq (str, "1"))
6490 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6491 else
6492 goto bad;
6493 break;
6494
6495 case '2':
6496 if (streq (str, "2"))
6497 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6498 else if (streq (str, "250"))
6499 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6500 else
6501 goto bad;
6502 break;
6503
6504 case '3':
6505 if (streq (str, "3"))
6506 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6507 else
6508 goto bad;
6509 break;
6510
6511 case '6':
6512 switch (strtol (str, NULL, 10))
6513 {
6514 case 6:
6515 case 60:
6516 case 600:
6517 case 610:
6518 case 620:
6519 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6520 break;
6521 default:
6522 goto bad;
6523 }
6524 break;
6525
6526 case '7':
6527 switch (strtol (str, & str, 10)) /* Eat the processor name */
6528 {
6529 case 7:
6530 case 70:
6531 case 700:
6532 case 710:
6533 case 720:
6534 case 7100:
6535 case 7500:
6536 break;
6537 default:
6538 goto bad;
6539 }
6540 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6541 for (; *str; str++)
6542 {
6543 switch (* str)
6544 {
6545 case 't':
6546 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6547 break;
6548
6549 case 'm':
6550 cpu_variant |= ARM_LONGMUL;
6551 break;
6552
6553 case 'f': /* fe => fp enabled cpu. */
6554 if (str[1] == 'e')
6555 ++ str;
6556 else
6557 goto bad;
6558
6559 case 'c': /* Left over from 710c processor name. */
6560 case 'd': /* Debug */
6561 case 'i': /* Embedded ICE */
6562 /* Included for completeness in ARM processor naming. */
6563 break;
6564
6565 default:
6566 goto bad;
6567 }
6568 }
6569 break;
6570
6571 case '8':
6572 if (streq (str, "8") || streq (str, "810"))
6573 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6574 else
6575 goto bad;
6576 break;
6577
6578 case '9':
6579 if (streq (str, "9"))
6580 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6581 else if (streq (str, "920"))
6582 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6583 else if (streq (str, "920t"))
6584 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6585 else if (streq (str, "9tdmi"))
6586 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6587 else
6588 goto bad;
6589 break;
6590
6591
6592 case 's':
6593 if (streq (str, "strongarm")
6594 || streq (str, "strongarm110")
6595 || streq (str, "strongarm1100"))
6596 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6597 else
6598 goto bad;
6599 break;
6600
6601 case 'v':
6602 /* Select variant based on architecture rather than processor */
6603 switch (*++str)
6604 {
6605 case '2':
6606 switch (*++str)
6607 {
6608 case 'a': cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; break;
6609 case 0: cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; break;
6610 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6611 }
6612 break;
6613
6614 case '3':
6615 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6616
6617 switch (*++str)
6618 {
6619 case 'm': cpu_variant |= ARM_LONGMUL; break;
6620 case 0: break;
6621 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6622 }
6623 break;
6624
6625 case '4':
6626 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6627
6628 switch (*++str)
6629 {
6630 case 't': cpu_variant |= ARM_THUMB; break;
6631 case 0: break;
6632 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6633 }
6634 break;
6635
6636 case '5':
6637 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6638 switch (*++str)
6639 {
6640 case 't': cpu_variant |= ARM_THUMB; break;
6641 case 'e': cpu_variant |= ARM_EXT_V5E; break;
6642 case 0: break;
6643 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6644 }
6645 break;
6646
6647 default:
6648 as_bad (_("Invalid architecture variant -m%s"), arg);
6649 break;
6650 }
6651 break;
6652
6653 default:
6654 bad:
6655 as_bad (_("Invalid processor variant -m%s"), arg);
6656 return 0;
6657 }
6658 }
6659 break;
6660
6661 #if defined OBJ_ELF || defined OBJ_COFF
6662 case 'k':
6663 pic_code = 1;
6664 break;
6665 #endif
6666
6667 default:
6668 return 0;
6669 }
6670
6671 return 1;
6672 }
6673
6674 void
6675 md_show_usage (fp)
6676 FILE * fp;
6677 {
6678 fprintf (fp,
6679 _("\
6680 ARM Specific Assembler Options:\n\
6681 -m[arm][<processor name>] select processor variant\n\
6682 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6683 -mthumb only allow Thumb instructions\n\
6684 -mthumb-interwork mark the assembled code as supporting interworking\n\
6685 -mall allow any instruction\n\
6686 -mfpa10, -mfpa11 select floating point architecture\n\
6687 -mfpe-old don't allow floating-point multiple instructions\n\
6688 -mno-fpu don't allow any floating-point instructions.\n"));
6689 fprintf (fp,
6690 _("\
6691 -k generate PIC code.\n"));
6692 #if defined OBJ_COFF || defined OBJ_ELF
6693 fprintf (fp,
6694 _("\
6695 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n"));
6696 fprintf (fp,
6697 _("\
6698 -mapcs-float floating point args are passed in FP regs\n"));
6699 fprintf (fp,
6700 _("\
6701 -mapcs-reentrant the code is position independent/reentrant\n"));
6702 #endif
6703 #ifdef OBJ_ELF
6704 fprintf (fp,
6705 _("\
6706 -moabi support the old ELF ABI\n"));
6707 #endif
6708 #ifdef ARM_BI_ENDIAN
6709 fprintf (fp,
6710 _("\
6711 -EB assemble code for a big endian cpu\n\
6712 -EL assemble code for a little endian cpu\n"));
6713 #endif
6714 }
6715
6716 /* We need to be able to fix up arbitrary expressions in some statements.
6717 This is so that we can handle symbols that are an arbitrary distance from
6718 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6719 which returns part of an address in a form which will be valid for
6720 a data instruction. We do this by pushing the expression into a symbol
6721 in the expr_section, and creating a fix for that. */
6722
6723 static void
6724 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6725 fragS * frag;
6726 int where;
6727 short int size;
6728 expressionS * exp;
6729 int pc_rel;
6730 int reloc;
6731 {
6732 fixS * new_fix;
6733 arm_fix_data * arm_data;
6734
6735 switch (exp->X_op)
6736 {
6737 case O_constant:
6738 case O_symbol:
6739 case O_add:
6740 case O_subtract:
6741 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6742 break;
6743
6744 default:
6745 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6746 pc_rel, reloc);
6747 break;
6748 }
6749
6750 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6751 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6752 new_fix->tc_fix_data = (PTR) arm_data;
6753 arm_data->thumb_mode = thumb_mode;
6754
6755 return;
6756 }
6757
6758
6759 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6760 void
6761 cons_fix_new_arm (frag, where, size, exp)
6762 fragS * frag;
6763 int where;
6764 int size;
6765 expressionS * exp;
6766 {
6767 bfd_reloc_code_real_type type;
6768 int pcrel = 0;
6769
6770 /* Pick a reloc ...
6771 *
6772 * @@ Should look at CPU word size.
6773 */
6774 switch (size)
6775 {
6776 case 2:
6777 type = BFD_RELOC_16;
6778 break;
6779 case 4:
6780 default:
6781 type = BFD_RELOC_32;
6782 break;
6783 case 8:
6784 type = BFD_RELOC_64;
6785 break;
6786 }
6787
6788 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6789 }
6790
6791 /* A good place to do this, although this was probably not intended
6792 for this kind of use. We need to dump the literal pool before
6793 references are made to a null symbol pointer. */
6794 void
6795 arm_cleanup ()
6796 {
6797 if (current_poolP == NULL)
6798 return;
6799
6800 subseg_set (text_section, 0); /* Put it at the end of text section. */
6801 s_ltorg (0);
6802 listing_prev_line ();
6803 }
6804
6805 void
6806 arm_start_line_hook ()
6807 {
6808 last_label_seen = NULL;
6809 }
6810
6811 void
6812 arm_frob_label (sym)
6813 symbolS * sym;
6814 {
6815 last_label_seen = sym;
6816
6817 ARM_SET_THUMB (sym, thumb_mode);
6818
6819 #if defined OBJ_COFF || defined OBJ_ELF
6820 ARM_SET_INTERWORK (sym, support_interwork);
6821 #endif
6822
6823 if (label_is_thumb_function_name)
6824 {
6825 /* When the address of a Thumb function is taken the bottom
6826 bit of that address should be set. This will allow
6827 interworking between Arm and Thumb functions to work
6828 correctly. */
6829
6830 THUMB_SET_FUNC (sym, 1);
6831
6832 label_is_thumb_function_name = false;
6833 }
6834 }
6835
6836 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6837 ARM ones. */
6838
6839 void
6840 arm_adjust_symtab ()
6841 {
6842 #ifdef OBJ_COFF
6843 symbolS * sym;
6844
6845 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6846 {
6847 if (ARM_IS_THUMB (sym))
6848 {
6849 if (THUMB_IS_FUNC (sym))
6850 {
6851 /* Mark the symbol as a Thumb function. */
6852 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6853 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6854 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6855
6856 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6857 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6858 else
6859 as_bad (_("%s: unexpected function type: %d"),
6860 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6861 }
6862 else switch (S_GET_STORAGE_CLASS (sym))
6863 {
6864 case C_EXT:
6865 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6866 break;
6867 case C_STAT:
6868 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6869 break;
6870 case C_LABEL:
6871 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6872 break;
6873 default: /* do nothing */
6874 break;
6875 }
6876 }
6877
6878 if (ARM_IS_INTERWORK (sym))
6879 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
6880 }
6881 #endif
6882 #ifdef OBJ_ELF
6883 symbolS * sym;
6884 elf_symbol_type * elf_sym;
6885 char bind;
6886
6887 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6888 {
6889 if (ARM_IS_THUMB (sym))
6890 {
6891 if (THUMB_IS_FUNC (sym))
6892 {
6893 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
6894 bind = ELF_ST_BIND (elf_sym);
6895 elf_sym->internal_elf_sym.st_info = ELF_ST_INFO (bind, STT_ARM_TFUNC);
6896 }
6897 }
6898 }
6899 #endif
6900 }
6901
6902 int
6903 arm_data_in_code ()
6904 {
6905 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
6906 {
6907 *input_line_pointer = '/';
6908 input_line_pointer += 5;
6909 *input_line_pointer = 0;
6910 return 1;
6911 }
6912
6913 return 0;
6914 }
6915
6916 char *
6917 arm_canonicalize_symbol_name (name)
6918 char * name;
6919 {
6920 int len;
6921
6922 if (thumb_mode && (len = strlen (name)) > 5
6923 && streq (name + len - 5, "/data"))
6924 *(name + len - 5) = 0;
6925
6926 return name;
6927 }
6928
6929 boolean
6930 arm_validate_fix (fixP)
6931 fixS * fixP;
6932 {
6933 /* If the destination of the branch is a defined symbol which does not have
6934 the THUMB_FUNC attribute, then we must be calling a function which has
6935 the (interfacearm) attribute. We look for the Thumb entry point to that
6936 function and change the branch to refer to that function instead. */
6937 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
6938 && fixP->fx_addsy != NULL
6939 && S_IS_DEFINED (fixP->fx_addsy)
6940 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6941 {
6942 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6943 return true;
6944 }
6945
6946 return false;
6947 }
6948
6949 #ifdef OBJ_ELF
6950 /* Relocations against Thumb function names must be left unadjusted,
6951 so that the linker can use this information to correctly set the
6952 bottom bit of their addresses. The MIPS version of this function
6953 also prevents relocations that are mips-16 specific, but I do not
6954 know why it does this.
6955
6956 FIXME:
6957 There is one other problem that ought to be addressed here, but
6958 which currently is not: Taking the address of a label (rather
6959 than a function) and then later jumping to that address. Such
6960 addresses also ought to have their bottom bit set (assuming that
6961 they reside in Thumb code), but at the moment they will not. */
6962
6963 boolean
6964 arm_fix_adjustable (fixP)
6965 fixS * fixP;
6966 {
6967 if (fixP->fx_addsy == NULL)
6968 return 1;
6969
6970 /* Prevent all adjustments to global symbols. */
6971 if (S_IS_EXTERN (fixP->fx_addsy))
6972 return 0;
6973
6974 if (S_IS_WEAK (fixP->fx_addsy))
6975 return 0;
6976
6977 if (THUMB_IS_FUNC (fixP->fx_addsy)
6978 && fixP->fx_subsy == NULL)
6979 return 0;
6980
6981 /* We need the symbol name for the VTABLE entries */
6982 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
6983 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6984 return 0;
6985
6986 return 1;
6987 }
6988
6989 const char *
6990 elf32_arm_target_format ()
6991 {
6992 if (target_big_endian)
6993 if (target_oabi)
6994 return "elf32-bigarm-oabi";
6995 else
6996 return "elf32-bigarm";
6997 else
6998 if (target_oabi)
6999 return "elf32-littlearm-oabi";
7000 else
7001 return "elf32-littlearm";
7002 }
7003
7004 void
7005 armelf_frob_symbol (symp, puntp)
7006 symbolS * symp;
7007 int * puntp;
7008 {
7009 elf_frob_symbol (symp, puntp);
7010 }
7011
7012 int
7013 arm_force_relocation (fixp)
7014 struct fix * fixp;
7015 {
7016 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7017 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7018 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7019 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7020 return 1;
7021
7022 return 0;
7023 }
7024
7025 static bfd_reloc_code_real_type
7026 arm_parse_reloc ()
7027 {
7028 char id[16];
7029 char * ip;
7030 int i;
7031 static struct
7032 {
7033 char * str;
7034 int len;
7035 bfd_reloc_code_real_type reloc;
7036 }
7037 reloc_map[] =
7038 {
7039 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7040 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7041 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7042 /* ScottB: Jan 30, 1998 */
7043 /* Added support for parsing "var(PLT)" branch instructions */
7044 /* generated by GCC for PLT relocs */
7045 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7046 { NULL, 0, BFD_RELOC_UNUSED }
7047 #undef MAP
7048 };
7049
7050 for (i = 0, ip = input_line_pointer;
7051 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7052 i++, ip++)
7053 id[i] = tolower (*ip);
7054
7055 for (i = 0; reloc_map[i].str; i++)
7056 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7057 break;
7058
7059 input_line_pointer += reloc_map[i].len;
7060
7061 return reloc_map[i].reloc;
7062 }
7063
7064 static void
7065 s_arm_elf_cons (nbytes)
7066 int nbytes;
7067 {
7068 expressionS exp;
7069
7070 #ifdef md_flush_pending_output
7071 md_flush_pending_output ();
7072 #endif
7073
7074 if (is_it_end_of_statement ())
7075 {
7076 demand_empty_rest_of_line ();
7077 return;
7078 }
7079
7080 #ifdef md_cons_align
7081 md_cons_align (nbytes);
7082 #endif
7083
7084 do
7085 {
7086 bfd_reloc_code_real_type reloc;
7087
7088 expression (& exp);
7089
7090 if (exp.X_op == O_symbol
7091 && * input_line_pointer == '('
7092 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7093 {
7094 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7095 int size = bfd_get_reloc_size (howto);
7096
7097 if (size > nbytes)
7098 as_bad ("%s relocations do not fit in %d bytes", howto->name, nbytes);
7099 else
7100 {
7101 register char * p = frag_more ((int) nbytes);
7102 int offset = nbytes - size;
7103
7104 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7105 & exp, 0, reloc);
7106 }
7107 }
7108 else
7109 emit_expr (& exp, (unsigned int) nbytes);
7110 }
7111 while (*input_line_pointer++ == ',');
7112
7113 input_line_pointer--; /* Put terminator back into stream. */
7114 demand_empty_rest_of_line ();
7115 }
7116
7117 #endif /* OBJ_ELF */
GDB Binutils - Deliverables
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