1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_neon_ext_armv8
=
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
241 static const arm_feature_set fpu_crypto_ext_armv8
=
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
244 static int mfloat_abi_opt
= -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name
[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu
.core
== arm_arch_none
.core
255 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
260 static int meabi_flags
= EABI_DEFAULT
;
262 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
265 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
270 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS
* GOT_symbol
;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode
= 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER
= 0x00,
293 IMPLICIT_IT_MODE_ARM
= 0x01,
294 IMPLICIT_IT_MODE_THUMB
= 0x02,
295 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
297 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax
= FALSE
;
337 enum neon_el_type type
;
341 #define NEON_MAX_TYPE_ELS 4
345 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
349 enum it_instruction_type
354 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
355 if inside, should be the last one. */
356 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
357 i.e. BKPT and NOP. */
358 IT_INSN
/* The IT insn has been parsed. */
361 /* The maximum number of operands we need. */
362 #define ARM_IT_MAX_OPERANDS 6
367 unsigned long instruction
;
371 /* "uncond_value" is set to the value in place of the conditional field in
372 unconditional versions of the instruction, or -1 if nothing is
375 struct neon_type vectype
;
376 /* This does not indicate an actual NEON instruction, only that
377 the mnemonic accepts neon-style type suffixes. */
379 /* Set to the opcode if the instruction needs relaxation.
380 Zero if the instruction is not relaxed. */
384 bfd_reloc_code_real_type type
;
389 enum it_instruction_type it_insn_type
;
395 struct neon_type_el vectype
;
396 unsigned present
: 1; /* Operand present. */
397 unsigned isreg
: 1; /* Operand was a register. */
398 unsigned immisreg
: 1; /* .imm field is a second register. */
399 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
400 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
401 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
402 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
403 instructions. This allows us to disambiguate ARM <-> vector insns. */
404 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
405 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
406 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
407 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
408 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
409 unsigned writeback
: 1; /* Operand has trailing ! */
410 unsigned preind
: 1; /* Preindexed address. */
411 unsigned postind
: 1; /* Postindexed address. */
412 unsigned negative
: 1; /* Index register was negated. */
413 unsigned shifted
: 1; /* Shift applied to operation. */
414 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
415 } operands
[ARM_IT_MAX_OPERANDS
];
418 static struct arm_it inst
;
420 #define NUM_FLOAT_VALS 8
422 const char * fp_const
[] =
424 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
427 /* Number of littlenums required to hold an extended precision number. */
428 #define MAX_LITTLENUMS 6
430 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
440 #define CP_T_X 0x00008000
441 #define CP_T_Y 0x00400000
443 #define CONDS_BIT 0x00100000
444 #define LOAD_BIT 0x00100000
446 #define DOUBLE_LOAD_FLAG 0x00000001
450 const char * template_name
;
454 #define COND_ALWAYS 0xE
458 const char * template_name
;
462 struct asm_barrier_opt
464 const char * template_name
;
466 const arm_feature_set arch
;
469 /* The bit that distinguishes CPSR and SPSR. */
470 #define SPSR_BIT (1 << 22)
472 /* The individual PSR flag bits. */
473 #define PSR_c (1 << 16)
474 #define PSR_x (1 << 17)
475 #define PSR_s (1 << 18)
476 #define PSR_f (1 << 19)
481 bfd_reloc_code_real_type reloc
;
486 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
487 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
492 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
495 /* Bits for DEFINED field in neon_typed_alias. */
496 #define NTA_HASTYPE 1
497 #define NTA_HASINDEX 2
499 struct neon_typed_alias
501 unsigned char defined
;
503 struct neon_type_el eltype
;
506 /* ARM register categories. This includes coprocessor numbers and various
507 architecture extensions' registers. */
534 /* Structure for a hash table entry for a register.
535 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
536 information which states whether a vector type or index is specified (for a
537 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
543 unsigned char builtin
;
544 struct neon_typed_alias
* neon
;
547 /* Diagnostics used when we don't get a register of the expected type. */
548 const char * const reg_expected_msgs
[] =
550 N_("ARM register expected"),
551 N_("bad or missing co-processor number"),
552 N_("co-processor register expected"),
553 N_("FPA register expected"),
554 N_("VFP single precision register expected"),
555 N_("VFP/Neon double precision register expected"),
556 N_("Neon quad precision register expected"),
557 N_("VFP single or double precision register expected"),
558 N_("Neon double or quad precision register expected"),
559 N_("VFP single, double or Neon quad precision register expected"),
560 N_("VFP system register expected"),
561 N_("Maverick MVF register expected"),
562 N_("Maverick MVD register expected"),
563 N_("Maverick MVFX register expected"),
564 N_("Maverick MVDX register expected"),
565 N_("Maverick MVAX register expected"),
566 N_("Maverick DSPSC register expected"),
567 N_("iWMMXt data register expected"),
568 N_("iWMMXt control register expected"),
569 N_("iWMMXt scalar register expected"),
570 N_("XScale accumulator register expected"),
573 /* Some well known registers that we refer to directly elsewhere. */
579 /* ARM instructions take 4bytes in the object file, Thumb instructions
585 /* Basic string to match. */
586 const char * template_name
;
588 /* Parameters to instruction. */
589 unsigned int operands
[8];
591 /* Conditional tag - see opcode_lookup. */
592 unsigned int tag
: 4;
594 /* Basic instruction code. */
595 unsigned int avalue
: 28;
597 /* Thumb-format instruction code. */
600 /* Which architecture variant provides this instruction. */
601 const arm_feature_set
* avariant
;
602 const arm_feature_set
* tvariant
;
604 /* Function to call to encode instruction in ARM format. */
605 void (* aencode
) (void);
607 /* Function to call to encode instruction in Thumb format. */
608 void (* tencode
) (void);
611 /* Defines for various bits that we will want to toggle. */
612 #define INST_IMMEDIATE 0x02000000
613 #define OFFSET_REG 0x02000000
614 #define HWOFFSET_IMM 0x00400000
615 #define SHIFT_BY_REG 0x00000010
616 #define PRE_INDEX 0x01000000
617 #define INDEX_UP 0x00800000
618 #define WRITE_BACK 0x00200000
619 #define LDM_TYPE_2_OR_3 0x00400000
620 #define CPSI_MMOD 0x00020000
622 #define LITERAL_MASK 0xf000f000
623 #define OPCODE_MASK 0xfe1fffff
624 #define V4_STR_BIT 0x00000020
626 #define T2_SUBS_PC_LR 0xf3de8f00
628 #define DATA_OP_SHIFT 21
630 #define T2_OPCODE_MASK 0xfe1fffff
631 #define T2_DATA_OP_SHIFT 21
633 #define A_COND_MASK 0xf0000000
634 #define A_PUSH_POP_OP_MASK 0x0fff0000
636 /* Opcodes for pushing/poping registers to/from the stack. */
637 #define A1_OPCODE_PUSH 0x092d0000
638 #define A2_OPCODE_PUSH 0x052d0004
639 #define A2_OPCODE_POP 0x049d0004
641 /* Codes to distinguish the arithmetic instructions. */
652 #define OPCODE_CMP 10
653 #define OPCODE_CMN 11
654 #define OPCODE_ORR 12
655 #define OPCODE_MOV 13
656 #define OPCODE_BIC 14
657 #define OPCODE_MVN 15
659 #define T2_OPCODE_AND 0
660 #define T2_OPCODE_BIC 1
661 #define T2_OPCODE_ORR 2
662 #define T2_OPCODE_ORN 3
663 #define T2_OPCODE_EOR 4
664 #define T2_OPCODE_ADD 8
665 #define T2_OPCODE_ADC 10
666 #define T2_OPCODE_SBC 11
667 #define T2_OPCODE_SUB 13
668 #define T2_OPCODE_RSB 14
670 #define T_OPCODE_MUL 0x4340
671 #define T_OPCODE_TST 0x4200
672 #define T_OPCODE_CMN 0x42c0
673 #define T_OPCODE_NEG 0x4240
674 #define T_OPCODE_MVN 0x43c0
676 #define T_OPCODE_ADD_R3 0x1800
677 #define T_OPCODE_SUB_R3 0x1a00
678 #define T_OPCODE_ADD_HI 0x4400
679 #define T_OPCODE_ADD_ST 0xb000
680 #define T_OPCODE_SUB_ST 0xb080
681 #define T_OPCODE_ADD_SP 0xa800
682 #define T_OPCODE_ADD_PC 0xa000
683 #define T_OPCODE_ADD_I8 0x3000
684 #define T_OPCODE_SUB_I8 0x3800
685 #define T_OPCODE_ADD_I3 0x1c00
686 #define T_OPCODE_SUB_I3 0x1e00
688 #define T_OPCODE_ASR_R 0x4100
689 #define T_OPCODE_LSL_R 0x4080
690 #define T_OPCODE_LSR_R 0x40c0
691 #define T_OPCODE_ROR_R 0x41c0
692 #define T_OPCODE_ASR_I 0x1000
693 #define T_OPCODE_LSL_I 0x0000
694 #define T_OPCODE_LSR_I 0x0800
696 #define T_OPCODE_MOV_I8 0x2000
697 #define T_OPCODE_CMP_I8 0x2800
698 #define T_OPCODE_CMP_LR 0x4280
699 #define T_OPCODE_MOV_HR 0x4600
700 #define T_OPCODE_CMP_HR 0x4500
702 #define T_OPCODE_LDR_PC 0x4800
703 #define T_OPCODE_LDR_SP 0x9800
704 #define T_OPCODE_STR_SP 0x9000
705 #define T_OPCODE_LDR_IW 0x6800
706 #define T_OPCODE_STR_IW 0x6000
707 #define T_OPCODE_LDR_IH 0x8800
708 #define T_OPCODE_STR_IH 0x8000
709 #define T_OPCODE_LDR_IB 0x7800
710 #define T_OPCODE_STR_IB 0x7000
711 #define T_OPCODE_LDR_RW 0x5800
712 #define T_OPCODE_STR_RW 0x5000
713 #define T_OPCODE_LDR_RH 0x5a00
714 #define T_OPCODE_STR_RH 0x5200
715 #define T_OPCODE_LDR_RB 0x5c00
716 #define T_OPCODE_STR_RB 0x5400
718 #define T_OPCODE_PUSH 0xb400
719 #define T_OPCODE_POP 0xbc00
721 #define T_OPCODE_BRANCH 0xe000
723 #define THUMB_SIZE 2 /* Size of thumb instruction. */
724 #define THUMB_PP_PC_LR 0x0100
725 #define THUMB_LOAD_BIT 0x0800
726 #define THUMB2_LOAD_BIT 0x00100000
728 #define BAD_ARGS _("bad arguments to instruction")
729 #define BAD_SP _("r13 not allowed here")
730 #define BAD_PC _("r15 not allowed here")
731 #define BAD_COND _("instruction cannot be conditional")
732 #define BAD_OVERLAP _("registers may not be the same")
733 #define BAD_HIREG _("lo register required")
734 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
735 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
736 #define BAD_BRANCH _("branch must be last instruction in IT block")
737 #define BAD_NOT_IT _("instruction not allowed in IT block")
738 #define BAD_FPU _("selected FPU does not support instruction")
739 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
740 #define BAD_IT_COND _("incorrect condition in IT block")
741 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
742 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
743 #define BAD_PC_ADDRESSING \
744 _("cannot use register index with PC-relative addressing")
745 #define BAD_PC_WRITEBACK \
746 _("cannot use writeback with PC-relative addressing")
747 #define BAD_RANGE _("branch out of range")
749 static struct hash_control
* arm_ops_hsh
;
750 static struct hash_control
* arm_cond_hsh
;
751 static struct hash_control
* arm_shift_hsh
;
752 static struct hash_control
* arm_psr_hsh
;
753 static struct hash_control
* arm_v7m_psr_hsh
;
754 static struct hash_control
* arm_reg_hsh
;
755 static struct hash_control
* arm_reloc_hsh
;
756 static struct hash_control
* arm_barrier_opt_hsh
;
758 /* Stuff needed to resolve the label ambiguity
767 symbolS
* last_label_seen
;
768 static int label_is_thumb_function_name
= FALSE
;
770 /* Literal pool structure. Held on a per-section
771 and per-sub-section basis. */
773 #define MAX_LITERAL_POOL_SIZE 1024
774 typedef struct literal_pool
776 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
777 unsigned int next_free_entry
;
783 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
785 struct literal_pool
* next
;
788 /* Pointer to a linked list of literal pools. */
789 literal_pool
* list_of_pools
= NULL
;
792 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
794 static struct current_it now_it
;
798 now_it_compatible (int cond
)
800 return (cond
& ~1) == (now_it
.cc
& ~1);
804 conditional_insn (void)
806 return inst
.cond
!= COND_ALWAYS
;
809 static int in_it_block (void);
811 static int handle_it_state (void);
813 static void force_automatic_it_block_close (void);
815 static void it_fsm_post_encode (void);
817 #define set_it_insn_type(type) \
820 inst.it_insn_type = type; \
821 if (handle_it_state () == FAIL) \
826 #define set_it_insn_type_nonvoid(type, failret) \
829 inst.it_insn_type = type; \
830 if (handle_it_state () == FAIL) \
835 #define set_it_insn_type_last() \
838 if (inst.cond == COND_ALWAYS) \
839 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
841 set_it_insn_type (INSIDE_IT_LAST_INSN); \
847 /* This array holds the chars that always start a comment. If the
848 pre-processor is disabled, these aren't very useful. */
849 const char comment_chars
[] = "@";
851 /* This array holds the chars that only start a comment at the beginning of
852 a line. If the line seems to have the form '# 123 filename'
853 .line and .file directives will appear in the pre-processed output. */
854 /* Note that input_file.c hand checks for '#' at the beginning of the
855 first line of the input file. This is because the compiler outputs
856 #NO_APP at the beginning of its output. */
857 /* Also note that comments like this one will always work. */
858 const char line_comment_chars
[] = "#";
860 const char line_separator_chars
[] = ";";
862 /* Chars that can be used to separate mant
863 from exp in floating point numbers. */
864 const char EXP_CHARS
[] = "eE";
866 /* Chars that mean this number is a floating point constant. */
870 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
872 /* Prefix characters that indicate the start of an immediate
874 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
876 /* Separator character handling. */
878 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
881 skip_past_char (char ** str
, char c
)
892 #define skip_past_comma(str) skip_past_char (str, ',')
894 /* Arithmetic expressions (possibly involving symbols). */
896 /* Return TRUE if anything in the expression is a bignum. */
899 walk_no_bignums (symbolS
* sp
)
901 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
904 if (symbol_get_value_expression (sp
)->X_add_symbol
)
906 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
907 || (symbol_get_value_expression (sp
)->X_op_symbol
908 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
914 static int in_my_get_expression
= 0;
916 /* Third argument to my_get_expression. */
917 #define GE_NO_PREFIX 0
918 #define GE_IMM_PREFIX 1
919 #define GE_OPT_PREFIX 2
920 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
921 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
922 #define GE_OPT_PREFIX_BIG 3
925 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
930 /* In unified syntax, all prefixes are optional. */
932 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
937 case GE_NO_PREFIX
: break;
939 if (!is_immediate_prefix (**str
))
941 inst
.error
= _("immediate expression requires a # prefix");
947 case GE_OPT_PREFIX_BIG
:
948 if (is_immediate_prefix (**str
))
954 memset (ep
, 0, sizeof (expressionS
));
956 save_in
= input_line_pointer
;
957 input_line_pointer
= *str
;
958 in_my_get_expression
= 1;
959 seg
= expression (ep
);
960 in_my_get_expression
= 0;
962 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
964 /* We found a bad or missing expression in md_operand(). */
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
967 if (inst
.error
== NULL
)
968 inst
.error
= (ep
->X_op
== O_absent
969 ? _("missing expression") :_("bad expression"));
974 if (seg
!= absolute_section
975 && seg
!= text_section
976 && seg
!= data_section
977 && seg
!= bss_section
978 && seg
!= undefined_section
)
980 inst
.error
= _("bad segment");
981 *str
= input_line_pointer
;
982 input_line_pointer
= save_in
;
989 /* Get rid of any bignums now, so that we don't generate an error for which
990 we can't establish a line number later on. Big numbers are never valid
991 in instructions, which is where this routine is always called. */
992 if (prefix_mode
!= GE_OPT_PREFIX_BIG
993 && (ep
->X_op
== O_big
995 && (walk_no_bignums (ep
->X_add_symbol
)
997 && walk_no_bignums (ep
->X_op_symbol
))))))
999 inst
.error
= _("invalid constant");
1000 *str
= input_line_pointer
;
1001 input_line_pointer
= save_in
;
1005 *str
= input_line_pointer
;
1006 input_line_pointer
= save_in
;
1010 /* Turn a string in input_line_pointer into a floating point constant
1011 of type TYPE, and store the appropriate bytes in *LITP. The number
1012 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1013 returned, or NULL on OK.
1015 Note that fp constants aren't represent in the normal way on the ARM.
1016 In big endian mode, things are as expected. However, in little endian
1017 mode fp constants are big-endian word-wise, and little-endian byte-wise
1018 within the words. For example, (double) 1.1 in big endian mode is
1019 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1020 the byte sequence 99 99 f1 3f 9a 99 99 99.
1022 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1025 md_atof (int type
, char * litP
, int * sizeP
)
1028 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1060 return _("Unrecognized or unsupported floating point constant");
1063 t
= atof_ieee (input_line_pointer
, type
, words
);
1065 input_line_pointer
= t
;
1066 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1068 if (target_big_endian
)
1070 for (i
= 0; i
< prec
; i
++)
1072 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1073 litP
+= sizeof (LITTLENUM_TYPE
);
1078 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1079 for (i
= prec
- 1; i
>= 0; i
--)
1081 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1082 litP
+= sizeof (LITTLENUM_TYPE
);
1085 /* For a 4 byte float the order of elements in `words' is 1 0.
1086 For an 8 byte float the order is 1 0 3 2. */
1087 for (i
= 0; i
< prec
; i
+= 2)
1089 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1090 sizeof (LITTLENUM_TYPE
));
1091 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1092 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1093 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1100 /* We handle all bad expressions here, so that we can report the faulty
1101 instruction in the error message. */
1103 md_operand (expressionS
* exp
)
1105 if (in_my_get_expression
)
1106 exp
->X_op
= O_illegal
;
1109 /* Immediate values. */
1111 /* Generic immediate-value read function for use in directives.
1112 Accepts anything that 'expression' can fold to a constant.
1113 *val receives the number. */
1116 immediate_for_directive (int *val
)
1119 exp
.X_op
= O_illegal
;
1121 if (is_immediate_prefix (*input_line_pointer
))
1123 input_line_pointer
++;
1127 if (exp
.X_op
!= O_constant
)
1129 as_bad (_("expected #constant"));
1130 ignore_rest_of_line ();
1133 *val
= exp
.X_add_number
;
1138 /* Register parsing. */
1140 /* Generic register parser. CCP points to what should be the
1141 beginning of a register name. If it is indeed a valid register
1142 name, advance CCP over it and return the reg_entry structure;
1143 otherwise return NULL. Does not issue diagnostics. */
1145 static struct reg_entry
*
1146 arm_reg_parse_multi (char **ccp
)
1150 struct reg_entry
*reg
;
1152 #ifdef REGISTER_PREFIX
1153 if (*start
!= REGISTER_PREFIX
)
1157 #ifdef OPTIONAL_REGISTER_PREFIX
1158 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1163 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1168 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1170 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1180 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1181 enum arm_reg_type type
)
1183 /* Alternative syntaxes are accepted for a few register classes. */
1190 /* Generic coprocessor register names are allowed for these. */
1191 if (reg
&& reg
->type
== REG_TYPE_CN
)
1196 /* For backward compatibility, a bare number is valid here. */
1198 unsigned long processor
= strtoul (start
, ccp
, 10);
1199 if (*ccp
!= start
&& processor
<= 15)
1203 case REG_TYPE_MMXWC
:
1204 /* WC includes WCG. ??? I'm not sure this is true for all
1205 instructions that take WC registers. */
1206 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1217 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1218 return value is the register number or FAIL. */
1221 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1224 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1227 /* Do not allow a scalar (reg+index) to parse as a register. */
1228 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1231 if (reg
&& reg
->type
== type
)
1234 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1241 /* Parse a Neon type specifier. *STR should point at the leading '.'
1242 character. Does no verification at this stage that the type fits the opcode
1249 Can all be legally parsed by this function.
1251 Fills in neon_type struct pointer with parsed information, and updates STR
1252 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1253 type, FAIL if not. */
1256 parse_neon_type (struct neon_type
*type
, char **str
)
1263 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1265 enum neon_el_type thistype
= NT_untyped
;
1266 unsigned thissize
= -1u;
1273 /* Just a size without an explicit type. */
1277 switch (TOLOWER (*ptr
))
1279 case 'i': thistype
= NT_integer
; break;
1280 case 'f': thistype
= NT_float
; break;
1281 case 'p': thistype
= NT_poly
; break;
1282 case 's': thistype
= NT_signed
; break;
1283 case 'u': thistype
= NT_unsigned
; break;
1285 thistype
= NT_float
;
1290 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1296 /* .f is an abbreviation for .f32. */
1297 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1302 thissize
= strtoul (ptr
, &ptr
, 10);
1304 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1307 as_bad (_("bad size %d in type specifier"), thissize
);
1315 type
->el
[type
->elems
].type
= thistype
;
1316 type
->el
[type
->elems
].size
= thissize
;
1321 /* Empty/missing type is not a successful parse. */
1322 if (type
->elems
== 0)
1330 /* Errors may be set multiple times during parsing or bit encoding
1331 (particularly in the Neon bits), but usually the earliest error which is set
1332 will be the most meaningful. Avoid overwriting it with later (cascading)
1333 errors by calling this function. */
1336 first_error (const char *err
)
1342 /* Parse a single type, e.g. ".s32", leading period included. */
1344 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1347 struct neon_type optype
;
1351 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1353 if (optype
.elems
== 1)
1354 *vectype
= optype
.el
[0];
1357 first_error (_("only one type should be specified for operand"));
1363 first_error (_("vector type expected"));
1375 /* Special meanings for indices (which have a range of 0-7), which will fit into
1378 #define NEON_ALL_LANES 15
1379 #define NEON_INTERLEAVE_LANES 14
1381 /* Parse either a register or a scalar, with an optional type. Return the
1382 register number, and optionally fill in the actual type of the register
1383 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1384 type/index information in *TYPEINFO. */
1387 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1388 enum arm_reg_type
*rtype
,
1389 struct neon_typed_alias
*typeinfo
)
1392 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1393 struct neon_typed_alias atype
;
1394 struct neon_type_el parsetype
;
1398 atype
.eltype
.type
= NT_invtype
;
1399 atype
.eltype
.size
= -1;
1401 /* Try alternate syntax for some types of register. Note these are mutually
1402 exclusive with the Neon syntax extensions. */
1405 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1413 /* Undo polymorphism when a set of register types may be accepted. */
1414 if ((type
== REG_TYPE_NDQ
1415 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1416 || (type
== REG_TYPE_VFSD
1417 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1418 || (type
== REG_TYPE_NSDQ
1419 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1420 || reg
->type
== REG_TYPE_NQ
))
1421 || (type
== REG_TYPE_MMXWC
1422 && (reg
->type
== REG_TYPE_MMXWCG
)))
1423 type
= (enum arm_reg_type
) reg
->type
;
1425 if (type
!= reg
->type
)
1431 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1433 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1435 first_error (_("can't redefine type for operand"));
1438 atype
.defined
|= NTA_HASTYPE
;
1439 atype
.eltype
= parsetype
;
1442 if (skip_past_char (&str
, '[') == SUCCESS
)
1444 if (type
!= REG_TYPE_VFD
)
1446 first_error (_("only D registers may be indexed"));
1450 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1452 first_error (_("can't change index for operand"));
1456 atype
.defined
|= NTA_HASINDEX
;
1458 if (skip_past_char (&str
, ']') == SUCCESS
)
1459 atype
.index
= NEON_ALL_LANES
;
1464 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1466 if (exp
.X_op
!= O_constant
)
1468 first_error (_("constant expression required"));
1472 if (skip_past_char (&str
, ']') == FAIL
)
1475 atype
.index
= exp
.X_add_number
;
1490 /* Like arm_reg_parse, but allow allow the following extra features:
1491 - If RTYPE is non-zero, return the (possibly restricted) type of the
1492 register (e.g. Neon double or quad reg when either has been requested).
1493 - If this is a Neon vector type with additional type information, fill
1494 in the struct pointed to by VECTYPE (if non-NULL).
1495 This function will fault on encountering a scalar. */
1498 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1499 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1501 struct neon_typed_alias atype
;
1503 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1508 /* Do not allow regname(... to parse as a register. */
1512 /* Do not allow a scalar (reg+index) to parse as a register. */
1513 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1515 first_error (_("register operand expected, but got scalar"));
1520 *vectype
= atype
.eltype
;
1527 #define NEON_SCALAR_REG(X) ((X) >> 4)
1528 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1530 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1531 have enough information to be able to do a good job bounds-checking. So, we
1532 just do easy checks here, and do further checks later. */
1535 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1539 struct neon_typed_alias atype
;
1541 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1543 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1546 if (atype
.index
== NEON_ALL_LANES
)
1548 first_error (_("scalar must have an index"));
1551 else if (atype
.index
>= 64 / elsize
)
1553 first_error (_("scalar index out of range"));
1558 *type
= atype
.eltype
;
1562 return reg
* 16 + atype
.index
;
1565 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1568 parse_reg_list (char ** strp
)
1570 char * str
= * strp
;
1574 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1591 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1601 first_error (_("bad range in register list"));
1605 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1607 if (range
& (1 << i
))
1609 (_("Warning: duplicated register (r%d) in register list"),
1617 if (range
& (1 << reg
))
1618 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1620 else if (reg
<= cur_reg
)
1621 as_tsktsk (_("Warning: register range not in ascending order"));
1626 while (skip_past_comma (&str
) != FAIL
1627 || (in_range
= 1, *str
++ == '-'));
1632 first_error (_("missing `}'"));
1640 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1643 if (exp
.X_op
== O_constant
)
1645 if (exp
.X_add_number
1646 != (exp
.X_add_number
& 0x0000ffff))
1648 inst
.error
= _("invalid register mask");
1652 if ((range
& exp
.X_add_number
) != 0)
1654 int regno
= range
& exp
.X_add_number
;
1657 regno
= (1 << regno
) - 1;
1659 (_("Warning: duplicated register (r%d) in register list"),
1663 range
|= exp
.X_add_number
;
1667 if (inst
.reloc
.type
!= 0)
1669 inst
.error
= _("expression too complex");
1673 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1674 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1675 inst
.reloc
.pc_rel
= 0;
1679 if (*str
== '|' || *str
== '+')
1685 while (another_range
);
1691 /* Types of registers in a list. */
1700 /* Parse a VFP register list. If the string is invalid return FAIL.
1701 Otherwise return the number of registers, and set PBASE to the first
1702 register. Parses registers of type ETYPE.
1703 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1704 - Q registers can be used to specify pairs of D registers
1705 - { } can be omitted from around a singleton register list
1706 FIXME: This is not implemented, as it would require backtracking in
1709 This could be done (the meaning isn't really ambiguous), but doesn't
1710 fit in well with the current parsing framework.
1711 - 32 D registers may be used (also true for VFPv3).
1712 FIXME: Types are ignored in these register lists, which is probably a
1716 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1721 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1725 unsigned long mask
= 0;
1730 inst
.error
= _("expecting {");
1739 regtype
= REG_TYPE_VFS
;
1744 regtype
= REG_TYPE_VFD
;
1747 case REGLIST_NEON_D
:
1748 regtype
= REG_TYPE_NDQ
;
1752 if (etype
!= REGLIST_VFP_S
)
1754 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1755 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1759 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1762 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1769 base_reg
= max_regs
;
1773 int setmask
= 1, addregs
= 1;
1775 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1777 if (new_base
== FAIL
)
1779 first_error (_(reg_expected_msgs
[regtype
]));
1783 if (new_base
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 /* Note: a value of 2 * n is returned for the register Q<n>. */
1790 if (regtype
== REG_TYPE_NQ
)
1796 if (new_base
< base_reg
)
1797 base_reg
= new_base
;
1799 if (mask
& (setmask
<< new_base
))
1801 first_error (_("invalid register list"));
1805 if ((mask
>> new_base
) != 0 && ! warned
)
1807 as_tsktsk (_("register list not in ascending order"));
1811 mask
|= setmask
<< new_base
;
1814 if (*str
== '-') /* We have the start of a range expression */
1820 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1823 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1827 if (high_range
>= max_regs
)
1829 first_error (_("register out of range in list"));
1833 if (regtype
== REG_TYPE_NQ
)
1834 high_range
= high_range
+ 1;
1836 if (high_range
<= new_base
)
1838 inst
.error
= _("register range not in ascending order");
1842 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1844 if (mask
& (setmask
<< new_base
))
1846 inst
.error
= _("invalid register list");
1850 mask
|= setmask
<< new_base
;
1855 while (skip_past_comma (&str
) != FAIL
);
1859 /* Sanity check -- should have raised a parse error above. */
1860 if (count
== 0 || count
> max_regs
)
1865 /* Final test -- the registers must be consecutive. */
1867 for (i
= 0; i
< count
; i
++)
1869 if ((mask
& (1u << i
)) == 0)
1871 inst
.error
= _("non-contiguous register range");
1881 /* True if two alias types are the same. */
1884 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1892 if (a
->defined
!= b
->defined
)
1895 if ((a
->defined
& NTA_HASTYPE
) != 0
1896 && (a
->eltype
.type
!= b
->eltype
.type
1897 || a
->eltype
.size
!= b
->eltype
.size
))
1900 if ((a
->defined
& NTA_HASINDEX
) != 0
1901 && (a
->index
!= b
->index
))
1907 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1908 The base register is put in *PBASE.
1909 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1911 The register stride (minus one) is put in bit 4 of the return value.
1912 Bits [6:5] encode the list length (minus one).
1913 The type of the list elements is put in *ELTYPE, if non-NULL. */
1915 #define NEON_LANE(X) ((X) & 0xf)
1916 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1917 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1920 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1921 struct neon_type_el
*eltype
)
1928 int leading_brace
= 0;
1929 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1930 const char *const incr_error
= _("register stride must be 1 or 2");
1931 const char *const type_error
= _("mismatched element/structure types in list");
1932 struct neon_typed_alias firsttype
;
1934 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1939 struct neon_typed_alias atype
;
1940 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1944 first_error (_(reg_expected_msgs
[rtype
]));
1951 if (rtype
== REG_TYPE_NQ
)
1957 else if (reg_incr
== -1)
1959 reg_incr
= getreg
- base_reg
;
1960 if (reg_incr
< 1 || reg_incr
> 2)
1962 first_error (_(incr_error
));
1966 else if (getreg
!= base_reg
+ reg_incr
* count
)
1968 first_error (_(incr_error
));
1972 if (! neon_alias_types_same (&atype
, &firsttype
))
1974 first_error (_(type_error
));
1978 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1982 struct neon_typed_alias htype
;
1983 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1985 lane
= NEON_INTERLEAVE_LANES
;
1986 else if (lane
!= NEON_INTERLEAVE_LANES
)
1988 first_error (_(type_error
));
1993 else if (reg_incr
!= 1)
1995 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1999 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2002 first_error (_(reg_expected_msgs
[rtype
]));
2005 if (! neon_alias_types_same (&htype
, &firsttype
))
2007 first_error (_(type_error
));
2010 count
+= hireg
+ dregs
- getreg
;
2014 /* If we're using Q registers, we can't use [] or [n] syntax. */
2015 if (rtype
== REG_TYPE_NQ
)
2021 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2025 else if (lane
!= atype
.index
)
2027 first_error (_(type_error
));
2031 else if (lane
== -1)
2032 lane
= NEON_INTERLEAVE_LANES
;
2033 else if (lane
!= NEON_INTERLEAVE_LANES
)
2035 first_error (_(type_error
));
2040 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2042 /* No lane set by [x]. We must be interleaving structures. */
2044 lane
= NEON_INTERLEAVE_LANES
;
2047 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2048 || (count
> 1 && reg_incr
== -1))
2050 first_error (_("error parsing element/structure list"));
2054 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2056 first_error (_("expected }"));
2064 *eltype
= firsttype
.eltype
;
2069 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2072 /* Parse an explicit relocation suffix on an expression. This is
2073 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2074 arm_reloc_hsh contains no entries, so this function can only
2075 succeed if there is no () after the word. Returns -1 on error,
2076 BFD_RELOC_UNUSED if there wasn't any suffix. */
2079 parse_reloc (char **str
)
2081 struct reloc_entry
*r
;
2085 return BFD_RELOC_UNUSED
;
2090 while (*q
&& *q
!= ')' && *q
!= ',')
2095 if ((r
= (struct reloc_entry
*)
2096 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2103 /* Directives: register aliases. */
2105 static struct reg_entry
*
2106 insert_reg_alias (char *str
, unsigned number
, int type
)
2108 struct reg_entry
*new_reg
;
2111 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2113 if (new_reg
->builtin
)
2114 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2116 /* Only warn about a redefinition if it's not defined as the
2118 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2119 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2124 name
= xstrdup (str
);
2125 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2127 new_reg
->name
= name
;
2128 new_reg
->number
= number
;
2129 new_reg
->type
= type
;
2130 new_reg
->builtin
= FALSE
;
2131 new_reg
->neon
= NULL
;
2133 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2140 insert_neon_reg_alias (char *str
, int number
, int type
,
2141 struct neon_typed_alias
*atype
)
2143 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2147 first_error (_("attempt to redefine typed alias"));
2153 reg
->neon
= (struct neon_typed_alias
*)
2154 xmalloc (sizeof (struct neon_typed_alias
));
2155 *reg
->neon
= *atype
;
2159 /* Look for the .req directive. This is of the form:
2161 new_register_name .req existing_register_name
2163 If we find one, or if it looks sufficiently like one that we want to
2164 handle any error here, return TRUE. Otherwise return FALSE. */
2167 create_register_alias (char * newname
, char *p
)
2169 struct reg_entry
*old
;
2170 char *oldname
, *nbuf
;
2173 /* The input scrubber ensures that whitespace after the mnemonic is
2174 collapsed to single spaces. */
2176 if (strncmp (oldname
, " .req ", 6) != 0)
2180 if (*oldname
== '\0')
2183 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2186 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2190 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2191 the desired alias name, and p points to its end. If not, then
2192 the desired alias name is in the global original_case_string. */
2193 #ifdef TC_CASE_SENSITIVE
2196 newname
= original_case_string
;
2197 nlen
= strlen (newname
);
2200 nbuf
= (char *) alloca (nlen
+ 1);
2201 memcpy (nbuf
, newname
, nlen
);
2204 /* Create aliases under the new name as stated; an all-lowercase
2205 version of the new name; and an all-uppercase version of the new
2207 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2209 for (p
= nbuf
; *p
; p
++)
2212 if (strncmp (nbuf
, newname
, nlen
))
2214 /* If this attempt to create an additional alias fails, do not bother
2215 trying to create the all-lower case alias. We will fail and issue
2216 a second, duplicate error message. This situation arises when the
2217 programmer does something like:
2220 The second .req creates the "Foo" alias but then fails to create
2221 the artificial FOO alias because it has already been created by the
2223 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2227 for (p
= nbuf
; *p
; p
++)
2230 if (strncmp (nbuf
, newname
, nlen
))
2231 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2237 /* Create a Neon typed/indexed register alias using directives, e.g.:
2242 These typed registers can be used instead of the types specified after the
2243 Neon mnemonic, so long as all operands given have types. Types can also be
2244 specified directly, e.g.:
2245 vadd d0.s32, d1.s32, d2.s32 */
2248 create_neon_reg_alias (char *newname
, char *p
)
2250 enum arm_reg_type basetype
;
2251 struct reg_entry
*basereg
;
2252 struct reg_entry mybasereg
;
2253 struct neon_type ntype
;
2254 struct neon_typed_alias typeinfo
;
2255 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2258 typeinfo
.defined
= 0;
2259 typeinfo
.eltype
.type
= NT_invtype
;
2260 typeinfo
.eltype
.size
= -1;
2261 typeinfo
.index
= -1;
2265 if (strncmp (p
, " .dn ", 5) == 0)
2266 basetype
= REG_TYPE_VFD
;
2267 else if (strncmp (p
, " .qn ", 5) == 0)
2268 basetype
= REG_TYPE_NQ
;
2277 basereg
= arm_reg_parse_multi (&p
);
2279 if (basereg
&& basereg
->type
!= basetype
)
2281 as_bad (_("bad type for register"));
2285 if (basereg
== NULL
)
2288 /* Try parsing as an integer. */
2289 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("expression must be constant"));
2295 basereg
= &mybasereg
;
2296 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2302 typeinfo
= *basereg
->neon
;
2304 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2306 /* We got a type. */
2307 if (typeinfo
.defined
& NTA_HASTYPE
)
2309 as_bad (_("can't redefine the type of a register alias"));
2313 typeinfo
.defined
|= NTA_HASTYPE
;
2314 if (ntype
.elems
!= 1)
2316 as_bad (_("you must specify a single type only"));
2319 typeinfo
.eltype
= ntype
.el
[0];
2322 if (skip_past_char (&p
, '[') == SUCCESS
)
2325 /* We got a scalar index. */
2327 if (typeinfo
.defined
& NTA_HASINDEX
)
2329 as_bad (_("can't redefine the index of a scalar alias"));
2333 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("scalar index must be constant"));
2341 typeinfo
.defined
|= NTA_HASINDEX
;
2342 typeinfo
.index
= exp
.X_add_number
;
2344 if (skip_past_char (&p
, ']') == FAIL
)
2346 as_bad (_("expecting ]"));
2351 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2352 the desired alias name, and p points to its end. If not, then
2353 the desired alias name is in the global original_case_string. */
2354 #ifdef TC_CASE_SENSITIVE
2355 namelen
= nameend
- newname
;
2357 newname
= original_case_string
;
2358 namelen
= strlen (newname
);
2361 namebuf
= (char *) alloca (namelen
+ 1);
2362 strncpy (namebuf
, newname
, namelen
);
2363 namebuf
[namelen
] = '\0';
2365 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2366 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2368 /* Insert name in all uppercase. */
2369 for (p
= namebuf
; *p
; p
++)
2372 if (strncmp (namebuf
, newname
, namelen
))
2373 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2374 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2376 /* Insert name in all lowercase. */
2377 for (p
= namebuf
; *p
; p
++)
2380 if (strncmp (namebuf
, newname
, namelen
))
2381 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2382 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2387 /* Should never be called, as .req goes between the alias and the
2388 register name, not at the beginning of the line. */
2391 s_req (int a ATTRIBUTE_UNUSED
)
2393 as_bad (_("invalid syntax for .req directive"));
2397 s_dn (int a ATTRIBUTE_UNUSED
)
2399 as_bad (_("invalid syntax for .dn directive"));
2403 s_qn (int a ATTRIBUTE_UNUSED
)
2405 as_bad (_("invalid syntax for .qn directive"));
2408 /* The .unreq directive deletes an alias which was previously defined
2409 by .req. For example:
2415 s_unreq (int a ATTRIBUTE_UNUSED
)
2420 name
= input_line_pointer
;
2422 while (*input_line_pointer
!= 0
2423 && *input_line_pointer
!= ' '
2424 && *input_line_pointer
!= '\n')
2425 ++input_line_pointer
;
2427 saved_char
= *input_line_pointer
;
2428 *input_line_pointer
= 0;
2431 as_bad (_("invalid syntax for .unreq directive"));
2434 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2438 as_bad (_("unknown register alias '%s'"), name
);
2439 else if (reg
->builtin
)
2440 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2447 hash_delete (arm_reg_hsh
, name
, FALSE
);
2448 free ((char *) reg
->name
);
2453 /* Also locate the all upper case and all lower case versions.
2454 Do not complain if we cannot find one or the other as it
2455 was probably deleted above. */
2457 nbuf
= strdup (name
);
2458 for (p
= nbuf
; *p
; p
++)
2460 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2463 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2464 free ((char *) reg
->name
);
2470 for (p
= nbuf
; *p
; p
++)
2472 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2475 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2476 free ((char *) reg
->name
);
2486 *input_line_pointer
= saved_char
;
2487 demand_empty_rest_of_line ();
2490 /* Directives: Instruction set selection. */
2493 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2494 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2495 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2496 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2498 /* Create a new mapping symbol for the transition to STATE. */
2501 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2504 const char * symname
;
2511 type
= BSF_NO_FLAGS
;
2515 type
= BSF_NO_FLAGS
;
2519 type
= BSF_NO_FLAGS
;
2525 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2526 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2531 THUMB_SET_FUNC (symbolP
, 0);
2532 ARM_SET_THUMB (symbolP
, 0);
2533 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2537 THUMB_SET_FUNC (symbolP
, 1);
2538 ARM_SET_THUMB (symbolP
, 1);
2539 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2547 /* Save the mapping symbols for future reference. Also check that
2548 we do not place two mapping symbols at the same offset within a
2549 frag. We'll handle overlap between frags in
2550 check_mapping_symbols.
2552 If .fill or other data filling directive generates zero sized data,
2553 the mapping symbol for the following code will have the same value
2554 as the one generated for the data filling directive. In this case,
2555 we replace the old symbol with the new one at the same address. */
2558 if (frag
->tc_frag_data
.first_map
!= NULL
)
2560 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2561 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2563 frag
->tc_frag_data
.first_map
= symbolP
;
2565 if (frag
->tc_frag_data
.last_map
!= NULL
)
2567 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2568 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2569 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2571 frag
->tc_frag_data
.last_map
= symbolP
;
2574 /* We must sometimes convert a region marked as code to data during
2575 code alignment, if an odd number of bytes have to be padded. The
2576 code mapping symbol is pushed to an aligned address. */
2579 insert_data_mapping_symbol (enum mstate state
,
2580 valueT value
, fragS
*frag
, offsetT bytes
)
2582 /* If there was already a mapping symbol, remove it. */
2583 if (frag
->tc_frag_data
.last_map
!= NULL
2584 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2586 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2590 know (frag
->tc_frag_data
.first_map
== symp
);
2591 frag
->tc_frag_data
.first_map
= NULL
;
2593 frag
->tc_frag_data
.last_map
= NULL
;
2594 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2597 make_mapping_symbol (MAP_DATA
, value
, frag
);
2598 make_mapping_symbol (state
, value
+ bytes
, frag
);
2601 static void mapping_state_2 (enum mstate state
, int max_chars
);
2603 /* Set the mapping state to STATE. Only call this when about to
2604 emit some STATE bytes to the file. */
2607 mapping_state (enum mstate state
)
2609 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2611 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2613 if (mapstate
== state
)
2614 /* The mapping symbol has already been emitted.
2615 There is nothing else to do. */
2618 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2620 All ARM instructions require 4-byte alignment.
2621 (Almost) all Thumb instructions require 2-byte alignment.
2623 When emitting instructions into any section, mark the section
2626 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2627 but themselves require 2-byte alignment; this applies to some
2628 PC- relative forms. However, these cases will invovle implicit
2629 literal pool generation or an explicit .align >=2, both of
2630 which will cause the section to me marked with sufficient
2631 alignment. Thus, we don't handle those cases here. */
2632 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2634 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2635 /* This case will be evaluated later in the next else. */
2637 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2638 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2640 /* Only add the symbol if the offset is > 0:
2641 if we're at the first frag, check it's size > 0;
2642 if we're not at the first frag, then for sure
2643 the offset is > 0. */
2644 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2645 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2648 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2651 mapping_state_2 (state
, 0);
2655 /* Same as mapping_state, but MAX_CHARS bytes have already been
2656 allocated. Put the mapping symbol that far back. */
2659 mapping_state_2 (enum mstate state
, int max_chars
)
2661 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2663 if (!SEG_NORMAL (now_seg
))
2666 if (mapstate
== state
)
2667 /* The mapping symbol has already been emitted.
2668 There is nothing else to do. */
2671 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2672 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2675 #define mapping_state(x) ((void)0)
2676 #define mapping_state_2(x, y) ((void)0)
2679 /* Find the real, Thumb encoded start of a Thumb function. */
2683 find_real_start (symbolS
* symbolP
)
2686 const char * name
= S_GET_NAME (symbolP
);
2687 symbolS
* new_target
;
2689 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2690 #define STUB_NAME ".real_start_of"
2695 /* The compiler may generate BL instructions to local labels because
2696 it needs to perform a branch to a far away location. These labels
2697 do not have a corresponding ".real_start_of" label. We check
2698 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2699 the ".real_start_of" convention for nonlocal branches. */
2700 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2703 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2704 new_target
= symbol_find (real_start
);
2706 if (new_target
== NULL
)
2708 as_warn (_("Failed to find real start of function: %s\n"), name
);
2709 new_target
= symbolP
;
2717 opcode_select (int width
)
2724 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2725 as_bad (_("selected processor does not support THUMB opcodes"));
2728 /* No need to force the alignment, since we will have been
2729 coming from ARM mode, which is word-aligned. */
2730 record_alignment (now_seg
, 1);
2737 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2738 as_bad (_("selected processor does not support ARM opcodes"));
2743 frag_align (2, 0, 0);
2745 record_alignment (now_seg
, 1);
2750 as_bad (_("invalid instruction size selected (%d)"), width
);
2755 s_arm (int ignore ATTRIBUTE_UNUSED
)
2758 demand_empty_rest_of_line ();
2762 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2765 demand_empty_rest_of_line ();
2769 s_code (int unused ATTRIBUTE_UNUSED
)
2773 temp
= get_absolute_expression ();
2778 opcode_select (temp
);
2782 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2787 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2789 /* If we are not already in thumb mode go into it, EVEN if
2790 the target processor does not support thumb instructions.
2791 This is used by gcc/config/arm/lib1funcs.asm for example
2792 to compile interworking support functions even if the
2793 target processor should not support interworking. */
2797 record_alignment (now_seg
, 1);
2800 demand_empty_rest_of_line ();
2804 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2808 /* The following label is the name/address of the start of a Thumb function.
2809 We need to know this for the interworking support. */
2810 label_is_thumb_function_name
= TRUE
;
2813 /* Perform a .set directive, but also mark the alias as
2814 being a thumb function. */
2817 s_thumb_set (int equiv
)
2819 /* XXX the following is a duplicate of the code for s_set() in read.c
2820 We cannot just call that code as we need to get at the symbol that
2827 /* Especial apologies for the random logic:
2828 This just grew, and could be parsed much more simply!
2830 name
= input_line_pointer
;
2831 delim
= get_symbol_end ();
2832 end_name
= input_line_pointer
;
2835 if (*input_line_pointer
!= ',')
2838 as_bad (_("expected comma after name \"%s\""), name
);
2840 ignore_rest_of_line ();
2844 input_line_pointer
++;
2847 if (name
[0] == '.' && name
[1] == '\0')
2849 /* XXX - this should not happen to .thumb_set. */
2853 if ((symbolP
= symbol_find (name
)) == NULL
2854 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2857 /* When doing symbol listings, play games with dummy fragments living
2858 outside the normal fragment chain to record the file and line info
2860 if (listing
& LISTING_SYMBOLS
)
2862 extern struct list_info_struct
* listing_tail
;
2863 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2865 memset (dummy_frag
, 0, sizeof (fragS
));
2866 dummy_frag
->fr_type
= rs_fill
;
2867 dummy_frag
->line
= listing_tail
;
2868 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2869 dummy_frag
->fr_symbol
= symbolP
;
2873 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2876 /* "set" symbols are local unless otherwise specified. */
2877 SF_SET_LOCAL (symbolP
);
2878 #endif /* OBJ_COFF */
2879 } /* Make a new symbol. */
2881 symbol_table_insert (symbolP
);
2886 && S_IS_DEFINED (symbolP
)
2887 && S_GET_SEGMENT (symbolP
) != reg_section
)
2888 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2890 pseudo_set (symbolP
);
2892 demand_empty_rest_of_line ();
2894 /* XXX Now we come to the Thumb specific bit of code. */
2896 THUMB_SET_FUNC (symbolP
, 1);
2897 ARM_SET_THUMB (symbolP
, 1);
2898 #if defined OBJ_ELF || defined OBJ_COFF
2899 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2903 /* Directives: Mode selection. */
2905 /* .syntax [unified|divided] - choose the new unified syntax
2906 (same for Arm and Thumb encoding, modulo slight differences in what
2907 can be represented) or the old divergent syntax for each mode. */
2909 s_syntax (int unused ATTRIBUTE_UNUSED
)
2913 name
= input_line_pointer
;
2914 delim
= get_symbol_end ();
2916 if (!strcasecmp (name
, "unified"))
2917 unified_syntax
= TRUE
;
2918 else if (!strcasecmp (name
, "divided"))
2919 unified_syntax
= FALSE
;
2922 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2925 *input_line_pointer
= delim
;
2926 demand_empty_rest_of_line ();
2929 /* Directives: sectioning and alignment. */
2931 /* Same as s_align_ptwo but align 0 => align 2. */
2934 s_align (int unused ATTRIBUTE_UNUSED
)
2939 long max_alignment
= 15;
2941 temp
= get_absolute_expression ();
2942 if (temp
> max_alignment
)
2943 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2946 as_bad (_("alignment negative. 0 assumed."));
2950 if (*input_line_pointer
== ',')
2952 input_line_pointer
++;
2953 temp_fill
= get_absolute_expression ();
2965 /* Only make a frag if we HAVE to. */
2966 if (temp
&& !need_pass_2
)
2968 if (!fill_p
&& subseg_text_p (now_seg
))
2969 frag_align_code (temp
, 0);
2971 frag_align (temp
, (int) temp_fill
, 0);
2973 demand_empty_rest_of_line ();
2975 record_alignment (now_seg
, temp
);
2979 s_bss (int ignore ATTRIBUTE_UNUSED
)
2981 /* We don't support putting frags in the BSS segment, we fake it by
2982 marking in_bss, then looking at s_skip for clues. */
2983 subseg_set (bss_section
, 0);
2984 demand_empty_rest_of_line ();
2986 #ifdef md_elf_section_change_hook
2987 md_elf_section_change_hook ();
2992 s_even (int ignore ATTRIBUTE_UNUSED
)
2994 /* Never make frag if expect extra pass. */
2996 frag_align (1, 0, 0);
2998 record_alignment (now_seg
, 1);
3000 demand_empty_rest_of_line ();
3003 /* Directives: Literal pools. */
3005 static literal_pool
*
3006 find_literal_pool (void)
3008 literal_pool
* pool
;
3010 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3012 if (pool
->section
== now_seg
3013 && pool
->sub_section
== now_subseg
)
3020 static literal_pool
*
3021 find_or_make_literal_pool (void)
3023 /* Next literal pool ID number. */
3024 static unsigned int latest_pool_num
= 1;
3025 literal_pool
* pool
;
3027 pool
= find_literal_pool ();
3031 /* Create a new pool. */
3032 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3036 pool
->next_free_entry
= 0;
3037 pool
->section
= now_seg
;
3038 pool
->sub_section
= now_subseg
;
3039 pool
->next
= list_of_pools
;
3040 pool
->symbol
= NULL
;
3042 /* Add it to the list. */
3043 list_of_pools
= pool
;
3046 /* New pools, and emptied pools, will have a NULL symbol. */
3047 if (pool
->symbol
== NULL
)
3049 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3050 (valueT
) 0, &zero_address_frag
);
3051 pool
->id
= latest_pool_num
++;
3058 /* Add the literal in the global 'inst'
3059 structure to the relevant literal pool. */
3062 add_to_lit_pool (void)
3064 literal_pool
* pool
;
3067 pool
= find_or_make_literal_pool ();
3069 /* Check if this literal value is already in the pool. */
3070 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3072 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3073 && (inst
.reloc
.exp
.X_op
== O_constant
)
3074 && (pool
->literals
[entry
].X_add_number
3075 == inst
.reloc
.exp
.X_add_number
)
3076 && (pool
->literals
[entry
].X_unsigned
3077 == inst
.reloc
.exp
.X_unsigned
))
3080 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3081 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3082 && (pool
->literals
[entry
].X_add_number
3083 == inst
.reloc
.exp
.X_add_number
)
3084 && (pool
->literals
[entry
].X_add_symbol
3085 == inst
.reloc
.exp
.X_add_symbol
)
3086 && (pool
->literals
[entry
].X_op_symbol
3087 == inst
.reloc
.exp
.X_op_symbol
))
3091 /* Do we need to create a new entry? */
3092 if (entry
== pool
->next_free_entry
)
3094 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3096 inst
.error
= _("literal pool overflow");
3100 pool
->literals
[entry
] = inst
.reloc
.exp
;
3102 /* PR ld/12974: Record the location of the first source line to reference
3103 this entry in the literal pool. If it turns out during linking that the
3104 symbol does not exist we will be able to give an accurate line number for
3105 the (first use of the) missing reference. */
3106 if (debug_type
== DEBUG_DWARF2
)
3107 dwarf2_where (pool
->locs
+ entry
);
3109 pool
->next_free_entry
+= 1;
3112 inst
.reloc
.exp
.X_op
= O_symbol
;
3113 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3114 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3119 /* Can't use symbol_new here, so have to create a symbol and then at
3120 a later date assign it a value. Thats what these functions do. */
3123 symbol_locate (symbolS
* symbolP
,
3124 const char * name
, /* It is copied, the caller can modify. */
3125 segT segment
, /* Segment identifier (SEG_<something>). */
3126 valueT valu
, /* Symbol value. */
3127 fragS
* frag
) /* Associated fragment. */
3129 unsigned int name_length
;
3130 char * preserved_copy_of_name
;
3132 name_length
= strlen (name
) + 1; /* +1 for \0. */
3133 obstack_grow (¬es
, name
, name_length
);
3134 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3136 #ifdef tc_canonicalize_symbol_name
3137 preserved_copy_of_name
=
3138 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3141 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3143 S_SET_SEGMENT (symbolP
, segment
);
3144 S_SET_VALUE (symbolP
, valu
);
3145 symbol_clear_list_pointers (symbolP
);
3147 symbol_set_frag (symbolP
, frag
);
3149 /* Link to end of symbol chain. */
3151 extern int symbol_table_frozen
;
3153 if (symbol_table_frozen
)
3157 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3159 obj_symbol_new_hook (symbolP
);
3161 #ifdef tc_symbol_new_hook
3162 tc_symbol_new_hook (symbolP
);
3166 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3167 #endif /* DEBUG_SYMS */
3172 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3175 literal_pool
* pool
;
3178 pool
= find_literal_pool ();
3180 || pool
->symbol
== NULL
3181 || pool
->next_free_entry
== 0)
3184 mapping_state (MAP_DATA
);
3186 /* Align pool as you have word accesses.
3187 Only make a frag if we have to. */
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg
, 2);
3193 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3195 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3196 (valueT
) frag_now_fix (), frag_now
);
3197 symbol_table_insert (pool
->symbol
);
3199 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3201 #if defined OBJ_COFF || defined OBJ_ELF
3202 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3205 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3208 if (debug_type
== DEBUG_DWARF2
)
3209 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3211 /* First output the expression in the instruction to the pool. */
3212 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3215 /* Mark the pool as empty. */
3216 pool
->next_free_entry
= 0;
3217 pool
->symbol
= NULL
;
3221 /* Forward declarations for functions below, in the MD interface
3223 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3224 static valueT
create_unwind_entry (int);
3225 static void start_unwind_section (const segT
, int);
3226 static void add_unwind_opcode (valueT
, int);
3227 static void flush_pending_unwind (void);
3229 /* Directives: Data. */
3232 s_arm_elf_cons (int nbytes
)
3236 #ifdef md_flush_pending_output
3237 md_flush_pending_output ();
3240 if (is_it_end_of_statement ())
3242 demand_empty_rest_of_line ();
3246 #ifdef md_cons_align
3247 md_cons_align (nbytes
);
3250 mapping_state (MAP_DATA
);
3254 char *base
= input_line_pointer
;
3258 if (exp
.X_op
!= O_symbol
)
3259 emit_expr (&exp
, (unsigned int) nbytes
);
3262 char *before_reloc
= input_line_pointer
;
3263 reloc
= parse_reloc (&input_line_pointer
);
3266 as_bad (_("unrecognized relocation suffix"));
3267 ignore_rest_of_line ();
3270 else if (reloc
== BFD_RELOC_UNUSED
)
3271 emit_expr (&exp
, (unsigned int) nbytes
);
3274 reloc_howto_type
*howto
= (reloc_howto_type
*)
3275 bfd_reloc_type_lookup (stdoutput
,
3276 (bfd_reloc_code_real_type
) reloc
);
3277 int size
= bfd_get_reloc_size (howto
);
3279 if (reloc
== BFD_RELOC_ARM_PLT32
)
3281 as_bad (_("(plt) is only valid on branch targets"));
3282 reloc
= BFD_RELOC_UNUSED
;
3287 as_bad (_("%s relocations do not fit in %d bytes"),
3288 howto
->name
, nbytes
);
3291 /* We've parsed an expression stopping at O_symbol.
3292 But there may be more expression left now that we
3293 have parsed the relocation marker. Parse it again.
3294 XXX Surely there is a cleaner way to do this. */
3295 char *p
= input_line_pointer
;
3297 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3298 memcpy (save_buf
, base
, input_line_pointer
- base
);
3299 memmove (base
+ (input_line_pointer
- before_reloc
),
3300 base
, before_reloc
- base
);
3302 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3304 memcpy (base
, save_buf
, p
- base
);
3306 offset
= nbytes
- size
;
3307 p
= frag_more ((int) nbytes
);
3308 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3309 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3314 while (*input_line_pointer
++ == ',');
3316 /* Put terminator back into stream. */
3317 input_line_pointer
--;
3318 demand_empty_rest_of_line ();
3321 /* Emit an expression containing a 32-bit thumb instruction.
3322 Implementation based on put_thumb32_insn. */
3325 emit_thumb32_expr (expressionS
* exp
)
3327 expressionS exp_high
= *exp
;
3329 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3330 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3331 exp
->X_add_number
&= 0xffff;
3332 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3335 /* Guess the instruction size based on the opcode. */
3338 thumb_insn_size (int opcode
)
3340 if ((unsigned int) opcode
< 0xe800u
)
3342 else if ((unsigned int) opcode
>= 0xe8000000u
)
3349 emit_insn (expressionS
*exp
, int nbytes
)
3353 if (exp
->X_op
== O_constant
)
3358 size
= thumb_insn_size (exp
->X_add_number
);
3362 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3364 as_bad (_(".inst.n operand too big. "\
3365 "Use .inst.w instead"));
3370 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3371 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3373 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3375 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3376 emit_thumb32_expr (exp
);
3378 emit_expr (exp
, (unsigned int) size
);
3380 it_fsm_post_encode ();
3384 as_bad (_("cannot determine Thumb instruction size. " \
3385 "Use .inst.n/.inst.w instead"));
3388 as_bad (_("constant expression required"));
3393 /* Like s_arm_elf_cons but do not use md_cons_align and
3394 set the mapping state to MAP_ARM/MAP_THUMB. */
3397 s_arm_elf_inst (int nbytes
)
3399 if (is_it_end_of_statement ())
3401 demand_empty_rest_of_line ();
3405 /* Calling mapping_state () here will not change ARM/THUMB,
3406 but will ensure not to be in DATA state. */
3409 mapping_state (MAP_THUMB
);
3414 as_bad (_("width suffixes are invalid in ARM mode"));
3415 ignore_rest_of_line ();
3421 mapping_state (MAP_ARM
);
3430 if (! emit_insn (& exp
, nbytes
))
3432 ignore_rest_of_line ();
3436 while (*input_line_pointer
++ == ',');
3438 /* Put terminator back into stream. */
3439 input_line_pointer
--;
3440 demand_empty_rest_of_line ();
3443 /* Parse a .rel31 directive. */
3446 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3453 if (*input_line_pointer
== '1')
3454 highbit
= 0x80000000;
3455 else if (*input_line_pointer
!= '0')
3456 as_bad (_("expected 0 or 1"));
3458 input_line_pointer
++;
3459 if (*input_line_pointer
!= ',')
3460 as_bad (_("missing comma"));
3461 input_line_pointer
++;
3463 #ifdef md_flush_pending_output
3464 md_flush_pending_output ();
3467 #ifdef md_cons_align
3471 mapping_state (MAP_DATA
);
3476 md_number_to_chars (p
, highbit
, 4);
3477 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3478 BFD_RELOC_ARM_PREL31
);
3480 demand_empty_rest_of_line ();
3483 /* Directives: AEABI stack-unwind tables. */
3485 /* Parse an unwind_fnstart directive. Simply records the current location. */
3488 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3490 demand_empty_rest_of_line ();
3491 if (unwind
.proc_start
)
3493 as_bad (_("duplicate .fnstart directive"));
3497 /* Mark the start of the function. */
3498 unwind
.proc_start
= expr_build_dot ();
3500 /* Reset the rest of the unwind info. */
3501 unwind
.opcode_count
= 0;
3502 unwind
.table_entry
= NULL
;
3503 unwind
.personality_routine
= NULL
;
3504 unwind
.personality_index
= -1;
3505 unwind
.frame_size
= 0;
3506 unwind
.fp_offset
= 0;
3507 unwind
.fp_reg
= REG_SP
;
3509 unwind
.sp_restored
= 0;
3513 /* Parse a handlerdata directive. Creates the exception handling table entry
3514 for the function. */
3517 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3519 demand_empty_rest_of_line ();
3520 if (!unwind
.proc_start
)
3521 as_bad (MISSING_FNSTART
);
3523 if (unwind
.table_entry
)
3524 as_bad (_("duplicate .handlerdata directive"));
3526 create_unwind_entry (1);
3529 /* Parse an unwind_fnend directive. Generates the index table entry. */
3532 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3537 unsigned int marked_pr_dependency
;
3539 demand_empty_rest_of_line ();
3541 if (!unwind
.proc_start
)
3543 as_bad (_(".fnend directive without .fnstart"));
3547 /* Add eh table entry. */
3548 if (unwind
.table_entry
== NULL
)
3549 val
= create_unwind_entry (0);
3553 /* Add index table entry. This is two words. */
3554 start_unwind_section (unwind
.saved_seg
, 1);
3555 frag_align (2, 0, 0);
3556 record_alignment (now_seg
, 2);
3558 ptr
= frag_more (8);
3560 where
= frag_now_fix () - 8;
3562 /* Self relative offset of the function start. */
3563 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3564 BFD_RELOC_ARM_PREL31
);
3566 /* Indicate dependency on EHABI-defined personality routines to the
3567 linker, if it hasn't been done already. */
3568 marked_pr_dependency
3569 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3570 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3571 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3573 static const char *const name
[] =
3575 "__aeabi_unwind_cpp_pr0",
3576 "__aeabi_unwind_cpp_pr1",
3577 "__aeabi_unwind_cpp_pr2"
3579 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3580 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3581 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3582 |= 1 << unwind
.personality_index
;
3586 /* Inline exception table entry. */
3587 md_number_to_chars (ptr
+ 4, val
, 4);
3589 /* Self relative offset of the table entry. */
3590 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3591 BFD_RELOC_ARM_PREL31
);
3593 /* Restore the original section. */
3594 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3596 unwind
.proc_start
= NULL
;
3600 /* Parse an unwind_cantunwind directive. */
3603 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3605 demand_empty_rest_of_line ();
3606 if (!unwind
.proc_start
)
3607 as_bad (MISSING_FNSTART
);
3609 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3610 as_bad (_("personality routine specified for cantunwind frame"));
3612 unwind
.personality_index
= -2;
3616 /* Parse a personalityindex directive. */
3619 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3623 if (!unwind
.proc_start
)
3624 as_bad (MISSING_FNSTART
);
3626 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3627 as_bad (_("duplicate .personalityindex directive"));
3631 if (exp
.X_op
!= O_constant
3632 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3634 as_bad (_("bad personality routine number"));
3635 ignore_rest_of_line ();
3639 unwind
.personality_index
= exp
.X_add_number
;
3641 demand_empty_rest_of_line ();
3645 /* Parse a personality directive. */
3648 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3652 if (!unwind
.proc_start
)
3653 as_bad (MISSING_FNSTART
);
3655 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3656 as_bad (_("duplicate .personality directive"));
3658 name
= input_line_pointer
;
3659 c
= get_symbol_end ();
3660 p
= input_line_pointer
;
3661 unwind
.personality_routine
= symbol_find_or_make (name
);
3663 demand_empty_rest_of_line ();
3667 /* Parse a directive saving core registers. */
3670 s_arm_unwind_save_core (void)
3676 range
= parse_reg_list (&input_line_pointer
);
3679 as_bad (_("expected register list"));
3680 ignore_rest_of_line ();
3684 demand_empty_rest_of_line ();
3686 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3687 into .unwind_save {..., sp...}. We aren't bothered about the value of
3688 ip because it is clobbered by calls. */
3689 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3690 && (range
& 0x3000) == 0x1000)
3692 unwind
.opcode_count
--;
3693 unwind
.sp_restored
= 0;
3694 range
= (range
| 0x2000) & ~0x1000;
3695 unwind
.pending_offset
= 0;
3701 /* See if we can use the short opcodes. These pop a block of up to 8
3702 registers starting with r4, plus maybe r14. */
3703 for (n
= 0; n
< 8; n
++)
3705 /* Break at the first non-saved register. */
3706 if ((range
& (1 << (n
+ 4))) == 0)
3709 /* See if there are any other bits set. */
3710 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3712 /* Use the long form. */
3713 op
= 0x8000 | ((range
>> 4) & 0xfff);
3714 add_unwind_opcode (op
, 2);
3718 /* Use the short form. */
3720 op
= 0xa8; /* Pop r14. */
3722 op
= 0xa0; /* Do not pop r14. */
3724 add_unwind_opcode (op
, 1);
3731 op
= 0xb100 | (range
& 0xf);
3732 add_unwind_opcode (op
, 2);
3735 /* Record the number of bytes pushed. */
3736 for (n
= 0; n
< 16; n
++)
3738 if (range
& (1 << n
))
3739 unwind
.frame_size
+= 4;
3744 /* Parse a directive saving FPA registers. */
3747 s_arm_unwind_save_fpa (int reg
)
3753 /* Get Number of registers to transfer. */
3754 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3757 exp
.X_op
= O_illegal
;
3759 if (exp
.X_op
!= O_constant
)
3761 as_bad (_("expected , <constant>"));
3762 ignore_rest_of_line ();
3766 num_regs
= exp
.X_add_number
;
3768 if (num_regs
< 1 || num_regs
> 4)
3770 as_bad (_("number of registers must be in the range [1:4]"));
3771 ignore_rest_of_line ();
3775 demand_empty_rest_of_line ();
3780 op
= 0xb4 | (num_regs
- 1);
3781 add_unwind_opcode (op
, 1);
3786 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3787 add_unwind_opcode (op
, 2);
3789 unwind
.frame_size
+= num_regs
* 12;
3793 /* Parse a directive saving VFP registers for ARMv6 and above. */
3796 s_arm_unwind_save_vfp_armv6 (void)
3801 int num_vfpv3_regs
= 0;
3802 int num_regs_below_16
;
3804 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3807 as_bad (_("expected register list"));
3808 ignore_rest_of_line ();
3812 demand_empty_rest_of_line ();
3814 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3815 than FSTMX/FLDMX-style ones). */
3817 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3819 num_vfpv3_regs
= count
;
3820 else if (start
+ count
> 16)
3821 num_vfpv3_regs
= start
+ count
- 16;
3823 if (num_vfpv3_regs
> 0)
3825 int start_offset
= start
> 16 ? start
- 16 : 0;
3826 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3827 add_unwind_opcode (op
, 2);
3830 /* Generate opcode for registers numbered in the range 0 .. 15. */
3831 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3832 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3833 if (num_regs_below_16
> 0)
3835 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3836 add_unwind_opcode (op
, 2);
3839 unwind
.frame_size
+= count
* 8;
3843 /* Parse a directive saving VFP registers for pre-ARMv6. */
3846 s_arm_unwind_save_vfp (void)
3852 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3855 as_bad (_("expected register list"));
3856 ignore_rest_of_line ();
3860 demand_empty_rest_of_line ();
3865 op
= 0xb8 | (count
- 1);
3866 add_unwind_opcode (op
, 1);
3871 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3872 add_unwind_opcode (op
, 2);
3874 unwind
.frame_size
+= count
* 8 + 4;
3878 /* Parse a directive saving iWMMXt data registers. */
3881 s_arm_unwind_save_mmxwr (void)
3889 if (*input_line_pointer
== '{')
3890 input_line_pointer
++;
3894 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3898 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3903 as_tsktsk (_("register list not in ascending order"));
3906 if (*input_line_pointer
== '-')
3908 input_line_pointer
++;
3909 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3912 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3915 else if (reg
>= hi_reg
)
3917 as_bad (_("bad register range"));
3920 for (; reg
< hi_reg
; reg
++)
3924 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3926 if (*input_line_pointer
== '}')
3927 input_line_pointer
++;
3929 demand_empty_rest_of_line ();
3931 /* Generate any deferred opcodes because we're going to be looking at
3933 flush_pending_unwind ();
3935 for (i
= 0; i
< 16; i
++)
3937 if (mask
& (1 << i
))
3938 unwind
.frame_size
+= 8;
3941 /* Attempt to combine with a previous opcode. We do this because gcc
3942 likes to output separate unwind directives for a single block of
3944 if (unwind
.opcode_count
> 0)
3946 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3947 if ((i
& 0xf8) == 0xc0)
3950 /* Only merge if the blocks are contiguous. */
3953 if ((mask
& 0xfe00) == (1 << 9))
3955 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3956 unwind
.opcode_count
--;
3959 else if (i
== 6 && unwind
.opcode_count
>= 2)
3961 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3965 op
= 0xffff << (reg
- 1);
3967 && ((mask
& op
) == (1u << (reg
- 1))))
3969 op
= (1 << (reg
+ i
+ 1)) - 1;
3970 op
&= ~((1 << reg
) - 1);
3972 unwind
.opcode_count
-= 2;
3979 /* We want to generate opcodes in the order the registers have been
3980 saved, ie. descending order. */
3981 for (reg
= 15; reg
>= -1; reg
--)
3983 /* Save registers in blocks. */
3985 || !(mask
& (1 << reg
)))
3987 /* We found an unsaved reg. Generate opcodes to save the
3994 op
= 0xc0 | (hi_reg
- 10);
3995 add_unwind_opcode (op
, 1);
4000 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4001 add_unwind_opcode (op
, 2);
4010 ignore_rest_of_line ();
4014 s_arm_unwind_save_mmxwcg (void)
4021 if (*input_line_pointer
== '{')
4022 input_line_pointer
++;
4026 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4030 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4036 as_tsktsk (_("register list not in ascending order"));
4039 if (*input_line_pointer
== '-')
4041 input_line_pointer
++;
4042 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4045 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4048 else if (reg
>= hi_reg
)
4050 as_bad (_("bad register range"));
4053 for (; reg
< hi_reg
; reg
++)
4057 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4059 if (*input_line_pointer
== '}')
4060 input_line_pointer
++;
4062 demand_empty_rest_of_line ();
4064 /* Generate any deferred opcodes because we're going to be looking at
4066 flush_pending_unwind ();
4068 for (reg
= 0; reg
< 16; reg
++)
4070 if (mask
& (1 << reg
))
4071 unwind
.frame_size
+= 4;
4074 add_unwind_opcode (op
, 2);
4077 ignore_rest_of_line ();
4081 /* Parse an unwind_save directive.
4082 If the argument is non-zero, this is a .vsave directive. */
4085 s_arm_unwind_save (int arch_v6
)
4088 struct reg_entry
*reg
;
4089 bfd_boolean had_brace
= FALSE
;
4091 if (!unwind
.proc_start
)
4092 as_bad (MISSING_FNSTART
);
4094 /* Figure out what sort of save we have. */
4095 peek
= input_line_pointer
;
4103 reg
= arm_reg_parse_multi (&peek
);
4107 as_bad (_("register expected"));
4108 ignore_rest_of_line ();
4117 as_bad (_("FPA .unwind_save does not take a register list"));
4118 ignore_rest_of_line ();
4121 input_line_pointer
= peek
;
4122 s_arm_unwind_save_fpa (reg
->number
);
4125 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4128 s_arm_unwind_save_vfp_armv6 ();
4130 s_arm_unwind_save_vfp ();
4132 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4133 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4136 as_bad (_(".unwind_save does not support this kind of register"));
4137 ignore_rest_of_line ();
4142 /* Parse an unwind_movsp directive. */
4145 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4151 if (!unwind
.proc_start
)
4152 as_bad (MISSING_FNSTART
);
4154 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4157 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4158 ignore_rest_of_line ();
4162 /* Optional constant. */
4163 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4165 if (immediate_for_directive (&offset
) == FAIL
)
4171 demand_empty_rest_of_line ();
4173 if (reg
== REG_SP
|| reg
== REG_PC
)
4175 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4179 if (unwind
.fp_reg
!= REG_SP
)
4180 as_bad (_("unexpected .unwind_movsp directive"));
4182 /* Generate opcode to restore the value. */
4184 add_unwind_opcode (op
, 1);
4186 /* Record the information for later. */
4187 unwind
.fp_reg
= reg
;
4188 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4189 unwind
.sp_restored
= 1;
4192 /* Parse an unwind_pad directive. */
4195 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4199 if (!unwind
.proc_start
)
4200 as_bad (MISSING_FNSTART
);
4202 if (immediate_for_directive (&offset
) == FAIL
)
4207 as_bad (_("stack increment must be multiple of 4"));
4208 ignore_rest_of_line ();
4212 /* Don't generate any opcodes, just record the details for later. */
4213 unwind
.frame_size
+= offset
;
4214 unwind
.pending_offset
+= offset
;
4216 demand_empty_rest_of_line ();
4219 /* Parse an unwind_setfp directive. */
4222 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4228 if (!unwind
.proc_start
)
4229 as_bad (MISSING_FNSTART
);
4231 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4232 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4235 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4237 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4239 as_bad (_("expected <reg>, <reg>"));
4240 ignore_rest_of_line ();
4244 /* Optional constant. */
4245 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4247 if (immediate_for_directive (&offset
) == FAIL
)
4253 demand_empty_rest_of_line ();
4255 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4257 as_bad (_("register must be either sp or set by a previous"
4258 "unwind_movsp directive"));
4262 /* Don't generate any opcodes, just record the information for later. */
4263 unwind
.fp_reg
= fp_reg
;
4265 if (sp_reg
== REG_SP
)
4266 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4268 unwind
.fp_offset
-= offset
;
4271 /* Parse an unwind_raw directive. */
4274 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4277 /* This is an arbitrary limit. */
4278 unsigned char op
[16];
4281 if (!unwind
.proc_start
)
4282 as_bad (MISSING_FNSTART
);
4285 if (exp
.X_op
== O_constant
4286 && skip_past_comma (&input_line_pointer
) != FAIL
)
4288 unwind
.frame_size
+= exp
.X_add_number
;
4292 exp
.X_op
= O_illegal
;
4294 if (exp
.X_op
!= O_constant
)
4296 as_bad (_("expected <offset>, <opcode>"));
4297 ignore_rest_of_line ();
4303 /* Parse the opcode. */
4308 as_bad (_("unwind opcode too long"));
4309 ignore_rest_of_line ();
4311 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4313 as_bad (_("invalid unwind opcode"));
4314 ignore_rest_of_line ();
4317 op
[count
++] = exp
.X_add_number
;
4319 /* Parse the next byte. */
4320 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4326 /* Add the opcode bytes in reverse order. */
4328 add_unwind_opcode (op
[count
], 1);
4330 demand_empty_rest_of_line ();
4334 /* Parse a .eabi_attribute directive. */
4337 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4339 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4341 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4342 attributes_set_explicitly
[tag
] = 1;
4345 /* Emit a tls fix for the symbol. */
4348 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4352 #ifdef md_flush_pending_output
4353 md_flush_pending_output ();
4356 #ifdef md_cons_align
4360 /* Since we're just labelling the code, there's no need to define a
4363 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4364 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4365 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4366 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4368 #endif /* OBJ_ELF */
4370 static void s_arm_arch (int);
4371 static void s_arm_object_arch (int);
4372 static void s_arm_cpu (int);
4373 static void s_arm_fpu (int);
4374 static void s_arm_arch_extension (int);
4379 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4386 if (exp
.X_op
== O_symbol
)
4387 exp
.X_op
= O_secrel
;
4389 emit_expr (&exp
, 4);
4391 while (*input_line_pointer
++ == ',');
4393 input_line_pointer
--;
4394 demand_empty_rest_of_line ();
4398 /* This table describes all the machine specific pseudo-ops the assembler
4399 has to support. The fields are:
4400 pseudo-op name without dot
4401 function to call to execute this pseudo-op
4402 Integer arg to pass to the function. */
4404 const pseudo_typeS md_pseudo_table
[] =
4406 /* Never called because '.req' does not start a line. */
4407 { "req", s_req
, 0 },
4408 /* Following two are likewise never called. */
4411 { "unreq", s_unreq
, 0 },
4412 { "bss", s_bss
, 0 },
4413 { "align", s_align
, 0 },
4414 { "arm", s_arm
, 0 },
4415 { "thumb", s_thumb
, 0 },
4416 { "code", s_code
, 0 },
4417 { "force_thumb", s_force_thumb
, 0 },
4418 { "thumb_func", s_thumb_func
, 0 },
4419 { "thumb_set", s_thumb_set
, 0 },
4420 { "even", s_even
, 0 },
4421 { "ltorg", s_ltorg
, 0 },
4422 { "pool", s_ltorg
, 0 },
4423 { "syntax", s_syntax
, 0 },
4424 { "cpu", s_arm_cpu
, 0 },
4425 { "arch", s_arm_arch
, 0 },
4426 { "object_arch", s_arm_object_arch
, 0 },
4427 { "fpu", s_arm_fpu
, 0 },
4428 { "arch_extension", s_arm_arch_extension
, 0 },
4430 { "word", s_arm_elf_cons
, 4 },
4431 { "long", s_arm_elf_cons
, 4 },
4432 { "inst.n", s_arm_elf_inst
, 2 },
4433 { "inst.w", s_arm_elf_inst
, 4 },
4434 { "inst", s_arm_elf_inst
, 0 },
4435 { "rel31", s_arm_rel31
, 0 },
4436 { "fnstart", s_arm_unwind_fnstart
, 0 },
4437 { "fnend", s_arm_unwind_fnend
, 0 },
4438 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4439 { "personality", s_arm_unwind_personality
, 0 },
4440 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4441 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4442 { "save", s_arm_unwind_save
, 0 },
4443 { "vsave", s_arm_unwind_save
, 1 },
4444 { "movsp", s_arm_unwind_movsp
, 0 },
4445 { "pad", s_arm_unwind_pad
, 0 },
4446 { "setfp", s_arm_unwind_setfp
, 0 },
4447 { "unwind_raw", s_arm_unwind_raw
, 0 },
4448 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4449 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4453 /* These are used for dwarf. */
4457 /* These are used for dwarf2. */
4458 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4459 { "loc", dwarf2_directive_loc
, 0 },
4460 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4462 { "extend", float_cons
, 'x' },
4463 { "ldouble", float_cons
, 'x' },
4464 { "packed", float_cons
, 'p' },
4466 {"secrel32", pe_directive_secrel
, 0},
4471 /* Parser functions used exclusively in instruction operands. */
4473 /* Generic immediate-value read function for use in insn parsing.
4474 STR points to the beginning of the immediate (the leading #);
4475 VAL receives the value; if the value is outside [MIN, MAX]
4476 issue an error. PREFIX_OPT is true if the immediate prefix is
4480 parse_immediate (char **str
, int *val
, int min
, int max
,
4481 bfd_boolean prefix_opt
)
4484 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4485 if (exp
.X_op
!= O_constant
)
4487 inst
.error
= _("constant expression required");
4491 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4493 inst
.error
= _("immediate value out of range");
4497 *val
= exp
.X_add_number
;
4501 /* Less-generic immediate-value read function with the possibility of loading a
4502 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4503 instructions. Puts the result directly in inst.operands[i]. */
4506 parse_big_immediate (char **str
, int i
)
4511 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4513 if (exp
.X_op
== O_constant
)
4515 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4516 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4517 O_constant. We have to be careful not to break compilation for
4518 32-bit X_add_number, though. */
4519 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4521 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4522 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4523 inst
.operands
[i
].regisimm
= 1;
4526 else if (exp
.X_op
== O_big
4527 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4529 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4531 /* Bignums have their least significant bits in
4532 generic_bignum[0]. Make sure we put 32 bits in imm and
4533 32 bits in reg, in a (hopefully) portable way. */
4534 gas_assert (parts
!= 0);
4536 /* Make sure that the number is not too big.
4537 PR 11972: Bignums can now be sign-extended to the
4538 size of a .octa so check that the out of range bits
4539 are all zero or all one. */
4540 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4542 LITTLENUM_TYPE m
= -1;
4544 if (generic_bignum
[parts
* 2] != 0
4545 && generic_bignum
[parts
* 2] != m
)
4548 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4549 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4553 inst
.operands
[i
].imm
= 0;
4554 for (j
= 0; j
< parts
; j
++, idx
++)
4555 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4556 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4557 inst
.operands
[i
].reg
= 0;
4558 for (j
= 0; j
< parts
; j
++, idx
++)
4559 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4560 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4561 inst
.operands
[i
].regisimm
= 1;
4571 /* Returns the pseudo-register number of an FPA immediate constant,
4572 or FAIL if there isn't a valid constant here. */
4575 parse_fpa_immediate (char ** str
)
4577 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4583 /* First try and match exact strings, this is to guarantee
4584 that some formats will work even for cross assembly. */
4586 for (i
= 0; fp_const
[i
]; i
++)
4588 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4592 *str
+= strlen (fp_const
[i
]);
4593 if (is_end_of_line
[(unsigned char) **str
])
4599 /* Just because we didn't get a match doesn't mean that the constant
4600 isn't valid, just that it is in a format that we don't
4601 automatically recognize. Try parsing it with the standard
4602 expression routines. */
4604 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4606 /* Look for a raw floating point number. */
4607 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4608 && is_end_of_line
[(unsigned char) *save_in
])
4610 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4612 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4614 if (words
[j
] != fp_values
[i
][j
])
4618 if (j
== MAX_LITTLENUMS
)
4626 /* Try and parse a more complex expression, this will probably fail
4627 unless the code uses a floating point prefix (eg "0f"). */
4628 save_in
= input_line_pointer
;
4629 input_line_pointer
= *str
;
4630 if (expression (&exp
) == absolute_section
4631 && exp
.X_op
== O_big
4632 && exp
.X_add_number
< 0)
4634 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4636 if (gen_to_words (words
, 5, (long) 15) == 0)
4638 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4640 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4642 if (words
[j
] != fp_values
[i
][j
])
4646 if (j
== MAX_LITTLENUMS
)
4648 *str
= input_line_pointer
;
4649 input_line_pointer
= save_in
;
4656 *str
= input_line_pointer
;
4657 input_line_pointer
= save_in
;
4658 inst
.error
= _("invalid FPA immediate expression");
4662 /* Returns 1 if a number has "quarter-precision" float format
4663 0baBbbbbbc defgh000 00000000 00000000. */
4666 is_quarter_float (unsigned imm
)
4668 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4669 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4672 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4673 0baBbbbbbc defgh000 00000000 00000000.
4674 The zero and minus-zero cases need special handling, since they can't be
4675 encoded in the "quarter-precision" float format, but can nonetheless be
4676 loaded as integer constants. */
4679 parse_qfloat_immediate (char **ccp
, int *immed
)
4683 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4684 int found_fpchar
= 0;
4686 skip_past_char (&str
, '#');
4688 /* We must not accidentally parse an integer as a floating-point number. Make
4689 sure that the value we parse is not an integer by checking for special
4690 characters '.' or 'e'.
4691 FIXME: This is a horrible hack, but doing better is tricky because type
4692 information isn't in a very usable state at parse time. */
4694 skip_whitespace (fpnum
);
4696 if (strncmp (fpnum
, "0x", 2) == 0)
4700 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4701 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4711 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4713 unsigned fpword
= 0;
4716 /* Our FP word must be 32 bits (single-precision FP). */
4717 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4719 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4723 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4736 /* Shift operands. */
4739 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4742 struct asm_shift_name
4745 enum shift_kind kind
;
4748 /* Third argument to parse_shift. */
4749 enum parse_shift_mode
4751 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4752 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4753 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4754 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4755 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4758 /* Parse a <shift> specifier on an ARM data processing instruction.
4759 This has three forms:
4761 (LSL|LSR|ASL|ASR|ROR) Rs
4762 (LSL|LSR|ASL|ASR|ROR) #imm
4765 Note that ASL is assimilated to LSL in the instruction encoding, and
4766 RRX to ROR #0 (which cannot be written as such). */
4769 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4771 const struct asm_shift_name
*shift_name
;
4772 enum shift_kind shift
;
4777 for (p
= *str
; ISALPHA (*p
); p
++)
4782 inst
.error
= _("shift expression expected");
4786 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4789 if (shift_name
== NULL
)
4791 inst
.error
= _("shift expression expected");
4795 shift
= shift_name
->kind
;
4799 case NO_SHIFT_RESTRICT
:
4800 case SHIFT_IMMEDIATE
: break;
4802 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4803 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4805 inst
.error
= _("'LSL' or 'ASR' required");
4810 case SHIFT_LSL_IMMEDIATE
:
4811 if (shift
!= SHIFT_LSL
)
4813 inst
.error
= _("'LSL' required");
4818 case SHIFT_ASR_IMMEDIATE
:
4819 if (shift
!= SHIFT_ASR
)
4821 inst
.error
= _("'ASR' required");
4829 if (shift
!= SHIFT_RRX
)
4831 /* Whitespace can appear here if the next thing is a bare digit. */
4832 skip_whitespace (p
);
4834 if (mode
== NO_SHIFT_RESTRICT
4835 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4837 inst
.operands
[i
].imm
= reg
;
4838 inst
.operands
[i
].immisreg
= 1;
4840 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4843 inst
.operands
[i
].shift_kind
= shift
;
4844 inst
.operands
[i
].shifted
= 1;
4849 /* Parse a <shifter_operand> for an ARM data processing instruction:
4852 #<immediate>, <rotate>
4856 where <shift> is defined by parse_shift above, and <rotate> is a
4857 multiple of 2 between 0 and 30. Validation of immediate operands
4858 is deferred to md_apply_fix. */
4861 parse_shifter_operand (char **str
, int i
)
4866 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4868 inst
.operands
[i
].reg
= value
;
4869 inst
.operands
[i
].isreg
= 1;
4871 /* parse_shift will override this if appropriate */
4872 inst
.reloc
.exp
.X_op
= O_constant
;
4873 inst
.reloc
.exp
.X_add_number
= 0;
4875 if (skip_past_comma (str
) == FAIL
)
4878 /* Shift operation on register. */
4879 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4882 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4885 if (skip_past_comma (str
) == SUCCESS
)
4887 /* #x, y -- ie explicit rotation by Y. */
4888 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4891 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4893 inst
.error
= _("constant expression expected");
4897 value
= exp
.X_add_number
;
4898 if (value
< 0 || value
> 30 || value
% 2 != 0)
4900 inst
.error
= _("invalid rotation");
4903 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4905 inst
.error
= _("invalid constant");
4909 /* Encode as specified. */
4910 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
4914 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4915 inst
.reloc
.pc_rel
= 0;
4919 /* Group relocation information. Each entry in the table contains the
4920 textual name of the relocation as may appear in assembler source
4921 and must end with a colon.
4922 Along with this textual name are the relocation codes to be used if
4923 the corresponding instruction is an ALU instruction (ADD or SUB only),
4924 an LDR, an LDRS, or an LDC. */
4926 struct group_reloc_table_entry
4937 /* Varieties of non-ALU group relocation. */
4944 static struct group_reloc_table_entry group_reloc_table
[] =
4945 { /* Program counter relative: */
4947 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4952 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4953 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4954 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4955 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4957 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4962 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4963 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4964 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4965 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4967 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4968 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4969 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4970 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4971 /* Section base relative */
4973 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4978 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4979 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4980 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4981 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4983 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4988 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4989 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4990 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4991 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4993 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4994 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4995 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4996 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4998 /* Given the address of a pointer pointing to the textual name of a group
4999 relocation as may appear in assembler source, attempt to find its details
5000 in group_reloc_table. The pointer will be updated to the character after
5001 the trailing colon. On failure, FAIL will be returned; SUCCESS
5002 otherwise. On success, *entry will be updated to point at the relevant
5003 group_reloc_table entry. */
5006 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5009 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5011 int length
= strlen (group_reloc_table
[i
].name
);
5013 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5014 && (*str
)[length
] == ':')
5016 *out
= &group_reloc_table
[i
];
5017 *str
+= (length
+ 1);
5025 /* Parse a <shifter_operand> for an ARM data processing instruction
5026 (as for parse_shifter_operand) where group relocations are allowed:
5029 #<immediate>, <rotate>
5030 #:<group_reloc>:<expression>
5034 where <group_reloc> is one of the strings defined in group_reloc_table.
5035 The hashes are optional.
5037 Everything else is as for parse_shifter_operand. */
5039 static parse_operand_result
5040 parse_shifter_operand_group_reloc (char **str
, int i
)
5042 /* Determine if we have the sequence of characters #: or just :
5043 coming next. If we do, then we check for a group relocation.
5044 If we don't, punt the whole lot to parse_shifter_operand. */
5046 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5047 || (*str
)[0] == ':')
5049 struct group_reloc_table_entry
*entry
;
5051 if ((*str
)[0] == '#')
5056 /* Try to parse a group relocation. Anything else is an error. */
5057 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5059 inst
.error
= _("unknown group relocation");
5060 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5063 /* We now have the group relocation table entry corresponding to
5064 the name in the assembler source. Next, we parse the expression. */
5065 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5066 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5068 /* Record the relocation type (always the ALU variant here). */
5069 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5070 gas_assert (inst
.reloc
.type
!= 0);
5072 return PARSE_OPERAND_SUCCESS
;
5075 return parse_shifter_operand (str
, i
) == SUCCESS
5076 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5078 /* Never reached. */
5081 /* Parse a Neon alignment expression. Information is written to
5082 inst.operands[i]. We assume the initial ':' has been skipped.
5084 align .imm = align << 8, .immisalign=1, .preind=0 */
5085 static parse_operand_result
5086 parse_neon_alignment (char **str
, int i
)
5091 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5093 if (exp
.X_op
!= O_constant
)
5095 inst
.error
= _("alignment must be constant");
5096 return PARSE_OPERAND_FAIL
;
5099 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5100 inst
.operands
[i
].immisalign
= 1;
5101 /* Alignments are not pre-indexes. */
5102 inst
.operands
[i
].preind
= 0;
5105 return PARSE_OPERAND_SUCCESS
;
5108 /* Parse all forms of an ARM address expression. Information is written
5109 to inst.operands[i] and/or inst.reloc.
5111 Preindexed addressing (.preind=1):
5113 [Rn, #offset] .reg=Rn .reloc.exp=offset
5114 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5115 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5116 .shift_kind=shift .reloc.exp=shift_imm
5118 These three may have a trailing ! which causes .writeback to be set also.
5120 Postindexed addressing (.postind=1, .writeback=1):
5122 [Rn], #offset .reg=Rn .reloc.exp=offset
5123 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 Unindexed addressing (.preind=0, .postind=0):
5129 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5133 [Rn]{!} shorthand for [Rn,#0]{!}
5134 =immediate .isreg=0 .reloc.exp=immediate
5135 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5137 It is the caller's responsibility to check for addressing modes not
5138 supported by the instruction, and to set inst.reloc.type. */
5140 static parse_operand_result
5141 parse_address_main (char **str
, int i
, int group_relocations
,
5142 group_reloc_type group_type
)
5147 if (skip_past_char (&p
, '[') == FAIL
)
5149 if (skip_past_char (&p
, '=') == FAIL
)
5151 /* Bare address - translate to PC-relative offset. */
5152 inst
.reloc
.pc_rel
= 1;
5153 inst
.operands
[i
].reg
= REG_PC
;
5154 inst
.operands
[i
].isreg
= 1;
5155 inst
.operands
[i
].preind
= 1;
5157 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5159 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5160 return PARSE_OPERAND_FAIL
;
5163 return PARSE_OPERAND_SUCCESS
;
5166 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5168 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5169 return PARSE_OPERAND_FAIL
;
5171 inst
.operands
[i
].reg
= reg
;
5172 inst
.operands
[i
].isreg
= 1;
5174 if (skip_past_comma (&p
) == SUCCESS
)
5176 inst
.operands
[i
].preind
= 1;
5179 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5181 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5183 inst
.operands
[i
].imm
= reg
;
5184 inst
.operands
[i
].immisreg
= 1;
5186 if (skip_past_comma (&p
) == SUCCESS
)
5187 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5188 return PARSE_OPERAND_FAIL
;
5190 else if (skip_past_char (&p
, ':') == SUCCESS
)
5192 /* FIXME: '@' should be used here, but it's filtered out by generic
5193 code before we get to see it here. This may be subject to
5195 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5197 if (result
!= PARSE_OPERAND_SUCCESS
)
5202 if (inst
.operands
[i
].negative
)
5204 inst
.operands
[i
].negative
= 0;
5208 if (group_relocations
5209 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5211 struct group_reloc_table_entry
*entry
;
5213 /* Skip over the #: or : sequence. */
5219 /* Try to parse a group relocation. Anything else is an
5221 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5223 inst
.error
= _("unknown group relocation");
5224 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5227 /* We now have the group relocation table entry corresponding to
5228 the name in the assembler source. Next, we parse the
5230 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5231 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5233 /* Record the relocation type. */
5237 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5241 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5245 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5252 if (inst
.reloc
.type
== 0)
5254 inst
.error
= _("this group relocation is not allowed on this instruction");
5255 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5261 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5262 return PARSE_OPERAND_FAIL
;
5263 /* If the offset is 0, find out if it's a +0 or -0. */
5264 if (inst
.reloc
.exp
.X_op
== O_constant
5265 && inst
.reloc
.exp
.X_add_number
== 0)
5267 skip_whitespace (q
);
5271 skip_whitespace (q
);
5274 inst
.operands
[i
].negative
= 1;
5279 else if (skip_past_char (&p
, ':') == SUCCESS
)
5281 /* FIXME: '@' should be used here, but it's filtered out by generic code
5282 before we get to see it here. This may be subject to change. */
5283 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5285 if (result
!= PARSE_OPERAND_SUCCESS
)
5289 if (skip_past_char (&p
, ']') == FAIL
)
5291 inst
.error
= _("']' expected");
5292 return PARSE_OPERAND_FAIL
;
5295 if (skip_past_char (&p
, '!') == SUCCESS
)
5296 inst
.operands
[i
].writeback
= 1;
5298 else if (skip_past_comma (&p
) == SUCCESS
)
5300 if (skip_past_char (&p
, '{') == SUCCESS
)
5302 /* [Rn], {expr} - unindexed, with option */
5303 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5304 0, 255, TRUE
) == FAIL
)
5305 return PARSE_OPERAND_FAIL
;
5307 if (skip_past_char (&p
, '}') == FAIL
)
5309 inst
.error
= _("'}' expected at end of 'option' field");
5310 return PARSE_OPERAND_FAIL
;
5312 if (inst
.operands
[i
].preind
)
5314 inst
.error
= _("cannot combine index with option");
5315 return PARSE_OPERAND_FAIL
;
5318 return PARSE_OPERAND_SUCCESS
;
5322 inst
.operands
[i
].postind
= 1;
5323 inst
.operands
[i
].writeback
= 1;
5325 if (inst
.operands
[i
].preind
)
5327 inst
.error
= _("cannot combine pre- and post-indexing");
5328 return PARSE_OPERAND_FAIL
;
5332 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5334 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5336 /* We might be using the immediate for alignment already. If we
5337 are, OR the register number into the low-order bits. */
5338 if (inst
.operands
[i
].immisalign
)
5339 inst
.operands
[i
].imm
|= reg
;
5341 inst
.operands
[i
].imm
= reg
;
5342 inst
.operands
[i
].immisreg
= 1;
5344 if (skip_past_comma (&p
) == SUCCESS
)
5345 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5346 return PARSE_OPERAND_FAIL
;
5351 if (inst
.operands
[i
].negative
)
5353 inst
.operands
[i
].negative
= 0;
5356 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5357 return PARSE_OPERAND_FAIL
;
5358 /* If the offset is 0, find out if it's a +0 or -0. */
5359 if (inst
.reloc
.exp
.X_op
== O_constant
5360 && inst
.reloc
.exp
.X_add_number
== 0)
5362 skip_whitespace (q
);
5366 skip_whitespace (q
);
5369 inst
.operands
[i
].negative
= 1;
5375 /* If at this point neither .preind nor .postind is set, we have a
5376 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5377 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5379 inst
.operands
[i
].preind
= 1;
5380 inst
.reloc
.exp
.X_op
= O_constant
;
5381 inst
.reloc
.exp
.X_add_number
= 0;
5384 return PARSE_OPERAND_SUCCESS
;
5388 parse_address (char **str
, int i
)
5390 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5394 static parse_operand_result
5395 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5397 return parse_address_main (str
, i
, 1, type
);
5400 /* Parse an operand for a MOVW or MOVT instruction. */
5402 parse_half (char **str
)
5407 skip_past_char (&p
, '#');
5408 if (strncasecmp (p
, ":lower16:", 9) == 0)
5409 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5410 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5411 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5413 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5416 skip_whitespace (p
);
5419 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5422 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5424 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5426 inst
.error
= _("constant expression expected");
5429 if (inst
.reloc
.exp
.X_add_number
< 0
5430 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5432 inst
.error
= _("immediate value out of range");
5440 /* Miscellaneous. */
5442 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5443 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5445 parse_psr (char **str
, bfd_boolean lhs
)
5448 unsigned long psr_field
;
5449 const struct asm_psr
*psr
;
5451 bfd_boolean is_apsr
= FALSE
;
5452 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5454 /* PR gas/12698: If the user has specified -march=all then m_profile will
5455 be TRUE, but we want to ignore it in this case as we are building for any
5456 CPU type, including non-m variants. */
5457 if (selected_cpu
.core
== arm_arch_any
.core
)
5460 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5461 feature for ease of use and backwards compatibility. */
5463 if (strncasecmp (p
, "SPSR", 4) == 0)
5466 goto unsupported_psr
;
5468 psr_field
= SPSR_BIT
;
5470 else if (strncasecmp (p
, "CPSR", 4) == 0)
5473 goto unsupported_psr
;
5477 else if (strncasecmp (p
, "APSR", 4) == 0)
5479 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5480 and ARMv7-R architecture CPUs. */
5489 while (ISALNUM (*p
) || *p
== '_');
5491 if (strncasecmp (start
, "iapsr", 5) == 0
5492 || strncasecmp (start
, "eapsr", 5) == 0
5493 || strncasecmp (start
, "xpsr", 4) == 0
5494 || strncasecmp (start
, "psr", 3) == 0)
5495 p
= start
+ strcspn (start
, "rR") + 1;
5497 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5503 /* If APSR is being written, a bitfield may be specified. Note that
5504 APSR itself is handled above. */
5505 if (psr
->field
<= 3)
5507 psr_field
= psr
->field
;
5513 /* M-profile MSR instructions have the mask field set to "10", except
5514 *PSR variants which modify APSR, which may use a different mask (and
5515 have been handled already). Do that by setting the PSR_f field
5517 return psr
->field
| (lhs
? PSR_f
: 0);
5520 goto unsupported_psr
;
5526 /* A suffix follows. */
5532 while (ISALNUM (*p
) || *p
== '_');
5536 /* APSR uses a notation for bits, rather than fields. */
5537 unsigned int nzcvq_bits
= 0;
5538 unsigned int g_bit
= 0;
5541 for (bit
= start
; bit
!= p
; bit
++)
5543 switch (TOLOWER (*bit
))
5546 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5550 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5554 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5558 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5562 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5566 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5570 inst
.error
= _("unexpected bit specified after APSR");
5575 if (nzcvq_bits
== 0x1f)
5580 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5582 inst
.error
= _("selected processor does not "
5583 "support DSP extension");
5590 if ((nzcvq_bits
& 0x20) != 0
5591 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5592 || (g_bit
& 0x2) != 0)
5594 inst
.error
= _("bad bitmask specified after APSR");
5600 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5605 psr_field
|= psr
->field
;
5611 goto error
; /* Garbage after "[CS]PSR". */
5613 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5614 is deprecated, but allow it anyway. */
5618 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5621 else if (!m_profile
)
5622 /* These bits are never right for M-profile devices: don't set them
5623 (only code paths which read/write APSR reach here). */
5624 psr_field
|= (PSR_c
| PSR_f
);
5630 inst
.error
= _("selected processor does not support requested special "
5631 "purpose register");
5635 inst
.error
= _("flag for {c}psr instruction expected");
5639 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5640 value suitable for splatting into the AIF field of the instruction. */
5643 parse_cps_flags (char **str
)
5652 case '\0': case ',':
5655 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5656 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5657 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5660 inst
.error
= _("unrecognized CPS flag");
5665 if (saw_a_flag
== 0)
5667 inst
.error
= _("missing CPS flags");
5675 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5676 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5679 parse_endian_specifier (char **str
)
5684 if (strncasecmp (s
, "BE", 2))
5686 else if (strncasecmp (s
, "LE", 2))
5690 inst
.error
= _("valid endian specifiers are be or le");
5694 if (ISALNUM (s
[2]) || s
[2] == '_')
5696 inst
.error
= _("valid endian specifiers are be or le");
5701 return little_endian
;
5704 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5705 value suitable for poking into the rotate field of an sxt or sxta
5706 instruction, or FAIL on error. */
5709 parse_ror (char **str
)
5714 if (strncasecmp (s
, "ROR", 3) == 0)
5718 inst
.error
= _("missing rotation field after comma");
5722 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5727 case 0: *str
= s
; return 0x0;
5728 case 8: *str
= s
; return 0x1;
5729 case 16: *str
= s
; return 0x2;
5730 case 24: *str
= s
; return 0x3;
5733 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5738 /* Parse a conditional code (from conds[] below). The value returned is in the
5739 range 0 .. 14, or FAIL. */
5741 parse_cond (char **str
)
5744 const struct asm_cond
*c
;
5746 /* Condition codes are always 2 characters, so matching up to
5747 3 characters is sufficient. */
5752 while (ISALPHA (*q
) && n
< 3)
5754 cond
[n
] = TOLOWER (*q
);
5759 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5762 inst
.error
= _("condition required");
5770 /* If the given feature available in the selected CPU, mark it as used.
5771 Returns TRUE iff feature is available. */
5773 mark_feature_used (const arm_feature_set
*feature
)
5775 /* Ensure the option is valid on the current architecture. */
5776 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
5779 /* Add the appropriate architecture feature for the barrier option used.
5782 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
5784 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
5789 /* Parse an option for a barrier instruction. Returns the encoding for the
5792 parse_barrier (char **str
)
5795 const struct asm_barrier_opt
*o
;
5798 while (ISALPHA (*q
))
5801 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5806 if (!mark_feature_used (&o
->arch
))
5813 /* Parse the operands of a table branch instruction. Similar to a memory
5816 parse_tb (char **str
)
5821 if (skip_past_char (&p
, '[') == FAIL
)
5823 inst
.error
= _("'[' expected");
5827 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5829 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5832 inst
.operands
[0].reg
= reg
;
5834 if (skip_past_comma (&p
) == FAIL
)
5836 inst
.error
= _("',' expected");
5840 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5842 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5845 inst
.operands
[0].imm
= reg
;
5847 if (skip_past_comma (&p
) == SUCCESS
)
5849 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5851 if (inst
.reloc
.exp
.X_add_number
!= 1)
5853 inst
.error
= _("invalid shift");
5856 inst
.operands
[0].shifted
= 1;
5859 if (skip_past_char (&p
, ']') == FAIL
)
5861 inst
.error
= _("']' expected");
5868 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5869 information on the types the operands can take and how they are encoded.
5870 Up to four operands may be read; this function handles setting the
5871 ".present" field for each read operand itself.
5872 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5873 else returns FAIL. */
5876 parse_neon_mov (char **str
, int *which_operand
)
5878 int i
= *which_operand
, val
;
5879 enum arm_reg_type rtype
;
5881 struct neon_type_el optype
;
5883 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5885 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5886 inst
.operands
[i
].reg
= val
;
5887 inst
.operands
[i
].isscalar
= 1;
5888 inst
.operands
[i
].vectype
= optype
;
5889 inst
.operands
[i
++].present
= 1;
5891 if (skip_past_comma (&ptr
) == FAIL
)
5894 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5897 inst
.operands
[i
].reg
= val
;
5898 inst
.operands
[i
].isreg
= 1;
5899 inst
.operands
[i
].present
= 1;
5901 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5904 /* Cases 0, 1, 2, 3, 5 (D only). */
5905 if (skip_past_comma (&ptr
) == FAIL
)
5908 inst
.operands
[i
].reg
= val
;
5909 inst
.operands
[i
].isreg
= 1;
5910 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5911 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5912 inst
.operands
[i
].isvec
= 1;
5913 inst
.operands
[i
].vectype
= optype
;
5914 inst
.operands
[i
++].present
= 1;
5916 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5918 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5919 Case 13: VMOV <Sd>, <Rm> */
5920 inst
.operands
[i
].reg
= val
;
5921 inst
.operands
[i
].isreg
= 1;
5922 inst
.operands
[i
].present
= 1;
5924 if (rtype
== REG_TYPE_NQ
)
5926 first_error (_("can't use Neon quad register here"));
5929 else if (rtype
!= REG_TYPE_VFS
)
5932 if (skip_past_comma (&ptr
) == FAIL
)
5934 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5936 inst
.operands
[i
].reg
= val
;
5937 inst
.operands
[i
].isreg
= 1;
5938 inst
.operands
[i
].present
= 1;
5941 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5944 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5945 Case 1: VMOV<c><q> <Dd>, <Dm>
5946 Case 8: VMOV.F32 <Sd>, <Sm>
5947 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5949 inst
.operands
[i
].reg
= val
;
5950 inst
.operands
[i
].isreg
= 1;
5951 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5952 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5953 inst
.operands
[i
].isvec
= 1;
5954 inst
.operands
[i
].vectype
= optype
;
5955 inst
.operands
[i
].present
= 1;
5957 if (skip_past_comma (&ptr
) == SUCCESS
)
5962 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5965 inst
.operands
[i
].reg
= val
;
5966 inst
.operands
[i
].isreg
= 1;
5967 inst
.operands
[i
++].present
= 1;
5969 if (skip_past_comma (&ptr
) == FAIL
)
5972 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5975 inst
.operands
[i
].reg
= val
;
5976 inst
.operands
[i
].isreg
= 1;
5977 inst
.operands
[i
].present
= 1;
5980 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5981 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5982 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5983 Case 10: VMOV.F32 <Sd>, #<imm>
5984 Case 11: VMOV.F64 <Dd>, #<imm> */
5985 inst
.operands
[i
].immisfloat
= 1;
5986 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5987 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5988 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5992 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5996 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5999 inst
.operands
[i
].reg
= val
;
6000 inst
.operands
[i
].isreg
= 1;
6001 inst
.operands
[i
++].present
= 1;
6003 if (skip_past_comma (&ptr
) == FAIL
)
6006 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6008 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6009 inst
.operands
[i
].reg
= val
;
6010 inst
.operands
[i
].isscalar
= 1;
6011 inst
.operands
[i
].present
= 1;
6012 inst
.operands
[i
].vectype
= optype
;
6014 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6016 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6017 inst
.operands
[i
].reg
= val
;
6018 inst
.operands
[i
].isreg
= 1;
6019 inst
.operands
[i
++].present
= 1;
6021 if (skip_past_comma (&ptr
) == FAIL
)
6024 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6027 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6031 inst
.operands
[i
].reg
= val
;
6032 inst
.operands
[i
].isreg
= 1;
6033 inst
.operands
[i
].isvec
= 1;
6034 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6035 inst
.operands
[i
].vectype
= optype
;
6036 inst
.operands
[i
].present
= 1;
6038 if (rtype
== REG_TYPE_VFS
)
6042 if (skip_past_comma (&ptr
) == FAIL
)
6044 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6047 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6050 inst
.operands
[i
].reg
= val
;
6051 inst
.operands
[i
].isreg
= 1;
6052 inst
.operands
[i
].isvec
= 1;
6053 inst
.operands
[i
].issingle
= 1;
6054 inst
.operands
[i
].vectype
= optype
;
6055 inst
.operands
[i
].present
= 1;
6058 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6062 inst
.operands
[i
].reg
= val
;
6063 inst
.operands
[i
].isreg
= 1;
6064 inst
.operands
[i
].isvec
= 1;
6065 inst
.operands
[i
].issingle
= 1;
6066 inst
.operands
[i
].vectype
= optype
;
6067 inst
.operands
[i
].present
= 1;
6072 first_error (_("parse error"));
6076 /* Successfully parsed the operands. Update args. */
6082 first_error (_("expected comma"));
6086 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6090 /* Use this macro when the operand constraints are different
6091 for ARM and THUMB (e.g. ldrd). */
6092 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6093 ((arm_operand) | ((thumb_operand) << 16))
6095 /* Matcher codes for parse_operands. */
6096 enum operand_parse_code
6098 OP_stop
, /* end of line */
6100 OP_RR
, /* ARM register */
6101 OP_RRnpc
, /* ARM register, not r15 */
6102 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6103 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6104 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6105 optional trailing ! */
6106 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6107 OP_RCP
, /* Coprocessor number */
6108 OP_RCN
, /* Coprocessor register */
6109 OP_RF
, /* FPA register */
6110 OP_RVS
, /* VFP single precision register */
6111 OP_RVD
, /* VFP double precision register (0..15) */
6112 OP_RND
, /* Neon double precision register (0..31) */
6113 OP_RNQ
, /* Neon quad precision register */
6114 OP_RVSD
, /* VFP single or double precision register */
6115 OP_RNDQ
, /* Neon double or quad precision register */
6116 OP_RNSDQ
, /* Neon single, double or quad precision register */
6117 OP_RNSC
, /* Neon scalar D[X] */
6118 OP_RVC
, /* VFP control register */
6119 OP_RMF
, /* Maverick F register */
6120 OP_RMD
, /* Maverick D register */
6121 OP_RMFX
, /* Maverick FX register */
6122 OP_RMDX
, /* Maverick DX register */
6123 OP_RMAX
, /* Maverick AX register */
6124 OP_RMDS
, /* Maverick DSPSC register */
6125 OP_RIWR
, /* iWMMXt wR register */
6126 OP_RIWC
, /* iWMMXt wC register */
6127 OP_RIWG
, /* iWMMXt wCG register */
6128 OP_RXA
, /* XScale accumulator register */
6130 OP_REGLST
, /* ARM register list */
6131 OP_VRSLST
, /* VFP single-precision register list */
6132 OP_VRDLST
, /* VFP double-precision register list */
6133 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6134 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6135 OP_NSTRLST
, /* Neon element/structure list */
6137 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6138 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6139 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6140 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6141 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6142 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6143 OP_VMOV
, /* Neon VMOV operands. */
6144 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6145 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6146 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6148 OP_I0
, /* immediate zero */
6149 OP_I7
, /* immediate value 0 .. 7 */
6150 OP_I15
, /* 0 .. 15 */
6151 OP_I16
, /* 1 .. 16 */
6152 OP_I16z
, /* 0 .. 16 */
6153 OP_I31
, /* 0 .. 31 */
6154 OP_I31w
, /* 0 .. 31, optional trailing ! */
6155 OP_I32
, /* 1 .. 32 */
6156 OP_I32z
, /* 0 .. 32 */
6157 OP_I63
, /* 0 .. 63 */
6158 OP_I63s
, /* -64 .. 63 */
6159 OP_I64
, /* 1 .. 64 */
6160 OP_I64z
, /* 0 .. 64 */
6161 OP_I255
, /* 0 .. 255 */
6163 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6164 OP_I7b
, /* 0 .. 7 */
6165 OP_I15b
, /* 0 .. 15 */
6166 OP_I31b
, /* 0 .. 31 */
6168 OP_SH
, /* shifter operand */
6169 OP_SHG
, /* shifter operand with possible group relocation */
6170 OP_ADDR
, /* Memory address expression (any mode) */
6171 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6172 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6173 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6174 OP_EXP
, /* arbitrary expression */
6175 OP_EXPi
, /* same, with optional immediate prefix */
6176 OP_EXPr
, /* same, with optional relocation suffix */
6177 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6179 OP_CPSF
, /* CPS flags */
6180 OP_ENDI
, /* Endianness specifier */
6181 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6182 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6183 OP_COND
, /* conditional code */
6184 OP_TB
, /* Table branch. */
6186 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6188 OP_RRnpc_I0
, /* ARM register or literal 0 */
6189 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6190 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6191 OP_RF_IF
, /* FPA register or immediate */
6192 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6193 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6195 /* Optional operands. */
6196 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6197 OP_oI31b
, /* 0 .. 31 */
6198 OP_oI32b
, /* 1 .. 32 */
6199 OP_oI32z
, /* 0 .. 32 */
6200 OP_oIffffb
, /* 0 .. 65535 */
6201 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6203 OP_oRR
, /* ARM register */
6204 OP_oRRnpc
, /* ARM register, not the PC */
6205 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6206 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6207 OP_oRND
, /* Optional Neon double precision register */
6208 OP_oRNQ
, /* Optional Neon quad precision register */
6209 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6210 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6211 OP_oSHll
, /* LSL immediate */
6212 OP_oSHar
, /* ASR immediate */
6213 OP_oSHllar
, /* LSL or ASR immediate */
6214 OP_oROR
, /* ROR 0/8/16/24 */
6215 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6217 /* Some pre-defined mixed (ARM/THUMB) operands. */
6218 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6219 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6220 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6222 OP_FIRST_OPTIONAL
= OP_oI7b
6225 /* Generic instruction operand parser. This does no encoding and no
6226 semantic validation; it merely squirrels values away in the inst
6227 structure. Returns SUCCESS or FAIL depending on whether the
6228 specified grammar matched. */
6230 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6232 unsigned const int *upat
= pattern
;
6233 char *backtrack_pos
= 0;
6234 const char *backtrack_error
= 0;
6235 int i
, val
= 0, backtrack_index
= 0;
6236 enum arm_reg_type rtype
;
6237 parse_operand_result result
;
6238 unsigned int op_parse_code
;
6240 #define po_char_or_fail(chr) \
6243 if (skip_past_char (&str, chr) == FAIL) \
6248 #define po_reg_or_fail(regtype) \
6251 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6252 & inst.operands[i].vectype); \
6255 first_error (_(reg_expected_msgs[regtype])); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isreg = 1; \
6260 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6261 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6262 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6263 || rtype == REG_TYPE_VFD \
6264 || rtype == REG_TYPE_NQ); \
6268 #define po_reg_or_goto(regtype, label) \
6271 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6272 & inst.operands[i].vectype); \
6276 inst.operands[i].reg = val; \
6277 inst.operands[i].isreg = 1; \
6278 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6279 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6280 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6281 || rtype == REG_TYPE_VFD \
6282 || rtype == REG_TYPE_NQ); \
6286 #define po_imm_or_fail(min, max, popt) \
6289 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6291 inst.operands[i].imm = val; \
6295 #define po_scalar_or_goto(elsz, label) \
6298 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6301 inst.operands[i].reg = val; \
6302 inst.operands[i].isscalar = 1; \
6306 #define po_misc_or_fail(expr) \
6314 #define po_misc_or_fail_no_backtrack(expr) \
6318 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6319 backtrack_pos = 0; \
6320 if (result != PARSE_OPERAND_SUCCESS) \
6325 #define po_barrier_or_imm(str) \
6328 val = parse_barrier (&str); \
6331 if (ISALPHA (*str)) \
6338 if ((inst.instruction & 0xf0) == 0x60 \
6341 /* ISB can only take SY as an option. */ \
6342 inst.error = _("invalid barrier type"); \
6349 skip_whitespace (str
);
6351 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6353 op_parse_code
= upat
[i
];
6354 if (op_parse_code
>= 1<<16)
6355 op_parse_code
= thumb
? (op_parse_code
>> 16)
6356 : (op_parse_code
& ((1<<16)-1));
6358 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6360 /* Remember where we are in case we need to backtrack. */
6361 gas_assert (!backtrack_pos
);
6362 backtrack_pos
= str
;
6363 backtrack_error
= inst
.error
;
6364 backtrack_index
= i
;
6367 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6368 po_char_or_fail (',');
6370 switch (op_parse_code
)
6378 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6379 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6380 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6381 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6382 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6383 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6385 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6387 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6389 /* Also accept generic coprocessor regs for unknown registers. */
6391 po_reg_or_fail (REG_TYPE_CN
);
6393 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6394 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6395 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6396 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6397 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6398 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6399 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6400 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6401 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6402 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6404 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6406 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6407 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6409 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6411 /* Neon scalar. Using an element size of 8 means that some invalid
6412 scalars are accepted here, so deal with those in later code. */
6413 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6417 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6420 po_imm_or_fail (0, 0, TRUE
);
6425 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6430 po_scalar_or_goto (8, try_rr
);
6433 po_reg_or_fail (REG_TYPE_RN
);
6439 po_scalar_or_goto (8, try_nsdq
);
6442 po_reg_or_fail (REG_TYPE_NSDQ
);
6448 po_scalar_or_goto (8, try_ndq
);
6451 po_reg_or_fail (REG_TYPE_NDQ
);
6457 po_scalar_or_goto (8, try_vfd
);
6460 po_reg_or_fail (REG_TYPE_VFD
);
6465 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6466 not careful then bad things might happen. */
6467 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6472 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6475 /* There's a possibility of getting a 64-bit immediate here, so
6476 we need special handling. */
6477 if (parse_big_immediate (&str
, i
) == FAIL
)
6479 inst
.error
= _("immediate value is out of range");
6487 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6490 po_imm_or_fail (0, 63, TRUE
);
6495 po_char_or_fail ('[');
6496 po_reg_or_fail (REG_TYPE_RN
);
6497 po_char_or_fail (']');
6503 po_reg_or_fail (REG_TYPE_RN
);
6504 if (skip_past_char (&str
, '!') == SUCCESS
)
6505 inst
.operands
[i
].writeback
= 1;
6509 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6510 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6511 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6512 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6513 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6514 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6515 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6516 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6517 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6518 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6519 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6520 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6522 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6524 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6525 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6527 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6528 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6529 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6530 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6532 /* Immediate variants */
6534 po_char_or_fail ('{');
6535 po_imm_or_fail (0, 255, TRUE
);
6536 po_char_or_fail ('}');
6540 /* The expression parser chokes on a trailing !, so we have
6541 to find it first and zap it. */
6544 while (*s
&& *s
!= ',')
6549 inst
.operands
[i
].writeback
= 1;
6551 po_imm_or_fail (0, 31, TRUE
);
6559 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6564 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6569 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6571 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6573 val
= parse_reloc (&str
);
6576 inst
.error
= _("unrecognized relocation suffix");
6579 else if (val
!= BFD_RELOC_UNUSED
)
6581 inst
.operands
[i
].imm
= val
;
6582 inst
.operands
[i
].hasreloc
= 1;
6587 /* Operand for MOVW or MOVT. */
6589 po_misc_or_fail (parse_half (&str
));
6592 /* Register or expression. */
6593 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6594 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6596 /* Register or immediate. */
6597 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6598 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6600 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6602 if (!is_immediate_prefix (*str
))
6605 val
= parse_fpa_immediate (&str
);
6608 /* FPA immediates are encoded as registers 8-15.
6609 parse_fpa_immediate has already applied the offset. */
6610 inst
.operands
[i
].reg
= val
;
6611 inst
.operands
[i
].isreg
= 1;
6614 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6615 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6617 /* Two kinds of register. */
6620 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6622 || (rege
->type
!= REG_TYPE_MMXWR
6623 && rege
->type
!= REG_TYPE_MMXWC
6624 && rege
->type
!= REG_TYPE_MMXWCG
))
6626 inst
.error
= _("iWMMXt data or control register expected");
6629 inst
.operands
[i
].reg
= rege
->number
;
6630 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6636 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6638 || (rege
->type
!= REG_TYPE_MMXWC
6639 && rege
->type
!= REG_TYPE_MMXWCG
))
6641 inst
.error
= _("iWMMXt control register expected");
6644 inst
.operands
[i
].reg
= rege
->number
;
6645 inst
.operands
[i
].isreg
= 1;
6650 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6651 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6652 case OP_oROR
: val
= parse_ror (&str
); break;
6653 case OP_COND
: val
= parse_cond (&str
); break;
6654 case OP_oBARRIER_I15
:
6655 po_barrier_or_imm (str
); break;
6657 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6663 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6664 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6666 inst
.error
= _("Banked registers are not available with this "
6672 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6676 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6679 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6681 if (strncasecmp (str
, "APSR_", 5) == 0)
6688 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6689 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6690 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6691 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6692 default: found
= 16;
6696 inst
.operands
[i
].isvec
= 1;
6697 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6698 inst
.operands
[i
].reg
= REG_PC
;
6705 po_misc_or_fail (parse_tb (&str
));
6708 /* Register lists. */
6710 val
= parse_reg_list (&str
);
6713 inst
.operands
[1].writeback
= 1;
6719 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6723 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6727 /* Allow Q registers too. */
6728 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6733 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6735 inst
.operands
[i
].issingle
= 1;
6740 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6745 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6746 &inst
.operands
[i
].vectype
);
6749 /* Addressing modes */
6751 po_misc_or_fail (parse_address (&str
, i
));
6755 po_misc_or_fail_no_backtrack (
6756 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6760 po_misc_or_fail_no_backtrack (
6761 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6765 po_misc_or_fail_no_backtrack (
6766 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6770 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6774 po_misc_or_fail_no_backtrack (
6775 parse_shifter_operand_group_reloc (&str
, i
));
6779 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6783 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6787 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6791 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6794 /* Various value-based sanity checks and shared operations. We
6795 do not signal immediate failures for the register constraints;
6796 this allows a syntax error to take precedence. */
6797 switch (op_parse_code
)
6805 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6806 inst
.error
= BAD_PC
;
6811 if (inst
.operands
[i
].isreg
)
6813 if (inst
.operands
[i
].reg
== REG_PC
)
6814 inst
.error
= BAD_PC
;
6815 else if (inst
.operands
[i
].reg
== REG_SP
)
6816 inst
.error
= BAD_SP
;
6821 if (inst
.operands
[i
].isreg
6822 && inst
.operands
[i
].reg
== REG_PC
6823 && (inst
.operands
[i
].writeback
|| thumb
))
6824 inst
.error
= BAD_PC
;
6833 case OP_oBARRIER_I15
:
6842 inst
.operands
[i
].imm
= val
;
6849 /* If we get here, this operand was successfully parsed. */
6850 inst
.operands
[i
].present
= 1;
6854 inst
.error
= BAD_ARGS
;
6859 /* The parse routine should already have set inst.error, but set a
6860 default here just in case. */
6862 inst
.error
= _("syntax error");
6866 /* Do not backtrack over a trailing optional argument that
6867 absorbed some text. We will only fail again, with the
6868 'garbage following instruction' error message, which is
6869 probably less helpful than the current one. */
6870 if (backtrack_index
== i
&& backtrack_pos
!= str
6871 && upat
[i
+1] == OP_stop
)
6874 inst
.error
= _("syntax error");
6878 /* Try again, skipping the optional argument at backtrack_pos. */
6879 str
= backtrack_pos
;
6880 inst
.error
= backtrack_error
;
6881 inst
.operands
[backtrack_index
].present
= 0;
6882 i
= backtrack_index
;
6886 /* Check that we have parsed all the arguments. */
6887 if (*str
!= '\0' && !inst
.error
)
6888 inst
.error
= _("garbage following instruction");
6890 return inst
.error
? FAIL
: SUCCESS
;
6893 #undef po_char_or_fail
6894 #undef po_reg_or_fail
6895 #undef po_reg_or_goto
6896 #undef po_imm_or_fail
6897 #undef po_scalar_or_fail
6898 #undef po_barrier_or_imm
6900 /* Shorthand macro for instruction encoding functions issuing errors. */
6901 #define constraint(expr, err) \
6912 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6913 instructions are unpredictable if these registers are used. This
6914 is the BadReg predicate in ARM's Thumb-2 documentation. */
6915 #define reject_bad_reg(reg) \
6917 if (reg == REG_SP || reg == REG_PC) \
6919 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6924 /* If REG is R13 (the stack pointer), warn that its use is
6926 #define warn_deprecated_sp(reg) \
6928 if (warn_on_deprecated && reg == REG_SP) \
6929 as_warn (_("use of r13 is deprecated")); \
6932 /* Functions for operand encoding. ARM, then Thumb. */
6934 #define rotate_left(v, n) (v << n | v >> (32 - n))
6936 /* If VAL can be encoded in the immediate field of an ARM instruction,
6937 return the encoded form. Otherwise, return FAIL. */
6940 encode_arm_immediate (unsigned int val
)
6944 for (i
= 0; i
< 32; i
+= 2)
6945 if ((a
= rotate_left (val
, i
)) <= 0xff)
6946 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6951 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6952 return the encoded form. Otherwise, return FAIL. */
6954 encode_thumb32_immediate (unsigned int val
)
6961 for (i
= 1; i
<= 24; i
++)
6964 if ((val
& ~(0xff << i
)) == 0)
6965 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6969 if (val
== ((a
<< 16) | a
))
6971 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6975 if (val
== ((a
<< 16) | a
))
6976 return 0x200 | (a
>> 8);
6980 /* Encode a VFP SP or DP register number into inst.instruction. */
6983 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6985 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6988 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6991 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6994 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6999 first_error (_("D register out of range for selected VFP version"));
7007 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7011 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7015 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7019 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7023 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7027 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7035 /* Encode a <shift> in an ARM-format instruction. The immediate,
7036 if any, is handled by md_apply_fix. */
7038 encode_arm_shift (int i
)
7040 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7041 inst
.instruction
|= SHIFT_ROR
<< 5;
7044 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7045 if (inst
.operands
[i
].immisreg
)
7047 inst
.instruction
|= SHIFT_BY_REG
;
7048 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7051 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7056 encode_arm_shifter_operand (int i
)
7058 if (inst
.operands
[i
].isreg
)
7060 inst
.instruction
|= inst
.operands
[i
].reg
;
7061 encode_arm_shift (i
);
7065 inst
.instruction
|= INST_IMMEDIATE
;
7066 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7067 inst
.instruction
|= inst
.operands
[i
].imm
;
7071 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7073 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7076 Generate an error if the operand is not a register. */
7077 constraint (!inst
.operands
[i
].isreg
,
7078 _("Instruction does not support =N addresses"));
7080 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7082 if (inst
.operands
[i
].preind
)
7086 inst
.error
= _("instruction does not accept preindexed addressing");
7089 inst
.instruction
|= PRE_INDEX
;
7090 if (inst
.operands
[i
].writeback
)
7091 inst
.instruction
|= WRITE_BACK
;
7094 else if (inst
.operands
[i
].postind
)
7096 gas_assert (inst
.operands
[i
].writeback
);
7098 inst
.instruction
|= WRITE_BACK
;
7100 else /* unindexed - only for coprocessor */
7102 inst
.error
= _("instruction does not accept unindexed addressing");
7106 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7107 && (((inst
.instruction
& 0x000f0000) >> 16)
7108 == ((inst
.instruction
& 0x0000f000) >> 12)))
7109 as_warn ((inst
.instruction
& LOAD_BIT
)
7110 ? _("destination register same as write-back base")
7111 : _("source register same as write-back base"));
7114 /* inst.operands[i] was set up by parse_address. Encode it into an
7115 ARM-format mode 2 load or store instruction. If is_t is true,
7116 reject forms that cannot be used with a T instruction (i.e. not
7119 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7121 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7123 encode_arm_addr_mode_common (i
, is_t
);
7125 if (inst
.operands
[i
].immisreg
)
7127 constraint ((inst
.operands
[i
].imm
== REG_PC
7128 || (is_pc
&& inst
.operands
[i
].writeback
)),
7130 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7131 inst
.instruction
|= inst
.operands
[i
].imm
;
7132 if (!inst
.operands
[i
].negative
)
7133 inst
.instruction
|= INDEX_UP
;
7134 if (inst
.operands
[i
].shifted
)
7136 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7137 inst
.instruction
|= SHIFT_ROR
<< 5;
7140 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7141 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7145 else /* immediate offset in inst.reloc */
7147 if (is_pc
&& !inst
.reloc
.pc_rel
)
7149 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7151 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7152 cannot use PC in addressing.
7153 PC cannot be used in writeback addressing, either. */
7154 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7157 /* Use of PC in str is deprecated for ARMv7. */
7158 if (warn_on_deprecated
7160 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7161 as_warn (_("use of PC in this instruction is deprecated"));
7164 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7166 /* Prefer + for zero encoded value. */
7167 if (!inst
.operands
[i
].negative
)
7168 inst
.instruction
|= INDEX_UP
;
7169 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7174 /* inst.operands[i] was set up by parse_address. Encode it into an
7175 ARM-format mode 3 load or store instruction. Reject forms that
7176 cannot be used with such instructions. If is_t is true, reject
7177 forms that cannot be used with a T instruction (i.e. not
7180 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7182 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7184 inst
.error
= _("instruction does not accept scaled register index");
7188 encode_arm_addr_mode_common (i
, is_t
);
7190 if (inst
.operands
[i
].immisreg
)
7192 constraint ((inst
.operands
[i
].imm
== REG_PC
7193 || inst
.operands
[i
].reg
== REG_PC
),
7195 inst
.instruction
|= inst
.operands
[i
].imm
;
7196 if (!inst
.operands
[i
].negative
)
7197 inst
.instruction
|= INDEX_UP
;
7199 else /* immediate offset in inst.reloc */
7201 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7202 && inst
.operands
[i
].writeback
),
7204 inst
.instruction
|= HWOFFSET_IMM
;
7205 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7207 /* Prefer + for zero encoded value. */
7208 if (!inst
.operands
[i
].negative
)
7209 inst
.instruction
|= INDEX_UP
;
7211 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7216 /* inst.operands[i] was set up by parse_address. Encode it into an
7217 ARM-format instruction. Reject all forms which cannot be encoded
7218 into a coprocessor load/store instruction. If wb_ok is false,
7219 reject use of writeback; if unind_ok is false, reject use of
7220 unindexed addressing. If reloc_override is not 0, use it instead
7221 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7222 (in which case it is preserved). */
7225 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7227 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7229 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7231 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7233 gas_assert (!inst
.operands
[i
].writeback
);
7236 inst
.error
= _("instruction does not support unindexed addressing");
7239 inst
.instruction
|= inst
.operands
[i
].imm
;
7240 inst
.instruction
|= INDEX_UP
;
7244 if (inst
.operands
[i
].preind
)
7245 inst
.instruction
|= PRE_INDEX
;
7247 if (inst
.operands
[i
].writeback
)
7249 if (inst
.operands
[i
].reg
== REG_PC
)
7251 inst
.error
= _("pc may not be used with write-back");
7256 inst
.error
= _("instruction does not support writeback");
7259 inst
.instruction
|= WRITE_BACK
;
7263 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7264 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7265 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7266 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7269 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7271 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7274 /* Prefer + for zero encoded value. */
7275 if (!inst
.operands
[i
].negative
)
7276 inst
.instruction
|= INDEX_UP
;
7281 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7282 Determine whether it can be performed with a move instruction; if
7283 it can, convert inst.instruction to that move instruction and
7284 return TRUE; if it can't, convert inst.instruction to a literal-pool
7285 load and return FALSE. If this is not a valid thing to do in the
7286 current context, set inst.error and return TRUE.
7288 inst.operands[i] describes the destination register. */
7291 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7296 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7300 if ((inst
.instruction
& tbit
) == 0)
7302 inst
.error
= _("invalid pseudo operation");
7305 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7307 inst
.error
= _("constant expression expected");
7310 if (inst
.reloc
.exp
.X_op
== O_constant
)
7314 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7316 /* This can be done with a mov(1) instruction. */
7317 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7318 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7324 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7327 /* This can be done with a mov instruction. */
7328 inst
.instruction
&= LITERAL_MASK
;
7329 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7330 inst
.instruction
|= value
& 0xfff;
7334 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7337 /* This can be done with a mvn instruction. */
7338 inst
.instruction
&= LITERAL_MASK
;
7339 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7340 inst
.instruction
|= value
& 0xfff;
7346 if (add_to_lit_pool () == FAIL
)
7348 inst
.error
= _("literal pool insertion failed");
7351 inst
.operands
[1].reg
= REG_PC
;
7352 inst
.operands
[1].isreg
= 1;
7353 inst
.operands
[1].preind
= 1;
7354 inst
.reloc
.pc_rel
= 1;
7355 inst
.reloc
.type
= (thumb_p
7356 ? BFD_RELOC_ARM_THUMB_OFFSET
7358 ? BFD_RELOC_ARM_HWLITERAL
7359 : BFD_RELOC_ARM_LITERAL
));
7363 /* Functions for instruction encoding, sorted by sub-architecture.
7364 First some generics; their names are taken from the conventional
7365 bit positions for register arguments in ARM format instructions. */
7375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7381 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7382 inst
.instruction
|= inst
.operands
[1].reg
;
7388 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7389 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7395 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7396 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7400 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7402 if (ARM_CPU_IS_ANY (cpu_variant
))
7404 as_warn ("%s", msg
);
7407 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
7419 unsigned Rn
= inst
.operands
[2].reg
;
7420 /* Enforce restrictions on SWP instruction. */
7421 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7423 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7424 _("Rn must not overlap other operands"));
7426 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7428 if (!check_obsolete (&arm_ext_v8
,
7429 _("swp{b} use is obsoleted for ARMv8 and later"))
7430 && warn_on_deprecated
7431 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
7432 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7436 inst
.instruction
|= inst
.operands
[1].reg
;
7437 inst
.instruction
|= Rn
<< 16;
7443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7444 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7445 inst
.instruction
|= inst
.operands
[2].reg
;
7451 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7452 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7453 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7454 || inst
.reloc
.exp
.X_add_number
!= 0),
7456 inst
.instruction
|= inst
.operands
[0].reg
;
7457 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7458 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7464 inst
.instruction
|= inst
.operands
[0].imm
;
7470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7471 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7474 /* ARM instructions, in alphabetical order by function name (except
7475 that wrapper functions appear immediately after the function they
7478 /* This is a pseudo-op of the form "adr rd, label" to be converted
7479 into a relative address of the form "add rd, pc, #label-.-8". */
7484 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7486 /* Frag hacking will turn this into a sub instruction if the offset turns
7487 out to be negative. */
7488 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7489 inst
.reloc
.pc_rel
= 1;
7490 inst
.reloc
.exp
.X_add_number
-= 8;
7493 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7494 into a relative address of the form:
7495 add rd, pc, #low(label-.-8)"
7496 add rd, rd, #high(label-.-8)" */
7501 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7503 /* Frag hacking will turn this into a sub instruction if the offset turns
7504 out to be negative. */
7505 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7506 inst
.reloc
.pc_rel
= 1;
7507 inst
.size
= INSN_SIZE
* 2;
7508 inst
.reloc
.exp
.X_add_number
-= 8;
7514 if (!inst
.operands
[1].present
)
7515 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7517 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7518 encode_arm_shifter_operand (2);
7524 if (inst
.operands
[0].present
)
7526 constraint ((inst
.instruction
& 0xf0) != 0x40
7527 && inst
.operands
[0].imm
> 0xf
7528 && inst
.operands
[0].imm
< 0x0,
7529 _("bad barrier type"));
7530 inst
.instruction
|= inst
.operands
[0].imm
;
7533 inst
.instruction
|= 0xf;
7539 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7540 constraint (msb
> 32, _("bit-field extends past end of register"));
7541 /* The instruction encoding stores the LSB and MSB,
7542 not the LSB and width. */
7543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7544 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7545 inst
.instruction
|= (msb
- 1) << 16;
7553 /* #0 in second position is alternative syntax for bfc, which is
7554 the same instruction but with REG_PC in the Rm field. */
7555 if (!inst
.operands
[1].isreg
)
7556 inst
.operands
[1].reg
= REG_PC
;
7558 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7559 constraint (msb
> 32, _("bit-field extends past end of register"));
7560 /* The instruction encoding stores the LSB and MSB,
7561 not the LSB and width. */
7562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7563 inst
.instruction
|= inst
.operands
[1].reg
;
7564 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7565 inst
.instruction
|= (msb
- 1) << 16;
7571 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7572 _("bit-field extends past end of register"));
7573 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7574 inst
.instruction
|= inst
.operands
[1].reg
;
7575 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7576 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7579 /* ARM V5 breakpoint instruction (argument parse)
7580 BKPT <16 bit unsigned immediate>
7581 Instruction is not conditional.
7582 The bit pattern given in insns[] has the COND_ALWAYS condition,
7583 and it is an error if the caller tried to override that. */
7588 /* Top 12 of 16 bits to bits 19:8. */
7589 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7591 /* Bottom 4 of 16 bits to bits 3:0. */
7592 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7596 encode_branch (int default_reloc
)
7598 if (inst
.operands
[0].hasreloc
)
7600 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7601 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7602 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7603 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7604 ? BFD_RELOC_ARM_PLT32
7605 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7608 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7609 inst
.reloc
.pc_rel
= 1;
7616 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7617 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7620 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7627 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7629 if (inst
.cond
== COND_ALWAYS
)
7630 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7632 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7636 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7639 /* ARM V5 branch-link-exchange instruction (argument parse)
7640 BLX <target_addr> ie BLX(1)
7641 BLX{<condition>} <Rm> ie BLX(2)
7642 Unfortunately, there are two different opcodes for this mnemonic.
7643 So, the insns[].value is not used, and the code here zaps values
7644 into inst.instruction.
7645 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7650 if (inst
.operands
[0].isreg
)
7652 /* Arg is a register; the opcode provided by insns[] is correct.
7653 It is not illegal to do "blx pc", just useless. */
7654 if (inst
.operands
[0].reg
== REG_PC
)
7655 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7657 inst
.instruction
|= inst
.operands
[0].reg
;
7661 /* Arg is an address; this instruction cannot be executed
7662 conditionally, and the opcode must be adjusted.
7663 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7664 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7665 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7666 inst
.instruction
= 0xfa000000;
7667 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7674 bfd_boolean want_reloc
;
7676 if (inst
.operands
[0].reg
== REG_PC
)
7677 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7679 inst
.instruction
|= inst
.operands
[0].reg
;
7680 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7681 it is for ARMv4t or earlier. */
7682 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7683 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7687 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7692 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7696 /* ARM v5TEJ. Jump to Jazelle code. */
7701 if (inst
.operands
[0].reg
== REG_PC
)
7702 as_tsktsk (_("use of r15 in bxj is not really useful"));
7704 inst
.instruction
|= inst
.operands
[0].reg
;
7707 /* Co-processor data operation:
7708 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7709 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7713 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7714 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7715 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7716 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7717 inst
.instruction
|= inst
.operands
[4].reg
;
7718 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7724 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7725 encode_arm_shifter_operand (1);
7728 /* Transfer between coprocessor and ARM registers.
7729 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7734 No special properties. */
7736 struct deprecated_coproc_regs_s
7743 arm_feature_set deprecated
;
7744 arm_feature_set obsoleted
;
7745 const char *dep_msg
;
7746 const char *obs_msg
;
7749 #define DEPR_ACCESS_V8 \
7750 N_("This coprocessor register access is deprecated in ARMv8")
7752 /* Table of all deprecated coprocessor registers. */
7753 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
7755 {15, 0, 7, 10, 5, /* CP15DMB. */
7756 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7757 DEPR_ACCESS_V8
, NULL
},
7758 {15, 0, 7, 10, 4, /* CP15DSB. */
7759 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7760 DEPR_ACCESS_V8
, NULL
},
7761 {15, 0, 7, 5, 4, /* CP15ISB. */
7762 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7763 DEPR_ACCESS_V8
, NULL
},
7764 {14, 6, 1, 0, 0, /* TEEHBR. */
7765 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7766 DEPR_ACCESS_V8
, NULL
},
7767 {14, 6, 0, 0, 0, /* TEECR. */
7768 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7769 DEPR_ACCESS_V8
, NULL
},
7772 #undef DEPR_ACCESS_V8
7774 static const size_t deprecated_coproc_reg_count
=
7775 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
7783 Rd
= inst
.operands
[2].reg
;
7786 if (inst
.instruction
== 0xee000010
7787 || inst
.instruction
== 0xfe000010)
7789 reject_bad_reg (Rd
);
7792 constraint (Rd
== REG_SP
, BAD_SP
);
7797 if (inst
.instruction
== 0xe000010)
7798 constraint (Rd
== REG_PC
, BAD_PC
);
7801 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
7803 const struct deprecated_coproc_regs_s
*r
=
7804 deprecated_coproc_regs
+ i
;
7806 if (inst
.operands
[0].reg
== r
->cp
7807 && inst
.operands
[1].imm
== r
->opc1
7808 && inst
.operands
[3].reg
== r
->crn
7809 && inst
.operands
[4].reg
== r
->crm
7810 && inst
.operands
[5].imm
== r
->opc2
)
7812 if (!check_obsolete (&r
->obsoleted
, r
->obs_msg
)
7813 && warn_on_deprecated
7814 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
7815 as_warn ("%s", r
->dep_msg
);
7819 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7820 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7821 inst
.instruction
|= Rd
<< 12;
7822 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7823 inst
.instruction
|= inst
.operands
[4].reg
;
7824 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7827 /* Transfer between coprocessor register and pair of ARM registers.
7828 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7833 Two XScale instructions are special cases of these:
7835 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7836 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7838 Result unpredictable if Rd or Rn is R15. */
7845 Rd
= inst
.operands
[2].reg
;
7846 Rn
= inst
.operands
[3].reg
;
7850 reject_bad_reg (Rd
);
7851 reject_bad_reg (Rn
);
7855 constraint (Rd
== REG_PC
, BAD_PC
);
7856 constraint (Rn
== REG_PC
, BAD_PC
);
7859 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7860 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7861 inst
.instruction
|= Rd
<< 12;
7862 inst
.instruction
|= Rn
<< 16;
7863 inst
.instruction
|= inst
.operands
[4].reg
;
7869 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7870 if (inst
.operands
[1].present
)
7872 inst
.instruction
|= CPSI_MMOD
;
7873 inst
.instruction
|= inst
.operands
[1].imm
;
7880 inst
.instruction
|= inst
.operands
[0].imm
;
7886 unsigned Rd
, Rn
, Rm
;
7888 Rd
= inst
.operands
[0].reg
;
7889 Rn
= (inst
.operands
[1].present
7890 ? inst
.operands
[1].reg
: Rd
);
7891 Rm
= inst
.operands
[2].reg
;
7893 constraint ((Rd
== REG_PC
), BAD_PC
);
7894 constraint ((Rn
== REG_PC
), BAD_PC
);
7895 constraint ((Rm
== REG_PC
), BAD_PC
);
7897 inst
.instruction
|= Rd
<< 16;
7898 inst
.instruction
|= Rn
<< 0;
7899 inst
.instruction
|= Rm
<< 8;
7905 /* There is no IT instruction in ARM mode. We
7906 process it to do the validation as if in
7907 thumb mode, just in case the code gets
7908 assembled for thumb using the unified syntax. */
7913 set_it_insn_type (IT_INSN
);
7914 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7915 now_it
.cc
= inst
.operands
[0].imm
;
7919 /* If there is only one register in the register list,
7920 then return its register number. Otherwise return -1. */
7922 only_one_reg_in_list (int range
)
7924 int i
= ffs (range
) - 1;
7925 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
7929 encode_ldmstm(int from_push_pop_mnem
)
7931 int base_reg
= inst
.operands
[0].reg
;
7932 int range
= inst
.operands
[1].imm
;
7935 inst
.instruction
|= base_reg
<< 16;
7936 inst
.instruction
|= range
;
7938 if (inst
.operands
[1].writeback
)
7939 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7941 if (inst
.operands
[0].writeback
)
7943 inst
.instruction
|= WRITE_BACK
;
7944 /* Check for unpredictable uses of writeback. */
7945 if (inst
.instruction
& LOAD_BIT
)
7947 /* Not allowed in LDM type 2. */
7948 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7949 && ((range
& (1 << REG_PC
)) == 0))
7950 as_warn (_("writeback of base register is UNPREDICTABLE"));
7951 /* Only allowed if base reg not in list for other types. */
7952 else if (range
& (1 << base_reg
))
7953 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7957 /* Not allowed for type 2. */
7958 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7959 as_warn (_("writeback of base register is UNPREDICTABLE"));
7960 /* Only allowed if base reg not in list, or first in list. */
7961 else if ((range
& (1 << base_reg
))
7962 && (range
& ((1 << base_reg
) - 1)))
7963 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7967 /* If PUSH/POP has only one register, then use the A2 encoding. */
7968 one_reg
= only_one_reg_in_list (range
);
7969 if (from_push_pop_mnem
&& one_reg
>= 0)
7971 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
7973 inst
.instruction
&= A_COND_MASK
;
7974 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
7975 inst
.instruction
|= one_reg
<< 12;
7982 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
7985 /* ARMv5TE load-consecutive (argument parse)
7994 constraint (inst
.operands
[0].reg
% 2 != 0,
7995 _("first transfer register must be even"));
7996 constraint (inst
.operands
[1].present
7997 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7998 _("can only transfer two consecutive registers"));
7999 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8000 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8002 if (!inst
.operands
[1].present
)
8003 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8005 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8006 register and the first register written; we have to diagnose
8007 overlap between the base and the second register written here. */
8009 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8010 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8011 as_warn (_("base register written back, and overlaps "
8012 "second transfer register"));
8014 if (!(inst
.instruction
& V4_STR_BIT
))
8016 /* For an index-register load, the index register must not overlap the
8017 destination (even if not write-back). */
8018 if (inst
.operands
[2].immisreg
8019 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8020 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8021 as_warn (_("index register overlaps transfer register"));
8023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8024 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8030 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8031 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8032 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8033 || inst
.operands
[1].negative
8034 /* This can arise if the programmer has written
8036 or if they have mistakenly used a register name as the last
8039 It is very difficult to distinguish between these two cases
8040 because "rX" might actually be a label. ie the register
8041 name has been occluded by a symbol of the same name. So we
8042 just generate a general 'bad addressing mode' type error
8043 message and leave it up to the programmer to discover the
8044 true cause and fix their mistake. */
8045 || (inst
.operands
[1].reg
== REG_PC
),
8048 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8049 || inst
.reloc
.exp
.X_add_number
!= 0,
8050 _("offset must be zero in ARM encoding"));
8052 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8055 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8056 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8062 constraint (inst
.operands
[0].reg
% 2 != 0,
8063 _("even register required"));
8064 constraint (inst
.operands
[1].present
8065 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8066 _("can only load two consecutive registers"));
8067 /* If op 1 were present and equal to PC, this function wouldn't
8068 have been called in the first place. */
8069 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8071 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8072 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8075 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8076 which is not a multiple of four is UNPREDICTABLE. */
8078 check_ldr_r15_aligned (void)
8080 constraint (!(inst
.operands
[1].immisreg
)
8081 && (inst
.operands
[0].reg
== REG_PC
8082 && inst
.operands
[1].reg
== REG_PC
8083 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8084 _("ldr to register 15 must be 4-byte alligned"));
8090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8091 if (!inst
.operands
[1].isreg
)
8092 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
8094 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8095 check_ldr_r15_aligned ();
8101 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8103 if (inst
.operands
[1].preind
)
8105 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8106 || inst
.reloc
.exp
.X_add_number
!= 0,
8107 _("this instruction requires a post-indexed address"));
8109 inst
.operands
[1].preind
= 0;
8110 inst
.operands
[1].postind
= 1;
8111 inst
.operands
[1].writeback
= 1;
8113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8114 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8117 /* Halfword and signed-byte load/store operations. */
8122 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8124 if (!inst
.operands
[1].isreg
)
8125 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
8127 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8133 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8135 if (inst
.operands
[1].preind
)
8137 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8138 || inst
.reloc
.exp
.X_add_number
!= 0,
8139 _("this instruction requires a post-indexed address"));
8141 inst
.operands
[1].preind
= 0;
8142 inst
.operands
[1].postind
= 1;
8143 inst
.operands
[1].writeback
= 1;
8145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8146 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8149 /* Co-processor register load/store.
8150 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8154 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8155 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8156 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8162 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8163 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8164 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8165 && !(inst
.instruction
& 0x00400000))
8166 as_tsktsk (_("Rd and Rm should be different in mla"));
8168 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8169 inst
.instruction
|= inst
.operands
[1].reg
;
8170 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8171 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8178 encode_arm_shifter_operand (1);
8181 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8188 top
= (inst
.instruction
& 0x00400000) != 0;
8189 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8190 _(":lower16: not allowed this instruction"));
8191 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8192 _(":upper16: not allowed instruction"));
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8194 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8196 imm
= inst
.reloc
.exp
.X_add_number
;
8197 /* The value is in two pieces: 0:11, 16:19. */
8198 inst
.instruction
|= (imm
& 0x00000fff);
8199 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8203 static void do_vfp_nsyn_opcode (const char *);
8206 do_vfp_nsyn_mrs (void)
8208 if (inst
.operands
[0].isvec
)
8210 if (inst
.operands
[1].reg
!= 1)
8211 first_error (_("operand 1 must be FPSCR"));
8212 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8213 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8214 do_vfp_nsyn_opcode ("fmstat");
8216 else if (inst
.operands
[1].isvec
)
8217 do_vfp_nsyn_opcode ("fmrx");
8225 do_vfp_nsyn_msr (void)
8227 if (inst
.operands
[0].isvec
)
8228 do_vfp_nsyn_opcode ("fmxr");
8238 unsigned Rt
= inst
.operands
[0].reg
;
8240 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8242 inst
.error
= BAD_SP
;
8246 /* APSR_ sets isvec. All other refs to PC are illegal. */
8247 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8249 inst
.error
= BAD_PC
;
8253 switch (inst
.operands
[1].reg
)
8260 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8263 first_error (_("operand 1 must be a VFP extension System Register"));
8266 inst
.instruction
|= (Rt
<< 12);
8272 unsigned Rt
= inst
.operands
[1].reg
;
8275 reject_bad_reg (Rt
);
8276 else if (Rt
== REG_PC
)
8278 inst
.error
= BAD_PC
;
8282 switch (inst
.operands
[0].reg
)
8287 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8290 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8293 inst
.instruction
|= (Rt
<< 12);
8301 if (do_vfp_nsyn_mrs () == SUCCESS
)
8304 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8307 if (inst
.operands
[1].isreg
)
8309 br
= inst
.operands
[1].reg
;
8310 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8311 as_bad (_("bad register for mrs"));
8315 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8316 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8318 _("'APSR', 'CPSR' or 'SPSR' expected"));
8319 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8322 inst
.instruction
|= br
;
8325 /* Two possible forms:
8326 "{C|S}PSR_<field>, Rm",
8327 "{C|S}PSR_f, #expression". */
8332 if (do_vfp_nsyn_msr () == SUCCESS
)
8335 inst
.instruction
|= inst
.operands
[0].imm
;
8336 if (inst
.operands
[1].isreg
)
8337 inst
.instruction
|= inst
.operands
[1].reg
;
8340 inst
.instruction
|= INST_IMMEDIATE
;
8341 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8342 inst
.reloc
.pc_rel
= 0;
8349 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8351 if (!inst
.operands
[2].present
)
8352 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8353 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8354 inst
.instruction
|= inst
.operands
[1].reg
;
8355 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8357 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8358 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8359 as_tsktsk (_("Rd and Rm should be different in mul"));
8362 /* Long Multiply Parser
8363 UMULL RdLo, RdHi, Rm, Rs
8364 SMULL RdLo, RdHi, Rm, Rs
8365 UMLAL RdLo, RdHi, Rm, Rs
8366 SMLAL RdLo, RdHi, Rm, Rs. */
8371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8372 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8373 inst
.instruction
|= inst
.operands
[2].reg
;
8374 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8376 /* rdhi and rdlo must be different. */
8377 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8378 as_tsktsk (_("rdhi and rdlo must be different"));
8380 /* rdhi, rdlo and rm must all be different before armv6. */
8381 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8382 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8383 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8384 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8390 if (inst
.operands
[0].present
8391 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8393 /* Architectural NOP hints are CPSR sets with no bits selected. */
8394 inst
.instruction
&= 0xf0000000;
8395 inst
.instruction
|= 0x0320f000;
8396 if (inst
.operands
[0].present
)
8397 inst
.instruction
|= inst
.operands
[0].imm
;
8401 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8402 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8403 Condition defaults to COND_ALWAYS.
8404 Error if Rd, Rn or Rm are R15. */
8409 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8410 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8411 inst
.instruction
|= inst
.operands
[2].reg
;
8412 if (inst
.operands
[3].present
)
8413 encode_arm_shift (3);
8416 /* ARM V6 PKHTB (Argument Parse). */
8421 if (!inst
.operands
[3].present
)
8423 /* If the shift specifier is omitted, turn the instruction
8424 into pkhbt rd, rm, rn. */
8425 inst
.instruction
&= 0xfff00010;
8426 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8427 inst
.instruction
|= inst
.operands
[1].reg
;
8428 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8432 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8433 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8434 inst
.instruction
|= inst
.operands
[2].reg
;
8435 encode_arm_shift (3);
8439 /* ARMv5TE: Preload-Cache
8440 MP Extensions: Preload for write
8444 Syntactically, like LDR with B=1, W=0, L=1. */
8449 constraint (!inst
.operands
[0].isreg
,
8450 _("'[' expected after PLD mnemonic"));
8451 constraint (inst
.operands
[0].postind
,
8452 _("post-indexed expression used in preload instruction"));
8453 constraint (inst
.operands
[0].writeback
,
8454 _("writeback used in preload instruction"));
8455 constraint (!inst
.operands
[0].preind
,
8456 _("unindexed addressing used in preload instruction"));
8457 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8460 /* ARMv7: PLI <addr_mode> */
8464 constraint (!inst
.operands
[0].isreg
,
8465 _("'[' expected after PLI mnemonic"));
8466 constraint (inst
.operands
[0].postind
,
8467 _("post-indexed expression used in preload instruction"));
8468 constraint (inst
.operands
[0].writeback
,
8469 _("writeback used in preload instruction"));
8470 constraint (!inst
.operands
[0].preind
,
8471 _("unindexed addressing used in preload instruction"));
8472 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8473 inst
.instruction
&= ~PRE_INDEX
;
8479 inst
.operands
[1] = inst
.operands
[0];
8480 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8481 inst
.operands
[0].isreg
= 1;
8482 inst
.operands
[0].writeback
= 1;
8483 inst
.operands
[0].reg
= REG_SP
;
8484 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
8487 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8488 word at the specified address and the following word
8490 Unconditionally executed.
8491 Error if Rn is R15. */
8496 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8497 if (inst
.operands
[0].writeback
)
8498 inst
.instruction
|= WRITE_BACK
;
8501 /* ARM V6 ssat (argument parse). */
8506 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8507 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8508 inst
.instruction
|= inst
.operands
[2].reg
;
8510 if (inst
.operands
[3].present
)
8511 encode_arm_shift (3);
8514 /* ARM V6 usat (argument parse). */
8519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8520 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8521 inst
.instruction
|= inst
.operands
[2].reg
;
8523 if (inst
.operands
[3].present
)
8524 encode_arm_shift (3);
8527 /* ARM V6 ssat16 (argument parse). */
8532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8533 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8534 inst
.instruction
|= inst
.operands
[2].reg
;
8540 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8541 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8542 inst
.instruction
|= inst
.operands
[2].reg
;
8545 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8546 preserving the other bits.
8548 setend <endian_specifier>, where <endian_specifier> is either
8554 if (warn_on_deprecated
8555 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8556 as_warn (_("setend use is deprecated for ARMv8"));
8558 if (inst
.operands
[0].imm
)
8559 inst
.instruction
|= 0x200;
8565 unsigned int Rm
= (inst
.operands
[1].present
8566 ? inst
.operands
[1].reg
8567 : inst
.operands
[0].reg
);
8569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8570 inst
.instruction
|= Rm
;
8571 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8573 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8574 inst
.instruction
|= SHIFT_BY_REG
;
8575 /* PR 12854: Error on extraneous shifts. */
8576 constraint (inst
.operands
[2].shifted
,
8577 _("extraneous shift as part of operand to shift insn"));
8580 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8586 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8587 inst
.reloc
.pc_rel
= 0;
8593 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8594 inst
.reloc
.pc_rel
= 0;
8600 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8601 inst
.reloc
.pc_rel
= 0;
8604 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8605 SMLAxy{cond} Rd,Rm,Rs,Rn
8606 SMLAWy{cond} Rd,Rm,Rs,Rn
8607 Error if any register is R15. */
8612 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8613 inst
.instruction
|= inst
.operands
[1].reg
;
8614 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8615 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8618 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8619 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8620 Error if any register is R15.
8621 Warning if Rdlo == Rdhi. */
8626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8627 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8628 inst
.instruction
|= inst
.operands
[2].reg
;
8629 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8631 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8632 as_tsktsk (_("rdhi and rdlo must be different"));
8635 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8636 SMULxy{cond} Rd,Rm,Rs
8637 Error if any register is R15. */
8642 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8643 inst
.instruction
|= inst
.operands
[1].reg
;
8644 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8647 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8648 the same for both ARM and Thumb-2. */
8655 if (inst
.operands
[0].present
)
8657 reg
= inst
.operands
[0].reg
;
8658 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8663 inst
.instruction
|= reg
<< 16;
8664 inst
.instruction
|= inst
.operands
[1].imm
;
8665 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8666 inst
.instruction
|= WRITE_BACK
;
8669 /* ARM V6 strex (argument parse). */
8674 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8675 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8676 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8677 || inst
.operands
[2].negative
8678 /* See comment in do_ldrex(). */
8679 || (inst
.operands
[2].reg
== REG_PC
),
8682 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8683 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8685 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8686 || inst
.reloc
.exp
.X_add_number
!= 0,
8687 _("offset must be zero in ARM encoding"));
8689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8690 inst
.instruction
|= inst
.operands
[1].reg
;
8691 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8692 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8698 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8699 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8700 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8701 || inst
.operands
[2].negative
,
8704 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8705 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8713 constraint (inst
.operands
[1].reg
% 2 != 0,
8714 _("even register required"));
8715 constraint (inst
.operands
[2].present
8716 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8717 _("can only store two consecutive registers"));
8718 /* If op 2 were present and equal to PC, this function wouldn't
8719 have been called in the first place. */
8720 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8722 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8723 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8724 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8728 inst
.instruction
|= inst
.operands
[1].reg
;
8729 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8732 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8733 extends it to 32-bits, and adds the result to a value in another
8734 register. You can specify a rotation by 0, 8, 16, or 24 bits
8735 before extracting the 16-bit value.
8736 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8737 Condition defaults to COND_ALWAYS.
8738 Error if any register uses R15. */
8743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8744 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8745 inst
.instruction
|= inst
.operands
[2].reg
;
8746 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8751 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8752 Condition defaults to COND_ALWAYS.
8753 Error if any register uses R15. */
8758 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8759 inst
.instruction
|= inst
.operands
[1].reg
;
8760 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8763 /* VFP instructions. In a logical order: SP variant first, monad
8764 before dyad, arithmetic then move then load/store. */
8767 do_vfp_sp_monadic (void)
8769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8770 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8774 do_vfp_sp_dyadic (void)
8776 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8777 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8778 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8782 do_vfp_sp_compare_z (void)
8784 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8788 do_vfp_dp_sp_cvt (void)
8790 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8791 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8795 do_vfp_sp_dp_cvt (void)
8797 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8798 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8802 do_vfp_reg_from_sp (void)
8804 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8805 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8809 do_vfp_reg2_from_sp2 (void)
8811 constraint (inst
.operands
[2].imm
!= 2,
8812 _("only two consecutive VFP SP registers allowed here"));
8813 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8814 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8815 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8819 do_vfp_sp_from_reg (void)
8821 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8822 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8826 do_vfp_sp2_from_reg2 (void)
8828 constraint (inst
.operands
[0].imm
!= 2,
8829 _("only two consecutive VFP SP registers allowed here"));
8830 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8831 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8832 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8836 do_vfp_sp_ldst (void)
8838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8839 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8843 do_vfp_dp_ldst (void)
8845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8846 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8851 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8853 if (inst
.operands
[0].writeback
)
8854 inst
.instruction
|= WRITE_BACK
;
8856 constraint (ldstm_type
!= VFP_LDSTMIA
,
8857 _("this addressing mode requires base-register writeback"));
8858 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8859 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8860 inst
.instruction
|= inst
.operands
[1].imm
;
8864 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8868 if (inst
.operands
[0].writeback
)
8869 inst
.instruction
|= WRITE_BACK
;
8871 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8872 _("this addressing mode requires base-register writeback"));
8874 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8875 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8877 count
= inst
.operands
[1].imm
<< 1;
8878 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8881 inst
.instruction
|= count
;
8885 do_vfp_sp_ldstmia (void)
8887 vfp_sp_ldstm (VFP_LDSTMIA
);
8891 do_vfp_sp_ldstmdb (void)
8893 vfp_sp_ldstm (VFP_LDSTMDB
);
8897 do_vfp_dp_ldstmia (void)
8899 vfp_dp_ldstm (VFP_LDSTMIA
);
8903 do_vfp_dp_ldstmdb (void)
8905 vfp_dp_ldstm (VFP_LDSTMDB
);
8909 do_vfp_xp_ldstmia (void)
8911 vfp_dp_ldstm (VFP_LDSTMIAX
);
8915 do_vfp_xp_ldstmdb (void)
8917 vfp_dp_ldstm (VFP_LDSTMDBX
);
8921 do_vfp_dp_rd_rm (void)
8923 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8924 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8928 do_vfp_dp_rn_rd (void)
8930 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8931 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8935 do_vfp_dp_rd_rn (void)
8937 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8938 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8942 do_vfp_dp_rd_rn_rm (void)
8944 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8945 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8946 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8952 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8956 do_vfp_dp_rm_rd_rn (void)
8958 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8959 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8960 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8963 /* VFPv3 instructions. */
8965 do_vfp_sp_const (void)
8967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8968 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8969 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8973 do_vfp_dp_const (void)
8975 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8976 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8977 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8981 vfp_conv (int srcsize
)
8983 int immbits
= srcsize
- inst
.operands
[1].imm
;
8985 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
8987 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8988 i.e. immbits must be in range 0 - 16. */
8989 inst
.error
= _("immediate value out of range, expected range [0, 16]");
8992 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
8994 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8995 i.e. immbits must be in range 0 - 31. */
8996 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9000 inst
.instruction
|= (immbits
& 1) << 5;
9001 inst
.instruction
|= (immbits
>> 1);
9005 do_vfp_sp_conv_16 (void)
9007 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9012 do_vfp_dp_conv_16 (void)
9014 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9019 do_vfp_sp_conv_32 (void)
9021 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9026 do_vfp_dp_conv_32 (void)
9028 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9032 /* FPA instructions. Also in a logical order. */
9037 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9038 inst
.instruction
|= inst
.operands
[1].reg
;
9042 do_fpa_ldmstm (void)
9044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9045 switch (inst
.operands
[1].imm
)
9047 case 1: inst
.instruction
|= CP_T_X
; break;
9048 case 2: inst
.instruction
|= CP_T_Y
; break;
9049 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9054 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9056 /* The instruction specified "ea" or "fd", so we can only accept
9057 [Rn]{!}. The instruction does not really support stacking or
9058 unstacking, so we have to emulate these by setting appropriate
9059 bits and offsets. */
9060 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9061 || inst
.reloc
.exp
.X_add_number
!= 0,
9062 _("this instruction does not support indexing"));
9064 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9065 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9067 if (!(inst
.instruction
& INDEX_UP
))
9068 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9070 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9072 inst
.operands
[2].preind
= 0;
9073 inst
.operands
[2].postind
= 1;
9077 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9080 /* iWMMXt instructions: strictly in alphabetical order. */
9083 do_iwmmxt_tandorc (void)
9085 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9089 do_iwmmxt_textrc (void)
9091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9092 inst
.instruction
|= inst
.operands
[1].imm
;
9096 do_iwmmxt_textrm (void)
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9100 inst
.instruction
|= inst
.operands
[2].imm
;
9104 do_iwmmxt_tinsr (void)
9106 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9107 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9108 inst
.instruction
|= inst
.operands
[2].imm
;
9112 do_iwmmxt_tmia (void)
9114 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9115 inst
.instruction
|= inst
.operands
[1].reg
;
9116 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9120 do_iwmmxt_waligni (void)
9122 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9123 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9124 inst
.instruction
|= inst
.operands
[2].reg
;
9125 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9129 do_iwmmxt_wmerge (void)
9131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9132 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9133 inst
.instruction
|= inst
.operands
[2].reg
;
9134 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9138 do_iwmmxt_wmov (void)
9140 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9142 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9143 inst
.instruction
|= inst
.operands
[1].reg
;
9147 do_iwmmxt_wldstbh (void)
9150 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9152 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9154 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9155 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9159 do_iwmmxt_wldstw (void)
9161 /* RIWR_RIWC clears .isreg for a control register. */
9162 if (!inst
.operands
[0].isreg
)
9164 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9165 inst
.instruction
|= 0xf0000000;
9168 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9169 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9173 do_iwmmxt_wldstd (void)
9175 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9176 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9177 && inst
.operands
[1].immisreg
)
9179 inst
.instruction
&= ~0x1a000ff;
9180 inst
.instruction
|= (0xf << 28);
9181 if (inst
.operands
[1].preind
)
9182 inst
.instruction
|= PRE_INDEX
;
9183 if (!inst
.operands
[1].negative
)
9184 inst
.instruction
|= INDEX_UP
;
9185 if (inst
.operands
[1].writeback
)
9186 inst
.instruction
|= WRITE_BACK
;
9187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9188 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9189 inst
.instruction
|= inst
.operands
[1].imm
;
9192 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9196 do_iwmmxt_wshufh (void)
9198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9200 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9201 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9205 do_iwmmxt_wzero (void)
9207 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9208 inst
.instruction
|= inst
.operands
[0].reg
;
9209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9210 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9214 do_iwmmxt_wrwrwr_or_imm5 (void)
9216 if (inst
.operands
[2].isreg
)
9219 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9220 _("immediate operand requires iWMMXt2"));
9222 if (inst
.operands
[2].imm
== 0)
9224 switch ((inst
.instruction
>> 20) & 0xf)
9230 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9231 inst
.operands
[2].imm
= 16;
9232 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9238 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9239 inst
.operands
[2].imm
= 32;
9240 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9247 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9249 wrn
= (inst
.instruction
>> 16) & 0xf;
9250 inst
.instruction
&= 0xff0fff0f;
9251 inst
.instruction
|= wrn
;
9252 /* Bail out here; the instruction is now assembled. */
9257 /* Map 32 -> 0, etc. */
9258 inst
.operands
[2].imm
&= 0x1f;
9259 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9263 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9264 operations first, then control, shift, and load/store. */
9266 /* Insns like "foo X,Y,Z". */
9269 do_mav_triple (void)
9271 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9272 inst
.instruction
|= inst
.operands
[1].reg
;
9273 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9276 /* Insns like "foo W,X,Y,Z".
9277 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9282 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9283 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9284 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9285 inst
.instruction
|= inst
.operands
[3].reg
;
9288 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9292 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9295 /* Maverick shift immediate instructions.
9296 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9297 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9302 int imm
= inst
.operands
[2].imm
;
9304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9305 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9307 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9308 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9309 Bit 4 should be 0. */
9310 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9312 inst
.instruction
|= imm
;
9315 /* XScale instructions. Also sorted arithmetic before move. */
9317 /* Xscale multiply-accumulate (argument parse)
9320 MIAxycc acc0,Rm,Rs. */
9325 inst
.instruction
|= inst
.operands
[1].reg
;
9326 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9329 /* Xscale move-accumulator-register (argument parse)
9331 MARcc acc0,RdLo,RdHi. */
9336 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9337 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9340 /* Xscale move-register-accumulator (argument parse)
9342 MRAcc RdLo,RdHi,acc0. */
9347 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9349 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9352 /* Encoding functions relevant only to Thumb. */
9354 /* inst.operands[i] is a shifted-register operand; encode
9355 it into inst.instruction in the format used by Thumb32. */
9358 encode_thumb32_shifted_operand (int i
)
9360 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9361 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9363 constraint (inst
.operands
[i
].immisreg
,
9364 _("shift by register not allowed in thumb mode"));
9365 inst
.instruction
|= inst
.operands
[i
].reg
;
9366 if (shift
== SHIFT_RRX
)
9367 inst
.instruction
|= SHIFT_ROR
<< 4;
9370 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9371 _("expression too complex"));
9373 constraint (value
> 32
9374 || (value
== 32 && (shift
== SHIFT_LSL
9375 || shift
== SHIFT_ROR
)),
9376 _("shift expression is too large"));
9380 else if (value
== 32)
9383 inst
.instruction
|= shift
<< 4;
9384 inst
.instruction
|= (value
& 0x1c) << 10;
9385 inst
.instruction
|= (value
& 0x03) << 6;
9390 /* inst.operands[i] was set up by parse_address. Encode it into a
9391 Thumb32 format load or store instruction. Reject forms that cannot
9392 be used with such instructions. If is_t is true, reject forms that
9393 cannot be used with a T instruction; if is_d is true, reject forms
9394 that cannot be used with a D instruction. If it is a store insn,
9398 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9400 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9402 constraint (!inst
.operands
[i
].isreg
,
9403 _("Instruction does not support =N addresses"));
9405 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9406 if (inst
.operands
[i
].immisreg
)
9408 constraint (is_pc
, BAD_PC_ADDRESSING
);
9409 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9410 constraint (inst
.operands
[i
].negative
,
9411 _("Thumb does not support negative register indexing"));
9412 constraint (inst
.operands
[i
].postind
,
9413 _("Thumb does not support register post-indexing"));
9414 constraint (inst
.operands
[i
].writeback
,
9415 _("Thumb does not support register indexing with writeback"));
9416 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9417 _("Thumb supports only LSL in shifted register indexing"));
9419 inst
.instruction
|= inst
.operands
[i
].imm
;
9420 if (inst
.operands
[i
].shifted
)
9422 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9423 _("expression too complex"));
9424 constraint (inst
.reloc
.exp
.X_add_number
< 0
9425 || inst
.reloc
.exp
.X_add_number
> 3,
9426 _("shift out of range"));
9427 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9429 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9431 else if (inst
.operands
[i
].preind
)
9433 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9434 constraint (is_t
&& inst
.operands
[i
].writeback
,
9435 _("cannot use writeback with this instruction"));
9436 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9437 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9441 inst
.instruction
|= 0x01000000;
9442 if (inst
.operands
[i
].writeback
)
9443 inst
.instruction
|= 0x00200000;
9447 inst
.instruction
|= 0x00000c00;
9448 if (inst
.operands
[i
].writeback
)
9449 inst
.instruction
|= 0x00000100;
9451 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9453 else if (inst
.operands
[i
].postind
)
9455 gas_assert (inst
.operands
[i
].writeback
);
9456 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9457 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9460 inst
.instruction
|= 0x00200000;
9462 inst
.instruction
|= 0x00000900;
9463 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9465 else /* unindexed - only for coprocessor */
9466 inst
.error
= _("instruction does not accept unindexed addressing");
9469 /* Table of Thumb instructions which exist in both 16- and 32-bit
9470 encodings (the latter only in post-V6T2 cores). The index is the
9471 value used in the insns table below. When there is more than one
9472 possible 16-bit encoding for the instruction, this table always
9474 Also contains several pseudo-instructions used during relaxation. */
9475 #define T16_32_TAB \
9476 X(_adc, 4140, eb400000), \
9477 X(_adcs, 4140, eb500000), \
9478 X(_add, 1c00, eb000000), \
9479 X(_adds, 1c00, eb100000), \
9480 X(_addi, 0000, f1000000), \
9481 X(_addis, 0000, f1100000), \
9482 X(_add_pc,000f, f20f0000), \
9483 X(_add_sp,000d, f10d0000), \
9484 X(_adr, 000f, f20f0000), \
9485 X(_and, 4000, ea000000), \
9486 X(_ands, 4000, ea100000), \
9487 X(_asr, 1000, fa40f000), \
9488 X(_asrs, 1000, fa50f000), \
9489 X(_b, e000, f000b000), \
9490 X(_bcond, d000, f0008000), \
9491 X(_bic, 4380, ea200000), \
9492 X(_bics, 4380, ea300000), \
9493 X(_cmn, 42c0, eb100f00), \
9494 X(_cmp, 2800, ebb00f00), \
9495 X(_cpsie, b660, f3af8400), \
9496 X(_cpsid, b670, f3af8600), \
9497 X(_cpy, 4600, ea4f0000), \
9498 X(_dec_sp,80dd, f1ad0d00), \
9499 X(_eor, 4040, ea800000), \
9500 X(_eors, 4040, ea900000), \
9501 X(_inc_sp,00dd, f10d0d00), \
9502 X(_ldmia, c800, e8900000), \
9503 X(_ldr, 6800, f8500000), \
9504 X(_ldrb, 7800, f8100000), \
9505 X(_ldrh, 8800, f8300000), \
9506 X(_ldrsb, 5600, f9100000), \
9507 X(_ldrsh, 5e00, f9300000), \
9508 X(_ldr_pc,4800, f85f0000), \
9509 X(_ldr_pc2,4800, f85f0000), \
9510 X(_ldr_sp,9800, f85d0000), \
9511 X(_lsl, 0000, fa00f000), \
9512 X(_lsls, 0000, fa10f000), \
9513 X(_lsr, 0800, fa20f000), \
9514 X(_lsrs, 0800, fa30f000), \
9515 X(_mov, 2000, ea4f0000), \
9516 X(_movs, 2000, ea5f0000), \
9517 X(_mul, 4340, fb00f000), \
9518 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9519 X(_mvn, 43c0, ea6f0000), \
9520 X(_mvns, 43c0, ea7f0000), \
9521 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9522 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9523 X(_orr, 4300, ea400000), \
9524 X(_orrs, 4300, ea500000), \
9525 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9526 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9527 X(_rev, ba00, fa90f080), \
9528 X(_rev16, ba40, fa90f090), \
9529 X(_revsh, bac0, fa90f0b0), \
9530 X(_ror, 41c0, fa60f000), \
9531 X(_rors, 41c0, fa70f000), \
9532 X(_sbc, 4180, eb600000), \
9533 X(_sbcs, 4180, eb700000), \
9534 X(_stmia, c000, e8800000), \
9535 X(_str, 6000, f8400000), \
9536 X(_strb, 7000, f8000000), \
9537 X(_strh, 8000, f8200000), \
9538 X(_str_sp,9000, f84d0000), \
9539 X(_sub, 1e00, eba00000), \
9540 X(_subs, 1e00, ebb00000), \
9541 X(_subi, 8000, f1a00000), \
9542 X(_subis, 8000, f1b00000), \
9543 X(_sxtb, b240, fa4ff080), \
9544 X(_sxth, b200, fa0ff080), \
9545 X(_tst, 4200, ea100f00), \
9546 X(_uxtb, b2c0, fa5ff080), \
9547 X(_uxth, b280, fa1ff080), \
9548 X(_nop, bf00, f3af8000), \
9549 X(_yield, bf10, f3af8001), \
9550 X(_wfe, bf20, f3af8002), \
9551 X(_wfi, bf30, f3af8003), \
9552 X(_sev, bf40, f3af8004), \
9553 X(_sevl, bf50, f3af8005)
9555 /* To catch errors in encoding functions, the codes are all offset by
9556 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9557 as 16-bit instructions. */
9558 #define X(a,b,c) T_MNEM##a
9559 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9562 #define X(a,b,c) 0x##b
9563 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9564 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9567 #define X(a,b,c) 0x##c
9568 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9569 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9570 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9574 /* Thumb instruction encoders, in alphabetical order. */
9579 do_t_add_sub_w (void)
9583 Rd
= inst
.operands
[0].reg
;
9584 Rn
= inst
.operands
[1].reg
;
9586 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9587 is the SP-{plus,minus}-immediate form of the instruction. */
9589 constraint (Rd
== REG_PC
, BAD_PC
);
9591 reject_bad_reg (Rd
);
9593 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9594 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9597 /* Parse an add or subtract instruction. We get here with inst.instruction
9598 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9605 Rd
= inst
.operands
[0].reg
;
9606 Rs
= (inst
.operands
[1].present
9607 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9608 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9611 set_it_insn_type_last ();
9619 flags
= (inst
.instruction
== T_MNEM_adds
9620 || inst
.instruction
== T_MNEM_subs
);
9622 narrow
= !in_it_block ();
9624 narrow
= in_it_block ();
9625 if (!inst
.operands
[2].isreg
)
9629 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9631 add
= (inst
.instruction
== T_MNEM_add
9632 || inst
.instruction
== T_MNEM_adds
);
9634 if (inst
.size_req
!= 4)
9636 /* Attempt to use a narrow opcode, with relaxation if
9638 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9639 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9640 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9641 opcode
= T_MNEM_add_sp
;
9642 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9643 opcode
= T_MNEM_add_pc
;
9644 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9647 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9649 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9653 inst
.instruction
= THUMB_OP16(opcode
);
9654 inst
.instruction
|= (Rd
<< 4) | Rs
;
9655 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9656 if (inst
.size_req
!= 2)
9657 inst
.relax
= opcode
;
9660 constraint (inst
.size_req
== 2, BAD_HIREG
);
9662 if (inst
.size_req
== 4
9663 || (inst
.size_req
!= 2 && !opcode
))
9667 constraint (add
, BAD_PC
);
9668 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9669 _("only SUBS PC, LR, #const allowed"));
9670 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9671 _("expression too complex"));
9672 constraint (inst
.reloc
.exp
.X_add_number
< 0
9673 || inst
.reloc
.exp
.X_add_number
> 0xff,
9674 _("immediate value out of range"));
9675 inst
.instruction
= T2_SUBS_PC_LR
9676 | inst
.reloc
.exp
.X_add_number
;
9677 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9680 else if (Rs
== REG_PC
)
9682 /* Always use addw/subw. */
9683 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9684 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9688 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9689 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9692 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9694 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9696 inst
.instruction
|= Rd
<< 8;
9697 inst
.instruction
|= Rs
<< 16;
9702 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9703 unsigned int shift
= inst
.operands
[2].shift_kind
;
9705 Rn
= inst
.operands
[2].reg
;
9706 /* See if we can do this with a 16-bit instruction. */
9707 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9709 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9714 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9715 || inst
.instruction
== T_MNEM_add
)
9718 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9722 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9724 /* Thumb-1 cores (except v6-M) require at least one high
9725 register in a narrow non flag setting add. */
9726 if (Rd
> 7 || Rn
> 7
9727 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9728 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9735 inst
.instruction
= T_OPCODE_ADD_HI
;
9736 inst
.instruction
|= (Rd
& 8) << 4;
9737 inst
.instruction
|= (Rd
& 7);
9738 inst
.instruction
|= Rn
<< 3;
9744 constraint (Rd
== REG_PC
, BAD_PC
);
9745 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9746 constraint (Rs
== REG_PC
, BAD_PC
);
9747 reject_bad_reg (Rn
);
9749 /* If we get here, it can't be done in 16 bits. */
9750 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9751 _("shift must be constant"));
9752 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9753 inst
.instruction
|= Rd
<< 8;
9754 inst
.instruction
|= Rs
<< 16;
9755 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9756 _("shift value over 3 not allowed in thumb mode"));
9757 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9758 _("only LSL shift allowed in thumb mode"));
9759 encode_thumb32_shifted_operand (2);
9764 constraint (inst
.instruction
== T_MNEM_adds
9765 || inst
.instruction
== T_MNEM_subs
,
9768 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9770 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9771 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9774 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9776 inst
.instruction
|= (Rd
<< 4) | Rs
;
9777 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9781 Rn
= inst
.operands
[2].reg
;
9782 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9784 /* We now have Rd, Rs, and Rn set to registers. */
9785 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9787 /* Can't do this for SUB. */
9788 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9789 inst
.instruction
= T_OPCODE_ADD_HI
;
9790 inst
.instruction
|= (Rd
& 8) << 4;
9791 inst
.instruction
|= (Rd
& 7);
9793 inst
.instruction
|= Rn
<< 3;
9795 inst
.instruction
|= Rs
<< 3;
9797 constraint (1, _("dest must overlap one source register"));
9801 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9802 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9803 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9813 Rd
= inst
.operands
[0].reg
;
9814 reject_bad_reg (Rd
);
9816 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9818 /* Defer to section relaxation. */
9819 inst
.relax
= inst
.instruction
;
9820 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9821 inst
.instruction
|= Rd
<< 4;
9823 else if (unified_syntax
&& inst
.size_req
!= 2)
9825 /* Generate a 32-bit opcode. */
9826 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9827 inst
.instruction
|= Rd
<< 8;
9828 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9829 inst
.reloc
.pc_rel
= 1;
9833 /* Generate a 16-bit opcode. */
9834 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9835 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9836 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9837 inst
.reloc
.pc_rel
= 1;
9839 inst
.instruction
|= Rd
<< 4;
9843 /* Arithmetic instructions for which there is just one 16-bit
9844 instruction encoding, and it allows only two low registers.
9845 For maximal compatibility with ARM syntax, we allow three register
9846 operands even when Thumb-32 instructions are not available, as long
9847 as the first two are identical. For instance, both "sbc r0,r1" and
9848 "sbc r0,r0,r1" are allowed. */
9854 Rd
= inst
.operands
[0].reg
;
9855 Rs
= (inst
.operands
[1].present
9856 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9857 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9858 Rn
= inst
.operands
[2].reg
;
9860 reject_bad_reg (Rd
);
9861 reject_bad_reg (Rs
);
9862 if (inst
.operands
[2].isreg
)
9863 reject_bad_reg (Rn
);
9867 if (!inst
.operands
[2].isreg
)
9869 /* For an immediate, we always generate a 32-bit opcode;
9870 section relaxation will shrink it later if possible. */
9871 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9872 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9873 inst
.instruction
|= Rd
<< 8;
9874 inst
.instruction
|= Rs
<< 16;
9875 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9881 /* See if we can do this with a 16-bit instruction. */
9882 if (THUMB_SETS_FLAGS (inst
.instruction
))
9883 narrow
= !in_it_block ();
9885 narrow
= in_it_block ();
9887 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9889 if (inst
.operands
[2].shifted
)
9891 if (inst
.size_req
== 4)
9897 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9898 inst
.instruction
|= Rd
;
9899 inst
.instruction
|= Rn
<< 3;
9903 /* If we get here, it can't be done in 16 bits. */
9904 constraint (inst
.operands
[2].shifted
9905 && inst
.operands
[2].immisreg
,
9906 _("shift must be constant"));
9907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9908 inst
.instruction
|= Rd
<< 8;
9909 inst
.instruction
|= Rs
<< 16;
9910 encode_thumb32_shifted_operand (2);
9915 /* On its face this is a lie - the instruction does set the
9916 flags. However, the only supported mnemonic in this mode
9918 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9920 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9921 _("unshifted register required"));
9922 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9923 constraint (Rd
!= Rs
,
9924 _("dest and source1 must be the same register"));
9926 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9927 inst
.instruction
|= Rd
;
9928 inst
.instruction
|= Rn
<< 3;
9932 /* Similarly, but for instructions where the arithmetic operation is
9933 commutative, so we can allow either of them to be different from
9934 the destination operand in a 16-bit instruction. For instance, all
9935 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9942 Rd
= inst
.operands
[0].reg
;
9943 Rs
= (inst
.operands
[1].present
9944 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9945 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9946 Rn
= inst
.operands
[2].reg
;
9948 reject_bad_reg (Rd
);
9949 reject_bad_reg (Rs
);
9950 if (inst
.operands
[2].isreg
)
9951 reject_bad_reg (Rn
);
9955 if (!inst
.operands
[2].isreg
)
9957 /* For an immediate, we always generate a 32-bit opcode;
9958 section relaxation will shrink it later if possible. */
9959 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9960 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9961 inst
.instruction
|= Rd
<< 8;
9962 inst
.instruction
|= Rs
<< 16;
9963 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9969 /* See if we can do this with a 16-bit instruction. */
9970 if (THUMB_SETS_FLAGS (inst
.instruction
))
9971 narrow
= !in_it_block ();
9973 narrow
= in_it_block ();
9975 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9977 if (inst
.operands
[2].shifted
)
9979 if (inst
.size_req
== 4)
9986 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9987 inst
.instruction
|= Rd
;
9988 inst
.instruction
|= Rn
<< 3;
9993 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9994 inst
.instruction
|= Rd
;
9995 inst
.instruction
|= Rs
<< 3;
10000 /* If we get here, it can't be done in 16 bits. */
10001 constraint (inst
.operands
[2].shifted
10002 && inst
.operands
[2].immisreg
,
10003 _("shift must be constant"));
10004 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10005 inst
.instruction
|= Rd
<< 8;
10006 inst
.instruction
|= Rs
<< 16;
10007 encode_thumb32_shifted_operand (2);
10012 /* On its face this is a lie - the instruction does set the
10013 flags. However, the only supported mnemonic in this mode
10014 says it doesn't. */
10015 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10017 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10018 _("unshifted register required"));
10019 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10021 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10022 inst
.instruction
|= Rd
;
10025 inst
.instruction
|= Rn
<< 3;
10027 inst
.instruction
|= Rs
<< 3;
10029 constraint (1, _("dest must overlap one source register"));
10034 do_t_barrier (void)
10036 if (inst
.operands
[0].present
)
10038 constraint ((inst
.instruction
& 0xf0) != 0x40
10039 && inst
.operands
[0].imm
> 0xf
10040 && inst
.operands
[0].imm
< 0x0,
10041 _("bad barrier type"));
10042 inst
.instruction
|= inst
.operands
[0].imm
;
10045 inst
.instruction
|= 0xf;
10052 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10053 constraint (msb
> 32, _("bit-field extends past end of register"));
10054 /* The instruction encoding stores the LSB and MSB,
10055 not the LSB and width. */
10056 Rd
= inst
.operands
[0].reg
;
10057 reject_bad_reg (Rd
);
10058 inst
.instruction
|= Rd
<< 8;
10059 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10060 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10061 inst
.instruction
|= msb
- 1;
10070 Rd
= inst
.operands
[0].reg
;
10071 reject_bad_reg (Rd
);
10073 /* #0 in second position is alternative syntax for bfc, which is
10074 the same instruction but with REG_PC in the Rm field. */
10075 if (!inst
.operands
[1].isreg
)
10079 Rn
= inst
.operands
[1].reg
;
10080 reject_bad_reg (Rn
);
10083 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10084 constraint (msb
> 32, _("bit-field extends past end of register"));
10085 /* The instruction encoding stores the LSB and MSB,
10086 not the LSB and width. */
10087 inst
.instruction
|= Rd
<< 8;
10088 inst
.instruction
|= Rn
<< 16;
10089 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10090 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10091 inst
.instruction
|= msb
- 1;
10099 Rd
= inst
.operands
[0].reg
;
10100 Rn
= inst
.operands
[1].reg
;
10102 reject_bad_reg (Rd
);
10103 reject_bad_reg (Rn
);
10105 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10106 _("bit-field extends past end of register"));
10107 inst
.instruction
|= Rd
<< 8;
10108 inst
.instruction
|= Rn
<< 16;
10109 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10110 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10111 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10114 /* ARM V5 Thumb BLX (argument parse)
10115 BLX <target_addr> which is BLX(1)
10116 BLX <Rm> which is BLX(2)
10117 Unfortunately, there are two different opcodes for this mnemonic.
10118 So, the insns[].value is not used, and the code here zaps values
10119 into inst.instruction.
10121 ??? How to take advantage of the additional two bits of displacement
10122 available in Thumb32 mode? Need new relocation? */
10127 set_it_insn_type_last ();
10129 if (inst
.operands
[0].isreg
)
10131 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10132 /* We have a register, so this is BLX(2). */
10133 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10137 /* No register. This must be BLX(1). */
10138 inst
.instruction
= 0xf000e800;
10139 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10151 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10153 if (in_it_block ())
10155 /* Conditional branches inside IT blocks are encoded as unconditional
10157 cond
= COND_ALWAYS
;
10162 if (cond
!= COND_ALWAYS
)
10163 opcode
= T_MNEM_bcond
;
10165 opcode
= inst
.instruction
;
10168 && (inst
.size_req
== 4
10169 || (inst
.size_req
!= 2
10170 && (inst
.operands
[0].hasreloc
10171 || inst
.reloc
.exp
.X_op
== O_constant
))))
10173 inst
.instruction
= THUMB_OP32(opcode
);
10174 if (cond
== COND_ALWAYS
)
10175 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10178 gas_assert (cond
!= 0xF);
10179 inst
.instruction
|= cond
<< 22;
10180 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10185 inst
.instruction
= THUMB_OP16(opcode
);
10186 if (cond
== COND_ALWAYS
)
10187 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10190 inst
.instruction
|= cond
<< 8;
10191 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10193 /* Allow section relaxation. */
10194 if (unified_syntax
&& inst
.size_req
!= 2)
10195 inst
.relax
= opcode
;
10197 inst
.reloc
.type
= reloc
;
10198 inst
.reloc
.pc_rel
= 1;
10204 constraint (inst
.cond
!= COND_ALWAYS
,
10205 _("instruction is always unconditional"));
10206 if (inst
.operands
[0].present
)
10208 constraint (inst
.operands
[0].imm
> 255,
10209 _("immediate value out of range"));
10210 inst
.instruction
|= inst
.operands
[0].imm
;
10211 set_it_insn_type (NEUTRAL_IT_INSN
);
10216 do_t_branch23 (void)
10218 set_it_insn_type_last ();
10219 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10221 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10222 this file. We used to simply ignore the PLT reloc type here --
10223 the branch encoding is now needed to deal with TLSCALL relocs.
10224 So if we see a PLT reloc now, put it back to how it used to be to
10225 keep the preexisting behaviour. */
10226 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10227 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10229 #if defined(OBJ_COFF)
10230 /* If the destination of the branch is a defined symbol which does not have
10231 the THUMB_FUNC attribute, then we must be calling a function which has
10232 the (interfacearm) attribute. We look for the Thumb entry point to that
10233 function and change the branch to refer to that function instead. */
10234 if ( inst
.reloc
.exp
.X_op
== O_symbol
10235 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10236 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10237 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10238 inst
.reloc
.exp
.X_add_symbol
=
10239 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10246 set_it_insn_type_last ();
10247 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10248 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10249 should cause the alignment to be checked once it is known. This is
10250 because BX PC only works if the instruction is word aligned. */
10258 set_it_insn_type_last ();
10259 Rm
= inst
.operands
[0].reg
;
10260 reject_bad_reg (Rm
);
10261 inst
.instruction
|= Rm
<< 16;
10270 Rd
= inst
.operands
[0].reg
;
10271 Rm
= inst
.operands
[1].reg
;
10273 reject_bad_reg (Rd
);
10274 reject_bad_reg (Rm
);
10276 inst
.instruction
|= Rd
<< 8;
10277 inst
.instruction
|= Rm
<< 16;
10278 inst
.instruction
|= Rm
;
10284 set_it_insn_type (OUTSIDE_IT_INSN
);
10285 inst
.instruction
|= inst
.operands
[0].imm
;
10291 set_it_insn_type (OUTSIDE_IT_INSN
);
10293 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10294 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10296 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10297 inst
.instruction
= 0xf3af8000;
10298 inst
.instruction
|= imod
<< 9;
10299 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10300 if (inst
.operands
[1].present
)
10301 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10305 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10306 && (inst
.operands
[0].imm
& 4),
10307 _("selected processor does not support 'A' form "
10308 "of this instruction"));
10309 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10310 _("Thumb does not support the 2-argument "
10311 "form of this instruction"));
10312 inst
.instruction
|= inst
.operands
[0].imm
;
10316 /* THUMB CPY instruction (argument parse). */
10321 if (inst
.size_req
== 4)
10323 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10324 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10325 inst
.instruction
|= inst
.operands
[1].reg
;
10329 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10330 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10331 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10338 set_it_insn_type (OUTSIDE_IT_INSN
);
10339 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10340 inst
.instruction
|= inst
.operands
[0].reg
;
10341 inst
.reloc
.pc_rel
= 1;
10342 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10348 inst
.instruction
|= inst
.operands
[0].imm
;
10354 unsigned Rd
, Rn
, Rm
;
10356 Rd
= inst
.operands
[0].reg
;
10357 Rn
= (inst
.operands
[1].present
10358 ? inst
.operands
[1].reg
: Rd
);
10359 Rm
= inst
.operands
[2].reg
;
10361 reject_bad_reg (Rd
);
10362 reject_bad_reg (Rn
);
10363 reject_bad_reg (Rm
);
10365 inst
.instruction
|= Rd
<< 8;
10366 inst
.instruction
|= Rn
<< 16;
10367 inst
.instruction
|= Rm
;
10373 if (unified_syntax
&& inst
.size_req
== 4)
10374 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10376 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10382 unsigned int cond
= inst
.operands
[0].imm
;
10384 set_it_insn_type (IT_INSN
);
10385 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10387 now_it
.warn_deprecated
= FALSE
;
10389 /* If the condition is a negative condition, invert the mask. */
10390 if ((cond
& 0x1) == 0x0)
10392 unsigned int mask
= inst
.instruction
& 0x000f;
10394 if ((mask
& 0x7) == 0)
10396 /* No conversion needed. */
10397 now_it
.block_length
= 1;
10399 else if ((mask
& 0x3) == 0)
10402 now_it
.block_length
= 2;
10404 else if ((mask
& 0x1) == 0)
10407 now_it
.block_length
= 3;
10412 now_it
.block_length
= 4;
10415 inst
.instruction
&= 0xfff0;
10416 inst
.instruction
|= mask
;
10419 inst
.instruction
|= cond
<< 4;
10422 /* Helper function used for both push/pop and ldm/stm. */
10424 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10428 load
= (inst
.instruction
& (1 << 20)) != 0;
10430 if (mask
& (1 << 13))
10431 inst
.error
= _("SP not allowed in register list");
10433 if ((mask
& (1 << base
)) != 0
10435 inst
.error
= _("having the base register in the register list when "
10436 "using write back is UNPREDICTABLE");
10440 if (mask
& (1 << 15))
10442 if (mask
& (1 << 14))
10443 inst
.error
= _("LR and PC should not both be in register list");
10445 set_it_insn_type_last ();
10450 if (mask
& (1 << 15))
10451 inst
.error
= _("PC not allowed in register list");
10454 if ((mask
& (mask
- 1)) == 0)
10456 /* Single register transfers implemented as str/ldr. */
10459 if (inst
.instruction
& (1 << 23))
10460 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10462 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10466 if (inst
.instruction
& (1 << 23))
10467 inst
.instruction
= 0x00800000; /* ia -> [base] */
10469 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10472 inst
.instruction
|= 0xf8400000;
10474 inst
.instruction
|= 0x00100000;
10476 mask
= ffs (mask
) - 1;
10479 else if (writeback
)
10480 inst
.instruction
|= WRITE_BACK
;
10482 inst
.instruction
|= mask
;
10483 inst
.instruction
|= base
<< 16;
10489 /* This really doesn't seem worth it. */
10490 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10491 _("expression too complex"));
10492 constraint (inst
.operands
[1].writeback
,
10493 _("Thumb load/store multiple does not support {reglist}^"));
10495 if (unified_syntax
)
10497 bfd_boolean narrow
;
10501 /* See if we can use a 16-bit instruction. */
10502 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10503 && inst
.size_req
!= 4
10504 && !(inst
.operands
[1].imm
& ~0xff))
10506 mask
= 1 << inst
.operands
[0].reg
;
10508 if (inst
.operands
[0].reg
<= 7)
10510 if (inst
.instruction
== T_MNEM_stmia
10511 ? inst
.operands
[0].writeback
10512 : (inst
.operands
[0].writeback
10513 == !(inst
.operands
[1].imm
& mask
)))
10515 if (inst
.instruction
== T_MNEM_stmia
10516 && (inst
.operands
[1].imm
& mask
)
10517 && (inst
.operands
[1].imm
& (mask
- 1)))
10518 as_warn (_("value stored for r%d is UNKNOWN"),
10519 inst
.operands
[0].reg
);
10521 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10522 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10523 inst
.instruction
|= inst
.operands
[1].imm
;
10526 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10528 /* This means 1 register in reg list one of 3 situations:
10529 1. Instruction is stmia, but without writeback.
10530 2. lmdia without writeback, but with Rn not in
10532 3. ldmia with writeback, but with Rn in reglist.
10533 Case 3 is UNPREDICTABLE behaviour, so we handle
10534 case 1 and 2 which can be converted into a 16-bit
10535 str or ldr. The SP cases are handled below. */
10536 unsigned long opcode
;
10537 /* First, record an error for Case 3. */
10538 if (inst
.operands
[1].imm
& mask
10539 && inst
.operands
[0].writeback
)
10541 _("having the base register in the register list when "
10542 "using write back is UNPREDICTABLE");
10544 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10546 inst
.instruction
= THUMB_OP16 (opcode
);
10547 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10548 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10552 else if (inst
.operands
[0] .reg
== REG_SP
)
10554 if (inst
.operands
[0].writeback
)
10557 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10558 ? T_MNEM_push
: T_MNEM_pop
);
10559 inst
.instruction
|= inst
.operands
[1].imm
;
10562 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10565 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10566 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10567 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10575 if (inst
.instruction
< 0xffff)
10576 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10578 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10579 inst
.operands
[0].writeback
);
10584 constraint (inst
.operands
[0].reg
> 7
10585 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10586 constraint (inst
.instruction
!= T_MNEM_ldmia
10587 && inst
.instruction
!= T_MNEM_stmia
,
10588 _("Thumb-2 instruction only valid in unified syntax"));
10589 if (inst
.instruction
== T_MNEM_stmia
)
10591 if (!inst
.operands
[0].writeback
)
10592 as_warn (_("this instruction will write back the base register"));
10593 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10594 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10595 as_warn (_("value stored for r%d is UNKNOWN"),
10596 inst
.operands
[0].reg
);
10600 if (!inst
.operands
[0].writeback
10601 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10602 as_warn (_("this instruction will write back the base register"));
10603 else if (inst
.operands
[0].writeback
10604 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10605 as_warn (_("this instruction will not write back the base register"));
10608 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10609 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10610 inst
.instruction
|= inst
.operands
[1].imm
;
10617 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10618 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10619 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10620 || inst
.operands
[1].negative
,
10623 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10625 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10626 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10627 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10633 if (!inst
.operands
[1].present
)
10635 constraint (inst
.operands
[0].reg
== REG_LR
,
10636 _("r14 not allowed as first register "
10637 "when second register is omitted"));
10638 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10640 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10644 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10645 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10651 unsigned long opcode
;
10654 if (inst
.operands
[0].isreg
10655 && !inst
.operands
[0].preind
10656 && inst
.operands
[0].reg
== REG_PC
)
10657 set_it_insn_type_last ();
10659 opcode
= inst
.instruction
;
10660 if (unified_syntax
)
10662 if (!inst
.operands
[1].isreg
)
10664 if (opcode
<= 0xffff)
10665 inst
.instruction
= THUMB_OP32 (opcode
);
10666 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10669 if (inst
.operands
[1].isreg
10670 && !inst
.operands
[1].writeback
10671 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10672 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10673 && opcode
<= 0xffff
10674 && inst
.size_req
!= 4)
10676 /* Insn may have a 16-bit form. */
10677 Rn
= inst
.operands
[1].reg
;
10678 if (inst
.operands
[1].immisreg
)
10680 inst
.instruction
= THUMB_OP16 (opcode
);
10682 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10684 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10685 reject_bad_reg (inst
.operands
[1].imm
);
10687 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10688 && opcode
!= T_MNEM_ldrsb
)
10689 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10690 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10697 if (inst
.reloc
.pc_rel
)
10698 opcode
= T_MNEM_ldr_pc2
;
10700 opcode
= T_MNEM_ldr_pc
;
10704 if (opcode
== T_MNEM_ldr
)
10705 opcode
= T_MNEM_ldr_sp
;
10707 opcode
= T_MNEM_str_sp
;
10709 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10713 inst
.instruction
= inst
.operands
[0].reg
;
10714 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10716 inst
.instruction
|= THUMB_OP16 (opcode
);
10717 if (inst
.size_req
== 2)
10718 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10720 inst
.relax
= opcode
;
10724 /* Definitely a 32-bit variant. */
10726 /* Warning for Erratum 752419. */
10727 if (opcode
== T_MNEM_ldr
10728 && inst
.operands
[0].reg
== REG_SP
10729 && inst
.operands
[1].writeback
== 1
10730 && !inst
.operands
[1].immisreg
)
10732 if (no_cpu_selected ()
10733 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10734 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10735 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10736 as_warn (_("This instruction may be unpredictable "
10737 "if executed on M-profile cores "
10738 "with interrupts enabled."));
10741 /* Do some validations regarding addressing modes. */
10742 if (inst
.operands
[1].immisreg
)
10743 reject_bad_reg (inst
.operands
[1].imm
);
10745 constraint (inst
.operands
[1].writeback
== 1
10746 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10749 inst
.instruction
= THUMB_OP32 (opcode
);
10750 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10751 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10752 check_ldr_r15_aligned ();
10756 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10758 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10760 /* Only [Rn,Rm] is acceptable. */
10761 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10762 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10763 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10764 || inst
.operands
[1].negative
,
10765 _("Thumb does not support this addressing mode"));
10766 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10771 if (!inst
.operands
[1].isreg
)
10772 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10775 constraint (!inst
.operands
[1].preind
10776 || inst
.operands
[1].shifted
10777 || inst
.operands
[1].writeback
,
10778 _("Thumb does not support this addressing mode"));
10779 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10781 constraint (inst
.instruction
& 0x0600,
10782 _("byte or halfword not valid for base register"));
10783 constraint (inst
.operands
[1].reg
== REG_PC
10784 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10785 _("r15 based store not allowed"));
10786 constraint (inst
.operands
[1].immisreg
,
10787 _("invalid base register for register offset"));
10789 if (inst
.operands
[1].reg
== REG_PC
)
10790 inst
.instruction
= T_OPCODE_LDR_PC
;
10791 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10792 inst
.instruction
= T_OPCODE_LDR_SP
;
10794 inst
.instruction
= T_OPCODE_STR_SP
;
10796 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10797 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10801 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10802 if (!inst
.operands
[1].immisreg
)
10804 /* Immediate offset. */
10805 inst
.instruction
|= inst
.operands
[0].reg
;
10806 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10807 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10811 /* Register offset. */
10812 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10813 constraint (inst
.operands
[1].negative
,
10814 _("Thumb does not support this addressing mode"));
10817 switch (inst
.instruction
)
10819 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10820 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10821 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10822 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10823 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10824 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10825 case 0x5600 /* ldrsb */:
10826 case 0x5e00 /* ldrsh */: break;
10830 inst
.instruction
|= inst
.operands
[0].reg
;
10831 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10832 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10838 if (!inst
.operands
[1].present
)
10840 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10841 constraint (inst
.operands
[0].reg
== REG_LR
,
10842 _("r14 not allowed here"));
10843 constraint (inst
.operands
[0].reg
== REG_R12
,
10844 _("r12 not allowed here"));
10847 if (inst
.operands
[2].writeback
10848 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
10849 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
10850 as_warn (_("base register written back, and overlaps "
10851 "one of transfer registers"));
10853 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10854 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10855 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10861 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10862 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10868 unsigned Rd
, Rn
, Rm
, Ra
;
10870 Rd
= inst
.operands
[0].reg
;
10871 Rn
= inst
.operands
[1].reg
;
10872 Rm
= inst
.operands
[2].reg
;
10873 Ra
= inst
.operands
[3].reg
;
10875 reject_bad_reg (Rd
);
10876 reject_bad_reg (Rn
);
10877 reject_bad_reg (Rm
);
10878 reject_bad_reg (Ra
);
10880 inst
.instruction
|= Rd
<< 8;
10881 inst
.instruction
|= Rn
<< 16;
10882 inst
.instruction
|= Rm
;
10883 inst
.instruction
|= Ra
<< 12;
10889 unsigned RdLo
, RdHi
, Rn
, Rm
;
10891 RdLo
= inst
.operands
[0].reg
;
10892 RdHi
= inst
.operands
[1].reg
;
10893 Rn
= inst
.operands
[2].reg
;
10894 Rm
= inst
.operands
[3].reg
;
10896 reject_bad_reg (RdLo
);
10897 reject_bad_reg (RdHi
);
10898 reject_bad_reg (Rn
);
10899 reject_bad_reg (Rm
);
10901 inst
.instruction
|= RdLo
<< 12;
10902 inst
.instruction
|= RdHi
<< 8;
10903 inst
.instruction
|= Rn
<< 16;
10904 inst
.instruction
|= Rm
;
10908 do_t_mov_cmp (void)
10912 Rn
= inst
.operands
[0].reg
;
10913 Rm
= inst
.operands
[1].reg
;
10916 set_it_insn_type_last ();
10918 if (unified_syntax
)
10920 int r0off
= (inst
.instruction
== T_MNEM_mov
10921 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10922 unsigned long opcode
;
10923 bfd_boolean narrow
;
10924 bfd_boolean low_regs
;
10926 low_regs
= (Rn
<= 7 && Rm
<= 7);
10927 opcode
= inst
.instruction
;
10928 if (in_it_block ())
10929 narrow
= opcode
!= T_MNEM_movs
;
10931 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10932 if (inst
.size_req
== 4
10933 || inst
.operands
[1].shifted
)
10936 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10937 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10938 && !inst
.operands
[1].shifted
10942 inst
.instruction
= T2_SUBS_PC_LR
;
10946 if (opcode
== T_MNEM_cmp
)
10948 constraint (Rn
== REG_PC
, BAD_PC
);
10951 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10953 warn_deprecated_sp (Rm
);
10954 /* R15 was documented as a valid choice for Rm in ARMv6,
10955 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10956 tools reject R15, so we do too. */
10957 constraint (Rm
== REG_PC
, BAD_PC
);
10960 reject_bad_reg (Rm
);
10962 else if (opcode
== T_MNEM_mov
10963 || opcode
== T_MNEM_movs
)
10965 if (inst
.operands
[1].isreg
)
10967 if (opcode
== T_MNEM_movs
)
10969 reject_bad_reg (Rn
);
10970 reject_bad_reg (Rm
);
10974 /* This is mov.n. */
10975 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10976 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10978 as_warn (_("Use of r%u as a source register is "
10979 "deprecated when r%u is the destination "
10980 "register."), Rm
, Rn
);
10985 /* This is mov.w. */
10986 constraint (Rn
== REG_PC
, BAD_PC
);
10987 constraint (Rm
== REG_PC
, BAD_PC
);
10988 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10992 reject_bad_reg (Rn
);
10995 if (!inst
.operands
[1].isreg
)
10997 /* Immediate operand. */
10998 if (!in_it_block () && opcode
== T_MNEM_mov
)
11000 if (low_regs
&& narrow
)
11002 inst
.instruction
= THUMB_OP16 (opcode
);
11003 inst
.instruction
|= Rn
<< 8;
11004 if (inst
.size_req
== 2)
11005 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11007 inst
.relax
= opcode
;
11011 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11012 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11013 inst
.instruction
|= Rn
<< r0off
;
11014 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11017 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11018 && (inst
.instruction
== T_MNEM_mov
11019 || inst
.instruction
== T_MNEM_movs
))
11021 /* Register shifts are encoded as separate shift instructions. */
11022 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11024 if (in_it_block ())
11029 if (inst
.size_req
== 4)
11032 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11038 switch (inst
.operands
[1].shift_kind
)
11041 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11044 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11047 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11050 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11056 inst
.instruction
= opcode
;
11059 inst
.instruction
|= Rn
;
11060 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11065 inst
.instruction
|= CONDS_BIT
;
11067 inst
.instruction
|= Rn
<< 8;
11068 inst
.instruction
|= Rm
<< 16;
11069 inst
.instruction
|= inst
.operands
[1].imm
;
11074 /* Some mov with immediate shift have narrow variants.
11075 Register shifts are handled above. */
11076 if (low_regs
&& inst
.operands
[1].shifted
11077 && (inst
.instruction
== T_MNEM_mov
11078 || inst
.instruction
== T_MNEM_movs
))
11080 if (in_it_block ())
11081 narrow
= (inst
.instruction
== T_MNEM_mov
);
11083 narrow
= (inst
.instruction
== T_MNEM_movs
);
11088 switch (inst
.operands
[1].shift_kind
)
11090 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11091 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11092 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11093 default: narrow
= FALSE
; break;
11099 inst
.instruction
|= Rn
;
11100 inst
.instruction
|= Rm
<< 3;
11101 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11105 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11106 inst
.instruction
|= Rn
<< r0off
;
11107 encode_thumb32_shifted_operand (1);
11111 switch (inst
.instruction
)
11114 /* In v4t or v5t a move of two lowregs produces unpredictable
11115 results. Don't allow this. */
11118 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11119 "MOV Rd, Rs with two low registers is not "
11120 "permitted on this architecture");
11121 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11125 inst
.instruction
= T_OPCODE_MOV_HR
;
11126 inst
.instruction
|= (Rn
& 0x8) << 4;
11127 inst
.instruction
|= (Rn
& 0x7);
11128 inst
.instruction
|= Rm
<< 3;
11132 /* We know we have low registers at this point.
11133 Generate LSLS Rd, Rs, #0. */
11134 inst
.instruction
= T_OPCODE_LSL_I
;
11135 inst
.instruction
|= Rn
;
11136 inst
.instruction
|= Rm
<< 3;
11142 inst
.instruction
= T_OPCODE_CMP_LR
;
11143 inst
.instruction
|= Rn
;
11144 inst
.instruction
|= Rm
<< 3;
11148 inst
.instruction
= T_OPCODE_CMP_HR
;
11149 inst
.instruction
|= (Rn
& 0x8) << 4;
11150 inst
.instruction
|= (Rn
& 0x7);
11151 inst
.instruction
|= Rm
<< 3;
11158 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11160 /* PR 10443: Do not silently ignore shifted operands. */
11161 constraint (inst
.operands
[1].shifted
,
11162 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11164 if (inst
.operands
[1].isreg
)
11166 if (Rn
< 8 && Rm
< 8)
11168 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11169 since a MOV instruction produces unpredictable results. */
11170 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11171 inst
.instruction
= T_OPCODE_ADD_I3
;
11173 inst
.instruction
= T_OPCODE_CMP_LR
;
11175 inst
.instruction
|= Rn
;
11176 inst
.instruction
|= Rm
<< 3;
11180 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11181 inst
.instruction
= T_OPCODE_MOV_HR
;
11183 inst
.instruction
= T_OPCODE_CMP_HR
;
11189 constraint (Rn
> 7,
11190 _("only lo regs allowed with immediate"));
11191 inst
.instruction
|= Rn
<< 8;
11192 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11203 top
= (inst
.instruction
& 0x00800000) != 0;
11204 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11206 constraint (top
, _(":lower16: not allowed this instruction"));
11207 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11209 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11211 constraint (!top
, _(":upper16: not allowed this instruction"));
11212 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11215 Rd
= inst
.operands
[0].reg
;
11216 reject_bad_reg (Rd
);
11218 inst
.instruction
|= Rd
<< 8;
11219 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11221 imm
= inst
.reloc
.exp
.X_add_number
;
11222 inst
.instruction
|= (imm
& 0xf000) << 4;
11223 inst
.instruction
|= (imm
& 0x0800) << 15;
11224 inst
.instruction
|= (imm
& 0x0700) << 4;
11225 inst
.instruction
|= (imm
& 0x00ff);
11230 do_t_mvn_tst (void)
11234 Rn
= inst
.operands
[0].reg
;
11235 Rm
= inst
.operands
[1].reg
;
11237 if (inst
.instruction
== T_MNEM_cmp
11238 || inst
.instruction
== T_MNEM_cmn
)
11239 constraint (Rn
== REG_PC
, BAD_PC
);
11241 reject_bad_reg (Rn
);
11242 reject_bad_reg (Rm
);
11244 if (unified_syntax
)
11246 int r0off
= (inst
.instruction
== T_MNEM_mvn
11247 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11248 bfd_boolean narrow
;
11250 if (inst
.size_req
== 4
11251 || inst
.instruction
> 0xffff
11252 || inst
.operands
[1].shifted
11253 || Rn
> 7 || Rm
> 7)
11255 else if (inst
.instruction
== T_MNEM_cmn
)
11257 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11258 narrow
= !in_it_block ();
11260 narrow
= in_it_block ();
11262 if (!inst
.operands
[1].isreg
)
11264 /* For an immediate, we always generate a 32-bit opcode;
11265 section relaxation will shrink it later if possible. */
11266 if (inst
.instruction
< 0xffff)
11267 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11268 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11269 inst
.instruction
|= Rn
<< r0off
;
11270 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11274 /* See if we can do this with a 16-bit instruction. */
11277 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11278 inst
.instruction
|= Rn
;
11279 inst
.instruction
|= Rm
<< 3;
11283 constraint (inst
.operands
[1].shifted
11284 && inst
.operands
[1].immisreg
,
11285 _("shift must be constant"));
11286 if (inst
.instruction
< 0xffff)
11287 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11288 inst
.instruction
|= Rn
<< r0off
;
11289 encode_thumb32_shifted_operand (1);
11295 constraint (inst
.instruction
> 0xffff
11296 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11297 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11298 _("unshifted register required"));
11299 constraint (Rn
> 7 || Rm
> 7,
11302 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11303 inst
.instruction
|= Rn
;
11304 inst
.instruction
|= Rm
<< 3;
11313 if (do_vfp_nsyn_mrs () == SUCCESS
)
11316 Rd
= inst
.operands
[0].reg
;
11317 reject_bad_reg (Rd
);
11318 inst
.instruction
|= Rd
<< 8;
11320 if (inst
.operands
[1].isreg
)
11322 unsigned br
= inst
.operands
[1].reg
;
11323 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11324 as_bad (_("bad register for mrs"));
11326 inst
.instruction
|= br
& (0xf << 16);
11327 inst
.instruction
|= (br
& 0x300) >> 4;
11328 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11332 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11334 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11336 /* PR gas/12698: The constraint is only applied for m_profile.
11337 If the user has specified -march=all, we want to ignore it as
11338 we are building for any CPU type, including non-m variants. */
11339 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11340 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11341 "not support requested special purpose register"));
11344 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11346 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11347 _("'APSR', 'CPSR' or 'SPSR' expected"));
11349 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11350 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11351 inst
.instruction
|= 0xf0000;
11361 if (do_vfp_nsyn_msr () == SUCCESS
)
11364 constraint (!inst
.operands
[1].isreg
,
11365 _("Thumb encoding does not support an immediate here"));
11367 if (inst
.operands
[0].isreg
)
11368 flags
= (int)(inst
.operands
[0].reg
);
11370 flags
= inst
.operands
[0].imm
;
11372 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11374 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11376 /* PR gas/12698: The constraint is only applied for m_profile.
11377 If the user has specified -march=all, we want to ignore it as
11378 we are building for any CPU type, including non-m variants. */
11379 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11380 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11381 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11382 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11383 && bits
!= PSR_f
)) && m_profile
,
11384 _("selected processor does not support requested special "
11385 "purpose register"));
11388 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11389 "requested special purpose register"));
11391 Rn
= inst
.operands
[1].reg
;
11392 reject_bad_reg (Rn
);
11394 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11395 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11396 inst
.instruction
|= (flags
& 0x300) >> 4;
11397 inst
.instruction
|= (flags
& 0xff);
11398 inst
.instruction
|= Rn
<< 16;
11404 bfd_boolean narrow
;
11405 unsigned Rd
, Rn
, Rm
;
11407 if (!inst
.operands
[2].present
)
11408 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11410 Rd
= inst
.operands
[0].reg
;
11411 Rn
= inst
.operands
[1].reg
;
11412 Rm
= inst
.operands
[2].reg
;
11414 if (unified_syntax
)
11416 if (inst
.size_req
== 4
11422 else if (inst
.instruction
== T_MNEM_muls
)
11423 narrow
= !in_it_block ();
11425 narrow
= in_it_block ();
11429 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11430 constraint (Rn
> 7 || Rm
> 7,
11437 /* 16-bit MULS/Conditional MUL. */
11438 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11439 inst
.instruction
|= Rd
;
11442 inst
.instruction
|= Rm
<< 3;
11444 inst
.instruction
|= Rn
<< 3;
11446 constraint (1, _("dest must overlap one source register"));
11450 constraint (inst
.instruction
!= T_MNEM_mul
,
11451 _("Thumb-2 MUL must not set flags"));
11453 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11454 inst
.instruction
|= Rd
<< 8;
11455 inst
.instruction
|= Rn
<< 16;
11456 inst
.instruction
|= Rm
<< 0;
11458 reject_bad_reg (Rd
);
11459 reject_bad_reg (Rn
);
11460 reject_bad_reg (Rm
);
11467 unsigned RdLo
, RdHi
, Rn
, Rm
;
11469 RdLo
= inst
.operands
[0].reg
;
11470 RdHi
= inst
.operands
[1].reg
;
11471 Rn
= inst
.operands
[2].reg
;
11472 Rm
= inst
.operands
[3].reg
;
11474 reject_bad_reg (RdLo
);
11475 reject_bad_reg (RdHi
);
11476 reject_bad_reg (Rn
);
11477 reject_bad_reg (Rm
);
11479 inst
.instruction
|= RdLo
<< 12;
11480 inst
.instruction
|= RdHi
<< 8;
11481 inst
.instruction
|= Rn
<< 16;
11482 inst
.instruction
|= Rm
;
11485 as_tsktsk (_("rdhi and rdlo must be different"));
11491 set_it_insn_type (NEUTRAL_IT_INSN
);
11493 if (unified_syntax
)
11495 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11497 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11498 inst
.instruction
|= inst
.operands
[0].imm
;
11502 /* PR9722: Check for Thumb2 availability before
11503 generating a thumb2 nop instruction. */
11504 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11506 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11507 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11510 inst
.instruction
= 0x46c0;
11515 constraint (inst
.operands
[0].present
,
11516 _("Thumb does not support NOP with hints"));
11517 inst
.instruction
= 0x46c0;
11524 if (unified_syntax
)
11526 bfd_boolean narrow
;
11528 if (THUMB_SETS_FLAGS (inst
.instruction
))
11529 narrow
= !in_it_block ();
11531 narrow
= in_it_block ();
11532 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11534 if (inst
.size_req
== 4)
11539 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11540 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11541 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11545 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11546 inst
.instruction
|= inst
.operands
[0].reg
;
11547 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11552 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11554 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11556 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11557 inst
.instruction
|= inst
.operands
[0].reg
;
11558 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11567 Rd
= inst
.operands
[0].reg
;
11568 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11570 reject_bad_reg (Rd
);
11571 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11572 reject_bad_reg (Rn
);
11574 inst
.instruction
|= Rd
<< 8;
11575 inst
.instruction
|= Rn
<< 16;
11577 if (!inst
.operands
[2].isreg
)
11579 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11580 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11586 Rm
= inst
.operands
[2].reg
;
11587 reject_bad_reg (Rm
);
11589 constraint (inst
.operands
[2].shifted
11590 && inst
.operands
[2].immisreg
,
11591 _("shift must be constant"));
11592 encode_thumb32_shifted_operand (2);
11599 unsigned Rd
, Rn
, Rm
;
11601 Rd
= inst
.operands
[0].reg
;
11602 Rn
= inst
.operands
[1].reg
;
11603 Rm
= inst
.operands
[2].reg
;
11605 reject_bad_reg (Rd
);
11606 reject_bad_reg (Rn
);
11607 reject_bad_reg (Rm
);
11609 inst
.instruction
|= Rd
<< 8;
11610 inst
.instruction
|= Rn
<< 16;
11611 inst
.instruction
|= Rm
;
11612 if (inst
.operands
[3].present
)
11614 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11615 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11616 _("expression too complex"));
11617 inst
.instruction
|= (val
& 0x1c) << 10;
11618 inst
.instruction
|= (val
& 0x03) << 6;
11625 if (!inst
.operands
[3].present
)
11629 inst
.instruction
&= ~0x00000020;
11631 /* PR 10168. Swap the Rm and Rn registers. */
11632 Rtmp
= inst
.operands
[1].reg
;
11633 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11634 inst
.operands
[2].reg
= Rtmp
;
11642 if (inst
.operands
[0].immisreg
)
11643 reject_bad_reg (inst
.operands
[0].imm
);
11645 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11649 do_t_push_pop (void)
11653 constraint (inst
.operands
[0].writeback
,
11654 _("push/pop do not support {reglist}^"));
11655 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11656 _("expression too complex"));
11658 mask
= inst
.operands
[0].imm
;
11659 if ((mask
& ~0xff) == 0)
11660 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11661 else if ((inst
.instruction
== T_MNEM_push
11662 && (mask
& ~0xff) == 1 << REG_LR
)
11663 || (inst
.instruction
== T_MNEM_pop
11664 && (mask
& ~0xff) == 1 << REG_PC
))
11666 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11667 inst
.instruction
|= THUMB_PP_PC_LR
;
11668 inst
.instruction
|= mask
& 0xff;
11670 else if (unified_syntax
)
11672 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11673 encode_thumb2_ldmstm (13, mask
, TRUE
);
11677 inst
.error
= _("invalid register list to push/pop instruction");
11687 Rd
= inst
.operands
[0].reg
;
11688 Rm
= inst
.operands
[1].reg
;
11690 reject_bad_reg (Rd
);
11691 reject_bad_reg (Rm
);
11693 inst
.instruction
|= Rd
<< 8;
11694 inst
.instruction
|= Rm
<< 16;
11695 inst
.instruction
|= Rm
;
11703 Rd
= inst
.operands
[0].reg
;
11704 Rm
= inst
.operands
[1].reg
;
11706 reject_bad_reg (Rd
);
11707 reject_bad_reg (Rm
);
11709 if (Rd
<= 7 && Rm
<= 7
11710 && inst
.size_req
!= 4)
11712 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11713 inst
.instruction
|= Rd
;
11714 inst
.instruction
|= Rm
<< 3;
11716 else if (unified_syntax
)
11718 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11719 inst
.instruction
|= Rd
<< 8;
11720 inst
.instruction
|= Rm
<< 16;
11721 inst
.instruction
|= Rm
;
11724 inst
.error
= BAD_HIREG
;
11732 Rd
= inst
.operands
[0].reg
;
11733 Rm
= inst
.operands
[1].reg
;
11735 reject_bad_reg (Rd
);
11736 reject_bad_reg (Rm
);
11738 inst
.instruction
|= Rd
<< 8;
11739 inst
.instruction
|= Rm
;
11747 Rd
= inst
.operands
[0].reg
;
11748 Rs
= (inst
.operands
[1].present
11749 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11750 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11752 reject_bad_reg (Rd
);
11753 reject_bad_reg (Rs
);
11754 if (inst
.operands
[2].isreg
)
11755 reject_bad_reg (inst
.operands
[2].reg
);
11757 inst
.instruction
|= Rd
<< 8;
11758 inst
.instruction
|= Rs
<< 16;
11759 if (!inst
.operands
[2].isreg
)
11761 bfd_boolean narrow
;
11763 if ((inst
.instruction
& 0x00100000) != 0)
11764 narrow
= !in_it_block ();
11766 narrow
= in_it_block ();
11768 if (Rd
> 7 || Rs
> 7)
11771 if (inst
.size_req
== 4 || !unified_syntax
)
11774 if (inst
.reloc
.exp
.X_op
!= O_constant
11775 || inst
.reloc
.exp
.X_add_number
!= 0)
11778 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11779 relaxation, but it doesn't seem worth the hassle. */
11782 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11783 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11784 inst
.instruction
|= Rs
<< 3;
11785 inst
.instruction
|= Rd
;
11789 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11790 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11794 encode_thumb32_shifted_operand (2);
11800 if (warn_on_deprecated
11801 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11802 as_warn (_("setend use is deprecated for ARMv8"));
11804 set_it_insn_type (OUTSIDE_IT_INSN
);
11805 if (inst
.operands
[0].imm
)
11806 inst
.instruction
|= 0x8;
11812 if (!inst
.operands
[1].present
)
11813 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11815 if (unified_syntax
)
11817 bfd_boolean narrow
;
11820 switch (inst
.instruction
)
11823 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11825 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11827 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11829 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11833 if (THUMB_SETS_FLAGS (inst
.instruction
))
11834 narrow
= !in_it_block ();
11836 narrow
= in_it_block ();
11837 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11839 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11841 if (inst
.operands
[2].isreg
11842 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11843 || inst
.operands
[2].reg
> 7))
11845 if (inst
.size_req
== 4)
11848 reject_bad_reg (inst
.operands
[0].reg
);
11849 reject_bad_reg (inst
.operands
[1].reg
);
11853 if (inst
.operands
[2].isreg
)
11855 reject_bad_reg (inst
.operands
[2].reg
);
11856 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11857 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11858 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11859 inst
.instruction
|= inst
.operands
[2].reg
;
11861 /* PR 12854: Error on extraneous shifts. */
11862 constraint (inst
.operands
[2].shifted
,
11863 _("extraneous shift as part of operand to shift insn"));
11867 inst
.operands
[1].shifted
= 1;
11868 inst
.operands
[1].shift_kind
= shift_kind
;
11869 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11870 ? T_MNEM_movs
: T_MNEM_mov
);
11871 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11872 encode_thumb32_shifted_operand (1);
11873 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11874 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11879 if (inst
.operands
[2].isreg
)
11881 switch (shift_kind
)
11883 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11884 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11885 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11886 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11890 inst
.instruction
|= inst
.operands
[0].reg
;
11891 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11893 /* PR 12854: Error on extraneous shifts. */
11894 constraint (inst
.operands
[2].shifted
,
11895 _("extraneous shift as part of operand to shift insn"));
11899 switch (shift_kind
)
11901 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11902 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11903 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11906 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11907 inst
.instruction
|= inst
.operands
[0].reg
;
11908 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11914 constraint (inst
.operands
[0].reg
> 7
11915 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11916 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11918 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11920 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11921 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11922 _("source1 and dest must be same register"));
11924 switch (inst
.instruction
)
11926 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11927 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11928 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11929 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11933 inst
.instruction
|= inst
.operands
[0].reg
;
11934 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11936 /* PR 12854: Error on extraneous shifts. */
11937 constraint (inst
.operands
[2].shifted
,
11938 _("extraneous shift as part of operand to shift insn"));
11942 switch (inst
.instruction
)
11944 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11945 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11946 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11947 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11950 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11951 inst
.instruction
|= inst
.operands
[0].reg
;
11952 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11960 unsigned Rd
, Rn
, Rm
;
11962 Rd
= inst
.operands
[0].reg
;
11963 Rn
= inst
.operands
[1].reg
;
11964 Rm
= inst
.operands
[2].reg
;
11966 reject_bad_reg (Rd
);
11967 reject_bad_reg (Rn
);
11968 reject_bad_reg (Rm
);
11970 inst
.instruction
|= Rd
<< 8;
11971 inst
.instruction
|= Rn
<< 16;
11972 inst
.instruction
|= Rm
;
11978 unsigned Rd
, Rn
, Rm
;
11980 Rd
= inst
.operands
[0].reg
;
11981 Rm
= inst
.operands
[1].reg
;
11982 Rn
= inst
.operands
[2].reg
;
11984 reject_bad_reg (Rd
);
11985 reject_bad_reg (Rn
);
11986 reject_bad_reg (Rm
);
11988 inst
.instruction
|= Rd
<< 8;
11989 inst
.instruction
|= Rn
<< 16;
11990 inst
.instruction
|= Rm
;
11996 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11997 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11998 _("SMC is not permitted on this architecture"));
11999 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12000 _("expression too complex"));
12001 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12002 inst
.instruction
|= (value
& 0xf000) >> 12;
12003 inst
.instruction
|= (value
& 0x0ff0);
12004 inst
.instruction
|= (value
& 0x000f) << 16;
12010 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12012 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12013 inst
.instruction
|= (value
& 0x0fff);
12014 inst
.instruction
|= (value
& 0xf000) << 4;
12018 do_t_ssat_usat (int bias
)
12022 Rd
= inst
.operands
[0].reg
;
12023 Rn
= inst
.operands
[2].reg
;
12025 reject_bad_reg (Rd
);
12026 reject_bad_reg (Rn
);
12028 inst
.instruction
|= Rd
<< 8;
12029 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12030 inst
.instruction
|= Rn
<< 16;
12032 if (inst
.operands
[3].present
)
12034 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12036 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12038 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12039 _("expression too complex"));
12041 if (shift_amount
!= 0)
12043 constraint (shift_amount
> 31,
12044 _("shift expression is too large"));
12046 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12047 inst
.instruction
|= 0x00200000; /* sh bit. */
12049 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12050 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12058 do_t_ssat_usat (1);
12066 Rd
= inst
.operands
[0].reg
;
12067 Rn
= inst
.operands
[2].reg
;
12069 reject_bad_reg (Rd
);
12070 reject_bad_reg (Rn
);
12072 inst
.instruction
|= Rd
<< 8;
12073 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12074 inst
.instruction
|= Rn
<< 16;
12080 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12081 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12082 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12083 || inst
.operands
[2].negative
,
12086 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12088 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12089 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12090 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12091 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12097 if (!inst
.operands
[2].present
)
12098 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12100 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12101 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12102 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12105 inst
.instruction
|= inst
.operands
[0].reg
;
12106 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12107 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12108 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12114 unsigned Rd
, Rn
, Rm
;
12116 Rd
= inst
.operands
[0].reg
;
12117 Rn
= inst
.operands
[1].reg
;
12118 Rm
= inst
.operands
[2].reg
;
12120 reject_bad_reg (Rd
);
12121 reject_bad_reg (Rn
);
12122 reject_bad_reg (Rm
);
12124 inst
.instruction
|= Rd
<< 8;
12125 inst
.instruction
|= Rn
<< 16;
12126 inst
.instruction
|= Rm
;
12127 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12135 Rd
= inst
.operands
[0].reg
;
12136 Rm
= inst
.operands
[1].reg
;
12138 reject_bad_reg (Rd
);
12139 reject_bad_reg (Rm
);
12141 if (inst
.instruction
<= 0xffff
12142 && inst
.size_req
!= 4
12143 && Rd
<= 7 && Rm
<= 7
12144 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12146 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12147 inst
.instruction
|= Rd
;
12148 inst
.instruction
|= Rm
<< 3;
12150 else if (unified_syntax
)
12152 if (inst
.instruction
<= 0xffff)
12153 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12154 inst
.instruction
|= Rd
<< 8;
12155 inst
.instruction
|= Rm
;
12156 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12160 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12161 _("Thumb encoding does not support rotation"));
12162 constraint (1, BAD_HIREG
);
12169 /* We have to do the following check manually as ARM_EXT_OS only applies
12171 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12173 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12174 /* This only applies to the v6m howver, not later architectures. */
12175 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12176 as_bad (_("SVC is not permitted on this architecture"));
12177 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12180 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12189 half
= (inst
.instruction
& 0x10) != 0;
12190 set_it_insn_type_last ();
12191 constraint (inst
.operands
[0].immisreg
,
12192 _("instruction requires register index"));
12194 Rn
= inst
.operands
[0].reg
;
12195 Rm
= inst
.operands
[0].imm
;
12197 constraint (Rn
== REG_SP
, BAD_SP
);
12198 reject_bad_reg (Rm
);
12200 constraint (!half
&& inst
.operands
[0].shifted
,
12201 _("instruction does not allow shifted index"));
12202 inst
.instruction
|= (Rn
<< 16) | Rm
;
12208 do_t_ssat_usat (0);
12216 Rd
= inst
.operands
[0].reg
;
12217 Rn
= inst
.operands
[2].reg
;
12219 reject_bad_reg (Rd
);
12220 reject_bad_reg (Rn
);
12222 inst
.instruction
|= Rd
<< 8;
12223 inst
.instruction
|= inst
.operands
[1].imm
;
12224 inst
.instruction
|= Rn
<< 16;
12227 /* Neon instruction encoder helpers. */
12229 /* Encodings for the different types for various Neon opcodes. */
12231 /* An "invalid" code for the following tables. */
12234 struct neon_tab_entry
12237 unsigned float_or_poly
;
12238 unsigned scalar_or_imm
;
12241 /* Map overloaded Neon opcodes to their respective encodings. */
12242 #define NEON_ENC_TAB \
12243 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12244 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12245 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12246 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12247 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12248 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12249 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12250 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12251 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12252 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12253 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12254 /* Register variants of the following two instructions are encoded as
12255 vcge / vcgt with the operands reversed. */ \
12256 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12257 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12258 X(vfma, N_INV, 0x0000c10, N_INV), \
12259 X(vfms, N_INV, 0x0200c10, N_INV), \
12260 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12261 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12262 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12263 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12264 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12265 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12266 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12267 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12268 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12269 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12270 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12271 X(vshl, 0x0000400, N_INV, 0x0800510), \
12272 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12273 X(vand, 0x0000110, N_INV, 0x0800030), \
12274 X(vbic, 0x0100110, N_INV, 0x0800030), \
12275 X(veor, 0x1000110, N_INV, N_INV), \
12276 X(vorn, 0x0300110, N_INV, 0x0800010), \
12277 X(vorr, 0x0200110, N_INV, 0x0800010), \
12278 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12279 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12280 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12281 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12282 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12283 X(vst1, 0x0000000, 0x0800000, N_INV), \
12284 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12285 X(vst2, 0x0000100, 0x0800100, N_INV), \
12286 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12287 X(vst3, 0x0000200, 0x0800200, N_INV), \
12288 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12289 X(vst4, 0x0000300, 0x0800300, N_INV), \
12290 X(vmovn, 0x1b20200, N_INV, N_INV), \
12291 X(vtrn, 0x1b20080, N_INV, N_INV), \
12292 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12293 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12294 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12295 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12296 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12297 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12298 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12299 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12300 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12301 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12302 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12306 #define X(OPC,I,F,S) N_MNEM_##OPC
12311 static const struct neon_tab_entry neon_enc_tab
[] =
12313 #define X(OPC,I,F,S) { (I), (F), (S) }
12318 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12319 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12320 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12321 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12322 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12323 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12324 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12325 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12326 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12327 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12328 #define NEON_ENC_SINGLE_(X) \
12329 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12330 #define NEON_ENC_DOUBLE_(X) \
12331 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12333 #define NEON_ENCODE(type, inst) \
12336 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12337 inst.is_neon = 1; \
12341 #define check_neon_suffixes \
12344 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12346 as_bad (_("invalid neon suffix for non neon instruction")); \
12352 /* Define shapes for instruction operands. The following mnemonic characters
12353 are used in this table:
12355 F - VFP S<n> register
12356 D - Neon D<n> register
12357 Q - Neon Q<n> register
12361 L - D<n> register list
12363 This table is used to generate various data:
12364 - enumerations of the form NS_DDR to be used as arguments to
12366 - a table classifying shapes into single, double, quad, mixed.
12367 - a table used to drive neon_select_shape. */
12369 #define NEON_SHAPE_DEF \
12370 X(3, (D, D, D), DOUBLE), \
12371 X(3, (Q, Q, Q), QUAD), \
12372 X(3, (D, D, I), DOUBLE), \
12373 X(3, (Q, Q, I), QUAD), \
12374 X(3, (D, D, S), DOUBLE), \
12375 X(3, (Q, Q, S), QUAD), \
12376 X(2, (D, D), DOUBLE), \
12377 X(2, (Q, Q), QUAD), \
12378 X(2, (D, S), DOUBLE), \
12379 X(2, (Q, S), QUAD), \
12380 X(2, (D, R), DOUBLE), \
12381 X(2, (Q, R), QUAD), \
12382 X(2, (D, I), DOUBLE), \
12383 X(2, (Q, I), QUAD), \
12384 X(3, (D, L, D), DOUBLE), \
12385 X(2, (D, Q), MIXED), \
12386 X(2, (Q, D), MIXED), \
12387 X(3, (D, Q, I), MIXED), \
12388 X(3, (Q, D, I), MIXED), \
12389 X(3, (Q, D, D), MIXED), \
12390 X(3, (D, Q, Q), MIXED), \
12391 X(3, (Q, Q, D), MIXED), \
12392 X(3, (Q, D, S), MIXED), \
12393 X(3, (D, Q, S), MIXED), \
12394 X(4, (D, D, D, I), DOUBLE), \
12395 X(4, (Q, Q, Q, I), QUAD), \
12396 X(2, (F, F), SINGLE), \
12397 X(3, (F, F, F), SINGLE), \
12398 X(2, (F, I), SINGLE), \
12399 X(2, (F, D), MIXED), \
12400 X(2, (D, F), MIXED), \
12401 X(3, (F, F, I), MIXED), \
12402 X(4, (R, R, F, F), SINGLE), \
12403 X(4, (F, F, R, R), SINGLE), \
12404 X(3, (D, R, R), DOUBLE), \
12405 X(3, (R, R, D), DOUBLE), \
12406 X(2, (S, R), SINGLE), \
12407 X(2, (R, S), SINGLE), \
12408 X(2, (F, R), SINGLE), \
12409 X(2, (R, F), SINGLE)
12411 #define S2(A,B) NS_##A##B
12412 #define S3(A,B,C) NS_##A##B##C
12413 #define S4(A,B,C,D) NS_##A##B##C##D
12415 #define X(N, L, C) S##N L
12428 enum neon_shape_class
12436 #define X(N, L, C) SC_##C
12438 static enum neon_shape_class neon_shape_class
[] =
12456 /* Register widths of above. */
12457 static unsigned neon_shape_el_size
[] =
12468 struct neon_shape_info
12471 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12474 #define S2(A,B) { SE_##A, SE_##B }
12475 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12476 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12478 #define X(N, L, C) { N, S##N L }
12480 static struct neon_shape_info neon_shape_tab
[] =
12490 /* Bit masks used in type checking given instructions.
12491 'N_EQK' means the type must be the same as (or based on in some way) the key
12492 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12493 set, various other bits can be set as well in order to modify the meaning of
12494 the type constraint. */
12496 enum neon_type_mask
12519 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12520 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12521 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12522 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12523 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12524 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12525 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12526 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12527 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12528 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12530 N_MAX_NONSPECIAL
= N_F64
12533 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12535 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12536 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12537 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12538 #define N_SUF_32 (N_SU_32 | N_F32)
12539 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12540 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12542 /* Pass this as the first type argument to neon_check_type to ignore types
12544 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12546 /* Select a "shape" for the current instruction (describing register types or
12547 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12548 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12549 function of operand parsing, so this function doesn't need to be called.
12550 Shapes should be listed in order of decreasing length. */
12552 static enum neon_shape
12553 neon_select_shape (enum neon_shape shape
, ...)
12556 enum neon_shape first_shape
= shape
;
12558 /* Fix missing optional operands. FIXME: we don't know at this point how
12559 many arguments we should have, so this makes the assumption that we have
12560 > 1. This is true of all current Neon opcodes, I think, but may not be
12561 true in the future. */
12562 if (!inst
.operands
[1].present
)
12563 inst
.operands
[1] = inst
.operands
[0];
12565 va_start (ap
, shape
);
12567 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12572 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12574 if (!inst
.operands
[j
].present
)
12580 switch (neon_shape_tab
[shape
].el
[j
])
12583 if (!(inst
.operands
[j
].isreg
12584 && inst
.operands
[j
].isvec
12585 && inst
.operands
[j
].issingle
12586 && !inst
.operands
[j
].isquad
))
12591 if (!(inst
.operands
[j
].isreg
12592 && inst
.operands
[j
].isvec
12593 && !inst
.operands
[j
].isquad
12594 && !inst
.operands
[j
].issingle
))
12599 if (!(inst
.operands
[j
].isreg
12600 && !inst
.operands
[j
].isvec
))
12605 if (!(inst
.operands
[j
].isreg
12606 && inst
.operands
[j
].isvec
12607 && inst
.operands
[j
].isquad
12608 && !inst
.operands
[j
].issingle
))
12613 if (!(!inst
.operands
[j
].isreg
12614 && !inst
.operands
[j
].isscalar
))
12619 if (!(!inst
.operands
[j
].isreg
12620 && inst
.operands
[j
].isscalar
))
12630 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
12631 /* We've matched all the entries in the shape table, and we don't
12632 have any left over operands which have not been matched. */
12638 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12639 first_error (_("invalid instruction shape"));
12644 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12645 means the Q bit should be set). */
12648 neon_quad (enum neon_shape shape
)
12650 return neon_shape_class
[shape
] == SC_QUAD
;
12654 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12657 /* Allow modification to be made to types which are constrained to be
12658 based on the key element, based on bits set alongside N_EQK. */
12659 if ((typebits
& N_EQK
) != 0)
12661 if ((typebits
& N_HLF
) != 0)
12663 else if ((typebits
& N_DBL
) != 0)
12665 if ((typebits
& N_SGN
) != 0)
12666 *g_type
= NT_signed
;
12667 else if ((typebits
& N_UNS
) != 0)
12668 *g_type
= NT_unsigned
;
12669 else if ((typebits
& N_INT
) != 0)
12670 *g_type
= NT_integer
;
12671 else if ((typebits
& N_FLT
) != 0)
12672 *g_type
= NT_float
;
12673 else if ((typebits
& N_SIZ
) != 0)
12674 *g_type
= NT_untyped
;
12678 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12679 operand type, i.e. the single type specified in a Neon instruction when it
12680 is the only one given. */
12682 static struct neon_type_el
12683 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12685 struct neon_type_el dest
= *key
;
12687 gas_assert ((thisarg
& N_EQK
) != 0);
12689 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12694 /* Convert Neon type and size into compact bitmask representation. */
12696 static enum neon_type_mask
12697 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12704 case 8: return N_8
;
12705 case 16: return N_16
;
12706 case 32: return N_32
;
12707 case 64: return N_64
;
12715 case 8: return N_I8
;
12716 case 16: return N_I16
;
12717 case 32: return N_I32
;
12718 case 64: return N_I64
;
12726 case 16: return N_F16
;
12727 case 32: return N_F32
;
12728 case 64: return N_F64
;
12736 case 8: return N_P8
;
12737 case 16: return N_P16
;
12745 case 8: return N_S8
;
12746 case 16: return N_S16
;
12747 case 32: return N_S32
;
12748 case 64: return N_S64
;
12756 case 8: return N_U8
;
12757 case 16: return N_U16
;
12758 case 32: return N_U32
;
12759 case 64: return N_U64
;
12770 /* Convert compact Neon bitmask type representation to a type and size. Only
12771 handles the case where a single bit is set in the mask. */
12774 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12775 enum neon_type_mask mask
)
12777 if ((mask
& N_EQK
) != 0)
12780 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12782 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12784 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12786 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12791 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12793 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12794 *type
= NT_unsigned
;
12795 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12796 *type
= NT_integer
;
12797 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12798 *type
= NT_untyped
;
12799 else if ((mask
& (N_P8
| N_P16
)) != 0)
12801 else if ((mask
& (N_F32
| N_F64
)) != 0)
12809 /* Modify a bitmask of allowed types. This is only needed for type
12813 modify_types_allowed (unsigned allowed
, unsigned mods
)
12816 enum neon_el_type type
;
12822 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12824 if (el_type_of_type_chk (&type
, &size
,
12825 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12827 neon_modify_type_size (mods
, &type
, &size
);
12828 destmask
|= type_chk_of_el_type (type
, size
);
12835 /* Check type and return type classification.
12836 The manual states (paraphrase): If one datatype is given, it indicates the
12838 - the second operand, if there is one
12839 - the operand, if there is no second operand
12840 - the result, if there are no operands.
12841 This isn't quite good enough though, so we use a concept of a "key" datatype
12842 which is set on a per-instruction basis, which is the one which matters when
12843 only one data type is written.
12844 Note: this function has side-effects (e.g. filling in missing operands). All
12845 Neon instructions should call it before performing bit encoding. */
12847 static struct neon_type_el
12848 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12851 unsigned i
, pass
, key_el
= 0;
12852 unsigned types
[NEON_MAX_TYPE_ELS
];
12853 enum neon_el_type k_type
= NT_invtype
;
12854 unsigned k_size
= -1u;
12855 struct neon_type_el badtype
= {NT_invtype
, -1};
12856 unsigned key_allowed
= 0;
12858 /* Optional registers in Neon instructions are always (not) in operand 1.
12859 Fill in the missing operand here, if it was omitted. */
12860 if (els
> 1 && !inst
.operands
[1].present
)
12861 inst
.operands
[1] = inst
.operands
[0];
12863 /* Suck up all the varargs. */
12865 for (i
= 0; i
< els
; i
++)
12867 unsigned thisarg
= va_arg (ap
, unsigned);
12868 if (thisarg
== N_IGNORE_TYPE
)
12873 types
[i
] = thisarg
;
12874 if ((thisarg
& N_KEY
) != 0)
12879 if (inst
.vectype
.elems
> 0)
12880 for (i
= 0; i
< els
; i
++)
12881 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12883 first_error (_("types specified in both the mnemonic and operands"));
12887 /* Duplicate inst.vectype elements here as necessary.
12888 FIXME: No idea if this is exactly the same as the ARM assembler,
12889 particularly when an insn takes one register and one non-register
12891 if (inst
.vectype
.elems
== 1 && els
> 1)
12894 inst
.vectype
.elems
= els
;
12895 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12896 for (j
= 0; j
< els
; j
++)
12898 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12901 else if (inst
.vectype
.elems
== 0 && els
> 0)
12904 /* No types were given after the mnemonic, so look for types specified
12905 after each operand. We allow some flexibility here; as long as the
12906 "key" operand has a type, we can infer the others. */
12907 for (j
= 0; j
< els
; j
++)
12908 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12909 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12911 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12913 for (j
= 0; j
< els
; j
++)
12914 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12915 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12920 first_error (_("operand types can't be inferred"));
12924 else if (inst
.vectype
.elems
!= els
)
12926 first_error (_("type specifier has the wrong number of parts"));
12930 for (pass
= 0; pass
< 2; pass
++)
12932 for (i
= 0; i
< els
; i
++)
12934 unsigned thisarg
= types
[i
];
12935 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12936 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12937 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12938 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12940 /* Decay more-specific signed & unsigned types to sign-insensitive
12941 integer types if sign-specific variants are unavailable. */
12942 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12943 && (types_allowed
& N_SU_ALL
) == 0)
12944 g_type
= NT_integer
;
12946 /* If only untyped args are allowed, decay any more specific types to
12947 them. Some instructions only care about signs for some element
12948 sizes, so handle that properly. */
12949 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12950 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12951 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12952 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12953 g_type
= NT_untyped
;
12957 if ((thisarg
& N_KEY
) != 0)
12961 key_allowed
= thisarg
& ~N_KEY
;
12966 if ((thisarg
& N_VFP
) != 0)
12968 enum neon_shape_el regshape
;
12969 unsigned regwidth
, match
;
12971 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12974 first_error (_("invalid instruction shape"));
12977 regshape
= neon_shape_tab
[ns
].el
[i
];
12978 regwidth
= neon_shape_el_size
[regshape
];
12980 /* In VFP mode, operands must match register widths. If we
12981 have a key operand, use its width, else use the width of
12982 the current operand. */
12988 if (regwidth
!= match
)
12990 first_error (_("operand size must match register width"));
12995 if ((thisarg
& N_EQK
) == 0)
12997 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12999 if ((given_type
& types_allowed
) == 0)
13001 first_error (_("bad type in Neon instruction"));
13007 enum neon_el_type mod_k_type
= k_type
;
13008 unsigned mod_k_size
= k_size
;
13009 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13010 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13012 first_error (_("inconsistent types in Neon instruction"));
13020 return inst
.vectype
.el
[key_el
];
13023 /* Neon-style VFP instruction forwarding. */
13025 /* Thumb VFP instructions have 0xE in the condition field. */
13028 do_vfp_cond_or_thumb (void)
13033 inst
.instruction
|= 0xe0000000;
13035 inst
.instruction
|= inst
.cond
<< 28;
13038 /* Look up and encode a simple mnemonic, for use as a helper function for the
13039 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13040 etc. It is assumed that operand parsing has already been done, and that the
13041 operands are in the form expected by the given opcode (this isn't necessarily
13042 the same as the form in which they were parsed, hence some massaging must
13043 take place before this function is called).
13044 Checks current arch version against that in the looked-up opcode. */
13047 do_vfp_nsyn_opcode (const char *opname
)
13049 const struct asm_opcode
*opcode
;
13051 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13056 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13057 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13064 inst
.instruction
= opcode
->tvalue
;
13065 opcode
->tencode ();
13069 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13070 opcode
->aencode ();
13075 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13077 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13082 do_vfp_nsyn_opcode ("fadds");
13084 do_vfp_nsyn_opcode ("fsubs");
13089 do_vfp_nsyn_opcode ("faddd");
13091 do_vfp_nsyn_opcode ("fsubd");
13095 /* Check operand types to see if this is a VFP instruction, and if so call
13099 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13101 enum neon_shape rs
;
13102 struct neon_type_el et
;
13107 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13108 et
= neon_check_type (2, rs
,
13109 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13113 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13114 et
= neon_check_type (3, rs
,
13115 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13122 if (et
.type
!= NT_invtype
)
13133 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13135 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13140 do_vfp_nsyn_opcode ("fmacs");
13142 do_vfp_nsyn_opcode ("fnmacs");
13147 do_vfp_nsyn_opcode ("fmacd");
13149 do_vfp_nsyn_opcode ("fnmacd");
13154 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13156 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13161 do_vfp_nsyn_opcode ("ffmas");
13163 do_vfp_nsyn_opcode ("ffnmas");
13168 do_vfp_nsyn_opcode ("ffmad");
13170 do_vfp_nsyn_opcode ("ffnmad");
13175 do_vfp_nsyn_mul (enum neon_shape rs
)
13178 do_vfp_nsyn_opcode ("fmuls");
13180 do_vfp_nsyn_opcode ("fmuld");
13184 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13186 int is_neg
= (inst
.instruction
& 0x80) != 0;
13187 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13192 do_vfp_nsyn_opcode ("fnegs");
13194 do_vfp_nsyn_opcode ("fabss");
13199 do_vfp_nsyn_opcode ("fnegd");
13201 do_vfp_nsyn_opcode ("fabsd");
13205 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13206 insns belong to Neon, and are handled elsewhere. */
13209 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13211 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13215 do_vfp_nsyn_opcode ("fldmdbs");
13217 do_vfp_nsyn_opcode ("fldmias");
13222 do_vfp_nsyn_opcode ("fstmdbs");
13224 do_vfp_nsyn_opcode ("fstmias");
13229 do_vfp_nsyn_sqrt (void)
13231 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13232 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13235 do_vfp_nsyn_opcode ("fsqrts");
13237 do_vfp_nsyn_opcode ("fsqrtd");
13241 do_vfp_nsyn_div (void)
13243 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13244 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13245 N_F32
| N_F64
| N_KEY
| N_VFP
);
13248 do_vfp_nsyn_opcode ("fdivs");
13250 do_vfp_nsyn_opcode ("fdivd");
13254 do_vfp_nsyn_nmul (void)
13256 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13257 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13258 N_F32
| N_F64
| N_KEY
| N_VFP
);
13262 NEON_ENCODE (SINGLE
, inst
);
13263 do_vfp_sp_dyadic ();
13267 NEON_ENCODE (DOUBLE
, inst
);
13268 do_vfp_dp_rd_rn_rm ();
13270 do_vfp_cond_or_thumb ();
13274 do_vfp_nsyn_cmp (void)
13276 if (inst
.operands
[1].isreg
)
13278 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13279 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13283 NEON_ENCODE (SINGLE
, inst
);
13284 do_vfp_sp_monadic ();
13288 NEON_ENCODE (DOUBLE
, inst
);
13289 do_vfp_dp_rd_rm ();
13294 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13295 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13297 switch (inst
.instruction
& 0x0fffffff)
13300 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13303 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13311 NEON_ENCODE (SINGLE
, inst
);
13312 do_vfp_sp_compare_z ();
13316 NEON_ENCODE (DOUBLE
, inst
);
13320 do_vfp_cond_or_thumb ();
13324 nsyn_insert_sp (void)
13326 inst
.operands
[1] = inst
.operands
[0];
13327 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13328 inst
.operands
[0].reg
= REG_SP
;
13329 inst
.operands
[0].isreg
= 1;
13330 inst
.operands
[0].writeback
= 1;
13331 inst
.operands
[0].present
= 1;
13335 do_vfp_nsyn_push (void)
13338 if (inst
.operands
[1].issingle
)
13339 do_vfp_nsyn_opcode ("fstmdbs");
13341 do_vfp_nsyn_opcode ("fstmdbd");
13345 do_vfp_nsyn_pop (void)
13348 if (inst
.operands
[1].issingle
)
13349 do_vfp_nsyn_opcode ("fldmias");
13351 do_vfp_nsyn_opcode ("fldmiad");
13354 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13355 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13358 neon_dp_fixup (struct arm_it
* insn
)
13360 unsigned int i
= insn
->instruction
;
13365 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13376 insn
->instruction
= i
;
13379 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13383 neon_logbits (unsigned x
)
13385 return ffs (x
) - 4;
13388 #define LOW4(R) ((R) & 0xf)
13389 #define HI1(R) (((R) >> 4) & 1)
13391 /* Encode insns with bit pattern:
13393 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13394 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13396 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13397 different meaning for some instruction. */
13400 neon_three_same (int isquad
, int ubit
, int size
)
13402 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13403 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13404 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13405 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13406 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13407 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13408 inst
.instruction
|= (isquad
!= 0) << 6;
13409 inst
.instruction
|= (ubit
!= 0) << 24;
13411 inst
.instruction
|= neon_logbits (size
) << 20;
13413 neon_dp_fixup (&inst
);
13416 /* Encode instructions of the form:
13418 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13419 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13421 Don't write size if SIZE == -1. */
13424 neon_two_same (int qbit
, int ubit
, int size
)
13426 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13427 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13428 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13429 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13430 inst
.instruction
|= (qbit
!= 0) << 6;
13431 inst
.instruction
|= (ubit
!= 0) << 24;
13434 inst
.instruction
|= neon_logbits (size
) << 18;
13436 neon_dp_fixup (&inst
);
13439 /* Neon instruction encoders, in approximate order of appearance. */
13442 do_neon_dyadic_i_su (void)
13444 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13445 struct neon_type_el et
= neon_check_type (3, rs
,
13446 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13447 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13451 do_neon_dyadic_i64_su (void)
13453 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13454 struct neon_type_el et
= neon_check_type (3, rs
,
13455 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13456 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13460 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13463 unsigned size
= et
.size
>> 3;
13464 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13465 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13466 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13467 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13468 inst
.instruction
|= (isquad
!= 0) << 6;
13469 inst
.instruction
|= immbits
<< 16;
13470 inst
.instruction
|= (size
>> 3) << 7;
13471 inst
.instruction
|= (size
& 0x7) << 19;
13473 inst
.instruction
|= (uval
!= 0) << 24;
13475 neon_dp_fixup (&inst
);
13479 do_neon_shl_imm (void)
13481 if (!inst
.operands
[2].isreg
)
13483 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13484 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13485 NEON_ENCODE (IMMED
, inst
);
13486 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13490 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13491 struct neon_type_el et
= neon_check_type (3, rs
,
13492 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13495 /* VSHL/VQSHL 3-register variants have syntax such as:
13497 whereas other 3-register operations encoded by neon_three_same have
13500 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13502 tmp
= inst
.operands
[2].reg
;
13503 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13504 inst
.operands
[1].reg
= tmp
;
13505 NEON_ENCODE (INTEGER
, inst
);
13506 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13511 do_neon_qshl_imm (void)
13513 if (!inst
.operands
[2].isreg
)
13515 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13516 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13518 NEON_ENCODE (IMMED
, inst
);
13519 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13520 inst
.operands
[2].imm
);
13524 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13525 struct neon_type_el et
= neon_check_type (3, rs
,
13526 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13529 /* See note in do_neon_shl_imm. */
13530 tmp
= inst
.operands
[2].reg
;
13531 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13532 inst
.operands
[1].reg
= tmp
;
13533 NEON_ENCODE (INTEGER
, inst
);
13534 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13539 do_neon_rshl (void)
13541 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13542 struct neon_type_el et
= neon_check_type (3, rs
,
13543 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13546 tmp
= inst
.operands
[2].reg
;
13547 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13548 inst
.operands
[1].reg
= tmp
;
13549 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13553 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13555 /* Handle .I8 pseudo-instructions. */
13558 /* Unfortunately, this will make everything apart from zero out-of-range.
13559 FIXME is this the intended semantics? There doesn't seem much point in
13560 accepting .I8 if so. */
13561 immediate
|= immediate
<< 8;
13567 if (immediate
== (immediate
& 0x000000ff))
13569 *immbits
= immediate
;
13572 else if (immediate
== (immediate
& 0x0000ff00))
13574 *immbits
= immediate
>> 8;
13577 else if (immediate
== (immediate
& 0x00ff0000))
13579 *immbits
= immediate
>> 16;
13582 else if (immediate
== (immediate
& 0xff000000))
13584 *immbits
= immediate
>> 24;
13587 if ((immediate
& 0xffff) != (immediate
>> 16))
13588 goto bad_immediate
;
13589 immediate
&= 0xffff;
13592 if (immediate
== (immediate
& 0x000000ff))
13594 *immbits
= immediate
;
13597 else if (immediate
== (immediate
& 0x0000ff00))
13599 *immbits
= immediate
>> 8;
13604 first_error (_("immediate value out of range"));
13608 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13612 neon_bits_same_in_bytes (unsigned imm
)
13614 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13615 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13616 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13617 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13620 /* For immediate of above form, return 0bABCD. */
13623 neon_squash_bits (unsigned imm
)
13625 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13626 | ((imm
& 0x01000000) >> 21);
13629 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13632 neon_qfloat_bits (unsigned imm
)
13634 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13637 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13638 the instruction. *OP is passed as the initial value of the op field, and
13639 may be set to a different value depending on the constant (i.e.
13640 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13641 MVN). If the immediate looks like a repeated pattern then also
13642 try smaller element sizes. */
13645 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13646 unsigned *immbits
, int *op
, int size
,
13647 enum neon_el_type type
)
13649 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13651 if (type
== NT_float
&& !float_p
)
13654 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13656 if (size
!= 32 || *op
== 1)
13658 *immbits
= neon_qfloat_bits (immlo
);
13664 if (neon_bits_same_in_bytes (immhi
)
13665 && neon_bits_same_in_bytes (immlo
))
13669 *immbits
= (neon_squash_bits (immhi
) << 4)
13670 | neon_squash_bits (immlo
);
13675 if (immhi
!= immlo
)
13681 if (immlo
== (immlo
& 0x000000ff))
13686 else if (immlo
== (immlo
& 0x0000ff00))
13688 *immbits
= immlo
>> 8;
13691 else if (immlo
== (immlo
& 0x00ff0000))
13693 *immbits
= immlo
>> 16;
13696 else if (immlo
== (immlo
& 0xff000000))
13698 *immbits
= immlo
>> 24;
13701 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13703 *immbits
= (immlo
>> 8) & 0xff;
13706 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13708 *immbits
= (immlo
>> 16) & 0xff;
13712 if ((immlo
& 0xffff) != (immlo
>> 16))
13719 if (immlo
== (immlo
& 0x000000ff))
13724 else if (immlo
== (immlo
& 0x0000ff00))
13726 *immbits
= immlo
>> 8;
13730 if ((immlo
& 0xff) != (immlo
>> 8))
13735 if (immlo
== (immlo
& 0x000000ff))
13737 /* Don't allow MVN with 8-bit immediate. */
13747 /* Write immediate bits [7:0] to the following locations:
13749 |28/24|23 19|18 16|15 4|3 0|
13750 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13752 This function is used by VMOV/VMVN/VORR/VBIC. */
13755 neon_write_immbits (unsigned immbits
)
13757 inst
.instruction
|= immbits
& 0xf;
13758 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13759 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13762 /* Invert low-order SIZE bits of XHI:XLO. */
13765 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13767 unsigned immlo
= xlo
? *xlo
: 0;
13768 unsigned immhi
= xhi
? *xhi
: 0;
13773 immlo
= (~immlo
) & 0xff;
13777 immlo
= (~immlo
) & 0xffff;
13781 immhi
= (~immhi
) & 0xffffffff;
13782 /* fall through. */
13785 immlo
= (~immlo
) & 0xffffffff;
13800 do_neon_logic (void)
13802 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13804 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13805 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13806 /* U bit and size field were set as part of the bitmask. */
13807 NEON_ENCODE (INTEGER
, inst
);
13808 neon_three_same (neon_quad (rs
), 0, -1);
13812 const int three_ops_form
= (inst
.operands
[2].present
13813 && !inst
.operands
[2].isreg
);
13814 const int immoperand
= (three_ops_form
? 2 : 1);
13815 enum neon_shape rs
= (three_ops_form
13816 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13817 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13818 struct neon_type_el et
= neon_check_type (2, rs
,
13819 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13820 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13824 if (et
.type
== NT_invtype
)
13827 if (three_ops_form
)
13828 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13829 _("first and second operands shall be the same register"));
13831 NEON_ENCODE (IMMED
, inst
);
13833 immbits
= inst
.operands
[immoperand
].imm
;
13836 /* .i64 is a pseudo-op, so the immediate must be a repeating
13838 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13839 inst
.operands
[immoperand
].reg
: 0))
13841 /* Set immbits to an invalid constant. */
13842 immbits
= 0xdeadbeef;
13849 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13853 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13857 /* Pseudo-instruction for VBIC. */
13858 neon_invert_size (&immbits
, 0, et
.size
);
13859 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13863 /* Pseudo-instruction for VORR. */
13864 neon_invert_size (&immbits
, 0, et
.size
);
13865 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13875 inst
.instruction
|= neon_quad (rs
) << 6;
13876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13878 inst
.instruction
|= cmode
<< 8;
13879 neon_write_immbits (immbits
);
13881 neon_dp_fixup (&inst
);
13886 do_neon_bitfield (void)
13888 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13889 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13890 neon_three_same (neon_quad (rs
), 0, -1);
13894 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13897 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13898 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13900 if (et
.type
== NT_float
)
13902 NEON_ENCODE (FLOAT
, inst
);
13903 neon_three_same (neon_quad (rs
), 0, -1);
13907 NEON_ENCODE (INTEGER
, inst
);
13908 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13913 do_neon_dyadic_if_su (void)
13915 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13919 do_neon_dyadic_if_su_d (void)
13921 /* This version only allow D registers, but that constraint is enforced during
13922 operand parsing so we don't need to do anything extra here. */
13923 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13927 do_neon_dyadic_if_i_d (void)
13929 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13930 affected if we specify unsigned args. */
13931 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13934 enum vfp_or_neon_is_neon_bits
13937 NEON_CHECK_ARCH
= 2
13940 /* Call this function if an instruction which may have belonged to the VFP or
13941 Neon instruction sets, but turned out to be a Neon instruction (due to the
13942 operand types involved, etc.). We have to check and/or fix-up a couple of
13945 - Make sure the user hasn't attempted to make a Neon instruction
13947 - Alter the value in the condition code field if necessary.
13948 - Make sure that the arch supports Neon instructions.
13950 Which of these operations take place depends on bits from enum
13951 vfp_or_neon_is_neon_bits.
13953 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13954 current instruction's condition is COND_ALWAYS, the condition field is
13955 changed to inst.uncond_value. This is necessary because instructions shared
13956 between VFP and Neon may be conditional for the VFP variants only, and the
13957 unconditional Neon version must have, e.g., 0xF in the condition field. */
13960 vfp_or_neon_is_neon (unsigned check
)
13962 /* Conditions are always legal in Thumb mode (IT blocks). */
13963 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13965 if (inst
.cond
!= COND_ALWAYS
)
13967 first_error (_(BAD_COND
));
13970 if (inst
.uncond_value
!= -1)
13971 inst
.instruction
|= inst
.uncond_value
<< 28;
13974 if ((check
& NEON_CHECK_ARCH
)
13975 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13977 first_error (_(BAD_FPU
));
13985 do_neon_addsub_if_i (void)
13987 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13990 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13993 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13994 affected if we specify unsigned args. */
13995 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13998 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14000 V<op> A,B (A is operand 0, B is operand 2)
14005 so handle that case specially. */
14008 neon_exchange_operands (void)
14010 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14011 if (inst
.operands
[1].present
)
14013 /* Swap operands[1] and operands[2]. */
14014 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14015 inst
.operands
[1] = inst
.operands
[2];
14016 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14020 inst
.operands
[1] = inst
.operands
[2];
14021 inst
.operands
[2] = inst
.operands
[0];
14026 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14028 if (inst
.operands
[2].isreg
)
14031 neon_exchange_operands ();
14032 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14036 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14037 struct neon_type_el et
= neon_check_type (2, rs
,
14038 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14040 NEON_ENCODE (IMMED
, inst
);
14041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14044 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14045 inst
.instruction
|= neon_quad (rs
) << 6;
14046 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14047 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14049 neon_dp_fixup (&inst
);
14056 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14060 do_neon_cmp_inv (void)
14062 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14068 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14071 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14072 scalars, which are encoded in 5 bits, M : Rm.
14073 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14074 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14078 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14080 unsigned regno
= NEON_SCALAR_REG (scalar
);
14081 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14086 if (regno
> 7 || elno
> 3)
14088 return regno
| (elno
<< 3);
14091 if (regno
> 15 || elno
> 1)
14093 return regno
| (elno
<< 4);
14097 first_error (_("scalar out of range for multiply instruction"));
14103 /* Encode multiply / multiply-accumulate scalar instructions. */
14106 neon_mul_mac (struct neon_type_el et
, int ubit
)
14110 /* Give a more helpful error message if we have an invalid type. */
14111 if (et
.type
== NT_invtype
)
14114 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14115 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14116 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14117 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14118 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14119 inst
.instruction
|= LOW4 (scalar
);
14120 inst
.instruction
|= HI1 (scalar
) << 5;
14121 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14122 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14123 inst
.instruction
|= (ubit
!= 0) << 24;
14125 neon_dp_fixup (&inst
);
14129 do_neon_mac_maybe_scalar (void)
14131 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14134 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14137 if (inst
.operands
[2].isscalar
)
14139 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14140 struct neon_type_el et
= neon_check_type (3, rs
,
14141 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14142 NEON_ENCODE (SCALAR
, inst
);
14143 neon_mul_mac (et
, neon_quad (rs
));
14147 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14148 affected if we specify unsigned args. */
14149 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14154 do_neon_fmac (void)
14156 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14159 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14162 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14168 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14169 struct neon_type_el et
= neon_check_type (3, rs
,
14170 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14171 neon_three_same (neon_quad (rs
), 0, et
.size
);
14174 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14175 same types as the MAC equivalents. The polynomial type for this instruction
14176 is encoded the same as the integer type. */
14181 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14184 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14187 if (inst
.operands
[2].isscalar
)
14188 do_neon_mac_maybe_scalar ();
14190 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14194 do_neon_qdmulh (void)
14196 if (inst
.operands
[2].isscalar
)
14198 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14199 struct neon_type_el et
= neon_check_type (3, rs
,
14200 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14201 NEON_ENCODE (SCALAR
, inst
);
14202 neon_mul_mac (et
, neon_quad (rs
));
14206 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14207 struct neon_type_el et
= neon_check_type (3, rs
,
14208 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14209 NEON_ENCODE (INTEGER
, inst
);
14210 /* The U bit (rounding) comes from bit mask. */
14211 neon_three_same (neon_quad (rs
), 0, et
.size
);
14216 do_neon_fcmp_absolute (void)
14218 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14219 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14220 /* Size field comes from bit mask. */
14221 neon_three_same (neon_quad (rs
), 1, -1);
14225 do_neon_fcmp_absolute_inv (void)
14227 neon_exchange_operands ();
14228 do_neon_fcmp_absolute ();
14232 do_neon_step (void)
14234 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14235 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14236 neon_three_same (neon_quad (rs
), 0, -1);
14240 do_neon_abs_neg (void)
14242 enum neon_shape rs
;
14243 struct neon_type_el et
;
14245 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14248 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14251 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14252 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14255 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14257 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14258 inst
.instruction
|= neon_quad (rs
) << 6;
14259 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14260 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14262 neon_dp_fixup (&inst
);
14268 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14269 struct neon_type_el et
= neon_check_type (2, rs
,
14270 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14271 int imm
= inst
.operands
[2].imm
;
14272 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14273 _("immediate out of range for insert"));
14274 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14280 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14281 struct neon_type_el et
= neon_check_type (2, rs
,
14282 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14283 int imm
= inst
.operands
[2].imm
;
14284 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14285 _("immediate out of range for insert"));
14286 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14290 do_neon_qshlu_imm (void)
14292 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14293 struct neon_type_el et
= neon_check_type (2, rs
,
14294 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14295 int imm
= inst
.operands
[2].imm
;
14296 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14297 _("immediate out of range for shift"));
14298 /* Only encodes the 'U present' variant of the instruction.
14299 In this case, signed types have OP (bit 8) set to 0.
14300 Unsigned types have OP set to 1. */
14301 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14302 /* The rest of the bits are the same as other immediate shifts. */
14303 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14307 do_neon_qmovn (void)
14309 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14310 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14311 /* Saturating move where operands can be signed or unsigned, and the
14312 destination has the same signedness. */
14313 NEON_ENCODE (INTEGER
, inst
);
14314 if (et
.type
== NT_unsigned
)
14315 inst
.instruction
|= 0xc0;
14317 inst
.instruction
|= 0x80;
14318 neon_two_same (0, 1, et
.size
/ 2);
14322 do_neon_qmovun (void)
14324 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14325 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14326 /* Saturating move with unsigned results. Operands must be signed. */
14327 NEON_ENCODE (INTEGER
, inst
);
14328 neon_two_same (0, 1, et
.size
/ 2);
14332 do_neon_rshift_sat_narrow (void)
14334 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14335 or unsigned. If operands are unsigned, results must also be unsigned. */
14336 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14337 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14338 int imm
= inst
.operands
[2].imm
;
14339 /* This gets the bounds check, size encoding and immediate bits calculation
14343 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14344 VQMOVN.I<size> <Dd>, <Qm>. */
14347 inst
.operands
[2].present
= 0;
14348 inst
.instruction
= N_MNEM_vqmovn
;
14353 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14354 _("immediate out of range"));
14355 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14359 do_neon_rshift_sat_narrow_u (void)
14361 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14362 or unsigned. If operands are unsigned, results must also be unsigned. */
14363 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14364 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14365 int imm
= inst
.operands
[2].imm
;
14366 /* This gets the bounds check, size encoding and immediate bits calculation
14370 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14371 VQMOVUN.I<size> <Dd>, <Qm>. */
14374 inst
.operands
[2].present
= 0;
14375 inst
.instruction
= N_MNEM_vqmovun
;
14380 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14381 _("immediate out of range"));
14382 /* FIXME: The manual is kind of unclear about what value U should have in
14383 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14385 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14389 do_neon_movn (void)
14391 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14392 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14393 NEON_ENCODE (INTEGER
, inst
);
14394 neon_two_same (0, 1, et
.size
/ 2);
14398 do_neon_rshift_narrow (void)
14400 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14401 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14402 int imm
= inst
.operands
[2].imm
;
14403 /* This gets the bounds check, size encoding and immediate bits calculation
14407 /* If immediate is zero then we are a pseudo-instruction for
14408 VMOVN.I<size> <Dd>, <Qm> */
14411 inst
.operands
[2].present
= 0;
14412 inst
.instruction
= N_MNEM_vmovn
;
14417 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14418 _("immediate out of range for narrowing operation"));
14419 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14423 do_neon_shll (void)
14425 /* FIXME: Type checking when lengthening. */
14426 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14427 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14428 unsigned imm
= inst
.operands
[2].imm
;
14430 if (imm
== et
.size
)
14432 /* Maximum shift variant. */
14433 NEON_ENCODE (INTEGER
, inst
);
14434 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14435 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14436 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14437 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14438 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14440 neon_dp_fixup (&inst
);
14444 /* A more-specific type check for non-max versions. */
14445 et
= neon_check_type (2, NS_QDI
,
14446 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14447 NEON_ENCODE (IMMED
, inst
);
14448 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14452 /* Check the various types for the VCVT instruction, and return which version
14453 the current instruction is. */
14456 neon_cvt_flavour (enum neon_shape rs
)
14458 #define CVT_VAR(C,X,Y) \
14459 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14460 if (et.type != NT_invtype) \
14462 inst.error = NULL; \
14465 struct neon_type_el et
;
14466 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14467 || rs
== NS_FF
) ? N_VFP
: 0;
14468 /* The instruction versions which take an immediate take one register
14469 argument, which is extended to the width of the full register. Thus the
14470 "source" and "destination" registers must have the same width. Hack that
14471 here by making the size equal to the key (wider, in this case) operand. */
14472 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14474 CVT_VAR (0, N_S32
, N_F32
);
14475 CVT_VAR (1, N_U32
, N_F32
);
14476 CVT_VAR (2, N_F32
, N_S32
);
14477 CVT_VAR (3, N_F32
, N_U32
);
14478 /* Half-precision conversions. */
14479 CVT_VAR (4, N_F32
, N_F16
);
14480 CVT_VAR (5, N_F16
, N_F32
);
14484 /* VFP instructions. */
14485 CVT_VAR (6, N_F32
, N_F64
);
14486 CVT_VAR (7, N_F64
, N_F32
);
14487 CVT_VAR (8, N_S32
, N_F64
| key
);
14488 CVT_VAR (9, N_U32
, N_F64
| key
);
14489 CVT_VAR (10, N_F64
| key
, N_S32
);
14490 CVT_VAR (11, N_F64
| key
, N_U32
);
14491 /* VFP instructions with bitshift. */
14492 CVT_VAR (12, N_F32
| key
, N_S16
);
14493 CVT_VAR (13, N_F32
| key
, N_U16
);
14494 CVT_VAR (14, N_F64
| key
, N_S16
);
14495 CVT_VAR (15, N_F64
| key
, N_U16
);
14496 CVT_VAR (16, N_S16
, N_F32
| key
);
14497 CVT_VAR (17, N_U16
, N_F32
| key
);
14498 CVT_VAR (18, N_S16
, N_F64
| key
);
14499 CVT_VAR (19, N_U16
, N_F64
| key
);
14505 /* Neon-syntax VFP conversions. */
14508 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14510 const char *opname
= 0;
14512 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14514 /* Conversions with immediate bitshift. */
14515 const char *enc
[] =
14539 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14541 opname
= enc
[flavour
];
14542 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14543 _("operands 0 and 1 must be the same register"));
14544 inst
.operands
[1] = inst
.operands
[2];
14545 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14550 /* Conversions without bitshift. */
14551 const char *enc
[] =
14567 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14568 opname
= enc
[flavour
];
14572 do_vfp_nsyn_opcode (opname
);
14576 do_vfp_nsyn_cvtz (void)
14578 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14579 int flavour
= neon_cvt_flavour (rs
);
14580 const char *enc
[] =
14594 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14595 do_vfp_nsyn_opcode (enc
[flavour
]);
14599 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14601 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14602 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14603 int flavour
= neon_cvt_flavour (rs
);
14605 /* PR11109: Handle round-to-zero for VCVT conversions. */
14607 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14608 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14609 && (rs
== NS_FD
|| rs
== NS_FF
))
14611 do_vfp_nsyn_cvtz ();
14615 /* VFP rather than Neon conversions. */
14618 do_vfp_nsyn_cvt (rs
, flavour
);
14628 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14630 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14633 /* Fixed-point conversion with #0 immediate is encoded as an
14634 integer conversion. */
14635 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14637 immbits
= 32 - inst
.operands
[2].imm
;
14638 NEON_ENCODE (IMMED
, inst
);
14640 inst
.instruction
|= enctab
[flavour
];
14641 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14642 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14643 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14644 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14645 inst
.instruction
|= neon_quad (rs
) << 6;
14646 inst
.instruction
|= 1 << 21;
14647 inst
.instruction
|= immbits
<< 16;
14649 neon_dp_fixup (&inst
);
14657 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14659 NEON_ENCODE (INTEGER
, inst
);
14661 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14665 inst
.instruction
|= enctab
[flavour
];
14667 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14668 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14669 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14670 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14671 inst
.instruction
|= neon_quad (rs
) << 6;
14672 inst
.instruction
|= 2 << 18;
14674 neon_dp_fixup (&inst
);
14678 /* Half-precision conversions for Advanced SIMD -- neon. */
14683 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14685 as_bad (_("operand size must match register width"));
14690 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14692 as_bad (_("operand size must match register width"));
14697 inst
.instruction
= 0x3b60600;
14699 inst
.instruction
= 0x3b60700;
14701 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14702 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14703 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14704 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14705 neon_dp_fixup (&inst
);
14709 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14710 do_vfp_nsyn_cvt (rs
, flavour
);
14715 do_neon_cvtr (void)
14717 do_neon_cvt_1 (FALSE
);
14723 do_neon_cvt_1 (TRUE
);
14727 do_neon_cvtb (void)
14729 inst
.instruction
= 0xeb20a40;
14731 /* The sizes are attached to the mnemonic. */
14732 if (inst
.vectype
.el
[0].type
!= NT_invtype
14733 && inst
.vectype
.el
[0].size
== 16)
14734 inst
.instruction
|= 0x00010000;
14736 /* Programmer's syntax: the sizes are attached to the operands. */
14737 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14738 && inst
.operands
[0].vectype
.size
== 16)
14739 inst
.instruction
|= 0x00010000;
14741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14742 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14743 do_vfp_cond_or_thumb ();
14748 do_neon_cvtt (void)
14751 inst
.instruction
|= 0x80;
14755 neon_move_immediate (void)
14757 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14758 struct neon_type_el et
= neon_check_type (2, rs
,
14759 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14760 unsigned immlo
, immhi
= 0, immbits
;
14761 int op
, cmode
, float_p
;
14763 constraint (et
.type
== NT_invtype
,
14764 _("operand size must be specified for immediate VMOV"));
14766 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14767 op
= (inst
.instruction
& (1 << 5)) != 0;
14769 immlo
= inst
.operands
[1].imm
;
14770 if (inst
.operands
[1].regisimm
)
14771 immhi
= inst
.operands
[1].reg
;
14773 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14774 _("immediate has bits set outside the operand size"));
14776 float_p
= inst
.operands
[1].immisfloat
;
14778 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14779 et
.size
, et
.type
)) == FAIL
)
14781 /* Invert relevant bits only. */
14782 neon_invert_size (&immlo
, &immhi
, et
.size
);
14783 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14784 with one or the other; those cases are caught by
14785 neon_cmode_for_move_imm. */
14787 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14788 &op
, et
.size
, et
.type
)) == FAIL
)
14790 first_error (_("immediate out of range"));
14795 inst
.instruction
&= ~(1 << 5);
14796 inst
.instruction
|= op
<< 5;
14798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14800 inst
.instruction
|= neon_quad (rs
) << 6;
14801 inst
.instruction
|= cmode
<< 8;
14803 neon_write_immbits (immbits
);
14809 if (inst
.operands
[1].isreg
)
14811 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14813 NEON_ENCODE (INTEGER
, inst
);
14814 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14815 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14816 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14817 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14818 inst
.instruction
|= neon_quad (rs
) << 6;
14822 NEON_ENCODE (IMMED
, inst
);
14823 neon_move_immediate ();
14826 neon_dp_fixup (&inst
);
14829 /* Encode instructions of form:
14831 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14832 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14835 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14841 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14842 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14843 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14844 inst
.instruction
|= neon_logbits (size
) << 20;
14846 neon_dp_fixup (&inst
);
14850 do_neon_dyadic_long (void)
14852 /* FIXME: Type checking for lengthening op. */
14853 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14854 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14855 neon_mixed_length (et
, et
.size
);
14859 do_neon_abal (void)
14861 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14862 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14863 neon_mixed_length (et
, et
.size
);
14867 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14869 if (inst
.operands
[2].isscalar
)
14871 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14872 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14873 NEON_ENCODE (SCALAR
, inst
);
14874 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14878 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14879 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14880 NEON_ENCODE (INTEGER
, inst
);
14881 neon_mixed_length (et
, et
.size
);
14886 do_neon_mac_maybe_scalar_long (void)
14888 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14892 do_neon_dyadic_wide (void)
14894 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14895 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14896 neon_mixed_length (et
, et
.size
);
14900 do_neon_dyadic_narrow (void)
14902 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14903 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14904 /* Operand sign is unimportant, and the U bit is part of the opcode,
14905 so force the operand type to integer. */
14906 et
.type
= NT_integer
;
14907 neon_mixed_length (et
, et
.size
/ 2);
14911 do_neon_mul_sat_scalar_long (void)
14913 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14917 do_neon_vmull (void)
14919 if (inst
.operands
[2].isscalar
)
14920 do_neon_mac_maybe_scalar_long ();
14923 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14924 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14925 if (et
.type
== NT_poly
)
14926 NEON_ENCODE (POLY
, inst
);
14928 NEON_ENCODE (INTEGER
, inst
);
14929 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14930 zero. Should be OK as-is. */
14931 neon_mixed_length (et
, et
.size
);
14938 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14939 struct neon_type_el et
= neon_check_type (3, rs
,
14940 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14941 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14943 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14944 _("shift out of range"));
14945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14946 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14947 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14948 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14949 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14950 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14951 inst
.instruction
|= neon_quad (rs
) << 6;
14952 inst
.instruction
|= imm
<< 8;
14954 neon_dp_fixup (&inst
);
14960 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14961 struct neon_type_el et
= neon_check_type (2, rs
,
14962 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14963 unsigned op
= (inst
.instruction
>> 7) & 3;
14964 /* N (width of reversed regions) is encoded as part of the bitmask. We
14965 extract it here to check the elements to be reversed are smaller.
14966 Otherwise we'd get a reserved instruction. */
14967 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14968 gas_assert (elsize
!= 0);
14969 constraint (et
.size
>= elsize
,
14970 _("elements must be smaller than reversal region"));
14971 neon_two_same (neon_quad (rs
), 1, et
.size
);
14977 if (inst
.operands
[1].isscalar
)
14979 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14980 struct neon_type_el et
= neon_check_type (2, rs
,
14981 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14982 unsigned sizebits
= et
.size
>> 3;
14983 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14984 int logsize
= neon_logbits (et
.size
);
14985 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14987 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14990 NEON_ENCODE (SCALAR
, inst
);
14991 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14992 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14993 inst
.instruction
|= LOW4 (dm
);
14994 inst
.instruction
|= HI1 (dm
) << 5;
14995 inst
.instruction
|= neon_quad (rs
) << 6;
14996 inst
.instruction
|= x
<< 17;
14997 inst
.instruction
|= sizebits
<< 16;
14999 neon_dp_fixup (&inst
);
15003 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15004 struct neon_type_el et
= neon_check_type (2, rs
,
15005 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15006 /* Duplicate ARM register to lanes of vector. */
15007 NEON_ENCODE (ARMREG
, inst
);
15010 case 8: inst
.instruction
|= 0x400000; break;
15011 case 16: inst
.instruction
|= 0x000020; break;
15012 case 32: inst
.instruction
|= 0x000000; break;
15015 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15017 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15018 inst
.instruction
|= neon_quad (rs
) << 21;
15019 /* The encoding for this instruction is identical for the ARM and Thumb
15020 variants, except for the condition field. */
15021 do_vfp_cond_or_thumb ();
15025 /* VMOV has particularly many variations. It can be one of:
15026 0. VMOV<c><q> <Qd>, <Qm>
15027 1. VMOV<c><q> <Dd>, <Dm>
15028 (Register operations, which are VORR with Rm = Rn.)
15029 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15030 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15032 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15033 (ARM register to scalar.)
15034 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15035 (Two ARM registers to vector.)
15036 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15037 (Scalar to ARM register.)
15038 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15039 (Vector to two ARM registers.)
15040 8. VMOV.F32 <Sd>, <Sm>
15041 9. VMOV.F64 <Dd>, <Dm>
15042 (VFP register moves.)
15043 10. VMOV.F32 <Sd>, #imm
15044 11. VMOV.F64 <Dd>, #imm
15045 (VFP float immediate load.)
15046 12. VMOV <Rd>, <Sm>
15047 (VFP single to ARM reg.)
15048 13. VMOV <Sd>, <Rm>
15049 (ARM reg to VFP single.)
15050 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15051 (Two ARM regs to two VFP singles.)
15052 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15053 (Two VFP singles to two ARM regs.)
15055 These cases can be disambiguated using neon_select_shape, except cases 1/9
15056 and 3/11 which depend on the operand type too.
15058 All the encoded bits are hardcoded by this function.
15060 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15061 Cases 5, 7 may be used with VFPv2 and above.
15063 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15064 can specify a type where it doesn't make sense to, and is ignored). */
15069 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15070 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15072 struct neon_type_el et
;
15073 const char *ldconst
= 0;
15077 case NS_DD
: /* case 1/9. */
15078 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15079 /* It is not an error here if no type is given. */
15081 if (et
.type
== NT_float
&& et
.size
== 64)
15083 do_vfp_nsyn_opcode ("fcpyd");
15086 /* fall through. */
15088 case NS_QQ
: /* case 0/1. */
15090 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15092 /* The architecture manual I have doesn't explicitly state which
15093 value the U bit should have for register->register moves, but
15094 the equivalent VORR instruction has U = 0, so do that. */
15095 inst
.instruction
= 0x0200110;
15096 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15097 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15098 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15099 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15100 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15101 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15102 inst
.instruction
|= neon_quad (rs
) << 6;
15104 neon_dp_fixup (&inst
);
15108 case NS_DI
: /* case 3/11. */
15109 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15111 if (et
.type
== NT_float
&& et
.size
== 64)
15113 /* case 11 (fconstd). */
15114 ldconst
= "fconstd";
15115 goto encode_fconstd
;
15117 /* fall through. */
15119 case NS_QI
: /* case 2/3. */
15120 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15122 inst
.instruction
= 0x0800010;
15123 neon_move_immediate ();
15124 neon_dp_fixup (&inst
);
15127 case NS_SR
: /* case 4. */
15129 unsigned bcdebits
= 0;
15131 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15132 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15134 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15135 logsize
= neon_logbits (et
.size
);
15137 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15140 && et
.size
!= 32, _(BAD_FPU
));
15141 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15142 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15146 case 8: bcdebits
= 0x8; break;
15147 case 16: bcdebits
= 0x1; break;
15148 case 32: bcdebits
= 0x0; break;
15152 bcdebits
|= x
<< logsize
;
15154 inst
.instruction
= 0xe000b10;
15155 do_vfp_cond_or_thumb ();
15156 inst
.instruction
|= LOW4 (dn
) << 16;
15157 inst
.instruction
|= HI1 (dn
) << 7;
15158 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15159 inst
.instruction
|= (bcdebits
& 3) << 5;
15160 inst
.instruction
|= (bcdebits
>> 2) << 21;
15164 case NS_DRR
: /* case 5 (fmdrr). */
15165 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15168 inst
.instruction
= 0xc400b10;
15169 do_vfp_cond_or_thumb ();
15170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15172 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15173 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15176 case NS_RS
: /* case 6. */
15179 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15180 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15181 unsigned abcdebits
= 0;
15183 et
= neon_check_type (2, NS_NULL
,
15184 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15185 logsize
= neon_logbits (et
.size
);
15187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15189 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15190 && et
.size
!= 32, _(BAD_FPU
));
15191 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15192 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15196 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15197 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15198 case 32: abcdebits
= 0x00; break;
15202 abcdebits
|= x
<< logsize
;
15203 inst
.instruction
= 0xe100b10;
15204 do_vfp_cond_or_thumb ();
15205 inst
.instruction
|= LOW4 (dn
) << 16;
15206 inst
.instruction
|= HI1 (dn
) << 7;
15207 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15208 inst
.instruction
|= (abcdebits
& 3) << 5;
15209 inst
.instruction
|= (abcdebits
>> 2) << 21;
15213 case NS_RRD
: /* case 7 (fmrrd). */
15214 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15217 inst
.instruction
= 0xc500b10;
15218 do_vfp_cond_or_thumb ();
15219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15220 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15221 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15222 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15225 case NS_FF
: /* case 8 (fcpys). */
15226 do_vfp_nsyn_opcode ("fcpys");
15229 case NS_FI
: /* case 10 (fconsts). */
15230 ldconst
= "fconsts";
15232 if (is_quarter_float (inst
.operands
[1].imm
))
15234 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15235 do_vfp_nsyn_opcode (ldconst
);
15238 first_error (_("immediate out of range"));
15241 case NS_RF
: /* case 12 (fmrs). */
15242 do_vfp_nsyn_opcode ("fmrs");
15245 case NS_FR
: /* case 13 (fmsr). */
15246 do_vfp_nsyn_opcode ("fmsr");
15249 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15250 (one of which is a list), but we have parsed four. Do some fiddling to
15251 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15253 case NS_RRFF
: /* case 14 (fmrrs). */
15254 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15255 _("VFP registers must be adjacent"));
15256 inst
.operands
[2].imm
= 2;
15257 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15258 do_vfp_nsyn_opcode ("fmrrs");
15261 case NS_FFRR
: /* case 15 (fmsrr). */
15262 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15263 _("VFP registers must be adjacent"));
15264 inst
.operands
[1] = inst
.operands
[2];
15265 inst
.operands
[2] = inst
.operands
[3];
15266 inst
.operands
[0].imm
= 2;
15267 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15268 do_vfp_nsyn_opcode ("fmsrr");
15277 do_neon_rshift_round_imm (void)
15279 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15280 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15281 int imm
= inst
.operands
[2].imm
;
15283 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15286 inst
.operands
[2].present
= 0;
15291 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15292 _("immediate out of range for shift"));
15293 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15298 do_neon_movl (void)
15300 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15301 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15302 unsigned sizebits
= et
.size
>> 3;
15303 inst
.instruction
|= sizebits
<< 19;
15304 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15310 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15311 struct neon_type_el et
= neon_check_type (2, rs
,
15312 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15313 NEON_ENCODE (INTEGER
, inst
);
15314 neon_two_same (neon_quad (rs
), 1, et
.size
);
15318 do_neon_zip_uzp (void)
15320 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15321 struct neon_type_el et
= neon_check_type (2, rs
,
15322 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15323 if (rs
== NS_DD
&& et
.size
== 32)
15325 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15326 inst
.instruction
= N_MNEM_vtrn
;
15330 neon_two_same (neon_quad (rs
), 1, et
.size
);
15334 do_neon_sat_abs_neg (void)
15336 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15337 struct neon_type_el et
= neon_check_type (2, rs
,
15338 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15339 neon_two_same (neon_quad (rs
), 1, et
.size
);
15343 do_neon_pair_long (void)
15345 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15346 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15347 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15348 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15349 neon_two_same (neon_quad (rs
), 1, et
.size
);
15353 do_neon_recip_est (void)
15355 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15356 struct neon_type_el et
= neon_check_type (2, rs
,
15357 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15358 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15359 neon_two_same (neon_quad (rs
), 1, et
.size
);
15365 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15366 struct neon_type_el et
= neon_check_type (2, rs
,
15367 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15368 neon_two_same (neon_quad (rs
), 1, et
.size
);
15374 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15375 struct neon_type_el et
= neon_check_type (2, rs
,
15376 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15377 neon_two_same (neon_quad (rs
), 1, et
.size
);
15383 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15384 struct neon_type_el et
= neon_check_type (2, rs
,
15385 N_EQK
| N_INT
, N_8
| N_KEY
);
15386 neon_two_same (neon_quad (rs
), 1, et
.size
);
15392 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15393 neon_two_same (neon_quad (rs
), 1, -1);
15397 do_neon_tbl_tbx (void)
15399 unsigned listlenbits
;
15400 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15402 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15404 first_error (_("bad list length for table lookup"));
15408 listlenbits
= inst
.operands
[1].imm
- 1;
15409 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15410 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15411 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15412 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15413 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15414 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15415 inst
.instruction
|= listlenbits
<< 8;
15417 neon_dp_fixup (&inst
);
15421 do_neon_ldm_stm (void)
15423 /* P, U and L bits are part of bitmask. */
15424 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15425 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15427 if (inst
.operands
[1].issingle
)
15429 do_vfp_nsyn_ldm_stm (is_dbmode
);
15433 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15434 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15436 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15437 _("register list must contain at least 1 and at most 16 "
15440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15441 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15442 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15443 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15445 inst
.instruction
|= offsetbits
;
15447 do_vfp_cond_or_thumb ();
15451 do_neon_ldr_str (void)
15453 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15455 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15456 And is UNPREDICTABLE in thumb mode. */
15458 && inst
.operands
[1].reg
== REG_PC
15459 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15461 if (!thumb_mode
&& warn_on_deprecated
)
15462 as_warn (_("Use of PC here is deprecated"));
15464 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15467 if (inst
.operands
[0].issingle
)
15470 do_vfp_nsyn_opcode ("flds");
15472 do_vfp_nsyn_opcode ("fsts");
15477 do_vfp_nsyn_opcode ("fldd");
15479 do_vfp_nsyn_opcode ("fstd");
15483 /* "interleave" version also handles non-interleaving register VLD1/VST1
15487 do_neon_ld_st_interleave (void)
15489 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15490 N_8
| N_16
| N_32
| N_64
);
15491 unsigned alignbits
= 0;
15493 /* The bits in this table go:
15494 0: register stride of one (0) or two (1)
15495 1,2: register list length, minus one (1, 2, 3, 4).
15496 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15497 We use -1 for invalid entries. */
15498 const int typetable
[] =
15500 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15501 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15502 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15503 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15507 if (et
.type
== NT_invtype
)
15510 if (inst
.operands
[1].immisalign
)
15511 switch (inst
.operands
[1].imm
>> 8)
15513 case 64: alignbits
= 1; break;
15515 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15516 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15517 goto bad_alignment
;
15521 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15522 goto bad_alignment
;
15527 first_error (_("bad alignment"));
15531 inst
.instruction
|= alignbits
<< 4;
15532 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15534 /* Bits [4:6] of the immediate in a list specifier encode register stride
15535 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15536 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15537 up the right value for "type" in a table based on this value and the given
15538 list style, then stick it back. */
15539 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15540 | (((inst
.instruction
>> 8) & 3) << 3);
15542 typebits
= typetable
[idx
];
15544 constraint (typebits
== -1, _("bad list type for instruction"));
15546 inst
.instruction
&= ~0xf00;
15547 inst
.instruction
|= typebits
<< 8;
15550 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15551 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15552 otherwise. The variable arguments are a list of pairs of legal (size, align)
15553 values, terminated with -1. */
15556 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15559 int result
= FAIL
, thissize
, thisalign
;
15561 if (!inst
.operands
[1].immisalign
)
15567 va_start (ap
, do_align
);
15571 thissize
= va_arg (ap
, int);
15572 if (thissize
== -1)
15574 thisalign
= va_arg (ap
, int);
15576 if (size
== thissize
&& align
== thisalign
)
15579 while (result
!= SUCCESS
);
15583 if (result
== SUCCESS
)
15586 first_error (_("unsupported alignment for instruction"));
15592 do_neon_ld_st_lane (void)
15594 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15595 int align_good
, do_align
= 0;
15596 int logsize
= neon_logbits (et
.size
);
15597 int align
= inst
.operands
[1].imm
>> 8;
15598 int n
= (inst
.instruction
>> 8) & 3;
15599 int max_el
= 64 / et
.size
;
15601 if (et
.type
== NT_invtype
)
15604 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15605 _("bad list length"));
15606 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15607 _("scalar index out of range"));
15608 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15610 _("stride of 2 unavailable when element size is 8"));
15614 case 0: /* VLD1 / VST1. */
15615 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15617 if (align_good
== FAIL
)
15621 unsigned alignbits
= 0;
15624 case 16: alignbits
= 0x1; break;
15625 case 32: alignbits
= 0x3; break;
15628 inst
.instruction
|= alignbits
<< 4;
15632 case 1: /* VLD2 / VST2. */
15633 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15635 if (align_good
== FAIL
)
15638 inst
.instruction
|= 1 << 4;
15641 case 2: /* VLD3 / VST3. */
15642 constraint (inst
.operands
[1].immisalign
,
15643 _("can't use alignment with this instruction"));
15646 case 3: /* VLD4 / VST4. */
15647 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15648 16, 64, 32, 64, 32, 128, -1);
15649 if (align_good
== FAIL
)
15653 unsigned alignbits
= 0;
15656 case 8: alignbits
= 0x1; break;
15657 case 16: alignbits
= 0x1; break;
15658 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15661 inst
.instruction
|= alignbits
<< 4;
15668 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15669 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15670 inst
.instruction
|= 1 << (4 + logsize
);
15672 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15673 inst
.instruction
|= logsize
<< 10;
15676 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15679 do_neon_ld_dup (void)
15681 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15682 int align_good
, do_align
= 0;
15684 if (et
.type
== NT_invtype
)
15687 switch ((inst
.instruction
>> 8) & 3)
15689 case 0: /* VLD1. */
15690 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15691 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15692 &do_align
, 16, 16, 32, 32, -1);
15693 if (align_good
== FAIL
)
15695 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15698 case 2: inst
.instruction
|= 1 << 5; break;
15699 default: first_error (_("bad list length")); return;
15701 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15704 case 1: /* VLD2. */
15705 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15706 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15707 if (align_good
== FAIL
)
15709 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15710 _("bad list length"));
15711 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15712 inst
.instruction
|= 1 << 5;
15713 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15716 case 2: /* VLD3. */
15717 constraint (inst
.operands
[1].immisalign
,
15718 _("can't use alignment with this instruction"));
15719 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15720 _("bad list length"));
15721 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15722 inst
.instruction
|= 1 << 5;
15723 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15726 case 3: /* VLD4. */
15728 int align
= inst
.operands
[1].imm
>> 8;
15729 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15730 16, 64, 32, 64, 32, 128, -1);
15731 if (align_good
== FAIL
)
15733 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15734 _("bad list length"));
15735 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15736 inst
.instruction
|= 1 << 5;
15737 if (et
.size
== 32 && align
== 128)
15738 inst
.instruction
|= 0x3 << 6;
15740 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15747 inst
.instruction
|= do_align
<< 4;
15750 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15751 apart from bits [11:4]. */
15754 do_neon_ldx_stx (void)
15756 if (inst
.operands
[1].isreg
)
15757 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15759 switch (NEON_LANE (inst
.operands
[0].imm
))
15761 case NEON_INTERLEAVE_LANES
:
15762 NEON_ENCODE (INTERLV
, inst
);
15763 do_neon_ld_st_interleave ();
15766 case NEON_ALL_LANES
:
15767 NEON_ENCODE (DUP
, inst
);
15772 NEON_ENCODE (LANE
, inst
);
15773 do_neon_ld_st_lane ();
15776 /* L bit comes from bit mask. */
15777 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15778 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15779 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15781 if (inst
.operands
[1].postind
)
15783 int postreg
= inst
.operands
[1].imm
& 0xf;
15784 constraint (!inst
.operands
[1].immisreg
,
15785 _("post-index must be a register"));
15786 constraint (postreg
== 0xd || postreg
== 0xf,
15787 _("bad register for post-index"));
15788 inst
.instruction
|= postreg
;
15790 else if (inst
.operands
[1].writeback
)
15792 inst
.instruction
|= 0xd;
15795 inst
.instruction
|= 0xf;
15798 inst
.instruction
|= 0xf9000000;
15800 inst
.instruction
|= 0xf4000000;
15803 /* Overall per-instruction processing. */
15805 /* We need to be able to fix up arbitrary expressions in some statements.
15806 This is so that we can handle symbols that are an arbitrary distance from
15807 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15808 which returns part of an address in a form which will be valid for
15809 a data instruction. We do this by pushing the expression into a symbol
15810 in the expr_section, and creating a fix for that. */
15813 fix_new_arm (fragS
* frag
,
15827 /* Create an absolute valued symbol, so we have something to
15828 refer to in the object file. Unfortunately for us, gas's
15829 generic expression parsing will already have folded out
15830 any use of .set foo/.type foo %function that may have
15831 been used to set type information of the target location,
15832 that's being specified symbolically. We have to presume
15833 the user knows what they are doing. */
15837 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15839 symbol
= symbol_find_or_make (name
);
15840 S_SET_SEGMENT (symbol
, absolute_section
);
15841 symbol_set_frag (symbol
, &zero_address_frag
);
15842 S_SET_VALUE (symbol
, exp
->X_add_number
);
15843 exp
->X_op
= O_symbol
;
15844 exp
->X_add_symbol
= symbol
;
15845 exp
->X_add_number
= 0;
15851 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15852 (enum bfd_reloc_code_real
) reloc
);
15856 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15857 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15861 /* Mark whether the fix is to a THUMB instruction, or an ARM
15863 new_fix
->tc_fix_data
= thumb_mode
;
15866 /* Create a frg for an instruction requiring relaxation. */
15868 output_relax_insn (void)
15874 /* The size of the instruction is unknown, so tie the debug info to the
15875 start of the instruction. */
15876 dwarf2_emit_insn (0);
15878 switch (inst
.reloc
.exp
.X_op
)
15881 sym
= inst
.reloc
.exp
.X_add_symbol
;
15882 offset
= inst
.reloc
.exp
.X_add_number
;
15886 offset
= inst
.reloc
.exp
.X_add_number
;
15889 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15893 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15894 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15895 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15898 /* Write a 32-bit thumb instruction to buf. */
15900 put_thumb32_insn (char * buf
, unsigned long insn
)
15902 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15903 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15907 output_inst (const char * str
)
15913 as_bad ("%s -- `%s'", inst
.error
, str
);
15918 output_relax_insn ();
15921 if (inst
.size
== 0)
15924 to
= frag_more (inst
.size
);
15925 /* PR 9814: Record the thumb mode into the current frag so that we know
15926 what type of NOP padding to use, if necessary. We override any previous
15927 setting so that if the mode has changed then the NOPS that we use will
15928 match the encoding of the last instruction in the frag. */
15929 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15931 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15933 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15934 put_thumb32_insn (to
, inst
.instruction
);
15936 else if (inst
.size
> INSN_SIZE
)
15938 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15939 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15940 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15943 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15945 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15946 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15947 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15950 dwarf2_emit_insn (inst
.size
);
15954 output_it_inst (int cond
, int mask
, char * to
)
15956 unsigned long instruction
= 0xbf00;
15959 instruction
|= mask
;
15960 instruction
|= cond
<< 4;
15964 to
= frag_more (2);
15966 dwarf2_emit_insn (2);
15970 md_number_to_chars (to
, instruction
, 2);
15975 /* Tag values used in struct asm_opcode's tag field. */
15978 OT_unconditional
, /* Instruction cannot be conditionalized.
15979 The ARM condition field is still 0xE. */
15980 OT_unconditionalF
, /* Instruction cannot be conditionalized
15981 and carries 0xF in its ARM condition field. */
15982 OT_csuffix
, /* Instruction takes a conditional suffix. */
15983 OT_csuffixF
, /* Some forms of the instruction take a conditional
15984 suffix, others place 0xF where the condition field
15986 OT_cinfix3
, /* Instruction takes a conditional infix,
15987 beginning at character index 3. (In
15988 unified mode, it becomes a suffix.) */
15989 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15990 tsts, cmps, cmns, and teqs. */
15991 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15992 character index 3, even in unified mode. Used for
15993 legacy instructions where suffix and infix forms
15994 may be ambiguous. */
15995 OT_csuf_or_in3
, /* Instruction takes either a conditional
15996 suffix or an infix at character index 3. */
15997 OT_odd_infix_unc
, /* This is the unconditional variant of an
15998 instruction that takes a conditional infix
15999 at an unusual position. In unified mode,
16000 this variant will accept a suffix. */
16001 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
16002 are the conditional variants of instructions that
16003 take conditional infixes in unusual positions.
16004 The infix appears at character index
16005 (tag - OT_odd_infix_0). These are not accepted
16006 in unified mode. */
16009 /* Subroutine of md_assemble, responsible for looking up the primary
16010 opcode from the mnemonic the user wrote. STR points to the
16011 beginning of the mnemonic.
16013 This is not simply a hash table lookup, because of conditional
16014 variants. Most instructions have conditional variants, which are
16015 expressed with a _conditional affix_ to the mnemonic. If we were
16016 to encode each conditional variant as a literal string in the opcode
16017 table, it would have approximately 20,000 entries.
16019 Most mnemonics take this affix as a suffix, and in unified syntax,
16020 'most' is upgraded to 'all'. However, in the divided syntax, some
16021 instructions take the affix as an infix, notably the s-variants of
16022 the arithmetic instructions. Of those instructions, all but six
16023 have the infix appear after the third character of the mnemonic.
16025 Accordingly, the algorithm for looking up primary opcodes given
16028 1. Look up the identifier in the opcode table.
16029 If we find a match, go to step U.
16031 2. Look up the last two characters of the identifier in the
16032 conditions table. If we find a match, look up the first N-2
16033 characters of the identifier in the opcode table. If we
16034 find a match, go to step CE.
16036 3. Look up the fourth and fifth characters of the identifier in
16037 the conditions table. If we find a match, extract those
16038 characters from the identifier, and look up the remaining
16039 characters in the opcode table. If we find a match, go
16044 U. Examine the tag field of the opcode structure, in case this is
16045 one of the six instructions with its conditional infix in an
16046 unusual place. If it is, the tag tells us where to find the
16047 infix; look it up in the conditions table and set inst.cond
16048 accordingly. Otherwise, this is an unconditional instruction.
16049 Again set inst.cond accordingly. Return the opcode structure.
16051 CE. Examine the tag field to make sure this is an instruction that
16052 should receive a conditional suffix. If it is not, fail.
16053 Otherwise, set inst.cond from the suffix we already looked up,
16054 and return the opcode structure.
16056 CM. Examine the tag field to make sure this is an instruction that
16057 should receive a conditional infix after the third character.
16058 If it is not, fail. Otherwise, undo the edits to the current
16059 line of input and proceed as for case CE. */
16061 static const struct asm_opcode
*
16062 opcode_lookup (char **str
)
16066 const struct asm_opcode
*opcode
;
16067 const struct asm_cond
*cond
;
16070 /* Scan up to the end of the mnemonic, which must end in white space,
16071 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16072 for (base
= end
= *str
; *end
!= '\0'; end
++)
16073 if (*end
== ' ' || *end
== '.')
16079 /* Handle a possible width suffix and/or Neon type suffix. */
16084 /* The .w and .n suffixes are only valid if the unified syntax is in
16086 if (unified_syntax
&& end
[1] == 'w')
16088 else if (unified_syntax
&& end
[1] == 'n')
16093 inst
.vectype
.elems
= 0;
16095 *str
= end
+ offset
;
16097 if (end
[offset
] == '.')
16099 /* See if we have a Neon type suffix (possible in either unified or
16100 non-unified ARM syntax mode). */
16101 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
16104 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
16110 /* Look for unaffixed or special-case affixed mnemonic. */
16111 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16116 if (opcode
->tag
< OT_odd_infix_0
)
16118 inst
.cond
= COND_ALWAYS
;
16122 if (warn_on_deprecated
&& unified_syntax
)
16123 as_warn (_("conditional infixes are deprecated in unified syntax"));
16124 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
16125 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16128 inst
.cond
= cond
->value
;
16132 /* Cannot have a conditional suffix on a mnemonic of less than two
16134 if (end
- base
< 3)
16137 /* Look for suffixed mnemonic. */
16139 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16140 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16142 if (opcode
&& cond
)
16145 switch (opcode
->tag
)
16147 case OT_cinfix3_legacy
:
16148 /* Ignore conditional suffixes matched on infix only mnemonics. */
16152 case OT_cinfix3_deprecated
:
16153 case OT_odd_infix_unc
:
16154 if (!unified_syntax
)
16156 /* else fall through */
16160 case OT_csuf_or_in3
:
16161 inst
.cond
= cond
->value
;
16164 case OT_unconditional
:
16165 case OT_unconditionalF
:
16167 inst
.cond
= cond
->value
;
16170 /* Delayed diagnostic. */
16171 inst
.error
= BAD_COND
;
16172 inst
.cond
= COND_ALWAYS
;
16181 /* Cannot have a usual-position infix on a mnemonic of less than
16182 six characters (five would be a suffix). */
16183 if (end
- base
< 6)
16186 /* Look for infixed mnemonic in the usual position. */
16188 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16192 memcpy (save
, affix
, 2);
16193 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
16194 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16196 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
16197 memcpy (affix
, save
, 2);
16200 && (opcode
->tag
== OT_cinfix3
16201 || opcode
->tag
== OT_cinfix3_deprecated
16202 || opcode
->tag
== OT_csuf_or_in3
16203 || opcode
->tag
== OT_cinfix3_legacy
))
16206 if (warn_on_deprecated
&& unified_syntax
16207 && (opcode
->tag
== OT_cinfix3
16208 || opcode
->tag
== OT_cinfix3_deprecated
))
16209 as_warn (_("conditional infixes are deprecated in unified syntax"));
16211 inst
.cond
= cond
->value
;
16218 /* This function generates an initial IT instruction, leaving its block
16219 virtually open for the new instructions. Eventually,
16220 the mask will be updated by now_it_add_mask () each time
16221 a new instruction needs to be included in the IT block.
16222 Finally, the block is closed with close_automatic_it_block ().
16223 The block closure can be requested either from md_assemble (),
16224 a tencode (), or due to a label hook. */
16227 new_automatic_it_block (int cond
)
16229 now_it
.state
= AUTOMATIC_IT_BLOCK
;
16230 now_it
.mask
= 0x18;
16232 now_it
.block_length
= 1;
16233 mapping_state (MAP_THUMB
);
16234 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
16235 now_it
.warn_deprecated
= FALSE
;
16236 now_it
.insn_cond
= TRUE
;
16239 /* Close an automatic IT block.
16240 See comments in new_automatic_it_block (). */
16243 close_automatic_it_block (void)
16245 now_it
.mask
= 0x10;
16246 now_it
.block_length
= 0;
16249 /* Update the mask of the current automatically-generated IT
16250 instruction. See comments in new_automatic_it_block (). */
16253 now_it_add_mask (int cond
)
16255 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16256 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16257 | ((bitvalue) << (nbit)))
16258 const int resulting_bit
= (cond
& 1);
16260 now_it
.mask
&= 0xf;
16261 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
16263 (5 - now_it
.block_length
));
16264 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
16266 ((5 - now_it
.block_length
) - 1) );
16267 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
16270 #undef SET_BIT_VALUE
16273 /* The IT blocks handling machinery is accessed through the these functions:
16274 it_fsm_pre_encode () from md_assemble ()
16275 set_it_insn_type () optional, from the tencode functions
16276 set_it_insn_type_last () ditto
16277 in_it_block () ditto
16278 it_fsm_post_encode () from md_assemble ()
16279 force_automatic_it_block_close () from label habdling functions
16282 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16283 initializing the IT insn type with a generic initial value depending
16284 on the inst.condition.
16285 2) During the tencode function, two things may happen:
16286 a) The tencode function overrides the IT insn type by
16287 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16288 b) The tencode function queries the IT block state by
16289 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16291 Both set_it_insn_type and in_it_block run the internal FSM state
16292 handling function (handle_it_state), because: a) setting the IT insn
16293 type may incur in an invalid state (exiting the function),
16294 and b) querying the state requires the FSM to be updated.
16295 Specifically we want to avoid creating an IT block for conditional
16296 branches, so it_fsm_pre_encode is actually a guess and we can't
16297 determine whether an IT block is required until the tencode () routine
16298 has decided what type of instruction this actually it.
16299 Because of this, if set_it_insn_type and in_it_block have to be used,
16300 set_it_insn_type has to be called first.
16302 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16303 determines the insn IT type depending on the inst.cond code.
16304 When a tencode () routine encodes an instruction that can be
16305 either outside an IT block, or, in the case of being inside, has to be
16306 the last one, set_it_insn_type_last () will determine the proper
16307 IT instruction type based on the inst.cond code. Otherwise,
16308 set_it_insn_type can be called for overriding that logic or
16309 for covering other cases.
16311 Calling handle_it_state () may not transition the IT block state to
16312 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16313 still queried. Instead, if the FSM determines that the state should
16314 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16315 after the tencode () function: that's what it_fsm_post_encode () does.
16317 Since in_it_block () calls the state handling function to get an
16318 updated state, an error may occur (due to invalid insns combination).
16319 In that case, inst.error is set.
16320 Therefore, inst.error has to be checked after the execution of
16321 the tencode () routine.
16323 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16324 any pending state change (if any) that didn't take place in
16325 handle_it_state () as explained above. */
16328 it_fsm_pre_encode (void)
16330 if (inst
.cond
!= COND_ALWAYS
)
16331 inst
.it_insn_type
= INSIDE_IT_INSN
;
16333 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16335 now_it
.state_handled
= 0;
16338 /* IT state FSM handling function. */
16341 handle_it_state (void)
16343 now_it
.state_handled
= 1;
16344 now_it
.insn_cond
= FALSE
;
16346 switch (now_it
.state
)
16348 case OUTSIDE_IT_BLOCK
:
16349 switch (inst
.it_insn_type
)
16351 case OUTSIDE_IT_INSN
:
16354 case INSIDE_IT_INSN
:
16355 case INSIDE_IT_LAST_INSN
:
16356 if (thumb_mode
== 0)
16359 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16360 as_tsktsk (_("Warning: conditional outside an IT block"\
16365 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16366 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16368 /* Automatically generate the IT instruction. */
16369 new_automatic_it_block (inst
.cond
);
16370 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16371 close_automatic_it_block ();
16375 inst
.error
= BAD_OUT_IT
;
16381 case IF_INSIDE_IT_LAST_INSN
:
16382 case NEUTRAL_IT_INSN
:
16386 now_it
.state
= MANUAL_IT_BLOCK
;
16387 now_it
.block_length
= 0;
16392 case AUTOMATIC_IT_BLOCK
:
16393 /* Three things may happen now:
16394 a) We should increment current it block size;
16395 b) We should close current it block (closing insn or 4 insns);
16396 c) We should close current it block and start a new one (due
16397 to incompatible conditions or
16398 4 insns-length block reached). */
16400 switch (inst
.it_insn_type
)
16402 case OUTSIDE_IT_INSN
:
16403 /* The closure of the block shall happen immediatelly,
16404 so any in_it_block () call reports the block as closed. */
16405 force_automatic_it_block_close ();
16408 case INSIDE_IT_INSN
:
16409 case INSIDE_IT_LAST_INSN
:
16410 case IF_INSIDE_IT_LAST_INSN
:
16411 now_it
.block_length
++;
16413 if (now_it
.block_length
> 4
16414 || !now_it_compatible (inst
.cond
))
16416 force_automatic_it_block_close ();
16417 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16418 new_automatic_it_block (inst
.cond
);
16422 now_it
.insn_cond
= TRUE
;
16423 now_it_add_mask (inst
.cond
);
16426 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16427 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16428 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16429 close_automatic_it_block ();
16432 case NEUTRAL_IT_INSN
:
16433 now_it
.block_length
++;
16434 now_it
.insn_cond
= TRUE
;
16436 if (now_it
.block_length
> 4)
16437 force_automatic_it_block_close ();
16439 now_it_add_mask (now_it
.cc
& 1);
16443 close_automatic_it_block ();
16444 now_it
.state
= MANUAL_IT_BLOCK
;
16449 case MANUAL_IT_BLOCK
:
16451 /* Check conditional suffixes. */
16452 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16455 now_it
.mask
&= 0x1f;
16456 is_last
= (now_it
.mask
== 0x10);
16457 now_it
.insn_cond
= TRUE
;
16459 switch (inst
.it_insn_type
)
16461 case OUTSIDE_IT_INSN
:
16462 inst
.error
= BAD_NOT_IT
;
16465 case INSIDE_IT_INSN
:
16466 if (cond
!= inst
.cond
)
16468 inst
.error
= BAD_IT_COND
;
16473 case INSIDE_IT_LAST_INSN
:
16474 case IF_INSIDE_IT_LAST_INSN
:
16475 if (cond
!= inst
.cond
)
16477 inst
.error
= BAD_IT_COND
;
16482 inst
.error
= BAD_BRANCH
;
16487 case NEUTRAL_IT_INSN
:
16488 /* The BKPT instruction is unconditional even in an IT block. */
16492 inst
.error
= BAD_IT_IT
;
16502 struct depr_insn_mask
16504 unsigned long pattern
;
16505 unsigned long mask
;
16506 const char* description
;
16509 /* List of 16-bit instruction patterns deprecated in an IT block in
16511 static const struct depr_insn_mask depr_it_insns
[] = {
16512 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
16513 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
16514 { 0xa000, 0xb800, N_("ADR") },
16515 { 0x4800, 0xf800, N_("Literal loads") },
16516 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
16517 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
16522 it_fsm_post_encode (void)
16526 if (!now_it
.state_handled
)
16527 handle_it_state ();
16529 if (now_it
.insn_cond
16530 && !now_it
.warn_deprecated
16531 && warn_on_deprecated
16532 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
16534 if (inst
.instruction
>= 0x10000)
16536 as_warn (_("it blocks containing wide Thumb instructions are "
16537 "deprecated in ARMv8"));
16538 now_it
.warn_deprecated
= TRUE
;
16542 const struct depr_insn_mask
*p
= depr_it_insns
;
16544 while (p
->mask
!= 0)
16546 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
16548 as_warn (_("it blocks containing 16-bit Thumb intsructions "
16549 "of the following class are deprecated in ARMv8: "
16550 "%s"), p
->description
);
16551 now_it
.warn_deprecated
= TRUE
;
16559 if (now_it
.block_length
> 1)
16561 as_warn (_("it blocks of more than one conditional instruction are "
16562 "deprecated in ARMv8"));
16563 now_it
.warn_deprecated
= TRUE
;
16567 is_last
= (now_it
.mask
== 0x10);
16570 now_it
.state
= OUTSIDE_IT_BLOCK
;
16576 force_automatic_it_block_close (void)
16578 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16580 close_automatic_it_block ();
16581 now_it
.state
= OUTSIDE_IT_BLOCK
;
16589 if (!now_it
.state_handled
)
16590 handle_it_state ();
16592 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16596 md_assemble (char *str
)
16599 const struct asm_opcode
* opcode
;
16601 /* Align the previous label if needed. */
16602 if (last_label_seen
!= NULL
)
16604 symbol_set_frag (last_label_seen
, frag_now
);
16605 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16606 S_SET_SEGMENT (last_label_seen
, now_seg
);
16609 memset (&inst
, '\0', sizeof (inst
));
16610 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16612 opcode
= opcode_lookup (&p
);
16615 /* It wasn't an instruction, but it might be a register alias of
16616 the form alias .req reg, or a Neon .dn/.qn directive. */
16617 if (! create_register_alias (str
, p
)
16618 && ! create_neon_reg_alias (str
, p
))
16619 as_bad (_("bad instruction `%s'"), str
);
16624 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16625 as_warn (_("s suffix on comparison instruction is deprecated"));
16627 /* The value which unconditional instructions should have in place of the
16628 condition field. */
16629 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16633 arm_feature_set variant
;
16635 variant
= cpu_variant
;
16636 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16637 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16638 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16639 /* Check that this instruction is supported for this CPU. */
16640 if (!opcode
->tvariant
16641 || (thumb_mode
== 1
16642 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16644 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16647 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16648 && opcode
->tencode
!= do_t_branch
)
16650 as_bad (_("Thumb does not support conditional execution"));
16654 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16656 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16657 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16658 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16660 /* Two things are addressed here.
16661 1) Implicit require narrow instructions on Thumb-1.
16662 This avoids relaxation accidentally introducing Thumb-2
16664 2) Reject wide instructions in non Thumb-2 cores. */
16665 if (inst
.size_req
== 0)
16667 else if (inst
.size_req
== 4)
16669 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16675 inst
.instruction
= opcode
->tvalue
;
16677 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16679 /* Prepare the it_insn_type for those encodings that don't set
16681 it_fsm_pre_encode ();
16683 opcode
->tencode ();
16685 it_fsm_post_encode ();
16688 if (!(inst
.error
|| inst
.relax
))
16690 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16691 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16692 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16694 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16699 /* Something has gone badly wrong if we try to relax a fixed size
16701 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16703 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16704 *opcode
->tvariant
);
16705 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16706 set those bits when Thumb-2 32-bit instructions are seen. ie.
16707 anything other than bl/blx and v6-M instructions.
16708 This is overly pessimistic for relaxable instructions. */
16709 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16711 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16712 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16713 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16716 check_neon_suffixes
;
16720 mapping_state (MAP_THUMB
);
16723 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16727 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16728 is_bx
= (opcode
->aencode
== do_bx
);
16730 /* Check that this instruction is supported for this CPU. */
16731 if (!(is_bx
&& fix_v4bx
)
16732 && !(opcode
->avariant
&&
16733 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16735 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16740 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16744 inst
.instruction
= opcode
->avalue
;
16745 if (opcode
->tag
== OT_unconditionalF
)
16746 inst
.instruction
|= 0xF << 28;
16748 inst
.instruction
|= inst
.cond
<< 28;
16749 inst
.size
= INSN_SIZE
;
16750 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16752 it_fsm_pre_encode ();
16753 opcode
->aencode ();
16754 it_fsm_post_encode ();
16756 /* Arm mode bx is marked as both v4T and v5 because it's still required
16757 on a hypothetical non-thumb v5 core. */
16759 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16761 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16762 *opcode
->avariant
);
16764 check_neon_suffixes
;
16768 mapping_state (MAP_ARM
);
16773 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16781 check_it_blocks_finished (void)
16786 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16787 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16788 == MANUAL_IT_BLOCK
)
16790 as_warn (_("section '%s' finished with an open IT block."),
16794 if (now_it
.state
== MANUAL_IT_BLOCK
)
16795 as_warn (_("file finished with an open IT block."));
16799 /* Various frobbings of labels and their addresses. */
16802 arm_start_line_hook (void)
16804 last_label_seen
= NULL
;
16808 arm_frob_label (symbolS
* sym
)
16810 last_label_seen
= sym
;
16812 ARM_SET_THUMB (sym
, thumb_mode
);
16814 #if defined OBJ_COFF || defined OBJ_ELF
16815 ARM_SET_INTERWORK (sym
, support_interwork
);
16818 force_automatic_it_block_close ();
16820 /* Note - do not allow local symbols (.Lxxx) to be labelled
16821 as Thumb functions. This is because these labels, whilst
16822 they exist inside Thumb code, are not the entry points for
16823 possible ARM->Thumb calls. Also, these labels can be used
16824 as part of a computed goto or switch statement. eg gcc
16825 can generate code that looks like this:
16827 ldr r2, [pc, .Laaa]
16837 The first instruction loads the address of the jump table.
16838 The second instruction converts a table index into a byte offset.
16839 The third instruction gets the jump address out of the table.
16840 The fourth instruction performs the jump.
16842 If the address stored at .Laaa is that of a symbol which has the
16843 Thumb_Func bit set, then the linker will arrange for this address
16844 to have the bottom bit set, which in turn would mean that the
16845 address computation performed by the third instruction would end
16846 up with the bottom bit set. Since the ARM is capable of unaligned
16847 word loads, the instruction would then load the incorrect address
16848 out of the jump table, and chaos would ensue. */
16849 if (label_is_thumb_function_name
16850 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16851 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16853 /* When the address of a Thumb function is taken the bottom
16854 bit of that address should be set. This will allow
16855 interworking between Arm and Thumb functions to work
16858 THUMB_SET_FUNC (sym
, 1);
16860 label_is_thumb_function_name
= FALSE
;
16863 dwarf2_emit_label (sym
);
16867 arm_data_in_code (void)
16869 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16871 *input_line_pointer
= '/';
16872 input_line_pointer
+= 5;
16873 *input_line_pointer
= 0;
16881 arm_canonicalize_symbol_name (char * name
)
16885 if (thumb_mode
&& (len
= strlen (name
)) > 5
16886 && streq (name
+ len
- 5, "/data"))
16887 *(name
+ len
- 5) = 0;
16892 /* Table of all register names defined by default. The user can
16893 define additional names with .req. Note that all register names
16894 should appear in both upper and lowercase variants. Some registers
16895 also have mixed-case names. */
16897 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16898 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16899 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16900 #define REGSET(p,t) \
16901 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16902 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16903 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16904 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16905 #define REGSETH(p,t) \
16906 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16907 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16908 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16909 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16910 #define REGSET2(p,t) \
16911 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16912 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16913 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16914 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16915 #define SPLRBANK(base,bank,t) \
16916 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16917 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16918 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16919 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16920 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16921 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16923 static const struct reg_entry reg_names
[] =
16925 /* ARM integer registers. */
16926 REGSET(r
, RN
), REGSET(R
, RN
),
16928 /* ATPCS synonyms. */
16929 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16930 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16931 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16933 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16934 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16935 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16937 /* Well-known aliases. */
16938 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16939 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16941 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16942 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16944 /* Coprocessor numbers. */
16945 REGSET(p
, CP
), REGSET(P
, CP
),
16947 /* Coprocessor register numbers. The "cr" variants are for backward
16949 REGSET(c
, CN
), REGSET(C
, CN
),
16950 REGSET(cr
, CN
), REGSET(CR
, CN
),
16952 /* ARM banked registers. */
16953 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16954 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16955 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16956 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16957 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16958 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16959 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16961 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16962 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16963 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16964 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16965 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16966 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16967 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16968 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16970 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16971 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16972 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16973 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16974 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16975 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16976 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16977 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16978 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16980 /* FPA registers. */
16981 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16982 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16984 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16985 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16987 /* VFP SP registers. */
16988 REGSET(s
,VFS
), REGSET(S
,VFS
),
16989 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16991 /* VFP DP Registers. */
16992 REGSET(d
,VFD
), REGSET(D
,VFD
),
16993 /* Extra Neon DP registers. */
16994 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16996 /* Neon QP registers. */
16997 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16999 /* VFP control registers. */
17000 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
17001 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
17002 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
17003 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
17004 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
17005 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
17007 /* Maverick DSP coprocessor registers. */
17008 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
17009 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
17011 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
17012 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
17013 REGDEF(dspsc
,0,DSPSC
),
17015 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
17016 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
17017 REGDEF(DSPSC
,0,DSPSC
),
17019 /* iWMMXt data registers - p0, c0-15. */
17020 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
17022 /* iWMMXt control registers - p1, c0-3. */
17023 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
17024 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
17025 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
17026 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
17028 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17029 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
17030 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
17031 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
17032 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
17034 /* XScale accumulator registers. */
17035 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
17041 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17042 within psr_required_here. */
17043 static const struct asm_psr psrs
[] =
17045 /* Backward compatibility notation. Note that "all" is no longer
17046 truly all possible PSR bits. */
17047 {"all", PSR_c
| PSR_f
},
17051 /* Individual flags. */
17057 /* Combinations of flags. */
17058 {"fs", PSR_f
| PSR_s
},
17059 {"fx", PSR_f
| PSR_x
},
17060 {"fc", PSR_f
| PSR_c
},
17061 {"sf", PSR_s
| PSR_f
},
17062 {"sx", PSR_s
| PSR_x
},
17063 {"sc", PSR_s
| PSR_c
},
17064 {"xf", PSR_x
| PSR_f
},
17065 {"xs", PSR_x
| PSR_s
},
17066 {"xc", PSR_x
| PSR_c
},
17067 {"cf", PSR_c
| PSR_f
},
17068 {"cs", PSR_c
| PSR_s
},
17069 {"cx", PSR_c
| PSR_x
},
17070 {"fsx", PSR_f
| PSR_s
| PSR_x
},
17071 {"fsc", PSR_f
| PSR_s
| PSR_c
},
17072 {"fxs", PSR_f
| PSR_x
| PSR_s
},
17073 {"fxc", PSR_f
| PSR_x
| PSR_c
},
17074 {"fcs", PSR_f
| PSR_c
| PSR_s
},
17075 {"fcx", PSR_f
| PSR_c
| PSR_x
},
17076 {"sfx", PSR_s
| PSR_f
| PSR_x
},
17077 {"sfc", PSR_s
| PSR_f
| PSR_c
},
17078 {"sxf", PSR_s
| PSR_x
| PSR_f
},
17079 {"sxc", PSR_s
| PSR_x
| PSR_c
},
17080 {"scf", PSR_s
| PSR_c
| PSR_f
},
17081 {"scx", PSR_s
| PSR_c
| PSR_x
},
17082 {"xfs", PSR_x
| PSR_f
| PSR_s
},
17083 {"xfc", PSR_x
| PSR_f
| PSR_c
},
17084 {"xsf", PSR_x
| PSR_s
| PSR_f
},
17085 {"xsc", PSR_x
| PSR_s
| PSR_c
},
17086 {"xcf", PSR_x
| PSR_c
| PSR_f
},
17087 {"xcs", PSR_x
| PSR_c
| PSR_s
},
17088 {"cfs", PSR_c
| PSR_f
| PSR_s
},
17089 {"cfx", PSR_c
| PSR_f
| PSR_x
},
17090 {"csf", PSR_c
| PSR_s
| PSR_f
},
17091 {"csx", PSR_c
| PSR_s
| PSR_x
},
17092 {"cxf", PSR_c
| PSR_x
| PSR_f
},
17093 {"cxs", PSR_c
| PSR_x
| PSR_s
},
17094 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
17095 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
17096 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
17097 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
17098 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
17099 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
17100 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
17101 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
17102 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
17103 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
17104 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
17105 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
17106 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
17107 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
17108 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
17109 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
17110 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
17111 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
17112 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
17113 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
17114 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
17115 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
17116 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
17117 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
17120 /* Table of V7M psr names. */
17121 static const struct asm_psr v7m_psrs
[] =
17123 {"apsr", 0 }, {"APSR", 0 },
17124 {"iapsr", 1 }, {"IAPSR", 1 },
17125 {"eapsr", 2 }, {"EAPSR", 2 },
17126 {"psr", 3 }, {"PSR", 3 },
17127 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17128 {"ipsr", 5 }, {"IPSR", 5 },
17129 {"epsr", 6 }, {"EPSR", 6 },
17130 {"iepsr", 7 }, {"IEPSR", 7 },
17131 {"msp", 8 }, {"MSP", 8 },
17132 {"psp", 9 }, {"PSP", 9 },
17133 {"primask", 16}, {"PRIMASK", 16},
17134 {"basepri", 17}, {"BASEPRI", 17},
17135 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17136 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17137 {"faultmask", 19}, {"FAULTMASK", 19},
17138 {"control", 20}, {"CONTROL", 20}
17141 /* Table of all shift-in-operand names. */
17142 static const struct asm_shift_name shift_names
[] =
17144 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
17145 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
17146 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
17147 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
17148 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
17149 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
17152 /* Table of all explicit relocation names. */
17154 static struct reloc_entry reloc_names
[] =
17156 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
17157 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
17158 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
17159 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
17160 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
17161 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
17162 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
17163 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
17164 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
17165 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
17166 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
17167 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
17168 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
17169 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
17170 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
17171 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
17172 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
17173 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
17177 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17178 static const struct asm_cond conds
[] =
17182 {"cs", 0x2}, {"hs", 0x2},
17183 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17197 #define UL_BARRIER(L,U,CODE,FEAT) \
17198 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17199 { U, CODE, ARM_FEATURE (FEAT, 0) }
17201 static struct asm_barrier_opt barrier_opt_names
[] =
17203 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
17204 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
17205 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
17206 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
17207 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
17208 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
17209 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
17210 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
17211 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
17212 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
17213 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
17214 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
17215 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
17216 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
17217 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
17218 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
17223 /* Table of ARM-format instructions. */
17225 /* Macros for gluing together operand strings. N.B. In all cases
17226 other than OPS0, the trailing OP_stop comes from default
17227 zero-initialization of the unspecified elements of the array. */
17228 #define OPS0() { OP_stop, }
17229 #define OPS1(a) { OP_##a, }
17230 #define OPS2(a,b) { OP_##a,OP_##b, }
17231 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17232 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17233 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17234 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17236 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17237 This is useful when mixing operands for ARM and THUMB, i.e. using the
17238 MIX_ARM_THUMB_OPERANDS macro.
17239 In order to use these macros, prefix the number of operands with _
17241 #define OPS_1(a) { a, }
17242 #define OPS_2(a,b) { a,b, }
17243 #define OPS_3(a,b,c) { a,b,c, }
17244 #define OPS_4(a,b,c,d) { a,b,c,d, }
17245 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17246 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17248 /* These macros abstract out the exact format of the mnemonic table and
17249 save some repeated characters. */
17251 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17252 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17253 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17254 THUMB_VARIANT, do_##ae, do_##te }
17256 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17257 a T_MNEM_xyz enumerator. */
17258 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17259 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17260 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17261 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17263 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17264 infix after the third character. */
17265 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17266 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17267 THUMB_VARIANT, do_##ae, do_##te }
17268 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17269 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17270 THUMB_VARIANT, do_##ae, do_##te }
17271 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17272 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17273 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17274 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17275 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17276 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17277 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17278 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17280 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17281 appear in the condition table. */
17282 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17283 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17284 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17286 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17287 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17288 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17289 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17290 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17291 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17292 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17293 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17294 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17295 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17296 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17297 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17298 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17299 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17300 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17301 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17302 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17303 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17304 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17305 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17307 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17308 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17309 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17310 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17312 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17313 field is still 0xE. Many of the Thumb variants can be executed
17314 conditionally, so this is checked separately. */
17315 #define TUE(mnem, op, top, nops, ops, ae, te) \
17316 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17317 THUMB_VARIANT, do_##ae, do_##te }
17319 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17320 condition code field. */
17321 #define TUF(mnem, op, top, nops, ops, ae, te) \
17322 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17323 THUMB_VARIANT, do_##ae, do_##te }
17325 /* ARM-only variants of all the above. */
17326 #define CE(mnem, op, nops, ops, ae) \
17327 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17329 #define C3(mnem, op, nops, ops, ae) \
17330 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17332 /* Legacy mnemonics that always have conditional infix after the third
17334 #define CL(mnem, op, nops, ops, ae) \
17335 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17336 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17338 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17339 #define cCE(mnem, op, nops, ops, ae) \
17340 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17342 /* Legacy coprocessor instructions where conditional infix and conditional
17343 suffix are ambiguous. For consistency this includes all FPA instructions,
17344 not just the potentially ambiguous ones. */
17345 #define cCL(mnem, op, nops, ops, ae) \
17346 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17347 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17349 /* Coprocessor, takes either a suffix or a position-3 infix
17350 (for an FPA corner case). */
17351 #define C3E(mnem, op, nops, ops, ae) \
17352 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17353 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17355 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17356 { m1 #m2 m3, OPS##nops ops, \
17357 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17358 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17360 #define CM(m1, m2, op, nops, ops, ae) \
17361 xCM_ (m1, , m2, op, nops, ops, ae), \
17362 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17363 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17364 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17365 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17366 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17367 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17368 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17369 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17370 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17371 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17372 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17373 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17374 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17375 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17376 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17377 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17378 xCM_ (m1, le, m2, op, nops, ops, ae), \
17379 xCM_ (m1, al, m2, op, nops, ops, ae)
17381 #define UE(mnem, op, nops, ops, ae) \
17382 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17384 #define UF(mnem, op, nops, ops, ae) \
17385 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17387 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17388 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17389 use the same encoding function for each. */
17390 #define NUF(mnem, op, nops, ops, enc) \
17391 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17392 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17394 /* Neon data processing, version which indirects through neon_enc_tab for
17395 the various overloaded versions of opcodes. */
17396 #define nUF(mnem, op, nops, ops, enc) \
17397 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17398 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17400 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17402 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17403 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17404 THUMB_VARIANT, do_##enc, do_##enc }
17406 #define NCE(mnem, op, nops, ops, enc) \
17407 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17409 #define NCEF(mnem, op, nops, ops, enc) \
17410 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17412 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17413 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17414 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17415 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17417 #define nCE(mnem, op, nops, ops, enc) \
17418 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17420 #define nCEF(mnem, op, nops, ops, enc) \
17421 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17425 static const struct asm_opcode insns
[] =
17427 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17428 #define THUMB_VARIANT &arm_ext_v4t
17429 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17430 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17431 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17432 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17433 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17434 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17435 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17436 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17437 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17438 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17439 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17440 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17441 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17442 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17443 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17444 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17446 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17447 for setting PSR flag bits. They are obsolete in V6 and do not
17448 have Thumb equivalents. */
17449 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17450 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17451 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17452 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17453 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17454 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17455 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17456 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17457 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17459 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17460 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17461 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17462 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17464 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17465 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17466 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17468 OP_ADDRGLDR
),ldst
, t_ldst
),
17469 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17471 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17472 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17473 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17474 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17475 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17476 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17478 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17479 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17480 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17481 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17484 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17485 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17486 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17488 /* Thumb-compatibility pseudo ops. */
17489 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17490 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17491 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17492 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17493 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17494 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17495 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17496 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17497 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17498 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17499 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17500 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17502 /* These may simplify to neg. */
17503 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17504 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17506 #undef THUMB_VARIANT
17507 #define THUMB_VARIANT & arm_ext_v6
17509 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17511 /* V1 instructions with no Thumb analogue prior to V6T2. */
17512 #undef THUMB_VARIANT
17513 #define THUMB_VARIANT & arm_ext_v6t2
17515 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17516 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17517 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17519 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17520 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17521 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17522 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17524 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17525 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17527 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17528 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17530 /* V1 instructions with no Thumb analogue at all. */
17531 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17532 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17534 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17535 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17536 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17537 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17538 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17539 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17540 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17541 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17544 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17545 #undef THUMB_VARIANT
17546 #define THUMB_VARIANT & arm_ext_v4t
17548 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17549 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17551 #undef THUMB_VARIANT
17552 #define THUMB_VARIANT & arm_ext_v6t2
17554 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17555 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17557 /* Generic coprocessor instructions. */
17558 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17559 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17560 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17561 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17562 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17563 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17564 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17567 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17569 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17570 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17573 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17574 #undef THUMB_VARIANT
17575 #define THUMB_VARIANT & arm_ext_msr
17577 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17578 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17581 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17582 #undef THUMB_VARIANT
17583 #define THUMB_VARIANT & arm_ext_v6t2
17585 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17586 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17587 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17588 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17589 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17590 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17591 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17592 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17595 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17596 #undef THUMB_VARIANT
17597 #define THUMB_VARIANT & arm_ext_v4t
17599 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17600 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17601 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17602 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17603 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17604 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17607 #define ARM_VARIANT & arm_ext_v4t_5
17609 /* ARM Architecture 4T. */
17610 /* Note: bx (and blx) are required on V5, even if the processor does
17611 not support Thumb. */
17612 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17615 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17616 #undef THUMB_VARIANT
17617 #define THUMB_VARIANT & arm_ext_v5t
17619 /* Note: blx has 2 variants; the .value coded here is for
17620 BLX(2). Only this variant has conditional execution. */
17621 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17622 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17624 #undef THUMB_VARIANT
17625 #define THUMB_VARIANT & arm_ext_v6t2
17627 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17628 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17629 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17630 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17631 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17632 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17633 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17634 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17637 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17638 #undef THUMB_VARIANT
17639 #define THUMB_VARIANT &arm_ext_v5exp
17641 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17642 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17643 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17644 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17646 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17647 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17649 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17650 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17651 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17652 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17654 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17655 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17656 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17657 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17659 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17660 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17662 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17663 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17664 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17665 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17668 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17669 #undef THUMB_VARIANT
17670 #define THUMB_VARIANT &arm_ext_v6t2
17672 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17673 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17675 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17676 ADDRGLDRS
), ldrd
, t_ldstd
),
17678 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17679 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17682 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17684 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17687 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17688 #undef THUMB_VARIANT
17689 #define THUMB_VARIANT & arm_ext_v6
17691 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17692 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17693 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17694 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17695 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17696 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17697 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17698 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17699 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17700 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17702 #undef THUMB_VARIANT
17703 #define THUMB_VARIANT & arm_ext_v6t2
17705 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17706 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17708 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17709 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17711 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17712 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17714 /* ARM V6 not included in V7M. */
17715 #undef THUMB_VARIANT
17716 #define THUMB_VARIANT & arm_ext_v6_notm
17717 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17718 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17719 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17720 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17721 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17722 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17723 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17724 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17725 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17726 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17727 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17728 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17730 /* ARM V6 not included in V7M (eg. integer SIMD). */
17731 #undef THUMB_VARIANT
17732 #define THUMB_VARIANT & arm_ext_v6_dsp
17733 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17734 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17735 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17736 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17737 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17738 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17739 /* Old name for QASX. */
17740 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17741 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17742 /* Old name for QSAX. */
17743 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17744 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17745 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17746 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17747 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17748 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17749 /* Old name for SASX. */
17750 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17751 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17752 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17753 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17754 /* Old name for SHASX. */
17755 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17756 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17757 /* Old name for SHSAX. */
17758 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17759 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17760 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17761 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17762 /* Old name for SSAX. */
17763 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17764 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17765 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17766 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17767 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17768 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17769 /* Old name for UASX. */
17770 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17771 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17772 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17773 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17774 /* Old name for UHASX. */
17775 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17776 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17777 /* Old name for UHSAX. */
17778 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17779 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17780 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17781 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17782 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17783 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17784 /* Old name for UQASX. */
17785 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17786 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17787 /* Old name for UQSAX. */
17788 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17789 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17790 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17791 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17792 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17793 /* Old name for USAX. */
17794 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17795 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17796 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17797 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17798 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17799 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17800 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17801 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17802 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17803 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17804 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17805 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17806 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17807 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17808 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17809 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17810 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17811 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17812 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17813 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17814 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17815 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17816 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17817 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17818 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17819 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17820 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17821 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17822 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17823 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17824 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17825 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17826 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17827 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17830 #define ARM_VARIANT & arm_ext_v6k
17831 #undef THUMB_VARIANT
17832 #define THUMB_VARIANT & arm_ext_v6k
17834 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17835 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17836 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17837 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17839 #undef THUMB_VARIANT
17840 #define THUMB_VARIANT & arm_ext_v6_notm
17841 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17843 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17844 RRnpcb
), strexd
, t_strexd
),
17846 #undef THUMB_VARIANT
17847 #define THUMB_VARIANT & arm_ext_v6t2
17848 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17850 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17852 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17854 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17856 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17859 #define ARM_VARIANT & arm_ext_sec
17860 #undef THUMB_VARIANT
17861 #define THUMB_VARIANT & arm_ext_sec
17863 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17866 #define ARM_VARIANT & arm_ext_virt
17867 #undef THUMB_VARIANT
17868 #define THUMB_VARIANT & arm_ext_virt
17870 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17871 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17874 #define ARM_VARIANT & arm_ext_v6t2
17875 #undef THUMB_VARIANT
17876 #define THUMB_VARIANT & arm_ext_v6t2
17878 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17879 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17880 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17881 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17883 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17884 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17885 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17886 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17888 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17889 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17890 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17891 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17893 /* Thumb-only instructions. */
17895 #define ARM_VARIANT NULL
17896 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17897 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17899 /* ARM does not really have an IT instruction, so always allow it.
17900 The opcode is copied from Thumb in order to allow warnings in
17901 -mimplicit-it=[never | arm] modes. */
17903 #define ARM_VARIANT & arm_ext_v1
17905 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17906 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17907 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17908 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17909 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17910 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17911 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17912 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17913 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17914 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17915 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17916 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17917 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17918 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17919 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17920 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17921 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17922 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17924 /* Thumb2 only instructions. */
17926 #define ARM_VARIANT NULL
17928 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17929 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17930 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17931 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17932 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17933 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17935 /* Hardware division instructions. */
17937 #define ARM_VARIANT & arm_ext_adiv
17938 #undef THUMB_VARIANT
17939 #define THUMB_VARIANT & arm_ext_div
17941 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17942 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17944 /* ARM V6M/V7 instructions. */
17946 #define ARM_VARIANT & arm_ext_barrier
17947 #undef THUMB_VARIANT
17948 #define THUMB_VARIANT & arm_ext_barrier
17950 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17951 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17952 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17954 /* ARM V7 instructions. */
17956 #define ARM_VARIANT & arm_ext_v7
17957 #undef THUMB_VARIANT
17958 #define THUMB_VARIANT & arm_ext_v7
17960 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17961 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17964 #define ARM_VARIANT & arm_ext_mp
17965 #undef THUMB_VARIANT
17966 #define THUMB_VARIANT & arm_ext_mp
17968 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17970 /* AArchv8 instructions. */
17972 #define ARM_VARIANT & arm_ext_v8
17973 #undef THUMB_VARIANT
17974 #define THUMB_VARIANT & arm_ext_v8
17976 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
17979 #define ARM_VARIANT NULL
17980 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
17981 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
17982 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
17985 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17986 #undef THUMB_VARIANT
17987 #define THUMB_VARIANT NULL
17989 cCE("wfs", e200110
, 1, (RR
), rd
),
17990 cCE("rfs", e300110
, 1, (RR
), rd
),
17991 cCE("wfc", e400110
, 1, (RR
), rd
),
17992 cCE("rfc", e500110
, 1, (RR
), rd
),
17994 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17995 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17996 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17997 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17999 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18000 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18001 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18002 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18004 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
18005 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
18006 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
18007 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
18008 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
18009 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
18010 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
18011 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
18012 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
18013 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
18014 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
18015 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
18017 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
18018 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
18019 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
18020 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
18021 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
18022 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
18023 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
18024 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
18025 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
18026 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
18027 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
18028 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
18030 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
18031 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
18032 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
18033 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
18034 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
18035 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
18036 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
18037 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
18038 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
18039 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
18040 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
18041 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
18043 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
18044 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
18045 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
18046 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
18047 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
18048 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
18049 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
18050 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
18051 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
18052 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
18053 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
18054 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
18056 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
18057 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
18058 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
18059 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
18060 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
18061 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
18062 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
18063 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
18064 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
18065 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
18066 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
18067 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
18069 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
18070 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
18071 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
18072 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
18073 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
18074 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
18075 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
18076 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
18077 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
18078 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
18079 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
18080 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
18082 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
18083 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
18084 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
18085 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
18086 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
18087 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
18088 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
18089 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
18090 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
18091 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
18092 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
18093 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
18095 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
18096 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
18097 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
18098 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
18099 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
18100 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
18101 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
18102 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
18103 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
18104 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
18105 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
18106 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
18108 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
18109 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
18110 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
18111 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
18112 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
18113 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
18114 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
18115 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
18116 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
18117 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
18118 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
18119 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
18121 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
18122 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
18123 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
18124 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
18125 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
18126 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
18127 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
18128 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
18129 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
18130 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
18131 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
18132 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
18134 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
18135 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
18136 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
18137 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
18138 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
18139 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
18140 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
18141 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
18142 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
18143 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
18144 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
18145 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
18147 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
18148 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
18149 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
18150 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
18151 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
18152 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
18153 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
18154 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
18155 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
18156 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
18157 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
18158 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
18160 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
18161 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
18162 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
18163 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
18164 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
18165 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
18166 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
18167 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
18168 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
18169 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
18170 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
18171 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
18173 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
18174 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
18175 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
18176 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
18177 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
18178 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
18179 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
18180 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
18181 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
18182 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
18183 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
18184 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
18186 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
18187 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
18188 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
18189 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
18190 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
18191 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
18192 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
18193 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
18194 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
18195 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
18196 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
18197 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
18199 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
18200 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
18201 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
18202 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
18203 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
18204 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
18205 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
18206 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
18207 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
18208 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
18209 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
18210 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
18212 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18213 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18214 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18215 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18216 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18217 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18218 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18219 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18220 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18221 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18222 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18223 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18225 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18226 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18227 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18228 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18229 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18230 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18231 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18232 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18233 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18234 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18235 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18236 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18238 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18239 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18240 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18241 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18242 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18243 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18244 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18245 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18246 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18247 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18248 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18249 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18251 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18252 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18253 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18254 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18255 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18256 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18257 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18258 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18259 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18260 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18261 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18262 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18264 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18265 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18266 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18267 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18268 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18269 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18270 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18271 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18272 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18273 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18274 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18275 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18277 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18278 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18279 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18280 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18281 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18282 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18283 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18284 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18285 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18286 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18287 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18288 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18290 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18291 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18292 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18293 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18294 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18295 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18296 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18297 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18298 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18299 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18300 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18301 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18303 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18304 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18305 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18306 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18307 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18308 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18309 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18310 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18311 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18312 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18313 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18314 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18316 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18317 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18318 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18319 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18320 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18321 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18322 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18323 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18324 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18325 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18326 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18327 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18329 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18330 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18331 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18332 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18333 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18334 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18335 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18336 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18337 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18338 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18339 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18340 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18342 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18343 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18344 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18345 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18346 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18347 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18348 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18349 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18350 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18351 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18352 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18353 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18355 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18356 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18357 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18358 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18359 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18360 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18361 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18362 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18363 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18364 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18365 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18366 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18368 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18369 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18370 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18371 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18372 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18373 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18374 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18375 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18376 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18377 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18378 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18379 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18381 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18382 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18383 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18384 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18386 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
18387 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
18388 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
18389 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
18390 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
18391 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
18392 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
18393 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
18394 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
18395 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
18396 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
18397 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
18399 /* The implementation of the FIX instruction is broken on some
18400 assemblers, in that it accepts a precision specifier as well as a
18401 rounding specifier, despite the fact that this is meaningless.
18402 To be more compatible, we accept it as well, though of course it
18403 does not set any bits. */
18404 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
18405 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
18406 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
18407 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
18408 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
18409 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18410 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18411 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18412 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18413 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18414 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18415 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18416 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18418 /* Instructions that were new with the real FPA, call them V2. */
18420 #define ARM_VARIANT & fpu_fpa_ext_v2
18422 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18423 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18424 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18425 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18426 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18427 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18430 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18432 /* Moves and type conversions. */
18433 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18434 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18435 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18436 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18437 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
18438 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
18439 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18440 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18441 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18442 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18443 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18444 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18445 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18446 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
18448 /* Memory operations. */
18449 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18450 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18451 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18452 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18453 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18454 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18455 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18456 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18457 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18458 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18459 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18460 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18461 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18462 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18463 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18464 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18465 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18466 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18468 /* Monadic operations. */
18469 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18470 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18471 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18473 /* Dyadic operations. */
18474 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18475 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18476 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18477 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18478 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18479 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18480 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18481 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18482 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18485 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18486 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18487 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18488 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18490 /* Double precision load/store are still present on single precision
18491 implementations. */
18492 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18493 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18494 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18495 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18496 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18497 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18498 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18499 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18500 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18501 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18504 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18506 /* Moves and type conversions. */
18507 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18508 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18509 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18510 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18511 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18512 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18513 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18514 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18515 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18516 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18517 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18518 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18519 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18521 /* Monadic operations. */
18522 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18523 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18524 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18526 /* Dyadic operations. */
18527 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18528 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18529 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18530 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18531 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18532 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18533 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18534 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18535 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18538 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18539 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18540 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18541 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18544 #define ARM_VARIANT & fpu_vfp_ext_v2
18546 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18547 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18548 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18549 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18551 /* Instructions which may belong to either the Neon or VFP instruction sets.
18552 Individual encoder functions perform additional architecture checks. */
18554 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18555 #undef THUMB_VARIANT
18556 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18558 /* These mnemonics are unique to VFP. */
18559 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18560 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18561 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18562 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18563 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18564 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18565 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18566 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18567 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18568 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18570 /* Mnemonics shared by Neon and VFP. */
18571 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18572 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18573 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18575 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18576 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18578 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18579 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18581 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18582 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18583 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18584 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18585 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18586 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18587 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18588 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18590 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
18591 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18592 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18593 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18596 /* NOTE: All VMOV encoding is special-cased! */
18597 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18598 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18600 #undef THUMB_VARIANT
18601 #define THUMB_VARIANT & fpu_neon_ext_v1
18603 #define ARM_VARIANT & fpu_neon_ext_v1
18605 /* Data processing with three registers of the same length. */
18606 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18607 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18608 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18609 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18610 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18611 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18612 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18613 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18614 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18615 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18616 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18617 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18618 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18619 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18620 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18621 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18622 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18623 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18624 /* If not immediate, fall back to neon_dyadic_i64_su.
18625 shl_imm should accept I8 I16 I32 I64,
18626 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18627 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18628 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18629 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18630 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18631 /* Logic ops, types optional & ignored. */
18632 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18633 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18634 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18635 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18636 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18637 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18638 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18639 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18640 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18641 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18642 /* Bitfield ops, untyped. */
18643 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18644 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18645 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18646 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18647 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18648 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18649 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18650 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18651 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18652 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18653 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18654 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18655 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18656 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18657 back to neon_dyadic_if_su. */
18658 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18659 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18660 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18661 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18662 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18663 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18664 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18665 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18666 /* Comparison. Type I8 I16 I32 F32. */
18667 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18668 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18669 /* As above, D registers only. */
18670 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18671 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18672 /* Int and float variants, signedness unimportant. */
18673 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18674 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18675 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18676 /* Add/sub take types I8 I16 I32 I64 F32. */
18677 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18678 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18679 /* vtst takes sizes 8, 16, 32. */
18680 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18681 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18682 /* VMUL takes I8 I16 I32 F32 P8. */
18683 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18684 /* VQD{R}MULH takes S16 S32. */
18685 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18686 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18687 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18688 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18689 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18690 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18691 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18692 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18693 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18694 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18695 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18696 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18697 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18698 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18699 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18700 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18702 /* Two address, int/float. Types S8 S16 S32 F32. */
18703 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18704 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18706 /* Data processing with two registers and a shift amount. */
18707 /* Right shifts, and variants with rounding.
18708 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18709 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18710 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18711 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18712 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18713 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18714 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18715 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18716 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18717 /* Shift and insert. Sizes accepted 8 16 32 64. */
18718 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18719 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18720 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18721 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18722 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18723 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18724 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18725 /* Right shift immediate, saturating & narrowing, with rounding variants.
18726 Types accepted S16 S32 S64 U16 U32 U64. */
18727 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18728 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18729 /* As above, unsigned. Types accepted S16 S32 S64. */
18730 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18731 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18732 /* Right shift narrowing. Types accepted I16 I32 I64. */
18733 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18734 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18735 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18736 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18737 /* CVT with optional immediate for fixed-point variant. */
18738 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18740 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18741 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18743 /* Data processing, three registers of different lengths. */
18744 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18745 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18746 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18747 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18748 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18749 /* If not scalar, fall back to neon_dyadic_long.
18750 Vector types as above, scalar types S16 S32 U16 U32. */
18751 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18752 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18753 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18754 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18755 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18756 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18757 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18758 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18759 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18760 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18761 /* Saturating doubling multiplies. Types S16 S32. */
18762 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18763 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18764 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18765 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18766 S16 S32 U16 U32. */
18767 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18769 /* Extract. Size 8. */
18770 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18771 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18773 /* Two registers, miscellaneous. */
18774 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18775 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18776 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18777 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18778 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18779 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18780 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18781 /* Vector replicate. Sizes 8 16 32. */
18782 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18783 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18784 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18785 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18786 /* VMOVN. Types I16 I32 I64. */
18787 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18788 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18789 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18790 /* VQMOVUN. Types S16 S32 S64. */
18791 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18792 /* VZIP / VUZP. Sizes 8 16 32. */
18793 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18794 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18795 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18796 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18797 /* VQABS / VQNEG. Types S8 S16 S32. */
18798 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18799 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18800 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18801 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18802 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18803 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18804 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18805 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18806 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18807 /* Reciprocal estimates. Types U32 F32. */
18808 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18809 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18810 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18811 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18812 /* VCLS. Types S8 S16 S32. */
18813 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18814 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18815 /* VCLZ. Types I8 I16 I32. */
18816 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18817 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18818 /* VCNT. Size 8. */
18819 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18820 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18821 /* Two address, untyped. */
18822 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18823 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18824 /* VTRN. Sizes 8 16 32. */
18825 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18826 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18828 /* Table lookup. Size 8. */
18829 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18830 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18832 #undef THUMB_VARIANT
18833 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18835 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18837 /* Neon element/structure load/store. */
18838 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18839 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18840 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18841 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18842 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18843 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18844 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18845 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18847 #undef THUMB_VARIANT
18848 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18850 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18851 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18852 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18853 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18854 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18855 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18856 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18857 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18858 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18859 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18861 #undef THUMB_VARIANT
18862 #define THUMB_VARIANT & fpu_vfp_ext_v3
18864 #define ARM_VARIANT & fpu_vfp_ext_v3
18866 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18867 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18868 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18869 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18870 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18871 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18872 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18873 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18874 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18877 #define ARM_VARIANT &fpu_vfp_ext_fma
18878 #undef THUMB_VARIANT
18879 #define THUMB_VARIANT &fpu_vfp_ext_fma
18880 /* Mnemonics shared by Neon and VFP. These are included in the
18881 VFP FMA variant; NEON and VFP FMA always includes the NEON
18882 FMA instructions. */
18883 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18884 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18885 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18886 the v form should always be used. */
18887 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18888 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18889 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18890 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18891 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18892 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18894 #undef THUMB_VARIANT
18896 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18898 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18899 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18900 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18901 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18902 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18903 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18904 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18905 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18908 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18910 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18911 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18912 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18913 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18914 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18915 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18916 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18917 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18918 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18919 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18920 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18921 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18922 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18923 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18924 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18925 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18926 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18927 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18928 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18929 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18930 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18931 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18932 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18933 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18934 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18935 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18936 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18937 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18938 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18939 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18940 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18941 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18942 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18943 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18944 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18945 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18946 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18947 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18948 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18949 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18950 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18951 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18952 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18953 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18954 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18955 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18956 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18957 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18958 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18959 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18960 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18961 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18962 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18963 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18964 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18965 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18966 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18967 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18968 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18969 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18970 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18971 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18972 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18973 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18974 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18975 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18976 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18977 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18978 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18979 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18980 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18981 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18982 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18983 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18984 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18985 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18986 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18987 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18988 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18989 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18990 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18991 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18992 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18993 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18994 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18995 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18996 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18997 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18998 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18999 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19000 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19001 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19002 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19003 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19004 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19005 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19006 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19007 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19008 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19009 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19010 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19011 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19012 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19013 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19014 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19015 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19016 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19017 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19018 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19019 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19020 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
19021 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19022 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19023 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19024 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19025 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19026 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19027 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19028 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19029 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19030 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19031 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19032 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19033 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19034 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19035 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19036 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19037 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19038 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19039 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19040 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19041 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19042 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19043 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19044 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19045 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19046 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19047 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19048 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19049 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19050 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19051 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19052 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19053 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19054 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19055 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19056 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19057 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19058 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19059 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19060 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19061 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19062 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19063 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19064 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19065 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19066 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19067 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19068 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19069 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19070 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19071 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
19074 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19076 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
19077 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
19078 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
19079 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19080 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19081 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19082 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19083 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19084 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19085 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19086 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19087 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19088 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19089 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19090 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19091 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19092 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19093 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19094 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19095 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19096 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
19097 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19098 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19099 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19100 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19101 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19102 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19103 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19104 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19105 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19106 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19107 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19108 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19109 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19110 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19111 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19112 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19113 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19114 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19115 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19116 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19117 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19118 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19119 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19120 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19121 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19122 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19123 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19124 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19125 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19126 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19127 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19128 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19129 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19130 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19131 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19132 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19135 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19137 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19138 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19139 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19140 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19141 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19142 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19143 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19144 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19145 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
19146 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
19147 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
19148 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
19149 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
19150 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
19151 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
19152 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
19153 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
19154 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
19155 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
19156 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
19157 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
19158 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
19159 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
19160 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
19161 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
19162 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
19163 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
19164 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
19165 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
19166 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
19167 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
19168 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
19169 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
19170 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
19171 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
19172 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
19173 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
19174 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
19175 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
19176 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
19177 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
19178 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
19179 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
19180 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
19181 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
19182 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
19183 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
19184 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
19185 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
19186 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
19187 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
19188 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
19189 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
19190 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
19191 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19192 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
19193 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19194 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
19195 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19196 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
19197 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
19198 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
19199 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
19200 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
19201 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19202 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
19203 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19204 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
19205 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19206 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
19207 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19208 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19209 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
19210 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
19211 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
19212 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
19215 #undef THUMB_VARIANT
19242 /* MD interface: bits in the object file. */
19244 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19245 for use in the a.out file, and stores them in the array pointed to by buf.
19246 This knows about the endian-ness of the target machine and does
19247 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19248 2 (short) and 4 (long) Floating numbers are put out as a series of
19249 LITTLENUMS (shorts, here at least). */
19252 md_number_to_chars (char * buf
, valueT val
, int n
)
19254 if (target_big_endian
)
19255 number_to_chars_bigendian (buf
, val
, n
);
19257 number_to_chars_littleendian (buf
, val
, n
);
19261 md_chars_to_number (char * buf
, int n
)
19264 unsigned char * where
= (unsigned char *) buf
;
19266 if (target_big_endian
)
19271 result
|= (*where
++ & 255);
19279 result
|= (where
[n
] & 255);
19286 /* MD interface: Sections. */
19288 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19289 that an rs_machine_dependent frag may reach. */
19292 arm_frag_max_var (fragS
*fragp
)
19294 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19295 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19297 Note that we generate relaxable instructions even for cases that don't
19298 really need it, like an immediate that's a trivial constant. So we're
19299 overestimating the instruction size for some of those cases. Rather
19300 than putting more intelligence here, it would probably be better to
19301 avoid generating a relaxation frag in the first place when it can be
19302 determined up front that a short instruction will suffice. */
19304 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
19308 /* Estimate the size of a frag before relaxing. Assume everything fits in
19312 md_estimate_size_before_relax (fragS
* fragp
,
19313 segT segtype ATTRIBUTE_UNUSED
)
19319 /* Convert a machine dependent frag. */
19322 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
19324 unsigned long insn
;
19325 unsigned long old_op
;
19333 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19335 old_op
= bfd_get_16(abfd
, buf
);
19336 if (fragp
->fr_symbol
)
19338 exp
.X_op
= O_symbol
;
19339 exp
.X_add_symbol
= fragp
->fr_symbol
;
19343 exp
.X_op
= O_constant
;
19345 exp
.X_add_number
= fragp
->fr_offset
;
19346 opcode
= fragp
->fr_subtype
;
19349 case T_MNEM_ldr_pc
:
19350 case T_MNEM_ldr_pc2
:
19351 case T_MNEM_ldr_sp
:
19352 case T_MNEM_str_sp
:
19359 if (fragp
->fr_var
== 4)
19361 insn
= THUMB_OP32 (opcode
);
19362 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
19364 insn
|= (old_op
& 0x700) << 4;
19368 insn
|= (old_op
& 7) << 12;
19369 insn
|= (old_op
& 0x38) << 13;
19371 insn
|= 0x00000c00;
19372 put_thumb32_insn (buf
, insn
);
19373 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
19377 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
19379 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
19382 if (fragp
->fr_var
== 4)
19384 insn
= THUMB_OP32 (opcode
);
19385 insn
|= (old_op
& 0xf0) << 4;
19386 put_thumb32_insn (buf
, insn
);
19387 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
19391 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19392 exp
.X_add_number
-= 4;
19400 if (fragp
->fr_var
== 4)
19402 int r0off
= (opcode
== T_MNEM_mov
19403 || opcode
== T_MNEM_movs
) ? 0 : 8;
19404 insn
= THUMB_OP32 (opcode
);
19405 insn
= (insn
& 0xe1ffffff) | 0x10000000;
19406 insn
|= (old_op
& 0x700) << r0off
;
19407 put_thumb32_insn (buf
, insn
);
19408 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19412 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
19417 if (fragp
->fr_var
== 4)
19419 insn
= THUMB_OP32(opcode
);
19420 put_thumb32_insn (buf
, insn
);
19421 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
19424 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
19428 if (fragp
->fr_var
== 4)
19430 insn
= THUMB_OP32(opcode
);
19431 insn
|= (old_op
& 0xf00) << 14;
19432 put_thumb32_insn (buf
, insn
);
19433 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19436 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19439 case T_MNEM_add_sp
:
19440 case T_MNEM_add_pc
:
19441 case T_MNEM_inc_sp
:
19442 case T_MNEM_dec_sp
:
19443 if (fragp
->fr_var
== 4)
19445 /* ??? Choose between add and addw. */
19446 insn
= THUMB_OP32 (opcode
);
19447 insn
|= (old_op
& 0xf0) << 4;
19448 put_thumb32_insn (buf
, insn
);
19449 if (opcode
== T_MNEM_add_pc
)
19450 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
19452 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19455 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19463 if (fragp
->fr_var
== 4)
19465 insn
= THUMB_OP32 (opcode
);
19466 insn
|= (old_op
& 0xf0) << 4;
19467 insn
|= (old_op
& 0xf) << 16;
19468 put_thumb32_insn (buf
, insn
);
19469 if (insn
& (1 << 20))
19470 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19472 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19475 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19481 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
19482 (enum bfd_reloc_code_real
) reloc_type
);
19483 fixp
->fx_file
= fragp
->fr_file
;
19484 fixp
->fx_line
= fragp
->fr_line
;
19485 fragp
->fr_fix
+= fragp
->fr_var
;
19488 /* Return the size of a relaxable immediate operand instruction.
19489 SHIFT and SIZE specify the form of the allowable immediate. */
19491 relax_immediate (fragS
*fragp
, int size
, int shift
)
19497 /* ??? Should be able to do better than this. */
19498 if (fragp
->fr_symbol
)
19501 low
= (1 << shift
) - 1;
19502 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19503 offset
= fragp
->fr_offset
;
19504 /* Force misaligned offsets to 32-bit variant. */
19507 if (offset
& ~mask
)
19512 /* Get the address of a symbol during relaxation. */
19514 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19520 sym
= fragp
->fr_symbol
;
19521 sym_frag
= symbol_get_frag (sym
);
19522 know (S_GET_SEGMENT (sym
) != absolute_section
19523 || sym_frag
== &zero_address_frag
);
19524 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19526 /* If frag has yet to be reached on this pass, assume it will
19527 move by STRETCH just as we did. If this is not so, it will
19528 be because some frag between grows, and that will force
19532 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19536 /* Adjust stretch for any alignment frag. Note that if have
19537 been expanding the earlier code, the symbol may be
19538 defined in what appears to be an earlier frag. FIXME:
19539 This doesn't handle the fr_subtype field, which specifies
19540 a maximum number of bytes to skip when doing an
19542 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19544 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19547 stretch
= - ((- stretch
)
19548 & ~ ((1 << (int) f
->fr_offset
) - 1));
19550 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19562 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19565 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19570 /* Assume worst case for symbols not known to be in the same section. */
19571 if (fragp
->fr_symbol
== NULL
19572 || !S_IS_DEFINED (fragp
->fr_symbol
)
19573 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19574 || S_IS_WEAK (fragp
->fr_symbol
))
19577 val
= relaxed_symbol_addr (fragp
, stretch
);
19578 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19579 addr
= (addr
+ 4) & ~3;
19580 /* Force misaligned targets to 32-bit variant. */
19584 if (val
< 0 || val
> 1020)
19589 /* Return the size of a relaxable add/sub immediate instruction. */
19591 relax_addsub (fragS
*fragp
, asection
*sec
)
19596 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19597 op
= bfd_get_16(sec
->owner
, buf
);
19598 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19599 return relax_immediate (fragp
, 8, 0);
19601 return relax_immediate (fragp
, 3, 0);
19605 /* Return the size of a relaxable branch instruction. BITS is the
19606 size of the offset field in the narrow instruction. */
19609 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19615 /* Assume worst case for symbols not known to be in the same section. */
19616 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19617 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19618 || S_IS_WEAK (fragp
->fr_symbol
))
19622 if (S_IS_DEFINED (fragp
->fr_symbol
)
19623 && ARM_IS_FUNC (fragp
->fr_symbol
))
19626 /* PR 12532. Global symbols with default visibility might
19627 be preempted, so do not relax relocations to them. */
19628 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19629 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19633 val
= relaxed_symbol_addr (fragp
, stretch
);
19634 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19637 /* Offset is a signed value *2 */
19639 if (val
>= limit
|| val
< -limit
)
19645 /* Relax a machine dependent frag. This returns the amount by which
19646 the current size of the frag should change. */
19649 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19654 oldsize
= fragp
->fr_var
;
19655 switch (fragp
->fr_subtype
)
19657 case T_MNEM_ldr_pc2
:
19658 newsize
= relax_adr (fragp
, sec
, stretch
);
19660 case T_MNEM_ldr_pc
:
19661 case T_MNEM_ldr_sp
:
19662 case T_MNEM_str_sp
:
19663 newsize
= relax_immediate (fragp
, 8, 2);
19667 newsize
= relax_immediate (fragp
, 5, 2);
19671 newsize
= relax_immediate (fragp
, 5, 1);
19675 newsize
= relax_immediate (fragp
, 5, 0);
19678 newsize
= relax_adr (fragp
, sec
, stretch
);
19684 newsize
= relax_immediate (fragp
, 8, 0);
19687 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19690 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19692 case T_MNEM_add_sp
:
19693 case T_MNEM_add_pc
:
19694 newsize
= relax_immediate (fragp
, 8, 2);
19696 case T_MNEM_inc_sp
:
19697 case T_MNEM_dec_sp
:
19698 newsize
= relax_immediate (fragp
, 7, 2);
19704 newsize
= relax_addsub (fragp
, sec
);
19710 fragp
->fr_var
= newsize
;
19711 /* Freeze wide instructions that are at or before the same location as
19712 in the previous pass. This avoids infinite loops.
19713 Don't freeze them unconditionally because targets may be artificially
19714 misaligned by the expansion of preceding frags. */
19715 if (stretch
<= 0 && newsize
> 2)
19717 md_convert_frag (sec
->owner
, sec
, fragp
);
19721 return newsize
- oldsize
;
19724 /* Round up a section size to the appropriate boundary. */
19727 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19730 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19731 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19733 /* For a.out, force the section size to be aligned. If we don't do
19734 this, BFD will align it for us, but it will not write out the
19735 final bytes of the section. This may be a bug in BFD, but it is
19736 easier to fix it here since that is how the other a.out targets
19740 align
= bfd_get_section_alignment (stdoutput
, segment
);
19741 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19748 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19749 of an rs_align_code fragment. */
19752 arm_handle_align (fragS
* fragP
)
19754 static char const arm_noop
[2][2][4] =
19757 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19758 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19761 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19762 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19765 static char const thumb_noop
[2][2][2] =
19768 {0xc0, 0x46}, /* LE */
19769 {0x46, 0xc0}, /* BE */
19772 {0x00, 0xbf}, /* LE */
19773 {0xbf, 0x00} /* BE */
19776 static char const wide_thumb_noop
[2][4] =
19777 { /* Wide Thumb-2 */
19778 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19779 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19782 unsigned bytes
, fix
, noop_size
;
19785 const char *narrow_noop
= NULL
;
19790 if (fragP
->fr_type
!= rs_align_code
)
19793 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19794 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19797 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19798 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19800 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19802 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19804 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19806 narrow_noop
= thumb_noop
[1][target_big_endian
];
19807 noop
= wide_thumb_noop
[target_big_endian
];
19810 noop
= thumb_noop
[0][target_big_endian
];
19818 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19819 [target_big_endian
];
19826 fragP
->fr_var
= noop_size
;
19828 if (bytes
& (noop_size
- 1))
19830 fix
= bytes
& (noop_size
- 1);
19832 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19834 memset (p
, 0, fix
);
19841 if (bytes
& noop_size
)
19843 /* Insert a narrow noop. */
19844 memcpy (p
, narrow_noop
, noop_size
);
19846 bytes
-= noop_size
;
19850 /* Use wide noops for the remainder */
19854 while (bytes
>= noop_size
)
19856 memcpy (p
, noop
, noop_size
);
19858 bytes
-= noop_size
;
19862 fragP
->fr_fix
+= fix
;
19865 /* Called from md_do_align. Used to create an alignment
19866 frag in a code section. */
19869 arm_frag_align_code (int n
, int max
)
19873 /* We assume that there will never be a requirement
19874 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19875 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19880 _("alignments greater than %d bytes not supported in .text sections."),
19881 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19882 as_fatal ("%s", err_msg
);
19885 p
= frag_var (rs_align_code
,
19886 MAX_MEM_FOR_RS_ALIGN_CODE
,
19888 (relax_substateT
) max
,
19895 /* Perform target specific initialisation of a frag.
19896 Note - despite the name this initialisation is not done when the frag
19897 is created, but only when its type is assigned. A frag can be created
19898 and used a long time before its type is set, so beware of assuming that
19899 this initialisationis performed first. */
19903 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19905 /* Record whether this frag is in an ARM or a THUMB area. */
19906 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19909 #else /* OBJ_ELF is defined. */
19911 arm_init_frag (fragS
* fragP
, int max_chars
)
19913 /* If the current ARM vs THUMB mode has not already
19914 been recorded into this frag then do so now. */
19915 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19917 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19919 /* Record a mapping symbol for alignment frags. We will delete this
19920 later if the alignment ends up empty. */
19921 switch (fragP
->fr_type
)
19924 case rs_align_test
:
19926 mapping_state_2 (MAP_DATA
, max_chars
);
19928 case rs_align_code
:
19929 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19937 /* When we change sections we need to issue a new mapping symbol. */
19940 arm_elf_change_section (void)
19942 /* Link an unlinked unwind index table section to the .text section. */
19943 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19944 && elf_linked_to_section (now_seg
) == NULL
)
19945 elf_linked_to_section (now_seg
) = text_section
;
19949 arm_elf_section_type (const char * str
, size_t len
)
19951 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19952 return SHT_ARM_EXIDX
;
19957 /* Code to deal with unwinding tables. */
19959 static void add_unwind_adjustsp (offsetT
);
19961 /* Generate any deferred unwind frame offset. */
19964 flush_pending_unwind (void)
19968 offset
= unwind
.pending_offset
;
19969 unwind
.pending_offset
= 0;
19971 add_unwind_adjustsp (offset
);
19974 /* Add an opcode to this list for this function. Two-byte opcodes should
19975 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19979 add_unwind_opcode (valueT op
, int length
)
19981 /* Add any deferred stack adjustment. */
19982 if (unwind
.pending_offset
)
19983 flush_pending_unwind ();
19985 unwind
.sp_restored
= 0;
19987 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19989 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19990 if (unwind
.opcodes
)
19991 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19992 unwind
.opcode_alloc
);
19994 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19999 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
20001 unwind
.opcode_count
++;
20005 /* Add unwind opcodes to adjust the stack pointer. */
20008 add_unwind_adjustsp (offsetT offset
)
20012 if (offset
> 0x200)
20014 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20019 /* Long form: 0xb2, uleb128. */
20020 /* This might not fit in a word so add the individual bytes,
20021 remembering the list is built in reverse order. */
20022 o
= (valueT
) ((offset
- 0x204) >> 2);
20024 add_unwind_opcode (0, 1);
20026 /* Calculate the uleb128 encoding of the offset. */
20030 bytes
[n
] = o
& 0x7f;
20036 /* Add the insn. */
20038 add_unwind_opcode (bytes
[n
- 1], 1);
20039 add_unwind_opcode (0xb2, 1);
20041 else if (offset
> 0x100)
20043 /* Two short opcodes. */
20044 add_unwind_opcode (0x3f, 1);
20045 op
= (offset
- 0x104) >> 2;
20046 add_unwind_opcode (op
, 1);
20048 else if (offset
> 0)
20050 /* Short opcode. */
20051 op
= (offset
- 4) >> 2;
20052 add_unwind_opcode (op
, 1);
20054 else if (offset
< 0)
20057 while (offset
> 0x100)
20059 add_unwind_opcode (0x7f, 1);
20062 op
= ((offset
- 4) >> 2) | 0x40;
20063 add_unwind_opcode (op
, 1);
20067 /* Finish the list of unwind opcodes for this function. */
20069 finish_unwind_opcodes (void)
20073 if (unwind
.fp_used
)
20075 /* Adjust sp as necessary. */
20076 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
20077 flush_pending_unwind ();
20079 /* After restoring sp from the frame pointer. */
20080 op
= 0x90 | unwind
.fp_reg
;
20081 add_unwind_opcode (op
, 1);
20084 flush_pending_unwind ();
20088 /* Start an exception table entry. If idx is nonzero this is an index table
20092 start_unwind_section (const segT text_seg
, int idx
)
20094 const char * text_name
;
20095 const char * prefix
;
20096 const char * prefix_once
;
20097 const char * group_name
;
20101 size_t sec_name_len
;
20108 prefix
= ELF_STRING_ARM_unwind
;
20109 prefix_once
= ELF_STRING_ARM_unwind_once
;
20110 type
= SHT_ARM_EXIDX
;
20114 prefix
= ELF_STRING_ARM_unwind_info
;
20115 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
20116 type
= SHT_PROGBITS
;
20119 text_name
= segment_name (text_seg
);
20120 if (streq (text_name
, ".text"))
20123 if (strncmp (text_name
, ".gnu.linkonce.t.",
20124 strlen (".gnu.linkonce.t.")) == 0)
20126 prefix
= prefix_once
;
20127 text_name
+= strlen (".gnu.linkonce.t.");
20130 prefix_len
= strlen (prefix
);
20131 text_len
= strlen (text_name
);
20132 sec_name_len
= prefix_len
+ text_len
;
20133 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
20134 memcpy (sec_name
, prefix
, prefix_len
);
20135 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
20136 sec_name
[prefix_len
+ text_len
] = '\0';
20142 /* Handle COMDAT group. */
20143 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
20145 group_name
= elf_group_name (text_seg
);
20146 if (group_name
== NULL
)
20148 as_bad (_("Group section `%s' has no group signature"),
20149 segment_name (text_seg
));
20150 ignore_rest_of_line ();
20153 flags
|= SHF_GROUP
;
20157 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
20159 /* Set the section link for index tables. */
20161 elf_linked_to_section (now_seg
) = text_seg
;
20165 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20166 personality routine data. Returns zero, or the index table value for
20167 and inline entry. */
20170 create_unwind_entry (int have_data
)
20175 /* The current word of data. */
20177 /* The number of bytes left in this word. */
20180 finish_unwind_opcodes ();
20182 /* Remember the current text section. */
20183 unwind
.saved_seg
= now_seg
;
20184 unwind
.saved_subseg
= now_subseg
;
20186 start_unwind_section (now_seg
, 0);
20188 if (unwind
.personality_routine
== NULL
)
20190 if (unwind
.personality_index
== -2)
20193 as_bad (_("handlerdata in cantunwind frame"));
20194 return 1; /* EXIDX_CANTUNWIND. */
20197 /* Use a default personality routine if none is specified. */
20198 if (unwind
.personality_index
== -1)
20200 if (unwind
.opcode_count
> 3)
20201 unwind
.personality_index
= 1;
20203 unwind
.personality_index
= 0;
20206 /* Space for the personality routine entry. */
20207 if (unwind
.personality_index
== 0)
20209 if (unwind
.opcode_count
> 3)
20210 as_bad (_("too many unwind opcodes for personality routine 0"));
20214 /* All the data is inline in the index table. */
20217 while (unwind
.opcode_count
> 0)
20219 unwind
.opcode_count
--;
20220 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
20224 /* Pad with "finish" opcodes. */
20226 data
= (data
<< 8) | 0xb0;
20233 /* We get two opcodes "free" in the first word. */
20234 size
= unwind
.opcode_count
- 2;
20238 gas_assert (unwind
.personality_index
== -1);
20240 /* An extra byte is required for the opcode count. */
20241 size
= unwind
.opcode_count
+ 1;
20244 size
= (size
+ 3) >> 2;
20246 as_bad (_("too many unwind opcodes"));
20248 frag_align (2, 0, 0);
20249 record_alignment (now_seg
, 2);
20250 unwind
.table_entry
= expr_build_dot ();
20252 /* Allocate the table entry. */
20253 ptr
= frag_more ((size
<< 2) + 4);
20254 /* PR 13449: Zero the table entries in case some of them are not used. */
20255 memset (ptr
, 0, (size
<< 2) + 4);
20256 where
= frag_now_fix () - ((size
<< 2) + 4);
20258 switch (unwind
.personality_index
)
20261 /* ??? Should this be a PLT generating relocation? */
20262 /* Custom personality routine. */
20263 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
20264 BFD_RELOC_ARM_PREL31
);
20269 /* Set the first byte to the number of additional words. */
20270 data
= size
> 0 ? size
- 1 : 0;
20274 /* ABI defined personality routines. */
20276 /* Three opcodes bytes are packed into the first word. */
20283 /* The size and first two opcode bytes go in the first word. */
20284 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
20289 /* Should never happen. */
20293 /* Pack the opcodes into words (MSB first), reversing the list at the same
20295 while (unwind
.opcode_count
> 0)
20299 md_number_to_chars (ptr
, data
, 4);
20304 unwind
.opcode_count
--;
20306 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
20309 /* Finish off the last word. */
20312 /* Pad with "finish" opcodes. */
20314 data
= (data
<< 8) | 0xb0;
20316 md_number_to_chars (ptr
, data
, 4);
20321 /* Add an empty descriptor if there is no user-specified data. */
20322 ptr
= frag_more (4);
20323 md_number_to_chars (ptr
, 0, 4);
20330 /* Initialize the DWARF-2 unwind information for this procedure. */
20333 tc_arm_frame_initial_instructions (void)
20335 cfi_add_CFA_def_cfa (REG_SP
, 0);
20337 #endif /* OBJ_ELF */
20339 /* Convert REGNAME to a DWARF-2 register number. */
20342 tc_arm_regname_to_dw2regnum (char *regname
)
20344 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
20354 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
20358 exp
.X_op
= O_secrel
;
20359 exp
.X_add_symbol
= symbol
;
20360 exp
.X_add_number
= 0;
20361 emit_expr (&exp
, size
);
20365 /* MD interface: Symbol and relocation handling. */
20367 /* Return the address within the segment that a PC-relative fixup is
20368 relative to. For ARM, PC-relative fixups applied to instructions
20369 are generally relative to the location of the fixup plus 8 bytes.
20370 Thumb branches are offset by 4, and Thumb loads relative to PC
20371 require special handling. */
20374 md_pcrel_from_section (fixS
* fixP
, segT seg
)
20376 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20378 /* If this is pc-relative and we are going to emit a relocation
20379 then we just want to put out any pipeline compensation that the linker
20380 will need. Otherwise we want to use the calculated base.
20381 For WinCE we skip the bias for externals as well, since this
20382 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20384 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20385 || (arm_force_relocation (fixP
)
20387 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20393 switch (fixP
->fx_r_type
)
20395 /* PC relative addressing on the Thumb is slightly odd as the
20396 bottom two bits of the PC are forced to zero for the
20397 calculation. This happens *after* application of the
20398 pipeline offset. However, Thumb adrl already adjusts for
20399 this, so we need not do it again. */
20400 case BFD_RELOC_ARM_THUMB_ADD
:
20403 case BFD_RELOC_ARM_THUMB_OFFSET
:
20404 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20405 case BFD_RELOC_ARM_T32_ADD_PC12
:
20406 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20407 return (base
+ 4) & ~3;
20409 /* Thumb branches are simply offset by +4. */
20410 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20411 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20412 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20413 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20414 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20417 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20419 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20420 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20421 && ARM_IS_FUNC (fixP
->fx_addsy
)
20422 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20423 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20426 /* BLX is like branches above, but forces the low two bits of PC to
20428 case BFD_RELOC_THUMB_PCREL_BLX
:
20430 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20431 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20432 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20433 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20434 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20435 return (base
+ 4) & ~3;
20437 /* ARM mode branches are offset by +8. However, the Windows CE
20438 loader expects the relocation not to take this into account. */
20439 case BFD_RELOC_ARM_PCREL_BLX
:
20441 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20442 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20443 && ARM_IS_FUNC (fixP
->fx_addsy
)
20444 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20445 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20448 case BFD_RELOC_ARM_PCREL_CALL
:
20450 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20451 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20452 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20453 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20454 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20457 case BFD_RELOC_ARM_PCREL_BRANCH
:
20458 case BFD_RELOC_ARM_PCREL_JUMP
:
20459 case BFD_RELOC_ARM_PLT32
:
20461 /* When handling fixups immediately, because we have already
20462 discovered the value of a symbol, or the address of the frag involved
20463 we must account for the offset by +8, as the OS loader will never see the reloc.
20464 see fixup_segment() in write.c
20465 The S_IS_EXTERNAL test handles the case of global symbols.
20466 Those need the calculated base, not just the pipe compensation the linker will need. */
20468 && fixP
->fx_addsy
!= NULL
20469 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20470 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
20478 /* ARM mode loads relative to PC are also offset by +8. Unlike
20479 branches, the Windows CE loader *does* expect the relocation
20480 to take this into account. */
20481 case BFD_RELOC_ARM_OFFSET_IMM
:
20482 case BFD_RELOC_ARM_OFFSET_IMM8
:
20483 case BFD_RELOC_ARM_HWLITERAL
:
20484 case BFD_RELOC_ARM_LITERAL
:
20485 case BFD_RELOC_ARM_CP_OFF_IMM
:
20489 /* Other PC-relative relocations are un-offset. */
20495 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20496 Otherwise we have no need to default values of symbols. */
20499 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20502 if (name
[0] == '_' && name
[1] == 'G'
20503 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20507 if (symbol_find (name
))
20508 as_bad (_("GOT already in the symbol table"));
20510 GOT_symbol
= symbol_new (name
, undefined_section
,
20511 (valueT
) 0, & zero_address_frag
);
20521 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20522 computed as two separate immediate values, added together. We
20523 already know that this value cannot be computed by just one ARM
20526 static unsigned int
20527 validate_immediate_twopart (unsigned int val
,
20528 unsigned int * highpart
)
20533 for (i
= 0; i
< 32; i
+= 2)
20534 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20540 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20542 else if (a
& 0xff0000)
20544 if (a
& 0xff000000)
20546 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20550 gas_assert (a
& 0xff000000);
20551 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20554 return (a
& 0xff) | (i
<< 7);
20561 validate_offset_imm (unsigned int val
, int hwse
)
20563 if ((hwse
&& val
> 255) || val
> 4095)
20568 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20569 negative immediate constant by altering the instruction. A bit of
20574 by inverting the second operand, and
20577 by negating the second operand. */
20580 negate_data_op (unsigned long * instruction
,
20581 unsigned long value
)
20584 unsigned long negated
, inverted
;
20586 negated
= encode_arm_immediate (-value
);
20587 inverted
= encode_arm_immediate (~value
);
20589 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20592 /* First negates. */
20593 case OPCODE_SUB
: /* ADD <-> SUB */
20594 new_inst
= OPCODE_ADD
;
20599 new_inst
= OPCODE_SUB
;
20603 case OPCODE_CMP
: /* CMP <-> CMN */
20604 new_inst
= OPCODE_CMN
;
20609 new_inst
= OPCODE_CMP
;
20613 /* Now Inverted ops. */
20614 case OPCODE_MOV
: /* MOV <-> MVN */
20615 new_inst
= OPCODE_MVN
;
20620 new_inst
= OPCODE_MOV
;
20624 case OPCODE_AND
: /* AND <-> BIC */
20625 new_inst
= OPCODE_BIC
;
20630 new_inst
= OPCODE_AND
;
20634 case OPCODE_ADC
: /* ADC <-> SBC */
20635 new_inst
= OPCODE_SBC
;
20640 new_inst
= OPCODE_ADC
;
20644 /* We cannot do anything. */
20649 if (value
== (unsigned) FAIL
)
20652 *instruction
&= OPCODE_MASK
;
20653 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20657 /* Like negate_data_op, but for Thumb-2. */
20659 static unsigned int
20660 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20664 unsigned int negated
, inverted
;
20666 negated
= encode_thumb32_immediate (-value
);
20667 inverted
= encode_thumb32_immediate (~value
);
20669 rd
= (*instruction
>> 8) & 0xf;
20670 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20673 /* ADD <-> SUB. Includes CMP <-> CMN. */
20674 case T2_OPCODE_SUB
:
20675 new_inst
= T2_OPCODE_ADD
;
20679 case T2_OPCODE_ADD
:
20680 new_inst
= T2_OPCODE_SUB
;
20684 /* ORR <-> ORN. Includes MOV <-> MVN. */
20685 case T2_OPCODE_ORR
:
20686 new_inst
= T2_OPCODE_ORN
;
20690 case T2_OPCODE_ORN
:
20691 new_inst
= T2_OPCODE_ORR
;
20695 /* AND <-> BIC. TST has no inverted equivalent. */
20696 case T2_OPCODE_AND
:
20697 new_inst
= T2_OPCODE_BIC
;
20704 case T2_OPCODE_BIC
:
20705 new_inst
= T2_OPCODE_AND
;
20710 case T2_OPCODE_ADC
:
20711 new_inst
= T2_OPCODE_SBC
;
20715 case T2_OPCODE_SBC
:
20716 new_inst
= T2_OPCODE_ADC
;
20720 /* We cannot do anything. */
20725 if (value
== (unsigned int)FAIL
)
20728 *instruction
&= T2_OPCODE_MASK
;
20729 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20733 /* Read a 32-bit thumb instruction from buf. */
20734 static unsigned long
20735 get_thumb32_insn (char * buf
)
20737 unsigned long insn
;
20738 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20739 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20745 /* We usually want to set the low bit on the address of thumb function
20746 symbols. In particular .word foo - . should have the low bit set.
20747 Generic code tries to fold the difference of two symbols to
20748 a constant. Prevent this and force a relocation when the first symbols
20749 is a thumb function. */
20752 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20754 if (op
== O_subtract
20755 && l
->X_op
== O_symbol
20756 && r
->X_op
== O_symbol
20757 && THUMB_IS_FUNC (l
->X_add_symbol
))
20759 l
->X_op
= O_subtract
;
20760 l
->X_op_symbol
= r
->X_add_symbol
;
20761 l
->X_add_number
-= r
->X_add_number
;
20765 /* Process as normal. */
20769 /* Encode Thumb2 unconditional branches and calls. The encoding
20770 for the 2 are identical for the immediate values. */
20773 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20775 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20778 addressT S
, I1
, I2
, lo
, hi
;
20780 S
= (value
>> 24) & 0x01;
20781 I1
= (value
>> 23) & 0x01;
20782 I2
= (value
>> 22) & 0x01;
20783 hi
= (value
>> 12) & 0x3ff;
20784 lo
= (value
>> 1) & 0x7ff;
20785 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20786 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20787 newval
|= (S
<< 10) | hi
;
20788 newval2
&= ~T2I1I2MASK
;
20789 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20790 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20791 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20795 md_apply_fix (fixS
* fixP
,
20799 offsetT value
= * valP
;
20801 unsigned int newimm
;
20802 unsigned long temp
;
20804 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20806 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20808 /* Note whether this will delete the relocation. */
20810 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20813 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20814 consistency with the behaviour on 32-bit hosts. Remember value
20816 value
&= 0xffffffff;
20817 value
^= 0x80000000;
20818 value
-= 0x80000000;
20821 fixP
->fx_addnumber
= value
;
20823 /* Same treatment for fixP->fx_offset. */
20824 fixP
->fx_offset
&= 0xffffffff;
20825 fixP
->fx_offset
^= 0x80000000;
20826 fixP
->fx_offset
-= 0x80000000;
20828 switch (fixP
->fx_r_type
)
20830 case BFD_RELOC_NONE
:
20831 /* This will need to go in the object file. */
20835 case BFD_RELOC_ARM_IMMEDIATE
:
20836 /* We claim that this fixup has been processed here,
20837 even if in fact we generate an error because we do
20838 not have a reloc for it, so tc_gen_reloc will reject it. */
20841 if (fixP
->fx_addsy
)
20843 const char *msg
= 0;
20845 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20846 msg
= _("undefined symbol %s used as an immediate value");
20847 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20848 msg
= _("symbol %s is in a different section");
20849 else if (S_IS_WEAK (fixP
->fx_addsy
))
20850 msg
= _("symbol %s is weak and may be overridden later");
20854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20855 msg
, S_GET_NAME (fixP
->fx_addsy
));
20860 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20862 /* If the offset is negative, we should use encoding A2 for ADR. */
20863 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
20864 newimm
= negate_data_op (&temp
, value
);
20867 newimm
= encode_arm_immediate (value
);
20869 /* If the instruction will fail, see if we can fix things up by
20870 changing the opcode. */
20871 if (newimm
== (unsigned int) FAIL
)
20872 newimm
= negate_data_op (&temp
, value
);
20875 if (newimm
== (unsigned int) FAIL
)
20877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20878 _("invalid constant (%lx) after fixup"),
20879 (unsigned long) value
);
20883 newimm
|= (temp
& 0xfffff000);
20884 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20887 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20889 unsigned int highpart
= 0;
20890 unsigned int newinsn
= 0xe1a00000; /* nop. */
20892 if (fixP
->fx_addsy
)
20894 const char *msg
= 0;
20896 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20897 msg
= _("undefined symbol %s used as an immediate value");
20898 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20899 msg
= _("symbol %s is in a different section");
20900 else if (S_IS_WEAK (fixP
->fx_addsy
))
20901 msg
= _("symbol %s is weak and may be overridden later");
20905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20906 msg
, S_GET_NAME (fixP
->fx_addsy
));
20911 newimm
= encode_arm_immediate (value
);
20912 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20914 /* If the instruction will fail, see if we can fix things up by
20915 changing the opcode. */
20916 if (newimm
== (unsigned int) FAIL
20917 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20919 /* No ? OK - try using two ADD instructions to generate
20921 newimm
= validate_immediate_twopart (value
, & highpart
);
20923 /* Yes - then make sure that the second instruction is
20925 if (newimm
!= (unsigned int) FAIL
)
20927 /* Still No ? Try using a negated value. */
20928 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20929 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20930 /* Otherwise - give up. */
20933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20934 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20939 /* Replace the first operand in the 2nd instruction (which
20940 is the PC) with the destination register. We have
20941 already added in the PC in the first instruction and we
20942 do not want to do it again. */
20943 newinsn
&= ~ 0xf0000;
20944 newinsn
|= ((newinsn
& 0x0f000) << 4);
20947 newimm
|= (temp
& 0xfffff000);
20948 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20950 highpart
|= (newinsn
& 0xfffff000);
20951 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20955 case BFD_RELOC_ARM_OFFSET_IMM
:
20956 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20959 case BFD_RELOC_ARM_LITERAL
:
20965 if (validate_offset_imm (value
, 0) == FAIL
)
20967 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20969 _("invalid literal constant: pool needs to be closer"));
20971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20972 _("bad immediate value for offset (%ld)"),
20977 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20979 newval
&= 0xfffff000;
20982 newval
&= 0xff7ff000;
20983 newval
|= value
| (sign
? INDEX_UP
: 0);
20985 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20988 case BFD_RELOC_ARM_OFFSET_IMM8
:
20989 case BFD_RELOC_ARM_HWLITERAL
:
20995 if (validate_offset_imm (value
, 1) == FAIL
)
20997 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20999 _("invalid literal constant: pool needs to be closer"));
21001 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
21006 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21008 newval
&= 0xfffff0f0;
21011 newval
&= 0xff7ff0f0;
21012 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
21014 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21017 case BFD_RELOC_ARM_T32_OFFSET_U8
:
21018 if (value
< 0 || value
> 1020 || value
% 4 != 0)
21019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21020 _("bad immediate value for offset (%ld)"), (long) value
);
21023 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
21025 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
21028 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21029 /* This is a complicated relocation used for all varieties of Thumb32
21030 load/store instruction with immediate offset:
21032 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21033 *4, optional writeback(W)
21034 (doubleword load/store)
21036 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21037 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21038 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21039 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21040 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21042 Uppercase letters indicate bits that are already encoded at
21043 this point. Lowercase letters are our problem. For the
21044 second block of instructions, the secondary opcode nybble
21045 (bits 8..11) is present, and bit 23 is zero, even if this is
21046 a PC-relative operation. */
21047 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21049 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
21051 if ((newval
& 0xf0000000) == 0xe0000000)
21053 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21055 newval
|= (1 << 23);
21058 if (value
% 4 != 0)
21060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21061 _("offset not a multiple of 4"));
21067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21068 _("offset out of range"));
21073 else if ((newval
& 0x000f0000) == 0x000f0000)
21075 /* PC-relative, 12-bit offset. */
21077 newval
|= (1 << 23);
21082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21083 _("offset out of range"));
21088 else if ((newval
& 0x00000100) == 0x00000100)
21090 /* Writeback: 8-bit, +/- offset. */
21092 newval
|= (1 << 9);
21097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21098 _("offset out of range"));
21103 else if ((newval
& 0x00000f00) == 0x00000e00)
21105 /* T-instruction: positive 8-bit offset. */
21106 if (value
< 0 || value
> 0xff)
21108 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21109 _("offset out of range"));
21117 /* Positive 12-bit or negative 8-bit offset. */
21121 newval
|= (1 << 23);
21131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21132 _("offset out of range"));
21139 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
21140 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
21143 case BFD_RELOC_ARM_SHIFT_IMM
:
21144 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21145 if (((unsigned long) value
) > 32
21147 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
21149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21150 _("shift expression is too large"));
21155 /* Shifts of zero must be done as lsl. */
21157 else if (value
== 32)
21159 newval
&= 0xfffff07f;
21160 newval
|= (value
& 0x1f) << 7;
21161 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21164 case BFD_RELOC_ARM_T32_IMMEDIATE
:
21165 case BFD_RELOC_ARM_T32_ADD_IMM
:
21166 case BFD_RELOC_ARM_T32_IMM12
:
21167 case BFD_RELOC_ARM_T32_ADD_PC12
:
21168 /* We claim that this fixup has been processed here,
21169 even if in fact we generate an error because we do
21170 not have a reloc for it, so tc_gen_reloc will reject it. */
21174 && ! S_IS_DEFINED (fixP
->fx_addsy
))
21176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21177 _("undefined symbol %s used as an immediate value"),
21178 S_GET_NAME (fixP
->fx_addsy
));
21182 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21184 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
21187 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21188 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
21190 newimm
= encode_thumb32_immediate (value
);
21191 if (newimm
== (unsigned int) FAIL
)
21192 newimm
= thumb32_negate_data_op (&newval
, value
);
21194 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
21195 && newimm
== (unsigned int) FAIL
)
21197 /* Turn add/sum into addw/subw. */
21198 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
21199 newval
= (newval
& 0xfeffffff) | 0x02000000;
21200 /* No flat 12-bit imm encoding for addsw/subsw. */
21201 if ((newval
& 0x00100000) == 0)
21203 /* 12 bit immediate for addw/subw. */
21207 newval
^= 0x00a00000;
21210 newimm
= (unsigned int) FAIL
;
21216 if (newimm
== (unsigned int)FAIL
)
21218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21219 _("invalid constant (%lx) after fixup"),
21220 (unsigned long) value
);
21224 newval
|= (newimm
& 0x800) << 15;
21225 newval
|= (newimm
& 0x700) << 4;
21226 newval
|= (newimm
& 0x0ff);
21228 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
21229 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
21232 case BFD_RELOC_ARM_SMC
:
21233 if (((unsigned long) value
) > 0xffff)
21234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21235 _("invalid smc expression"));
21236 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21237 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
21238 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21241 case BFD_RELOC_ARM_HVC
:
21242 if (((unsigned long) value
) > 0xffff)
21243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21244 _("invalid hvc expression"));
21245 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21246 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
21247 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21250 case BFD_RELOC_ARM_SWI
:
21251 if (fixP
->tc_fix_data
!= 0)
21253 if (((unsigned long) value
) > 0xff)
21254 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21255 _("invalid swi expression"));
21256 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21258 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21262 if (((unsigned long) value
) > 0x00ffffff)
21263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21264 _("invalid swi expression"));
21265 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21267 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21271 case BFD_RELOC_ARM_MULTI
:
21272 if (((unsigned long) value
) > 0xffff)
21273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21274 _("invalid expression in load/store multiple"));
21275 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
21276 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21280 case BFD_RELOC_ARM_PCREL_CALL
:
21282 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21284 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21285 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21286 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21287 /* Flip the bl to blx. This is a simple flip
21288 bit here because we generate PCREL_CALL for
21289 unconditional bls. */
21291 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21292 newval
= newval
| 0x10000000;
21293 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21299 goto arm_branch_common
;
21301 case BFD_RELOC_ARM_PCREL_JUMP
:
21302 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21304 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21305 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21306 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21308 /* This would map to a bl<cond>, b<cond>,
21309 b<always> to a Thumb function. We
21310 need to force a relocation for this particular
21312 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21316 case BFD_RELOC_ARM_PLT32
:
21318 case BFD_RELOC_ARM_PCREL_BRANCH
:
21320 goto arm_branch_common
;
21322 case BFD_RELOC_ARM_PCREL_BLX
:
21325 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21327 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21328 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21329 && ARM_IS_FUNC (fixP
->fx_addsy
))
21331 /* Flip the blx to a bl and warn. */
21332 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21333 newval
= 0xeb000000;
21334 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21335 _("blx to '%s' an ARM ISA state function changed to bl"),
21337 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21343 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21344 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
21348 /* We are going to store value (shifted right by two) in the
21349 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21350 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21351 also be be clear. */
21353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21354 _("misaligned branch destination"));
21355 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
21356 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
21357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21359 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21361 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21362 newval
|= (value
>> 2) & 0x00ffffff;
21363 /* Set the H bit on BLX instructions. */
21367 newval
|= 0x01000000;
21369 newval
&= ~0x01000000;
21371 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21375 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
21376 /* CBZ can only branch forward. */
21378 /* Attempts to use CBZ to branch to the next instruction
21379 (which, strictly speaking, are prohibited) will be turned into
21382 FIXME: It may be better to remove the instruction completely and
21383 perform relaxation. */
21386 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21387 newval
= 0xbf00; /* NOP encoding T1 */
21388 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21395 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21397 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21398 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
21399 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21404 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
21405 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
21406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21408 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21410 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21411 newval
|= (value
& 0x1ff) >> 1;
21412 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21416 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
21417 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
21418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21420 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21422 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21423 newval
|= (value
& 0xfff) >> 1;
21424 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21428 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21430 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21431 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21432 && ARM_IS_FUNC (fixP
->fx_addsy
)
21433 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21435 /* Force a relocation for a branch 20 bits wide. */
21438 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
21439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21440 _("conditional branch out of range"));
21442 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21445 addressT S
, J1
, J2
, lo
, hi
;
21447 S
= (value
& 0x00100000) >> 20;
21448 J2
= (value
& 0x00080000) >> 19;
21449 J1
= (value
& 0x00040000) >> 18;
21450 hi
= (value
& 0x0003f000) >> 12;
21451 lo
= (value
& 0x00000ffe) >> 1;
21453 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21454 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21455 newval
|= (S
<< 10) | hi
;
21456 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
21457 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21458 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21462 case BFD_RELOC_THUMB_PCREL_BLX
:
21463 /* If there is a blx from a thumb state function to
21464 another thumb function flip this to a bl and warn
21468 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21469 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21470 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21472 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21473 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21474 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21476 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21477 newval
= newval
| 0x1000;
21478 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21479 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21484 goto thumb_bl_common
;
21486 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21487 /* A bl from Thumb state ISA to an internal ARM state function
21488 is converted to a blx. */
21490 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21491 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21492 && ARM_IS_FUNC (fixP
->fx_addsy
)
21493 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21495 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21496 newval
= newval
& ~0x1000;
21497 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21498 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
21505 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
21506 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21507 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21510 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21511 /* For a BLX instruction, make sure that the relocation is rounded up
21512 to a word boundary. This follows the semantics of the instruction
21513 which specifies that bit 1 of the target address will come from bit
21514 1 of the base address. */
21515 value
= (value
+ 1) & ~ 1;
21517 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21519 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21521 else if ((value
& ~0x1ffffff)
21522 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21524 _("Thumb2 branch out of range"));
21527 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21528 encode_thumb2_b_bl_offset (buf
, value
);
21532 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21533 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
21534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21536 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21537 encode_thumb2_b_bl_offset (buf
, value
);
21542 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21543 md_number_to_chars (buf
, value
, 1);
21547 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21548 md_number_to_chars (buf
, value
, 2);
21552 case BFD_RELOC_ARM_TLS_CALL
:
21553 case BFD_RELOC_ARM_THM_TLS_CALL
:
21554 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21555 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21556 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21559 case BFD_RELOC_ARM_TLS_GOTDESC
:
21560 case BFD_RELOC_ARM_TLS_GD32
:
21561 case BFD_RELOC_ARM_TLS_LE32
:
21562 case BFD_RELOC_ARM_TLS_IE32
:
21563 case BFD_RELOC_ARM_TLS_LDM32
:
21564 case BFD_RELOC_ARM_TLS_LDO32
:
21565 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21568 case BFD_RELOC_ARM_GOT32
:
21569 case BFD_RELOC_ARM_GOTOFF
:
21570 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21571 md_number_to_chars (buf
, 0, 4);
21574 case BFD_RELOC_ARM_GOT_PREL
:
21575 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21576 md_number_to_chars (buf
, value
, 4);
21579 case BFD_RELOC_ARM_TARGET2
:
21580 /* TARGET2 is not partial-inplace, so we need to write the
21581 addend here for REL targets, because it won't be written out
21582 during reloc processing later. */
21583 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21584 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21588 case BFD_RELOC_RVA
:
21590 case BFD_RELOC_ARM_TARGET1
:
21591 case BFD_RELOC_ARM_ROSEGREL32
:
21592 case BFD_RELOC_ARM_SBREL32
:
21593 case BFD_RELOC_32_PCREL
:
21595 case BFD_RELOC_32_SECREL
:
21597 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21599 /* For WinCE we only do this for pcrel fixups. */
21600 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21602 md_number_to_chars (buf
, value
, 4);
21606 case BFD_RELOC_ARM_PREL31
:
21607 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21609 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21610 if ((value
^ (value
>> 1)) & 0x40000000)
21612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21613 _("rel31 relocation overflow"));
21615 newval
|= value
& 0x7fffffff;
21616 md_number_to_chars (buf
, newval
, 4);
21621 case BFD_RELOC_ARM_CP_OFF_IMM
:
21622 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21623 if (value
< -1023 || value
> 1023 || (value
& 3))
21624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21625 _("co-processor offset out of range"));
21630 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21631 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21632 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21634 newval
= get_thumb32_insn (buf
);
21636 newval
&= 0xffffff00;
21639 newval
&= 0xff7fff00;
21640 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21642 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21643 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21644 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21646 put_thumb32_insn (buf
, newval
);
21649 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21650 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21651 if (value
< -255 || value
> 255)
21652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21653 _("co-processor offset out of range"));
21655 goto cp_off_common
;
21657 case BFD_RELOC_ARM_THUMB_OFFSET
:
21658 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21659 /* Exactly what ranges, and where the offset is inserted depends
21660 on the type of instruction, we can establish this from the
21662 switch (newval
>> 12)
21664 case 4: /* PC load. */
21665 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21666 forced to zero for these loads; md_pcrel_from has already
21667 compensated for this. */
21669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21670 _("invalid offset, target not word aligned (0x%08lX)"),
21671 (((unsigned long) fixP
->fx_frag
->fr_address
21672 + (unsigned long) fixP
->fx_where
) & ~3)
21673 + (unsigned long) value
);
21675 if (value
& ~0x3fc)
21676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21677 _("invalid offset, value too big (0x%08lX)"),
21680 newval
|= value
>> 2;
21683 case 9: /* SP load/store. */
21684 if (value
& ~0x3fc)
21685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21686 _("invalid offset, value too big (0x%08lX)"),
21688 newval
|= value
>> 2;
21691 case 6: /* Word load/store. */
21693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21694 _("invalid offset, value too big (0x%08lX)"),
21696 newval
|= value
<< 4; /* 6 - 2. */
21699 case 7: /* Byte load/store. */
21701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21702 _("invalid offset, value too big (0x%08lX)"),
21704 newval
|= value
<< 6;
21707 case 8: /* Halfword load/store. */
21709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21710 _("invalid offset, value too big (0x%08lX)"),
21712 newval
|= value
<< 5; /* 6 - 1. */
21716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21717 "Unable to process relocation for thumb opcode: %lx",
21718 (unsigned long) newval
);
21721 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21724 case BFD_RELOC_ARM_THUMB_ADD
:
21725 /* This is a complicated relocation, since we use it for all of
21726 the following immediate relocations:
21730 9bit ADD/SUB SP word-aligned
21731 10bit ADD PC/SP word-aligned
21733 The type of instruction being processed is encoded in the
21740 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21742 int rd
= (newval
>> 4) & 0xf;
21743 int rs
= newval
& 0xf;
21744 int subtract
= !!(newval
& 0x8000);
21746 /* Check for HI regs, only very restricted cases allowed:
21747 Adjusting SP, and using PC or SP to get an address. */
21748 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21749 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21751 _("invalid Hi register with immediate"));
21753 /* If value is negative, choose the opposite instruction. */
21757 subtract
= !subtract
;
21759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21760 _("immediate value out of range"));
21765 if (value
& ~0x1fc)
21766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21767 _("invalid immediate for stack address calculation"));
21768 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21769 newval
|= value
>> 2;
21771 else if (rs
== REG_PC
|| rs
== REG_SP
)
21773 if (subtract
|| value
& ~0x3fc)
21774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21775 _("invalid immediate for address calculation (value = 0x%08lX)"),
21776 (unsigned long) value
);
21777 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21779 newval
|= value
>> 2;
21784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21785 _("immediate value out of range"));
21786 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21787 newval
|= (rd
<< 8) | value
;
21792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21793 _("immediate value out of range"));
21794 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21795 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21798 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21801 case BFD_RELOC_ARM_THUMB_IMM
:
21802 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21803 if (value
< 0 || value
> 255)
21804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21805 _("invalid immediate: %ld is out of range"),
21808 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21811 case BFD_RELOC_ARM_THUMB_SHIFT
:
21812 /* 5bit shift value (0..32). LSL cannot take 32. */
21813 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21814 temp
= newval
& 0xf800;
21815 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21817 _("invalid shift value: %ld"), (long) value
);
21818 /* Shifts of zero must be encoded as LSL. */
21820 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21821 /* Shifts of 32 are encoded as zero. */
21822 else if (value
== 32)
21824 newval
|= value
<< 6;
21825 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21828 case BFD_RELOC_VTABLE_INHERIT
:
21829 case BFD_RELOC_VTABLE_ENTRY
:
21833 case BFD_RELOC_ARM_MOVW
:
21834 case BFD_RELOC_ARM_MOVT
:
21835 case BFD_RELOC_ARM_THUMB_MOVW
:
21836 case BFD_RELOC_ARM_THUMB_MOVT
:
21837 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21839 /* REL format relocations are limited to a 16-bit addend. */
21840 if (!fixP
->fx_done
)
21842 if (value
< -0x8000 || value
> 0x7fff)
21843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21844 _("offset out of range"));
21846 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21847 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21852 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21853 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21855 newval
= get_thumb32_insn (buf
);
21856 newval
&= 0xfbf08f00;
21857 newval
|= (value
& 0xf000) << 4;
21858 newval
|= (value
& 0x0800) << 15;
21859 newval
|= (value
& 0x0700) << 4;
21860 newval
|= (value
& 0x00ff);
21861 put_thumb32_insn (buf
, newval
);
21865 newval
= md_chars_to_number (buf
, 4);
21866 newval
&= 0xfff0f000;
21867 newval
|= value
& 0x0fff;
21868 newval
|= (value
& 0xf000) << 4;
21869 md_number_to_chars (buf
, newval
, 4);
21874 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21875 case BFD_RELOC_ARM_ALU_PC_G0
:
21876 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21877 case BFD_RELOC_ARM_ALU_PC_G1
:
21878 case BFD_RELOC_ARM_ALU_PC_G2
:
21879 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21880 case BFD_RELOC_ARM_ALU_SB_G0
:
21881 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21882 case BFD_RELOC_ARM_ALU_SB_G1
:
21883 case BFD_RELOC_ARM_ALU_SB_G2
:
21884 gas_assert (!fixP
->fx_done
);
21885 if (!seg
->use_rela_p
)
21888 bfd_vma encoded_addend
;
21889 bfd_vma addend_abs
= abs (value
);
21891 /* Check that the absolute value of the addend can be
21892 expressed as an 8-bit constant plus a rotation. */
21893 encoded_addend
= encode_arm_immediate (addend_abs
);
21894 if (encoded_addend
== (unsigned int) FAIL
)
21895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21896 _("the offset 0x%08lX is not representable"),
21897 (unsigned long) addend_abs
);
21899 /* Extract the instruction. */
21900 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21902 /* If the addend is positive, use an ADD instruction.
21903 Otherwise use a SUB. Take care not to destroy the S bit. */
21904 insn
&= 0xff1fffff;
21910 /* Place the encoded addend into the first 12 bits of the
21912 insn
&= 0xfffff000;
21913 insn
|= encoded_addend
;
21915 /* Update the instruction. */
21916 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21920 case BFD_RELOC_ARM_LDR_PC_G0
:
21921 case BFD_RELOC_ARM_LDR_PC_G1
:
21922 case BFD_RELOC_ARM_LDR_PC_G2
:
21923 case BFD_RELOC_ARM_LDR_SB_G0
:
21924 case BFD_RELOC_ARM_LDR_SB_G1
:
21925 case BFD_RELOC_ARM_LDR_SB_G2
:
21926 gas_assert (!fixP
->fx_done
);
21927 if (!seg
->use_rela_p
)
21930 bfd_vma addend_abs
= abs (value
);
21932 /* Check that the absolute value of the addend can be
21933 encoded in 12 bits. */
21934 if (addend_abs
>= 0x1000)
21935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21936 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21937 (unsigned long) addend_abs
);
21939 /* Extract the instruction. */
21940 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21942 /* If the addend is negative, clear bit 23 of the instruction.
21943 Otherwise set it. */
21945 insn
&= ~(1 << 23);
21949 /* Place the absolute value of the addend into the first 12 bits
21950 of the instruction. */
21951 insn
&= 0xfffff000;
21952 insn
|= addend_abs
;
21954 /* Update the instruction. */
21955 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21959 case BFD_RELOC_ARM_LDRS_PC_G0
:
21960 case BFD_RELOC_ARM_LDRS_PC_G1
:
21961 case BFD_RELOC_ARM_LDRS_PC_G2
:
21962 case BFD_RELOC_ARM_LDRS_SB_G0
:
21963 case BFD_RELOC_ARM_LDRS_SB_G1
:
21964 case BFD_RELOC_ARM_LDRS_SB_G2
:
21965 gas_assert (!fixP
->fx_done
);
21966 if (!seg
->use_rela_p
)
21969 bfd_vma addend_abs
= abs (value
);
21971 /* Check that the absolute value of the addend can be
21972 encoded in 8 bits. */
21973 if (addend_abs
>= 0x100)
21974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21975 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21976 (unsigned long) addend_abs
);
21978 /* Extract the instruction. */
21979 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21981 /* If the addend is negative, clear bit 23 of the instruction.
21982 Otherwise set it. */
21984 insn
&= ~(1 << 23);
21988 /* Place the first four bits of the absolute value of the addend
21989 into the first 4 bits of the instruction, and the remaining
21990 four into bits 8 .. 11. */
21991 insn
&= 0xfffff0f0;
21992 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21994 /* Update the instruction. */
21995 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21999 case BFD_RELOC_ARM_LDC_PC_G0
:
22000 case BFD_RELOC_ARM_LDC_PC_G1
:
22001 case BFD_RELOC_ARM_LDC_PC_G2
:
22002 case BFD_RELOC_ARM_LDC_SB_G0
:
22003 case BFD_RELOC_ARM_LDC_SB_G1
:
22004 case BFD_RELOC_ARM_LDC_SB_G2
:
22005 gas_assert (!fixP
->fx_done
);
22006 if (!seg
->use_rela_p
)
22009 bfd_vma addend_abs
= abs (value
);
22011 /* Check that the absolute value of the addend is a multiple of
22012 four and, when divided by four, fits in 8 bits. */
22013 if (addend_abs
& 0x3)
22014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22015 _("bad offset 0x%08lX (must be word-aligned)"),
22016 (unsigned long) addend_abs
);
22018 if ((addend_abs
>> 2) > 0xff)
22019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22020 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22021 (unsigned long) addend_abs
);
22023 /* Extract the instruction. */
22024 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22026 /* If the addend is negative, clear bit 23 of the instruction.
22027 Otherwise set it. */
22029 insn
&= ~(1 << 23);
22033 /* Place the addend (divided by four) into the first eight
22034 bits of the instruction. */
22035 insn
&= 0xfffffff0;
22036 insn
|= addend_abs
>> 2;
22038 /* Update the instruction. */
22039 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22043 case BFD_RELOC_ARM_V4BX
:
22044 /* This will need to go in the object file. */
22048 case BFD_RELOC_UNUSED
:
22050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22051 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
22055 /* Translate internal representation of relocation info to BFD target
22059 tc_gen_reloc (asection
*section
, fixS
*fixp
)
22062 bfd_reloc_code_real_type code
;
22064 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
22066 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
22067 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
22068 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
22070 if (fixp
->fx_pcrel
)
22072 if (section
->use_rela_p
)
22073 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
22075 fixp
->fx_offset
= reloc
->address
;
22077 reloc
->addend
= fixp
->fx_offset
;
22079 switch (fixp
->fx_r_type
)
22082 if (fixp
->fx_pcrel
)
22084 code
= BFD_RELOC_8_PCREL
;
22089 if (fixp
->fx_pcrel
)
22091 code
= BFD_RELOC_16_PCREL
;
22096 if (fixp
->fx_pcrel
)
22098 code
= BFD_RELOC_32_PCREL
;
22102 case BFD_RELOC_ARM_MOVW
:
22103 if (fixp
->fx_pcrel
)
22105 code
= BFD_RELOC_ARM_MOVW_PCREL
;
22109 case BFD_RELOC_ARM_MOVT
:
22110 if (fixp
->fx_pcrel
)
22112 code
= BFD_RELOC_ARM_MOVT_PCREL
;
22116 case BFD_RELOC_ARM_THUMB_MOVW
:
22117 if (fixp
->fx_pcrel
)
22119 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
22123 case BFD_RELOC_ARM_THUMB_MOVT
:
22124 if (fixp
->fx_pcrel
)
22126 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
22130 case BFD_RELOC_NONE
:
22131 case BFD_RELOC_ARM_PCREL_BRANCH
:
22132 case BFD_RELOC_ARM_PCREL_BLX
:
22133 case BFD_RELOC_RVA
:
22134 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22135 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22136 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22137 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22138 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22139 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22140 case BFD_RELOC_VTABLE_ENTRY
:
22141 case BFD_RELOC_VTABLE_INHERIT
:
22143 case BFD_RELOC_32_SECREL
:
22145 code
= fixp
->fx_r_type
;
22148 case BFD_RELOC_THUMB_PCREL_BLX
:
22150 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22151 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22154 code
= BFD_RELOC_THUMB_PCREL_BLX
;
22157 case BFD_RELOC_ARM_LITERAL
:
22158 case BFD_RELOC_ARM_HWLITERAL
:
22159 /* If this is called then the a literal has
22160 been referenced across a section boundary. */
22161 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22162 _("literal referenced across section boundary"));
22166 case BFD_RELOC_ARM_TLS_CALL
:
22167 case BFD_RELOC_ARM_THM_TLS_CALL
:
22168 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22169 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22170 case BFD_RELOC_ARM_GOT32
:
22171 case BFD_RELOC_ARM_GOTOFF
:
22172 case BFD_RELOC_ARM_GOT_PREL
:
22173 case BFD_RELOC_ARM_PLT32
:
22174 case BFD_RELOC_ARM_TARGET1
:
22175 case BFD_RELOC_ARM_ROSEGREL32
:
22176 case BFD_RELOC_ARM_SBREL32
:
22177 case BFD_RELOC_ARM_PREL31
:
22178 case BFD_RELOC_ARM_TARGET2
:
22179 case BFD_RELOC_ARM_TLS_LE32
:
22180 case BFD_RELOC_ARM_TLS_LDO32
:
22181 case BFD_RELOC_ARM_PCREL_CALL
:
22182 case BFD_RELOC_ARM_PCREL_JUMP
:
22183 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22184 case BFD_RELOC_ARM_ALU_PC_G0
:
22185 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22186 case BFD_RELOC_ARM_ALU_PC_G1
:
22187 case BFD_RELOC_ARM_ALU_PC_G2
:
22188 case BFD_RELOC_ARM_LDR_PC_G0
:
22189 case BFD_RELOC_ARM_LDR_PC_G1
:
22190 case BFD_RELOC_ARM_LDR_PC_G2
:
22191 case BFD_RELOC_ARM_LDRS_PC_G0
:
22192 case BFD_RELOC_ARM_LDRS_PC_G1
:
22193 case BFD_RELOC_ARM_LDRS_PC_G2
:
22194 case BFD_RELOC_ARM_LDC_PC_G0
:
22195 case BFD_RELOC_ARM_LDC_PC_G1
:
22196 case BFD_RELOC_ARM_LDC_PC_G2
:
22197 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22198 case BFD_RELOC_ARM_ALU_SB_G0
:
22199 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22200 case BFD_RELOC_ARM_ALU_SB_G1
:
22201 case BFD_RELOC_ARM_ALU_SB_G2
:
22202 case BFD_RELOC_ARM_LDR_SB_G0
:
22203 case BFD_RELOC_ARM_LDR_SB_G1
:
22204 case BFD_RELOC_ARM_LDR_SB_G2
:
22205 case BFD_RELOC_ARM_LDRS_SB_G0
:
22206 case BFD_RELOC_ARM_LDRS_SB_G1
:
22207 case BFD_RELOC_ARM_LDRS_SB_G2
:
22208 case BFD_RELOC_ARM_LDC_SB_G0
:
22209 case BFD_RELOC_ARM_LDC_SB_G1
:
22210 case BFD_RELOC_ARM_LDC_SB_G2
:
22211 case BFD_RELOC_ARM_V4BX
:
22212 code
= fixp
->fx_r_type
;
22215 case BFD_RELOC_ARM_TLS_GOTDESC
:
22216 case BFD_RELOC_ARM_TLS_GD32
:
22217 case BFD_RELOC_ARM_TLS_IE32
:
22218 case BFD_RELOC_ARM_TLS_LDM32
:
22219 /* BFD will include the symbol's address in the addend.
22220 But we don't want that, so subtract it out again here. */
22221 if (!S_IS_COMMON (fixp
->fx_addsy
))
22222 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
22223 code
= fixp
->fx_r_type
;
22227 case BFD_RELOC_ARM_IMMEDIATE
:
22228 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22229 _("internal relocation (type: IMMEDIATE) not fixed up"));
22232 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22233 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22234 _("ADRL used for a symbol not defined in the same file"));
22237 case BFD_RELOC_ARM_OFFSET_IMM
:
22238 if (section
->use_rela_p
)
22240 code
= fixp
->fx_r_type
;
22244 if (fixp
->fx_addsy
!= NULL
22245 && !S_IS_DEFINED (fixp
->fx_addsy
)
22246 && S_IS_LOCAL (fixp
->fx_addsy
))
22248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22249 _("undefined local label `%s'"),
22250 S_GET_NAME (fixp
->fx_addsy
));
22254 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22255 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22262 switch (fixp
->fx_r_type
)
22264 case BFD_RELOC_NONE
: type
= "NONE"; break;
22265 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
22266 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
22267 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
22268 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
22269 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
22270 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
22271 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
22272 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
22273 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
22274 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
22275 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
22276 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
22277 default: type
= _("<unknown>"); break;
22279 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22280 _("cannot represent %s relocation in this object file format"),
22287 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
22289 && fixp
->fx_addsy
== GOT_symbol
)
22291 code
= BFD_RELOC_ARM_GOTPC
;
22292 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
22296 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
22298 if (reloc
->howto
== NULL
)
22300 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22301 _("cannot represent %s relocation in this object file format"),
22302 bfd_get_reloc_code_name (code
));
22306 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22307 vtable entry to be used in the relocation's section offset. */
22308 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22309 reloc
->address
= fixp
->fx_offset
;
22314 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22317 cons_fix_new_arm (fragS
* frag
,
22322 bfd_reloc_code_real_type type
;
22326 FIXME: @@ Should look at CPU word size. */
22330 type
= BFD_RELOC_8
;
22333 type
= BFD_RELOC_16
;
22337 type
= BFD_RELOC_32
;
22340 type
= BFD_RELOC_64
;
22345 if (exp
->X_op
== O_secrel
)
22347 exp
->X_op
= O_symbol
;
22348 type
= BFD_RELOC_32_SECREL
;
22352 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
22355 #if defined (OBJ_COFF)
22357 arm_validate_fix (fixS
* fixP
)
22359 /* If the destination of the branch is a defined symbol which does not have
22360 the THUMB_FUNC attribute, then we must be calling a function which has
22361 the (interfacearm) attribute. We look for the Thumb entry point to that
22362 function and change the branch to refer to that function instead. */
22363 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
22364 && fixP
->fx_addsy
!= NULL
22365 && S_IS_DEFINED (fixP
->fx_addsy
)
22366 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
22368 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
22375 arm_force_relocation (struct fix
* fixp
)
22377 #if defined (OBJ_COFF) && defined (TE_PE)
22378 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
22382 /* In case we have a call or a branch to a function in ARM ISA mode from
22383 a thumb function or vice-versa force the relocation. These relocations
22384 are cleared off for some cores that might have blx and simple transformations
22388 switch (fixp
->fx_r_type
)
22390 case BFD_RELOC_ARM_PCREL_JUMP
:
22391 case BFD_RELOC_ARM_PCREL_CALL
:
22392 case BFD_RELOC_THUMB_PCREL_BLX
:
22393 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
22397 case BFD_RELOC_ARM_PCREL_BLX
:
22398 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22399 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22400 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22401 if (ARM_IS_FUNC (fixp
->fx_addsy
))
22410 /* Resolve these relocations even if the symbol is extern or weak.
22411 Technically this is probably wrong due to symbol preemption.
22412 In practice these relocations do not have enough range to be useful
22413 at dynamic link time, and some code (e.g. in the Linux kernel)
22414 expects these references to be resolved. */
22415 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
22416 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
22417 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
22418 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
22419 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22420 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
22421 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
22422 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
22423 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22424 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
22425 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
22426 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
22427 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
22428 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
22431 /* Always leave these relocations for the linker. */
22432 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22433 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22434 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22437 /* Always generate relocations against function symbols. */
22438 if (fixp
->fx_r_type
== BFD_RELOC_32
22440 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22443 return generic_force_reloc (fixp
);
22446 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22447 /* Relocations against function names must be left unadjusted,
22448 so that the linker can use this information to generate interworking
22449 stubs. The MIPS version of this function
22450 also prevents relocations that are mips-16 specific, but I do not
22451 know why it does this.
22454 There is one other problem that ought to be addressed here, but
22455 which currently is not: Taking the address of a label (rather
22456 than a function) and then later jumping to that address. Such
22457 addresses also ought to have their bottom bit set (assuming that
22458 they reside in Thumb code), but at the moment they will not. */
22461 arm_fix_adjustable (fixS
* fixP
)
22463 if (fixP
->fx_addsy
== NULL
)
22466 /* Preserve relocations against symbols with function type. */
22467 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
22470 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
22471 && fixP
->fx_subsy
== NULL
)
22474 /* We need the symbol name for the VTABLE entries. */
22475 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
22476 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22479 /* Don't allow symbols to be discarded on GOT related relocs. */
22480 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
22481 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
22482 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
22483 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
22484 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
22485 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
22486 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
22487 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
22488 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
22489 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
22490 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
22491 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
22492 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
22493 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
22496 /* Similarly for group relocations. */
22497 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22498 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22499 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22502 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22503 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
22504 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22505 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
22506 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
22507 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22508 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
22509 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
22510 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22515 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22520 elf32_arm_target_format (void)
22523 return (target_big_endian
22524 ? "elf32-bigarm-symbian"
22525 : "elf32-littlearm-symbian");
22526 #elif defined (TE_VXWORKS)
22527 return (target_big_endian
22528 ? "elf32-bigarm-vxworks"
22529 : "elf32-littlearm-vxworks");
22530 #elif defined (TE_NACL)
22531 return (target_big_endian
22532 ? "elf32-bigarm-nacl"
22533 : "elf32-littlearm-nacl");
22535 if (target_big_endian
)
22536 return "elf32-bigarm";
22538 return "elf32-littlearm";
22543 armelf_frob_symbol (symbolS
* symp
,
22546 elf_frob_symbol (symp
, puntp
);
22550 /* MD interface: Finalization. */
22555 literal_pool
* pool
;
22557 /* Ensure that all the IT blocks are properly closed. */
22558 check_it_blocks_finished ();
22560 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22562 /* Put it at the end of the relevant section. */
22563 subseg_set (pool
->section
, pool
->sub_section
);
22565 arm_elf_change_section ();
22572 /* Remove any excess mapping symbols generated for alignment frags in
22573 SEC. We may have created a mapping symbol before a zero byte
22574 alignment; remove it if there's a mapping symbol after the
22577 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22578 void *dummy ATTRIBUTE_UNUSED
)
22580 segment_info_type
*seginfo
= seg_info (sec
);
22583 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22586 for (fragp
= seginfo
->frchainP
->frch_root
;
22588 fragp
= fragp
->fr_next
)
22590 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22591 fragS
*next
= fragp
->fr_next
;
22593 /* Variable-sized frags have been converted to fixed size by
22594 this point. But if this was variable-sized to start with,
22595 there will be a fixed-size frag after it. So don't handle
22597 if (sym
== NULL
|| next
== NULL
)
22600 if (S_GET_VALUE (sym
) < next
->fr_address
)
22601 /* Not at the end of this frag. */
22603 know (S_GET_VALUE (sym
) == next
->fr_address
);
22607 if (next
->tc_frag_data
.first_map
!= NULL
)
22609 /* Next frag starts with a mapping symbol. Discard this
22611 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22615 if (next
->fr_next
== NULL
)
22617 /* This mapping symbol is at the end of the section. Discard
22619 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22620 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22624 /* As long as we have empty frags without any mapping symbols,
22626 /* If the next frag is non-empty and does not start with a
22627 mapping symbol, then this mapping symbol is required. */
22628 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22631 next
= next
->fr_next
;
22633 while (next
!= NULL
);
22638 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22642 arm_adjust_symtab (void)
22647 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22649 if (ARM_IS_THUMB (sym
))
22651 if (THUMB_IS_FUNC (sym
))
22653 /* Mark the symbol as a Thumb function. */
22654 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22655 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22656 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22658 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22659 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22661 as_bad (_("%s: unexpected function type: %d"),
22662 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22664 else switch (S_GET_STORAGE_CLASS (sym
))
22667 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22670 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22673 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22681 if (ARM_IS_INTERWORK (sym
))
22682 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22689 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22691 if (ARM_IS_THUMB (sym
))
22693 elf_symbol_type
* elf_sym
;
22695 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22696 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22698 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22699 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22701 /* If it's a .thumb_func, declare it as so,
22702 otherwise tag label as .code 16. */
22703 if (THUMB_IS_FUNC (sym
))
22704 elf_sym
->internal_elf_sym
.st_target_internal
22705 = ST_BRANCH_TO_THUMB
;
22706 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22707 elf_sym
->internal_elf_sym
.st_info
=
22708 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22713 /* Remove any overlapping mapping symbols generated by alignment frags. */
22714 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22715 /* Now do generic ELF adjustments. */
22716 elf_adjust_symtab ();
22720 /* MD interface: Initialization. */
22723 set_constant_flonums (void)
22727 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22728 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22732 /* Auto-select Thumb mode if it's the only available instruction set for the
22733 given architecture. */
22736 autoselect_thumb_from_cpu_variant (void)
22738 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22739 opcode_select (16);
22748 if ( (arm_ops_hsh
= hash_new ()) == NULL
22749 || (arm_cond_hsh
= hash_new ()) == NULL
22750 || (arm_shift_hsh
= hash_new ()) == NULL
22751 || (arm_psr_hsh
= hash_new ()) == NULL
22752 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22753 || (arm_reg_hsh
= hash_new ()) == NULL
22754 || (arm_reloc_hsh
= hash_new ()) == NULL
22755 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22756 as_fatal (_("virtual memory exhausted"));
22758 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22759 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22760 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22761 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22762 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22763 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22764 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22765 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22766 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22767 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22768 (void *) (v7m_psrs
+ i
));
22769 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22770 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22772 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22774 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22775 (void *) (barrier_opt_names
+ i
));
22777 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
22779 struct reloc_entry
* entry
= reloc_names
+ i
;
22781 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
22782 /* This makes encode_branch() use the EABI versions of this relocation. */
22783 entry
->reloc
= BFD_RELOC_UNUSED
;
22785 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
22789 set_constant_flonums ();
22791 /* Set the cpu variant based on the command-line options. We prefer
22792 -mcpu= over -march= if both are set (as for GCC); and we prefer
22793 -mfpu= over any other way of setting the floating point unit.
22794 Use of legacy options with new options are faulted. */
22797 if (mcpu_cpu_opt
|| march_cpu_opt
)
22798 as_bad (_("use of old and new-style options to set CPU type"));
22800 mcpu_cpu_opt
= legacy_cpu
;
22802 else if (!mcpu_cpu_opt
)
22803 mcpu_cpu_opt
= march_cpu_opt
;
22808 as_bad (_("use of old and new-style options to set FPU type"));
22810 mfpu_opt
= legacy_fpu
;
22812 else if (!mfpu_opt
)
22814 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22815 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22816 /* Some environments specify a default FPU. If they don't, infer it
22817 from the processor. */
22819 mfpu_opt
= mcpu_fpu_opt
;
22821 mfpu_opt
= march_fpu_opt
;
22823 mfpu_opt
= &fpu_default
;
22829 if (mcpu_cpu_opt
!= NULL
)
22830 mfpu_opt
= &fpu_default
;
22831 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22832 mfpu_opt
= &fpu_arch_vfp_v2
;
22834 mfpu_opt
= &fpu_arch_fpa
;
22840 mcpu_cpu_opt
= &cpu_default
;
22841 selected_cpu
= cpu_default
;
22845 selected_cpu
= *mcpu_cpu_opt
;
22847 mcpu_cpu_opt
= &arm_arch_any
;
22850 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22852 autoselect_thumb_from_cpu_variant ();
22854 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22856 #if defined OBJ_COFF || defined OBJ_ELF
22858 unsigned int flags
= 0;
22860 #if defined OBJ_ELF
22861 flags
= meabi_flags
;
22863 switch (meabi_flags
)
22865 case EF_ARM_EABI_UNKNOWN
:
22867 /* Set the flags in the private structure. */
22868 if (uses_apcs_26
) flags
|= F_APCS26
;
22869 if (support_interwork
) flags
|= F_INTERWORK
;
22870 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22871 if (pic_code
) flags
|= F_PIC
;
22872 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22873 flags
|= F_SOFT_FLOAT
;
22875 switch (mfloat_abi_opt
)
22877 case ARM_FLOAT_ABI_SOFT
:
22878 case ARM_FLOAT_ABI_SOFTFP
:
22879 flags
|= F_SOFT_FLOAT
;
22882 case ARM_FLOAT_ABI_HARD
:
22883 if (flags
& F_SOFT_FLOAT
)
22884 as_bad (_("hard-float conflicts with specified fpu"));
22888 /* Using pure-endian doubles (even if soft-float). */
22889 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22890 flags
|= F_VFP_FLOAT
;
22892 #if defined OBJ_ELF
22893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22894 flags
|= EF_ARM_MAVERICK_FLOAT
;
22897 case EF_ARM_EABI_VER4
:
22898 case EF_ARM_EABI_VER5
:
22899 /* No additional flags to set. */
22906 bfd_set_private_flags (stdoutput
, flags
);
22908 /* We have run out flags in the COFF header to encode the
22909 status of ATPCS support, so instead we create a dummy,
22910 empty, debug section called .arm.atpcs. */
22915 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22919 bfd_set_section_flags
22920 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22921 bfd_set_section_size (stdoutput
, sec
, 0);
22922 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22928 /* Record the CPU type as well. */
22929 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22930 mach
= bfd_mach_arm_iWMMXt2
;
22931 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22932 mach
= bfd_mach_arm_iWMMXt
;
22933 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22934 mach
= bfd_mach_arm_XScale
;
22935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22936 mach
= bfd_mach_arm_ep9312
;
22937 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22938 mach
= bfd_mach_arm_5TE
;
22939 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22941 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22942 mach
= bfd_mach_arm_5T
;
22944 mach
= bfd_mach_arm_5
;
22946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22948 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22949 mach
= bfd_mach_arm_4T
;
22951 mach
= bfd_mach_arm_4
;
22953 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22954 mach
= bfd_mach_arm_3M
;
22955 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22956 mach
= bfd_mach_arm_3
;
22957 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22958 mach
= bfd_mach_arm_2a
;
22959 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22960 mach
= bfd_mach_arm_2
;
22962 mach
= bfd_mach_arm_unknown
;
22964 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22967 /* Command line processing. */
22970 Invocation line includes a switch not recognized by the base assembler.
22971 See if it's a processor-specific option.
22973 This routine is somewhat complicated by the need for backwards
22974 compatibility (since older releases of gcc can't be changed).
22975 The new options try to make the interface as compatible as
22978 New options (supported) are:
22980 -mcpu=<cpu name> Assemble for selected processor
22981 -march=<architecture name> Assemble for selected architecture
22982 -mfpu=<fpu architecture> Assemble for selected FPU.
22983 -EB/-mbig-endian Big-endian
22984 -EL/-mlittle-endian Little-endian
22985 -k Generate PIC code
22986 -mthumb Start in Thumb mode
22987 -mthumb-interwork Code supports ARM/Thumb interworking
22989 -m[no-]warn-deprecated Warn about deprecated features
22991 For now we will also provide support for:
22993 -mapcs-32 32-bit Program counter
22994 -mapcs-26 26-bit Program counter
22995 -macps-float Floats passed in FP registers
22996 -mapcs-reentrant Reentrant code
22998 (sometime these will probably be replaced with -mapcs=<list of options>
22999 and -matpcs=<list of options>)
23001 The remaining options are only supported for back-wards compatibility.
23002 Cpu variants, the arm part is optional:
23003 -m[arm]1 Currently not supported.
23004 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23005 -m[arm]3 Arm 3 processor
23006 -m[arm]6[xx], Arm 6 processors
23007 -m[arm]7[xx][t][[d]m] Arm 7 processors
23008 -m[arm]8[10] Arm 8 processors
23009 -m[arm]9[20][tdmi] Arm 9 processors
23010 -mstrongarm[110[0]] StrongARM processors
23011 -mxscale XScale processors
23012 -m[arm]v[2345[t[e]]] Arm architectures
23013 -mall All (except the ARM1)
23015 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23016 -mfpe-old (No float load/store multiples)
23017 -mvfpxd VFP Single precision
23019 -mno-fpu Disable all floating point instructions
23021 The following CPU names are recognized:
23022 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23023 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23024 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23025 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23026 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23027 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23028 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23032 const char * md_shortopts
= "m:k";
23034 #ifdef ARM_BI_ENDIAN
23035 #define OPTION_EB (OPTION_MD_BASE + 0)
23036 #define OPTION_EL (OPTION_MD_BASE + 1)
23038 #if TARGET_BYTES_BIG_ENDIAN
23039 #define OPTION_EB (OPTION_MD_BASE + 0)
23041 #define OPTION_EL (OPTION_MD_BASE + 1)
23044 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23046 struct option md_longopts
[] =
23049 {"EB", no_argument
, NULL
, OPTION_EB
},
23052 {"EL", no_argument
, NULL
, OPTION_EL
},
23054 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
23055 {NULL
, no_argument
, NULL
, 0}
23058 size_t md_longopts_size
= sizeof (md_longopts
);
23060 struct arm_option_table
23062 char *option
; /* Option name to match. */
23063 char *help
; /* Help information. */
23064 int *var
; /* Variable to change. */
23065 int value
; /* What to change it to. */
23066 char *deprecated
; /* If non-null, print this message. */
23069 struct arm_option_table arm_opts
[] =
23071 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
23072 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
23073 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23074 &support_interwork
, 1, NULL
},
23075 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
23076 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
23077 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
23079 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
23080 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
23081 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
23082 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
23085 /* These are recognized by the assembler, but have no affect on code. */
23086 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
23087 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
23089 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
23090 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23091 &warn_on_deprecated
, 0, NULL
},
23092 {NULL
, NULL
, NULL
, 0, NULL
}
23095 struct arm_legacy_option_table
23097 char *option
; /* Option name to match. */
23098 const arm_feature_set
**var
; /* Variable to change. */
23099 const arm_feature_set value
; /* What to change it to. */
23100 char *deprecated
; /* If non-null, print this message. */
23103 const struct arm_legacy_option_table arm_legacy_opts
[] =
23105 /* DON'T add any new processors to this list -- we want the whole list
23106 to go away... Add them to the processors table instead. */
23107 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23108 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23109 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23110 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23111 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23112 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23113 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23114 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23115 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23116 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23117 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23118 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23119 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23120 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23121 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23122 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23123 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23124 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23125 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23126 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23127 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23128 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23129 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23130 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23131 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23132 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23133 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23134 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23135 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23136 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23137 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23138 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23139 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23140 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23141 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23142 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23143 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23144 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23145 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23146 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23147 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23148 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23149 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23150 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23151 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23152 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23153 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23154 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23155 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23156 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23157 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
23158 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
23159 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
23160 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
23161 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
23162 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
23163 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
23164 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
23165 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
23166 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
23167 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
23168 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
23169 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
23170 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
23171 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
23172 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
23173 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
23174 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
23175 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
23176 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
23177 N_("use -mcpu=strongarm110")},
23178 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
23179 N_("use -mcpu=strongarm1100")},
23180 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
23181 N_("use -mcpu=strongarm1110")},
23182 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
23183 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
23184 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
23186 /* Architecture variants -- don't add any more to this list either. */
23187 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
23188 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
23189 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
23190 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
23191 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
23192 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
23193 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
23194 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
23195 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
23196 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
23197 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
23198 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
23199 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
23200 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
23201 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
23202 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
23203 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
23204 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
23206 /* Floating point variants -- don't add any more to this list either. */
23207 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
23208 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
23209 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
23210 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
23211 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23213 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
23216 struct arm_cpu_option_table
23220 const arm_feature_set value
;
23221 /* For some CPUs we assume an FPU unless the user explicitly sets
23223 const arm_feature_set default_fpu
;
23224 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23226 const char *canonical_name
;
23229 /* This list should, at a minimum, contain all the cpu names
23230 recognized by GCC. */
23231 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23232 static const struct arm_cpu_option_table arm_cpus
[] =
23234 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
23235 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
23236 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
23237 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
23238 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
23239 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23240 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23241 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23242 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23243 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23244 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23245 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
23246 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23247 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
23248 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23249 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
23250 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23251 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23252 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23253 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23254 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23255 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23256 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23257 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23258 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23259 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23260 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23261 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23262 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23263 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23264 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23265 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23266 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23267 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23268 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23269 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23270 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23271 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23272 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23273 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
23274 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23275 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23276 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23277 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23278 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23279 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23280 /* For V5 or later processors we default to using VFP; but the user
23281 should really set the FPU type explicitly. */
23282 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
23283 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23284 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
23285 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
23286 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
23287 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
23288 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
23289 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23290 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
23291 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
23292 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23293 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23294 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
23295 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
23296 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23297 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
23298 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
23299 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23300 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23301 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
23303 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
23304 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23305 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23306 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23307 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23308 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23309 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
23310 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
23311 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
23313 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
23314 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
23315 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
23316 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
23317 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
23318 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
23319 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
23320 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
23321 FPU_NONE
, "Cortex-A5"),
23322 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
23323 FPU_ARCH_NEON_VFP_V4
,
23325 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
23326 ARM_FEATURE (0, FPU_VFP_V3
23327 | FPU_NEON_EXT_V1
),
23329 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
23330 ARM_FEATURE (0, FPU_VFP_V3
23331 | FPU_NEON_EXT_V1
),
23333 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
23334 FPU_ARCH_NEON_VFP_V4
,
23336 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
23337 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
23339 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
23340 FPU_NONE
, "Cortex-R5"),
23341 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
23342 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
23343 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
23344 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
23345 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
23346 /* ??? XSCALE is really an architecture. */
23347 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
23348 /* ??? iwmmxt is not a processor. */
23349 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
23350 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
23351 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
23353 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
23356 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
23360 struct arm_arch_option_table
23364 const arm_feature_set value
;
23365 const arm_feature_set default_fpu
;
23368 /* This list should, at a minimum, contain all the architecture names
23369 recognized by GCC. */
23370 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23371 static const struct arm_arch_option_table arm_archs
[] =
23373 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
23374 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
23375 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
23376 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
23377 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
23378 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
23379 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
23380 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
23381 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
23382 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
23383 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
23384 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
23385 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
23386 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
23387 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
23388 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
23389 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
23390 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
23391 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
23392 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
23393 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
23394 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
23395 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
23396 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
23397 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
23398 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
23399 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
23400 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
23401 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
23402 /* The official spelling of the ARMv7 profile variants is the dashed form.
23403 Accept the non-dashed form for compatibility with old toolchains. */
23404 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
23405 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
23406 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
23407 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
23408 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
23409 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
23410 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
23411 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
23412 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
23413 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
23414 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
23415 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23417 #undef ARM_ARCH_OPT
23419 /* ISA extensions in the co-processor and main instruction set space. */
23420 struct arm_option_extension_value_table
23424 const arm_feature_set value
;
23425 const arm_feature_set allowed_archs
;
23428 /* The following table must be in alphabetical order with a NULL last entry.
23430 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23431 static const struct arm_option_extension_value_table arm_extensions
[] =
23433 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
23434 ARM_FEATURE (ARM_EXT_V8
, 0)),
23435 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
,
23436 ARM_FEATURE (ARM_EXT_V8
, 0)),
23437 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23438 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
23439 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
23440 ARM_EXT_OPT ("iwmmxt2",
23441 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
23442 ARM_EXT_OPT ("maverick",
23443 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
23444 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
23445 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
23446 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
23447 ARM_FEATURE (ARM_EXT_V8
, 0)),
23448 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
23449 ARM_FEATURE (ARM_EXT_V6M
, 0)),
23450 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
23451 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
23452 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
23454 ARM_FEATURE (ARM_EXT_V7A
, 0)),
23455 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
23456 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23460 /* ISA floating-point and Advanced SIMD extensions. */
23461 struct arm_option_fpu_value_table
23464 const arm_feature_set value
;
23467 /* This list should, at a minimum, contain all the fpu names
23468 recognized by GCC. */
23469 static const struct arm_option_fpu_value_table arm_fpus
[] =
23471 {"softfpa", FPU_NONE
},
23472 {"fpe", FPU_ARCH_FPE
},
23473 {"fpe2", FPU_ARCH_FPE
},
23474 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
23475 {"fpa", FPU_ARCH_FPA
},
23476 {"fpa10", FPU_ARCH_FPA
},
23477 {"fpa11", FPU_ARCH_FPA
},
23478 {"arm7500fe", FPU_ARCH_FPA
},
23479 {"softvfp", FPU_ARCH_VFP
},
23480 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
23481 {"vfp", FPU_ARCH_VFP_V2
},
23482 {"vfp9", FPU_ARCH_VFP_V2
},
23483 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
23484 {"vfp10", FPU_ARCH_VFP_V2
},
23485 {"vfp10-r0", FPU_ARCH_VFP_V1
},
23486 {"vfpxd", FPU_ARCH_VFP_V1xD
},
23487 {"vfpv2", FPU_ARCH_VFP_V2
},
23488 {"vfpv3", FPU_ARCH_VFP_V3
},
23489 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
23490 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
23491 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
23492 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
23493 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
23494 {"arm1020t", FPU_ARCH_VFP_V1
},
23495 {"arm1020e", FPU_ARCH_VFP_V2
},
23496 {"arm1136jfs", FPU_ARCH_VFP_V2
},
23497 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
23498 {"maverick", FPU_ARCH_MAVERICK
},
23499 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
23500 {"neon-fp16", FPU_ARCH_NEON_FP16
},
23501 {"vfpv4", FPU_ARCH_VFP_V4
},
23502 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
23503 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
23504 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
23505 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
23506 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
23507 {"crypto-neon-fp-armv8",
23508 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
23509 {NULL
, ARM_ARCH_NONE
}
23512 struct arm_option_value_table
23518 static const struct arm_option_value_table arm_float_abis
[] =
23520 {"hard", ARM_FLOAT_ABI_HARD
},
23521 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
23522 {"soft", ARM_FLOAT_ABI_SOFT
},
23527 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23528 static const struct arm_option_value_table arm_eabis
[] =
23530 {"gnu", EF_ARM_EABI_UNKNOWN
},
23531 {"4", EF_ARM_EABI_VER4
},
23532 {"5", EF_ARM_EABI_VER5
},
23537 struct arm_long_option_table
23539 char * option
; /* Substring to match. */
23540 char * help
; /* Help information. */
23541 int (* func
) (char * subopt
); /* Function to decode sub-option. */
23542 char * deprecated
; /* If non-null, print this message. */
23546 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
23548 arm_feature_set
*ext_set
= (arm_feature_set
*)
23549 xmalloc (sizeof (arm_feature_set
));
23551 /* We insist on extensions being specified in alphabetical order, and with
23552 extensions being added before being removed. We achieve this by having
23553 the global ARM_EXTENSIONS table in alphabetical order, and using the
23554 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23555 or removing it (0) and only allowing it to change in the order
23557 const struct arm_option_extension_value_table
* opt
= NULL
;
23558 int adding_value
= -1;
23560 /* Copy the feature set, so that we can modify it. */
23561 *ext_set
= **opt_p
;
23564 while (str
!= NULL
&& *str
!= 0)
23571 as_bad (_("invalid architectural extension"));
23576 ext
= strchr (str
, '+');
23581 len
= strlen (str
);
23583 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
23585 if (adding_value
!= 0)
23588 opt
= arm_extensions
;
23596 if (adding_value
== -1)
23599 opt
= arm_extensions
;
23601 else if (adding_value
!= 1)
23603 as_bad (_("must specify extensions to add before specifying "
23604 "those to remove"));
23611 as_bad (_("missing architectural extension"));
23615 gas_assert (adding_value
!= -1);
23616 gas_assert (opt
!= NULL
);
23618 /* Scan over the options table trying to find an exact match. */
23619 for (; opt
->name
!= NULL
; opt
++)
23620 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23622 /* Check we can apply the extension to this architecture. */
23623 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23625 as_bad (_("extension does not apply to the base architecture"));
23629 /* Add or remove the extension. */
23631 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23633 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23638 if (opt
->name
== NULL
)
23640 /* Did we fail to find an extension because it wasn't specified in
23641 alphabetical order, or because it does not exist? */
23643 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23644 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23647 if (opt
->name
== NULL
)
23648 as_bad (_("unknown architectural extension `%s'"), str
);
23650 as_bad (_("architectural extensions must be specified in "
23651 "alphabetical order"));
23657 /* We should skip the extension we've just matched the next time
23669 arm_parse_cpu (char *str
)
23671 const struct arm_cpu_option_table
*opt
;
23672 char *ext
= strchr (str
, '+');
23678 len
= strlen (str
);
23682 as_bad (_("missing cpu name `%s'"), str
);
23686 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23687 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23689 mcpu_cpu_opt
= &opt
->value
;
23690 mcpu_fpu_opt
= &opt
->default_fpu
;
23691 if (opt
->canonical_name
)
23692 strcpy (selected_cpu_name
, opt
->canonical_name
);
23697 for (i
= 0; i
< len
; i
++)
23698 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23699 selected_cpu_name
[i
] = 0;
23703 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23708 as_bad (_("unknown cpu `%s'"), str
);
23713 arm_parse_arch (char *str
)
23715 const struct arm_arch_option_table
*opt
;
23716 char *ext
= strchr (str
, '+');
23722 len
= strlen (str
);
23726 as_bad (_("missing architecture name `%s'"), str
);
23730 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23731 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
23733 march_cpu_opt
= &opt
->value
;
23734 march_fpu_opt
= &opt
->default_fpu
;
23735 strcpy (selected_cpu_name
, opt
->name
);
23738 return arm_parse_extension (ext
, &march_cpu_opt
);
23743 as_bad (_("unknown architecture `%s'\n"), str
);
23748 arm_parse_fpu (char * str
)
23750 const struct arm_option_fpu_value_table
* opt
;
23752 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23753 if (streq (opt
->name
, str
))
23755 mfpu_opt
= &opt
->value
;
23759 as_bad (_("unknown floating point format `%s'\n"), str
);
23764 arm_parse_float_abi (char * str
)
23766 const struct arm_option_value_table
* opt
;
23768 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23769 if (streq (opt
->name
, str
))
23771 mfloat_abi_opt
= opt
->value
;
23775 as_bad (_("unknown floating point abi `%s'\n"), str
);
23781 arm_parse_eabi (char * str
)
23783 const struct arm_option_value_table
*opt
;
23785 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23786 if (streq (opt
->name
, str
))
23788 meabi_flags
= opt
->value
;
23791 as_bad (_("unknown EABI `%s'\n"), str
);
23797 arm_parse_it_mode (char * str
)
23799 bfd_boolean ret
= TRUE
;
23801 if (streq ("arm", str
))
23802 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23803 else if (streq ("thumb", str
))
23804 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23805 else if (streq ("always", str
))
23806 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23807 else if (streq ("never", str
))
23808 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23811 as_bad (_("unknown implicit IT mode `%s', should be "\
23812 "arm, thumb, always, or never."), str
);
23819 struct arm_long_option_table arm_long_opts
[] =
23821 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23822 arm_parse_cpu
, NULL
},
23823 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23824 arm_parse_arch
, NULL
},
23825 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23826 arm_parse_fpu
, NULL
},
23827 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23828 arm_parse_float_abi
, NULL
},
23830 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23831 arm_parse_eabi
, NULL
},
23833 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23834 arm_parse_it_mode
, NULL
},
23835 {NULL
, NULL
, 0, NULL
}
23839 md_parse_option (int c
, char * arg
)
23841 struct arm_option_table
*opt
;
23842 const struct arm_legacy_option_table
*fopt
;
23843 struct arm_long_option_table
*lopt
;
23849 target_big_endian
= 1;
23855 target_big_endian
= 0;
23859 case OPTION_FIX_V4BX
:
23864 /* Listing option. Just ignore these, we don't support additional
23869 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23871 if (c
== opt
->option
[0]
23872 && ((arg
== NULL
&& opt
->option
[1] == 0)
23873 || streq (arg
, opt
->option
+ 1)))
23875 /* If the option is deprecated, tell the user. */
23876 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23877 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23878 arg
? arg
: "", _(opt
->deprecated
));
23880 if (opt
->var
!= NULL
)
23881 *opt
->var
= opt
->value
;
23887 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23889 if (c
== fopt
->option
[0]
23890 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23891 || streq (arg
, fopt
->option
+ 1)))
23893 /* If the option is deprecated, tell the user. */
23894 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23895 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23896 arg
? arg
: "", _(fopt
->deprecated
));
23898 if (fopt
->var
!= NULL
)
23899 *fopt
->var
= &fopt
->value
;
23905 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23907 /* These options are expected to have an argument. */
23908 if (c
== lopt
->option
[0]
23910 && strncmp (arg
, lopt
->option
+ 1,
23911 strlen (lopt
->option
+ 1)) == 0)
23913 /* If the option is deprecated, tell the user. */
23914 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23915 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23916 _(lopt
->deprecated
));
23918 /* Call the sup-option parser. */
23919 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23930 md_show_usage (FILE * fp
)
23932 struct arm_option_table
*opt
;
23933 struct arm_long_option_table
*lopt
;
23935 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23937 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23938 if (opt
->help
!= NULL
)
23939 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23941 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23942 if (lopt
->help
!= NULL
)
23943 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23947 -EB assemble code for a big-endian cpu\n"));
23952 -EL assemble code for a little-endian cpu\n"));
23956 --fix-v4bx Allow BX in ARMv4 code\n"));
23964 arm_feature_set flags
;
23965 } cpu_arch_ver_table
;
23967 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23968 least features first. */
23969 static const cpu_arch_ver_table cpu_arch_ver
[] =
23975 {4, ARM_ARCH_V5TE
},
23976 {5, ARM_ARCH_V5TEJ
},
23980 {11, ARM_ARCH_V6M
},
23981 {12, ARM_ARCH_V6SM
},
23982 {8, ARM_ARCH_V6T2
},
23983 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
},
23984 {10, ARM_ARCH_V7R
},
23985 {10, ARM_ARCH_V7M
},
23986 {14, ARM_ARCH_V8A
},
23990 /* Set an attribute if it has not already been set by the user. */
23992 aeabi_set_attribute_int (int tag
, int value
)
23995 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23996 || !attributes_set_explicitly
[tag
])
23997 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
24001 aeabi_set_attribute_string (int tag
, const char *value
)
24004 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24005 || !attributes_set_explicitly
[tag
])
24006 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
24009 /* Set the public EABI object attributes. */
24011 aeabi_set_public_attributes (void)
24016 int fp16_optional
= 0;
24017 arm_feature_set flags
;
24018 arm_feature_set tmp
;
24019 const cpu_arch_ver_table
*p
;
24021 /* Choose the architecture based on the capabilities of the requested cpu
24022 (if any) and/or the instructions actually used. */
24023 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
24024 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
24025 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
24027 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
24028 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
24030 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
24031 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
24033 /* Allow the user to override the reported architecture. */
24036 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
24037 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
24040 /* We need to make sure that the attributes do not identify us as v6S-M
24041 when the only v6S-M feature in use is the Operating System Extensions. */
24042 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
24043 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
24044 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
24048 for (p
= cpu_arch_ver
; p
->val
; p
++)
24050 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
24053 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
24057 /* The table lookup above finds the last architecture to contribute
24058 a new feature. Unfortunately, Tag13 is a subset of the union of
24059 v6T2 and v7-M, so it is never seen as contributing a new feature.
24060 We can not search for the last entry which is entirely used,
24061 because if no CPU is specified we build up only those flags
24062 actually used. Perhaps we should separate out the specified
24063 and implicit cases. Avoid taking this path for -march=all by
24064 checking for contradictory v7-A / v7-M features. */
24066 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
24067 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
24068 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
24071 /* Tag_CPU_name. */
24072 if (selected_cpu_name
[0])
24076 q
= selected_cpu_name
;
24077 if (strncmp (q
, "armv", 4) == 0)
24082 for (i
= 0; q
[i
]; i
++)
24083 q
[i
] = TOUPPER (q
[i
]);
24085 aeabi_set_attribute_string (Tag_CPU_name
, q
);
24088 /* Tag_CPU_arch. */
24089 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
24091 /* Tag_CPU_arch_profile. */
24092 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
24094 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
24096 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
24101 if (profile
!= '\0')
24102 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
24104 /* Tag_ARM_ISA_use. */
24105 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
24107 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
24109 /* Tag_THUMB_ISA_use. */
24110 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
24112 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
24113 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
24115 /* Tag_VFP_arch. */
24116 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8
))
24117 aeabi_set_attribute_int (Tag_VFP_arch
, 7);
24118 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
24119 aeabi_set_attribute_int (Tag_VFP_arch
,
24120 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
24122 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
24125 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
24127 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
24129 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
24132 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
24133 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
24134 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
24135 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
24136 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
24138 /* Tag_ABI_HardFP_use. */
24139 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
24140 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
24141 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
24143 /* Tag_WMMX_arch. */
24144 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
24145 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
24146 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
24147 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
24149 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24150 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
24151 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
24152 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
24154 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
24156 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
24160 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
24165 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24166 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
24167 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
24171 We set Tag_DIV_use to two when integer divide instructions have been used
24172 in ARM state, or when Thumb integer divide instructions have been used,
24173 but we have no architecture profile set, nor have we any ARM instructions.
24175 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24178 For new architectures we will have to check these tests. */
24179 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
24180 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
24181 aeabi_set_attribute_int (Tag_DIV_use
, 0);
24182 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
24183 || (profile
== '\0'
24184 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
24185 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
24186 aeabi_set_attribute_int (Tag_DIV_use
, 2);
24188 /* Tag_MP_extension_use. */
24189 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
24190 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
24192 /* Tag Virtualization_use. */
24193 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
24195 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
24198 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
24201 /* Add the default contents for the .ARM.attributes section. */
24205 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24208 aeabi_set_public_attributes ();
24210 #endif /* OBJ_ELF */
24213 /* Parse a .cpu directive. */
24216 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
24218 const struct arm_cpu_option_table
*opt
;
24222 name
= input_line_pointer
;
24223 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24224 input_line_pointer
++;
24225 saved_char
= *input_line_pointer
;
24226 *input_line_pointer
= 0;
24228 /* Skip the first "all" entry. */
24229 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
24230 if (streq (opt
->name
, name
))
24232 mcpu_cpu_opt
= &opt
->value
;
24233 selected_cpu
= opt
->value
;
24234 if (opt
->canonical_name
)
24235 strcpy (selected_cpu_name
, opt
->canonical_name
);
24239 for (i
= 0; opt
->name
[i
]; i
++)
24240 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24242 selected_cpu_name
[i
] = 0;
24244 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24245 *input_line_pointer
= saved_char
;
24246 demand_empty_rest_of_line ();
24249 as_bad (_("unknown cpu `%s'"), name
);
24250 *input_line_pointer
= saved_char
;
24251 ignore_rest_of_line ();
24255 /* Parse a .arch directive. */
24258 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
24260 const struct arm_arch_option_table
*opt
;
24264 name
= input_line_pointer
;
24265 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24266 input_line_pointer
++;
24267 saved_char
= *input_line_pointer
;
24268 *input_line_pointer
= 0;
24270 /* Skip the first "all" entry. */
24271 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
24272 if (streq (opt
->name
, name
))
24274 mcpu_cpu_opt
= &opt
->value
;
24275 selected_cpu
= opt
->value
;
24276 strcpy (selected_cpu_name
, opt
->name
);
24277 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24278 *input_line_pointer
= saved_char
;
24279 demand_empty_rest_of_line ();
24283 as_bad (_("unknown architecture `%s'\n"), name
);
24284 *input_line_pointer
= saved_char
;
24285 ignore_rest_of_line ();
24289 /* Parse a .object_arch directive. */
24292 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
24294 const struct arm_arch_option_table
*opt
;
24298 name
= input_line_pointer
;
24299 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24300 input_line_pointer
++;
24301 saved_char
= *input_line_pointer
;
24302 *input_line_pointer
= 0;
24304 /* Skip the first "all" entry. */
24305 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
24306 if (streq (opt
->name
, name
))
24308 object_arch
= &opt
->value
;
24309 *input_line_pointer
= saved_char
;
24310 demand_empty_rest_of_line ();
24314 as_bad (_("unknown architecture `%s'\n"), name
);
24315 *input_line_pointer
= saved_char
;
24316 ignore_rest_of_line ();
24319 /* Parse a .arch_extension directive. */
24322 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
24324 const struct arm_option_extension_value_table
*opt
;
24327 int adding_value
= 1;
24329 name
= input_line_pointer
;
24330 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24331 input_line_pointer
++;
24332 saved_char
= *input_line_pointer
;
24333 *input_line_pointer
= 0;
24335 if (strlen (name
) >= 2
24336 && strncmp (name
, "no", 2) == 0)
24342 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24343 if (streq (opt
->name
, name
))
24345 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
24347 as_bad (_("architectural extension `%s' is not allowed for the "
24348 "current base architecture"), name
);
24353 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
24355 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
24357 mcpu_cpu_opt
= &selected_cpu
;
24358 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24359 *input_line_pointer
= saved_char
;
24360 demand_empty_rest_of_line ();
24364 if (opt
->name
== NULL
)
24365 as_bad (_("unknown architecture `%s'\n"), name
);
24367 *input_line_pointer
= saved_char
;
24368 ignore_rest_of_line ();
24371 /* Parse a .fpu directive. */
24374 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
24376 const struct arm_option_fpu_value_table
*opt
;
24380 name
= input_line_pointer
;
24381 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24382 input_line_pointer
++;
24383 saved_char
= *input_line_pointer
;
24384 *input_line_pointer
= 0;
24386 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24387 if (streq (opt
->name
, name
))
24389 mfpu_opt
= &opt
->value
;
24390 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24391 *input_line_pointer
= saved_char
;
24392 demand_empty_rest_of_line ();
24396 as_bad (_("unknown floating point format `%s'\n"), name
);
24397 *input_line_pointer
= saved_char
;
24398 ignore_rest_of_line ();
24401 /* Copy symbol information. */
24404 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
24406 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
24410 /* Given a symbolic attribute NAME, return the proper integer value.
24411 Returns -1 if the attribute is not known. */
24414 arm_convert_symbolic_attribute (const char *name
)
24416 static const struct
24421 attribute_table
[] =
24423 /* When you modify this table you should
24424 also modify the list in doc/c-arm.texi. */
24425 #define T(tag) {#tag, tag}
24426 T (Tag_CPU_raw_name
),
24429 T (Tag_CPU_arch_profile
),
24430 T (Tag_ARM_ISA_use
),
24431 T (Tag_THUMB_ISA_use
),
24435 T (Tag_Advanced_SIMD_arch
),
24436 T (Tag_PCS_config
),
24437 T (Tag_ABI_PCS_R9_use
),
24438 T (Tag_ABI_PCS_RW_data
),
24439 T (Tag_ABI_PCS_RO_data
),
24440 T (Tag_ABI_PCS_GOT_use
),
24441 T (Tag_ABI_PCS_wchar_t
),
24442 T (Tag_ABI_FP_rounding
),
24443 T (Tag_ABI_FP_denormal
),
24444 T (Tag_ABI_FP_exceptions
),
24445 T (Tag_ABI_FP_user_exceptions
),
24446 T (Tag_ABI_FP_number_model
),
24447 T (Tag_ABI_align_needed
),
24448 T (Tag_ABI_align8_needed
),
24449 T (Tag_ABI_align_preserved
),
24450 T (Tag_ABI_align8_preserved
),
24451 T (Tag_ABI_enum_size
),
24452 T (Tag_ABI_HardFP_use
),
24453 T (Tag_ABI_VFP_args
),
24454 T (Tag_ABI_WMMX_args
),
24455 T (Tag_ABI_optimization_goals
),
24456 T (Tag_ABI_FP_optimization_goals
),
24457 T (Tag_compatibility
),
24458 T (Tag_CPU_unaligned_access
),
24459 T (Tag_FP_HP_extension
),
24460 T (Tag_VFP_HP_extension
),
24461 T (Tag_ABI_FP_16bit_format
),
24462 T (Tag_MPextension_use
),
24464 T (Tag_nodefaults
),
24465 T (Tag_also_compatible_with
),
24466 T (Tag_conformance
),
24468 T (Tag_Virtualization_use
),
24469 /* We deliberately do not include Tag_MPextension_use_legacy. */
24477 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
24478 if (streq (name
, attribute_table
[i
].name
))
24479 return attribute_table
[i
].tag
;
24485 /* Apply sym value for relocations only in the case that
24486 they are for local symbols and you have the respective
24487 architectural feature for blx and simple switches. */
24489 arm_apply_sym_value (struct fix
* fixP
)
24492 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24493 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
24495 switch (fixP
->fx_r_type
)
24497 case BFD_RELOC_ARM_PCREL_BLX
:
24498 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24499 if (ARM_IS_FUNC (fixP
->fx_addsy
))
24503 case BFD_RELOC_ARM_PCREL_CALL
:
24504 case BFD_RELOC_THUMB_PCREL_BLX
:
24505 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
24516 #endif /* OBJ_ELF */