1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
158 /* Understand CodeComposer Studio assembly syntax. */
159 bfd_boolean codecomposer_syntax
= FALSE
;
161 /* Variables that we set while parsing command-line options. Once all
162 options have been read we re-process these values to set the real
165 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
166 instead of -mcpu=arm1). */
167 static const arm_feature_set
*legacy_cpu
= NULL
;
168 static const arm_feature_set
*legacy_fpu
= NULL
;
170 /* CPU, extension and FPU feature bits selected by -mcpu. */
171 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
172 static arm_feature_set
*mcpu_ext_opt
= NULL
;
173 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
175 /* CPU, extension and FPU feature bits selected by -march. */
176 static const arm_feature_set
*march_cpu_opt
= NULL
;
177 static arm_feature_set
*march_ext_opt
= NULL
;
178 static const arm_feature_set
*march_fpu_opt
= NULL
;
180 /* Feature bits selected by -mfpu. */
181 static const arm_feature_set
*mfpu_opt
= NULL
;
183 /* Constants for known architecture features. */
184 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
185 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
186 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
187 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
188 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
189 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
190 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
192 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
194 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
197 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
200 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
201 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
202 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
203 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
204 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
205 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
206 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
207 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
208 static const arm_feature_set arm_ext_v4t_5
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
210 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
211 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
212 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
213 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
214 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
215 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
216 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
217 /* Only for compatability of hint instructions. */
218 static const arm_feature_set arm_ext_v6k_v6t2
=
219 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
220 static const arm_feature_set arm_ext_v6_notm
=
221 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
222 static const arm_feature_set arm_ext_v6_dsp
=
223 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
224 static const arm_feature_set arm_ext_barrier
=
225 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
226 static const arm_feature_set arm_ext_msr
=
227 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
228 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
229 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
230 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
231 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
235 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
236 static const arm_feature_set arm_ext_m
=
237 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
238 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
239 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
240 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
241 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
242 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
243 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
244 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
245 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
246 static const arm_feature_set arm_ext_v8m_main
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
248 static const arm_feature_set arm_ext_v8_1m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
250 /* Instructions in ARMv8-M only found in M profile architectures. */
251 static const arm_feature_set arm_ext_v8m_m_only
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
253 static const arm_feature_set arm_ext_v6t2_v8m
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
255 /* Instructions shared between ARMv8-A and ARMv8-M. */
256 static const arm_feature_set arm_ext_atomics
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
259 /* DSP instructions Tag_DSP_extension refers to. */
260 static const arm_feature_set arm_ext_dsp
=
261 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
263 static const arm_feature_set arm_ext_ras
=
264 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
265 /* FP16 instructions. */
266 static const arm_feature_set arm_ext_fp16
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
268 static const arm_feature_set arm_ext_fp16_fml
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
270 static const arm_feature_set arm_ext_v8_2
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
272 static const arm_feature_set arm_ext_v8_3
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
274 static const arm_feature_set arm_ext_sb
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
276 static const arm_feature_set arm_ext_predres
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
279 static const arm_feature_set arm_arch_any
= ARM_ANY
;
281 static const arm_feature_set fpu_any
= FPU_ANY
;
283 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
284 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
285 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
287 static const arm_feature_set arm_cext_iwmmxt2
=
288 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
289 static const arm_feature_set arm_cext_iwmmxt
=
290 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
291 static const arm_feature_set arm_cext_xscale
=
292 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
293 static const arm_feature_set arm_cext_maverick
=
294 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
295 static const arm_feature_set fpu_fpa_ext_v1
=
296 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
297 static const arm_feature_set fpu_fpa_ext_v2
=
298 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
299 static const arm_feature_set fpu_vfp_ext_v1xd
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
301 static const arm_feature_set fpu_vfp_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
303 static const arm_feature_set fpu_vfp_ext_v2
=
304 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
305 static const arm_feature_set fpu_vfp_ext_v3xd
=
306 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
307 static const arm_feature_set fpu_vfp_ext_v3
=
308 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
309 static const arm_feature_set fpu_vfp_ext_d32
=
310 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
311 static const arm_feature_set fpu_neon_ext_v1
=
312 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
313 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
314 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
315 static const arm_feature_set mve_ext
=
316 ARM_FEATURE_COPROC (FPU_MVE
);
317 static const arm_feature_set mve_fp_ext
=
318 ARM_FEATURE_COPROC (FPU_MVE_FP
);
320 static const arm_feature_set fpu_vfp_fp16
=
321 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
322 static const arm_feature_set fpu_neon_ext_fma
=
323 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
325 static const arm_feature_set fpu_vfp_ext_fma
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
327 static const arm_feature_set fpu_vfp_ext_armv8
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
329 static const arm_feature_set fpu_vfp_ext_armv8xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
331 static const arm_feature_set fpu_neon_ext_armv8
=
332 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
333 static const arm_feature_set fpu_crypto_ext_armv8
=
334 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
335 static const arm_feature_set crc_ext_armv8
=
336 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
337 static const arm_feature_set fpu_neon_ext_v8_1
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
339 static const arm_feature_set fpu_neon_ext_dotprod
=
340 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
342 static int mfloat_abi_opt
= -1;
343 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
345 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
346 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
348 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
349 /* Feature bits selected by the last -mcpu/-march or by the combination of the
350 last .cpu/.arch directive .arch_extension directives since that
352 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
353 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
354 static arm_feature_set selected_fpu
= FPU_NONE
;
355 /* Feature bits selected by the last .object_arch directive. */
356 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
357 /* Must be long enough to hold any of the names in arm_cpus. */
358 static char selected_cpu_name
[20];
360 extern FLONUM_TYPE generic_floating_point_number
;
362 /* Return if no cpu was selected on command-line. */
364 no_cpu_selected (void)
366 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
371 static int meabi_flags
= EABI_DEFAULT
;
373 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
376 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
381 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
386 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
387 symbolS
* GOT_symbol
;
390 /* 0: assemble for ARM,
391 1: assemble for Thumb,
392 2: assemble for Thumb even though target CPU does not support thumb
394 static int thumb_mode
= 0;
395 /* A value distinct from the possible values for thumb_mode that we
396 can use to record whether thumb_mode has been copied into the
397 tc_frag_data field of a frag. */
398 #define MODE_RECORDED (1 << 4)
400 /* Specifies the intrinsic IT insn behavior mode. */
401 enum implicit_it_mode
403 IMPLICIT_IT_MODE_NEVER
= 0x00,
404 IMPLICIT_IT_MODE_ARM
= 0x01,
405 IMPLICIT_IT_MODE_THUMB
= 0x02,
406 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
408 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
410 /* If unified_syntax is true, we are processing the new unified
411 ARM/Thumb syntax. Important differences from the old ARM mode:
413 - Immediate operands do not require a # prefix.
414 - Conditional affixes always appear at the end of the
415 instruction. (For backward compatibility, those instructions
416 that formerly had them in the middle, continue to accept them
418 - The IT instruction may appear, and if it does is validated
419 against subsequent conditional affixes. It does not generate
422 Important differences from the old Thumb mode:
424 - Immediate operands do not require a # prefix.
425 - Most of the V6T2 instructions are only available in unified mode.
426 - The .N and .W suffixes are recognized and honored (it is an error
427 if they cannot be honored).
428 - All instructions set the flags if and only if they have an 's' affix.
429 - Conditional affixes may be used. They are validated against
430 preceding IT instructions. Unlike ARM mode, you cannot use a
431 conditional affix except in the scope of an IT instruction. */
433 static bfd_boolean unified_syntax
= FALSE
;
435 /* An immediate operand can start with #, and ld*, st*, pld operands
436 can contain [ and ]. We need to tell APP not to elide whitespace
437 before a [, which can appear as the first operand for pld.
438 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
439 const char arm_symbol_chars
[] = "#[]{}";
454 enum neon_el_type type
;
458 #define NEON_MAX_TYPE_ELS 4
462 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
466 enum pred_instruction_type
472 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
473 if inside, should be the last one. */
474 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
475 i.e. BKPT and NOP. */
476 IT_INSN
, /* The IT insn has been parsed. */
477 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
478 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
479 a predication code. */
480 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
483 /* The maximum number of operands we need. */
484 #define ARM_IT_MAX_OPERANDS 6
485 #define ARM_IT_MAX_RELOCS 3
490 unsigned long instruction
;
494 /* "uncond_value" is set to the value in place of the conditional field in
495 unconditional versions of the instruction, or -1 if nothing is
498 struct neon_type vectype
;
499 /* This does not indicate an actual NEON instruction, only that
500 the mnemonic accepts neon-style type suffixes. */
502 /* Set to the opcode if the instruction needs relaxation.
503 Zero if the instruction is not relaxed. */
507 bfd_reloc_code_real_type type
;
510 } relocs
[ARM_IT_MAX_RELOCS
];
512 enum pred_instruction_type pred_insn_type
;
518 struct neon_type_el vectype
;
519 unsigned present
: 1; /* Operand present. */
520 unsigned isreg
: 1; /* Operand was a register. */
521 unsigned immisreg
: 2; /* .imm field is a second register.
522 0: imm, 1: gpr, 2: MVE Q-register. */
523 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
527 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
528 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
529 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
530 instructions. This allows us to disambiguate ARM <-> vector insns. */
531 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
532 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
533 unsigned isquad
: 1; /* Operand is SIMD quad register. */
534 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
535 unsigned iszr
: 1; /* Operand is ZR register. */
536 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
537 unsigned writeback
: 1; /* Operand has trailing ! */
538 unsigned preind
: 1; /* Preindexed address. */
539 unsigned postind
: 1; /* Postindexed address. */
540 unsigned negative
: 1; /* Index register was negated. */
541 unsigned shifted
: 1; /* Shift applied to operation. */
542 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
543 } operands
[ARM_IT_MAX_OPERANDS
];
546 static struct arm_it inst
;
548 #define NUM_FLOAT_VALS 8
550 const char * fp_const
[] =
552 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
555 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
565 #define CP_T_X 0x00008000
566 #define CP_T_Y 0x00400000
568 #define CONDS_BIT 0x00100000
569 #define LOAD_BIT 0x00100000
571 #define DOUBLE_LOAD_FLAG 0x00000001
575 const char * template_name
;
579 #define COND_ALWAYS 0xE
583 const char * template_name
;
587 struct asm_barrier_opt
589 const char * template_name
;
591 const arm_feature_set arch
;
594 /* The bit that distinguishes CPSR and SPSR. */
595 #define SPSR_BIT (1 << 22)
597 /* The individual PSR flag bits. */
598 #define PSR_c (1 << 16)
599 #define PSR_x (1 << 17)
600 #define PSR_s (1 << 18)
601 #define PSR_f (1 << 19)
606 bfd_reloc_code_real_type reloc
;
611 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
612 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
617 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
620 /* Bits for DEFINED field in neon_typed_alias. */
621 #define NTA_HASTYPE 1
622 #define NTA_HASINDEX 2
624 struct neon_typed_alias
626 unsigned char defined
;
628 struct neon_type_el eltype
;
631 /* ARM register categories. This includes coprocessor numbers and various
632 architecture extensions' registers. Each entry should have an error message
633 in reg_expected_msgs below. */
663 /* Structure for a hash table entry for a register.
664 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
665 information which states whether a vector type or index is specified (for a
666 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
672 unsigned char builtin
;
673 struct neon_typed_alias
* neon
;
676 /* Diagnostics used when we don't get a register of the expected type. */
677 const char * const reg_expected_msgs
[] =
679 [REG_TYPE_RN
] = N_("ARM register expected"),
680 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
681 [REG_TYPE_CN
] = N_("co-processor register expected"),
682 [REG_TYPE_FN
] = N_("FPA register expected"),
683 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
684 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
685 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
686 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
687 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
688 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
689 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
691 [REG_TYPE_VFC
] = N_("VFP system register expected"),
692 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
693 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
694 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
695 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
696 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
697 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
698 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
699 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
700 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
701 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
702 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
703 [REG_TYPE_RNB
] = N_("")
706 /* Some well known registers that we refer to directly elsewhere. */
712 /* ARM instructions take 4bytes in the object file, Thumb instructions
718 /* Basic string to match. */
719 const char * template_name
;
721 /* Parameters to instruction. */
722 unsigned int operands
[8];
724 /* Conditional tag - see opcode_lookup. */
725 unsigned int tag
: 4;
727 /* Basic instruction code. */
730 /* Thumb-format instruction code. */
733 /* Which architecture variant provides this instruction. */
734 const arm_feature_set
* avariant
;
735 const arm_feature_set
* tvariant
;
737 /* Function to call to encode instruction in ARM format. */
738 void (* aencode
) (void);
740 /* Function to call to encode instruction in Thumb format. */
741 void (* tencode
) (void);
743 /* Indicates whether this instruction may be vector predicated. */
744 unsigned int mayBeVecPred
: 1;
747 /* Defines for various bits that we will want to toggle. */
748 #define INST_IMMEDIATE 0x02000000
749 #define OFFSET_REG 0x02000000
750 #define HWOFFSET_IMM 0x00400000
751 #define SHIFT_BY_REG 0x00000010
752 #define PRE_INDEX 0x01000000
753 #define INDEX_UP 0x00800000
754 #define WRITE_BACK 0x00200000
755 #define LDM_TYPE_2_OR_3 0x00400000
756 #define CPSI_MMOD 0x00020000
758 #define LITERAL_MASK 0xf000f000
759 #define OPCODE_MASK 0xfe1fffff
760 #define V4_STR_BIT 0x00000020
761 #define VLDR_VMOV_SAME 0x0040f000
763 #define T2_SUBS_PC_LR 0xf3de8f00
765 #define DATA_OP_SHIFT 21
766 #define SBIT_SHIFT 20
768 #define T2_OPCODE_MASK 0xfe1fffff
769 #define T2_DATA_OP_SHIFT 21
770 #define T2_SBIT_SHIFT 20
772 #define A_COND_MASK 0xf0000000
773 #define A_PUSH_POP_OP_MASK 0x0fff0000
775 /* Opcodes for pushing/poping registers to/from the stack. */
776 #define A1_OPCODE_PUSH 0x092d0000
777 #define A2_OPCODE_PUSH 0x052d0004
778 #define A2_OPCODE_POP 0x049d0004
780 /* Codes to distinguish the arithmetic instructions. */
791 #define OPCODE_CMP 10
792 #define OPCODE_CMN 11
793 #define OPCODE_ORR 12
794 #define OPCODE_MOV 13
795 #define OPCODE_BIC 14
796 #define OPCODE_MVN 15
798 #define T2_OPCODE_AND 0
799 #define T2_OPCODE_BIC 1
800 #define T2_OPCODE_ORR 2
801 #define T2_OPCODE_ORN 3
802 #define T2_OPCODE_EOR 4
803 #define T2_OPCODE_ADD 8
804 #define T2_OPCODE_ADC 10
805 #define T2_OPCODE_SBC 11
806 #define T2_OPCODE_SUB 13
807 #define T2_OPCODE_RSB 14
809 #define T_OPCODE_MUL 0x4340
810 #define T_OPCODE_TST 0x4200
811 #define T_OPCODE_CMN 0x42c0
812 #define T_OPCODE_NEG 0x4240
813 #define T_OPCODE_MVN 0x43c0
815 #define T_OPCODE_ADD_R3 0x1800
816 #define T_OPCODE_SUB_R3 0x1a00
817 #define T_OPCODE_ADD_HI 0x4400
818 #define T_OPCODE_ADD_ST 0xb000
819 #define T_OPCODE_SUB_ST 0xb080
820 #define T_OPCODE_ADD_SP 0xa800
821 #define T_OPCODE_ADD_PC 0xa000
822 #define T_OPCODE_ADD_I8 0x3000
823 #define T_OPCODE_SUB_I8 0x3800
824 #define T_OPCODE_ADD_I3 0x1c00
825 #define T_OPCODE_SUB_I3 0x1e00
827 #define T_OPCODE_ASR_R 0x4100
828 #define T_OPCODE_LSL_R 0x4080
829 #define T_OPCODE_LSR_R 0x40c0
830 #define T_OPCODE_ROR_R 0x41c0
831 #define T_OPCODE_ASR_I 0x1000
832 #define T_OPCODE_LSL_I 0x0000
833 #define T_OPCODE_LSR_I 0x0800
835 #define T_OPCODE_MOV_I8 0x2000
836 #define T_OPCODE_CMP_I8 0x2800
837 #define T_OPCODE_CMP_LR 0x4280
838 #define T_OPCODE_MOV_HR 0x4600
839 #define T_OPCODE_CMP_HR 0x4500
841 #define T_OPCODE_LDR_PC 0x4800
842 #define T_OPCODE_LDR_SP 0x9800
843 #define T_OPCODE_STR_SP 0x9000
844 #define T_OPCODE_LDR_IW 0x6800
845 #define T_OPCODE_STR_IW 0x6000
846 #define T_OPCODE_LDR_IH 0x8800
847 #define T_OPCODE_STR_IH 0x8000
848 #define T_OPCODE_LDR_IB 0x7800
849 #define T_OPCODE_STR_IB 0x7000
850 #define T_OPCODE_LDR_RW 0x5800
851 #define T_OPCODE_STR_RW 0x5000
852 #define T_OPCODE_LDR_RH 0x5a00
853 #define T_OPCODE_STR_RH 0x5200
854 #define T_OPCODE_LDR_RB 0x5c00
855 #define T_OPCODE_STR_RB 0x5400
857 #define T_OPCODE_PUSH 0xb400
858 #define T_OPCODE_POP 0xbc00
860 #define T_OPCODE_BRANCH 0xe000
862 #define THUMB_SIZE 2 /* Size of thumb instruction. */
863 #define THUMB_PP_PC_LR 0x0100
864 #define THUMB_LOAD_BIT 0x0800
865 #define THUMB2_LOAD_BIT 0x00100000
867 #define BAD_SYNTAX _("syntax error")
868 #define BAD_ARGS _("bad arguments to instruction")
869 #define BAD_SP _("r13 not allowed here")
870 #define BAD_PC _("r15 not allowed here")
871 #define BAD_ODD _("Odd register not allowed here")
872 #define BAD_EVEN _("Even register not allowed here")
873 #define BAD_COND _("instruction cannot be conditional")
874 #define BAD_OVERLAP _("registers may not be the same")
875 #define BAD_HIREG _("lo register required")
876 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
877 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
878 #define BAD_BRANCH _("branch must be last instruction in IT block")
879 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
880 #define BAD_NOT_IT _("instruction not allowed in IT block")
881 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
882 #define BAD_FPU _("selected FPU does not support instruction")
883 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
884 #define BAD_OUT_VPT \
885 _("vector predicated instruction should be in VPT/VPST block")
886 #define BAD_IT_COND _("incorrect condition in IT block")
887 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
888 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
889 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
890 #define BAD_PC_ADDRESSING \
891 _("cannot use register index with PC-relative addressing")
892 #define BAD_PC_WRITEBACK \
893 _("cannot use writeback with PC-relative addressing")
894 #define BAD_RANGE _("branch out of range")
895 #define BAD_FP16 _("selected processor does not support fp16 instruction")
896 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
897 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
898 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
900 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
902 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
904 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
906 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
907 #define BAD_MVE_AUTO \
908 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
909 " use a valid -march or -mcpu option.")
910 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
911 "and source operands makes instruction UNPREDICTABLE")
912 #define BAD_EL_TYPE _("bad element type for instruction")
913 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
915 static struct hash_control
* arm_ops_hsh
;
916 static struct hash_control
* arm_cond_hsh
;
917 static struct hash_control
* arm_vcond_hsh
;
918 static struct hash_control
* arm_shift_hsh
;
919 static struct hash_control
* arm_psr_hsh
;
920 static struct hash_control
* arm_v7m_psr_hsh
;
921 static struct hash_control
* arm_reg_hsh
;
922 static struct hash_control
* arm_reloc_hsh
;
923 static struct hash_control
* arm_barrier_opt_hsh
;
925 /* Stuff needed to resolve the label ambiguity
934 symbolS
* last_label_seen
;
935 static int label_is_thumb_function_name
= FALSE
;
937 /* Literal pool structure. Held on a per-section
938 and per-sub-section basis. */
940 #define MAX_LITERAL_POOL_SIZE 1024
941 typedef struct literal_pool
943 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
944 unsigned int next_free_entry
;
950 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
952 struct literal_pool
* next
;
953 unsigned int alignment
;
956 /* Pointer to a linked list of literal pools. */
957 literal_pool
* list_of_pools
= NULL
;
959 typedef enum asmfunc_states
962 WAITING_ASMFUNC_NAME
,
966 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
969 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
971 static struct current_pred now_pred
;
975 now_pred_compatible (int cond
)
977 return (cond
& ~1) == (now_pred
.cc
& ~1);
981 conditional_insn (void)
983 return inst
.cond
!= COND_ALWAYS
;
986 static int in_pred_block (void);
988 static int handle_pred_state (void);
990 static void force_automatic_it_block_close (void);
992 static void it_fsm_post_encode (void);
994 #define set_pred_insn_type(type) \
997 inst.pred_insn_type = type; \
998 if (handle_pred_state () == FAIL) \
1003 #define set_pred_insn_type_nonvoid(type, failret) \
1006 inst.pred_insn_type = type; \
1007 if (handle_pred_state () == FAIL) \
1012 #define set_pred_insn_type_last() \
1015 if (inst.cond == COND_ALWAYS) \
1016 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1018 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1022 /* Toggle value[pos]. */
1023 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1027 /* This array holds the chars that always start a comment. If the
1028 pre-processor is disabled, these aren't very useful. */
1029 char arm_comment_chars
[] = "@";
1031 /* This array holds the chars that only start a comment at the beginning of
1032 a line. If the line seems to have the form '# 123 filename'
1033 .line and .file directives will appear in the pre-processed output. */
1034 /* Note that input_file.c hand checks for '#' at the beginning of the
1035 first line of the input file. This is because the compiler outputs
1036 #NO_APP at the beginning of its output. */
1037 /* Also note that comments like this one will always work. */
1038 const char line_comment_chars
[] = "#";
1040 char arm_line_separator_chars
[] = ";";
1042 /* Chars that can be used to separate mant
1043 from exp in floating point numbers. */
1044 const char EXP_CHARS
[] = "eE";
1046 /* Chars that mean this number is a floating point constant. */
1047 /* As in 0f12.456 */
1048 /* or 0d1.2345e12 */
1050 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1052 /* Prefix characters that indicate the start of an immediate
1054 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1056 /* Separator character handling. */
1058 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1060 enum fp_16bit_format
1062 ARM_FP16_FORMAT_IEEE
= 0x1,
1063 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1064 ARM_FP16_FORMAT_DEFAULT
= 0x3
1067 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1071 skip_past_char (char ** str
, char c
)
1073 /* PR gas/14987: Allow for whitespace before the expected character. */
1074 skip_whitespace (*str
);
1085 #define skip_past_comma(str) skip_past_char (str, ',')
1087 /* Arithmetic expressions (possibly involving symbols). */
1089 /* Return TRUE if anything in the expression is a bignum. */
1092 walk_no_bignums (symbolS
* sp
)
1094 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1097 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1099 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1100 || (symbol_get_value_expression (sp
)->X_op_symbol
1101 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1107 static bfd_boolean in_my_get_expression
= FALSE
;
1109 /* Third argument to my_get_expression. */
1110 #define GE_NO_PREFIX 0
1111 #define GE_IMM_PREFIX 1
1112 #define GE_OPT_PREFIX 2
1113 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1114 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1115 #define GE_OPT_PREFIX_BIG 3
1118 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1122 /* In unified syntax, all prefixes are optional. */
1124 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1127 switch (prefix_mode
)
1129 case GE_NO_PREFIX
: break;
1131 if (!is_immediate_prefix (**str
))
1133 inst
.error
= _("immediate expression requires a # prefix");
1139 case GE_OPT_PREFIX_BIG
:
1140 if (is_immediate_prefix (**str
))
1147 memset (ep
, 0, sizeof (expressionS
));
1149 save_in
= input_line_pointer
;
1150 input_line_pointer
= *str
;
1151 in_my_get_expression
= TRUE
;
1153 in_my_get_expression
= FALSE
;
1155 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1157 /* We found a bad or missing expression in md_operand(). */
1158 *str
= input_line_pointer
;
1159 input_line_pointer
= save_in
;
1160 if (inst
.error
== NULL
)
1161 inst
.error
= (ep
->X_op
== O_absent
1162 ? _("missing expression") :_("bad expression"));
1166 /* Get rid of any bignums now, so that we don't generate an error for which
1167 we can't establish a line number later on. Big numbers are never valid
1168 in instructions, which is where this routine is always called. */
1169 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1170 && (ep
->X_op
== O_big
1171 || (ep
->X_add_symbol
1172 && (walk_no_bignums (ep
->X_add_symbol
)
1174 && walk_no_bignums (ep
->X_op_symbol
))))))
1176 inst
.error
= _("invalid constant");
1177 *str
= input_line_pointer
;
1178 input_line_pointer
= save_in
;
1182 *str
= input_line_pointer
;
1183 input_line_pointer
= save_in
;
1187 /* Turn a string in input_line_pointer into a floating point constant
1188 of type TYPE, and store the appropriate bytes in *LITP. The number
1189 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1190 returned, or NULL on OK.
1192 Note that fp constants aren't represent in the normal way on the ARM.
1193 In big endian mode, things are as expected. However, in little endian
1194 mode fp constants are big-endian word-wise, and little-endian byte-wise
1195 within the words. For example, (double) 1.1 in big endian mode is
1196 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1197 the byte sequence 99 99 f1 3f 9a 99 99 99.
1199 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1202 md_atof (int type
, char * litP
, int * sizeP
)
1205 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1242 return _("Unrecognized or unsupported floating point constant");
1245 t
= atof_ieee (input_line_pointer
, type
, words
);
1247 input_line_pointer
= t
;
1248 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1250 if (target_big_endian
|| prec
== 1)
1251 for (i
= 0; i
< prec
; i
++)
1253 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1254 litP
+= sizeof (LITTLENUM_TYPE
);
1256 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1257 for (i
= prec
- 1; i
>= 0; i
--)
1259 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1260 litP
+= sizeof (LITTLENUM_TYPE
);
1263 /* For a 4 byte float the order of elements in `words' is 1 0.
1264 For an 8 byte float the order is 1 0 3 2. */
1265 for (i
= 0; i
< prec
; i
+= 2)
1267 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1268 sizeof (LITTLENUM_TYPE
));
1269 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1270 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1271 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1277 /* We handle all bad expressions here, so that we can report the faulty
1278 instruction in the error message. */
1281 md_operand (expressionS
* exp
)
1283 if (in_my_get_expression
)
1284 exp
->X_op
= O_illegal
;
1287 /* Immediate values. */
1290 /* Generic immediate-value read function for use in directives.
1291 Accepts anything that 'expression' can fold to a constant.
1292 *val receives the number. */
1295 immediate_for_directive (int *val
)
1298 exp
.X_op
= O_illegal
;
1300 if (is_immediate_prefix (*input_line_pointer
))
1302 input_line_pointer
++;
1306 if (exp
.X_op
!= O_constant
)
1308 as_bad (_("expected #constant"));
1309 ignore_rest_of_line ();
1312 *val
= exp
.X_add_number
;
1317 /* Register parsing. */
1319 /* Generic register parser. CCP points to what should be the
1320 beginning of a register name. If it is indeed a valid register
1321 name, advance CCP over it and return the reg_entry structure;
1322 otherwise return NULL. Does not issue diagnostics. */
1324 static struct reg_entry
*
1325 arm_reg_parse_multi (char **ccp
)
1329 struct reg_entry
*reg
;
1331 skip_whitespace (start
);
1333 #ifdef REGISTER_PREFIX
1334 if (*start
!= REGISTER_PREFIX
)
1338 #ifdef OPTIONAL_REGISTER_PREFIX
1339 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1344 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1349 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1351 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1361 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1362 enum arm_reg_type type
)
1364 /* Alternative syntaxes are accepted for a few register classes. */
1371 /* Generic coprocessor register names are allowed for these. */
1372 if (reg
&& reg
->type
== REG_TYPE_CN
)
1377 /* For backward compatibility, a bare number is valid here. */
1379 unsigned long processor
= strtoul (start
, ccp
, 10);
1380 if (*ccp
!= start
&& processor
<= 15)
1385 case REG_TYPE_MMXWC
:
1386 /* WC includes WCG. ??? I'm not sure this is true for all
1387 instructions that take WC registers. */
1388 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1399 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1400 return value is the register number or FAIL. */
1403 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1406 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1409 /* Do not allow a scalar (reg+index) to parse as a register. */
1410 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1413 if (reg
&& reg
->type
== type
)
1416 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1423 /* Parse a Neon type specifier. *STR should point at the leading '.'
1424 character. Does no verification at this stage that the type fits the opcode
1431 Can all be legally parsed by this function.
1433 Fills in neon_type struct pointer with parsed information, and updates STR
1434 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1435 type, FAIL if not. */
1438 parse_neon_type (struct neon_type
*type
, char **str
)
1445 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1447 enum neon_el_type thistype
= NT_untyped
;
1448 unsigned thissize
= -1u;
1455 /* Just a size without an explicit type. */
1459 switch (TOLOWER (*ptr
))
1461 case 'i': thistype
= NT_integer
; break;
1462 case 'f': thistype
= NT_float
; break;
1463 case 'p': thistype
= NT_poly
; break;
1464 case 's': thistype
= NT_signed
; break;
1465 case 'u': thistype
= NT_unsigned
; break;
1467 thistype
= NT_float
;
1472 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1478 /* .f is an abbreviation for .f32. */
1479 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1484 thissize
= strtoul (ptr
, &ptr
, 10);
1486 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1489 as_bad (_("bad size %d in type specifier"), thissize
);
1497 type
->el
[type
->elems
].type
= thistype
;
1498 type
->el
[type
->elems
].size
= thissize
;
1503 /* Empty/missing type is not a successful parse. */
1504 if (type
->elems
== 0)
1512 /* Errors may be set multiple times during parsing or bit encoding
1513 (particularly in the Neon bits), but usually the earliest error which is set
1514 will be the most meaningful. Avoid overwriting it with later (cascading)
1515 errors by calling this function. */
1518 first_error (const char *err
)
1524 /* Parse a single type, e.g. ".s32", leading period included. */
1526 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1529 struct neon_type optype
;
1533 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1535 if (optype
.elems
== 1)
1536 *vectype
= optype
.el
[0];
1539 first_error (_("only one type should be specified for operand"));
1545 first_error (_("vector type expected"));
1557 /* Special meanings for indices (which have a range of 0-7), which will fit into
1560 #define NEON_ALL_LANES 15
1561 #define NEON_INTERLEAVE_LANES 14
1563 /* Record a use of the given feature. */
1565 record_feature_use (const arm_feature_set
*feature
)
1568 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1570 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1573 /* If the given feature available in the selected CPU, mark it as used.
1574 Returns TRUE iff feature is available. */
1576 mark_feature_used (const arm_feature_set
*feature
)
1579 /* Do not support the use of MVE only instructions when in auto-detection or
1581 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1582 && ARM_CPU_IS_ANY (cpu_variant
))
1584 first_error (BAD_MVE_AUTO
);
1587 /* Ensure the option is valid on the current architecture. */
1588 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1591 /* Add the appropriate architecture feature for the barrier option used.
1593 record_feature_use (feature
);
1598 /* Parse either a register or a scalar, with an optional type. Return the
1599 register number, and optionally fill in the actual type of the register
1600 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1601 type/index information in *TYPEINFO. */
1604 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1605 enum arm_reg_type
*rtype
,
1606 struct neon_typed_alias
*typeinfo
)
1609 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1610 struct neon_typed_alias atype
;
1611 struct neon_type_el parsetype
;
1615 atype
.eltype
.type
= NT_invtype
;
1616 atype
.eltype
.size
= -1;
1618 /* Try alternate syntax for some types of register. Note these are mutually
1619 exclusive with the Neon syntax extensions. */
1622 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1630 /* Undo polymorphism when a set of register types may be accepted. */
1631 if ((type
== REG_TYPE_NDQ
1632 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1633 || (type
== REG_TYPE_VFSD
1634 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1635 || (type
== REG_TYPE_NSDQ
1636 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1637 || reg
->type
== REG_TYPE_NQ
))
1638 || (type
== REG_TYPE_NSD
1639 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1640 || (type
== REG_TYPE_MMXWC
1641 && (reg
->type
== REG_TYPE_MMXWCG
)))
1642 type
= (enum arm_reg_type
) reg
->type
;
1644 if (type
== REG_TYPE_MQ
)
1646 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1649 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1652 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1654 first_error (_("expected MVE register [q0..q7]"));
1659 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1660 && (type
== REG_TYPE_NQ
))
1664 if (type
!= reg
->type
)
1670 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1672 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1674 first_error (_("can't redefine type for operand"));
1677 atype
.defined
|= NTA_HASTYPE
;
1678 atype
.eltype
= parsetype
;
1681 if (skip_past_char (&str
, '[') == SUCCESS
)
1683 if (type
!= REG_TYPE_VFD
1684 && !(type
== REG_TYPE_VFS
1685 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1686 && !(type
== REG_TYPE_NQ
1687 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1689 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1690 first_error (_("only D and Q registers may be indexed"));
1692 first_error (_("only D registers may be indexed"));
1696 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1698 first_error (_("can't change index for operand"));
1702 atype
.defined
|= NTA_HASINDEX
;
1704 if (skip_past_char (&str
, ']') == SUCCESS
)
1705 atype
.index
= NEON_ALL_LANES
;
1710 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1712 if (exp
.X_op
!= O_constant
)
1714 first_error (_("constant expression required"));
1718 if (skip_past_char (&str
, ']') == FAIL
)
1721 atype
.index
= exp
.X_add_number
;
1736 /* Like arm_reg_parse, but also allow the following extra features:
1737 - If RTYPE is non-zero, return the (possibly restricted) type of the
1738 register (e.g. Neon double or quad reg when either has been requested).
1739 - If this is a Neon vector type with additional type information, fill
1740 in the struct pointed to by VECTYPE (if non-NULL).
1741 This function will fault on encountering a scalar. */
1744 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1745 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1747 struct neon_typed_alias atype
;
1749 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1754 /* Do not allow regname(... to parse as a register. */
1758 /* Do not allow a scalar (reg+index) to parse as a register. */
1759 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1761 first_error (_("register operand expected, but got scalar"));
1766 *vectype
= atype
.eltype
;
1773 #define NEON_SCALAR_REG(X) ((X) >> 4)
1774 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1776 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1777 have enough information to be able to do a good job bounds-checking. So, we
1778 just do easy checks here, and do further checks later. */
1781 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1782 arm_reg_type reg_type
)
1786 struct neon_typed_alias atype
;
1789 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1807 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1810 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1812 first_error (_("scalar must have an index"));
1815 else if (atype
.index
>= reg_size
/ elsize
)
1817 first_error (_("scalar index out of range"));
1822 *type
= atype
.eltype
;
1826 return reg
* 16 + atype
.index
;
1829 /* Types of registers in a list. */
1842 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1845 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1851 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1853 /* We come back here if we get ranges concatenated by '+' or '|'. */
1856 skip_whitespace (str
);
1869 const char apsr_str
[] = "apsr";
1870 int apsr_str_len
= strlen (apsr_str
);
1872 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1873 if (etype
== REGLIST_CLRM
)
1875 if (reg
== REG_SP
|| reg
== REG_PC
)
1877 else if (reg
== FAIL
1878 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1879 && !ISALPHA (*(str
+ apsr_str_len
)))
1882 str
+= apsr_str_len
;
1887 first_error (_("r0-r12, lr or APSR expected"));
1891 else /* etype == REGLIST_RN. */
1895 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1906 first_error (_("bad range in register list"));
1910 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1912 if (range
& (1 << i
))
1914 (_("Warning: duplicated register (r%d) in register list"),
1922 if (range
& (1 << reg
))
1923 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1925 else if (reg
<= cur_reg
)
1926 as_tsktsk (_("Warning: register range not in ascending order"));
1931 while (skip_past_comma (&str
) != FAIL
1932 || (in_range
= 1, *str
++ == '-'));
1935 if (skip_past_char (&str
, '}') == FAIL
)
1937 first_error (_("missing `}'"));
1941 else if (etype
== REGLIST_RN
)
1945 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1948 if (exp
.X_op
== O_constant
)
1950 if (exp
.X_add_number
1951 != (exp
.X_add_number
& 0x0000ffff))
1953 inst
.error
= _("invalid register mask");
1957 if ((range
& exp
.X_add_number
) != 0)
1959 int regno
= range
& exp
.X_add_number
;
1962 regno
= (1 << regno
) - 1;
1964 (_("Warning: duplicated register (r%d) in register list"),
1968 range
|= exp
.X_add_number
;
1972 if (inst
.relocs
[0].type
!= 0)
1974 inst
.error
= _("expression too complex");
1978 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1979 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1980 inst
.relocs
[0].pc_rel
= 0;
1984 if (*str
== '|' || *str
== '+')
1990 while (another_range
);
1996 /* Parse a VFP register list. If the string is invalid return FAIL.
1997 Otherwise return the number of registers, and set PBASE to the first
1998 register. Parses registers of type ETYPE.
1999 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2000 - Q registers can be used to specify pairs of D registers
2001 - { } can be omitted from around a singleton register list
2002 FIXME: This is not implemented, as it would require backtracking in
2005 This could be done (the meaning isn't really ambiguous), but doesn't
2006 fit in well with the current parsing framework.
2007 - 32 D registers may be used (also true for VFPv3).
2008 FIXME: Types are ignored in these register lists, which is probably a
2012 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2013 bfd_boolean
*partial_match
)
2018 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2022 unsigned long mask
= 0;
2024 bfd_boolean vpr_seen
= FALSE
;
2025 bfd_boolean expect_vpr
=
2026 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2028 if (skip_past_char (&str
, '{') == FAIL
)
2030 inst
.error
= _("expecting {");
2037 case REGLIST_VFP_S_VPR
:
2038 regtype
= REG_TYPE_VFS
;
2043 case REGLIST_VFP_D_VPR
:
2044 regtype
= REG_TYPE_VFD
;
2047 case REGLIST_NEON_D
:
2048 regtype
= REG_TYPE_NDQ
;
2055 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2057 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2058 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2062 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2065 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2072 base_reg
= max_regs
;
2073 *partial_match
= FALSE
;
2077 int setmask
= 1, addregs
= 1;
2078 const char vpr_str
[] = "vpr";
2079 int vpr_str_len
= strlen (vpr_str
);
2081 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2085 if (new_base
== FAIL
2086 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2087 && !ISALPHA (*(str
+ vpr_str_len
))
2093 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2097 first_error (_("VPR expected last"));
2100 else if (new_base
== FAIL
)
2102 if (regtype
== REG_TYPE_VFS
)
2103 first_error (_("VFP single precision register or VPR "
2105 else /* regtype == REG_TYPE_VFD. */
2106 first_error (_("VFP/Neon double precision register or VPR "
2111 else if (new_base
== FAIL
)
2113 first_error (_(reg_expected_msgs
[regtype
]));
2117 *partial_match
= TRUE
;
2121 if (new_base
>= max_regs
)
2123 first_error (_("register out of range in list"));
2127 /* Note: a value of 2 * n is returned for the register Q<n>. */
2128 if (regtype
== REG_TYPE_NQ
)
2134 if (new_base
< base_reg
)
2135 base_reg
= new_base
;
2137 if (mask
& (setmask
<< new_base
))
2139 first_error (_("invalid register list"));
2143 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2145 as_tsktsk (_("register list not in ascending order"));
2149 mask
|= setmask
<< new_base
;
2152 if (*str
== '-') /* We have the start of a range expression */
2158 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2161 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2165 if (high_range
>= max_regs
)
2167 first_error (_("register out of range in list"));
2171 if (regtype
== REG_TYPE_NQ
)
2172 high_range
= high_range
+ 1;
2174 if (high_range
<= new_base
)
2176 inst
.error
= _("register range not in ascending order");
2180 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2182 if (mask
& (setmask
<< new_base
))
2184 inst
.error
= _("invalid register list");
2188 mask
|= setmask
<< new_base
;
2193 while (skip_past_comma (&str
) != FAIL
);
2197 /* Sanity check -- should have raised a parse error above. */
2198 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2203 if (expect_vpr
&& !vpr_seen
)
2205 first_error (_("VPR expected last"));
2209 /* Final test -- the registers must be consecutive. */
2211 for (i
= 0; i
< count
; i
++)
2213 if ((mask
& (1u << i
)) == 0)
2215 inst
.error
= _("non-contiguous register range");
2225 /* True if two alias types are the same. */
2228 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2236 if (a
->defined
!= b
->defined
)
2239 if ((a
->defined
& NTA_HASTYPE
) != 0
2240 && (a
->eltype
.type
!= b
->eltype
.type
2241 || a
->eltype
.size
!= b
->eltype
.size
))
2244 if ((a
->defined
& NTA_HASINDEX
) != 0
2245 && (a
->index
!= b
->index
))
2251 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2252 The base register is put in *PBASE.
2253 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2255 The register stride (minus one) is put in bit 4 of the return value.
2256 Bits [6:5] encode the list length (minus one).
2257 The type of the list elements is put in *ELTYPE, if non-NULL. */
2259 #define NEON_LANE(X) ((X) & 0xf)
2260 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2261 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2264 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2266 struct neon_type_el
*eltype
)
2273 int leading_brace
= 0;
2274 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2275 const char *const incr_error
= mve
? _("register stride must be 1") :
2276 _("register stride must be 1 or 2");
2277 const char *const type_error
= _("mismatched element/structure types in list");
2278 struct neon_typed_alias firsttype
;
2279 firsttype
.defined
= 0;
2280 firsttype
.eltype
.type
= NT_invtype
;
2281 firsttype
.eltype
.size
= -1;
2282 firsttype
.index
= -1;
2284 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2289 struct neon_typed_alias atype
;
2291 rtype
= REG_TYPE_MQ
;
2292 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2296 first_error (_(reg_expected_msgs
[rtype
]));
2303 if (rtype
== REG_TYPE_NQ
)
2309 else if (reg_incr
== -1)
2311 reg_incr
= getreg
- base_reg
;
2312 if (reg_incr
< 1 || reg_incr
> 2)
2314 first_error (_(incr_error
));
2318 else if (getreg
!= base_reg
+ reg_incr
* count
)
2320 first_error (_(incr_error
));
2324 if (! neon_alias_types_same (&atype
, &firsttype
))
2326 first_error (_(type_error
));
2330 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2334 struct neon_typed_alias htype
;
2335 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2337 lane
= NEON_INTERLEAVE_LANES
;
2338 else if (lane
!= NEON_INTERLEAVE_LANES
)
2340 first_error (_(type_error
));
2345 else if (reg_incr
!= 1)
2347 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2351 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2354 first_error (_(reg_expected_msgs
[rtype
]));
2357 if (! neon_alias_types_same (&htype
, &firsttype
))
2359 first_error (_(type_error
));
2362 count
+= hireg
+ dregs
- getreg
;
2366 /* If we're using Q registers, we can't use [] or [n] syntax. */
2367 if (rtype
== REG_TYPE_NQ
)
2373 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2377 else if (lane
!= atype
.index
)
2379 first_error (_(type_error
));
2383 else if (lane
== -1)
2384 lane
= NEON_INTERLEAVE_LANES
;
2385 else if (lane
!= NEON_INTERLEAVE_LANES
)
2387 first_error (_(type_error
));
2392 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2394 /* No lane set by [x]. We must be interleaving structures. */
2396 lane
= NEON_INTERLEAVE_LANES
;
2399 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2400 || (count
> 1 && reg_incr
== -1))
2402 first_error (_("error parsing element/structure list"));
2406 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2408 first_error (_("expected }"));
2416 *eltype
= firsttype
.eltype
;
2421 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2424 /* Parse an explicit relocation suffix on an expression. This is
2425 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2426 arm_reloc_hsh contains no entries, so this function can only
2427 succeed if there is no () after the word. Returns -1 on error,
2428 BFD_RELOC_UNUSED if there wasn't any suffix. */
2431 parse_reloc (char **str
)
2433 struct reloc_entry
*r
;
2437 return BFD_RELOC_UNUSED
;
2442 while (*q
&& *q
!= ')' && *q
!= ',')
2447 if ((r
= (struct reloc_entry
*)
2448 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2455 /* Directives: register aliases. */
2457 static struct reg_entry
*
2458 insert_reg_alias (char *str
, unsigned number
, int type
)
2460 struct reg_entry
*new_reg
;
2463 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2465 if (new_reg
->builtin
)
2466 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2468 /* Only warn about a redefinition if it's not defined as the
2470 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2471 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2476 name
= xstrdup (str
);
2477 new_reg
= XNEW (struct reg_entry
);
2479 new_reg
->name
= name
;
2480 new_reg
->number
= number
;
2481 new_reg
->type
= type
;
2482 new_reg
->builtin
= FALSE
;
2483 new_reg
->neon
= NULL
;
2485 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2492 insert_neon_reg_alias (char *str
, int number
, int type
,
2493 struct neon_typed_alias
*atype
)
2495 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2499 first_error (_("attempt to redefine typed alias"));
2505 reg
->neon
= XNEW (struct neon_typed_alias
);
2506 *reg
->neon
= *atype
;
2510 /* Look for the .req directive. This is of the form:
2512 new_register_name .req existing_register_name
2514 If we find one, or if it looks sufficiently like one that we want to
2515 handle any error here, return TRUE. Otherwise return FALSE. */
2518 create_register_alias (char * newname
, char *p
)
2520 struct reg_entry
*old
;
2521 char *oldname
, *nbuf
;
2524 /* The input scrubber ensures that whitespace after the mnemonic is
2525 collapsed to single spaces. */
2527 if (strncmp (oldname
, " .req ", 6) != 0)
2531 if (*oldname
== '\0')
2534 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2537 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2541 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2542 the desired alias name, and p points to its end. If not, then
2543 the desired alias name is in the global original_case_string. */
2544 #ifdef TC_CASE_SENSITIVE
2547 newname
= original_case_string
;
2548 nlen
= strlen (newname
);
2551 nbuf
= xmemdup0 (newname
, nlen
);
2553 /* Create aliases under the new name as stated; an all-lowercase
2554 version of the new name; and an all-uppercase version of the new
2556 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2558 for (p
= nbuf
; *p
; p
++)
2561 if (strncmp (nbuf
, newname
, nlen
))
2563 /* If this attempt to create an additional alias fails, do not bother
2564 trying to create the all-lower case alias. We will fail and issue
2565 a second, duplicate error message. This situation arises when the
2566 programmer does something like:
2569 The second .req creates the "Foo" alias but then fails to create
2570 the artificial FOO alias because it has already been created by the
2572 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2579 for (p
= nbuf
; *p
; p
++)
2582 if (strncmp (nbuf
, newname
, nlen
))
2583 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2590 /* Create a Neon typed/indexed register alias using directives, e.g.:
2595 These typed registers can be used instead of the types specified after the
2596 Neon mnemonic, so long as all operands given have types. Types can also be
2597 specified directly, e.g.:
2598 vadd d0.s32, d1.s32, d2.s32 */
2601 create_neon_reg_alias (char *newname
, char *p
)
2603 enum arm_reg_type basetype
;
2604 struct reg_entry
*basereg
;
2605 struct reg_entry mybasereg
;
2606 struct neon_type ntype
;
2607 struct neon_typed_alias typeinfo
;
2608 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2611 typeinfo
.defined
= 0;
2612 typeinfo
.eltype
.type
= NT_invtype
;
2613 typeinfo
.eltype
.size
= -1;
2614 typeinfo
.index
= -1;
2618 if (strncmp (p
, " .dn ", 5) == 0)
2619 basetype
= REG_TYPE_VFD
;
2620 else if (strncmp (p
, " .qn ", 5) == 0)
2621 basetype
= REG_TYPE_NQ
;
2630 basereg
= arm_reg_parse_multi (&p
);
2632 if (basereg
&& basereg
->type
!= basetype
)
2634 as_bad (_("bad type for register"));
2638 if (basereg
== NULL
)
2641 /* Try parsing as an integer. */
2642 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2643 if (exp
.X_op
!= O_constant
)
2645 as_bad (_("expression must be constant"));
2648 basereg
= &mybasereg
;
2649 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2655 typeinfo
= *basereg
->neon
;
2657 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2659 /* We got a type. */
2660 if (typeinfo
.defined
& NTA_HASTYPE
)
2662 as_bad (_("can't redefine the type of a register alias"));
2666 typeinfo
.defined
|= NTA_HASTYPE
;
2667 if (ntype
.elems
!= 1)
2669 as_bad (_("you must specify a single type only"));
2672 typeinfo
.eltype
= ntype
.el
[0];
2675 if (skip_past_char (&p
, '[') == SUCCESS
)
2678 /* We got a scalar index. */
2680 if (typeinfo
.defined
& NTA_HASINDEX
)
2682 as_bad (_("can't redefine the index of a scalar alias"));
2686 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2688 if (exp
.X_op
!= O_constant
)
2690 as_bad (_("scalar index must be constant"));
2694 typeinfo
.defined
|= NTA_HASINDEX
;
2695 typeinfo
.index
= exp
.X_add_number
;
2697 if (skip_past_char (&p
, ']') == FAIL
)
2699 as_bad (_("expecting ]"));
2704 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2705 the desired alias name, and p points to its end. If not, then
2706 the desired alias name is in the global original_case_string. */
2707 #ifdef TC_CASE_SENSITIVE
2708 namelen
= nameend
- newname
;
2710 newname
= original_case_string
;
2711 namelen
= strlen (newname
);
2714 namebuf
= xmemdup0 (newname
, namelen
);
2716 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2717 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2719 /* Insert name in all uppercase. */
2720 for (p
= namebuf
; *p
; p
++)
2723 if (strncmp (namebuf
, newname
, namelen
))
2724 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2725 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2727 /* Insert name in all lowercase. */
2728 for (p
= namebuf
; *p
; p
++)
2731 if (strncmp (namebuf
, newname
, namelen
))
2732 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2733 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2739 /* Should never be called, as .req goes between the alias and the
2740 register name, not at the beginning of the line. */
2743 s_req (int a ATTRIBUTE_UNUSED
)
2745 as_bad (_("invalid syntax for .req directive"));
2749 s_dn (int a ATTRIBUTE_UNUSED
)
2751 as_bad (_("invalid syntax for .dn directive"));
2755 s_qn (int a ATTRIBUTE_UNUSED
)
2757 as_bad (_("invalid syntax for .qn directive"));
2760 /* The .unreq directive deletes an alias which was previously defined
2761 by .req. For example:
2767 s_unreq (int a ATTRIBUTE_UNUSED
)
2772 name
= input_line_pointer
;
2774 while (*input_line_pointer
!= 0
2775 && *input_line_pointer
!= ' '
2776 && *input_line_pointer
!= '\n')
2777 ++input_line_pointer
;
2779 saved_char
= *input_line_pointer
;
2780 *input_line_pointer
= 0;
2783 as_bad (_("invalid syntax for .unreq directive"));
2786 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2790 as_bad (_("unknown register alias '%s'"), name
);
2791 else if (reg
->builtin
)
2792 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2799 hash_delete (arm_reg_hsh
, name
, FALSE
);
2800 free ((char *) reg
->name
);
2805 /* Also locate the all upper case and all lower case versions.
2806 Do not complain if we cannot find one or the other as it
2807 was probably deleted above. */
2809 nbuf
= strdup (name
);
2810 for (p
= nbuf
; *p
; p
++)
2812 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2815 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2816 free ((char *) reg
->name
);
2822 for (p
= nbuf
; *p
; p
++)
2824 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2827 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2828 free ((char *) reg
->name
);
2838 *input_line_pointer
= saved_char
;
2839 demand_empty_rest_of_line ();
2842 /* Directives: Instruction set selection. */
2845 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2846 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2847 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2848 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2850 /* Create a new mapping symbol for the transition to STATE. */
2853 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2856 const char * symname
;
2863 type
= BSF_NO_FLAGS
;
2867 type
= BSF_NO_FLAGS
;
2871 type
= BSF_NO_FLAGS
;
2877 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2878 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2883 THUMB_SET_FUNC (symbolP
, 0);
2884 ARM_SET_THUMB (symbolP
, 0);
2885 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2889 THUMB_SET_FUNC (symbolP
, 1);
2890 ARM_SET_THUMB (symbolP
, 1);
2891 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2899 /* Save the mapping symbols for future reference. Also check that
2900 we do not place two mapping symbols at the same offset within a
2901 frag. We'll handle overlap between frags in
2902 check_mapping_symbols.
2904 If .fill or other data filling directive generates zero sized data,
2905 the mapping symbol for the following code will have the same value
2906 as the one generated for the data filling directive. In this case,
2907 we replace the old symbol with the new one at the same address. */
2910 if (frag
->tc_frag_data
.first_map
!= NULL
)
2912 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2913 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2915 frag
->tc_frag_data
.first_map
= symbolP
;
2917 if (frag
->tc_frag_data
.last_map
!= NULL
)
2919 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2920 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2921 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2923 frag
->tc_frag_data
.last_map
= symbolP
;
2926 /* We must sometimes convert a region marked as code to data during
2927 code alignment, if an odd number of bytes have to be padded. The
2928 code mapping symbol is pushed to an aligned address. */
2931 insert_data_mapping_symbol (enum mstate state
,
2932 valueT value
, fragS
*frag
, offsetT bytes
)
2934 /* If there was already a mapping symbol, remove it. */
2935 if (frag
->tc_frag_data
.last_map
!= NULL
2936 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2938 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2942 know (frag
->tc_frag_data
.first_map
== symp
);
2943 frag
->tc_frag_data
.first_map
= NULL
;
2945 frag
->tc_frag_data
.last_map
= NULL
;
2946 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2949 make_mapping_symbol (MAP_DATA
, value
, frag
);
2950 make_mapping_symbol (state
, value
+ bytes
, frag
);
2953 static void mapping_state_2 (enum mstate state
, int max_chars
);
2955 /* Set the mapping state to STATE. Only call this when about to
2956 emit some STATE bytes to the file. */
2958 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2960 mapping_state (enum mstate state
)
2962 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2964 if (mapstate
== state
)
2965 /* The mapping symbol has already been emitted.
2966 There is nothing else to do. */
2969 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2971 All ARM instructions require 4-byte alignment.
2972 (Almost) all Thumb instructions require 2-byte alignment.
2974 When emitting instructions into any section, mark the section
2977 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2978 but themselves require 2-byte alignment; this applies to some
2979 PC- relative forms. However, these cases will involve implicit
2980 literal pool generation or an explicit .align >=2, both of
2981 which will cause the section to me marked with sufficient
2982 alignment. Thus, we don't handle those cases here. */
2983 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2986 /* This case will be evaluated later. */
2989 mapping_state_2 (state
, 0);
2992 /* Same as mapping_state, but MAX_CHARS bytes have already been
2993 allocated. Put the mapping symbol that far back. */
2996 mapping_state_2 (enum mstate state
, int max_chars
)
2998 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3000 if (!SEG_NORMAL (now_seg
))
3003 if (mapstate
== state
)
3004 /* The mapping symbol has already been emitted.
3005 There is nothing else to do. */
3008 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3009 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3011 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3012 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3015 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3018 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3019 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3023 #define mapping_state(x) ((void)0)
3024 #define mapping_state_2(x, y) ((void)0)
3027 /* Find the real, Thumb encoded start of a Thumb function. */
3031 find_real_start (symbolS
* symbolP
)
3034 const char * name
= S_GET_NAME (symbolP
);
3035 symbolS
* new_target
;
3037 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3038 #define STUB_NAME ".real_start_of"
3043 /* The compiler may generate BL instructions to local labels because
3044 it needs to perform a branch to a far away location. These labels
3045 do not have a corresponding ".real_start_of" label. We check
3046 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3047 the ".real_start_of" convention for nonlocal branches. */
3048 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3051 real_start
= concat (STUB_NAME
, name
, NULL
);
3052 new_target
= symbol_find (real_start
);
3055 if (new_target
== NULL
)
3057 as_warn (_("Failed to find real start of function: %s\n"), name
);
3058 new_target
= symbolP
;
3066 opcode_select (int width
)
3073 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3074 as_bad (_("selected processor does not support THUMB opcodes"));
3077 /* No need to force the alignment, since we will have been
3078 coming from ARM mode, which is word-aligned. */
3079 record_alignment (now_seg
, 1);
3086 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3087 as_bad (_("selected processor does not support ARM opcodes"));
3092 frag_align (2, 0, 0);
3094 record_alignment (now_seg
, 1);
3099 as_bad (_("invalid instruction size selected (%d)"), width
);
3104 s_arm (int ignore ATTRIBUTE_UNUSED
)
3107 demand_empty_rest_of_line ();
3111 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3114 demand_empty_rest_of_line ();
3118 s_code (int unused ATTRIBUTE_UNUSED
)
3122 temp
= get_absolute_expression ();
3127 opcode_select (temp
);
3131 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3136 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3138 /* If we are not already in thumb mode go into it, EVEN if
3139 the target processor does not support thumb instructions.
3140 This is used by gcc/config/arm/lib1funcs.asm for example
3141 to compile interworking support functions even if the
3142 target processor should not support interworking. */
3146 record_alignment (now_seg
, 1);
3149 demand_empty_rest_of_line ();
3153 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3157 /* The following label is the name/address of the start of a Thumb function.
3158 We need to know this for the interworking support. */
3159 label_is_thumb_function_name
= TRUE
;
3162 /* Perform a .set directive, but also mark the alias as
3163 being a thumb function. */
3166 s_thumb_set (int equiv
)
3168 /* XXX the following is a duplicate of the code for s_set() in read.c
3169 We cannot just call that code as we need to get at the symbol that
3176 /* Especial apologies for the random logic:
3177 This just grew, and could be parsed much more simply!
3179 delim
= get_symbol_name (& name
);
3180 end_name
= input_line_pointer
;
3181 (void) restore_line_pointer (delim
);
3183 if (*input_line_pointer
!= ',')
3186 as_bad (_("expected comma after name \"%s\""), name
);
3188 ignore_rest_of_line ();
3192 input_line_pointer
++;
3195 if (name
[0] == '.' && name
[1] == '\0')
3197 /* XXX - this should not happen to .thumb_set. */
3201 if ((symbolP
= symbol_find (name
)) == NULL
3202 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3205 /* When doing symbol listings, play games with dummy fragments living
3206 outside the normal fragment chain to record the file and line info
3208 if (listing
& LISTING_SYMBOLS
)
3210 extern struct list_info_struct
* listing_tail
;
3211 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3213 memset (dummy_frag
, 0, sizeof (fragS
));
3214 dummy_frag
->fr_type
= rs_fill
;
3215 dummy_frag
->line
= listing_tail
;
3216 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3217 dummy_frag
->fr_symbol
= symbolP
;
3221 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3224 /* "set" symbols are local unless otherwise specified. */
3225 SF_SET_LOCAL (symbolP
);
3226 #endif /* OBJ_COFF */
3227 } /* Make a new symbol. */
3229 symbol_table_insert (symbolP
);
3234 && S_IS_DEFINED (symbolP
)
3235 && S_GET_SEGMENT (symbolP
) != reg_section
)
3236 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3238 pseudo_set (symbolP
);
3240 demand_empty_rest_of_line ();
3242 /* XXX Now we come to the Thumb specific bit of code. */
3244 THUMB_SET_FUNC (symbolP
, 1);
3245 ARM_SET_THUMB (symbolP
, 1);
3246 #if defined OBJ_ELF || defined OBJ_COFF
3247 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3251 /* Directives: Mode selection. */
3253 /* .syntax [unified|divided] - choose the new unified syntax
3254 (same for Arm and Thumb encoding, modulo slight differences in what
3255 can be represented) or the old divergent syntax for each mode. */
3257 s_syntax (int unused ATTRIBUTE_UNUSED
)
3261 delim
= get_symbol_name (& name
);
3263 if (!strcasecmp (name
, "unified"))
3264 unified_syntax
= TRUE
;
3265 else if (!strcasecmp (name
, "divided"))
3266 unified_syntax
= FALSE
;
3269 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3272 (void) restore_line_pointer (delim
);
3273 demand_empty_rest_of_line ();
3276 /* Directives: sectioning and alignment. */
3279 s_bss (int ignore ATTRIBUTE_UNUSED
)
3281 /* We don't support putting frags in the BSS segment, we fake it by
3282 marking in_bss, then looking at s_skip for clues. */
3283 subseg_set (bss_section
, 0);
3284 demand_empty_rest_of_line ();
3286 #ifdef md_elf_section_change_hook
3287 md_elf_section_change_hook ();
3292 s_even (int ignore ATTRIBUTE_UNUSED
)
3294 /* Never make frag if expect extra pass. */
3296 frag_align (1, 0, 0);
3298 record_alignment (now_seg
, 1);
3300 demand_empty_rest_of_line ();
3303 /* Directives: CodeComposer Studio. */
3305 /* .ref (for CodeComposer Studio syntax only). */
3307 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3309 if (codecomposer_syntax
)
3310 ignore_rest_of_line ();
3312 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3315 /* If name is not NULL, then it is used for marking the beginning of a
3316 function, whereas if it is NULL then it means the function end. */
3318 asmfunc_debug (const char * name
)
3320 static const char * last_name
= NULL
;
3324 gas_assert (last_name
== NULL
);
3327 if (debug_type
== DEBUG_STABS
)
3328 stabs_generate_asm_func (name
, name
);
3332 gas_assert (last_name
!= NULL
);
3334 if (debug_type
== DEBUG_STABS
)
3335 stabs_generate_asm_endfunc (last_name
, last_name
);
3342 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3344 if (codecomposer_syntax
)
3346 switch (asmfunc_state
)
3348 case OUTSIDE_ASMFUNC
:
3349 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3352 case WAITING_ASMFUNC_NAME
:
3353 as_bad (_(".asmfunc repeated."));
3356 case WAITING_ENDASMFUNC
:
3357 as_bad (_(".asmfunc without function."));
3360 demand_empty_rest_of_line ();
3363 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3367 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3369 if (codecomposer_syntax
)
3371 switch (asmfunc_state
)
3373 case OUTSIDE_ASMFUNC
:
3374 as_bad (_(".endasmfunc without a .asmfunc."));
3377 case WAITING_ASMFUNC_NAME
:
3378 as_bad (_(".endasmfunc without function."));
3381 case WAITING_ENDASMFUNC
:
3382 asmfunc_state
= OUTSIDE_ASMFUNC
;
3383 asmfunc_debug (NULL
);
3386 demand_empty_rest_of_line ();
3389 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3393 s_ccs_def (int name
)
3395 if (codecomposer_syntax
)
3398 as_bad (_(".def pseudo-op only available with -mccs flag."));
3401 /* Directives: Literal pools. */
3403 static literal_pool
*
3404 find_literal_pool (void)
3406 literal_pool
* pool
;
3408 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3410 if (pool
->section
== now_seg
3411 && pool
->sub_section
== now_subseg
)
3418 static literal_pool
*
3419 find_or_make_literal_pool (void)
3421 /* Next literal pool ID number. */
3422 static unsigned int latest_pool_num
= 1;
3423 literal_pool
* pool
;
3425 pool
= find_literal_pool ();
3429 /* Create a new pool. */
3430 pool
= XNEW (literal_pool
);
3434 pool
->next_free_entry
= 0;
3435 pool
->section
= now_seg
;
3436 pool
->sub_section
= now_subseg
;
3437 pool
->next
= list_of_pools
;
3438 pool
->symbol
= NULL
;
3439 pool
->alignment
= 2;
3441 /* Add it to the list. */
3442 list_of_pools
= pool
;
3445 /* New pools, and emptied pools, will have a NULL symbol. */
3446 if (pool
->symbol
== NULL
)
3448 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3449 (valueT
) 0, &zero_address_frag
);
3450 pool
->id
= latest_pool_num
++;
3457 /* Add the literal in the global 'inst'
3458 structure to the relevant literal pool. */
3461 add_to_lit_pool (unsigned int nbytes
)
3463 #define PADDING_SLOT 0x1
3464 #define LIT_ENTRY_SIZE_MASK 0xFF
3465 literal_pool
* pool
;
3466 unsigned int entry
, pool_size
= 0;
3467 bfd_boolean padding_slot_p
= FALSE
;
3473 imm1
= inst
.operands
[1].imm
;
3474 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3475 : inst
.relocs
[0].exp
.X_unsigned
? 0
3476 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3477 if (target_big_endian
)
3480 imm2
= inst
.operands
[1].imm
;
3484 pool
= find_or_make_literal_pool ();
3486 /* Check if this literal value is already in the pool. */
3487 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3491 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3492 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3493 && (pool
->literals
[entry
].X_add_number
3494 == inst
.relocs
[0].exp
.X_add_number
)
3495 && (pool
->literals
[entry
].X_md
== nbytes
)
3496 && (pool
->literals
[entry
].X_unsigned
3497 == inst
.relocs
[0].exp
.X_unsigned
))
3500 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3501 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3502 && (pool
->literals
[entry
].X_add_number
3503 == inst
.relocs
[0].exp
.X_add_number
)
3504 && (pool
->literals
[entry
].X_add_symbol
3505 == inst
.relocs
[0].exp
.X_add_symbol
)
3506 && (pool
->literals
[entry
].X_op_symbol
3507 == inst
.relocs
[0].exp
.X_op_symbol
)
3508 && (pool
->literals
[entry
].X_md
== nbytes
))
3511 else if ((nbytes
== 8)
3512 && !(pool_size
& 0x7)
3513 && ((entry
+ 1) != pool
->next_free_entry
)
3514 && (pool
->literals
[entry
].X_op
== O_constant
)
3515 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3516 && (pool
->literals
[entry
].X_unsigned
3517 == inst
.relocs
[0].exp
.X_unsigned
)
3518 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3519 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3520 && (pool
->literals
[entry
+ 1].X_unsigned
3521 == inst
.relocs
[0].exp
.X_unsigned
))
3524 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3525 if (padding_slot_p
&& (nbytes
== 4))
3531 /* Do we need to create a new entry? */
3532 if (entry
== pool
->next_free_entry
)
3534 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3536 inst
.error
= _("literal pool overflow");
3542 /* For 8-byte entries, we align to an 8-byte boundary,
3543 and split it into two 4-byte entries, because on 32-bit
3544 host, 8-byte constants are treated as big num, thus
3545 saved in "generic_bignum" which will be overwritten
3546 by later assignments.
3548 We also need to make sure there is enough space for
3551 We also check to make sure the literal operand is a
3553 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3554 || inst
.relocs
[0].exp
.X_op
== O_big
))
3556 inst
.error
= _("invalid type for literal pool");
3559 else if (pool_size
& 0x7)
3561 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3563 inst
.error
= _("literal pool overflow");
3567 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3568 pool
->literals
[entry
].X_op
= O_constant
;
3569 pool
->literals
[entry
].X_add_number
= 0;
3570 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3571 pool
->next_free_entry
+= 1;
3574 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3576 inst
.error
= _("literal pool overflow");
3580 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3581 pool
->literals
[entry
].X_op
= O_constant
;
3582 pool
->literals
[entry
].X_add_number
= imm1
;
3583 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3584 pool
->literals
[entry
++].X_md
= 4;
3585 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3586 pool
->literals
[entry
].X_op
= O_constant
;
3587 pool
->literals
[entry
].X_add_number
= imm2
;
3588 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3589 pool
->literals
[entry
].X_md
= 4;
3590 pool
->alignment
= 3;
3591 pool
->next_free_entry
+= 1;
3595 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3596 pool
->literals
[entry
].X_md
= 4;
3600 /* PR ld/12974: Record the location of the first source line to reference
3601 this entry in the literal pool. If it turns out during linking that the
3602 symbol does not exist we will be able to give an accurate line number for
3603 the (first use of the) missing reference. */
3604 if (debug_type
== DEBUG_DWARF2
)
3605 dwarf2_where (pool
->locs
+ entry
);
3607 pool
->next_free_entry
+= 1;
3609 else if (padding_slot_p
)
3611 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3612 pool
->literals
[entry
].X_md
= nbytes
;
3615 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3616 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3617 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3623 tc_start_label_without_colon (void)
3625 bfd_boolean ret
= TRUE
;
3627 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3629 const char *label
= input_line_pointer
;
3631 while (!is_end_of_line
[(int) label
[-1]])
3636 as_bad (_("Invalid label '%s'"), label
);
3640 asmfunc_debug (label
);
3642 asmfunc_state
= WAITING_ENDASMFUNC
;
3648 /* Can't use symbol_new here, so have to create a symbol and then at
3649 a later date assign it a value. That's what these functions do. */
3652 symbol_locate (symbolS
* symbolP
,
3653 const char * name
, /* It is copied, the caller can modify. */
3654 segT segment
, /* Segment identifier (SEG_<something>). */
3655 valueT valu
, /* Symbol value. */
3656 fragS
* frag
) /* Associated fragment. */
3659 char * preserved_copy_of_name
;
3661 name_length
= strlen (name
) + 1; /* +1 for \0. */
3662 obstack_grow (¬es
, name
, name_length
);
3663 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3665 #ifdef tc_canonicalize_symbol_name
3666 preserved_copy_of_name
=
3667 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3670 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3672 S_SET_SEGMENT (symbolP
, segment
);
3673 S_SET_VALUE (symbolP
, valu
);
3674 symbol_clear_list_pointers (symbolP
);
3676 symbol_set_frag (symbolP
, frag
);
3678 /* Link to end of symbol chain. */
3680 extern int symbol_table_frozen
;
3682 if (symbol_table_frozen
)
3686 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3688 obj_symbol_new_hook (symbolP
);
3690 #ifdef tc_symbol_new_hook
3691 tc_symbol_new_hook (symbolP
);
3695 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3696 #endif /* DEBUG_SYMS */
3700 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3703 literal_pool
* pool
;
3706 pool
= find_literal_pool ();
3708 || pool
->symbol
== NULL
3709 || pool
->next_free_entry
== 0)
3712 /* Align pool as you have word accesses.
3713 Only make a frag if we have to. */
3715 frag_align (pool
->alignment
, 0, 0);
3717 record_alignment (now_seg
, 2);
3720 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3721 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3723 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3725 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3726 (valueT
) frag_now_fix (), frag_now
);
3727 symbol_table_insert (pool
->symbol
);
3729 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3731 #if defined OBJ_COFF || defined OBJ_ELF
3732 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3735 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3738 if (debug_type
== DEBUG_DWARF2
)
3739 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3741 /* First output the expression in the instruction to the pool. */
3742 emit_expr (&(pool
->literals
[entry
]),
3743 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3746 /* Mark the pool as empty. */
3747 pool
->next_free_entry
= 0;
3748 pool
->symbol
= NULL
;
3752 /* Forward declarations for functions below, in the MD interface
3754 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3755 static valueT
create_unwind_entry (int);
3756 static void start_unwind_section (const segT
, int);
3757 static void add_unwind_opcode (valueT
, int);
3758 static void flush_pending_unwind (void);
3760 /* Directives: Data. */
3763 s_arm_elf_cons (int nbytes
)
3767 #ifdef md_flush_pending_output
3768 md_flush_pending_output ();
3771 if (is_it_end_of_statement ())
3773 demand_empty_rest_of_line ();
3777 #ifdef md_cons_align
3778 md_cons_align (nbytes
);
3781 mapping_state (MAP_DATA
);
3785 char *base
= input_line_pointer
;
3789 if (exp
.X_op
!= O_symbol
)
3790 emit_expr (&exp
, (unsigned int) nbytes
);
3793 char *before_reloc
= input_line_pointer
;
3794 reloc
= parse_reloc (&input_line_pointer
);
3797 as_bad (_("unrecognized relocation suffix"));
3798 ignore_rest_of_line ();
3801 else if (reloc
== BFD_RELOC_UNUSED
)
3802 emit_expr (&exp
, (unsigned int) nbytes
);
3805 reloc_howto_type
*howto
= (reloc_howto_type
*)
3806 bfd_reloc_type_lookup (stdoutput
,
3807 (bfd_reloc_code_real_type
) reloc
);
3808 int size
= bfd_get_reloc_size (howto
);
3810 if (reloc
== BFD_RELOC_ARM_PLT32
)
3812 as_bad (_("(plt) is only valid on branch targets"));
3813 reloc
= BFD_RELOC_UNUSED
;
3818 as_bad (ngettext ("%s relocations do not fit in %d byte",
3819 "%s relocations do not fit in %d bytes",
3821 howto
->name
, nbytes
);
3824 /* We've parsed an expression stopping at O_symbol.
3825 But there may be more expression left now that we
3826 have parsed the relocation marker. Parse it again.
3827 XXX Surely there is a cleaner way to do this. */
3828 char *p
= input_line_pointer
;
3830 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3832 memcpy (save_buf
, base
, input_line_pointer
- base
);
3833 memmove (base
+ (input_line_pointer
- before_reloc
),
3834 base
, before_reloc
- base
);
3836 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3838 memcpy (base
, save_buf
, p
- base
);
3840 offset
= nbytes
- size
;
3841 p
= frag_more (nbytes
);
3842 memset (p
, 0, nbytes
);
3843 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3844 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3850 while (*input_line_pointer
++ == ',');
3852 /* Put terminator back into stream. */
3853 input_line_pointer
--;
3854 demand_empty_rest_of_line ();
3857 /* Emit an expression containing a 32-bit thumb instruction.
3858 Implementation based on put_thumb32_insn. */
3861 emit_thumb32_expr (expressionS
* exp
)
3863 expressionS exp_high
= *exp
;
3865 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3866 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3867 exp
->X_add_number
&= 0xffff;
3868 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3871 /* Guess the instruction size based on the opcode. */
3874 thumb_insn_size (int opcode
)
3876 if ((unsigned int) opcode
< 0xe800u
)
3878 else if ((unsigned int) opcode
>= 0xe8000000u
)
3885 emit_insn (expressionS
*exp
, int nbytes
)
3889 if (exp
->X_op
== O_constant
)
3894 size
= thumb_insn_size (exp
->X_add_number
);
3898 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3900 as_bad (_(".inst.n operand too big. "\
3901 "Use .inst.w instead"));
3906 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3907 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3909 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3911 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3912 emit_thumb32_expr (exp
);
3914 emit_expr (exp
, (unsigned int) size
);
3916 it_fsm_post_encode ();
3920 as_bad (_("cannot determine Thumb instruction size. " \
3921 "Use .inst.n/.inst.w instead"));
3924 as_bad (_("constant expression required"));
3929 /* Like s_arm_elf_cons but do not use md_cons_align and
3930 set the mapping state to MAP_ARM/MAP_THUMB. */
3933 s_arm_elf_inst (int nbytes
)
3935 if (is_it_end_of_statement ())
3937 demand_empty_rest_of_line ();
3941 /* Calling mapping_state () here will not change ARM/THUMB,
3942 but will ensure not to be in DATA state. */
3945 mapping_state (MAP_THUMB
);
3950 as_bad (_("width suffixes are invalid in ARM mode"));
3951 ignore_rest_of_line ();
3957 mapping_state (MAP_ARM
);
3966 if (! emit_insn (& exp
, nbytes
))
3968 ignore_rest_of_line ();
3972 while (*input_line_pointer
++ == ',');
3974 /* Put terminator back into stream. */
3975 input_line_pointer
--;
3976 demand_empty_rest_of_line ();
3979 /* Parse a .rel31 directive. */
3982 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3989 if (*input_line_pointer
== '1')
3990 highbit
= 0x80000000;
3991 else if (*input_line_pointer
!= '0')
3992 as_bad (_("expected 0 or 1"));
3994 input_line_pointer
++;
3995 if (*input_line_pointer
!= ',')
3996 as_bad (_("missing comma"));
3997 input_line_pointer
++;
3999 #ifdef md_flush_pending_output
4000 md_flush_pending_output ();
4003 #ifdef md_cons_align
4007 mapping_state (MAP_DATA
);
4012 md_number_to_chars (p
, highbit
, 4);
4013 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4014 BFD_RELOC_ARM_PREL31
);
4016 demand_empty_rest_of_line ();
4019 /* Directives: AEABI stack-unwind tables. */
4021 /* Parse an unwind_fnstart directive. Simply records the current location. */
4024 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4026 demand_empty_rest_of_line ();
4027 if (unwind
.proc_start
)
4029 as_bad (_("duplicate .fnstart directive"));
4033 /* Mark the start of the function. */
4034 unwind
.proc_start
= expr_build_dot ();
4036 /* Reset the rest of the unwind info. */
4037 unwind
.opcode_count
= 0;
4038 unwind
.table_entry
= NULL
;
4039 unwind
.personality_routine
= NULL
;
4040 unwind
.personality_index
= -1;
4041 unwind
.frame_size
= 0;
4042 unwind
.fp_offset
= 0;
4043 unwind
.fp_reg
= REG_SP
;
4045 unwind
.sp_restored
= 0;
4049 /* Parse a handlerdata directive. Creates the exception handling table entry
4050 for the function. */
4053 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4055 demand_empty_rest_of_line ();
4056 if (!unwind
.proc_start
)
4057 as_bad (MISSING_FNSTART
);
4059 if (unwind
.table_entry
)
4060 as_bad (_("duplicate .handlerdata directive"));
4062 create_unwind_entry (1);
4065 /* Parse an unwind_fnend directive. Generates the index table entry. */
4068 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4073 unsigned int marked_pr_dependency
;
4075 demand_empty_rest_of_line ();
4077 if (!unwind
.proc_start
)
4079 as_bad (_(".fnend directive without .fnstart"));
4083 /* Add eh table entry. */
4084 if (unwind
.table_entry
== NULL
)
4085 val
= create_unwind_entry (0);
4089 /* Add index table entry. This is two words. */
4090 start_unwind_section (unwind
.saved_seg
, 1);
4091 frag_align (2, 0, 0);
4092 record_alignment (now_seg
, 2);
4094 ptr
= frag_more (8);
4096 where
= frag_now_fix () - 8;
4098 /* Self relative offset of the function start. */
4099 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4100 BFD_RELOC_ARM_PREL31
);
4102 /* Indicate dependency on EHABI-defined personality routines to the
4103 linker, if it hasn't been done already. */
4104 marked_pr_dependency
4105 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4106 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4107 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4109 static const char *const name
[] =
4111 "__aeabi_unwind_cpp_pr0",
4112 "__aeabi_unwind_cpp_pr1",
4113 "__aeabi_unwind_cpp_pr2"
4115 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4116 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4117 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4118 |= 1 << unwind
.personality_index
;
4122 /* Inline exception table entry. */
4123 md_number_to_chars (ptr
+ 4, val
, 4);
4125 /* Self relative offset of the table entry. */
4126 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4127 BFD_RELOC_ARM_PREL31
);
4129 /* Restore the original section. */
4130 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4132 unwind
.proc_start
= NULL
;
4136 /* Parse an unwind_cantunwind directive. */
4139 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4141 demand_empty_rest_of_line ();
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4146 as_bad (_("personality routine specified for cantunwind frame"));
4148 unwind
.personality_index
= -2;
4152 /* Parse a personalityindex directive. */
4155 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4159 if (!unwind
.proc_start
)
4160 as_bad (MISSING_FNSTART
);
4162 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4163 as_bad (_("duplicate .personalityindex directive"));
4167 if (exp
.X_op
!= O_constant
4168 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4170 as_bad (_("bad personality routine number"));
4171 ignore_rest_of_line ();
4175 unwind
.personality_index
= exp
.X_add_number
;
4177 demand_empty_rest_of_line ();
4181 /* Parse a personality directive. */
4184 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4188 if (!unwind
.proc_start
)
4189 as_bad (MISSING_FNSTART
);
4191 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4192 as_bad (_("duplicate .personality directive"));
4194 c
= get_symbol_name (& name
);
4195 p
= input_line_pointer
;
4197 ++ input_line_pointer
;
4198 unwind
.personality_routine
= symbol_find_or_make (name
);
4200 demand_empty_rest_of_line ();
4204 /* Parse a directive saving core registers. */
4207 s_arm_unwind_save_core (void)
4213 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4216 as_bad (_("expected register list"));
4217 ignore_rest_of_line ();
4221 demand_empty_rest_of_line ();
4223 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4224 into .unwind_save {..., sp...}. We aren't bothered about the value of
4225 ip because it is clobbered by calls. */
4226 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4227 && (range
& 0x3000) == 0x1000)
4229 unwind
.opcode_count
--;
4230 unwind
.sp_restored
= 0;
4231 range
= (range
| 0x2000) & ~0x1000;
4232 unwind
.pending_offset
= 0;
4238 /* See if we can use the short opcodes. These pop a block of up to 8
4239 registers starting with r4, plus maybe r14. */
4240 for (n
= 0; n
< 8; n
++)
4242 /* Break at the first non-saved register. */
4243 if ((range
& (1 << (n
+ 4))) == 0)
4246 /* See if there are any other bits set. */
4247 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4249 /* Use the long form. */
4250 op
= 0x8000 | ((range
>> 4) & 0xfff);
4251 add_unwind_opcode (op
, 2);
4255 /* Use the short form. */
4257 op
= 0xa8; /* Pop r14. */
4259 op
= 0xa0; /* Do not pop r14. */
4261 add_unwind_opcode (op
, 1);
4268 op
= 0xb100 | (range
& 0xf);
4269 add_unwind_opcode (op
, 2);
4272 /* Record the number of bytes pushed. */
4273 for (n
= 0; n
< 16; n
++)
4275 if (range
& (1 << n
))
4276 unwind
.frame_size
+= 4;
4281 /* Parse a directive saving FPA registers. */
4284 s_arm_unwind_save_fpa (int reg
)
4290 /* Get Number of registers to transfer. */
4291 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4294 exp
.X_op
= O_illegal
;
4296 if (exp
.X_op
!= O_constant
)
4298 as_bad (_("expected , <constant>"));
4299 ignore_rest_of_line ();
4303 num_regs
= exp
.X_add_number
;
4305 if (num_regs
< 1 || num_regs
> 4)
4307 as_bad (_("number of registers must be in the range [1:4]"));
4308 ignore_rest_of_line ();
4312 demand_empty_rest_of_line ();
4317 op
= 0xb4 | (num_regs
- 1);
4318 add_unwind_opcode (op
, 1);
4323 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4324 add_unwind_opcode (op
, 2);
4326 unwind
.frame_size
+= num_regs
* 12;
4330 /* Parse a directive saving VFP registers for ARMv6 and above. */
4333 s_arm_unwind_save_vfp_armv6 (void)
4338 int num_vfpv3_regs
= 0;
4339 int num_regs_below_16
;
4340 bfd_boolean partial_match
;
4342 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4346 as_bad (_("expected register list"));
4347 ignore_rest_of_line ();
4351 demand_empty_rest_of_line ();
4353 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4354 than FSTMX/FLDMX-style ones). */
4356 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4358 num_vfpv3_regs
= count
;
4359 else if (start
+ count
> 16)
4360 num_vfpv3_regs
= start
+ count
- 16;
4362 if (num_vfpv3_regs
> 0)
4364 int start_offset
= start
> 16 ? start
- 16 : 0;
4365 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4366 add_unwind_opcode (op
, 2);
4369 /* Generate opcode for registers numbered in the range 0 .. 15. */
4370 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4371 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4372 if (num_regs_below_16
> 0)
4374 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4375 add_unwind_opcode (op
, 2);
4378 unwind
.frame_size
+= count
* 8;
4382 /* Parse a directive saving VFP registers for pre-ARMv6. */
4385 s_arm_unwind_save_vfp (void)
4390 bfd_boolean partial_match
;
4392 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4396 as_bad (_("expected register list"));
4397 ignore_rest_of_line ();
4401 demand_empty_rest_of_line ();
4406 op
= 0xb8 | (count
- 1);
4407 add_unwind_opcode (op
, 1);
4412 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4413 add_unwind_opcode (op
, 2);
4415 unwind
.frame_size
+= count
* 8 + 4;
4419 /* Parse a directive saving iWMMXt data registers. */
4422 s_arm_unwind_save_mmxwr (void)
4430 if (*input_line_pointer
== '{')
4431 input_line_pointer
++;
4435 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4439 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4444 as_tsktsk (_("register list not in ascending order"));
4447 if (*input_line_pointer
== '-')
4449 input_line_pointer
++;
4450 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4453 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4456 else if (reg
>= hi_reg
)
4458 as_bad (_("bad register range"));
4461 for (; reg
< hi_reg
; reg
++)
4465 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4467 skip_past_char (&input_line_pointer
, '}');
4469 demand_empty_rest_of_line ();
4471 /* Generate any deferred opcodes because we're going to be looking at
4473 flush_pending_unwind ();
4475 for (i
= 0; i
< 16; i
++)
4477 if (mask
& (1 << i
))
4478 unwind
.frame_size
+= 8;
4481 /* Attempt to combine with a previous opcode. We do this because gcc
4482 likes to output separate unwind directives for a single block of
4484 if (unwind
.opcode_count
> 0)
4486 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4487 if ((i
& 0xf8) == 0xc0)
4490 /* Only merge if the blocks are contiguous. */
4493 if ((mask
& 0xfe00) == (1 << 9))
4495 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4496 unwind
.opcode_count
--;
4499 else if (i
== 6 && unwind
.opcode_count
>= 2)
4501 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4505 op
= 0xffff << (reg
- 1);
4507 && ((mask
& op
) == (1u << (reg
- 1))))
4509 op
= (1 << (reg
+ i
+ 1)) - 1;
4510 op
&= ~((1 << reg
) - 1);
4512 unwind
.opcode_count
-= 2;
4519 /* We want to generate opcodes in the order the registers have been
4520 saved, ie. descending order. */
4521 for (reg
= 15; reg
>= -1; reg
--)
4523 /* Save registers in blocks. */
4525 || !(mask
& (1 << reg
)))
4527 /* We found an unsaved reg. Generate opcodes to save the
4534 op
= 0xc0 | (hi_reg
- 10);
4535 add_unwind_opcode (op
, 1);
4540 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4541 add_unwind_opcode (op
, 2);
4550 ignore_rest_of_line ();
4554 s_arm_unwind_save_mmxwcg (void)
4561 if (*input_line_pointer
== '{')
4562 input_line_pointer
++;
4564 skip_whitespace (input_line_pointer
);
4568 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4572 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4578 as_tsktsk (_("register list not in ascending order"));
4581 if (*input_line_pointer
== '-')
4583 input_line_pointer
++;
4584 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4587 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4590 else if (reg
>= hi_reg
)
4592 as_bad (_("bad register range"));
4595 for (; reg
< hi_reg
; reg
++)
4599 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4601 skip_past_char (&input_line_pointer
, '}');
4603 demand_empty_rest_of_line ();
4605 /* Generate any deferred opcodes because we're going to be looking at
4607 flush_pending_unwind ();
4609 for (reg
= 0; reg
< 16; reg
++)
4611 if (mask
& (1 << reg
))
4612 unwind
.frame_size
+= 4;
4615 add_unwind_opcode (op
, 2);
4618 ignore_rest_of_line ();
4622 /* Parse an unwind_save directive.
4623 If the argument is non-zero, this is a .vsave directive. */
4626 s_arm_unwind_save (int arch_v6
)
4629 struct reg_entry
*reg
;
4630 bfd_boolean had_brace
= FALSE
;
4632 if (!unwind
.proc_start
)
4633 as_bad (MISSING_FNSTART
);
4635 /* Figure out what sort of save we have. */
4636 peek
= input_line_pointer
;
4644 reg
= arm_reg_parse_multi (&peek
);
4648 as_bad (_("register expected"));
4649 ignore_rest_of_line ();
4658 as_bad (_("FPA .unwind_save does not take a register list"));
4659 ignore_rest_of_line ();
4662 input_line_pointer
= peek
;
4663 s_arm_unwind_save_fpa (reg
->number
);
4667 s_arm_unwind_save_core ();
4672 s_arm_unwind_save_vfp_armv6 ();
4674 s_arm_unwind_save_vfp ();
4677 case REG_TYPE_MMXWR
:
4678 s_arm_unwind_save_mmxwr ();
4681 case REG_TYPE_MMXWCG
:
4682 s_arm_unwind_save_mmxwcg ();
4686 as_bad (_(".unwind_save does not support this kind of register"));
4687 ignore_rest_of_line ();
4692 /* Parse an unwind_movsp directive. */
4695 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4701 if (!unwind
.proc_start
)
4702 as_bad (MISSING_FNSTART
);
4704 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4707 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4708 ignore_rest_of_line ();
4712 /* Optional constant. */
4713 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4715 if (immediate_for_directive (&offset
) == FAIL
)
4721 demand_empty_rest_of_line ();
4723 if (reg
== REG_SP
|| reg
== REG_PC
)
4725 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4729 if (unwind
.fp_reg
!= REG_SP
)
4730 as_bad (_("unexpected .unwind_movsp directive"));
4732 /* Generate opcode to restore the value. */
4734 add_unwind_opcode (op
, 1);
4736 /* Record the information for later. */
4737 unwind
.fp_reg
= reg
;
4738 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4739 unwind
.sp_restored
= 1;
4742 /* Parse an unwind_pad directive. */
4745 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4749 if (!unwind
.proc_start
)
4750 as_bad (MISSING_FNSTART
);
4752 if (immediate_for_directive (&offset
) == FAIL
)
4757 as_bad (_("stack increment must be multiple of 4"));
4758 ignore_rest_of_line ();
4762 /* Don't generate any opcodes, just record the details for later. */
4763 unwind
.frame_size
+= offset
;
4764 unwind
.pending_offset
+= offset
;
4766 demand_empty_rest_of_line ();
4769 /* Parse an unwind_setfp directive. */
4772 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4778 if (!unwind
.proc_start
)
4779 as_bad (MISSING_FNSTART
);
4781 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4782 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4785 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4787 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4789 as_bad (_("expected <reg>, <reg>"));
4790 ignore_rest_of_line ();
4794 /* Optional constant. */
4795 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4797 if (immediate_for_directive (&offset
) == FAIL
)
4803 demand_empty_rest_of_line ();
4805 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4807 as_bad (_("register must be either sp or set by a previous"
4808 "unwind_movsp directive"));
4812 /* Don't generate any opcodes, just record the information for later. */
4813 unwind
.fp_reg
= fp_reg
;
4815 if (sp_reg
== REG_SP
)
4816 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4818 unwind
.fp_offset
-= offset
;
4821 /* Parse an unwind_raw directive. */
4824 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4827 /* This is an arbitrary limit. */
4828 unsigned char op
[16];
4831 if (!unwind
.proc_start
)
4832 as_bad (MISSING_FNSTART
);
4835 if (exp
.X_op
== O_constant
4836 && skip_past_comma (&input_line_pointer
) != FAIL
)
4838 unwind
.frame_size
+= exp
.X_add_number
;
4842 exp
.X_op
= O_illegal
;
4844 if (exp
.X_op
!= O_constant
)
4846 as_bad (_("expected <offset>, <opcode>"));
4847 ignore_rest_of_line ();
4853 /* Parse the opcode. */
4858 as_bad (_("unwind opcode too long"));
4859 ignore_rest_of_line ();
4861 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4863 as_bad (_("invalid unwind opcode"));
4864 ignore_rest_of_line ();
4867 op
[count
++] = exp
.X_add_number
;
4869 /* Parse the next byte. */
4870 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4876 /* Add the opcode bytes in reverse order. */
4878 add_unwind_opcode (op
[count
], 1);
4880 demand_empty_rest_of_line ();
4884 /* Parse a .eabi_attribute directive. */
4887 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4889 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4891 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4892 attributes_set_explicitly
[tag
] = 1;
4895 /* Emit a tls fix for the symbol. */
4898 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4902 #ifdef md_flush_pending_output
4903 md_flush_pending_output ();
4906 #ifdef md_cons_align
4910 /* Since we're just labelling the code, there's no need to define a
4913 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4914 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4915 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4916 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4918 #endif /* OBJ_ELF */
4920 static void s_arm_arch (int);
4921 static void s_arm_object_arch (int);
4922 static void s_arm_cpu (int);
4923 static void s_arm_fpu (int);
4924 static void s_arm_arch_extension (int);
4929 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4936 if (exp
.X_op
== O_symbol
)
4937 exp
.X_op
= O_secrel
;
4939 emit_expr (&exp
, 4);
4941 while (*input_line_pointer
++ == ',');
4943 input_line_pointer
--;
4944 demand_empty_rest_of_line ();
4949 arm_is_largest_exponent_ok (int precision
)
4951 /* precision == 1 ensures that this will only return
4952 true for 16 bit floats. */
4953 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
4957 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
4961 enum fp_16bit_format new_format
;
4963 new_format
= ARM_FP16_FORMAT_DEFAULT
;
4965 name
= input_line_pointer
;
4966 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
4967 input_line_pointer
++;
4969 saved_char
= *input_line_pointer
;
4970 *input_line_pointer
= 0;
4972 if (strcasecmp (name
, "ieee") == 0)
4973 new_format
= ARM_FP16_FORMAT_IEEE
;
4974 else if (strcasecmp (name
, "alternative") == 0)
4975 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
4978 as_bad (_("unrecognised float16 format \"%s\""), name
);
4982 /* Only set fp16_format if it is still the default (aka not already
4984 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
4985 fp16_format
= new_format
;
4988 if (new_format
!= fp16_format
)
4989 as_warn (_("float16 format cannot be set more than once, ignoring."));
4993 *input_line_pointer
= saved_char
;
4994 ignore_rest_of_line ();
4997 /* This table describes all the machine specific pseudo-ops the assembler
4998 has to support. The fields are:
4999 pseudo-op name without dot
5000 function to call to execute this pseudo-op
5001 Integer arg to pass to the function. */
5003 const pseudo_typeS md_pseudo_table
[] =
5005 /* Never called because '.req' does not start a line. */
5006 { "req", s_req
, 0 },
5007 /* Following two are likewise never called. */
5010 { "unreq", s_unreq
, 0 },
5011 { "bss", s_bss
, 0 },
5012 { "align", s_align_ptwo
, 2 },
5013 { "arm", s_arm
, 0 },
5014 { "thumb", s_thumb
, 0 },
5015 { "code", s_code
, 0 },
5016 { "force_thumb", s_force_thumb
, 0 },
5017 { "thumb_func", s_thumb_func
, 0 },
5018 { "thumb_set", s_thumb_set
, 0 },
5019 { "even", s_even
, 0 },
5020 { "ltorg", s_ltorg
, 0 },
5021 { "pool", s_ltorg
, 0 },
5022 { "syntax", s_syntax
, 0 },
5023 { "cpu", s_arm_cpu
, 0 },
5024 { "arch", s_arm_arch
, 0 },
5025 { "object_arch", s_arm_object_arch
, 0 },
5026 { "fpu", s_arm_fpu
, 0 },
5027 { "arch_extension", s_arm_arch_extension
, 0 },
5029 { "word", s_arm_elf_cons
, 4 },
5030 { "long", s_arm_elf_cons
, 4 },
5031 { "inst.n", s_arm_elf_inst
, 2 },
5032 { "inst.w", s_arm_elf_inst
, 4 },
5033 { "inst", s_arm_elf_inst
, 0 },
5034 { "rel31", s_arm_rel31
, 0 },
5035 { "fnstart", s_arm_unwind_fnstart
, 0 },
5036 { "fnend", s_arm_unwind_fnend
, 0 },
5037 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5038 { "personality", s_arm_unwind_personality
, 0 },
5039 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5040 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5041 { "save", s_arm_unwind_save
, 0 },
5042 { "vsave", s_arm_unwind_save
, 1 },
5043 { "movsp", s_arm_unwind_movsp
, 0 },
5044 { "pad", s_arm_unwind_pad
, 0 },
5045 { "setfp", s_arm_unwind_setfp
, 0 },
5046 { "unwind_raw", s_arm_unwind_raw
, 0 },
5047 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5048 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5052 /* These are used for dwarf. */
5056 /* These are used for dwarf2. */
5057 { "file", dwarf2_directive_file
, 0 },
5058 { "loc", dwarf2_directive_loc
, 0 },
5059 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5061 { "extend", float_cons
, 'x' },
5062 { "ldouble", float_cons
, 'x' },
5063 { "packed", float_cons
, 'p' },
5065 {"secrel32", pe_directive_secrel
, 0},
5068 /* These are for compatibility with CodeComposer Studio. */
5069 {"ref", s_ccs_ref
, 0},
5070 {"def", s_ccs_def
, 0},
5071 {"asmfunc", s_ccs_asmfunc
, 0},
5072 {"endasmfunc", s_ccs_endasmfunc
, 0},
5074 {"float16", float_cons
, 'h' },
5075 {"float16_format", set_fp16_format
, 0 },
5080 /* Parser functions used exclusively in instruction operands. */
5082 /* Generic immediate-value read function for use in insn parsing.
5083 STR points to the beginning of the immediate (the leading #);
5084 VAL receives the value; if the value is outside [MIN, MAX]
5085 issue an error. PREFIX_OPT is true if the immediate prefix is
5089 parse_immediate (char **str
, int *val
, int min
, int max
,
5090 bfd_boolean prefix_opt
)
5094 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5095 if (exp
.X_op
!= O_constant
)
5097 inst
.error
= _("constant expression required");
5101 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5103 inst
.error
= _("immediate value out of range");
5107 *val
= exp
.X_add_number
;
5111 /* Less-generic immediate-value read function with the possibility of loading a
5112 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5113 instructions. Puts the result directly in inst.operands[i]. */
5116 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5117 bfd_boolean allow_symbol_p
)
5120 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5123 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5125 if (exp_p
->X_op
== O_constant
)
5127 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5128 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5129 O_constant. We have to be careful not to break compilation for
5130 32-bit X_add_number, though. */
5131 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5133 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5134 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5136 inst
.operands
[i
].regisimm
= 1;
5139 else if (exp_p
->X_op
== O_big
5140 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5142 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5144 /* Bignums have their least significant bits in
5145 generic_bignum[0]. Make sure we put 32 bits in imm and
5146 32 bits in reg, in a (hopefully) portable way. */
5147 gas_assert (parts
!= 0);
5149 /* Make sure that the number is not too big.
5150 PR 11972: Bignums can now be sign-extended to the
5151 size of a .octa so check that the out of range bits
5152 are all zero or all one. */
5153 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5155 LITTLENUM_TYPE m
= -1;
5157 if (generic_bignum
[parts
* 2] != 0
5158 && generic_bignum
[parts
* 2] != m
)
5161 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5162 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5166 inst
.operands
[i
].imm
= 0;
5167 for (j
= 0; j
< parts
; j
++, idx
++)
5168 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5169 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5170 inst
.operands
[i
].reg
= 0;
5171 for (j
= 0; j
< parts
; j
++, idx
++)
5172 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5173 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5174 inst
.operands
[i
].regisimm
= 1;
5176 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5184 /* Returns the pseudo-register number of an FPA immediate constant,
5185 or FAIL if there isn't a valid constant here. */
5188 parse_fpa_immediate (char ** str
)
5190 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5196 /* First try and match exact strings, this is to guarantee
5197 that some formats will work even for cross assembly. */
5199 for (i
= 0; fp_const
[i
]; i
++)
5201 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5205 *str
+= strlen (fp_const
[i
]);
5206 if (is_end_of_line
[(unsigned char) **str
])
5212 /* Just because we didn't get a match doesn't mean that the constant
5213 isn't valid, just that it is in a format that we don't
5214 automatically recognize. Try parsing it with the standard
5215 expression routines. */
5217 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5219 /* Look for a raw floating point number. */
5220 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5221 && is_end_of_line
[(unsigned char) *save_in
])
5223 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5225 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5227 if (words
[j
] != fp_values
[i
][j
])
5231 if (j
== MAX_LITTLENUMS
)
5239 /* Try and parse a more complex expression, this will probably fail
5240 unless the code uses a floating point prefix (eg "0f"). */
5241 save_in
= input_line_pointer
;
5242 input_line_pointer
= *str
;
5243 if (expression (&exp
) == absolute_section
5244 && exp
.X_op
== O_big
5245 && exp
.X_add_number
< 0)
5247 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5249 #define X_PRECISION 5
5250 #define E_PRECISION 15L
5251 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5253 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5255 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5257 if (words
[j
] != fp_values
[i
][j
])
5261 if (j
== MAX_LITTLENUMS
)
5263 *str
= input_line_pointer
;
5264 input_line_pointer
= save_in
;
5271 *str
= input_line_pointer
;
5272 input_line_pointer
= save_in
;
5273 inst
.error
= _("invalid FPA immediate expression");
5277 /* Returns 1 if a number has "quarter-precision" float format
5278 0baBbbbbbc defgh000 00000000 00000000. */
5281 is_quarter_float (unsigned imm
)
5283 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5284 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5288 /* Detect the presence of a floating point or integer zero constant,
5292 parse_ifimm_zero (char **in
)
5296 if (!is_immediate_prefix (**in
))
5298 /* In unified syntax, all prefixes are optional. */
5299 if (!unified_syntax
)
5305 /* Accept #0x0 as a synonym for #0. */
5306 if (strncmp (*in
, "0x", 2) == 0)
5309 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5314 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5315 &generic_floating_point_number
);
5318 && generic_floating_point_number
.sign
== '+'
5319 && (generic_floating_point_number
.low
5320 > generic_floating_point_number
.leader
))
5326 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5327 0baBbbbbbc defgh000 00000000 00000000.
5328 The zero and minus-zero cases need special handling, since they can't be
5329 encoded in the "quarter-precision" float format, but can nonetheless be
5330 loaded as integer constants. */
5333 parse_qfloat_immediate (char **ccp
, int *immed
)
5337 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5338 int found_fpchar
= 0;
5340 skip_past_char (&str
, '#');
5342 /* We must not accidentally parse an integer as a floating-point number. Make
5343 sure that the value we parse is not an integer by checking for special
5344 characters '.' or 'e'.
5345 FIXME: This is a horrible hack, but doing better is tricky because type
5346 information isn't in a very usable state at parse time. */
5348 skip_whitespace (fpnum
);
5350 if (strncmp (fpnum
, "0x", 2) == 0)
5354 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5355 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5365 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5367 unsigned fpword
= 0;
5370 /* Our FP word must be 32 bits (single-precision FP). */
5371 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5373 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5377 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5390 /* Shift operands. */
5393 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5396 struct asm_shift_name
5399 enum shift_kind kind
;
5402 /* Third argument to parse_shift. */
5403 enum parse_shift_mode
5405 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5406 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5407 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5408 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5409 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5410 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5413 /* Parse a <shift> specifier on an ARM data processing instruction.
5414 This has three forms:
5416 (LSL|LSR|ASL|ASR|ROR) Rs
5417 (LSL|LSR|ASL|ASR|ROR) #imm
5420 Note that ASL is assimilated to LSL in the instruction encoding, and
5421 RRX to ROR #0 (which cannot be written as such). */
5424 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5426 const struct asm_shift_name
*shift_name
;
5427 enum shift_kind shift
;
5432 for (p
= *str
; ISALPHA (*p
); p
++)
5437 inst
.error
= _("shift expression expected");
5441 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5444 if (shift_name
== NULL
)
5446 inst
.error
= _("shift expression expected");
5450 shift
= shift_name
->kind
;
5454 case NO_SHIFT_RESTRICT
:
5455 case SHIFT_IMMEDIATE
:
5456 if (shift
== SHIFT_UXTW
)
5458 inst
.error
= _("'UXTW' not allowed here");
5463 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5464 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5466 inst
.error
= _("'LSL' or 'ASR' required");
5471 case SHIFT_LSL_IMMEDIATE
:
5472 if (shift
!= SHIFT_LSL
)
5474 inst
.error
= _("'LSL' required");
5479 case SHIFT_ASR_IMMEDIATE
:
5480 if (shift
!= SHIFT_ASR
)
5482 inst
.error
= _("'ASR' required");
5486 case SHIFT_UXTW_IMMEDIATE
:
5487 if (shift
!= SHIFT_UXTW
)
5489 inst
.error
= _("'UXTW' required");
5497 if (shift
!= SHIFT_RRX
)
5499 /* Whitespace can appear here if the next thing is a bare digit. */
5500 skip_whitespace (p
);
5502 if (mode
== NO_SHIFT_RESTRICT
5503 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5505 inst
.operands
[i
].imm
= reg
;
5506 inst
.operands
[i
].immisreg
= 1;
5508 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5511 inst
.operands
[i
].shift_kind
= shift
;
5512 inst
.operands
[i
].shifted
= 1;
5517 /* Parse a <shifter_operand> for an ARM data processing instruction:
5520 #<immediate>, <rotate>
5524 where <shift> is defined by parse_shift above, and <rotate> is a
5525 multiple of 2 between 0 and 30. Validation of immediate operands
5526 is deferred to md_apply_fix. */
5529 parse_shifter_operand (char **str
, int i
)
5534 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5536 inst
.operands
[i
].reg
= value
;
5537 inst
.operands
[i
].isreg
= 1;
5539 /* parse_shift will override this if appropriate */
5540 inst
.relocs
[0].exp
.X_op
= O_constant
;
5541 inst
.relocs
[0].exp
.X_add_number
= 0;
5543 if (skip_past_comma (str
) == FAIL
)
5546 /* Shift operation on register. */
5547 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5550 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5553 if (skip_past_comma (str
) == SUCCESS
)
5555 /* #x, y -- ie explicit rotation by Y. */
5556 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5559 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5561 inst
.error
= _("constant expression expected");
5565 value
= exp
.X_add_number
;
5566 if (value
< 0 || value
> 30 || value
% 2 != 0)
5568 inst
.error
= _("invalid rotation");
5571 if (inst
.relocs
[0].exp
.X_add_number
< 0
5572 || inst
.relocs
[0].exp
.X_add_number
> 255)
5574 inst
.error
= _("invalid constant");
5578 /* Encode as specified. */
5579 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5583 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5584 inst
.relocs
[0].pc_rel
= 0;
5588 /* Group relocation information. Each entry in the table contains the
5589 textual name of the relocation as may appear in assembler source
5590 and must end with a colon.
5591 Along with this textual name are the relocation codes to be used if
5592 the corresponding instruction is an ALU instruction (ADD or SUB only),
5593 an LDR, an LDRS, or an LDC. */
5595 struct group_reloc_table_entry
5606 /* Varieties of non-ALU group relocation. */
5614 static struct group_reloc_table_entry group_reloc_table
[] =
5615 { /* Program counter relative: */
5617 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5622 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5623 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5624 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5625 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5627 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5632 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5633 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5634 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5635 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5637 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5638 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5639 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5640 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5641 /* Section base relative */
5643 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5648 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5649 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5650 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5651 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5653 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5658 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5659 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5660 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5661 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5663 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5664 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5665 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5666 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5667 /* Absolute thumb alu relocations. */
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5679 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5684 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5689 /* Given the address of a pointer pointing to the textual name of a group
5690 relocation as may appear in assembler source, attempt to find its details
5691 in group_reloc_table. The pointer will be updated to the character after
5692 the trailing colon. On failure, FAIL will be returned; SUCCESS
5693 otherwise. On success, *entry will be updated to point at the relevant
5694 group_reloc_table entry. */
5697 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5700 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5702 int length
= strlen (group_reloc_table
[i
].name
);
5704 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5705 && (*str
)[length
] == ':')
5707 *out
= &group_reloc_table
[i
];
5708 *str
+= (length
+ 1);
5716 /* Parse a <shifter_operand> for an ARM data processing instruction
5717 (as for parse_shifter_operand) where group relocations are allowed:
5720 #<immediate>, <rotate>
5721 #:<group_reloc>:<expression>
5725 where <group_reloc> is one of the strings defined in group_reloc_table.
5726 The hashes are optional.
5728 Everything else is as for parse_shifter_operand. */
5730 static parse_operand_result
5731 parse_shifter_operand_group_reloc (char **str
, int i
)
5733 /* Determine if we have the sequence of characters #: or just :
5734 coming next. If we do, then we check for a group relocation.
5735 If we don't, punt the whole lot to parse_shifter_operand. */
5737 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5738 || (*str
)[0] == ':')
5740 struct group_reloc_table_entry
*entry
;
5742 if ((*str
)[0] == '#')
5747 /* Try to parse a group relocation. Anything else is an error. */
5748 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5750 inst
.error
= _("unknown group relocation");
5751 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5754 /* We now have the group relocation table entry corresponding to
5755 the name in the assembler source. Next, we parse the expression. */
5756 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5757 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5759 /* Record the relocation type (always the ALU variant here). */
5760 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5761 gas_assert (inst
.relocs
[0].type
!= 0);
5763 return PARSE_OPERAND_SUCCESS
;
5766 return parse_shifter_operand (str
, i
) == SUCCESS
5767 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5769 /* Never reached. */
5772 /* Parse a Neon alignment expression. Information is written to
5773 inst.operands[i]. We assume the initial ':' has been skipped.
5775 align .imm = align << 8, .immisalign=1, .preind=0 */
5776 static parse_operand_result
5777 parse_neon_alignment (char **str
, int i
)
5782 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5784 if (exp
.X_op
!= O_constant
)
5786 inst
.error
= _("alignment must be constant");
5787 return PARSE_OPERAND_FAIL
;
5790 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5791 inst
.operands
[i
].immisalign
= 1;
5792 /* Alignments are not pre-indexes. */
5793 inst
.operands
[i
].preind
= 0;
5796 return PARSE_OPERAND_SUCCESS
;
5799 /* Parse all forms of an ARM address expression. Information is written
5800 to inst.operands[i] and/or inst.relocs[0].
5802 Preindexed addressing (.preind=1):
5804 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5805 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5806 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5807 .shift_kind=shift .relocs[0].exp=shift_imm
5809 These three may have a trailing ! which causes .writeback to be set also.
5811 Postindexed addressing (.postind=1, .writeback=1):
5813 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5814 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5815 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5816 .shift_kind=shift .relocs[0].exp=shift_imm
5818 Unindexed addressing (.preind=0, .postind=0):
5820 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5824 [Rn]{!} shorthand for [Rn,#0]{!}
5825 =immediate .isreg=0 .relocs[0].exp=immediate
5826 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5828 It is the caller's responsibility to check for addressing modes not
5829 supported by the instruction, and to set inst.relocs[0].type. */
5831 static parse_operand_result
5832 parse_address_main (char **str
, int i
, int group_relocations
,
5833 group_reloc_type group_type
)
5838 if (skip_past_char (&p
, '[') == FAIL
)
5840 if (skip_past_char (&p
, '=') == FAIL
)
5842 /* Bare address - translate to PC-relative offset. */
5843 inst
.relocs
[0].pc_rel
= 1;
5844 inst
.operands
[i
].reg
= REG_PC
;
5845 inst
.operands
[i
].isreg
= 1;
5846 inst
.operands
[i
].preind
= 1;
5848 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5849 return PARSE_OPERAND_FAIL
;
5851 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5852 /*allow_symbol_p=*/TRUE
))
5853 return PARSE_OPERAND_FAIL
;
5856 return PARSE_OPERAND_SUCCESS
;
5859 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5860 skip_whitespace (p
);
5862 if (group_type
== GROUP_MVE
)
5864 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5865 struct neon_type_el et
;
5866 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5868 inst
.operands
[i
].isquad
= 1;
5870 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5872 inst
.error
= BAD_ADDR_MODE
;
5873 return PARSE_OPERAND_FAIL
;
5876 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5878 if (group_type
== GROUP_MVE
)
5879 inst
.error
= BAD_ADDR_MODE
;
5881 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5882 return PARSE_OPERAND_FAIL
;
5884 inst
.operands
[i
].reg
= reg
;
5885 inst
.operands
[i
].isreg
= 1;
5887 if (skip_past_comma (&p
) == SUCCESS
)
5889 inst
.operands
[i
].preind
= 1;
5892 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5894 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5895 struct neon_type_el et
;
5896 if (group_type
== GROUP_MVE
5897 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5899 inst
.operands
[i
].immisreg
= 2;
5900 inst
.operands
[i
].imm
= reg
;
5902 if (skip_past_comma (&p
) == SUCCESS
)
5904 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5906 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5907 inst
.relocs
[0].exp
.X_add_number
= 0;
5910 return PARSE_OPERAND_FAIL
;
5913 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5915 inst
.operands
[i
].imm
= reg
;
5916 inst
.operands
[i
].immisreg
= 1;
5918 if (skip_past_comma (&p
) == SUCCESS
)
5919 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5920 return PARSE_OPERAND_FAIL
;
5922 else if (skip_past_char (&p
, ':') == SUCCESS
)
5924 /* FIXME: '@' should be used here, but it's filtered out by generic
5925 code before we get to see it here. This may be subject to
5927 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5929 if (result
!= PARSE_OPERAND_SUCCESS
)
5934 if (inst
.operands
[i
].negative
)
5936 inst
.operands
[i
].negative
= 0;
5940 if (group_relocations
5941 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5943 struct group_reloc_table_entry
*entry
;
5945 /* Skip over the #: or : sequence. */
5951 /* Try to parse a group relocation. Anything else is an
5953 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5955 inst
.error
= _("unknown group relocation");
5956 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5959 /* We now have the group relocation table entry corresponding to
5960 the name in the assembler source. Next, we parse the
5962 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5963 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5965 /* Record the relocation type. */
5970 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5975 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5980 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5987 if (inst
.relocs
[0].type
== 0)
5989 inst
.error
= _("this group relocation is not allowed on this instruction");
5990 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5997 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5998 return PARSE_OPERAND_FAIL
;
5999 /* If the offset is 0, find out if it's a +0 or -0. */
6000 if (inst
.relocs
[0].exp
.X_op
== O_constant
6001 && inst
.relocs
[0].exp
.X_add_number
== 0)
6003 skip_whitespace (q
);
6007 skip_whitespace (q
);
6010 inst
.operands
[i
].negative
= 1;
6015 else if (skip_past_char (&p
, ':') == SUCCESS
)
6017 /* FIXME: '@' should be used here, but it's filtered out by generic code
6018 before we get to see it here. This may be subject to change. */
6019 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6021 if (result
!= PARSE_OPERAND_SUCCESS
)
6025 if (skip_past_char (&p
, ']') == FAIL
)
6027 inst
.error
= _("']' expected");
6028 return PARSE_OPERAND_FAIL
;
6031 if (skip_past_char (&p
, '!') == SUCCESS
)
6032 inst
.operands
[i
].writeback
= 1;
6034 else if (skip_past_comma (&p
) == SUCCESS
)
6036 if (skip_past_char (&p
, '{') == SUCCESS
)
6038 /* [Rn], {expr} - unindexed, with option */
6039 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6040 0, 255, TRUE
) == FAIL
)
6041 return PARSE_OPERAND_FAIL
;
6043 if (skip_past_char (&p
, '}') == FAIL
)
6045 inst
.error
= _("'}' expected at end of 'option' field");
6046 return PARSE_OPERAND_FAIL
;
6048 if (inst
.operands
[i
].preind
)
6050 inst
.error
= _("cannot combine index with option");
6051 return PARSE_OPERAND_FAIL
;
6054 return PARSE_OPERAND_SUCCESS
;
6058 inst
.operands
[i
].postind
= 1;
6059 inst
.operands
[i
].writeback
= 1;
6061 if (inst
.operands
[i
].preind
)
6063 inst
.error
= _("cannot combine pre- and post-indexing");
6064 return PARSE_OPERAND_FAIL
;
6068 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6070 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6071 struct neon_type_el et
;
6072 if (group_type
== GROUP_MVE
6073 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6075 inst
.operands
[i
].immisreg
= 2;
6076 inst
.operands
[i
].imm
= reg
;
6078 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6080 /* We might be using the immediate for alignment already. If we
6081 are, OR the register number into the low-order bits. */
6082 if (inst
.operands
[i
].immisalign
)
6083 inst
.operands
[i
].imm
|= reg
;
6085 inst
.operands
[i
].imm
= reg
;
6086 inst
.operands
[i
].immisreg
= 1;
6088 if (skip_past_comma (&p
) == SUCCESS
)
6089 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6090 return PARSE_OPERAND_FAIL
;
6096 if (inst
.operands
[i
].negative
)
6098 inst
.operands
[i
].negative
= 0;
6101 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6102 return PARSE_OPERAND_FAIL
;
6103 /* If the offset is 0, find out if it's a +0 or -0. */
6104 if (inst
.relocs
[0].exp
.X_op
== O_constant
6105 && inst
.relocs
[0].exp
.X_add_number
== 0)
6107 skip_whitespace (q
);
6111 skip_whitespace (q
);
6114 inst
.operands
[i
].negative
= 1;
6120 /* If at this point neither .preind nor .postind is set, we have a
6121 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6122 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6124 inst
.operands
[i
].preind
= 1;
6125 inst
.relocs
[0].exp
.X_op
= O_constant
;
6126 inst
.relocs
[0].exp
.X_add_number
= 0;
6129 return PARSE_OPERAND_SUCCESS
;
6133 parse_address (char **str
, int i
)
6135 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6139 static parse_operand_result
6140 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6142 return parse_address_main (str
, i
, 1, type
);
6145 /* Parse an operand for a MOVW or MOVT instruction. */
6147 parse_half (char **str
)
6152 skip_past_char (&p
, '#');
6153 if (strncasecmp (p
, ":lower16:", 9) == 0)
6154 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6155 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6156 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6158 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6161 skip_whitespace (p
);
6164 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6167 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6169 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6171 inst
.error
= _("constant expression expected");
6174 if (inst
.relocs
[0].exp
.X_add_number
< 0
6175 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6177 inst
.error
= _("immediate value out of range");
6185 /* Miscellaneous. */
6187 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6188 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6190 parse_psr (char **str
, bfd_boolean lhs
)
6193 unsigned long psr_field
;
6194 const struct asm_psr
*psr
;
6196 bfd_boolean is_apsr
= FALSE
;
6197 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6199 /* PR gas/12698: If the user has specified -march=all then m_profile will
6200 be TRUE, but we want to ignore it in this case as we are building for any
6201 CPU type, including non-m variants. */
6202 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6205 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6206 feature for ease of use and backwards compatibility. */
6208 if (strncasecmp (p
, "SPSR", 4) == 0)
6211 goto unsupported_psr
;
6213 psr_field
= SPSR_BIT
;
6215 else if (strncasecmp (p
, "CPSR", 4) == 0)
6218 goto unsupported_psr
;
6222 else if (strncasecmp (p
, "APSR", 4) == 0)
6224 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6225 and ARMv7-R architecture CPUs. */
6234 while (ISALNUM (*p
) || *p
== '_');
6236 if (strncasecmp (start
, "iapsr", 5) == 0
6237 || strncasecmp (start
, "eapsr", 5) == 0
6238 || strncasecmp (start
, "xpsr", 4) == 0
6239 || strncasecmp (start
, "psr", 3) == 0)
6240 p
= start
+ strcspn (start
, "rR") + 1;
6242 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6248 /* If APSR is being written, a bitfield may be specified. Note that
6249 APSR itself is handled above. */
6250 if (psr
->field
<= 3)
6252 psr_field
= psr
->field
;
6258 /* M-profile MSR instructions have the mask field set to "10", except
6259 *PSR variants which modify APSR, which may use a different mask (and
6260 have been handled already). Do that by setting the PSR_f field
6262 return psr
->field
| (lhs
? PSR_f
: 0);
6265 goto unsupported_psr
;
6271 /* A suffix follows. */
6277 while (ISALNUM (*p
) || *p
== '_');
6281 /* APSR uses a notation for bits, rather than fields. */
6282 unsigned int nzcvq_bits
= 0;
6283 unsigned int g_bit
= 0;
6286 for (bit
= start
; bit
!= p
; bit
++)
6288 switch (TOLOWER (*bit
))
6291 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6295 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6299 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6303 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6307 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6311 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6315 inst
.error
= _("unexpected bit specified after APSR");
6320 if (nzcvq_bits
== 0x1f)
6325 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6327 inst
.error
= _("selected processor does not "
6328 "support DSP extension");
6335 if ((nzcvq_bits
& 0x20) != 0
6336 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6337 || (g_bit
& 0x2) != 0)
6339 inst
.error
= _("bad bitmask specified after APSR");
6345 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6350 psr_field
|= psr
->field
;
6356 goto error
; /* Garbage after "[CS]PSR". */
6358 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6359 is deprecated, but allow it anyway. */
6363 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6366 else if (!m_profile
)
6367 /* These bits are never right for M-profile devices: don't set them
6368 (only code paths which read/write APSR reach here). */
6369 psr_field
|= (PSR_c
| PSR_f
);
6375 inst
.error
= _("selected processor does not support requested special "
6376 "purpose register");
6380 inst
.error
= _("flag for {c}psr instruction expected");
6385 parse_sys_vldr_vstr (char **str
)
6394 {"FPSCR", 0x1, 0x0},
6395 {"FPSCR_nzcvqc", 0x2, 0x0},
6398 {"FPCXTNS", 0x6, 0x1},
6399 {"FPCXTS", 0x7, 0x1}
6401 char *op_end
= strchr (*str
, ',');
6402 size_t op_strlen
= op_end
- *str
;
6404 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6406 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6408 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6417 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6418 value suitable for splatting into the AIF field of the instruction. */
6421 parse_cps_flags (char **str
)
6430 case '\0': case ',':
6433 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6434 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6435 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6438 inst
.error
= _("unrecognized CPS flag");
6443 if (saw_a_flag
== 0)
6445 inst
.error
= _("missing CPS flags");
6453 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6454 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6457 parse_endian_specifier (char **str
)
6462 if (strncasecmp (s
, "BE", 2))
6464 else if (strncasecmp (s
, "LE", 2))
6468 inst
.error
= _("valid endian specifiers are be or le");
6472 if (ISALNUM (s
[2]) || s
[2] == '_')
6474 inst
.error
= _("valid endian specifiers are be or le");
6479 return little_endian
;
6482 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6483 value suitable for poking into the rotate field of an sxt or sxta
6484 instruction, or FAIL on error. */
6487 parse_ror (char **str
)
6492 if (strncasecmp (s
, "ROR", 3) == 0)
6496 inst
.error
= _("missing rotation field after comma");
6500 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6505 case 0: *str
= s
; return 0x0;
6506 case 8: *str
= s
; return 0x1;
6507 case 16: *str
= s
; return 0x2;
6508 case 24: *str
= s
; return 0x3;
6511 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6516 /* Parse a conditional code (from conds[] below). The value returned is in the
6517 range 0 .. 14, or FAIL. */
6519 parse_cond (char **str
)
6522 const struct asm_cond
*c
;
6524 /* Condition codes are always 2 characters, so matching up to
6525 3 characters is sufficient. */
6530 while (ISALPHA (*q
) && n
< 3)
6532 cond
[n
] = TOLOWER (*q
);
6537 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6540 inst
.error
= _("condition required");
6548 /* Parse an option for a barrier instruction. Returns the encoding for the
6551 parse_barrier (char **str
)
6554 const struct asm_barrier_opt
*o
;
6557 while (ISALPHA (*q
))
6560 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6565 if (!mark_feature_used (&o
->arch
))
6572 /* Parse the operands of a table branch instruction. Similar to a memory
6575 parse_tb (char **str
)
6580 if (skip_past_char (&p
, '[') == FAIL
)
6582 inst
.error
= _("'[' expected");
6586 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6588 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6591 inst
.operands
[0].reg
= reg
;
6593 if (skip_past_comma (&p
) == FAIL
)
6595 inst
.error
= _("',' expected");
6599 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6604 inst
.operands
[0].imm
= reg
;
6606 if (skip_past_comma (&p
) == SUCCESS
)
6608 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6610 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6612 inst
.error
= _("invalid shift");
6615 inst
.operands
[0].shifted
= 1;
6618 if (skip_past_char (&p
, ']') == FAIL
)
6620 inst
.error
= _("']' expected");
6627 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6628 information on the types the operands can take and how they are encoded.
6629 Up to four operands may be read; this function handles setting the
6630 ".present" field for each read operand itself.
6631 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6632 else returns FAIL. */
6635 parse_neon_mov (char **str
, int *which_operand
)
6637 int i
= *which_operand
, val
;
6638 enum arm_reg_type rtype
;
6640 struct neon_type_el optype
;
6642 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6644 /* Cases 17 or 19. */
6645 inst
.operands
[i
].reg
= val
;
6646 inst
.operands
[i
].isvec
= 1;
6647 inst
.operands
[i
].isscalar
= 2;
6648 inst
.operands
[i
].vectype
= optype
;
6649 inst
.operands
[i
++].present
= 1;
6651 if (skip_past_comma (&ptr
) == FAIL
)
6654 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6656 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6657 inst
.operands
[i
].reg
= val
;
6658 inst
.operands
[i
].isreg
= 1;
6659 inst
.operands
[i
].present
= 1;
6661 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6663 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6664 inst
.operands
[i
].reg
= val
;
6665 inst
.operands
[i
].isvec
= 1;
6666 inst
.operands
[i
].isscalar
= 2;
6667 inst
.operands
[i
].vectype
= optype
;
6668 inst
.operands
[i
++].present
= 1;
6670 if (skip_past_comma (&ptr
) == FAIL
)
6673 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
++].present
= 1;
6680 if (skip_past_comma (&ptr
) == FAIL
)
6683 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6686 inst
.operands
[i
].reg
= val
;
6687 inst
.operands
[i
].isreg
= 1;
6688 inst
.operands
[i
].present
= 1;
6692 first_error (_("expected ARM or MVE vector register"));
6696 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6698 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6699 inst
.operands
[i
].reg
= val
;
6700 inst
.operands
[i
].isscalar
= 1;
6701 inst
.operands
[i
].vectype
= optype
;
6702 inst
.operands
[i
++].present
= 1;
6704 if (skip_past_comma (&ptr
) == FAIL
)
6707 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6710 inst
.operands
[i
].reg
= val
;
6711 inst
.operands
[i
].isreg
= 1;
6712 inst
.operands
[i
].present
= 1;
6714 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6716 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6719 /* Cases 0, 1, 2, 3, 5 (D only). */
6720 if (skip_past_comma (&ptr
) == FAIL
)
6723 inst
.operands
[i
].reg
= val
;
6724 inst
.operands
[i
].isreg
= 1;
6725 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6726 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6727 inst
.operands
[i
].isvec
= 1;
6728 inst
.operands
[i
].vectype
= optype
;
6729 inst
.operands
[i
++].present
= 1;
6731 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6733 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6734 Case 13: VMOV <Sd>, <Rm> */
6735 inst
.operands
[i
].reg
= val
;
6736 inst
.operands
[i
].isreg
= 1;
6737 inst
.operands
[i
].present
= 1;
6739 if (rtype
== REG_TYPE_NQ
)
6741 first_error (_("can't use Neon quad register here"));
6744 else if (rtype
!= REG_TYPE_VFS
)
6747 if (skip_past_comma (&ptr
) == FAIL
)
6749 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6751 inst
.operands
[i
].reg
= val
;
6752 inst
.operands
[i
].isreg
= 1;
6753 inst
.operands
[i
].present
= 1;
6756 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6758 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6761 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6762 Case 1: VMOV<c><q> <Dd>, <Dm>
6763 Case 8: VMOV.F32 <Sd>, <Sm>
6764 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6766 inst
.operands
[i
].reg
= val
;
6767 inst
.operands
[i
].isreg
= 1;
6768 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6769 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6770 inst
.operands
[i
].isvec
= 1;
6771 inst
.operands
[i
].vectype
= optype
;
6772 inst
.operands
[i
].present
= 1;
6774 if (skip_past_comma (&ptr
) == SUCCESS
)
6779 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6782 inst
.operands
[i
].reg
= val
;
6783 inst
.operands
[i
].isreg
= 1;
6784 inst
.operands
[i
++].present
= 1;
6786 if (skip_past_comma (&ptr
) == FAIL
)
6789 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6792 inst
.operands
[i
].reg
= val
;
6793 inst
.operands
[i
].isreg
= 1;
6794 inst
.operands
[i
].present
= 1;
6797 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6798 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6799 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6800 Case 10: VMOV.F32 <Sd>, #<imm>
6801 Case 11: VMOV.F64 <Dd>, #<imm> */
6802 inst
.operands
[i
].immisfloat
= 1;
6803 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6805 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6806 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6810 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6814 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6816 /* Cases 6, 7, 16, 18. */
6817 inst
.operands
[i
].reg
= val
;
6818 inst
.operands
[i
].isreg
= 1;
6819 inst
.operands
[i
++].present
= 1;
6821 if (skip_past_comma (&ptr
) == FAIL
)
6824 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6826 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6827 inst
.operands
[i
].reg
= val
;
6828 inst
.operands
[i
].isscalar
= 2;
6829 inst
.operands
[i
].present
= 1;
6830 inst
.operands
[i
].vectype
= optype
;
6832 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6834 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6835 inst
.operands
[i
].reg
= val
;
6836 inst
.operands
[i
].isscalar
= 1;
6837 inst
.operands
[i
].present
= 1;
6838 inst
.operands
[i
].vectype
= optype
;
6840 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6842 inst
.operands
[i
].reg
= val
;
6843 inst
.operands
[i
].isreg
= 1;
6844 inst
.operands
[i
++].present
= 1;
6846 if (skip_past_comma (&ptr
) == FAIL
)
6849 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6852 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6854 inst
.operands
[i
].reg
= val
;
6855 inst
.operands
[i
].isreg
= 1;
6856 inst
.operands
[i
].isvec
= 1;
6857 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6858 inst
.operands
[i
].vectype
= optype
;
6859 inst
.operands
[i
].present
= 1;
6861 if (rtype
== REG_TYPE_VFS
)
6865 if (skip_past_comma (&ptr
) == FAIL
)
6867 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6870 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6873 inst
.operands
[i
].reg
= val
;
6874 inst
.operands
[i
].isreg
= 1;
6875 inst
.operands
[i
].isvec
= 1;
6876 inst
.operands
[i
].issingle
= 1;
6877 inst
.operands
[i
].vectype
= optype
;
6878 inst
.operands
[i
].present
= 1;
6883 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6886 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6887 inst
.operands
[i
].reg
= val
;
6888 inst
.operands
[i
].isvec
= 1;
6889 inst
.operands
[i
].isscalar
= 2;
6890 inst
.operands
[i
].vectype
= optype
;
6891 inst
.operands
[i
++].present
= 1;
6893 if (skip_past_comma (&ptr
) == FAIL
)
6896 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6899 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6902 inst
.operands
[i
].reg
= val
;
6903 inst
.operands
[i
].isvec
= 1;
6904 inst
.operands
[i
].isscalar
= 2;
6905 inst
.operands
[i
].vectype
= optype
;
6906 inst
.operands
[i
].present
= 1;
6910 first_error (_("VFP single, double or MVE vector register"
6916 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6920 inst
.operands
[i
].reg
= val
;
6921 inst
.operands
[i
].isreg
= 1;
6922 inst
.operands
[i
].isvec
= 1;
6923 inst
.operands
[i
].issingle
= 1;
6924 inst
.operands
[i
].vectype
= optype
;
6925 inst
.operands
[i
].present
= 1;
6930 first_error (_("parse error"));
6934 /* Successfully parsed the operands. Update args. */
6940 first_error (_("expected comma"));
6944 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6948 /* Use this macro when the operand constraints are different
6949 for ARM and THUMB (e.g. ldrd). */
6950 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6951 ((arm_operand) | ((thumb_operand) << 16))
6953 /* Matcher codes for parse_operands. */
6954 enum operand_parse_code
6956 OP_stop
, /* end of line */
6958 OP_RR
, /* ARM register */
6959 OP_RRnpc
, /* ARM register, not r15 */
6960 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6961 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6962 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6963 optional trailing ! */
6964 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6965 OP_RCP
, /* Coprocessor number */
6966 OP_RCN
, /* Coprocessor register */
6967 OP_RF
, /* FPA register */
6968 OP_RVS
, /* VFP single precision register */
6969 OP_RVD
, /* VFP double precision register (0..15) */
6970 OP_RND
, /* Neon double precision register (0..31) */
6971 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6972 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6974 OP_RNQ
, /* Neon quad precision register */
6975 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6976 OP_RVSD
, /* VFP single or double precision register */
6977 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6978 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6979 OP_RNSD
, /* Neon single or double precision register */
6980 OP_RNDQ
, /* Neon double or quad precision register */
6981 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6982 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6983 OP_RNSDQ
, /* Neon single, double or quad precision register */
6984 OP_RNSC
, /* Neon scalar D[X] */
6985 OP_RVC
, /* VFP control register */
6986 OP_RMF
, /* Maverick F register */
6987 OP_RMD
, /* Maverick D register */
6988 OP_RMFX
, /* Maverick FX register */
6989 OP_RMDX
, /* Maverick DX register */
6990 OP_RMAX
, /* Maverick AX register */
6991 OP_RMDS
, /* Maverick DSPSC register */
6992 OP_RIWR
, /* iWMMXt wR register */
6993 OP_RIWC
, /* iWMMXt wC register */
6994 OP_RIWG
, /* iWMMXt wCG register */
6995 OP_RXA
, /* XScale accumulator register */
6997 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6999 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7001 OP_RMQ
, /* MVE vector register. */
7002 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7003 OP_RMQRR
, /* MVE vector or ARM register. */
7005 /* New operands for Armv8.1-M Mainline. */
7006 OP_LR
, /* ARM LR register */
7007 OP_RRe
, /* ARM register, only even numbered. */
7008 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7009 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7010 OP_RR_ZR
, /* ARM register or ZR but no PC */
7012 OP_REGLST
, /* ARM register list */
7013 OP_CLRMLST
, /* CLRM register list */
7014 OP_VRSLST
, /* VFP single-precision register list */
7015 OP_VRDLST
, /* VFP double-precision register list */
7016 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7017 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7018 OP_NSTRLST
, /* Neon element/structure list */
7019 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7020 OP_MSTRLST2
, /* MVE vector list with two elements. */
7021 OP_MSTRLST4
, /* MVE vector list with four elements. */
7023 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7024 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7025 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7026 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7028 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7029 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7030 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7031 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7033 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7034 scalar, or ARM register. */
7035 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7036 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7037 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7039 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7040 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7041 OP_VMOV
, /* Neon VMOV operands. */
7042 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7043 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7045 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7046 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7048 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7049 OP_VLDR
, /* VLDR operand. */
7051 OP_I0
, /* immediate zero */
7052 OP_I7
, /* immediate value 0 .. 7 */
7053 OP_I15
, /* 0 .. 15 */
7054 OP_I16
, /* 1 .. 16 */
7055 OP_I16z
, /* 0 .. 16 */
7056 OP_I31
, /* 0 .. 31 */
7057 OP_I31w
, /* 0 .. 31, optional trailing ! */
7058 OP_I32
, /* 1 .. 32 */
7059 OP_I32z
, /* 0 .. 32 */
7060 OP_I48_I64
, /* 48 or 64 */
7061 OP_I63
, /* 0 .. 63 */
7062 OP_I63s
, /* -64 .. 63 */
7063 OP_I64
, /* 1 .. 64 */
7064 OP_I64z
, /* 0 .. 64 */
7065 OP_I255
, /* 0 .. 255 */
7067 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7068 OP_I7b
, /* 0 .. 7 */
7069 OP_I15b
, /* 0 .. 15 */
7070 OP_I31b
, /* 0 .. 31 */
7072 OP_SH
, /* shifter operand */
7073 OP_SHG
, /* shifter operand with possible group relocation */
7074 OP_ADDR
, /* Memory address expression (any mode) */
7075 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7076 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7077 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7078 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7079 OP_EXP
, /* arbitrary expression */
7080 OP_EXPi
, /* same, with optional immediate prefix */
7081 OP_EXPr
, /* same, with optional relocation suffix */
7082 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7083 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7084 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7085 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7087 OP_CPSF
, /* CPS flags */
7088 OP_ENDI
, /* Endianness specifier */
7089 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7090 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7091 OP_COND
, /* conditional code */
7092 OP_TB
, /* Table branch. */
7094 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7096 OP_RRnpc_I0
, /* ARM register or literal 0 */
7097 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7098 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7099 OP_RF_IF
, /* FPA register or immediate */
7100 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7101 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7103 /* Optional operands. */
7104 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7105 OP_oI31b
, /* 0 .. 31 */
7106 OP_oI32b
, /* 1 .. 32 */
7107 OP_oI32z
, /* 0 .. 32 */
7108 OP_oIffffb
, /* 0 .. 65535 */
7109 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7111 OP_oRR
, /* ARM register */
7112 OP_oLR
, /* ARM LR register */
7113 OP_oRRnpc
, /* ARM register, not the PC */
7114 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7115 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7116 OP_oRND
, /* Optional Neon double precision register */
7117 OP_oRNQ
, /* Optional Neon quad precision register */
7118 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7119 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7120 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7121 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7123 OP_oSHll
, /* LSL immediate */
7124 OP_oSHar
, /* ASR immediate */
7125 OP_oSHllar
, /* LSL or ASR immediate */
7126 OP_oROR
, /* ROR 0/8/16/24 */
7127 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7129 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7131 /* Some pre-defined mixed (ARM/THUMB) operands. */
7132 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7133 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7134 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7136 OP_FIRST_OPTIONAL
= OP_oI7b
7139 /* Generic instruction operand parser. This does no encoding and no
7140 semantic validation; it merely squirrels values away in the inst
7141 structure. Returns SUCCESS or FAIL depending on whether the
7142 specified grammar matched. */
7144 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7146 unsigned const int *upat
= pattern
;
7147 char *backtrack_pos
= 0;
7148 const char *backtrack_error
= 0;
7149 int i
, val
= 0, backtrack_index
= 0;
7150 enum arm_reg_type rtype
;
7151 parse_operand_result result
;
7152 unsigned int op_parse_code
;
7153 bfd_boolean partial_match
;
7155 #define po_char_or_fail(chr) \
7158 if (skip_past_char (&str, chr) == FAIL) \
7163 #define po_reg_or_fail(regtype) \
7166 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7167 & inst.operands[i].vectype); \
7170 first_error (_(reg_expected_msgs[regtype])); \
7173 inst.operands[i].reg = val; \
7174 inst.operands[i].isreg = 1; \
7175 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7176 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7177 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7178 || rtype == REG_TYPE_VFD \
7179 || rtype == REG_TYPE_NQ); \
7180 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7184 #define po_reg_or_goto(regtype, label) \
7187 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7188 & inst.operands[i].vectype); \
7192 inst.operands[i].reg = val; \
7193 inst.operands[i].isreg = 1; \
7194 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7195 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7196 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7197 || rtype == REG_TYPE_VFD \
7198 || rtype == REG_TYPE_NQ); \
7199 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7203 #define po_imm_or_fail(min, max, popt) \
7206 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7208 inst.operands[i].imm = val; \
7212 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7216 my_get_expression (&exp, &str, popt); \
7217 if (exp.X_op != O_constant) \
7219 inst.error = _("constant expression required"); \
7222 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7224 inst.error = _("immediate value 48 or 64 expected"); \
7227 inst.operands[i].imm = exp.X_add_number; \
7231 #define po_scalar_or_goto(elsz, label, reg_type) \
7234 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7238 inst.operands[i].reg = val; \
7239 inst.operands[i].isscalar = 1; \
7243 #define po_misc_or_fail(expr) \
7251 #define po_misc_or_fail_no_backtrack(expr) \
7255 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7256 backtrack_pos = 0; \
7257 if (result != PARSE_OPERAND_SUCCESS) \
7262 #define po_barrier_or_imm(str) \
7265 val = parse_barrier (&str); \
7266 if (val == FAIL && ! ISALPHA (*str)) \
7269 /* ISB can only take SY as an option. */ \
7270 || ((inst.instruction & 0xf0) == 0x60 \
7273 inst.error = _("invalid barrier type"); \
7274 backtrack_pos = 0; \
7280 skip_whitespace (str
);
7282 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7284 op_parse_code
= upat
[i
];
7285 if (op_parse_code
>= 1<<16)
7286 op_parse_code
= thumb
? (op_parse_code
>> 16)
7287 : (op_parse_code
& ((1<<16)-1));
7289 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7291 /* Remember where we are in case we need to backtrack. */
7292 backtrack_pos
= str
;
7293 backtrack_error
= inst
.error
;
7294 backtrack_index
= i
;
7297 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7298 po_char_or_fail (',');
7300 switch (op_parse_code
)
7312 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7313 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7314 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7315 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7316 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7317 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7320 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7324 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7327 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7329 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7331 /* Also accept generic coprocessor regs for unknown registers. */
7333 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7335 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7336 existing register with a value of 0, this seems like the
7337 best way to parse P0. */
7339 if (strncasecmp (str
, "P0", 2) == 0)
7342 inst
.operands
[i
].isreg
= 1;
7343 inst
.operands
[i
].reg
= 13;
7348 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7349 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7350 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7351 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7352 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7353 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7354 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7355 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7356 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7357 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7360 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7363 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7364 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7366 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7371 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7375 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7377 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7380 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7382 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7385 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7387 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7392 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7395 po_reg_or_fail (REG_TYPE_NSDQ
);
7399 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7403 po_reg_or_fail (REG_TYPE_MQ
);
7405 /* Neon scalar. Using an element size of 8 means that some invalid
7406 scalars are accepted here, so deal with those in later code. */
7407 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7411 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7414 po_imm_or_fail (0, 0, TRUE
);
7419 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7423 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7428 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7431 if (parse_ifimm_zero (&str
))
7432 inst
.operands
[i
].imm
= 0;
7436 = _("only floating point zero is allowed as immediate value");
7444 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7447 po_reg_or_fail (REG_TYPE_RN
);
7451 case OP_RNSDQ_RNSC_MQ_RR
:
7452 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7455 case OP_RNSDQ_RNSC_MQ
:
7456 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7461 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7465 po_reg_or_fail (REG_TYPE_NSDQ
);
7472 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7475 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7478 po_reg_or_fail (REG_TYPE_NSD
);
7482 case OP_RNDQMQ_RNSC_RR
:
7483 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7486 case OP_RNDQ_RNSC_RR
:
7487 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7489 case OP_RNDQMQ_RNSC
:
7490 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7495 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7498 po_reg_or_fail (REG_TYPE_NDQ
);
7504 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7507 po_reg_or_fail (REG_TYPE_VFD
);
7512 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7513 not careful then bad things might happen. */
7514 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7517 case OP_RNDQMQ_Ibig
:
7518 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7523 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7526 /* There's a possibility of getting a 64-bit immediate here, so
7527 we need special handling. */
7528 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7531 inst
.error
= _("immediate value is out of range");
7537 case OP_RNDQMQ_I63b_RR
:
7538 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7541 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7546 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7549 po_imm_or_fail (0, 63, TRUE
);
7554 po_char_or_fail ('[');
7555 po_reg_or_fail (REG_TYPE_RN
);
7556 po_char_or_fail (']');
7562 po_reg_or_fail (REG_TYPE_RN
);
7563 if (skip_past_char (&str
, '!') == SUCCESS
)
7564 inst
.operands
[i
].writeback
= 1;
7568 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7569 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7570 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7571 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7572 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7573 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7574 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7575 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7576 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7577 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7578 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7579 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7580 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7582 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7584 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7585 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7587 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7588 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7589 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7590 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7592 /* Immediate variants */
7594 po_char_or_fail ('{');
7595 po_imm_or_fail (0, 255, TRUE
);
7596 po_char_or_fail ('}');
7600 /* The expression parser chokes on a trailing !, so we have
7601 to find it first and zap it. */
7604 while (*s
&& *s
!= ',')
7609 inst
.operands
[i
].writeback
= 1;
7611 po_imm_or_fail (0, 31, TRUE
);
7619 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7624 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7629 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7631 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7633 val
= parse_reloc (&str
);
7636 inst
.error
= _("unrecognized relocation suffix");
7639 else if (val
!= BFD_RELOC_UNUSED
)
7641 inst
.operands
[i
].imm
= val
;
7642 inst
.operands
[i
].hasreloc
= 1;
7648 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7650 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7652 inst
.operands
[i
].hasreloc
= 1;
7654 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7656 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7657 inst
.operands
[i
].hasreloc
= 0;
7661 /* Operand for MOVW or MOVT. */
7663 po_misc_or_fail (parse_half (&str
));
7666 /* Register or expression. */
7667 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7668 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7670 /* Register or immediate. */
7671 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7672 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7674 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7675 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7677 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7679 if (!is_immediate_prefix (*str
))
7682 val
= parse_fpa_immediate (&str
);
7685 /* FPA immediates are encoded as registers 8-15.
7686 parse_fpa_immediate has already applied the offset. */
7687 inst
.operands
[i
].reg
= val
;
7688 inst
.operands
[i
].isreg
= 1;
7691 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7692 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7694 /* Two kinds of register. */
7697 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7699 || (rege
->type
!= REG_TYPE_MMXWR
7700 && rege
->type
!= REG_TYPE_MMXWC
7701 && rege
->type
!= REG_TYPE_MMXWCG
))
7703 inst
.error
= _("iWMMXt data or control register expected");
7706 inst
.operands
[i
].reg
= rege
->number
;
7707 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7713 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7715 || (rege
->type
!= REG_TYPE_MMXWC
7716 && rege
->type
!= REG_TYPE_MMXWCG
))
7718 inst
.error
= _("iWMMXt control register expected");
7721 inst
.operands
[i
].reg
= rege
->number
;
7722 inst
.operands
[i
].isreg
= 1;
7727 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7728 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7729 case OP_oROR
: val
= parse_ror (&str
); break;
7731 case OP_COND
: val
= parse_cond (&str
); break;
7732 case OP_oBARRIER_I15
:
7733 po_barrier_or_imm (str
); break;
7735 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7741 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7742 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7744 inst
.error
= _("Banked registers are not available with this "
7750 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7754 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7757 val
= parse_sys_vldr_vstr (&str
);
7761 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7764 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7766 if (strncasecmp (str
, "APSR_", 5) == 0)
7773 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7774 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7775 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7776 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7777 default: found
= 16;
7781 inst
.operands
[i
].isvec
= 1;
7782 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7783 inst
.operands
[i
].reg
= REG_PC
;
7790 po_misc_or_fail (parse_tb (&str
));
7793 /* Register lists. */
7795 val
= parse_reg_list (&str
, REGLIST_RN
);
7798 inst
.operands
[i
].writeback
= 1;
7804 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7808 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7813 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7818 /* Allow Q registers too. */
7819 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7820 REGLIST_NEON_D
, &partial_match
);
7824 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7825 REGLIST_VFP_S
, &partial_match
);
7826 inst
.operands
[i
].issingle
= 1;
7831 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7832 REGLIST_VFP_D_VPR
, &partial_match
);
7833 if (val
== FAIL
&& !partial_match
)
7836 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7837 REGLIST_VFP_S_VPR
, &partial_match
);
7838 inst
.operands
[i
].issingle
= 1;
7843 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7844 REGLIST_NEON_D
, &partial_match
);
7849 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7850 1, &inst
.operands
[i
].vectype
);
7851 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7855 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7856 0, &inst
.operands
[i
].vectype
);
7859 /* Addressing modes */
7861 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7865 po_misc_or_fail (parse_address (&str
, i
));
7869 po_misc_or_fail_no_backtrack (
7870 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7874 po_misc_or_fail_no_backtrack (
7875 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7879 po_misc_or_fail_no_backtrack (
7880 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7884 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7888 po_misc_or_fail_no_backtrack (
7889 parse_shifter_operand_group_reloc (&str
, i
));
7893 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7897 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7901 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7906 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7911 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7914 po_reg_or_fail (REG_TYPE_ZR
);
7918 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7921 /* Various value-based sanity checks and shared operations. We
7922 do not signal immediate failures for the register constraints;
7923 this allows a syntax error to take precedence. */
7924 switch (op_parse_code
)
7932 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7933 inst
.error
= BAD_PC
;
7938 case OP_RRnpcsp_I32
:
7939 if (inst
.operands
[i
].isreg
)
7941 if (inst
.operands
[i
].reg
== REG_PC
)
7942 inst
.error
= BAD_PC
;
7943 else if (inst
.operands
[i
].reg
== REG_SP
7944 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7945 relaxed since ARMv8-A. */
7946 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7949 inst
.error
= BAD_SP
;
7955 if (inst
.operands
[i
].isreg
7956 && inst
.operands
[i
].reg
== REG_PC
7957 && (inst
.operands
[i
].writeback
|| thumb
))
7958 inst
.error
= BAD_PC
;
7963 if (inst
.operands
[i
].isreg
)
7973 case OP_oBARRIER_I15
:
7986 inst
.operands
[i
].imm
= val
;
7991 if (inst
.operands
[i
].reg
!= REG_LR
)
7992 inst
.error
= _("operand must be LR register");
7998 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7999 inst
.error
= BAD_PC
;
8003 if (inst
.operands
[i
].isreg
8004 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8005 inst
.error
= BAD_ODD
;
8009 if (inst
.operands
[i
].isreg
)
8011 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8012 inst
.error
= BAD_EVEN
;
8013 else if (inst
.operands
[i
].reg
== REG_SP
)
8014 as_tsktsk (MVE_BAD_SP
);
8015 else if (inst
.operands
[i
].reg
== REG_PC
)
8016 inst
.error
= BAD_PC
;
8024 /* If we get here, this operand was successfully parsed. */
8025 inst
.operands
[i
].present
= 1;
8029 inst
.error
= BAD_ARGS
;
8034 /* The parse routine should already have set inst.error, but set a
8035 default here just in case. */
8037 inst
.error
= BAD_SYNTAX
;
8041 /* Do not backtrack over a trailing optional argument that
8042 absorbed some text. We will only fail again, with the
8043 'garbage following instruction' error message, which is
8044 probably less helpful than the current one. */
8045 if (backtrack_index
== i
&& backtrack_pos
!= str
8046 && upat
[i
+1] == OP_stop
)
8049 inst
.error
= BAD_SYNTAX
;
8053 /* Try again, skipping the optional argument at backtrack_pos. */
8054 str
= backtrack_pos
;
8055 inst
.error
= backtrack_error
;
8056 inst
.operands
[backtrack_index
].present
= 0;
8057 i
= backtrack_index
;
8061 /* Check that we have parsed all the arguments. */
8062 if (*str
!= '\0' && !inst
.error
)
8063 inst
.error
= _("garbage following instruction");
8065 return inst
.error
? FAIL
: SUCCESS
;
8068 #undef po_char_or_fail
8069 #undef po_reg_or_fail
8070 #undef po_reg_or_goto
8071 #undef po_imm_or_fail
8072 #undef po_scalar_or_fail
8073 #undef po_barrier_or_imm
8075 /* Shorthand macro for instruction encoding functions issuing errors. */
8076 #define constraint(expr, err) \
8087 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8088 instructions are unpredictable if these registers are used. This
8089 is the BadReg predicate in ARM's Thumb-2 documentation.
8091 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8092 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8093 #define reject_bad_reg(reg) \
8095 if (reg == REG_PC) \
8097 inst.error = BAD_PC; \
8100 else if (reg == REG_SP \
8101 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8103 inst.error = BAD_SP; \
8108 /* If REG is R13 (the stack pointer), warn that its use is
8110 #define warn_deprecated_sp(reg) \
8112 if (warn_on_deprecated && reg == REG_SP) \
8113 as_tsktsk (_("use of r13 is deprecated")); \
8116 /* Functions for operand encoding. ARM, then Thumb. */
8118 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8120 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8122 The only binary encoding difference is the Coprocessor number. Coprocessor
8123 9 is used for half-precision calculations or conversions. The format of the
8124 instruction is the same as the equivalent Coprocessor 10 instruction that
8125 exists for Single-Precision operation. */
8128 do_scalar_fp16_v82_encode (void)
8130 if (inst
.cond
< COND_ALWAYS
)
8131 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8132 " the behaviour is UNPREDICTABLE"));
8133 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8136 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8137 mark_feature_used (&arm_ext_fp16
);
8140 /* If VAL can be encoded in the immediate field of an ARM instruction,
8141 return the encoded form. Otherwise, return FAIL. */
8144 encode_arm_immediate (unsigned int val
)
8151 for (i
= 2; i
< 32; i
+= 2)
8152 if ((a
= rotate_left (val
, i
)) <= 0xff)
8153 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8158 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8159 return the encoded form. Otherwise, return FAIL. */
8161 encode_thumb32_immediate (unsigned int val
)
8168 for (i
= 1; i
<= 24; i
++)
8171 if ((val
& ~(0xff << i
)) == 0)
8172 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8176 if (val
== ((a
<< 16) | a
))
8178 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8182 if (val
== ((a
<< 16) | a
))
8183 return 0x200 | (a
>> 8);
8187 /* Encode a VFP SP or DP register number into inst.instruction. */
8190 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8192 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8195 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8198 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8201 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8206 first_error (_("D register out of range for selected VFP version"));
8214 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8218 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8222 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8226 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8230 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8234 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8242 /* Encode a <shift> in an ARM-format instruction. The immediate,
8243 if any, is handled by md_apply_fix. */
8245 encode_arm_shift (int i
)
8247 /* register-shifted register. */
8248 if (inst
.operands
[i
].immisreg
)
8251 for (op_index
= 0; op_index
<= i
; ++op_index
)
8253 /* Check the operand only when it's presented. In pre-UAL syntax,
8254 if the destination register is the same as the first operand, two
8255 register form of the instruction can be used. */
8256 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8257 && inst
.operands
[op_index
].reg
== REG_PC
)
8258 as_warn (UNPRED_REG ("r15"));
8261 if (inst
.operands
[i
].imm
== REG_PC
)
8262 as_warn (UNPRED_REG ("r15"));
8265 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8266 inst
.instruction
|= SHIFT_ROR
<< 5;
8269 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8270 if (inst
.operands
[i
].immisreg
)
8272 inst
.instruction
|= SHIFT_BY_REG
;
8273 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8276 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8281 encode_arm_shifter_operand (int i
)
8283 if (inst
.operands
[i
].isreg
)
8285 inst
.instruction
|= inst
.operands
[i
].reg
;
8286 encode_arm_shift (i
);
8290 inst
.instruction
|= INST_IMMEDIATE
;
8291 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8292 inst
.instruction
|= inst
.operands
[i
].imm
;
8296 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8298 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8301 Generate an error if the operand is not a register. */
8302 constraint (!inst
.operands
[i
].isreg
,
8303 _("Instruction does not support =N addresses"));
8305 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8307 if (inst
.operands
[i
].preind
)
8311 inst
.error
= _("instruction does not accept preindexed addressing");
8314 inst
.instruction
|= PRE_INDEX
;
8315 if (inst
.operands
[i
].writeback
)
8316 inst
.instruction
|= WRITE_BACK
;
8319 else if (inst
.operands
[i
].postind
)
8321 gas_assert (inst
.operands
[i
].writeback
);
8323 inst
.instruction
|= WRITE_BACK
;
8325 else /* unindexed - only for coprocessor */
8327 inst
.error
= _("instruction does not accept unindexed addressing");
8331 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8332 && (((inst
.instruction
& 0x000f0000) >> 16)
8333 == ((inst
.instruction
& 0x0000f000) >> 12)))
8334 as_warn ((inst
.instruction
& LOAD_BIT
)
8335 ? _("destination register same as write-back base")
8336 : _("source register same as write-back base"));
8339 /* inst.operands[i] was set up by parse_address. Encode it into an
8340 ARM-format mode 2 load or store instruction. If is_t is true,
8341 reject forms that cannot be used with a T instruction (i.e. not
8344 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8346 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8348 encode_arm_addr_mode_common (i
, is_t
);
8350 if (inst
.operands
[i
].immisreg
)
8352 constraint ((inst
.operands
[i
].imm
== REG_PC
8353 || (is_pc
&& inst
.operands
[i
].writeback
)),
8355 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8356 inst
.instruction
|= inst
.operands
[i
].imm
;
8357 if (!inst
.operands
[i
].negative
)
8358 inst
.instruction
|= INDEX_UP
;
8359 if (inst
.operands
[i
].shifted
)
8361 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8362 inst
.instruction
|= SHIFT_ROR
<< 5;
8365 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8366 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8370 else /* immediate offset in inst.relocs[0] */
8372 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8374 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8376 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8377 cannot use PC in addressing.
8378 PC cannot be used in writeback addressing, either. */
8379 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8382 /* Use of PC in str is deprecated for ARMv7. */
8383 if (warn_on_deprecated
8385 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8386 as_tsktsk (_("use of PC in this instruction is deprecated"));
8389 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8391 /* Prefer + for zero encoded value. */
8392 if (!inst
.operands
[i
].negative
)
8393 inst
.instruction
|= INDEX_UP
;
8394 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8399 /* inst.operands[i] was set up by parse_address. Encode it into an
8400 ARM-format mode 3 load or store instruction. Reject forms that
8401 cannot be used with such instructions. If is_t is true, reject
8402 forms that cannot be used with a T instruction (i.e. not
8405 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8407 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8409 inst
.error
= _("instruction does not accept scaled register index");
8413 encode_arm_addr_mode_common (i
, is_t
);
8415 if (inst
.operands
[i
].immisreg
)
8417 constraint ((inst
.operands
[i
].imm
== REG_PC
8418 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8420 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8422 inst
.instruction
|= inst
.operands
[i
].imm
;
8423 if (!inst
.operands
[i
].negative
)
8424 inst
.instruction
|= INDEX_UP
;
8426 else /* immediate offset in inst.relocs[0] */
8428 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8429 && inst
.operands
[i
].writeback
),
8431 inst
.instruction
|= HWOFFSET_IMM
;
8432 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8434 /* Prefer + for zero encoded value. */
8435 if (!inst
.operands
[i
].negative
)
8436 inst
.instruction
|= INDEX_UP
;
8438 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8443 /* Write immediate bits [7:0] to the following locations:
8445 |28/24|23 19|18 16|15 4|3 0|
8446 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8448 This function is used by VMOV/VMVN/VORR/VBIC. */
8451 neon_write_immbits (unsigned immbits
)
8453 inst
.instruction
|= immbits
& 0xf;
8454 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8455 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8458 /* Invert low-order SIZE bits of XHI:XLO. */
8461 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8463 unsigned immlo
= xlo
? *xlo
: 0;
8464 unsigned immhi
= xhi
? *xhi
: 0;
8469 immlo
= (~immlo
) & 0xff;
8473 immlo
= (~immlo
) & 0xffff;
8477 immhi
= (~immhi
) & 0xffffffff;
8481 immlo
= (~immlo
) & 0xffffffff;
8495 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8499 neon_bits_same_in_bytes (unsigned imm
)
8501 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8502 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8503 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8504 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8507 /* For immediate of above form, return 0bABCD. */
8510 neon_squash_bits (unsigned imm
)
8512 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8513 | ((imm
& 0x01000000) >> 21);
8516 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8519 neon_qfloat_bits (unsigned imm
)
8521 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8524 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8525 the instruction. *OP is passed as the initial value of the op field, and
8526 may be set to a different value depending on the constant (i.e.
8527 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8528 MVN). If the immediate looks like a repeated pattern then also
8529 try smaller element sizes. */
8532 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8533 unsigned *immbits
, int *op
, int size
,
8534 enum neon_el_type type
)
8536 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8538 if (type
== NT_float
&& !float_p
)
8541 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8543 if (size
!= 32 || *op
== 1)
8545 *immbits
= neon_qfloat_bits (immlo
);
8551 if (neon_bits_same_in_bytes (immhi
)
8552 && neon_bits_same_in_bytes (immlo
))
8556 *immbits
= (neon_squash_bits (immhi
) << 4)
8557 | neon_squash_bits (immlo
);
8568 if (immlo
== (immlo
& 0x000000ff))
8573 else if (immlo
== (immlo
& 0x0000ff00))
8575 *immbits
= immlo
>> 8;
8578 else if (immlo
== (immlo
& 0x00ff0000))
8580 *immbits
= immlo
>> 16;
8583 else if (immlo
== (immlo
& 0xff000000))
8585 *immbits
= immlo
>> 24;
8588 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8590 *immbits
= (immlo
>> 8) & 0xff;
8593 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8595 *immbits
= (immlo
>> 16) & 0xff;
8599 if ((immlo
& 0xffff) != (immlo
>> 16))
8606 if (immlo
== (immlo
& 0x000000ff))
8611 else if (immlo
== (immlo
& 0x0000ff00))
8613 *immbits
= immlo
>> 8;
8617 if ((immlo
& 0xff) != (immlo
>> 8))
8622 if (immlo
== (immlo
& 0x000000ff))
8624 /* Don't allow MVN with 8-bit immediate. */
8634 #if defined BFD_HOST_64_BIT
8635 /* Returns TRUE if double precision value V may be cast
8636 to single precision without loss of accuracy. */
8639 is_double_a_single (bfd_int64_t v
)
8641 int exp
= (int)((v
>> 52) & 0x7FF);
8642 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8644 return (exp
== 0 || exp
== 0x7FF
8645 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8646 && (mantissa
& 0x1FFFFFFFl
) == 0;
8649 /* Returns a double precision value casted to single precision
8650 (ignoring the least significant bits in exponent and mantissa). */
8653 double_to_single (bfd_int64_t v
)
8655 int sign
= (int) ((v
>> 63) & 1l);
8656 int exp
= (int) ((v
>> 52) & 0x7FF);
8657 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8663 exp
= exp
- 1023 + 127;
8672 /* No denormalized numbers. */
8678 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8680 #endif /* BFD_HOST_64_BIT */
8689 static void do_vfp_nsyn_opcode (const char *);
8691 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8692 Determine whether it can be performed with a move instruction; if
8693 it can, convert inst.instruction to that move instruction and
8694 return TRUE; if it can't, convert inst.instruction to a literal-pool
8695 load and return FALSE. If this is not a valid thing to do in the
8696 current context, set inst.error and return TRUE.
8698 inst.operands[i] describes the destination register. */
8701 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8704 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8705 bfd_boolean arm_p
= (t
== CONST_ARM
);
8708 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8712 if ((inst
.instruction
& tbit
) == 0)
8714 inst
.error
= _("invalid pseudo operation");
8718 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8719 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8720 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8722 inst
.error
= _("constant expression expected");
8726 if (inst
.relocs
[0].exp
.X_op
== O_constant
8727 || inst
.relocs
[0].exp
.X_op
== O_big
)
8729 #if defined BFD_HOST_64_BIT
8734 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8736 LITTLENUM_TYPE w
[X_PRECISION
];
8739 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8741 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8743 /* FIXME: Should we check words w[2..5] ? */
8748 #if defined BFD_HOST_64_BIT
8750 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8751 << LITTLENUM_NUMBER_OF_BITS
)
8752 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8753 << LITTLENUM_NUMBER_OF_BITS
)
8754 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8755 << LITTLENUM_NUMBER_OF_BITS
)
8756 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8758 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8759 | (l
[0] & LITTLENUM_MASK
);
8763 v
= inst
.relocs
[0].exp
.X_add_number
;
8765 if (!inst
.operands
[i
].issingle
)
8769 /* LDR should not use lead in a flag-setting instruction being
8770 chosen so we do not check whether movs can be used. */
8772 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8773 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8774 && inst
.operands
[i
].reg
!= 13
8775 && inst
.operands
[i
].reg
!= 15)
8777 /* Check if on thumb2 it can be done with a mov.w, mvn or
8778 movw instruction. */
8779 unsigned int newimm
;
8780 bfd_boolean isNegated
;
8782 newimm
= encode_thumb32_immediate (v
);
8783 if (newimm
!= (unsigned int) FAIL
)
8787 newimm
= encode_thumb32_immediate (~v
);
8788 if (newimm
!= (unsigned int) FAIL
)
8792 /* The number can be loaded with a mov.w or mvn
8794 if (newimm
!= (unsigned int) FAIL
8795 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8797 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8798 | (inst
.operands
[i
].reg
<< 8));
8799 /* Change to MOVN. */
8800 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8801 inst
.instruction
|= (newimm
& 0x800) << 15;
8802 inst
.instruction
|= (newimm
& 0x700) << 4;
8803 inst
.instruction
|= (newimm
& 0x0ff);
8806 /* The number can be loaded with a movw instruction. */
8807 else if ((v
& ~0xFFFF) == 0
8808 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8810 int imm
= v
& 0xFFFF;
8812 inst
.instruction
= 0xf2400000; /* MOVW. */
8813 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8814 inst
.instruction
|= (imm
& 0xf000) << 4;
8815 inst
.instruction
|= (imm
& 0x0800) << 15;
8816 inst
.instruction
|= (imm
& 0x0700) << 4;
8817 inst
.instruction
|= (imm
& 0x00ff);
8818 /* In case this replacement is being done on Armv8-M
8819 Baseline we need to make sure to disable the
8820 instruction size check, as otherwise GAS will reject
8821 the use of this T32 instruction. */
8829 int value
= encode_arm_immediate (v
);
8833 /* This can be done with a mov instruction. */
8834 inst
.instruction
&= LITERAL_MASK
;
8835 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8836 inst
.instruction
|= value
& 0xfff;
8840 value
= encode_arm_immediate (~ v
);
8843 /* This can be done with a mvn instruction. */
8844 inst
.instruction
&= LITERAL_MASK
;
8845 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8846 inst
.instruction
|= value
& 0xfff;
8850 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8853 unsigned immbits
= 0;
8854 unsigned immlo
= inst
.operands
[1].imm
;
8855 unsigned immhi
= inst
.operands
[1].regisimm
8856 ? inst
.operands
[1].reg
8857 : inst
.relocs
[0].exp
.X_unsigned
8859 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8860 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8861 &op
, 64, NT_invtype
);
8865 neon_invert_size (&immlo
, &immhi
, 64);
8867 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8868 &op
, 64, NT_invtype
);
8873 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8879 /* Fill other bits in vmov encoding for both thumb and arm. */
8881 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8883 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8884 neon_write_immbits (immbits
);
8892 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8893 if (inst
.operands
[i
].issingle
8894 && is_quarter_float (inst
.operands
[1].imm
)
8895 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8897 inst
.operands
[1].imm
=
8898 neon_qfloat_bits (v
);
8899 do_vfp_nsyn_opcode ("fconsts");
8903 /* If our host does not support a 64-bit type then we cannot perform
8904 the following optimization. This mean that there will be a
8905 discrepancy between the output produced by an assembler built for
8906 a 32-bit-only host and the output produced from a 64-bit host, but
8907 this cannot be helped. */
8908 #if defined BFD_HOST_64_BIT
8909 else if (!inst
.operands
[1].issingle
8910 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8912 if (is_double_a_single (v
)
8913 && is_quarter_float (double_to_single (v
)))
8915 inst
.operands
[1].imm
=
8916 neon_qfloat_bits (double_to_single (v
));
8917 do_vfp_nsyn_opcode ("fconstd");
8925 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8926 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8929 inst
.operands
[1].reg
= REG_PC
;
8930 inst
.operands
[1].isreg
= 1;
8931 inst
.operands
[1].preind
= 1;
8932 inst
.relocs
[0].pc_rel
= 1;
8933 inst
.relocs
[0].type
= (thumb_p
8934 ? BFD_RELOC_ARM_THUMB_OFFSET
8936 ? BFD_RELOC_ARM_HWLITERAL
8937 : BFD_RELOC_ARM_LITERAL
));
8941 /* inst.operands[i] was set up by parse_address. Encode it into an
8942 ARM-format instruction. Reject all forms which cannot be encoded
8943 into a coprocessor load/store instruction. If wb_ok is false,
8944 reject use of writeback; if unind_ok is false, reject use of
8945 unindexed addressing. If reloc_override is not 0, use it instead
8946 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8947 (in which case it is preserved). */
8950 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8952 if (!inst
.operands
[i
].isreg
)
8955 if (! inst
.operands
[0].isvec
)
8957 inst
.error
= _("invalid co-processor operand");
8960 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8964 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8966 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8968 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8970 gas_assert (!inst
.operands
[i
].writeback
);
8973 inst
.error
= _("instruction does not support unindexed addressing");
8976 inst
.instruction
|= inst
.operands
[i
].imm
;
8977 inst
.instruction
|= INDEX_UP
;
8981 if (inst
.operands
[i
].preind
)
8982 inst
.instruction
|= PRE_INDEX
;
8984 if (inst
.operands
[i
].writeback
)
8986 if (inst
.operands
[i
].reg
== REG_PC
)
8988 inst
.error
= _("pc may not be used with write-back");
8993 inst
.error
= _("instruction does not support writeback");
8996 inst
.instruction
|= WRITE_BACK
;
9000 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9001 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9002 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9003 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9006 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9008 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9011 /* Prefer + for zero encoded value. */
9012 if (!inst
.operands
[i
].negative
)
9013 inst
.instruction
|= INDEX_UP
;
9018 /* Functions for instruction encoding, sorted by sub-architecture.
9019 First some generics; their names are taken from the conventional
9020 bit positions for register arguments in ARM format instructions. */
9030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9036 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9042 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9043 inst
.instruction
|= inst
.operands
[1].reg
;
9049 inst
.instruction
|= inst
.operands
[0].reg
;
9050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9057 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9063 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9064 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9070 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9071 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9075 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9077 if (ARM_CPU_IS_ANY (cpu_variant
))
9079 as_tsktsk ("%s", msg
);
9082 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9094 unsigned Rn
= inst
.operands
[2].reg
;
9095 /* Enforce restrictions on SWP instruction. */
9096 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9098 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9099 _("Rn must not overlap other operands"));
9101 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9103 if (!check_obsolete (&arm_ext_v8
,
9104 _("swp{b} use is obsoleted for ARMv8 and later"))
9105 && warn_on_deprecated
9106 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9107 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9111 inst
.instruction
|= inst
.operands
[1].reg
;
9112 inst
.instruction
|= Rn
<< 16;
9118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9120 inst
.instruction
|= inst
.operands
[2].reg
;
9126 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9127 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9128 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9129 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9131 inst
.instruction
|= inst
.operands
[0].reg
;
9132 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9133 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9139 inst
.instruction
|= inst
.operands
[0].imm
;
9145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9146 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9149 /* ARM instructions, in alphabetical order by function name (except
9150 that wrapper functions appear immediately after the function they
9153 /* This is a pseudo-op of the form "adr rd, label" to be converted
9154 into a relative address of the form "add rd, pc, #label-.-8". */
9159 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9161 /* Frag hacking will turn this into a sub instruction if the offset turns
9162 out to be negative. */
9163 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9164 inst
.relocs
[0].pc_rel
= 1;
9165 inst
.relocs
[0].exp
.X_add_number
-= 8;
9167 if (support_interwork
9168 && inst
.relocs
[0].exp
.X_op
== O_symbol
9169 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9170 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9171 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9172 inst
.relocs
[0].exp
.X_add_number
|= 1;
9175 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9176 into a relative address of the form:
9177 add rd, pc, #low(label-.-8)"
9178 add rd, rd, #high(label-.-8)" */
9183 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9185 /* Frag hacking will turn this into a sub instruction if the offset turns
9186 out to be negative. */
9187 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9188 inst
.relocs
[0].pc_rel
= 1;
9189 inst
.size
= INSN_SIZE
* 2;
9190 inst
.relocs
[0].exp
.X_add_number
-= 8;
9192 if (support_interwork
9193 && inst
.relocs
[0].exp
.X_op
== O_symbol
9194 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9195 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9196 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9197 inst
.relocs
[0].exp
.X_add_number
|= 1;
9203 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9204 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9206 if (!inst
.operands
[1].present
)
9207 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9208 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9209 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9210 encode_arm_shifter_operand (2);
9216 if (inst
.operands
[0].present
)
9217 inst
.instruction
|= inst
.operands
[0].imm
;
9219 inst
.instruction
|= 0xf;
9225 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9226 constraint (msb
> 32, _("bit-field extends past end of register"));
9227 /* The instruction encoding stores the LSB and MSB,
9228 not the LSB and width. */
9229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9230 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9231 inst
.instruction
|= (msb
- 1) << 16;
9239 /* #0 in second position is alternative syntax for bfc, which is
9240 the same instruction but with REG_PC in the Rm field. */
9241 if (!inst
.operands
[1].isreg
)
9242 inst
.operands
[1].reg
= REG_PC
;
9244 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9245 constraint (msb
> 32, _("bit-field extends past end of register"));
9246 /* The instruction encoding stores the LSB and MSB,
9247 not the LSB and width. */
9248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9249 inst
.instruction
|= inst
.operands
[1].reg
;
9250 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9251 inst
.instruction
|= (msb
- 1) << 16;
9257 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9258 _("bit-field extends past end of register"));
9259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9260 inst
.instruction
|= inst
.operands
[1].reg
;
9261 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9262 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9265 /* ARM V5 breakpoint instruction (argument parse)
9266 BKPT <16 bit unsigned immediate>
9267 Instruction is not conditional.
9268 The bit pattern given in insns[] has the COND_ALWAYS condition,
9269 and it is an error if the caller tried to override that. */
9274 /* Top 12 of 16 bits to bits 19:8. */
9275 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9277 /* Bottom 4 of 16 bits to bits 3:0. */
9278 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9282 encode_branch (int default_reloc
)
9284 if (inst
.operands
[0].hasreloc
)
9286 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9287 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9288 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9289 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9290 ? BFD_RELOC_ARM_PLT32
9291 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9294 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9295 inst
.relocs
[0].pc_rel
= 1;
9302 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9303 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9306 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9313 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9315 if (inst
.cond
== COND_ALWAYS
)
9316 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9318 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9322 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9325 /* ARM V5 branch-link-exchange instruction (argument parse)
9326 BLX <target_addr> ie BLX(1)
9327 BLX{<condition>} <Rm> ie BLX(2)
9328 Unfortunately, there are two different opcodes for this mnemonic.
9329 So, the insns[].value is not used, and the code here zaps values
9330 into inst.instruction.
9331 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9336 if (inst
.operands
[0].isreg
)
9338 /* Arg is a register; the opcode provided by insns[] is correct.
9339 It is not illegal to do "blx pc", just useless. */
9340 if (inst
.operands
[0].reg
== REG_PC
)
9341 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9343 inst
.instruction
|= inst
.operands
[0].reg
;
9347 /* Arg is an address; this instruction cannot be executed
9348 conditionally, and the opcode must be adjusted.
9349 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9350 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9351 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9352 inst
.instruction
= 0xfa000000;
9353 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9360 bfd_boolean want_reloc
;
9362 if (inst
.operands
[0].reg
== REG_PC
)
9363 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9365 inst
.instruction
|= inst
.operands
[0].reg
;
9366 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9367 it is for ARMv4t or earlier. */
9368 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9369 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9370 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9374 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9379 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9383 /* ARM v5TEJ. Jump to Jazelle code. */
9388 if (inst
.operands
[0].reg
== REG_PC
)
9389 as_tsktsk (_("use of r15 in bxj is not really useful"));
9391 inst
.instruction
|= inst
.operands
[0].reg
;
9394 /* Co-processor data operation:
9395 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9396 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9400 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9401 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9402 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9403 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9404 inst
.instruction
|= inst
.operands
[4].reg
;
9405 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9411 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9412 encode_arm_shifter_operand (1);
9415 /* Transfer between coprocessor and ARM registers.
9416 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9421 No special properties. */
9423 struct deprecated_coproc_regs_s
9430 arm_feature_set deprecated
;
9431 arm_feature_set obsoleted
;
9432 const char *dep_msg
;
9433 const char *obs_msg
;
9436 #define DEPR_ACCESS_V8 \
9437 N_("This coprocessor register access is deprecated in ARMv8")
9439 /* Table of all deprecated coprocessor registers. */
9440 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9442 {15, 0, 7, 10, 5, /* CP15DMB. */
9443 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9444 DEPR_ACCESS_V8
, NULL
},
9445 {15, 0, 7, 10, 4, /* CP15DSB. */
9446 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9447 DEPR_ACCESS_V8
, NULL
},
9448 {15, 0, 7, 5, 4, /* CP15ISB. */
9449 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9450 DEPR_ACCESS_V8
, NULL
},
9451 {14, 6, 1, 0, 0, /* TEEHBR. */
9452 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9453 DEPR_ACCESS_V8
, NULL
},
9454 {14, 6, 0, 0, 0, /* TEECR. */
9455 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9456 DEPR_ACCESS_V8
, NULL
},
9459 #undef DEPR_ACCESS_V8
9461 static const size_t deprecated_coproc_reg_count
=
9462 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9470 Rd
= inst
.operands
[2].reg
;
9473 if (inst
.instruction
== 0xee000010
9474 || inst
.instruction
== 0xfe000010)
9476 reject_bad_reg (Rd
);
9477 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9479 constraint (Rd
== REG_SP
, BAD_SP
);
9484 if (inst
.instruction
== 0xe000010)
9485 constraint (Rd
== REG_PC
, BAD_PC
);
9488 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9490 const struct deprecated_coproc_regs_s
*r
=
9491 deprecated_coproc_regs
+ i
;
9493 if (inst
.operands
[0].reg
== r
->cp
9494 && inst
.operands
[1].imm
== r
->opc1
9495 && inst
.operands
[3].reg
== r
->crn
9496 && inst
.operands
[4].reg
== r
->crm
9497 && inst
.operands
[5].imm
== r
->opc2
)
9499 if (! ARM_CPU_IS_ANY (cpu_variant
)
9500 && warn_on_deprecated
9501 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9502 as_tsktsk ("%s", r
->dep_msg
);
9506 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9507 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9508 inst
.instruction
|= Rd
<< 12;
9509 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9510 inst
.instruction
|= inst
.operands
[4].reg
;
9511 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9514 /* Transfer between coprocessor register and pair of ARM registers.
9515 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9520 Two XScale instructions are special cases of these:
9522 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9523 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9525 Result unpredictable if Rd or Rn is R15. */
9532 Rd
= inst
.operands
[2].reg
;
9533 Rn
= inst
.operands
[3].reg
;
9537 reject_bad_reg (Rd
);
9538 reject_bad_reg (Rn
);
9542 constraint (Rd
== REG_PC
, BAD_PC
);
9543 constraint (Rn
== REG_PC
, BAD_PC
);
9546 /* Only check the MRRC{2} variants. */
9547 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9549 /* If Rd == Rn, error that the operation is
9550 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9551 constraint (Rd
== Rn
, BAD_OVERLAP
);
9554 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9555 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9556 inst
.instruction
|= Rd
<< 12;
9557 inst
.instruction
|= Rn
<< 16;
9558 inst
.instruction
|= inst
.operands
[4].reg
;
9564 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9565 if (inst
.operands
[1].present
)
9567 inst
.instruction
|= CPSI_MMOD
;
9568 inst
.instruction
|= inst
.operands
[1].imm
;
9575 inst
.instruction
|= inst
.operands
[0].imm
;
9581 unsigned Rd
, Rn
, Rm
;
9583 Rd
= inst
.operands
[0].reg
;
9584 Rn
= (inst
.operands
[1].present
9585 ? inst
.operands
[1].reg
: Rd
);
9586 Rm
= inst
.operands
[2].reg
;
9588 constraint ((Rd
== REG_PC
), BAD_PC
);
9589 constraint ((Rn
== REG_PC
), BAD_PC
);
9590 constraint ((Rm
== REG_PC
), BAD_PC
);
9592 inst
.instruction
|= Rd
<< 16;
9593 inst
.instruction
|= Rn
<< 0;
9594 inst
.instruction
|= Rm
<< 8;
9600 /* There is no IT instruction in ARM mode. We
9601 process it to do the validation as if in
9602 thumb mode, just in case the code gets
9603 assembled for thumb using the unified syntax. */
9608 set_pred_insn_type (IT_INSN
);
9609 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9610 now_pred
.cc
= inst
.operands
[0].imm
;
9614 /* If there is only one register in the register list,
9615 then return its register number. Otherwise return -1. */
9617 only_one_reg_in_list (int range
)
9619 int i
= ffs (range
) - 1;
9620 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9624 encode_ldmstm(int from_push_pop_mnem
)
9626 int base_reg
= inst
.operands
[0].reg
;
9627 int range
= inst
.operands
[1].imm
;
9630 inst
.instruction
|= base_reg
<< 16;
9631 inst
.instruction
|= range
;
9633 if (inst
.operands
[1].writeback
)
9634 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9636 if (inst
.operands
[0].writeback
)
9638 inst
.instruction
|= WRITE_BACK
;
9639 /* Check for unpredictable uses of writeback. */
9640 if (inst
.instruction
& LOAD_BIT
)
9642 /* Not allowed in LDM type 2. */
9643 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9644 && ((range
& (1 << REG_PC
)) == 0))
9645 as_warn (_("writeback of base register is UNPREDICTABLE"));
9646 /* Only allowed if base reg not in list for other types. */
9647 else if (range
& (1 << base_reg
))
9648 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9652 /* Not allowed for type 2. */
9653 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9654 as_warn (_("writeback of base register is UNPREDICTABLE"));
9655 /* Only allowed if base reg not in list, or first in list. */
9656 else if ((range
& (1 << base_reg
))
9657 && (range
& ((1 << base_reg
) - 1)))
9658 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9662 /* If PUSH/POP has only one register, then use the A2 encoding. */
9663 one_reg
= only_one_reg_in_list (range
);
9664 if (from_push_pop_mnem
&& one_reg
>= 0)
9666 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9668 if (is_push
&& one_reg
== 13 /* SP */)
9669 /* PR 22483: The A2 encoding cannot be used when
9670 pushing the stack pointer as this is UNPREDICTABLE. */
9673 inst
.instruction
&= A_COND_MASK
;
9674 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9675 inst
.instruction
|= one_reg
<< 12;
9682 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9685 /* ARMv5TE load-consecutive (argument parse)
9694 constraint (inst
.operands
[0].reg
% 2 != 0,
9695 _("first transfer register must be even"));
9696 constraint (inst
.operands
[1].present
9697 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9698 _("can only transfer two consecutive registers"));
9699 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9700 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9702 if (!inst
.operands
[1].present
)
9703 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9705 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9706 register and the first register written; we have to diagnose
9707 overlap between the base and the second register written here. */
9709 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9710 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9711 as_warn (_("base register written back, and overlaps "
9712 "second transfer register"));
9714 if (!(inst
.instruction
& V4_STR_BIT
))
9716 /* For an index-register load, the index register must not overlap the
9717 destination (even if not write-back). */
9718 if (inst
.operands
[2].immisreg
9719 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9720 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9721 as_warn (_("index register overlaps transfer register"));
9723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9724 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9730 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9731 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9732 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9733 || inst
.operands
[1].negative
9734 /* This can arise if the programmer has written
9736 or if they have mistakenly used a register name as the last
9739 It is very difficult to distinguish between these two cases
9740 because "rX" might actually be a label. ie the register
9741 name has been occluded by a symbol of the same name. So we
9742 just generate a general 'bad addressing mode' type error
9743 message and leave it up to the programmer to discover the
9744 true cause and fix their mistake. */
9745 || (inst
.operands
[1].reg
== REG_PC
),
9748 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9749 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9750 _("offset must be zero in ARM encoding"));
9752 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9755 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9756 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9762 constraint (inst
.operands
[0].reg
% 2 != 0,
9763 _("even register required"));
9764 constraint (inst
.operands
[1].present
9765 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9766 _("can only load two consecutive registers"));
9767 /* If op 1 were present and equal to PC, this function wouldn't
9768 have been called in the first place. */
9769 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9771 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9772 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9775 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9776 which is not a multiple of four is UNPREDICTABLE. */
9778 check_ldr_r15_aligned (void)
9780 constraint (!(inst
.operands
[1].immisreg
)
9781 && (inst
.operands
[0].reg
== REG_PC
9782 && inst
.operands
[1].reg
== REG_PC
9783 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9784 _("ldr to register 15 must be 4-byte aligned"));
9790 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9791 if (!inst
.operands
[1].isreg
)
9792 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9794 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9795 check_ldr_r15_aligned ();
9801 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9803 if (inst
.operands
[1].preind
)
9805 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9806 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9807 _("this instruction requires a post-indexed address"));
9809 inst
.operands
[1].preind
= 0;
9810 inst
.operands
[1].postind
= 1;
9811 inst
.operands
[1].writeback
= 1;
9813 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9814 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9817 /* Halfword and signed-byte load/store operations. */
9822 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9823 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9824 if (!inst
.operands
[1].isreg
)
9825 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9827 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9833 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9835 if (inst
.operands
[1].preind
)
9837 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9838 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9839 _("this instruction requires a post-indexed address"));
9841 inst
.operands
[1].preind
= 0;
9842 inst
.operands
[1].postind
= 1;
9843 inst
.operands
[1].writeback
= 1;
9845 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9846 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9849 /* Co-processor register load/store.
9850 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9854 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9855 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9856 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9862 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9863 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9864 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9865 && !(inst
.instruction
& 0x00400000))
9866 as_tsktsk (_("Rd and Rm should be different in mla"));
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9869 inst
.instruction
|= inst
.operands
[1].reg
;
9870 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9871 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9877 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9878 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9881 encode_arm_shifter_operand (1);
9884 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9891 top
= (inst
.instruction
& 0x00400000) != 0;
9892 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9893 _(":lower16: not allowed in this instruction"));
9894 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9895 _(":upper16: not allowed in this instruction"));
9896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9897 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9899 imm
= inst
.relocs
[0].exp
.X_add_number
;
9900 /* The value is in two pieces: 0:11, 16:19. */
9901 inst
.instruction
|= (imm
& 0x00000fff);
9902 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9907 do_vfp_nsyn_mrs (void)
9909 if (inst
.operands
[0].isvec
)
9911 if (inst
.operands
[1].reg
!= 1)
9912 first_error (_("operand 1 must be FPSCR"));
9913 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9914 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9915 do_vfp_nsyn_opcode ("fmstat");
9917 else if (inst
.operands
[1].isvec
)
9918 do_vfp_nsyn_opcode ("fmrx");
9926 do_vfp_nsyn_msr (void)
9928 if (inst
.operands
[0].isvec
)
9929 do_vfp_nsyn_opcode ("fmxr");
9939 unsigned Rt
= inst
.operands
[0].reg
;
9941 if (thumb_mode
&& Rt
== REG_SP
)
9943 inst
.error
= BAD_SP
;
9947 switch (inst
.operands
[1].reg
)
9949 /* MVFR2 is only valid for Armv8-A. */
9951 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9955 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9956 case 1: /* fpscr. */
9957 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9958 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9962 case 14: /* fpcxt_ns. */
9963 case 15: /* fpcxt_s. */
9964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9965 _("selected processor does not support instruction"));
9968 case 2: /* fpscr_nzcvqc. */
9971 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9972 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9973 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9974 _("selected processor does not support instruction"));
9975 if (inst
.operands
[0].reg
!= 2
9976 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9977 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9984 /* APSR_ sets isvec. All other refs to PC are illegal. */
9985 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9987 inst
.error
= BAD_PC
;
9991 /* If we get through parsing the register name, we just insert the number
9992 generated into the instruction without further validation. */
9993 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9994 inst
.instruction
|= (Rt
<< 12);
10000 unsigned Rt
= inst
.operands
[1].reg
;
10003 reject_bad_reg (Rt
);
10004 else if (Rt
== REG_PC
)
10006 inst
.error
= BAD_PC
;
10010 switch (inst
.operands
[0].reg
)
10012 /* MVFR2 is only valid for Armv8-A. */
10014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10018 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10019 case 1: /* fpcr. */
10020 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10021 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10025 case 14: /* fpcxt_ns. */
10026 case 15: /* fpcxt_s. */
10027 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10028 _("selected processor does not support instruction"));
10031 case 2: /* fpscr_nzcvqc. */
10032 case 12: /* vpr. */
10034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10035 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10036 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10037 _("selected processor does not support instruction"));
10038 if (inst
.operands
[0].reg
!= 2
10039 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10040 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10047 /* If we get through parsing the register name, we just insert the number
10048 generated into the instruction without further validation. */
10049 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10050 inst
.instruction
|= (Rt
<< 12);
10058 if (do_vfp_nsyn_mrs () == SUCCESS
)
10061 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10064 if (inst
.operands
[1].isreg
)
10066 br
= inst
.operands
[1].reg
;
10067 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10068 as_bad (_("bad register for mrs"));
10072 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10073 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10075 _("'APSR', 'CPSR' or 'SPSR' expected"));
10076 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10079 inst
.instruction
|= br
;
10082 /* Two possible forms:
10083 "{C|S}PSR_<field>, Rm",
10084 "{C|S}PSR_f, #expression". */
10089 if (do_vfp_nsyn_msr () == SUCCESS
)
10092 inst
.instruction
|= inst
.operands
[0].imm
;
10093 if (inst
.operands
[1].isreg
)
10094 inst
.instruction
|= inst
.operands
[1].reg
;
10097 inst
.instruction
|= INST_IMMEDIATE
;
10098 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10099 inst
.relocs
[0].pc_rel
= 0;
10106 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10108 if (!inst
.operands
[2].present
)
10109 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10110 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10111 inst
.instruction
|= inst
.operands
[1].reg
;
10112 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10114 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10115 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10116 as_tsktsk (_("Rd and Rm should be different in mul"));
10119 /* Long Multiply Parser
10120 UMULL RdLo, RdHi, Rm, Rs
10121 SMULL RdLo, RdHi, Rm, Rs
10122 UMLAL RdLo, RdHi, Rm, Rs
10123 SMLAL RdLo, RdHi, Rm, Rs. */
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10130 inst
.instruction
|= inst
.operands
[2].reg
;
10131 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10133 /* rdhi and rdlo must be different. */
10134 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10135 as_tsktsk (_("rdhi and rdlo must be different"));
10137 /* rdhi, rdlo and rm must all be different before armv6. */
10138 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10139 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10140 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10141 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10147 if (inst
.operands
[0].present
10148 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10150 /* Architectural NOP hints are CPSR sets with no bits selected. */
10151 inst
.instruction
&= 0xf0000000;
10152 inst
.instruction
|= 0x0320f000;
10153 if (inst
.operands
[0].present
)
10154 inst
.instruction
|= inst
.operands
[0].imm
;
10158 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10159 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10160 Condition defaults to COND_ALWAYS.
10161 Error if Rd, Rn or Rm are R15. */
10166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10168 inst
.instruction
|= inst
.operands
[2].reg
;
10169 if (inst
.operands
[3].present
)
10170 encode_arm_shift (3);
10173 /* ARM V6 PKHTB (Argument Parse). */
10178 if (!inst
.operands
[3].present
)
10180 /* If the shift specifier is omitted, turn the instruction
10181 into pkhbt rd, rm, rn. */
10182 inst
.instruction
&= 0xfff00010;
10183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10184 inst
.instruction
|= inst
.operands
[1].reg
;
10185 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10189 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10190 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10191 inst
.instruction
|= inst
.operands
[2].reg
;
10192 encode_arm_shift (3);
10196 /* ARMv5TE: Preload-Cache
10197 MP Extensions: Preload for write
10201 Syntactically, like LDR with B=1, W=0, L=1. */
10206 constraint (!inst
.operands
[0].isreg
,
10207 _("'[' expected after PLD mnemonic"));
10208 constraint (inst
.operands
[0].postind
,
10209 _("post-indexed expression used in preload instruction"));
10210 constraint (inst
.operands
[0].writeback
,
10211 _("writeback used in preload instruction"));
10212 constraint (!inst
.operands
[0].preind
,
10213 _("unindexed addressing used in preload instruction"));
10214 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10217 /* ARMv7: PLI <addr_mode> */
10221 constraint (!inst
.operands
[0].isreg
,
10222 _("'[' expected after PLI mnemonic"));
10223 constraint (inst
.operands
[0].postind
,
10224 _("post-indexed expression used in preload instruction"));
10225 constraint (inst
.operands
[0].writeback
,
10226 _("writeback used in preload instruction"));
10227 constraint (!inst
.operands
[0].preind
,
10228 _("unindexed addressing used in preload instruction"));
10229 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10230 inst
.instruction
&= ~PRE_INDEX
;
10236 constraint (inst
.operands
[0].writeback
,
10237 _("push/pop do not support {reglist}^"));
10238 inst
.operands
[1] = inst
.operands
[0];
10239 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10240 inst
.operands
[0].isreg
= 1;
10241 inst
.operands
[0].writeback
= 1;
10242 inst
.operands
[0].reg
= REG_SP
;
10243 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10246 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10247 word at the specified address and the following word
10249 Unconditionally executed.
10250 Error if Rn is R15. */
10255 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10256 if (inst
.operands
[0].writeback
)
10257 inst
.instruction
|= WRITE_BACK
;
10260 /* ARM V6 ssat (argument parse). */
10265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10266 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10267 inst
.instruction
|= inst
.operands
[2].reg
;
10269 if (inst
.operands
[3].present
)
10270 encode_arm_shift (3);
10273 /* ARM V6 usat (argument parse). */
10278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10279 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10280 inst
.instruction
|= inst
.operands
[2].reg
;
10282 if (inst
.operands
[3].present
)
10283 encode_arm_shift (3);
10286 /* ARM V6 ssat16 (argument parse). */
10291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10292 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10293 inst
.instruction
|= inst
.operands
[2].reg
;
10299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10300 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10301 inst
.instruction
|= inst
.operands
[2].reg
;
10304 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10305 preserving the other bits.
10307 setend <endian_specifier>, where <endian_specifier> is either
10313 if (warn_on_deprecated
10314 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10315 as_tsktsk (_("setend use is deprecated for ARMv8"));
10317 if (inst
.operands
[0].imm
)
10318 inst
.instruction
|= 0x200;
10324 unsigned int Rm
= (inst
.operands
[1].present
10325 ? inst
.operands
[1].reg
10326 : inst
.operands
[0].reg
);
10328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10329 inst
.instruction
|= Rm
;
10330 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10332 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10333 inst
.instruction
|= SHIFT_BY_REG
;
10334 /* PR 12854: Error on extraneous shifts. */
10335 constraint (inst
.operands
[2].shifted
,
10336 _("extraneous shift as part of operand to shift insn"));
10339 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10345 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10346 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10348 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10349 inst
.relocs
[0].pc_rel
= 0;
10355 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10356 inst
.relocs
[0].pc_rel
= 0;
10362 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10363 inst
.relocs
[0].pc_rel
= 0;
10369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10370 _("selected processor does not support SETPAN instruction"));
10372 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10378 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10379 _("selected processor does not support SETPAN instruction"));
10381 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10384 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10385 SMLAxy{cond} Rd,Rm,Rs,Rn
10386 SMLAWy{cond} Rd,Rm,Rs,Rn
10387 Error if any register is R15. */
10392 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10393 inst
.instruction
|= inst
.operands
[1].reg
;
10394 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10395 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10398 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10399 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10400 Error if any register is R15.
10401 Warning if Rdlo == Rdhi. */
10406 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10407 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10408 inst
.instruction
|= inst
.operands
[2].reg
;
10409 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10411 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10412 as_tsktsk (_("rdhi and rdlo must be different"));
10415 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10416 SMULxy{cond} Rd,Rm,Rs
10417 Error if any register is R15. */
10422 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10423 inst
.instruction
|= inst
.operands
[1].reg
;
10424 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10427 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10428 the same for both ARM and Thumb-2. */
10435 if (inst
.operands
[0].present
)
10437 reg
= inst
.operands
[0].reg
;
10438 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10443 inst
.instruction
|= reg
<< 16;
10444 inst
.instruction
|= inst
.operands
[1].imm
;
10445 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10446 inst
.instruction
|= WRITE_BACK
;
10449 /* ARM V6 strex (argument parse). */
10454 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10455 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10456 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10457 || inst
.operands
[2].negative
10458 /* See comment in do_ldrex(). */
10459 || (inst
.operands
[2].reg
== REG_PC
),
10462 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10463 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10465 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10466 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10467 _("offset must be zero in ARM encoding"));
10469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10470 inst
.instruction
|= inst
.operands
[1].reg
;
10471 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10472 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10476 do_t_strexbh (void)
10478 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10479 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10480 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10481 || inst
.operands
[2].negative
,
10484 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10485 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10493 constraint (inst
.operands
[1].reg
% 2 != 0,
10494 _("even register required"));
10495 constraint (inst
.operands
[2].present
10496 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10497 _("can only store two consecutive registers"));
10498 /* If op 2 were present and equal to PC, this function wouldn't
10499 have been called in the first place. */
10500 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10502 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10503 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10504 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10508 inst
.instruction
|= inst
.operands
[1].reg
;
10509 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10516 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10517 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10525 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10526 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10531 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10532 extends it to 32-bits, and adds the result to a value in another
10533 register. You can specify a rotation by 0, 8, 16, or 24 bits
10534 before extracting the 16-bit value.
10535 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10536 Condition defaults to COND_ALWAYS.
10537 Error if any register uses R15. */
10542 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10543 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10544 inst
.instruction
|= inst
.operands
[2].reg
;
10545 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10550 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10551 Condition defaults to COND_ALWAYS.
10552 Error if any register uses R15. */
10557 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10558 inst
.instruction
|= inst
.operands
[1].reg
;
10559 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10562 /* VFP instructions. In a logical order: SP variant first, monad
10563 before dyad, arithmetic then move then load/store. */
10566 do_vfp_sp_monadic (void)
10568 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10569 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10573 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10577 do_vfp_sp_dyadic (void)
10579 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10580 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10581 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10585 do_vfp_sp_compare_z (void)
10587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10591 do_vfp_dp_sp_cvt (void)
10593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10594 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10598 do_vfp_sp_dp_cvt (void)
10600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10601 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10605 do_vfp_reg_from_sp (void)
10607 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10608 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10611 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10612 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10616 do_vfp_reg2_from_sp2 (void)
10618 constraint (inst
.operands
[2].imm
!= 2,
10619 _("only two consecutive VFP SP registers allowed here"));
10620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10621 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10622 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10626 do_vfp_sp_from_reg (void)
10628 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10629 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10632 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10633 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10637 do_vfp_sp2_from_reg2 (void)
10639 constraint (inst
.operands
[0].imm
!= 2,
10640 _("only two consecutive VFP SP registers allowed here"));
10641 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10642 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10643 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10647 do_vfp_sp_ldst (void)
10649 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10650 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10654 do_vfp_dp_ldst (void)
10656 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10657 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10662 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10664 if (inst
.operands
[0].writeback
)
10665 inst
.instruction
|= WRITE_BACK
;
10667 constraint (ldstm_type
!= VFP_LDSTMIA
,
10668 _("this addressing mode requires base-register writeback"));
10669 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10670 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10671 inst
.instruction
|= inst
.operands
[1].imm
;
10675 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10679 if (inst
.operands
[0].writeback
)
10680 inst
.instruction
|= WRITE_BACK
;
10682 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10683 _("this addressing mode requires base-register writeback"));
10685 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10688 count
= inst
.operands
[1].imm
<< 1;
10689 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10692 inst
.instruction
|= count
;
10696 do_vfp_sp_ldstmia (void)
10698 vfp_sp_ldstm (VFP_LDSTMIA
);
10702 do_vfp_sp_ldstmdb (void)
10704 vfp_sp_ldstm (VFP_LDSTMDB
);
10708 do_vfp_dp_ldstmia (void)
10710 vfp_dp_ldstm (VFP_LDSTMIA
);
10714 do_vfp_dp_ldstmdb (void)
10716 vfp_dp_ldstm (VFP_LDSTMDB
);
10720 do_vfp_xp_ldstmia (void)
10722 vfp_dp_ldstm (VFP_LDSTMIAX
);
10726 do_vfp_xp_ldstmdb (void)
10728 vfp_dp_ldstm (VFP_LDSTMDBX
);
10732 do_vfp_dp_rd_rm (void)
10734 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10735 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10738 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10739 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10743 do_vfp_dp_rn_rd (void)
10745 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10746 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10750 do_vfp_dp_rd_rn (void)
10752 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10753 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10757 do_vfp_dp_rd_rn_rm (void)
10759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10760 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10764 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10765 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10769 do_vfp_dp_rd (void)
10771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10775 do_vfp_dp_rm_rd_rn (void)
10777 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10778 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10781 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10782 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10783 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10786 /* VFPv3 instructions. */
10788 do_vfp_sp_const (void)
10790 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10791 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10792 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10796 do_vfp_dp_const (void)
10798 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10799 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10800 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10804 vfp_conv (int srcsize
)
10806 int immbits
= srcsize
- inst
.operands
[1].imm
;
10808 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10810 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10811 i.e. immbits must be in range 0 - 16. */
10812 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10815 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10817 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10818 i.e. immbits must be in range 0 - 31. */
10819 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10823 inst
.instruction
|= (immbits
& 1) << 5;
10824 inst
.instruction
|= (immbits
>> 1);
10828 do_vfp_sp_conv_16 (void)
10830 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10835 do_vfp_dp_conv_16 (void)
10837 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10842 do_vfp_sp_conv_32 (void)
10844 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10849 do_vfp_dp_conv_32 (void)
10851 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10855 /* FPA instructions. Also in a logical order. */
10860 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10861 inst
.instruction
|= inst
.operands
[1].reg
;
10865 do_fpa_ldmstm (void)
10867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10868 switch (inst
.operands
[1].imm
)
10870 case 1: inst
.instruction
|= CP_T_X
; break;
10871 case 2: inst
.instruction
|= CP_T_Y
; break;
10872 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10877 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10879 /* The instruction specified "ea" or "fd", so we can only accept
10880 [Rn]{!}. The instruction does not really support stacking or
10881 unstacking, so we have to emulate these by setting appropriate
10882 bits and offsets. */
10883 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10884 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10885 _("this instruction does not support indexing"));
10887 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10888 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10890 if (!(inst
.instruction
& INDEX_UP
))
10891 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10893 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10895 inst
.operands
[2].preind
= 0;
10896 inst
.operands
[2].postind
= 1;
10900 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10903 /* iWMMXt instructions: strictly in alphabetical order. */
10906 do_iwmmxt_tandorc (void)
10908 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10912 do_iwmmxt_textrc (void)
10914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10915 inst
.instruction
|= inst
.operands
[1].imm
;
10919 do_iwmmxt_textrm (void)
10921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10922 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10923 inst
.instruction
|= inst
.operands
[2].imm
;
10927 do_iwmmxt_tinsr (void)
10929 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10930 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10931 inst
.instruction
|= inst
.operands
[2].imm
;
10935 do_iwmmxt_tmia (void)
10937 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10938 inst
.instruction
|= inst
.operands
[1].reg
;
10939 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10943 do_iwmmxt_waligni (void)
10945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10946 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10947 inst
.instruction
|= inst
.operands
[2].reg
;
10948 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10952 do_iwmmxt_wmerge (void)
10954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10956 inst
.instruction
|= inst
.operands
[2].reg
;
10957 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10961 do_iwmmxt_wmov (void)
10963 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10964 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10965 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10966 inst
.instruction
|= inst
.operands
[1].reg
;
10970 do_iwmmxt_wldstbh (void)
10973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10975 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10977 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10978 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10982 do_iwmmxt_wldstw (void)
10984 /* RIWR_RIWC clears .isreg for a control register. */
10985 if (!inst
.operands
[0].isreg
)
10987 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10988 inst
.instruction
|= 0xf0000000;
10991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10992 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10996 do_iwmmxt_wldstd (void)
10998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10999 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11000 && inst
.operands
[1].immisreg
)
11002 inst
.instruction
&= ~0x1a000ff;
11003 inst
.instruction
|= (0xfU
<< 28);
11004 if (inst
.operands
[1].preind
)
11005 inst
.instruction
|= PRE_INDEX
;
11006 if (!inst
.operands
[1].negative
)
11007 inst
.instruction
|= INDEX_UP
;
11008 if (inst
.operands
[1].writeback
)
11009 inst
.instruction
|= WRITE_BACK
;
11010 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11011 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11012 inst
.instruction
|= inst
.operands
[1].imm
;
11015 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11019 do_iwmmxt_wshufh (void)
11021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11023 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11024 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11028 do_iwmmxt_wzero (void)
11030 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11031 inst
.instruction
|= inst
.operands
[0].reg
;
11032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11033 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11037 do_iwmmxt_wrwrwr_or_imm5 (void)
11039 if (inst
.operands
[2].isreg
)
11042 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11043 _("immediate operand requires iWMMXt2"));
11045 if (inst
.operands
[2].imm
== 0)
11047 switch ((inst
.instruction
>> 20) & 0xf)
11053 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11054 inst
.operands
[2].imm
= 16;
11055 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11061 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11062 inst
.operands
[2].imm
= 32;
11063 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11070 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11072 wrn
= (inst
.instruction
>> 16) & 0xf;
11073 inst
.instruction
&= 0xff0fff0f;
11074 inst
.instruction
|= wrn
;
11075 /* Bail out here; the instruction is now assembled. */
11080 /* Map 32 -> 0, etc. */
11081 inst
.operands
[2].imm
&= 0x1f;
11082 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11086 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11087 operations first, then control, shift, and load/store. */
11089 /* Insns like "foo X,Y,Z". */
11092 do_mav_triple (void)
11094 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11095 inst
.instruction
|= inst
.operands
[1].reg
;
11096 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11099 /* Insns like "foo W,X,Y,Z".
11100 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11105 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11106 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11107 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11108 inst
.instruction
|= inst
.operands
[3].reg
;
11111 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11113 do_mav_dspsc (void)
11115 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11118 /* Maverick shift immediate instructions.
11119 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11120 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11123 do_mav_shift (void)
11125 int imm
= inst
.operands
[2].imm
;
11127 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11128 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11130 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11131 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11132 Bit 4 should be 0. */
11133 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11135 inst
.instruction
|= imm
;
11138 /* XScale instructions. Also sorted arithmetic before move. */
11140 /* Xscale multiply-accumulate (argument parse)
11143 MIAxycc acc0,Rm,Rs. */
11148 inst
.instruction
|= inst
.operands
[1].reg
;
11149 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11152 /* Xscale move-accumulator-register (argument parse)
11154 MARcc acc0,RdLo,RdHi. */
11159 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11160 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11163 /* Xscale move-register-accumulator (argument parse)
11165 MRAcc RdLo,RdHi,acc0. */
11170 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11172 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11175 /* Encoding functions relevant only to Thumb. */
11177 /* inst.operands[i] is a shifted-register operand; encode
11178 it into inst.instruction in the format used by Thumb32. */
11181 encode_thumb32_shifted_operand (int i
)
11183 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11184 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11186 constraint (inst
.operands
[i
].immisreg
,
11187 _("shift by register not allowed in thumb mode"));
11188 inst
.instruction
|= inst
.operands
[i
].reg
;
11189 if (shift
== SHIFT_RRX
)
11190 inst
.instruction
|= SHIFT_ROR
<< 4;
11193 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11194 _("expression too complex"));
11196 constraint (value
> 32
11197 || (value
== 32 && (shift
== SHIFT_LSL
11198 || shift
== SHIFT_ROR
)),
11199 _("shift expression is too large"));
11203 else if (value
== 32)
11206 inst
.instruction
|= shift
<< 4;
11207 inst
.instruction
|= (value
& 0x1c) << 10;
11208 inst
.instruction
|= (value
& 0x03) << 6;
11213 /* inst.operands[i] was set up by parse_address. Encode it into a
11214 Thumb32 format load or store instruction. Reject forms that cannot
11215 be used with such instructions. If is_t is true, reject forms that
11216 cannot be used with a T instruction; if is_d is true, reject forms
11217 that cannot be used with a D instruction. If it is a store insn,
11218 reject PC in Rn. */
11221 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11223 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11225 constraint (!inst
.operands
[i
].isreg
,
11226 _("Instruction does not support =N addresses"));
11228 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11229 if (inst
.operands
[i
].immisreg
)
11231 constraint (is_pc
, BAD_PC_ADDRESSING
);
11232 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11233 constraint (inst
.operands
[i
].negative
,
11234 _("Thumb does not support negative register indexing"));
11235 constraint (inst
.operands
[i
].postind
,
11236 _("Thumb does not support register post-indexing"));
11237 constraint (inst
.operands
[i
].writeback
,
11238 _("Thumb does not support register indexing with writeback"));
11239 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11240 _("Thumb supports only LSL in shifted register indexing"));
11242 inst
.instruction
|= inst
.operands
[i
].imm
;
11243 if (inst
.operands
[i
].shifted
)
11245 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11246 _("expression too complex"));
11247 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11248 || inst
.relocs
[0].exp
.X_add_number
> 3,
11249 _("shift out of range"));
11250 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11252 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11254 else if (inst
.operands
[i
].preind
)
11256 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11257 constraint (is_t
&& inst
.operands
[i
].writeback
,
11258 _("cannot use writeback with this instruction"));
11259 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11260 BAD_PC_ADDRESSING
);
11264 inst
.instruction
|= 0x01000000;
11265 if (inst
.operands
[i
].writeback
)
11266 inst
.instruction
|= 0x00200000;
11270 inst
.instruction
|= 0x00000c00;
11271 if (inst
.operands
[i
].writeback
)
11272 inst
.instruction
|= 0x00000100;
11274 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11276 else if (inst
.operands
[i
].postind
)
11278 gas_assert (inst
.operands
[i
].writeback
);
11279 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11280 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11283 inst
.instruction
|= 0x00200000;
11285 inst
.instruction
|= 0x00000900;
11286 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11288 else /* unindexed - only for coprocessor */
11289 inst
.error
= _("instruction does not accept unindexed addressing");
11292 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11293 encodings (the latter only in post-V6T2 cores). The index is the
11294 value used in the insns table below. When there is more than one
11295 possible 16-bit encoding for the instruction, this table always
11297 Also contains several pseudo-instructions used during relaxation. */
11298 #define T16_32_TAB \
11299 X(_adc, 4140, eb400000), \
11300 X(_adcs, 4140, eb500000), \
11301 X(_add, 1c00, eb000000), \
11302 X(_adds, 1c00, eb100000), \
11303 X(_addi, 0000, f1000000), \
11304 X(_addis, 0000, f1100000), \
11305 X(_add_pc,000f, f20f0000), \
11306 X(_add_sp,000d, f10d0000), \
11307 X(_adr, 000f, f20f0000), \
11308 X(_and, 4000, ea000000), \
11309 X(_ands, 4000, ea100000), \
11310 X(_asr, 1000, fa40f000), \
11311 X(_asrs, 1000, fa50f000), \
11312 X(_b, e000, f000b000), \
11313 X(_bcond, d000, f0008000), \
11314 X(_bf, 0000, f040e001), \
11315 X(_bfcsel,0000, f000e001), \
11316 X(_bfx, 0000, f060e001), \
11317 X(_bfl, 0000, f000c001), \
11318 X(_bflx, 0000, f070e001), \
11319 X(_bic, 4380, ea200000), \
11320 X(_bics, 4380, ea300000), \
11321 X(_cinc, 0000, ea509000), \
11322 X(_cinv, 0000, ea50a000), \
11323 X(_cmn, 42c0, eb100f00), \
11324 X(_cmp, 2800, ebb00f00), \
11325 X(_cneg, 0000, ea50b000), \
11326 X(_cpsie, b660, f3af8400), \
11327 X(_cpsid, b670, f3af8600), \
11328 X(_cpy, 4600, ea4f0000), \
11329 X(_csel, 0000, ea508000), \
11330 X(_cset, 0000, ea5f900f), \
11331 X(_csetm, 0000, ea5fa00f), \
11332 X(_csinc, 0000, ea509000), \
11333 X(_csinv, 0000, ea50a000), \
11334 X(_csneg, 0000, ea50b000), \
11335 X(_dec_sp,80dd, f1ad0d00), \
11336 X(_dls, 0000, f040e001), \
11337 X(_dlstp, 0000, f000e001), \
11338 X(_eor, 4040, ea800000), \
11339 X(_eors, 4040, ea900000), \
11340 X(_inc_sp,00dd, f10d0d00), \
11341 X(_lctp, 0000, f00fe001), \
11342 X(_ldmia, c800, e8900000), \
11343 X(_ldr, 6800, f8500000), \
11344 X(_ldrb, 7800, f8100000), \
11345 X(_ldrh, 8800, f8300000), \
11346 X(_ldrsb, 5600, f9100000), \
11347 X(_ldrsh, 5e00, f9300000), \
11348 X(_ldr_pc,4800, f85f0000), \
11349 X(_ldr_pc2,4800, f85f0000), \
11350 X(_ldr_sp,9800, f85d0000), \
11351 X(_le, 0000, f00fc001), \
11352 X(_letp, 0000, f01fc001), \
11353 X(_lsl, 0000, fa00f000), \
11354 X(_lsls, 0000, fa10f000), \
11355 X(_lsr, 0800, fa20f000), \
11356 X(_lsrs, 0800, fa30f000), \
11357 X(_mov, 2000, ea4f0000), \
11358 X(_movs, 2000, ea5f0000), \
11359 X(_mul, 4340, fb00f000), \
11360 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11361 X(_mvn, 43c0, ea6f0000), \
11362 X(_mvns, 43c0, ea7f0000), \
11363 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11364 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11365 X(_orr, 4300, ea400000), \
11366 X(_orrs, 4300, ea500000), \
11367 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11368 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11369 X(_rev, ba00, fa90f080), \
11370 X(_rev16, ba40, fa90f090), \
11371 X(_revsh, bac0, fa90f0b0), \
11372 X(_ror, 41c0, fa60f000), \
11373 X(_rors, 41c0, fa70f000), \
11374 X(_sbc, 4180, eb600000), \
11375 X(_sbcs, 4180, eb700000), \
11376 X(_stmia, c000, e8800000), \
11377 X(_str, 6000, f8400000), \
11378 X(_strb, 7000, f8000000), \
11379 X(_strh, 8000, f8200000), \
11380 X(_str_sp,9000, f84d0000), \
11381 X(_sub, 1e00, eba00000), \
11382 X(_subs, 1e00, ebb00000), \
11383 X(_subi, 8000, f1a00000), \
11384 X(_subis, 8000, f1b00000), \
11385 X(_sxtb, b240, fa4ff080), \
11386 X(_sxth, b200, fa0ff080), \
11387 X(_tst, 4200, ea100f00), \
11388 X(_uxtb, b2c0, fa5ff080), \
11389 X(_uxth, b280, fa1ff080), \
11390 X(_nop, bf00, f3af8000), \
11391 X(_yield, bf10, f3af8001), \
11392 X(_wfe, bf20, f3af8002), \
11393 X(_wfi, bf30, f3af8003), \
11394 X(_wls, 0000, f040c001), \
11395 X(_wlstp, 0000, f000c001), \
11396 X(_sev, bf40, f3af8004), \
11397 X(_sevl, bf50, f3af8005), \
11398 X(_udf, de00, f7f0a000)
11400 /* To catch errors in encoding functions, the codes are all offset by
11401 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11402 as 16-bit instructions. */
11403 #define X(a,b,c) T_MNEM##a
11404 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11407 #define X(a,b,c) 0x##b
11408 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11409 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11412 #define X(a,b,c) 0x##c
11413 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11414 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11415 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11419 /* Thumb instruction encoders, in alphabetical order. */
11421 /* ADDW or SUBW. */
11424 do_t_add_sub_w (void)
11428 Rd
= inst
.operands
[0].reg
;
11429 Rn
= inst
.operands
[1].reg
;
11431 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11432 is the SP-{plus,minus}-immediate form of the instruction. */
11434 constraint (Rd
== REG_PC
, BAD_PC
);
11436 reject_bad_reg (Rd
);
11438 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11439 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11442 /* Parse an add or subtract instruction. We get here with inst.instruction
11443 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11446 do_t_add_sub (void)
11450 Rd
= inst
.operands
[0].reg
;
11451 Rs
= (inst
.operands
[1].present
11452 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11453 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11456 set_pred_insn_type_last ();
11458 if (unified_syntax
)
11461 bfd_boolean narrow
;
11464 flags
= (inst
.instruction
== T_MNEM_adds
11465 || inst
.instruction
== T_MNEM_subs
);
11467 narrow
= !in_pred_block ();
11469 narrow
= in_pred_block ();
11470 if (!inst
.operands
[2].isreg
)
11474 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11475 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11477 add
= (inst
.instruction
== T_MNEM_add
11478 || inst
.instruction
== T_MNEM_adds
);
11480 if (inst
.size_req
!= 4)
11482 /* Attempt to use a narrow opcode, with relaxation if
11484 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11485 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11486 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11487 opcode
= T_MNEM_add_sp
;
11488 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11489 opcode
= T_MNEM_add_pc
;
11490 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11493 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11495 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11499 inst
.instruction
= THUMB_OP16(opcode
);
11500 inst
.instruction
|= (Rd
<< 4) | Rs
;
11501 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11502 || (inst
.relocs
[0].type
11503 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11505 if (inst
.size_req
== 2)
11506 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11508 inst
.relax
= opcode
;
11512 constraint (inst
.size_req
== 2, BAD_HIREG
);
11514 if (inst
.size_req
== 4
11515 || (inst
.size_req
!= 2 && !opcode
))
11517 constraint ((inst
.relocs
[0].type
11518 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11519 && (inst
.relocs
[0].type
11520 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11521 THUMB1_RELOC_ONLY
);
11524 constraint (add
, BAD_PC
);
11525 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11526 _("only SUBS PC, LR, #const allowed"));
11527 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11528 _("expression too complex"));
11529 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11530 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11531 _("immediate value out of range"));
11532 inst
.instruction
= T2_SUBS_PC_LR
11533 | inst
.relocs
[0].exp
.X_add_number
;
11534 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11537 else if (Rs
== REG_PC
)
11539 /* Always use addw/subw. */
11540 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11541 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11545 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11546 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11549 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11551 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11553 inst
.instruction
|= Rd
<< 8;
11554 inst
.instruction
|= Rs
<< 16;
11559 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11560 unsigned int shift
= inst
.operands
[2].shift_kind
;
11562 Rn
= inst
.operands
[2].reg
;
11563 /* See if we can do this with a 16-bit instruction. */
11564 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11566 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11571 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11572 || inst
.instruction
== T_MNEM_add
)
11574 : T_OPCODE_SUB_R3
);
11575 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11579 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11581 /* Thumb-1 cores (except v6-M) require at least one high
11582 register in a narrow non flag setting add. */
11583 if (Rd
> 7 || Rn
> 7
11584 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11585 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11592 inst
.instruction
= T_OPCODE_ADD_HI
;
11593 inst
.instruction
|= (Rd
& 8) << 4;
11594 inst
.instruction
|= (Rd
& 7);
11595 inst
.instruction
|= Rn
<< 3;
11601 constraint (Rd
== REG_PC
, BAD_PC
);
11602 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11603 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11604 constraint (Rs
== REG_PC
, BAD_PC
);
11605 reject_bad_reg (Rn
);
11607 /* If we get here, it can't be done in 16 bits. */
11608 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11609 _("shift must be constant"));
11610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11611 inst
.instruction
|= Rd
<< 8;
11612 inst
.instruction
|= Rs
<< 16;
11613 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11614 _("shift value over 3 not allowed in thumb mode"));
11615 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11616 _("only LSL shift allowed in thumb mode"));
11617 encode_thumb32_shifted_operand (2);
11622 constraint (inst
.instruction
== T_MNEM_adds
11623 || inst
.instruction
== T_MNEM_subs
,
11626 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11628 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11629 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11632 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11633 ? 0x0000 : 0x8000);
11634 inst
.instruction
|= (Rd
<< 4) | Rs
;
11635 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11639 Rn
= inst
.operands
[2].reg
;
11640 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11642 /* We now have Rd, Rs, and Rn set to registers. */
11643 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11645 /* Can't do this for SUB. */
11646 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11647 inst
.instruction
= T_OPCODE_ADD_HI
;
11648 inst
.instruction
|= (Rd
& 8) << 4;
11649 inst
.instruction
|= (Rd
& 7);
11651 inst
.instruction
|= Rn
<< 3;
11653 inst
.instruction
|= Rs
<< 3;
11655 constraint (1, _("dest must overlap one source register"));
11659 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11660 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11661 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11671 Rd
= inst
.operands
[0].reg
;
11672 reject_bad_reg (Rd
);
11674 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11676 /* Defer to section relaxation. */
11677 inst
.relax
= inst
.instruction
;
11678 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11679 inst
.instruction
|= Rd
<< 4;
11681 else if (unified_syntax
&& inst
.size_req
!= 2)
11683 /* Generate a 32-bit opcode. */
11684 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11685 inst
.instruction
|= Rd
<< 8;
11686 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11687 inst
.relocs
[0].pc_rel
= 1;
11691 /* Generate a 16-bit opcode. */
11692 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11693 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11694 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11695 inst
.relocs
[0].pc_rel
= 1;
11696 inst
.instruction
|= Rd
<< 4;
11699 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11700 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11701 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11702 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11703 inst
.relocs
[0].exp
.X_add_number
+= 1;
11706 /* Arithmetic instructions for which there is just one 16-bit
11707 instruction encoding, and it allows only two low registers.
11708 For maximal compatibility with ARM syntax, we allow three register
11709 operands even when Thumb-32 instructions are not available, as long
11710 as the first two are identical. For instance, both "sbc r0,r1" and
11711 "sbc r0,r0,r1" are allowed. */
11717 Rd
= inst
.operands
[0].reg
;
11718 Rs
= (inst
.operands
[1].present
11719 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11720 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11721 Rn
= inst
.operands
[2].reg
;
11723 reject_bad_reg (Rd
);
11724 reject_bad_reg (Rs
);
11725 if (inst
.operands
[2].isreg
)
11726 reject_bad_reg (Rn
);
11728 if (unified_syntax
)
11730 if (!inst
.operands
[2].isreg
)
11732 /* For an immediate, we always generate a 32-bit opcode;
11733 section relaxation will shrink it later if possible. */
11734 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11735 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11736 inst
.instruction
|= Rd
<< 8;
11737 inst
.instruction
|= Rs
<< 16;
11738 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11742 bfd_boolean narrow
;
11744 /* See if we can do this with a 16-bit instruction. */
11745 if (THUMB_SETS_FLAGS (inst
.instruction
))
11746 narrow
= !in_pred_block ();
11748 narrow
= in_pred_block ();
11750 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11752 if (inst
.operands
[2].shifted
)
11754 if (inst
.size_req
== 4)
11760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11761 inst
.instruction
|= Rd
;
11762 inst
.instruction
|= Rn
<< 3;
11766 /* If we get here, it can't be done in 16 bits. */
11767 constraint (inst
.operands
[2].shifted
11768 && inst
.operands
[2].immisreg
,
11769 _("shift must be constant"));
11770 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11771 inst
.instruction
|= Rd
<< 8;
11772 inst
.instruction
|= Rs
<< 16;
11773 encode_thumb32_shifted_operand (2);
11778 /* On its face this is a lie - the instruction does set the
11779 flags. However, the only supported mnemonic in this mode
11780 says it doesn't. */
11781 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11783 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11784 _("unshifted register required"));
11785 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11786 constraint (Rd
!= Rs
,
11787 _("dest and source1 must be the same register"));
11789 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11790 inst
.instruction
|= Rd
;
11791 inst
.instruction
|= Rn
<< 3;
11795 /* Similarly, but for instructions where the arithmetic operation is
11796 commutative, so we can allow either of them to be different from
11797 the destination operand in a 16-bit instruction. For instance, all
11798 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11805 Rd
= inst
.operands
[0].reg
;
11806 Rs
= (inst
.operands
[1].present
11807 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11808 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11809 Rn
= inst
.operands
[2].reg
;
11811 reject_bad_reg (Rd
);
11812 reject_bad_reg (Rs
);
11813 if (inst
.operands
[2].isreg
)
11814 reject_bad_reg (Rn
);
11816 if (unified_syntax
)
11818 if (!inst
.operands
[2].isreg
)
11820 /* For an immediate, we always generate a 32-bit opcode;
11821 section relaxation will shrink it later if possible. */
11822 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11823 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11824 inst
.instruction
|= Rd
<< 8;
11825 inst
.instruction
|= Rs
<< 16;
11826 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11830 bfd_boolean narrow
;
11832 /* See if we can do this with a 16-bit instruction. */
11833 if (THUMB_SETS_FLAGS (inst
.instruction
))
11834 narrow
= !in_pred_block ();
11836 narrow
= in_pred_block ();
11838 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11840 if (inst
.operands
[2].shifted
)
11842 if (inst
.size_req
== 4)
11849 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11850 inst
.instruction
|= Rd
;
11851 inst
.instruction
|= Rn
<< 3;
11856 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11857 inst
.instruction
|= Rd
;
11858 inst
.instruction
|= Rs
<< 3;
11863 /* If we get here, it can't be done in 16 bits. */
11864 constraint (inst
.operands
[2].shifted
11865 && inst
.operands
[2].immisreg
,
11866 _("shift must be constant"));
11867 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11868 inst
.instruction
|= Rd
<< 8;
11869 inst
.instruction
|= Rs
<< 16;
11870 encode_thumb32_shifted_operand (2);
11875 /* On its face this is a lie - the instruction does set the
11876 flags. However, the only supported mnemonic in this mode
11877 says it doesn't. */
11878 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11880 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11881 _("unshifted register required"));
11882 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11884 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11885 inst
.instruction
|= Rd
;
11888 inst
.instruction
|= Rn
<< 3;
11890 inst
.instruction
|= Rs
<< 3;
11892 constraint (1, _("dest must overlap one source register"));
11900 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11901 constraint (msb
> 32, _("bit-field extends past end of register"));
11902 /* The instruction encoding stores the LSB and MSB,
11903 not the LSB and width. */
11904 Rd
= inst
.operands
[0].reg
;
11905 reject_bad_reg (Rd
);
11906 inst
.instruction
|= Rd
<< 8;
11907 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11908 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11909 inst
.instruction
|= msb
- 1;
11918 Rd
= inst
.operands
[0].reg
;
11919 reject_bad_reg (Rd
);
11921 /* #0 in second position is alternative syntax for bfc, which is
11922 the same instruction but with REG_PC in the Rm field. */
11923 if (!inst
.operands
[1].isreg
)
11927 Rn
= inst
.operands
[1].reg
;
11928 reject_bad_reg (Rn
);
11931 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11932 constraint (msb
> 32, _("bit-field extends past end of register"));
11933 /* The instruction encoding stores the LSB and MSB,
11934 not the LSB and width. */
11935 inst
.instruction
|= Rd
<< 8;
11936 inst
.instruction
|= Rn
<< 16;
11937 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11938 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11939 inst
.instruction
|= msb
- 1;
11947 Rd
= inst
.operands
[0].reg
;
11948 Rn
= inst
.operands
[1].reg
;
11950 reject_bad_reg (Rd
);
11951 reject_bad_reg (Rn
);
11953 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11954 _("bit-field extends past end of register"));
11955 inst
.instruction
|= Rd
<< 8;
11956 inst
.instruction
|= Rn
<< 16;
11957 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11958 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11959 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11962 /* ARM V5 Thumb BLX (argument parse)
11963 BLX <target_addr> which is BLX(1)
11964 BLX <Rm> which is BLX(2)
11965 Unfortunately, there are two different opcodes for this mnemonic.
11966 So, the insns[].value is not used, and the code here zaps values
11967 into inst.instruction.
11969 ??? How to take advantage of the additional two bits of displacement
11970 available in Thumb32 mode? Need new relocation? */
11975 set_pred_insn_type_last ();
11977 if (inst
.operands
[0].isreg
)
11979 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11980 /* We have a register, so this is BLX(2). */
11981 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11985 /* No register. This must be BLX(1). */
11986 inst
.instruction
= 0xf000e800;
11987 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11996 bfd_reloc_code_real_type reloc
;
11999 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12001 if (in_pred_block ())
12003 /* Conditional branches inside IT blocks are encoded as unconditional
12005 cond
= COND_ALWAYS
;
12010 if (cond
!= COND_ALWAYS
)
12011 opcode
= T_MNEM_bcond
;
12013 opcode
= inst
.instruction
;
12016 && (inst
.size_req
== 4
12017 || (inst
.size_req
!= 2
12018 && (inst
.operands
[0].hasreloc
12019 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12021 inst
.instruction
= THUMB_OP32(opcode
);
12022 if (cond
== COND_ALWAYS
)
12023 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12026 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12027 _("selected architecture does not support "
12028 "wide conditional branch instruction"));
12030 gas_assert (cond
!= 0xF);
12031 inst
.instruction
|= cond
<< 22;
12032 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12037 inst
.instruction
= THUMB_OP16(opcode
);
12038 if (cond
== COND_ALWAYS
)
12039 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12042 inst
.instruction
|= cond
<< 8;
12043 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12045 /* Allow section relaxation. */
12046 if (unified_syntax
&& inst
.size_req
!= 2)
12047 inst
.relax
= opcode
;
12049 inst
.relocs
[0].type
= reloc
;
12050 inst
.relocs
[0].pc_rel
= 1;
12053 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12054 between the two is the maximum immediate allowed - which is passed in
12057 do_t_bkpt_hlt1 (int range
)
12059 constraint (inst
.cond
!= COND_ALWAYS
,
12060 _("instruction is always unconditional"));
12061 if (inst
.operands
[0].present
)
12063 constraint (inst
.operands
[0].imm
> range
,
12064 _("immediate value out of range"));
12065 inst
.instruction
|= inst
.operands
[0].imm
;
12068 set_pred_insn_type (NEUTRAL_IT_INSN
);
12074 do_t_bkpt_hlt1 (63);
12080 do_t_bkpt_hlt1 (255);
12084 do_t_branch23 (void)
12086 set_pred_insn_type_last ();
12087 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12089 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12090 this file. We used to simply ignore the PLT reloc type here --
12091 the branch encoding is now needed to deal with TLSCALL relocs.
12092 So if we see a PLT reloc now, put it back to how it used to be to
12093 keep the preexisting behaviour. */
12094 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12095 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12097 #if defined(OBJ_COFF)
12098 /* If the destination of the branch is a defined symbol which does not have
12099 the THUMB_FUNC attribute, then we must be calling a function which has
12100 the (interfacearm) attribute. We look for the Thumb entry point to that
12101 function and change the branch to refer to that function instead. */
12102 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12103 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12104 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12105 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12106 inst
.relocs
[0].exp
.X_add_symbol
12107 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12114 set_pred_insn_type_last ();
12115 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12116 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12117 should cause the alignment to be checked once it is known. This is
12118 because BX PC only works if the instruction is word aligned. */
12126 set_pred_insn_type_last ();
12127 Rm
= inst
.operands
[0].reg
;
12128 reject_bad_reg (Rm
);
12129 inst
.instruction
|= Rm
<< 16;
12138 Rd
= inst
.operands
[0].reg
;
12139 Rm
= inst
.operands
[1].reg
;
12141 reject_bad_reg (Rd
);
12142 reject_bad_reg (Rm
);
12144 inst
.instruction
|= Rd
<< 8;
12145 inst
.instruction
|= Rm
<< 16;
12146 inst
.instruction
|= Rm
;
12149 /* For the Armv8.1-M conditional instructions. */
12153 unsigned Rd
, Rn
, Rm
;
12156 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12158 Rd
= inst
.operands
[0].reg
;
12159 switch (inst
.instruction
)
12165 Rn
= inst
.operands
[1].reg
;
12166 Rm
= inst
.operands
[2].reg
;
12167 cond
= inst
.operands
[3].imm
;
12168 constraint (Rn
== REG_SP
, BAD_SP
);
12169 constraint (Rm
== REG_SP
, BAD_SP
);
12175 Rn
= inst
.operands
[1].reg
;
12176 cond
= inst
.operands
[2].imm
;
12177 /* Invert the last bit to invert the cond. */
12178 cond
= TOGGLE_BIT (cond
, 0);
12179 constraint (Rn
== REG_SP
, BAD_SP
);
12185 cond
= inst
.operands
[1].imm
;
12186 /* Invert the last bit to invert the cond. */
12187 cond
= TOGGLE_BIT (cond
, 0);
12195 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12196 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12197 inst
.instruction
|= Rd
<< 8;
12198 inst
.instruction
|= Rn
<< 16;
12199 inst
.instruction
|= Rm
;
12200 inst
.instruction
|= cond
<< 4;
12206 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12212 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12213 inst
.instruction
|= inst
.operands
[0].imm
;
12219 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12221 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12222 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12224 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12225 inst
.instruction
= 0xf3af8000;
12226 inst
.instruction
|= imod
<< 9;
12227 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12228 if (inst
.operands
[1].present
)
12229 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12234 && (inst
.operands
[0].imm
& 4),
12235 _("selected processor does not support 'A' form "
12236 "of this instruction"));
12237 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12238 _("Thumb does not support the 2-argument "
12239 "form of this instruction"));
12240 inst
.instruction
|= inst
.operands
[0].imm
;
12244 /* THUMB CPY instruction (argument parse). */
12249 if (inst
.size_req
== 4)
12251 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12252 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12253 inst
.instruction
|= inst
.operands
[1].reg
;
12257 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12258 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12259 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12266 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12267 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12268 inst
.instruction
|= inst
.operands
[0].reg
;
12269 inst
.relocs
[0].pc_rel
= 1;
12270 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12276 inst
.instruction
|= inst
.operands
[0].imm
;
12282 unsigned Rd
, Rn
, Rm
;
12284 Rd
= inst
.operands
[0].reg
;
12285 Rn
= (inst
.operands
[1].present
12286 ? inst
.operands
[1].reg
: Rd
);
12287 Rm
= inst
.operands
[2].reg
;
12289 reject_bad_reg (Rd
);
12290 reject_bad_reg (Rn
);
12291 reject_bad_reg (Rm
);
12293 inst
.instruction
|= Rd
<< 8;
12294 inst
.instruction
|= Rn
<< 16;
12295 inst
.instruction
|= Rm
;
12301 if (unified_syntax
&& inst
.size_req
== 4)
12302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12304 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12310 unsigned int cond
= inst
.operands
[0].imm
;
12312 set_pred_insn_type (IT_INSN
);
12313 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12314 now_pred
.cc
= cond
;
12315 now_pred
.warn_deprecated
= FALSE
;
12316 now_pred
.type
= SCALAR_PRED
;
12318 /* If the condition is a negative condition, invert the mask. */
12319 if ((cond
& 0x1) == 0x0)
12321 unsigned int mask
= inst
.instruction
& 0x000f;
12323 if ((mask
& 0x7) == 0)
12325 /* No conversion needed. */
12326 now_pred
.block_length
= 1;
12328 else if ((mask
& 0x3) == 0)
12331 now_pred
.block_length
= 2;
12333 else if ((mask
& 0x1) == 0)
12336 now_pred
.block_length
= 3;
12341 now_pred
.block_length
= 4;
12344 inst
.instruction
&= 0xfff0;
12345 inst
.instruction
|= mask
;
12348 inst
.instruction
|= cond
<< 4;
12351 /* Helper function used for both push/pop and ldm/stm. */
12353 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12354 bfd_boolean writeback
)
12356 bfd_boolean load
, store
;
12358 gas_assert (base
!= -1 || !do_io
);
12359 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12360 store
= do_io
&& !load
;
12362 if (mask
& (1 << 13))
12363 inst
.error
= _("SP not allowed in register list");
12365 if (do_io
&& (mask
& (1 << base
)) != 0
12367 inst
.error
= _("having the base register in the register list when "
12368 "using write back is UNPREDICTABLE");
12372 if (mask
& (1 << 15))
12374 if (mask
& (1 << 14))
12375 inst
.error
= _("LR and PC should not both be in register list");
12377 set_pred_insn_type_last ();
12382 if (mask
& (1 << 15))
12383 inst
.error
= _("PC not allowed in register list");
12386 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12388 /* Single register transfers implemented as str/ldr. */
12391 if (inst
.instruction
& (1 << 23))
12392 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12394 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12398 if (inst
.instruction
& (1 << 23))
12399 inst
.instruction
= 0x00800000; /* ia -> [base] */
12401 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12404 inst
.instruction
|= 0xf8400000;
12406 inst
.instruction
|= 0x00100000;
12408 mask
= ffs (mask
) - 1;
12411 else if (writeback
)
12412 inst
.instruction
|= WRITE_BACK
;
12414 inst
.instruction
|= mask
;
12416 inst
.instruction
|= base
<< 16;
12422 /* This really doesn't seem worth it. */
12423 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12424 _("expression too complex"));
12425 constraint (inst
.operands
[1].writeback
,
12426 _("Thumb load/store multiple does not support {reglist}^"));
12428 if (unified_syntax
)
12430 bfd_boolean narrow
;
12434 /* See if we can use a 16-bit instruction. */
12435 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12436 && inst
.size_req
!= 4
12437 && !(inst
.operands
[1].imm
& ~0xff))
12439 mask
= 1 << inst
.operands
[0].reg
;
12441 if (inst
.operands
[0].reg
<= 7)
12443 if (inst
.instruction
== T_MNEM_stmia
12444 ? inst
.operands
[0].writeback
12445 : (inst
.operands
[0].writeback
12446 == !(inst
.operands
[1].imm
& mask
)))
12448 if (inst
.instruction
== T_MNEM_stmia
12449 && (inst
.operands
[1].imm
& mask
)
12450 && (inst
.operands
[1].imm
& (mask
- 1)))
12451 as_warn (_("value stored for r%d is UNKNOWN"),
12452 inst
.operands
[0].reg
);
12454 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12455 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12456 inst
.instruction
|= inst
.operands
[1].imm
;
12459 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12461 /* This means 1 register in reg list one of 3 situations:
12462 1. Instruction is stmia, but without writeback.
12463 2. lmdia without writeback, but with Rn not in
12465 3. ldmia with writeback, but with Rn in reglist.
12466 Case 3 is UNPREDICTABLE behaviour, so we handle
12467 case 1 and 2 which can be converted into a 16-bit
12468 str or ldr. The SP cases are handled below. */
12469 unsigned long opcode
;
12470 /* First, record an error for Case 3. */
12471 if (inst
.operands
[1].imm
& mask
12472 && inst
.operands
[0].writeback
)
12474 _("having the base register in the register list when "
12475 "using write back is UNPREDICTABLE");
12477 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12479 inst
.instruction
= THUMB_OP16 (opcode
);
12480 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12481 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12485 else if (inst
.operands
[0] .reg
== REG_SP
)
12487 if (inst
.operands
[0].writeback
)
12490 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12491 ? T_MNEM_push
: T_MNEM_pop
);
12492 inst
.instruction
|= inst
.operands
[1].imm
;
12495 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12498 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12499 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12500 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12508 if (inst
.instruction
< 0xffff)
12509 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12511 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12512 inst
.operands
[1].imm
,
12513 inst
.operands
[0].writeback
);
12518 constraint (inst
.operands
[0].reg
> 7
12519 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12520 constraint (inst
.instruction
!= T_MNEM_ldmia
12521 && inst
.instruction
!= T_MNEM_stmia
,
12522 _("Thumb-2 instruction only valid in unified syntax"));
12523 if (inst
.instruction
== T_MNEM_stmia
)
12525 if (!inst
.operands
[0].writeback
)
12526 as_warn (_("this instruction will write back the base register"));
12527 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12528 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12529 as_warn (_("value stored for r%d is UNKNOWN"),
12530 inst
.operands
[0].reg
);
12534 if (!inst
.operands
[0].writeback
12535 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12536 as_warn (_("this instruction will write back the base register"));
12537 else if (inst
.operands
[0].writeback
12538 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12539 as_warn (_("this instruction will not write back the base register"));
12542 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12543 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12544 inst
.instruction
|= inst
.operands
[1].imm
;
12551 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12552 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12553 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12554 || inst
.operands
[1].negative
,
12557 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12560 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12561 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12567 if (!inst
.operands
[1].present
)
12569 constraint (inst
.operands
[0].reg
== REG_LR
,
12570 _("r14 not allowed as first register "
12571 "when second register is omitted"));
12572 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12574 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12578 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12579 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12585 unsigned long opcode
;
12588 if (inst
.operands
[0].isreg
12589 && !inst
.operands
[0].preind
12590 && inst
.operands
[0].reg
== REG_PC
)
12591 set_pred_insn_type_last ();
12593 opcode
= inst
.instruction
;
12594 if (unified_syntax
)
12596 if (!inst
.operands
[1].isreg
)
12598 if (opcode
<= 0xffff)
12599 inst
.instruction
= THUMB_OP32 (opcode
);
12600 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12603 if (inst
.operands
[1].isreg
12604 && !inst
.operands
[1].writeback
12605 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12606 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12607 && opcode
<= 0xffff
12608 && inst
.size_req
!= 4)
12610 /* Insn may have a 16-bit form. */
12611 Rn
= inst
.operands
[1].reg
;
12612 if (inst
.operands
[1].immisreg
)
12614 inst
.instruction
= THUMB_OP16 (opcode
);
12616 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12618 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12619 reject_bad_reg (inst
.operands
[1].imm
);
12621 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12622 && opcode
!= T_MNEM_ldrsb
)
12623 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12624 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12631 if (inst
.relocs
[0].pc_rel
)
12632 opcode
= T_MNEM_ldr_pc2
;
12634 opcode
= T_MNEM_ldr_pc
;
12638 if (opcode
== T_MNEM_ldr
)
12639 opcode
= T_MNEM_ldr_sp
;
12641 opcode
= T_MNEM_str_sp
;
12643 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12647 inst
.instruction
= inst
.operands
[0].reg
;
12648 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12650 inst
.instruction
|= THUMB_OP16 (opcode
);
12651 if (inst
.size_req
== 2)
12652 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12654 inst
.relax
= opcode
;
12658 /* Definitely a 32-bit variant. */
12660 /* Warning for Erratum 752419. */
12661 if (opcode
== T_MNEM_ldr
12662 && inst
.operands
[0].reg
== REG_SP
12663 && inst
.operands
[1].writeback
== 1
12664 && !inst
.operands
[1].immisreg
)
12666 if (no_cpu_selected ()
12667 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12668 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12669 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12670 as_warn (_("This instruction may be unpredictable "
12671 "if executed on M-profile cores "
12672 "with interrupts enabled."));
12675 /* Do some validations regarding addressing modes. */
12676 if (inst
.operands
[1].immisreg
)
12677 reject_bad_reg (inst
.operands
[1].imm
);
12679 constraint (inst
.operands
[1].writeback
== 1
12680 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12683 inst
.instruction
= THUMB_OP32 (opcode
);
12684 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12685 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12686 check_ldr_r15_aligned ();
12690 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12692 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12694 /* Only [Rn,Rm] is acceptable. */
12695 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12696 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12697 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12698 || inst
.operands
[1].negative
,
12699 _("Thumb does not support this addressing mode"));
12700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12704 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12705 if (!inst
.operands
[1].isreg
)
12706 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12709 constraint (!inst
.operands
[1].preind
12710 || inst
.operands
[1].shifted
12711 || inst
.operands
[1].writeback
,
12712 _("Thumb does not support this addressing mode"));
12713 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12715 constraint (inst
.instruction
& 0x0600,
12716 _("byte or halfword not valid for base register"));
12717 constraint (inst
.operands
[1].reg
== REG_PC
12718 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12719 _("r15 based store not allowed"));
12720 constraint (inst
.operands
[1].immisreg
,
12721 _("invalid base register for register offset"));
12723 if (inst
.operands
[1].reg
== REG_PC
)
12724 inst
.instruction
= T_OPCODE_LDR_PC
;
12725 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12726 inst
.instruction
= T_OPCODE_LDR_SP
;
12728 inst
.instruction
= T_OPCODE_STR_SP
;
12730 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12731 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12735 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12736 if (!inst
.operands
[1].immisreg
)
12738 /* Immediate offset. */
12739 inst
.instruction
|= inst
.operands
[0].reg
;
12740 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12741 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12745 /* Register offset. */
12746 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12747 constraint (inst
.operands
[1].negative
,
12748 _("Thumb does not support this addressing mode"));
12751 switch (inst
.instruction
)
12753 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12754 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12755 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12756 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12757 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12758 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12759 case 0x5600 /* ldrsb */:
12760 case 0x5e00 /* ldrsh */: break;
12764 inst
.instruction
|= inst
.operands
[0].reg
;
12765 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12766 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12772 if (!inst
.operands
[1].present
)
12774 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12775 constraint (inst
.operands
[0].reg
== REG_LR
,
12776 _("r14 not allowed here"));
12777 constraint (inst
.operands
[0].reg
== REG_R12
,
12778 _("r12 not allowed here"));
12781 if (inst
.operands
[2].writeback
12782 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12783 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12784 as_warn (_("base register written back, and overlaps "
12785 "one of transfer registers"));
12787 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12788 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12789 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12796 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12802 unsigned Rd
, Rn
, Rm
, Ra
;
12804 Rd
= inst
.operands
[0].reg
;
12805 Rn
= inst
.operands
[1].reg
;
12806 Rm
= inst
.operands
[2].reg
;
12807 Ra
= inst
.operands
[3].reg
;
12809 reject_bad_reg (Rd
);
12810 reject_bad_reg (Rn
);
12811 reject_bad_reg (Rm
);
12812 reject_bad_reg (Ra
);
12814 inst
.instruction
|= Rd
<< 8;
12815 inst
.instruction
|= Rn
<< 16;
12816 inst
.instruction
|= Rm
;
12817 inst
.instruction
|= Ra
<< 12;
12823 unsigned RdLo
, RdHi
, Rn
, Rm
;
12825 RdLo
= inst
.operands
[0].reg
;
12826 RdHi
= inst
.operands
[1].reg
;
12827 Rn
= inst
.operands
[2].reg
;
12828 Rm
= inst
.operands
[3].reg
;
12830 reject_bad_reg (RdLo
);
12831 reject_bad_reg (RdHi
);
12832 reject_bad_reg (Rn
);
12833 reject_bad_reg (Rm
);
12835 inst
.instruction
|= RdLo
<< 12;
12836 inst
.instruction
|= RdHi
<< 8;
12837 inst
.instruction
|= Rn
<< 16;
12838 inst
.instruction
|= Rm
;
12842 do_t_mov_cmp (void)
12846 Rn
= inst
.operands
[0].reg
;
12847 Rm
= inst
.operands
[1].reg
;
12850 set_pred_insn_type_last ();
12852 if (unified_syntax
)
12854 int r0off
= (inst
.instruction
== T_MNEM_mov
12855 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12856 unsigned long opcode
;
12857 bfd_boolean narrow
;
12858 bfd_boolean low_regs
;
12860 low_regs
= (Rn
<= 7 && Rm
<= 7);
12861 opcode
= inst
.instruction
;
12862 if (in_pred_block ())
12863 narrow
= opcode
!= T_MNEM_movs
;
12865 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12866 if (inst
.size_req
== 4
12867 || inst
.operands
[1].shifted
)
12870 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12871 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12872 && !inst
.operands
[1].shifted
12876 inst
.instruction
= T2_SUBS_PC_LR
;
12880 if (opcode
== T_MNEM_cmp
)
12882 constraint (Rn
== REG_PC
, BAD_PC
);
12885 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12887 warn_deprecated_sp (Rm
);
12888 /* R15 was documented as a valid choice for Rm in ARMv6,
12889 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12890 tools reject R15, so we do too. */
12891 constraint (Rm
== REG_PC
, BAD_PC
);
12894 reject_bad_reg (Rm
);
12896 else if (opcode
== T_MNEM_mov
12897 || opcode
== T_MNEM_movs
)
12899 if (inst
.operands
[1].isreg
)
12901 if (opcode
== T_MNEM_movs
)
12903 reject_bad_reg (Rn
);
12904 reject_bad_reg (Rm
);
12908 /* This is mov.n. */
12909 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12910 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12912 as_tsktsk (_("Use of r%u as a source register is "
12913 "deprecated when r%u is the destination "
12914 "register."), Rm
, Rn
);
12919 /* This is mov.w. */
12920 constraint (Rn
== REG_PC
, BAD_PC
);
12921 constraint (Rm
== REG_PC
, BAD_PC
);
12922 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12923 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12927 reject_bad_reg (Rn
);
12930 if (!inst
.operands
[1].isreg
)
12932 /* Immediate operand. */
12933 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12935 if (low_regs
&& narrow
)
12937 inst
.instruction
= THUMB_OP16 (opcode
);
12938 inst
.instruction
|= Rn
<< 8;
12939 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12940 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12942 if (inst
.size_req
== 2)
12943 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12945 inst
.relax
= opcode
;
12950 constraint ((inst
.relocs
[0].type
12951 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12952 && (inst
.relocs
[0].type
12953 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12954 THUMB1_RELOC_ONLY
);
12956 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12957 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12958 inst
.instruction
|= Rn
<< r0off
;
12959 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12962 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12963 && (inst
.instruction
== T_MNEM_mov
12964 || inst
.instruction
== T_MNEM_movs
))
12966 /* Register shifts are encoded as separate shift instructions. */
12967 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12969 if (in_pred_block ())
12974 if (inst
.size_req
== 4)
12977 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12983 switch (inst
.operands
[1].shift_kind
)
12986 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12989 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12992 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12995 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13001 inst
.instruction
= opcode
;
13004 inst
.instruction
|= Rn
;
13005 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13010 inst
.instruction
|= CONDS_BIT
;
13012 inst
.instruction
|= Rn
<< 8;
13013 inst
.instruction
|= Rm
<< 16;
13014 inst
.instruction
|= inst
.operands
[1].imm
;
13019 /* Some mov with immediate shift have narrow variants.
13020 Register shifts are handled above. */
13021 if (low_regs
&& inst
.operands
[1].shifted
13022 && (inst
.instruction
== T_MNEM_mov
13023 || inst
.instruction
== T_MNEM_movs
))
13025 if (in_pred_block ())
13026 narrow
= (inst
.instruction
== T_MNEM_mov
);
13028 narrow
= (inst
.instruction
== T_MNEM_movs
);
13033 switch (inst
.operands
[1].shift_kind
)
13035 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13036 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13037 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13038 default: narrow
= FALSE
; break;
13044 inst
.instruction
|= Rn
;
13045 inst
.instruction
|= Rm
<< 3;
13046 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13050 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13051 inst
.instruction
|= Rn
<< r0off
;
13052 encode_thumb32_shifted_operand (1);
13056 switch (inst
.instruction
)
13059 /* In v4t or v5t a move of two lowregs produces unpredictable
13060 results. Don't allow this. */
13063 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13064 "MOV Rd, Rs with two low registers is not "
13065 "permitted on this architecture");
13066 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13070 inst
.instruction
= T_OPCODE_MOV_HR
;
13071 inst
.instruction
|= (Rn
& 0x8) << 4;
13072 inst
.instruction
|= (Rn
& 0x7);
13073 inst
.instruction
|= Rm
<< 3;
13077 /* We know we have low registers at this point.
13078 Generate LSLS Rd, Rs, #0. */
13079 inst
.instruction
= T_OPCODE_LSL_I
;
13080 inst
.instruction
|= Rn
;
13081 inst
.instruction
|= Rm
<< 3;
13087 inst
.instruction
= T_OPCODE_CMP_LR
;
13088 inst
.instruction
|= Rn
;
13089 inst
.instruction
|= Rm
<< 3;
13093 inst
.instruction
= T_OPCODE_CMP_HR
;
13094 inst
.instruction
|= (Rn
& 0x8) << 4;
13095 inst
.instruction
|= (Rn
& 0x7);
13096 inst
.instruction
|= Rm
<< 3;
13103 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13105 /* PR 10443: Do not silently ignore shifted operands. */
13106 constraint (inst
.operands
[1].shifted
,
13107 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13109 if (inst
.operands
[1].isreg
)
13111 if (Rn
< 8 && Rm
< 8)
13113 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13114 since a MOV instruction produces unpredictable results. */
13115 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13116 inst
.instruction
= T_OPCODE_ADD_I3
;
13118 inst
.instruction
= T_OPCODE_CMP_LR
;
13120 inst
.instruction
|= Rn
;
13121 inst
.instruction
|= Rm
<< 3;
13125 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13126 inst
.instruction
= T_OPCODE_MOV_HR
;
13128 inst
.instruction
= T_OPCODE_CMP_HR
;
13134 constraint (Rn
> 7,
13135 _("only lo regs allowed with immediate"));
13136 inst
.instruction
|= Rn
<< 8;
13137 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13148 top
= (inst
.instruction
& 0x00800000) != 0;
13149 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13151 constraint (top
, _(":lower16: not allowed in this instruction"));
13152 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13154 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13156 constraint (!top
, _(":upper16: not allowed in this instruction"));
13157 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13160 Rd
= inst
.operands
[0].reg
;
13161 reject_bad_reg (Rd
);
13163 inst
.instruction
|= Rd
<< 8;
13164 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13166 imm
= inst
.relocs
[0].exp
.X_add_number
;
13167 inst
.instruction
|= (imm
& 0xf000) << 4;
13168 inst
.instruction
|= (imm
& 0x0800) << 15;
13169 inst
.instruction
|= (imm
& 0x0700) << 4;
13170 inst
.instruction
|= (imm
& 0x00ff);
13175 do_t_mvn_tst (void)
13179 Rn
= inst
.operands
[0].reg
;
13180 Rm
= inst
.operands
[1].reg
;
13182 if (inst
.instruction
== T_MNEM_cmp
13183 || inst
.instruction
== T_MNEM_cmn
)
13184 constraint (Rn
== REG_PC
, BAD_PC
);
13186 reject_bad_reg (Rn
);
13187 reject_bad_reg (Rm
);
13189 if (unified_syntax
)
13191 int r0off
= (inst
.instruction
== T_MNEM_mvn
13192 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13193 bfd_boolean narrow
;
13195 if (inst
.size_req
== 4
13196 || inst
.instruction
> 0xffff
13197 || inst
.operands
[1].shifted
13198 || Rn
> 7 || Rm
> 7)
13200 else if (inst
.instruction
== T_MNEM_cmn
13201 || inst
.instruction
== T_MNEM_tst
)
13203 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13204 narrow
= !in_pred_block ();
13206 narrow
= in_pred_block ();
13208 if (!inst
.operands
[1].isreg
)
13210 /* For an immediate, we always generate a 32-bit opcode;
13211 section relaxation will shrink it later if possible. */
13212 if (inst
.instruction
< 0xffff)
13213 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13214 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13215 inst
.instruction
|= Rn
<< r0off
;
13216 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13220 /* See if we can do this with a 16-bit instruction. */
13223 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13224 inst
.instruction
|= Rn
;
13225 inst
.instruction
|= Rm
<< 3;
13229 constraint (inst
.operands
[1].shifted
13230 && inst
.operands
[1].immisreg
,
13231 _("shift must be constant"));
13232 if (inst
.instruction
< 0xffff)
13233 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13234 inst
.instruction
|= Rn
<< r0off
;
13235 encode_thumb32_shifted_operand (1);
13241 constraint (inst
.instruction
> 0xffff
13242 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13243 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13244 _("unshifted register required"));
13245 constraint (Rn
> 7 || Rm
> 7,
13248 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13249 inst
.instruction
|= Rn
;
13250 inst
.instruction
|= Rm
<< 3;
13259 if (do_vfp_nsyn_mrs () == SUCCESS
)
13262 Rd
= inst
.operands
[0].reg
;
13263 reject_bad_reg (Rd
);
13264 inst
.instruction
|= Rd
<< 8;
13266 if (inst
.operands
[1].isreg
)
13268 unsigned br
= inst
.operands
[1].reg
;
13269 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13270 as_bad (_("bad register for mrs"));
13272 inst
.instruction
|= br
& (0xf << 16);
13273 inst
.instruction
|= (br
& 0x300) >> 4;
13274 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13278 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13280 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13282 /* PR gas/12698: The constraint is only applied for m_profile.
13283 If the user has specified -march=all, we want to ignore it as
13284 we are building for any CPU type, including non-m variants. */
13285 bfd_boolean m_profile
=
13286 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13287 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13288 "not support requested special purpose register"));
13291 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13293 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13294 _("'APSR', 'CPSR' or 'SPSR' expected"));
13296 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13297 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13298 inst
.instruction
|= 0xf0000;
13308 if (do_vfp_nsyn_msr () == SUCCESS
)
13311 constraint (!inst
.operands
[1].isreg
,
13312 _("Thumb encoding does not support an immediate here"));
13314 if (inst
.operands
[0].isreg
)
13315 flags
= (int)(inst
.operands
[0].reg
);
13317 flags
= inst
.operands
[0].imm
;
13319 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13321 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13323 /* PR gas/12698: The constraint is only applied for m_profile.
13324 If the user has specified -march=all, we want to ignore it as
13325 we are building for any CPU type, including non-m variants. */
13326 bfd_boolean m_profile
=
13327 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13328 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13329 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13330 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13331 && bits
!= PSR_f
)) && m_profile
,
13332 _("selected processor does not support requested special "
13333 "purpose register"));
13336 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13337 "requested special purpose register"));
13339 Rn
= inst
.operands
[1].reg
;
13340 reject_bad_reg (Rn
);
13342 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13343 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13344 inst
.instruction
|= (flags
& 0x300) >> 4;
13345 inst
.instruction
|= (flags
& 0xff);
13346 inst
.instruction
|= Rn
<< 16;
13352 bfd_boolean narrow
;
13353 unsigned Rd
, Rn
, Rm
;
13355 if (!inst
.operands
[2].present
)
13356 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13358 Rd
= inst
.operands
[0].reg
;
13359 Rn
= inst
.operands
[1].reg
;
13360 Rm
= inst
.operands
[2].reg
;
13362 if (unified_syntax
)
13364 if (inst
.size_req
== 4
13370 else if (inst
.instruction
== T_MNEM_muls
)
13371 narrow
= !in_pred_block ();
13373 narrow
= in_pred_block ();
13377 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13378 constraint (Rn
> 7 || Rm
> 7,
13385 /* 16-bit MULS/Conditional MUL. */
13386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13387 inst
.instruction
|= Rd
;
13390 inst
.instruction
|= Rm
<< 3;
13392 inst
.instruction
|= Rn
<< 3;
13394 constraint (1, _("dest must overlap one source register"));
13398 constraint (inst
.instruction
!= T_MNEM_mul
,
13399 _("Thumb-2 MUL must not set flags"));
13401 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13402 inst
.instruction
|= Rd
<< 8;
13403 inst
.instruction
|= Rn
<< 16;
13404 inst
.instruction
|= Rm
<< 0;
13406 reject_bad_reg (Rd
);
13407 reject_bad_reg (Rn
);
13408 reject_bad_reg (Rm
);
13415 unsigned RdLo
, RdHi
, Rn
, Rm
;
13417 RdLo
= inst
.operands
[0].reg
;
13418 RdHi
= inst
.operands
[1].reg
;
13419 Rn
= inst
.operands
[2].reg
;
13420 Rm
= inst
.operands
[3].reg
;
13422 reject_bad_reg (RdLo
);
13423 reject_bad_reg (RdHi
);
13424 reject_bad_reg (Rn
);
13425 reject_bad_reg (Rm
);
13427 inst
.instruction
|= RdLo
<< 12;
13428 inst
.instruction
|= RdHi
<< 8;
13429 inst
.instruction
|= Rn
<< 16;
13430 inst
.instruction
|= Rm
;
13433 as_tsktsk (_("rdhi and rdlo must be different"));
13439 set_pred_insn_type (NEUTRAL_IT_INSN
);
13441 if (unified_syntax
)
13443 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13446 inst
.instruction
|= inst
.operands
[0].imm
;
13450 /* PR9722: Check for Thumb2 availability before
13451 generating a thumb2 nop instruction. */
13452 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13454 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13455 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13458 inst
.instruction
= 0x46c0;
13463 constraint (inst
.operands
[0].present
,
13464 _("Thumb does not support NOP with hints"));
13465 inst
.instruction
= 0x46c0;
13472 if (unified_syntax
)
13474 bfd_boolean narrow
;
13476 if (THUMB_SETS_FLAGS (inst
.instruction
))
13477 narrow
= !in_pred_block ();
13479 narrow
= in_pred_block ();
13480 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13482 if (inst
.size_req
== 4)
13487 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13488 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13489 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13493 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13494 inst
.instruction
|= inst
.operands
[0].reg
;
13495 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13500 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13502 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13504 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13505 inst
.instruction
|= inst
.operands
[0].reg
;
13506 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13515 Rd
= inst
.operands
[0].reg
;
13516 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13518 reject_bad_reg (Rd
);
13519 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13520 reject_bad_reg (Rn
);
13522 inst
.instruction
|= Rd
<< 8;
13523 inst
.instruction
|= Rn
<< 16;
13525 if (!inst
.operands
[2].isreg
)
13527 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13528 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13534 Rm
= inst
.operands
[2].reg
;
13535 reject_bad_reg (Rm
);
13537 constraint (inst
.operands
[2].shifted
13538 && inst
.operands
[2].immisreg
,
13539 _("shift must be constant"));
13540 encode_thumb32_shifted_operand (2);
13547 unsigned Rd
, Rn
, Rm
;
13549 Rd
= inst
.operands
[0].reg
;
13550 Rn
= inst
.operands
[1].reg
;
13551 Rm
= inst
.operands
[2].reg
;
13553 reject_bad_reg (Rd
);
13554 reject_bad_reg (Rn
);
13555 reject_bad_reg (Rm
);
13557 inst
.instruction
|= Rd
<< 8;
13558 inst
.instruction
|= Rn
<< 16;
13559 inst
.instruction
|= Rm
;
13560 if (inst
.operands
[3].present
)
13562 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13563 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13564 _("expression too complex"));
13565 inst
.instruction
|= (val
& 0x1c) << 10;
13566 inst
.instruction
|= (val
& 0x03) << 6;
13573 if (!inst
.operands
[3].present
)
13577 inst
.instruction
&= ~0x00000020;
13579 /* PR 10168. Swap the Rm and Rn registers. */
13580 Rtmp
= inst
.operands
[1].reg
;
13581 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13582 inst
.operands
[2].reg
= Rtmp
;
13590 if (inst
.operands
[0].immisreg
)
13591 reject_bad_reg (inst
.operands
[0].imm
);
13593 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13597 do_t_push_pop (void)
13601 constraint (inst
.operands
[0].writeback
,
13602 _("push/pop do not support {reglist}^"));
13603 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13604 _("expression too complex"));
13606 mask
= inst
.operands
[0].imm
;
13607 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13608 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13609 else if (inst
.size_req
!= 4
13610 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13611 ? REG_LR
: REG_PC
)))
13613 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13614 inst
.instruction
|= THUMB_PP_PC_LR
;
13615 inst
.instruction
|= mask
& 0xff;
13617 else if (unified_syntax
)
13619 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13620 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13624 inst
.error
= _("invalid register list to push/pop instruction");
13632 if (unified_syntax
)
13633 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13636 inst
.error
= _("invalid register list to push/pop instruction");
13642 do_t_vscclrm (void)
13644 if (inst
.operands
[0].issingle
)
13646 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13647 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13648 inst
.instruction
|= inst
.operands
[0].imm
;
13652 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13653 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13654 inst
.instruction
|= 1 << 8;
13655 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13664 Rd
= inst
.operands
[0].reg
;
13665 Rm
= inst
.operands
[1].reg
;
13667 reject_bad_reg (Rd
);
13668 reject_bad_reg (Rm
);
13670 inst
.instruction
|= Rd
<< 8;
13671 inst
.instruction
|= Rm
<< 16;
13672 inst
.instruction
|= Rm
;
13680 Rd
= inst
.operands
[0].reg
;
13681 Rm
= inst
.operands
[1].reg
;
13683 reject_bad_reg (Rd
);
13684 reject_bad_reg (Rm
);
13686 if (Rd
<= 7 && Rm
<= 7
13687 && inst
.size_req
!= 4)
13689 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13690 inst
.instruction
|= Rd
;
13691 inst
.instruction
|= Rm
<< 3;
13693 else if (unified_syntax
)
13695 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13696 inst
.instruction
|= Rd
<< 8;
13697 inst
.instruction
|= Rm
<< 16;
13698 inst
.instruction
|= Rm
;
13701 inst
.error
= BAD_HIREG
;
13709 Rd
= inst
.operands
[0].reg
;
13710 Rm
= inst
.operands
[1].reg
;
13712 reject_bad_reg (Rd
);
13713 reject_bad_reg (Rm
);
13715 inst
.instruction
|= Rd
<< 8;
13716 inst
.instruction
|= Rm
;
13724 Rd
= inst
.operands
[0].reg
;
13725 Rs
= (inst
.operands
[1].present
13726 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13727 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13729 reject_bad_reg (Rd
);
13730 reject_bad_reg (Rs
);
13731 if (inst
.operands
[2].isreg
)
13732 reject_bad_reg (inst
.operands
[2].reg
);
13734 inst
.instruction
|= Rd
<< 8;
13735 inst
.instruction
|= Rs
<< 16;
13736 if (!inst
.operands
[2].isreg
)
13738 bfd_boolean narrow
;
13740 if ((inst
.instruction
& 0x00100000) != 0)
13741 narrow
= !in_pred_block ();
13743 narrow
= in_pred_block ();
13745 if (Rd
> 7 || Rs
> 7)
13748 if (inst
.size_req
== 4 || !unified_syntax
)
13751 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13752 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13755 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13756 relaxation, but it doesn't seem worth the hassle. */
13759 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13760 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13761 inst
.instruction
|= Rs
<< 3;
13762 inst
.instruction
|= Rd
;
13766 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13767 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13771 encode_thumb32_shifted_operand (2);
13777 if (warn_on_deprecated
13778 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13779 as_tsktsk (_("setend use is deprecated for ARMv8"));
13781 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13782 if (inst
.operands
[0].imm
)
13783 inst
.instruction
|= 0x8;
13789 if (!inst
.operands
[1].present
)
13790 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13792 if (unified_syntax
)
13794 bfd_boolean narrow
;
13797 switch (inst
.instruction
)
13800 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13802 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13804 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13806 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13810 if (THUMB_SETS_FLAGS (inst
.instruction
))
13811 narrow
= !in_pred_block ();
13813 narrow
= in_pred_block ();
13814 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13816 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13818 if (inst
.operands
[2].isreg
13819 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13820 || inst
.operands
[2].reg
> 7))
13822 if (inst
.size_req
== 4)
13825 reject_bad_reg (inst
.operands
[0].reg
);
13826 reject_bad_reg (inst
.operands
[1].reg
);
13830 if (inst
.operands
[2].isreg
)
13832 reject_bad_reg (inst
.operands
[2].reg
);
13833 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13834 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13835 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13836 inst
.instruction
|= inst
.operands
[2].reg
;
13838 /* PR 12854: Error on extraneous shifts. */
13839 constraint (inst
.operands
[2].shifted
,
13840 _("extraneous shift as part of operand to shift insn"));
13844 inst
.operands
[1].shifted
= 1;
13845 inst
.operands
[1].shift_kind
= shift_kind
;
13846 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13847 ? T_MNEM_movs
: T_MNEM_mov
);
13848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13849 encode_thumb32_shifted_operand (1);
13850 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13851 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13856 if (inst
.operands
[2].isreg
)
13858 switch (shift_kind
)
13860 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13861 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13862 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13863 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13867 inst
.instruction
|= inst
.operands
[0].reg
;
13868 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13870 /* PR 12854: Error on extraneous shifts. */
13871 constraint (inst
.operands
[2].shifted
,
13872 _("extraneous shift as part of operand to shift insn"));
13876 switch (shift_kind
)
13878 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13879 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13880 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13883 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13884 inst
.instruction
|= inst
.operands
[0].reg
;
13885 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13891 constraint (inst
.operands
[0].reg
> 7
13892 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13893 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13895 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13897 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13898 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13899 _("source1 and dest must be same register"));
13901 switch (inst
.instruction
)
13903 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13904 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13905 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13906 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13910 inst
.instruction
|= inst
.operands
[0].reg
;
13911 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13913 /* PR 12854: Error on extraneous shifts. */
13914 constraint (inst
.operands
[2].shifted
,
13915 _("extraneous shift as part of operand to shift insn"));
13919 switch (inst
.instruction
)
13921 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13922 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13923 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13924 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13927 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13928 inst
.instruction
|= inst
.operands
[0].reg
;
13929 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13937 unsigned Rd
, Rn
, Rm
;
13939 Rd
= inst
.operands
[0].reg
;
13940 Rn
= inst
.operands
[1].reg
;
13941 Rm
= inst
.operands
[2].reg
;
13943 reject_bad_reg (Rd
);
13944 reject_bad_reg (Rn
);
13945 reject_bad_reg (Rm
);
13947 inst
.instruction
|= Rd
<< 8;
13948 inst
.instruction
|= Rn
<< 16;
13949 inst
.instruction
|= Rm
;
13955 unsigned Rd
, Rn
, Rm
;
13957 Rd
= inst
.operands
[0].reg
;
13958 Rm
= inst
.operands
[1].reg
;
13959 Rn
= inst
.operands
[2].reg
;
13961 reject_bad_reg (Rd
);
13962 reject_bad_reg (Rn
);
13963 reject_bad_reg (Rm
);
13965 inst
.instruction
|= Rd
<< 8;
13966 inst
.instruction
|= Rn
<< 16;
13967 inst
.instruction
|= Rm
;
13973 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13974 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13975 _("SMC is not permitted on this architecture"));
13976 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13977 _("expression too complex"));
13978 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
13980 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13981 inst
.instruction
|= (value
& 0x000f) << 16;
13983 /* PR gas/15623: SMC instructions must be last in an IT block. */
13984 set_pred_insn_type_last ();
13990 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13992 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13993 inst
.instruction
|= (value
& 0x0fff);
13994 inst
.instruction
|= (value
& 0xf000) << 4;
13998 do_t_ssat_usat (int bias
)
14002 Rd
= inst
.operands
[0].reg
;
14003 Rn
= inst
.operands
[2].reg
;
14005 reject_bad_reg (Rd
);
14006 reject_bad_reg (Rn
);
14008 inst
.instruction
|= Rd
<< 8;
14009 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14010 inst
.instruction
|= Rn
<< 16;
14012 if (inst
.operands
[3].present
)
14014 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14016 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14018 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14019 _("expression too complex"));
14021 if (shift_amount
!= 0)
14023 constraint (shift_amount
> 31,
14024 _("shift expression is too large"));
14026 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14027 inst
.instruction
|= 0x00200000; /* sh bit. */
14029 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14030 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14038 do_t_ssat_usat (1);
14046 Rd
= inst
.operands
[0].reg
;
14047 Rn
= inst
.operands
[2].reg
;
14049 reject_bad_reg (Rd
);
14050 reject_bad_reg (Rn
);
14052 inst
.instruction
|= Rd
<< 8;
14053 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14054 inst
.instruction
|= Rn
<< 16;
14060 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14061 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14062 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14063 || inst
.operands
[2].negative
,
14066 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14068 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14069 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14070 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14071 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14077 if (!inst
.operands
[2].present
)
14078 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14080 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14081 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14082 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14085 inst
.instruction
|= inst
.operands
[0].reg
;
14086 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14087 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14088 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14094 unsigned Rd
, Rn
, Rm
;
14096 Rd
= inst
.operands
[0].reg
;
14097 Rn
= inst
.operands
[1].reg
;
14098 Rm
= inst
.operands
[2].reg
;
14100 reject_bad_reg (Rd
);
14101 reject_bad_reg (Rn
);
14102 reject_bad_reg (Rm
);
14104 inst
.instruction
|= Rd
<< 8;
14105 inst
.instruction
|= Rn
<< 16;
14106 inst
.instruction
|= Rm
;
14107 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14115 Rd
= inst
.operands
[0].reg
;
14116 Rm
= inst
.operands
[1].reg
;
14118 reject_bad_reg (Rd
);
14119 reject_bad_reg (Rm
);
14121 if (inst
.instruction
<= 0xffff
14122 && inst
.size_req
!= 4
14123 && Rd
<= 7 && Rm
<= 7
14124 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14126 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14127 inst
.instruction
|= Rd
;
14128 inst
.instruction
|= Rm
<< 3;
14130 else if (unified_syntax
)
14132 if (inst
.instruction
<= 0xffff)
14133 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14134 inst
.instruction
|= Rd
<< 8;
14135 inst
.instruction
|= Rm
;
14136 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14140 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14141 _("Thumb encoding does not support rotation"));
14142 constraint (1, BAD_HIREG
);
14149 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14158 half
= (inst
.instruction
& 0x10) != 0;
14159 set_pred_insn_type_last ();
14160 constraint (inst
.operands
[0].immisreg
,
14161 _("instruction requires register index"));
14163 Rn
= inst
.operands
[0].reg
;
14164 Rm
= inst
.operands
[0].imm
;
14166 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14167 constraint (Rn
== REG_SP
, BAD_SP
);
14168 reject_bad_reg (Rm
);
14170 constraint (!half
&& inst
.operands
[0].shifted
,
14171 _("instruction does not allow shifted index"));
14172 inst
.instruction
|= (Rn
<< 16) | Rm
;
14178 if (!inst
.operands
[0].present
)
14179 inst
.operands
[0].imm
= 0;
14181 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14183 constraint (inst
.size_req
== 2,
14184 _("immediate value out of range"));
14185 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14186 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14187 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14192 inst
.instruction
|= inst
.operands
[0].imm
;
14195 set_pred_insn_type (NEUTRAL_IT_INSN
);
14202 do_t_ssat_usat (0);
14210 Rd
= inst
.operands
[0].reg
;
14211 Rn
= inst
.operands
[2].reg
;
14213 reject_bad_reg (Rd
);
14214 reject_bad_reg (Rn
);
14216 inst
.instruction
|= Rd
<< 8;
14217 inst
.instruction
|= inst
.operands
[1].imm
;
14218 inst
.instruction
|= Rn
<< 16;
14221 /* Checking the range of the branch offset (VAL) with NBITS bits
14222 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14224 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14226 gas_assert (nbits
> 0 && nbits
<= 32);
14229 int cmp
= (1 << (nbits
- 1));
14230 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14235 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14241 /* For branches in Armv8.1-M Mainline. */
14243 do_t_branch_future (void)
14245 unsigned long insn
= inst
.instruction
;
14247 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14248 if (inst
.operands
[0].hasreloc
== 0)
14250 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14251 as_bad (BAD_BRANCH_OFF
);
14253 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14257 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14258 inst
.relocs
[0].pc_rel
= 1;
14264 if (inst
.operands
[1].hasreloc
== 0)
14266 int val
= inst
.operands
[1].imm
;
14267 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14268 as_bad (BAD_BRANCH_OFF
);
14270 int immA
= (val
& 0x0001f000) >> 12;
14271 int immB
= (val
& 0x00000ffc) >> 2;
14272 int immC
= (val
& 0x00000002) >> 1;
14273 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14277 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14278 inst
.relocs
[1].pc_rel
= 1;
14283 if (inst
.operands
[1].hasreloc
== 0)
14285 int val
= inst
.operands
[1].imm
;
14286 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14287 as_bad (BAD_BRANCH_OFF
);
14289 int immA
= (val
& 0x0007f000) >> 12;
14290 int immB
= (val
& 0x00000ffc) >> 2;
14291 int immC
= (val
& 0x00000002) >> 1;
14292 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14296 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14297 inst
.relocs
[1].pc_rel
= 1;
14301 case T_MNEM_bfcsel
:
14303 if (inst
.operands
[1].hasreloc
== 0)
14305 int val
= inst
.operands
[1].imm
;
14306 int immA
= (val
& 0x00001000) >> 12;
14307 int immB
= (val
& 0x00000ffc) >> 2;
14308 int immC
= (val
& 0x00000002) >> 1;
14309 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14313 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14314 inst
.relocs
[1].pc_rel
= 1;
14318 if (inst
.operands
[2].hasreloc
== 0)
14320 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14321 int val2
= inst
.operands
[2].imm
;
14322 int val0
= inst
.operands
[0].imm
& 0x1f;
14323 int diff
= val2
- val0
;
14325 inst
.instruction
|= 1 << 17; /* T bit. */
14326 else if (diff
!= 2)
14327 as_bad (_("out of range label-relative fixup value"));
14331 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14332 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14333 inst
.relocs
[2].pc_rel
= 1;
14337 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14338 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14343 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14350 /* Helper function for do_t_loloop to handle relocations. */
14352 v8_1_loop_reloc (int is_le
)
14354 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14356 int value
= inst
.relocs
[0].exp
.X_add_number
;
14357 value
= (is_le
) ? -value
: value
;
14359 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14360 as_bad (BAD_BRANCH_OFF
);
14364 immh
= (value
& 0x00000ffc) >> 2;
14365 imml
= (value
& 0x00000002) >> 1;
14367 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14371 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14372 inst
.relocs
[0].pc_rel
= 1;
14376 /* For shifts with four operands in MVE. */
14378 do_mve_scalar_shift1 (void)
14380 unsigned int value
= inst
.operands
[2].imm
;
14382 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14383 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14385 /* Setting the bit for saturation. */
14386 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14388 /* Assuming Rm is already checked not to be 11x1. */
14389 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14390 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14391 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14394 /* For shifts in MVE. */
14396 do_mve_scalar_shift (void)
14398 if (!inst
.operands
[2].present
)
14400 inst
.operands
[2] = inst
.operands
[1];
14401 inst
.operands
[1].reg
= 0xf;
14404 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14405 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14407 if (inst
.operands
[2].isreg
)
14409 /* Assuming Rm is already checked not to be 11x1. */
14410 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14411 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14412 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14416 /* Assuming imm is already checked as [1,32]. */
14417 unsigned int value
= inst
.operands
[2].imm
;
14418 inst
.instruction
|= (value
& 0x1c) << 10;
14419 inst
.instruction
|= (value
& 0x03) << 6;
14420 /* Change last 4 bits from 0xd to 0xf. */
14421 inst
.instruction
|= 0x2;
14425 /* MVE instruction encoder helpers. */
14426 #define M_MNEM_vabav 0xee800f01
14427 #define M_MNEM_vmladav 0xeef00e00
14428 #define M_MNEM_vmladava 0xeef00e20
14429 #define M_MNEM_vmladavx 0xeef01e00
14430 #define M_MNEM_vmladavax 0xeef01e20
14431 #define M_MNEM_vmlsdav 0xeef00e01
14432 #define M_MNEM_vmlsdava 0xeef00e21
14433 #define M_MNEM_vmlsdavx 0xeef01e01
14434 #define M_MNEM_vmlsdavax 0xeef01e21
14435 #define M_MNEM_vmullt 0xee011e00
14436 #define M_MNEM_vmullb 0xee010e00
14437 #define M_MNEM_vctp 0xf000e801
14438 #define M_MNEM_vst20 0xfc801e00
14439 #define M_MNEM_vst21 0xfc801e20
14440 #define M_MNEM_vst40 0xfc801e01
14441 #define M_MNEM_vst41 0xfc801e21
14442 #define M_MNEM_vst42 0xfc801e41
14443 #define M_MNEM_vst43 0xfc801e61
14444 #define M_MNEM_vld20 0xfc901e00
14445 #define M_MNEM_vld21 0xfc901e20
14446 #define M_MNEM_vld40 0xfc901e01
14447 #define M_MNEM_vld41 0xfc901e21
14448 #define M_MNEM_vld42 0xfc901e41
14449 #define M_MNEM_vld43 0xfc901e61
14450 #define M_MNEM_vstrb 0xec000e00
14451 #define M_MNEM_vstrh 0xec000e10
14452 #define M_MNEM_vstrw 0xec000e40
14453 #define M_MNEM_vstrd 0xec000e50
14454 #define M_MNEM_vldrb 0xec100e00
14455 #define M_MNEM_vldrh 0xec100e10
14456 #define M_MNEM_vldrw 0xec100e40
14457 #define M_MNEM_vldrd 0xec100e50
14458 #define M_MNEM_vmovlt 0xeea01f40
14459 #define M_MNEM_vmovlb 0xeea00f40
14460 #define M_MNEM_vmovnt 0xfe311e81
14461 #define M_MNEM_vmovnb 0xfe310e81
14462 #define M_MNEM_vadc 0xee300f00
14463 #define M_MNEM_vadci 0xee301f00
14464 #define M_MNEM_vbrsr 0xfe011e60
14465 #define M_MNEM_vaddlv 0xee890f00
14466 #define M_MNEM_vaddlva 0xee890f20
14467 #define M_MNEM_vaddv 0xeef10f00
14468 #define M_MNEM_vaddva 0xeef10f20
14469 #define M_MNEM_vddup 0xee011f6e
14470 #define M_MNEM_vdwdup 0xee011f60
14471 #define M_MNEM_vidup 0xee010f6e
14472 #define M_MNEM_viwdup 0xee010f60
14473 #define M_MNEM_vmaxv 0xeee20f00
14474 #define M_MNEM_vmaxav 0xeee00f00
14475 #define M_MNEM_vminv 0xeee20f80
14476 #define M_MNEM_vminav 0xeee00f80
14477 #define M_MNEM_vmlaldav 0xee800e00
14478 #define M_MNEM_vmlaldava 0xee800e20
14479 #define M_MNEM_vmlaldavx 0xee801e00
14480 #define M_MNEM_vmlaldavax 0xee801e20
14481 #define M_MNEM_vmlsldav 0xee800e01
14482 #define M_MNEM_vmlsldava 0xee800e21
14483 #define M_MNEM_vmlsldavx 0xee801e01
14484 #define M_MNEM_vmlsldavax 0xee801e21
14485 #define M_MNEM_vrmlaldavhx 0xee801f00
14486 #define M_MNEM_vrmlaldavhax 0xee801f20
14487 #define M_MNEM_vrmlsldavh 0xfe800e01
14488 #define M_MNEM_vrmlsldavha 0xfe800e21
14489 #define M_MNEM_vrmlsldavhx 0xfe801e01
14490 #define M_MNEM_vrmlsldavhax 0xfe801e21
14491 #define M_MNEM_vqmovnt 0xee331e01
14492 #define M_MNEM_vqmovnb 0xee330e01
14493 #define M_MNEM_vqmovunt 0xee311e81
14494 #define M_MNEM_vqmovunb 0xee310e81
14495 #define M_MNEM_vshrnt 0xee801fc1
14496 #define M_MNEM_vshrnb 0xee800fc1
14497 #define M_MNEM_vrshrnt 0xfe801fc1
14498 #define M_MNEM_vqshrnt 0xee801f40
14499 #define M_MNEM_vqshrnb 0xee800f40
14500 #define M_MNEM_vqshrunt 0xee801fc0
14501 #define M_MNEM_vqshrunb 0xee800fc0
14502 #define M_MNEM_vrshrnb 0xfe800fc1
14503 #define M_MNEM_vqrshrnt 0xee801f41
14504 #define M_MNEM_vqrshrnb 0xee800f41
14505 #define M_MNEM_vqrshrunt 0xfe801fc0
14506 #define M_MNEM_vqrshrunb 0xfe800fc0
14508 /* Neon instruction encoder helpers. */
14510 /* Encodings for the different types for various Neon opcodes. */
14512 /* An "invalid" code for the following tables. */
14515 struct neon_tab_entry
14518 unsigned float_or_poly
;
14519 unsigned scalar_or_imm
;
14522 /* Map overloaded Neon opcodes to their respective encodings. */
14523 #define NEON_ENC_TAB \
14524 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14525 X(vabdl, 0x0800700, N_INV, N_INV), \
14526 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14527 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14528 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14529 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14530 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14531 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14532 X(vaddl, 0x0800000, N_INV, N_INV), \
14533 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14534 X(vsubl, 0x0800200, N_INV, N_INV), \
14535 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14536 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14537 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14538 /* Register variants of the following two instructions are encoded as
14539 vcge / vcgt with the operands reversed. */ \
14540 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14541 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14542 X(vfma, N_INV, 0x0000c10, N_INV), \
14543 X(vfms, N_INV, 0x0200c10, N_INV), \
14544 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14545 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14546 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14547 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14548 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14549 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14550 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14551 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14552 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14553 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14554 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14555 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14556 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14557 X(vshl, 0x0000400, N_INV, 0x0800510), \
14558 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14559 X(vand, 0x0000110, N_INV, 0x0800030), \
14560 X(vbic, 0x0100110, N_INV, 0x0800030), \
14561 X(veor, 0x1000110, N_INV, N_INV), \
14562 X(vorn, 0x0300110, N_INV, 0x0800010), \
14563 X(vorr, 0x0200110, N_INV, 0x0800010), \
14564 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14565 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14566 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14567 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14568 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14569 X(vst1, 0x0000000, 0x0800000, N_INV), \
14570 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14571 X(vst2, 0x0000100, 0x0800100, N_INV), \
14572 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14573 X(vst3, 0x0000200, 0x0800200, N_INV), \
14574 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14575 X(vst4, 0x0000300, 0x0800300, N_INV), \
14576 X(vmovn, 0x1b20200, N_INV, N_INV), \
14577 X(vtrn, 0x1b20080, N_INV, N_INV), \
14578 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14579 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14580 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14581 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14582 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14583 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14584 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14585 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14586 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14587 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14588 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14589 X(vseleq, 0xe000a00, N_INV, N_INV), \
14590 X(vselvs, 0xe100a00, N_INV, N_INV), \
14591 X(vselge, 0xe200a00, N_INV, N_INV), \
14592 X(vselgt, 0xe300a00, N_INV, N_INV), \
14593 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14594 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14595 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14596 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14597 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14598 X(aes, 0x3b00300, N_INV, N_INV), \
14599 X(sha3op, 0x2000c00, N_INV, N_INV), \
14600 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14601 X(sha2op, 0x3ba0380, N_INV, N_INV)
14605 #define X(OPC,I,F,S) N_MNEM_##OPC
14610 static const struct neon_tab_entry neon_enc_tab
[] =
14612 #define X(OPC,I,F,S) { (I), (F), (S) }
14617 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14618 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14619 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14620 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14621 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14622 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14623 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14624 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14625 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14626 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14627 #define NEON_ENC_SINGLE_(X) \
14628 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14629 #define NEON_ENC_DOUBLE_(X) \
14630 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14631 #define NEON_ENC_FPV8_(X) \
14632 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14634 #define NEON_ENCODE(type, inst) \
14637 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14638 inst.is_neon = 1; \
14642 #define check_neon_suffixes \
14645 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14647 as_bad (_("invalid neon suffix for non neon instruction")); \
14653 /* Define shapes for instruction operands. The following mnemonic characters
14654 are used in this table:
14656 F - VFP S<n> register
14657 D - Neon D<n> register
14658 Q - Neon Q<n> register
14662 L - D<n> register list
14664 This table is used to generate various data:
14665 - enumerations of the form NS_DDR to be used as arguments to
14667 - a table classifying shapes into single, double, quad, mixed.
14668 - a table used to drive neon_select_shape. */
14670 #define NEON_SHAPE_DEF \
14671 X(4, (R, R, Q, Q), QUAD), \
14672 X(4, (Q, R, R, I), QUAD), \
14673 X(4, (R, R, S, S), QUAD), \
14674 X(4, (S, S, R, R), QUAD), \
14675 X(3, (Q, R, I), QUAD), \
14676 X(3, (I, Q, Q), QUAD), \
14677 X(3, (I, Q, R), QUAD), \
14678 X(3, (R, Q, Q), QUAD), \
14679 X(3, (D, D, D), DOUBLE), \
14680 X(3, (Q, Q, Q), QUAD), \
14681 X(3, (D, D, I), DOUBLE), \
14682 X(3, (Q, Q, I), QUAD), \
14683 X(3, (D, D, S), DOUBLE), \
14684 X(3, (Q, Q, S), QUAD), \
14685 X(3, (Q, Q, R), QUAD), \
14686 X(3, (R, R, Q), QUAD), \
14687 X(2, (R, Q), QUAD), \
14688 X(2, (D, D), DOUBLE), \
14689 X(2, (Q, Q), QUAD), \
14690 X(2, (D, S), DOUBLE), \
14691 X(2, (Q, S), QUAD), \
14692 X(2, (D, R), DOUBLE), \
14693 X(2, (Q, R), QUAD), \
14694 X(2, (D, I), DOUBLE), \
14695 X(2, (Q, I), QUAD), \
14696 X(3, (D, L, D), DOUBLE), \
14697 X(2, (D, Q), MIXED), \
14698 X(2, (Q, D), MIXED), \
14699 X(3, (D, Q, I), MIXED), \
14700 X(3, (Q, D, I), MIXED), \
14701 X(3, (Q, D, D), MIXED), \
14702 X(3, (D, Q, Q), MIXED), \
14703 X(3, (Q, Q, D), MIXED), \
14704 X(3, (Q, D, S), MIXED), \
14705 X(3, (D, Q, S), MIXED), \
14706 X(4, (D, D, D, I), DOUBLE), \
14707 X(4, (Q, Q, Q, I), QUAD), \
14708 X(4, (D, D, S, I), DOUBLE), \
14709 X(4, (Q, Q, S, I), QUAD), \
14710 X(2, (F, F), SINGLE), \
14711 X(3, (F, F, F), SINGLE), \
14712 X(2, (F, I), SINGLE), \
14713 X(2, (F, D), MIXED), \
14714 X(2, (D, F), MIXED), \
14715 X(3, (F, F, I), MIXED), \
14716 X(4, (R, R, F, F), SINGLE), \
14717 X(4, (F, F, R, R), SINGLE), \
14718 X(3, (D, R, R), DOUBLE), \
14719 X(3, (R, R, D), DOUBLE), \
14720 X(2, (S, R), SINGLE), \
14721 X(2, (R, S), SINGLE), \
14722 X(2, (F, R), SINGLE), \
14723 X(2, (R, F), SINGLE), \
14724 /* Used for MVE tail predicated loop instructions. */\
14725 X(2, (R, R), QUAD), \
14726 /* Half float shape supported so far. */\
14727 X (2, (H, D), MIXED), \
14728 X (2, (D, H), MIXED), \
14729 X (2, (H, F), MIXED), \
14730 X (2, (F, H), MIXED), \
14731 X (2, (H, H), HALF), \
14732 X (2, (H, R), HALF), \
14733 X (2, (R, H), HALF), \
14734 X (2, (H, I), HALF), \
14735 X (3, (H, H, H), HALF), \
14736 X (3, (H, F, I), MIXED), \
14737 X (3, (F, H, I), MIXED), \
14738 X (3, (D, H, H), MIXED), \
14739 X (3, (D, H, S), MIXED)
14741 #define S2(A,B) NS_##A##B
14742 #define S3(A,B,C) NS_##A##B##C
14743 #define S4(A,B,C,D) NS_##A##B##C##D
14745 #define X(N, L, C) S##N L
14758 enum neon_shape_class
14767 #define X(N, L, C) SC_##C
14769 static enum neon_shape_class neon_shape_class
[] =
14788 /* Register widths of above. */
14789 static unsigned neon_shape_el_size
[] =
14801 struct neon_shape_info
14804 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14807 #define S2(A,B) { SE_##A, SE_##B }
14808 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14809 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14811 #define X(N, L, C) { N, S##N L }
14813 static struct neon_shape_info neon_shape_tab
[] =
14823 /* Bit masks used in type checking given instructions.
14824 'N_EQK' means the type must be the same as (or based on in some way) the key
14825 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14826 set, various other bits can be set as well in order to modify the meaning of
14827 the type constraint. */
14829 enum neon_type_mask
14853 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14854 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14855 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14856 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14857 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14858 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14859 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14860 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14861 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14862 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14863 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14865 N_MAX_NONSPECIAL
= N_P64
14868 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14870 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14871 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14872 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14873 #define N_S_32 (N_S8 | N_S16 | N_S32)
14874 #define N_F_16_32 (N_F16 | N_F32)
14875 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14876 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14877 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14878 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14879 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14880 #define N_F_MVE (N_F16 | N_F32)
14881 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14883 /* Pass this as the first type argument to neon_check_type to ignore types
14885 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14887 /* Select a "shape" for the current instruction (describing register types or
14888 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14889 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14890 function of operand parsing, so this function doesn't need to be called.
14891 Shapes should be listed in order of decreasing length. */
14893 static enum neon_shape
14894 neon_select_shape (enum neon_shape shape
, ...)
14897 enum neon_shape first_shape
= shape
;
14899 /* Fix missing optional operands. FIXME: we don't know at this point how
14900 many arguments we should have, so this makes the assumption that we have
14901 > 1. This is true of all current Neon opcodes, I think, but may not be
14902 true in the future. */
14903 if (!inst
.operands
[1].present
)
14904 inst
.operands
[1] = inst
.operands
[0];
14906 va_start (ap
, shape
);
14908 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14913 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14915 if (!inst
.operands
[j
].present
)
14921 switch (neon_shape_tab
[shape
].el
[j
])
14923 /* If a .f16, .16, .u16, .s16 type specifier is given over
14924 a VFP single precision register operand, it's essentially
14925 means only half of the register is used.
14927 If the type specifier is given after the mnemonics, the
14928 information is stored in inst.vectype. If the type specifier
14929 is given after register operand, the information is stored
14930 in inst.operands[].vectype.
14932 When there is only one type specifier, and all the register
14933 operands are the same type of hardware register, the type
14934 specifier applies to all register operands.
14936 If no type specifier is given, the shape is inferred from
14937 operand information.
14940 vadd.f16 s0, s1, s2: NS_HHH
14941 vabs.f16 s0, s1: NS_HH
14942 vmov.f16 s0, r1: NS_HR
14943 vmov.f16 r0, s1: NS_RH
14944 vcvt.f16 r0, s1: NS_RH
14945 vcvt.f16.s32 s2, s2, #29: NS_HFI
14946 vcvt.f16.s32 s2, s2: NS_HF
14949 if (!(inst
.operands
[j
].isreg
14950 && inst
.operands
[j
].isvec
14951 && inst
.operands
[j
].issingle
14952 && !inst
.operands
[j
].isquad
14953 && ((inst
.vectype
.elems
== 1
14954 && inst
.vectype
.el
[0].size
== 16)
14955 || (inst
.vectype
.elems
> 1
14956 && inst
.vectype
.el
[j
].size
== 16)
14957 || (inst
.vectype
.elems
== 0
14958 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14959 && inst
.operands
[j
].vectype
.size
== 16))))
14964 if (!(inst
.operands
[j
].isreg
14965 && inst
.operands
[j
].isvec
14966 && inst
.operands
[j
].issingle
14967 && !inst
.operands
[j
].isquad
14968 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14969 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14970 || (inst
.vectype
.elems
== 0
14971 && (inst
.operands
[j
].vectype
.size
== 32
14972 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14977 if (!(inst
.operands
[j
].isreg
14978 && inst
.operands
[j
].isvec
14979 && !inst
.operands
[j
].isquad
14980 && !inst
.operands
[j
].issingle
))
14985 if (!(inst
.operands
[j
].isreg
14986 && !inst
.operands
[j
].isvec
))
14991 if (!(inst
.operands
[j
].isreg
14992 && inst
.operands
[j
].isvec
14993 && inst
.operands
[j
].isquad
14994 && !inst
.operands
[j
].issingle
))
14999 if (!(!inst
.operands
[j
].isreg
15000 && !inst
.operands
[j
].isscalar
))
15005 if (!(!inst
.operands
[j
].isreg
15006 && inst
.operands
[j
].isscalar
))
15016 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15017 /* We've matched all the entries in the shape table, and we don't
15018 have any left over operands which have not been matched. */
15024 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15025 first_error (_("invalid instruction shape"));
15030 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15031 means the Q bit should be set). */
15034 neon_quad (enum neon_shape shape
)
15036 return neon_shape_class
[shape
] == SC_QUAD
;
15040 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15043 /* Allow modification to be made to types which are constrained to be
15044 based on the key element, based on bits set alongside N_EQK. */
15045 if ((typebits
& N_EQK
) != 0)
15047 if ((typebits
& N_HLF
) != 0)
15049 else if ((typebits
& N_DBL
) != 0)
15051 if ((typebits
& N_SGN
) != 0)
15052 *g_type
= NT_signed
;
15053 else if ((typebits
& N_UNS
) != 0)
15054 *g_type
= NT_unsigned
;
15055 else if ((typebits
& N_INT
) != 0)
15056 *g_type
= NT_integer
;
15057 else if ((typebits
& N_FLT
) != 0)
15058 *g_type
= NT_float
;
15059 else if ((typebits
& N_SIZ
) != 0)
15060 *g_type
= NT_untyped
;
15064 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15065 operand type, i.e. the single type specified in a Neon instruction when it
15066 is the only one given. */
15068 static struct neon_type_el
15069 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15071 struct neon_type_el dest
= *key
;
15073 gas_assert ((thisarg
& N_EQK
) != 0);
15075 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15080 /* Convert Neon type and size into compact bitmask representation. */
15082 static enum neon_type_mask
15083 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15090 case 8: return N_8
;
15091 case 16: return N_16
;
15092 case 32: return N_32
;
15093 case 64: return N_64
;
15101 case 8: return N_I8
;
15102 case 16: return N_I16
;
15103 case 32: return N_I32
;
15104 case 64: return N_I64
;
15112 case 16: return N_F16
;
15113 case 32: return N_F32
;
15114 case 64: return N_F64
;
15122 case 8: return N_P8
;
15123 case 16: return N_P16
;
15124 case 64: return N_P64
;
15132 case 8: return N_S8
;
15133 case 16: return N_S16
;
15134 case 32: return N_S32
;
15135 case 64: return N_S64
;
15143 case 8: return N_U8
;
15144 case 16: return N_U16
;
15145 case 32: return N_U32
;
15146 case 64: return N_U64
;
15157 /* Convert compact Neon bitmask type representation to a type and size. Only
15158 handles the case where a single bit is set in the mask. */
15161 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15162 enum neon_type_mask mask
)
15164 if ((mask
& N_EQK
) != 0)
15167 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15169 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
15171 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15173 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15178 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15180 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15181 *type
= NT_unsigned
;
15182 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15183 *type
= NT_integer
;
15184 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15185 *type
= NT_untyped
;
15186 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15188 else if ((mask
& (N_F_ALL
)) != 0)
15196 /* Modify a bitmask of allowed types. This is only needed for type
15200 modify_types_allowed (unsigned allowed
, unsigned mods
)
15203 enum neon_el_type type
;
15209 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15211 if (el_type_of_type_chk (&type
, &size
,
15212 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15214 neon_modify_type_size (mods
, &type
, &size
);
15215 destmask
|= type_chk_of_el_type (type
, size
);
15222 /* Check type and return type classification.
15223 The manual states (paraphrase): If one datatype is given, it indicates the
15225 - the second operand, if there is one
15226 - the operand, if there is no second operand
15227 - the result, if there are no operands.
15228 This isn't quite good enough though, so we use a concept of a "key" datatype
15229 which is set on a per-instruction basis, which is the one which matters when
15230 only one data type is written.
15231 Note: this function has side-effects (e.g. filling in missing operands). All
15232 Neon instructions should call it before performing bit encoding. */
15234 static struct neon_type_el
15235 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15238 unsigned i
, pass
, key_el
= 0;
15239 unsigned types
[NEON_MAX_TYPE_ELS
];
15240 enum neon_el_type k_type
= NT_invtype
;
15241 unsigned k_size
= -1u;
15242 struct neon_type_el badtype
= {NT_invtype
, -1};
15243 unsigned key_allowed
= 0;
15245 /* Optional registers in Neon instructions are always (not) in operand 1.
15246 Fill in the missing operand here, if it was omitted. */
15247 if (els
> 1 && !inst
.operands
[1].present
)
15248 inst
.operands
[1] = inst
.operands
[0];
15250 /* Suck up all the varargs. */
15252 for (i
= 0; i
< els
; i
++)
15254 unsigned thisarg
= va_arg (ap
, unsigned);
15255 if (thisarg
== N_IGNORE_TYPE
)
15260 types
[i
] = thisarg
;
15261 if ((thisarg
& N_KEY
) != 0)
15266 if (inst
.vectype
.elems
> 0)
15267 for (i
= 0; i
< els
; i
++)
15268 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15270 first_error (_("types specified in both the mnemonic and operands"));
15274 /* Duplicate inst.vectype elements here as necessary.
15275 FIXME: No idea if this is exactly the same as the ARM assembler,
15276 particularly when an insn takes one register and one non-register
15278 if (inst
.vectype
.elems
== 1 && els
> 1)
15281 inst
.vectype
.elems
= els
;
15282 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15283 for (j
= 0; j
< els
; j
++)
15285 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15288 else if (inst
.vectype
.elems
== 0 && els
> 0)
15291 /* No types were given after the mnemonic, so look for types specified
15292 after each operand. We allow some flexibility here; as long as the
15293 "key" operand has a type, we can infer the others. */
15294 for (j
= 0; j
< els
; j
++)
15295 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15296 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15298 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15300 for (j
= 0; j
< els
; j
++)
15301 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15302 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15307 first_error (_("operand types can't be inferred"));
15311 else if (inst
.vectype
.elems
!= els
)
15313 first_error (_("type specifier has the wrong number of parts"));
15317 for (pass
= 0; pass
< 2; pass
++)
15319 for (i
= 0; i
< els
; i
++)
15321 unsigned thisarg
= types
[i
];
15322 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15323 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15324 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15325 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15327 /* Decay more-specific signed & unsigned types to sign-insensitive
15328 integer types if sign-specific variants are unavailable. */
15329 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15330 && (types_allowed
& N_SU_ALL
) == 0)
15331 g_type
= NT_integer
;
15333 /* If only untyped args are allowed, decay any more specific types to
15334 them. Some instructions only care about signs for some element
15335 sizes, so handle that properly. */
15336 if (((types_allowed
& N_UNT
) == 0)
15337 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15338 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15339 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15340 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15341 g_type
= NT_untyped
;
15345 if ((thisarg
& N_KEY
) != 0)
15349 key_allowed
= thisarg
& ~N_KEY
;
15351 /* Check architecture constraint on FP16 extension. */
15353 && k_type
== NT_float
15354 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15356 inst
.error
= _(BAD_FP16
);
15363 if ((thisarg
& N_VFP
) != 0)
15365 enum neon_shape_el regshape
;
15366 unsigned regwidth
, match
;
15368 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15371 first_error (_("invalid instruction shape"));
15374 regshape
= neon_shape_tab
[ns
].el
[i
];
15375 regwidth
= neon_shape_el_size
[regshape
];
15377 /* In VFP mode, operands must match register widths. If we
15378 have a key operand, use its width, else use the width of
15379 the current operand. */
15385 /* FP16 will use a single precision register. */
15386 if (regwidth
== 32 && match
== 16)
15388 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15392 inst
.error
= _(BAD_FP16
);
15397 if (regwidth
!= match
)
15399 first_error (_("operand size must match register width"));
15404 if ((thisarg
& N_EQK
) == 0)
15406 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15408 if ((given_type
& types_allowed
) == 0)
15410 first_error (BAD_SIMD_TYPE
);
15416 enum neon_el_type mod_k_type
= k_type
;
15417 unsigned mod_k_size
= k_size
;
15418 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15419 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15421 first_error (_("inconsistent types in Neon instruction"));
15429 return inst
.vectype
.el
[key_el
];
15432 /* Neon-style VFP instruction forwarding. */
15434 /* Thumb VFP instructions have 0xE in the condition field. */
15437 do_vfp_cond_or_thumb (void)
15442 inst
.instruction
|= 0xe0000000;
15444 inst
.instruction
|= inst
.cond
<< 28;
15447 /* Look up and encode a simple mnemonic, for use as a helper function for the
15448 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15449 etc. It is assumed that operand parsing has already been done, and that the
15450 operands are in the form expected by the given opcode (this isn't necessarily
15451 the same as the form in which they were parsed, hence some massaging must
15452 take place before this function is called).
15453 Checks current arch version against that in the looked-up opcode. */
15456 do_vfp_nsyn_opcode (const char *opname
)
15458 const struct asm_opcode
*opcode
;
15460 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15465 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15466 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15473 inst
.instruction
= opcode
->tvalue
;
15474 opcode
->tencode ();
15478 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15479 opcode
->aencode ();
15484 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15486 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15488 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15491 do_vfp_nsyn_opcode ("fadds");
15493 do_vfp_nsyn_opcode ("fsubs");
15495 /* ARMv8.2 fp16 instruction. */
15497 do_scalar_fp16_v82_encode ();
15502 do_vfp_nsyn_opcode ("faddd");
15504 do_vfp_nsyn_opcode ("fsubd");
15508 /* Check operand types to see if this is a VFP instruction, and if so call
15512 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15514 enum neon_shape rs
;
15515 struct neon_type_el et
;
15520 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15521 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15525 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15526 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15527 N_F_ALL
| N_KEY
| N_VFP
);
15534 if (et
.type
!= NT_invtype
)
15545 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15547 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15549 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15552 do_vfp_nsyn_opcode ("fmacs");
15554 do_vfp_nsyn_opcode ("fnmacs");
15556 /* ARMv8.2 fp16 instruction. */
15558 do_scalar_fp16_v82_encode ();
15563 do_vfp_nsyn_opcode ("fmacd");
15565 do_vfp_nsyn_opcode ("fnmacd");
15570 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15572 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15574 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15577 do_vfp_nsyn_opcode ("ffmas");
15579 do_vfp_nsyn_opcode ("ffnmas");
15581 /* ARMv8.2 fp16 instruction. */
15583 do_scalar_fp16_v82_encode ();
15588 do_vfp_nsyn_opcode ("ffmad");
15590 do_vfp_nsyn_opcode ("ffnmad");
15595 do_vfp_nsyn_mul (enum neon_shape rs
)
15597 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15599 do_vfp_nsyn_opcode ("fmuls");
15601 /* ARMv8.2 fp16 instruction. */
15603 do_scalar_fp16_v82_encode ();
15606 do_vfp_nsyn_opcode ("fmuld");
15610 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15612 int is_neg
= (inst
.instruction
& 0x80) != 0;
15613 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15615 if (rs
== NS_FF
|| rs
== NS_HH
)
15618 do_vfp_nsyn_opcode ("fnegs");
15620 do_vfp_nsyn_opcode ("fabss");
15622 /* ARMv8.2 fp16 instruction. */
15624 do_scalar_fp16_v82_encode ();
15629 do_vfp_nsyn_opcode ("fnegd");
15631 do_vfp_nsyn_opcode ("fabsd");
15635 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15636 insns belong to Neon, and are handled elsewhere. */
15639 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15641 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15645 do_vfp_nsyn_opcode ("fldmdbs");
15647 do_vfp_nsyn_opcode ("fldmias");
15652 do_vfp_nsyn_opcode ("fstmdbs");
15654 do_vfp_nsyn_opcode ("fstmias");
15659 do_vfp_nsyn_sqrt (void)
15661 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15662 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15664 if (rs
== NS_FF
|| rs
== NS_HH
)
15666 do_vfp_nsyn_opcode ("fsqrts");
15668 /* ARMv8.2 fp16 instruction. */
15670 do_scalar_fp16_v82_encode ();
15673 do_vfp_nsyn_opcode ("fsqrtd");
15677 do_vfp_nsyn_div (void)
15679 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15680 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15681 N_F_ALL
| N_KEY
| N_VFP
);
15683 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15685 do_vfp_nsyn_opcode ("fdivs");
15687 /* ARMv8.2 fp16 instruction. */
15689 do_scalar_fp16_v82_encode ();
15692 do_vfp_nsyn_opcode ("fdivd");
15696 do_vfp_nsyn_nmul (void)
15698 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15699 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15700 N_F_ALL
| N_KEY
| N_VFP
);
15702 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15704 NEON_ENCODE (SINGLE
, inst
);
15705 do_vfp_sp_dyadic ();
15707 /* ARMv8.2 fp16 instruction. */
15709 do_scalar_fp16_v82_encode ();
15713 NEON_ENCODE (DOUBLE
, inst
);
15714 do_vfp_dp_rd_rn_rm ();
15716 do_vfp_cond_or_thumb ();
15720 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15724 neon_logbits (unsigned x
)
15726 return ffs (x
) - 4;
15729 #define LOW4(R) ((R) & 0xf)
15730 #define HI1(R) (((R) >> 4) & 1)
15733 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15738 first_error (BAD_EL_TYPE
);
15741 switch (inst
.operands
[0].imm
)
15744 first_error (_("invalid condition"));
15766 /* only accept eq and ne. */
15767 if (inst
.operands
[0].imm
> 1)
15769 first_error (_("invalid condition"));
15772 return inst
.operands
[0].imm
;
15774 if (inst
.operands
[0].imm
== 0x2)
15776 else if (inst
.operands
[0].imm
== 0x8)
15780 first_error (_("invalid condition"));
15784 switch (inst
.operands
[0].imm
)
15787 first_error (_("invalid condition"));
15803 /* Should be unreachable. */
15807 /* For VCTP (create vector tail predicate) in MVE. */
15812 unsigned size
= 0x0;
15814 if (inst
.cond
> COND_ALWAYS
)
15815 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15817 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15819 /* This is a typical MVE instruction which has no type but have size 8, 16,
15820 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15821 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15822 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15823 dt
= inst
.vectype
.el
[0].size
;
15825 /* Setting this does not indicate an actual NEON instruction, but only
15826 indicates that the mnemonic accepts neon-style type suffixes. */
15840 first_error (_("Type is not allowed for this instruction"));
15842 inst
.instruction
|= size
<< 20;
15843 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15849 /* We are dealing with a vector predicated block. */
15850 if (inst
.operands
[0].present
)
15852 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15853 struct neon_type_el et
15854 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15857 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15859 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15861 if (et
.type
== NT_invtype
)
15864 if (et
.type
== NT_float
)
15866 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15868 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15869 inst
.instruction
|= (et
.size
== 16) << 28;
15870 inst
.instruction
|= 0x3 << 20;
15874 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15876 inst
.instruction
|= 1 << 28;
15877 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15880 if (inst
.operands
[2].isquad
)
15882 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15883 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15884 inst
.instruction
|= (fcond
& 0x2) >> 1;
15888 if (inst
.operands
[2].reg
== REG_SP
)
15889 as_tsktsk (MVE_BAD_SP
);
15890 inst
.instruction
|= 1 << 6;
15891 inst
.instruction
|= (fcond
& 0x2) << 4;
15892 inst
.instruction
|= inst
.operands
[2].reg
;
15894 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15895 inst
.instruction
|= (fcond
& 0x4) << 10;
15896 inst
.instruction
|= (fcond
& 0x1) << 7;
15899 set_pred_insn_type (VPT_INSN
);
15901 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15902 | ((inst
.instruction
& 0xe000) >> 13);
15903 now_pred
.warn_deprecated
= FALSE
;
15904 now_pred
.type
= VECTOR_PRED
;
15911 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15912 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15913 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15914 if (!inst
.operands
[2].present
)
15915 first_error (_("MVE vector or ARM register expected"));
15916 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15918 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15919 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15920 && inst
.operands
[1].isquad
)
15922 inst
.instruction
= N_MNEM_vcmp
;
15926 if (inst
.cond
> COND_ALWAYS
)
15927 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15929 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15931 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15932 struct neon_type_el et
15933 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15936 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15937 && !inst
.operands
[2].iszr
, BAD_PC
);
15939 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15941 inst
.instruction
= 0xee010f00;
15942 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15943 inst
.instruction
|= (fcond
& 0x4) << 10;
15944 inst
.instruction
|= (fcond
& 0x1) << 7;
15945 if (et
.type
== NT_float
)
15947 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15949 inst
.instruction
|= (et
.size
== 16) << 28;
15950 inst
.instruction
|= 0x3 << 20;
15954 inst
.instruction
|= 1 << 28;
15955 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15957 if (inst
.operands
[2].isquad
)
15959 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15960 inst
.instruction
|= (fcond
& 0x2) >> 1;
15961 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15965 if (inst
.operands
[2].reg
== REG_SP
)
15966 as_tsktsk (MVE_BAD_SP
);
15967 inst
.instruction
|= 1 << 6;
15968 inst
.instruction
|= (fcond
& 0x2) << 4;
15969 inst
.instruction
|= inst
.operands
[2].reg
;
15977 do_mve_vmaxa_vmina (void)
15979 if (inst
.cond
> COND_ALWAYS
)
15980 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15982 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15984 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15985 struct neon_type_el et
15986 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15989 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15990 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15991 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15992 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15997 do_mve_vfmas (void)
15999 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16000 struct neon_type_el et
16001 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16003 if (inst
.cond
> COND_ALWAYS
)
16004 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16006 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16008 if (inst
.operands
[2].reg
== REG_SP
)
16009 as_tsktsk (MVE_BAD_SP
);
16010 else if (inst
.operands
[2].reg
== REG_PC
)
16011 as_tsktsk (MVE_BAD_PC
);
16013 inst
.instruction
|= (et
.size
== 16) << 28;
16014 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16015 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16017 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16018 inst
.instruction
|= inst
.operands
[2].reg
;
16023 do_mve_viddup (void)
16025 if (inst
.cond
> COND_ALWAYS
)
16026 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16028 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16030 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16031 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16032 _("immediate must be either 1, 2, 4 or 8"));
16034 enum neon_shape rs
;
16035 struct neon_type_el et
;
16037 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16039 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16040 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16045 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16046 if (inst
.operands
[2].reg
== REG_SP
)
16047 as_tsktsk (MVE_BAD_SP
);
16048 else if (inst
.operands
[2].reg
== REG_PC
)
16049 first_error (BAD_PC
);
16051 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16052 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16053 Rm
= inst
.operands
[2].reg
>> 1;
16055 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16056 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16057 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16058 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16059 inst
.instruction
|= (imm
> 2) << 7;
16060 inst
.instruction
|= Rm
<< 1;
16061 inst
.instruction
|= (imm
== 2 || imm
== 8);
16066 do_mve_vmlas (void)
16068 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16069 struct neon_type_el et
16070 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16072 if (inst
.operands
[2].reg
== REG_PC
)
16073 as_tsktsk (MVE_BAD_PC
);
16074 else if (inst
.operands
[2].reg
== REG_SP
)
16075 as_tsktsk (MVE_BAD_SP
);
16077 if (inst
.cond
> COND_ALWAYS
)
16078 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16080 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16082 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16083 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16084 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16085 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16086 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16087 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16088 inst
.instruction
|= inst
.operands
[2].reg
;
16093 do_mve_vshll (void)
16095 struct neon_type_el et
16096 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16098 if (inst
.cond
> COND_ALWAYS
)
16099 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16101 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16103 int imm
= inst
.operands
[2].imm
;
16104 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16105 _("immediate value out of range"));
16107 if ((unsigned)imm
== et
.size
)
16109 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16110 inst
.instruction
|= 0x110001;
16114 inst
.instruction
|= (et
.size
+ imm
) << 16;
16115 inst
.instruction
|= 0x800140;
16118 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16119 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16120 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16121 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16122 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16127 do_mve_vshlc (void)
16129 if (inst
.cond
> COND_ALWAYS
)
16130 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16132 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16134 if (inst
.operands
[1].reg
== REG_PC
)
16135 as_tsktsk (MVE_BAD_PC
);
16136 else if (inst
.operands
[1].reg
== REG_SP
)
16137 as_tsktsk (MVE_BAD_SP
);
16139 int imm
= inst
.operands
[2].imm
;
16140 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16142 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16143 inst
.instruction
|= (imm
& 0x1f) << 16;
16144 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16145 inst
.instruction
|= inst
.operands
[1].reg
;
16150 do_mve_vshrn (void)
16153 switch (inst
.instruction
)
16155 case M_MNEM_vshrnt
:
16156 case M_MNEM_vshrnb
:
16157 case M_MNEM_vrshrnt
:
16158 case M_MNEM_vrshrnb
:
16159 types
= N_I16
| N_I32
;
16161 case M_MNEM_vqshrnt
:
16162 case M_MNEM_vqshrnb
:
16163 case M_MNEM_vqrshrnt
:
16164 case M_MNEM_vqrshrnb
:
16165 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16167 case M_MNEM_vqshrunt
:
16168 case M_MNEM_vqshrunb
:
16169 case M_MNEM_vqrshrunt
:
16170 case M_MNEM_vqrshrunb
:
16171 types
= N_S16
| N_S32
;
16177 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16179 if (inst
.cond
> COND_ALWAYS
)
16180 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16182 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16184 unsigned Qd
= inst
.operands
[0].reg
;
16185 unsigned Qm
= inst
.operands
[1].reg
;
16186 unsigned imm
= inst
.operands
[2].imm
;
16187 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16189 ? _("immediate operand expected in the range [1,8]")
16190 : _("immediate operand expected in the range [1,16]"));
16192 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16193 inst
.instruction
|= HI1 (Qd
) << 22;
16194 inst
.instruction
|= (et
.size
- imm
) << 16;
16195 inst
.instruction
|= LOW4 (Qd
) << 12;
16196 inst
.instruction
|= HI1 (Qm
) << 5;
16197 inst
.instruction
|= LOW4 (Qm
);
16202 do_mve_vqmovn (void)
16204 struct neon_type_el et
;
16205 if (inst
.instruction
== M_MNEM_vqmovnt
16206 || inst
.instruction
== M_MNEM_vqmovnb
)
16207 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16208 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16210 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16212 if (inst
.cond
> COND_ALWAYS
)
16213 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16215 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16217 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16219 inst
.instruction
|= (et
.size
== 32) << 18;
16220 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16221 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16222 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16227 do_mve_vpsel (void)
16229 neon_select_shape (NS_QQQ
, NS_NULL
);
16231 if (inst
.cond
> COND_ALWAYS
)
16232 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16234 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16236 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16237 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16239 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16240 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16241 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16246 do_mve_vpnot (void)
16248 if (inst
.cond
> COND_ALWAYS
)
16249 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16251 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16255 do_mve_vmaxnma_vminnma (void)
16257 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16258 struct neon_type_el et
16259 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16261 if (inst
.cond
> COND_ALWAYS
)
16262 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16264 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16266 inst
.instruction
|= (et
.size
== 16) << 28;
16267 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16268 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16269 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16270 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16275 do_mve_vcmul (void)
16277 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16278 struct neon_type_el et
16279 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16281 if (inst
.cond
> COND_ALWAYS
)
16282 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16284 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16286 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16287 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16288 _("immediate out of range"));
16290 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16291 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16292 as_tsktsk (BAD_MVE_SRCDEST
);
16294 inst
.instruction
|= (et
.size
== 32) << 28;
16295 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16296 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16297 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16298 inst
.instruction
|= (rot
> 90) << 12;
16299 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16300 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16301 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16302 inst
.instruction
|= (rot
== 90 || rot
== 270);
16306 /* To handle the Low Overhead Loop instructions
16307 in Armv8.1-M Mainline and MVE. */
16311 unsigned long insn
= inst
.instruction
;
16313 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16315 if (insn
== T_MNEM_lctp
)
16318 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16320 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16322 struct neon_type_el et
16323 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16324 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16331 constraint (!inst
.operands
[0].present
,
16333 /* fall through. */
16336 if (!inst
.operands
[0].present
)
16337 inst
.instruction
|= 1 << 21;
16339 v8_1_loop_reloc (TRUE
);
16344 v8_1_loop_reloc (FALSE
);
16345 /* fall through. */
16348 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16350 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16351 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16352 else if (inst
.operands
[1].reg
== REG_PC
)
16353 as_tsktsk (MVE_BAD_PC
);
16354 if (inst
.operands
[1].reg
== REG_SP
)
16355 as_tsktsk (MVE_BAD_SP
);
16357 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16367 do_vfp_nsyn_cmp (void)
16369 enum neon_shape rs
;
16370 if (!inst
.operands
[0].isreg
)
16377 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16378 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16382 if (inst
.operands
[1].isreg
)
16384 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16385 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16387 if (rs
== NS_FF
|| rs
== NS_HH
)
16389 NEON_ENCODE (SINGLE
, inst
);
16390 do_vfp_sp_monadic ();
16394 NEON_ENCODE (DOUBLE
, inst
);
16395 do_vfp_dp_rd_rm ();
16400 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16401 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16403 switch (inst
.instruction
& 0x0fffffff)
16406 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16409 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16415 if (rs
== NS_FI
|| rs
== NS_HI
)
16417 NEON_ENCODE (SINGLE
, inst
);
16418 do_vfp_sp_compare_z ();
16422 NEON_ENCODE (DOUBLE
, inst
);
16426 do_vfp_cond_or_thumb ();
16428 /* ARMv8.2 fp16 instruction. */
16429 if (rs
== NS_HI
|| rs
== NS_HH
)
16430 do_scalar_fp16_v82_encode ();
16434 nsyn_insert_sp (void)
16436 inst
.operands
[1] = inst
.operands
[0];
16437 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16438 inst
.operands
[0].reg
= REG_SP
;
16439 inst
.operands
[0].isreg
= 1;
16440 inst
.operands
[0].writeback
= 1;
16441 inst
.operands
[0].present
= 1;
16445 do_vfp_nsyn_push (void)
16449 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16450 _("register list must contain at least 1 and at most 16 "
16453 if (inst
.operands
[1].issingle
)
16454 do_vfp_nsyn_opcode ("fstmdbs");
16456 do_vfp_nsyn_opcode ("fstmdbd");
16460 do_vfp_nsyn_pop (void)
16464 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16465 _("register list must contain at least 1 and at most 16 "
16468 if (inst
.operands
[1].issingle
)
16469 do_vfp_nsyn_opcode ("fldmias");
16471 do_vfp_nsyn_opcode ("fldmiad");
16474 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16475 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16478 neon_dp_fixup (struct arm_it
* insn
)
16480 unsigned int i
= insn
->instruction
;
16485 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16496 insn
->instruction
= i
;
16500 mve_encode_qqr (int size
, int U
, int fp
)
16502 if (inst
.operands
[2].reg
== REG_SP
)
16503 as_tsktsk (MVE_BAD_SP
);
16504 else if (inst
.operands
[2].reg
== REG_PC
)
16505 as_tsktsk (MVE_BAD_PC
);
16510 if (((unsigned)inst
.instruction
) == 0xd00)
16511 inst
.instruction
= 0xee300f40;
16513 else if (((unsigned)inst
.instruction
) == 0x200d00)
16514 inst
.instruction
= 0xee301f40;
16516 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16517 inst
.instruction
= 0xee310e60;
16519 /* Setting size which is 1 for F16 and 0 for F32. */
16520 inst
.instruction
|= (size
== 16) << 28;
16525 if (((unsigned)inst
.instruction
) == 0x800)
16526 inst
.instruction
= 0xee010f40;
16528 else if (((unsigned)inst
.instruction
) == 0x1000800)
16529 inst
.instruction
= 0xee011f40;
16531 else if (((unsigned)inst
.instruction
) == 0)
16532 inst
.instruction
= 0xee000f40;
16534 else if (((unsigned)inst
.instruction
) == 0x200)
16535 inst
.instruction
= 0xee001f40;
16537 else if (((unsigned)inst
.instruction
) == 0x900)
16538 inst
.instruction
= 0xee010e40;
16540 else if (((unsigned)inst
.instruction
) == 0x910)
16541 inst
.instruction
= 0xee011e60;
16543 else if (((unsigned)inst
.instruction
) == 0x10)
16544 inst
.instruction
= 0xee000f60;
16546 else if (((unsigned)inst
.instruction
) == 0x210)
16547 inst
.instruction
= 0xee001f60;
16549 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16550 inst
.instruction
= 0xee000e40;
16552 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16553 inst
.instruction
= 0xee010e60;
16555 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16556 inst
.instruction
= 0xfe010e60;
16559 inst
.instruction
|= U
<< 28;
16561 /* Setting bits for size. */
16562 inst
.instruction
|= neon_logbits (size
) << 20;
16564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16568 inst
.instruction
|= inst
.operands
[2].reg
;
16573 mve_encode_rqq (unsigned bit28
, unsigned size
)
16575 inst
.instruction
|= bit28
<< 28;
16576 inst
.instruction
|= neon_logbits (size
) << 20;
16577 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16579 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16580 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16581 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16586 mve_encode_qqq (int ubit
, int size
)
16589 inst
.instruction
|= (ubit
!= 0) << 28;
16590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16591 inst
.instruction
|= neon_logbits (size
) << 20;
16592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16593 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16594 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16595 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16596 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16602 mve_encode_rq (unsigned bit28
, unsigned size
)
16604 inst
.instruction
|= bit28
<< 28;
16605 inst
.instruction
|= neon_logbits (size
) << 18;
16606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16612 mve_encode_rrqq (unsigned U
, unsigned size
)
16614 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16616 inst
.instruction
|= U
<< 28;
16617 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16618 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16619 inst
.instruction
|= (size
== 32) << 16;
16620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16621 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16622 inst
.instruction
|= inst
.operands
[3].reg
;
16626 /* Encode insns with bit pattern:
16628 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16629 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16631 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16632 different meaning for some instruction. */
16635 neon_three_same (int isquad
, int ubit
, int size
)
16637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16638 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16639 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16640 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16641 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16642 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16643 inst
.instruction
|= (isquad
!= 0) << 6;
16644 inst
.instruction
|= (ubit
!= 0) << 24;
16646 inst
.instruction
|= neon_logbits (size
) << 20;
16648 neon_dp_fixup (&inst
);
16651 /* Encode instructions of the form:
16653 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16654 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16656 Don't write size if SIZE == -1. */
16659 neon_two_same (int qbit
, int ubit
, int size
)
16661 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16662 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16663 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16664 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16665 inst
.instruction
|= (qbit
!= 0) << 6;
16666 inst
.instruction
|= (ubit
!= 0) << 24;
16669 inst
.instruction
|= neon_logbits (size
) << 18;
16671 neon_dp_fixup (&inst
);
16674 enum vfp_or_neon_is_neon_bits
16677 NEON_CHECK_ARCH
= 2,
16678 NEON_CHECK_ARCH8
= 4
16681 /* Call this function if an instruction which may have belonged to the VFP or
16682 Neon instruction sets, but turned out to be a Neon instruction (due to the
16683 operand types involved, etc.). We have to check and/or fix-up a couple of
16686 - Make sure the user hasn't attempted to make a Neon instruction
16688 - Alter the value in the condition code field if necessary.
16689 - Make sure that the arch supports Neon instructions.
16691 Which of these operations take place depends on bits from enum
16692 vfp_or_neon_is_neon_bits.
16694 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16695 current instruction's condition is COND_ALWAYS, the condition field is
16696 changed to inst.uncond_value. This is necessary because instructions shared
16697 between VFP and Neon may be conditional for the VFP variants only, and the
16698 unconditional Neon version must have, e.g., 0xF in the condition field. */
16701 vfp_or_neon_is_neon (unsigned check
)
16703 /* Conditions are always legal in Thumb mode (IT blocks). */
16704 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16706 if (inst
.cond
!= COND_ALWAYS
)
16708 first_error (_(BAD_COND
));
16711 if (inst
.uncond_value
!= -1)
16712 inst
.instruction
|= inst
.uncond_value
<< 28;
16716 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16717 || ((check
& NEON_CHECK_ARCH8
)
16718 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16720 first_error (_(BAD_FPU
));
16728 /* Return TRUE if the SIMD instruction is available for the current
16729 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16730 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16731 vfp_or_neon_is_neon for the NEON specific checks. */
16734 check_simd_pred_availability (int fp
, unsigned check
)
16736 if (inst
.cond
> COND_ALWAYS
)
16738 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16740 inst
.error
= BAD_FPU
;
16743 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16745 else if (inst
.cond
< COND_ALWAYS
)
16747 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16748 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16749 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16754 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16755 && vfp_or_neon_is_neon (check
) == FAIL
)
16758 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16759 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16764 /* Neon instruction encoders, in approximate order of appearance. */
16767 do_neon_dyadic_i_su (void)
16769 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16772 enum neon_shape rs
;
16773 struct neon_type_el et
;
16774 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16775 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16777 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16779 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16783 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16785 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16789 do_neon_dyadic_i64_su (void)
16791 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16793 enum neon_shape rs
;
16794 struct neon_type_el et
;
16795 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16797 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16798 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16802 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16803 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16806 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16808 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16812 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16815 unsigned size
= et
.size
>> 3;
16816 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16817 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16818 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16819 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16820 inst
.instruction
|= (isquad
!= 0) << 6;
16821 inst
.instruction
|= immbits
<< 16;
16822 inst
.instruction
|= (size
>> 3) << 7;
16823 inst
.instruction
|= (size
& 0x7) << 19;
16825 inst
.instruction
|= (uval
!= 0) << 24;
16827 neon_dp_fixup (&inst
);
16833 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16836 if (!inst
.operands
[2].isreg
)
16838 enum neon_shape rs
;
16839 struct neon_type_el et
;
16840 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16842 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16843 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16847 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16848 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16850 int imm
= inst
.operands
[2].imm
;
16852 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16853 _("immediate out of range for shift"));
16854 NEON_ENCODE (IMMED
, inst
);
16855 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16859 enum neon_shape rs
;
16860 struct neon_type_el et
;
16861 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16863 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16864 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16868 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16869 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16875 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16876 _("invalid instruction shape"));
16877 if (inst
.operands
[2].reg
== REG_SP
)
16878 as_tsktsk (MVE_BAD_SP
);
16879 else if (inst
.operands
[2].reg
== REG_PC
)
16880 as_tsktsk (MVE_BAD_PC
);
16882 inst
.instruction
= 0xee311e60;
16883 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16884 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16885 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16887 inst
.instruction
|= inst
.operands
[2].reg
;
16894 /* VSHL/VQSHL 3-register variants have syntax such as:
16896 whereas other 3-register operations encoded by neon_three_same have
16899 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16900 operands[2].reg here. */
16901 tmp
= inst
.operands
[2].reg
;
16902 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16903 inst
.operands
[1].reg
= tmp
;
16904 NEON_ENCODE (INTEGER
, inst
);
16905 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16911 do_neon_qshl (void)
16913 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16916 if (!inst
.operands
[2].isreg
)
16918 enum neon_shape rs
;
16919 struct neon_type_el et
;
16920 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16922 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16923 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16927 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16928 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16930 int imm
= inst
.operands
[2].imm
;
16932 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16933 _("immediate out of range for shift"));
16934 NEON_ENCODE (IMMED
, inst
);
16935 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16939 enum neon_shape rs
;
16940 struct neon_type_el et
;
16942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16944 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16945 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16949 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16950 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16955 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16956 _("invalid instruction shape"));
16957 if (inst
.operands
[2].reg
== REG_SP
)
16958 as_tsktsk (MVE_BAD_SP
);
16959 else if (inst
.operands
[2].reg
== REG_PC
)
16960 as_tsktsk (MVE_BAD_PC
);
16962 inst
.instruction
= 0xee311ee0;
16963 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16964 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16965 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16966 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16967 inst
.instruction
|= inst
.operands
[2].reg
;
16974 /* See note in do_neon_shl. */
16975 tmp
= inst
.operands
[2].reg
;
16976 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16977 inst
.operands
[1].reg
= tmp
;
16978 NEON_ENCODE (INTEGER
, inst
);
16979 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16985 do_neon_rshl (void)
16987 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16990 enum neon_shape rs
;
16991 struct neon_type_el et
;
16992 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16994 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16995 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16999 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17000 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17007 if (inst
.operands
[2].reg
== REG_PC
)
17008 as_tsktsk (MVE_BAD_PC
);
17009 else if (inst
.operands
[2].reg
== REG_SP
)
17010 as_tsktsk (MVE_BAD_SP
);
17012 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17013 _("invalid instruction shape"));
17015 if (inst
.instruction
== 0x0000510)
17016 /* We are dealing with vqrshl. */
17017 inst
.instruction
= 0xee331ee0;
17019 /* We are dealing with vrshl. */
17020 inst
.instruction
= 0xee331e60;
17022 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17024 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17025 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17026 inst
.instruction
|= inst
.operands
[2].reg
;
17031 tmp
= inst
.operands
[2].reg
;
17032 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17033 inst
.operands
[1].reg
= tmp
;
17034 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17039 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17041 /* Handle .I8 pseudo-instructions. */
17044 /* Unfortunately, this will make everything apart from zero out-of-range.
17045 FIXME is this the intended semantics? There doesn't seem much point in
17046 accepting .I8 if so. */
17047 immediate
|= immediate
<< 8;
17053 if (immediate
== (immediate
& 0x000000ff))
17055 *immbits
= immediate
;
17058 else if (immediate
== (immediate
& 0x0000ff00))
17060 *immbits
= immediate
>> 8;
17063 else if (immediate
== (immediate
& 0x00ff0000))
17065 *immbits
= immediate
>> 16;
17068 else if (immediate
== (immediate
& 0xff000000))
17070 *immbits
= immediate
>> 24;
17073 if ((immediate
& 0xffff) != (immediate
>> 16))
17074 goto bad_immediate
;
17075 immediate
&= 0xffff;
17078 if (immediate
== (immediate
& 0x000000ff))
17080 *immbits
= immediate
;
17083 else if (immediate
== (immediate
& 0x0000ff00))
17085 *immbits
= immediate
>> 8;
17090 first_error (_("immediate value out of range"));
17095 do_neon_logic (void)
17097 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17099 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17101 && !check_simd_pred_availability (FALSE
,
17102 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17104 else if (rs
!= NS_QQQ
17105 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17106 first_error (BAD_FPU
);
17108 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17109 /* U bit and size field were set as part of the bitmask. */
17110 NEON_ENCODE (INTEGER
, inst
);
17111 neon_three_same (neon_quad (rs
), 0, -1);
17115 const int three_ops_form
= (inst
.operands
[2].present
17116 && !inst
.operands
[2].isreg
);
17117 const int immoperand
= (three_ops_form
? 2 : 1);
17118 enum neon_shape rs
= (three_ops_form
17119 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17120 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17121 /* Because neon_select_shape makes the second operand a copy of the first
17122 if the second operand is not present. */
17124 && !check_simd_pred_availability (FALSE
,
17125 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17127 else if (rs
!= NS_QQI
17128 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17129 first_error (BAD_FPU
);
17131 struct neon_type_el et
;
17132 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17133 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17135 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17138 if (et
.type
== NT_invtype
)
17140 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17145 if (three_ops_form
)
17146 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17147 _("first and second operands shall be the same register"));
17149 NEON_ENCODE (IMMED
, inst
);
17151 immbits
= inst
.operands
[immoperand
].imm
;
17154 /* .i64 is a pseudo-op, so the immediate must be a repeating
17156 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17157 inst
.operands
[immoperand
].reg
: 0))
17159 /* Set immbits to an invalid constant. */
17160 immbits
= 0xdeadbeef;
17167 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17171 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17175 /* Pseudo-instruction for VBIC. */
17176 neon_invert_size (&immbits
, 0, et
.size
);
17177 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17181 /* Pseudo-instruction for VORR. */
17182 neon_invert_size (&immbits
, 0, et
.size
);
17183 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17193 inst
.instruction
|= neon_quad (rs
) << 6;
17194 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17195 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17196 inst
.instruction
|= cmode
<< 8;
17197 neon_write_immbits (immbits
);
17199 neon_dp_fixup (&inst
);
17204 do_neon_bitfield (void)
17206 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17207 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17208 neon_three_same (neon_quad (rs
), 0, -1);
17212 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17215 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17216 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17218 if (et
.type
== NT_float
)
17220 NEON_ENCODE (FLOAT
, inst
);
17222 mve_encode_qqr (et
.size
, 0, 1);
17224 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17228 NEON_ENCODE (INTEGER
, inst
);
17230 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17232 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17238 do_neon_dyadic_if_su_d (void)
17240 /* This version only allow D registers, but that constraint is enforced during
17241 operand parsing so we don't need to do anything extra here. */
17242 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17246 do_neon_dyadic_if_i_d (void)
17248 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17249 affected if we specify unsigned args. */
17250 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17254 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17256 constraint (size
< 32, BAD_ADDR_MODE
);
17257 constraint (size
!= elsize
, BAD_EL_TYPE
);
17258 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17259 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17260 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17261 _("destination register and offset register may not be the"
17264 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17271 constraint ((imm
% (size
/ 8) != 0)
17272 || imm
> (0x7f << neon_logbits (size
)),
17273 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17274 " range of +/-[0,508]")
17275 : _("immediate must be a multiple of 8 in the"
17276 " range of +/-[0,1016]"));
17277 inst
.instruction
|= 0x11 << 24;
17278 inst
.instruction
|= add
<< 23;
17279 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17280 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17281 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17282 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17283 inst
.instruction
|= 1 << 12;
17284 inst
.instruction
|= (size
== 64) << 8;
17285 inst
.instruction
&= 0xffffff00;
17286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17287 inst
.instruction
|= imm
>> neon_logbits (size
);
17291 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17293 unsigned os
= inst
.operands
[1].imm
>> 5;
17294 unsigned type
= inst
.vectype
.el
[0].type
;
17295 constraint (os
!= 0 && size
== 8,
17296 _("can not shift offsets when accessing less than half-word"));
17297 constraint (os
&& os
!= neon_logbits (size
),
17298 _("shift immediate must be 1, 2 or 3 for half-word, word"
17299 " or double-word accesses respectively"));
17300 if (inst
.operands
[1].reg
== REG_PC
)
17301 as_tsktsk (MVE_BAD_PC
);
17306 constraint (elsize
>= 64, BAD_EL_TYPE
);
17309 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17313 constraint (elsize
!= size
, BAD_EL_TYPE
);
17318 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17322 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17323 _("destination register and offset register may not be"
17325 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17326 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17328 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17332 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17335 inst
.instruction
|= 1 << 23;
17336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17337 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17338 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17339 inst
.instruction
|= neon_logbits (elsize
) << 7;
17340 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17341 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17342 inst
.instruction
|= !!os
;
17346 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17348 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17350 constraint (size
>= 64, BAD_ADDR_MODE
);
17354 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17357 constraint (elsize
!= size
, BAD_EL_TYPE
);
17364 constraint (elsize
!= size
&& type
!= NT_unsigned
17365 && type
!= NT_signed
, BAD_EL_TYPE
);
17369 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17372 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17380 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17385 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17388 constraint (1, _("immediate must be a multiple of 2 in the"
17389 " range of +/-[0,254]"));
17392 constraint (1, _("immediate must be a multiple of 4 in the"
17393 " range of +/-[0,508]"));
17398 if (size
!= elsize
)
17400 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17401 constraint (inst
.operands
[0].reg
> 14,
17402 _("MVE vector register in the range [Q0..Q7] expected"));
17403 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17404 inst
.instruction
|= (size
== 16) << 19;
17405 inst
.instruction
|= neon_logbits (elsize
) << 7;
17409 if (inst
.operands
[1].reg
== REG_PC
)
17410 as_tsktsk (MVE_BAD_PC
);
17411 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17412 as_tsktsk (MVE_BAD_SP
);
17413 inst
.instruction
|= 1 << 12;
17414 inst
.instruction
|= neon_logbits (size
) << 7;
17416 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17417 inst
.instruction
|= add
<< 23;
17418 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17419 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17420 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17421 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17422 inst
.instruction
&= 0xffffff80;
17423 inst
.instruction
|= imm
>> neon_logbits (size
);
17428 do_mve_vstr_vldr (void)
17433 if (inst
.cond
> COND_ALWAYS
)
17434 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17436 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17438 switch (inst
.instruction
)
17445 /* fall through. */
17451 /* fall through. */
17457 /* fall through. */
17463 /* fall through. */
17468 unsigned elsize
= inst
.vectype
.el
[0].size
;
17470 if (inst
.operands
[1].isquad
)
17472 /* We are dealing with [Q, imm]{!} cases. */
17473 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17477 if (inst
.operands
[1].immisreg
== 2)
17479 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17480 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17482 else if (!inst
.operands
[1].immisreg
)
17484 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17485 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17488 constraint (1, BAD_ADDR_MODE
);
17495 do_mve_vst_vld (void)
17497 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17500 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17501 || inst
.relocs
[0].exp
.X_add_number
!= 0
17502 || inst
.operands
[1].immisreg
!= 0,
17504 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17505 if (inst
.operands
[1].reg
== REG_PC
)
17506 as_tsktsk (MVE_BAD_PC
);
17507 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17508 as_tsktsk (MVE_BAD_SP
);
17511 /* These instructions are one of the "exceptions" mentioned in
17512 handle_pred_state. They are MVE instructions that are not VPT compatible
17513 and do not accept a VPT code, thus appending such a code is a syntax
17515 if (inst
.cond
> COND_ALWAYS
)
17516 first_error (BAD_SYNTAX
);
17517 /* If we append a scalar condition code we can set this to
17518 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17519 else if (inst
.cond
< COND_ALWAYS
)
17520 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17522 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17524 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17525 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17527 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17528 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17533 do_mve_vaddlv (void)
17535 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17536 struct neon_type_el et
17537 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17539 if (et
.type
== NT_invtype
)
17540 first_error (BAD_EL_TYPE
);
17542 if (inst
.cond
> COND_ALWAYS
)
17543 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17545 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17547 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17549 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17550 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17552 inst
.instruction
|= inst
.operands
[2].reg
;
17557 do_neon_dyadic_if_su (void)
17559 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17560 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17563 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17564 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17565 && et
.type
== NT_float
17566 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17568 if (!check_simd_pred_availability (et
.type
== NT_float
,
17569 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17572 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17576 do_neon_addsub_if_i (void)
17578 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17579 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17582 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17583 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17584 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17586 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17587 /* If we are parsing Q registers and the element types match MVE, which NEON
17588 also supports, then we must check whether this is an instruction that can
17589 be used by both MVE/NEON. This distinction can be made based on whether
17590 they are predicated or not. */
17591 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17593 if (!check_simd_pred_availability (et
.type
== NT_float
,
17594 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17599 /* If they are either in a D register or are using an unsupported. */
17601 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17605 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17606 affected if we specify unsigned args. */
17607 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17610 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17612 V<op> A,B (A is operand 0, B is operand 2)
17617 so handle that case specially. */
17620 neon_exchange_operands (void)
17622 if (inst
.operands
[1].present
)
17624 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17626 /* Swap operands[1] and operands[2]. */
17627 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17628 inst
.operands
[1] = inst
.operands
[2];
17629 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17634 inst
.operands
[1] = inst
.operands
[2];
17635 inst
.operands
[2] = inst
.operands
[0];
17640 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17642 if (inst
.operands
[2].isreg
)
17645 neon_exchange_operands ();
17646 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17650 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17651 struct neon_type_el et
= neon_check_type (2, rs
,
17652 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17654 NEON_ENCODE (IMMED
, inst
);
17655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17659 inst
.instruction
|= neon_quad (rs
) << 6;
17660 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17661 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17663 neon_dp_fixup (&inst
);
17670 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17674 do_neon_cmp_inv (void)
17676 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17682 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17685 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17686 scalars, which are encoded in 5 bits, M : Rm.
17687 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17688 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17691 Dot Product instructions are similar to multiply instructions except elsize
17692 should always be 32.
17694 This function translates SCALAR, which is GAS's internal encoding of indexed
17695 scalar register, to raw encoding. There is also register and index range
17696 check based on ELSIZE. */
17699 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17701 unsigned regno
= NEON_SCALAR_REG (scalar
);
17702 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17707 if (regno
> 7 || elno
> 3)
17709 return regno
| (elno
<< 3);
17712 if (regno
> 15 || elno
> 1)
17714 return regno
| (elno
<< 4);
17718 first_error (_("scalar out of range for multiply instruction"));
17724 /* Encode multiply / multiply-accumulate scalar instructions. */
17727 neon_mul_mac (struct neon_type_el et
, int ubit
)
17731 /* Give a more helpful error message if we have an invalid type. */
17732 if (et
.type
== NT_invtype
)
17735 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17736 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17738 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17739 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17740 inst
.instruction
|= LOW4 (scalar
);
17741 inst
.instruction
|= HI1 (scalar
) << 5;
17742 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17743 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17744 inst
.instruction
|= (ubit
!= 0) << 24;
17746 neon_dp_fixup (&inst
);
17750 do_neon_mac_maybe_scalar (void)
17752 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17755 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17758 if (inst
.operands
[2].isscalar
)
17760 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17761 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17762 struct neon_type_el et
= neon_check_type (3, rs
,
17763 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17764 NEON_ENCODE (SCALAR
, inst
);
17765 neon_mul_mac (et
, neon_quad (rs
));
17767 else if (!inst
.operands
[2].isvec
)
17769 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17771 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17772 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17774 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17778 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17779 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17780 affected if we specify unsigned args. */
17781 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17786 do_neon_fmac (void)
17788 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17789 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17792 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17795 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17797 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17798 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17803 if (inst
.operands
[2].reg
== REG_SP
)
17804 as_tsktsk (MVE_BAD_SP
);
17805 else if (inst
.operands
[2].reg
== REG_PC
)
17806 as_tsktsk (MVE_BAD_PC
);
17808 inst
.instruction
= 0xee310e40;
17809 inst
.instruction
|= (et
.size
== 16) << 28;
17810 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17811 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17812 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17813 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17814 inst
.instruction
|= inst
.operands
[2].reg
;
17821 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17824 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17830 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17831 struct neon_type_el et
= neon_check_type (3, rs
,
17832 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17833 neon_three_same (neon_quad (rs
), 0, et
.size
);
17836 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17837 same types as the MAC equivalents. The polynomial type for this instruction
17838 is encoded the same as the integer type. */
17843 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17846 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17849 if (inst
.operands
[2].isscalar
)
17851 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17852 do_neon_mac_maybe_scalar ();
17856 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17858 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17859 struct neon_type_el et
17860 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17861 if (et
.type
== NT_float
)
17862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17865 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17869 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17870 neon_dyadic_misc (NT_poly
,
17871 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17877 do_neon_qdmulh (void)
17879 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17882 if (inst
.operands
[2].isscalar
)
17884 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17885 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17886 struct neon_type_el et
= neon_check_type (3, rs
,
17887 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17888 NEON_ENCODE (SCALAR
, inst
);
17889 neon_mul_mac (et
, neon_quad (rs
));
17893 enum neon_shape rs
;
17894 struct neon_type_el et
;
17895 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17897 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17898 et
= neon_check_type (3, rs
,
17899 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17903 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17904 et
= neon_check_type (3, rs
,
17905 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17908 NEON_ENCODE (INTEGER
, inst
);
17910 mve_encode_qqr (et
.size
, 0, 0);
17912 /* The U bit (rounding) comes from bit mask. */
17913 neon_three_same (neon_quad (rs
), 0, et
.size
);
17918 do_mve_vaddv (void)
17920 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17921 struct neon_type_el et
17922 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17924 if (et
.type
== NT_invtype
)
17925 first_error (BAD_EL_TYPE
);
17927 if (inst
.cond
> COND_ALWAYS
)
17928 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17930 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17932 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17934 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17938 do_mve_vhcadd (void)
17940 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17941 struct neon_type_el et
17942 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17944 if (inst
.cond
> COND_ALWAYS
)
17945 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17947 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17949 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17950 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17952 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17953 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17954 "operand makes instruction UNPREDICTABLE"));
17956 mve_encode_qqq (0, et
.size
);
17957 inst
.instruction
|= (rot
== 270) << 12;
17962 do_mve_vqdmull (void)
17964 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17965 struct neon_type_el et
17966 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17969 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17970 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17971 as_tsktsk (BAD_MVE_SRCDEST
);
17973 if (inst
.cond
> COND_ALWAYS
)
17974 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17976 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17980 mve_encode_qqq (et
.size
== 32, 64);
17981 inst
.instruction
|= 1;
17985 mve_encode_qqr (64, et
.size
== 32, 0);
17986 inst
.instruction
|= 0x3 << 5;
17993 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17994 struct neon_type_el et
17995 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17997 if (et
.type
== NT_invtype
)
17998 first_error (BAD_EL_TYPE
);
18000 if (inst
.cond
> COND_ALWAYS
)
18001 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18003 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18005 mve_encode_qqq (0, 64);
18009 do_mve_vbrsr (void)
18011 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18012 struct neon_type_el et
18013 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18015 if (inst
.cond
> COND_ALWAYS
)
18016 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18018 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18020 mve_encode_qqr (et
.size
, 0, 0);
18026 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18028 if (inst
.cond
> COND_ALWAYS
)
18029 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18031 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18033 mve_encode_qqq (1, 64);
18037 do_mve_vmulh (void)
18039 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18040 struct neon_type_el et
18041 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18043 if (inst
.cond
> COND_ALWAYS
)
18044 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18046 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18048 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18052 do_mve_vqdmlah (void)
18054 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18055 struct neon_type_el et
18056 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18058 if (inst
.cond
> COND_ALWAYS
)
18059 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18061 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18063 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18067 do_mve_vqdmladh (void)
18069 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18070 struct neon_type_el et
18071 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18073 if (inst
.cond
> COND_ALWAYS
)
18074 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18076 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18078 mve_encode_qqq (0, et
.size
);
18083 do_mve_vmull (void)
18086 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18087 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18088 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18089 && inst
.cond
== COND_ALWAYS
18090 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18095 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18096 N_SUF_32
| N_F64
| N_P8
18097 | N_P16
| N_I_MVE
| N_KEY
);
18098 if (((et
.type
== NT_poly
) && et
.size
== 8
18099 && ARM_CPU_IS_ANY (cpu_variant
))
18100 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18107 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18108 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18109 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18111 /* We are dealing with MVE's vmullt. */
18113 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18114 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18115 as_tsktsk (BAD_MVE_SRCDEST
);
18117 if (inst
.cond
> COND_ALWAYS
)
18118 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18120 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18122 if (et
.type
== NT_poly
)
18123 mve_encode_qqq (neon_logbits (et
.size
), 64);
18125 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18130 inst
.instruction
= N_MNEM_vmul
;
18133 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18138 do_mve_vabav (void)
18140 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18145 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18148 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18149 | N_S16
| N_S32
| N_U8
| N_U16
18152 if (inst
.cond
> COND_ALWAYS
)
18153 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18155 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18157 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18161 do_mve_vmladav (void)
18163 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18164 struct neon_type_el et
= neon_check_type (3, rs
,
18165 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18167 if (et
.type
== NT_unsigned
18168 && (inst
.instruction
== M_MNEM_vmladavx
18169 || inst
.instruction
== M_MNEM_vmladavax
18170 || inst
.instruction
== M_MNEM_vmlsdav
18171 || inst
.instruction
== M_MNEM_vmlsdava
18172 || inst
.instruction
== M_MNEM_vmlsdavx
18173 || inst
.instruction
== M_MNEM_vmlsdavax
))
18174 first_error (BAD_SIMD_TYPE
);
18176 constraint (inst
.operands
[2].reg
> 14,
18177 _("MVE vector register in the range [Q0..Q7] expected"));
18179 if (inst
.cond
> COND_ALWAYS
)
18180 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18182 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18184 if (inst
.instruction
== M_MNEM_vmlsdav
18185 || inst
.instruction
== M_MNEM_vmlsdava
18186 || inst
.instruction
== M_MNEM_vmlsdavx
18187 || inst
.instruction
== M_MNEM_vmlsdavax
)
18188 inst
.instruction
|= (et
.size
== 8) << 28;
18190 inst
.instruction
|= (et
.size
== 8) << 8;
18192 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18193 inst
.instruction
|= (et
.size
== 32) << 16;
18197 do_mve_vmlaldav (void)
18199 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18200 struct neon_type_el et
18201 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18202 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18204 if (et
.type
== NT_unsigned
18205 && (inst
.instruction
== M_MNEM_vmlsldav
18206 || inst
.instruction
== M_MNEM_vmlsldava
18207 || inst
.instruction
== M_MNEM_vmlsldavx
18208 || inst
.instruction
== M_MNEM_vmlsldavax
))
18209 first_error (BAD_SIMD_TYPE
);
18211 if (inst
.cond
> COND_ALWAYS
)
18212 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18214 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18216 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18220 do_mve_vrmlaldavh (void)
18222 struct neon_type_el et
;
18223 if (inst
.instruction
== M_MNEM_vrmlsldavh
18224 || inst
.instruction
== M_MNEM_vrmlsldavha
18225 || inst
.instruction
== M_MNEM_vrmlsldavhx
18226 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18228 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18229 if (inst
.operands
[1].reg
== REG_SP
)
18230 as_tsktsk (MVE_BAD_SP
);
18234 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18235 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18236 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18238 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18239 N_U32
| N_S32
| N_KEY
);
18240 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18241 with vmax/min instructions, making the use of SP in assembly really
18242 nonsensical, so instead of issuing a warning like we do for other uses
18243 of SP for the odd register operand we error out. */
18244 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18247 /* Make sure we still check the second operand is an odd one and that PC is
18248 disallowed. This because we are parsing for any GPR operand, to be able
18249 to distinguish between giving a warning or an error for SP as described
18251 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18252 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18254 if (inst
.cond
> COND_ALWAYS
)
18255 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18257 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18259 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18264 do_mve_vmaxnmv (void)
18266 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18267 struct neon_type_el et
18268 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18270 if (inst
.cond
> COND_ALWAYS
)
18271 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18273 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18275 if (inst
.operands
[0].reg
== REG_SP
)
18276 as_tsktsk (MVE_BAD_SP
);
18277 else if (inst
.operands
[0].reg
== REG_PC
)
18278 as_tsktsk (MVE_BAD_PC
);
18280 mve_encode_rq (et
.size
== 16, 64);
18284 do_mve_vmaxv (void)
18286 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18287 struct neon_type_el et
;
18289 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18290 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18292 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18294 if (inst
.cond
> COND_ALWAYS
)
18295 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18297 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18299 if (inst
.operands
[0].reg
== REG_SP
)
18300 as_tsktsk (MVE_BAD_SP
);
18301 else if (inst
.operands
[0].reg
== REG_PC
)
18302 as_tsktsk (MVE_BAD_PC
);
18304 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18309 do_neon_qrdmlah (void)
18311 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18313 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18315 /* Check we're on the correct architecture. */
18316 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18318 = _("instruction form not available on this architecture.");
18319 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18321 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18322 record_feature_use (&fpu_neon_ext_v8_1
);
18324 if (inst
.operands
[2].isscalar
)
18326 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18327 struct neon_type_el et
= neon_check_type (3, rs
,
18328 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18329 NEON_ENCODE (SCALAR
, inst
);
18330 neon_mul_mac (et
, neon_quad (rs
));
18334 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18335 struct neon_type_el et
= neon_check_type (3, rs
,
18336 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18337 NEON_ENCODE (INTEGER
, inst
);
18338 /* The U bit (rounding) comes from bit mask. */
18339 neon_three_same (neon_quad (rs
), 0, et
.size
);
18344 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18345 struct neon_type_el et
18346 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18348 NEON_ENCODE (INTEGER
, inst
);
18349 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18354 do_neon_fcmp_absolute (void)
18356 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18357 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18358 N_F_16_32
| N_KEY
);
18359 /* Size field comes from bit mask. */
18360 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18364 do_neon_fcmp_absolute_inv (void)
18366 neon_exchange_operands ();
18367 do_neon_fcmp_absolute ();
18371 do_neon_step (void)
18373 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18374 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18375 N_F_16_32
| N_KEY
);
18376 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18380 do_neon_abs_neg (void)
18382 enum neon_shape rs
;
18383 struct neon_type_el et
;
18385 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18388 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18389 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18391 if (!check_simd_pred_availability (et
.type
== NT_float
,
18392 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18395 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18396 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18397 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18398 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18399 inst
.instruction
|= neon_quad (rs
) << 6;
18400 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18401 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18403 neon_dp_fixup (&inst
);
18409 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18412 enum neon_shape rs
;
18413 struct neon_type_el et
;
18414 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18416 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18417 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18421 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18422 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18426 int imm
= inst
.operands
[2].imm
;
18427 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18428 _("immediate out of range for insert"));
18429 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18435 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18438 enum neon_shape rs
;
18439 struct neon_type_el et
;
18440 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18442 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18443 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18447 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18448 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18451 int imm
= inst
.operands
[2].imm
;
18452 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18453 _("immediate out of range for insert"));
18454 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18458 do_neon_qshlu_imm (void)
18460 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18463 enum neon_shape rs
;
18464 struct neon_type_el et
;
18465 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18467 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18468 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18472 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18473 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18474 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18477 int imm
= inst
.operands
[2].imm
;
18478 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18479 _("immediate out of range for shift"));
18480 /* Only encodes the 'U present' variant of the instruction.
18481 In this case, signed types have OP (bit 8) set to 0.
18482 Unsigned types have OP set to 1. */
18483 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18484 /* The rest of the bits are the same as other immediate shifts. */
18485 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18489 do_neon_qmovn (void)
18491 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18492 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18493 /* Saturating move where operands can be signed or unsigned, and the
18494 destination has the same signedness. */
18495 NEON_ENCODE (INTEGER
, inst
);
18496 if (et
.type
== NT_unsigned
)
18497 inst
.instruction
|= 0xc0;
18499 inst
.instruction
|= 0x80;
18500 neon_two_same (0, 1, et
.size
/ 2);
18504 do_neon_qmovun (void)
18506 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18507 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18508 /* Saturating move with unsigned results. Operands must be signed. */
18509 NEON_ENCODE (INTEGER
, inst
);
18510 neon_two_same (0, 1, et
.size
/ 2);
18514 do_neon_rshift_sat_narrow (void)
18516 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18517 or unsigned. If operands are unsigned, results must also be unsigned. */
18518 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18519 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18520 int imm
= inst
.operands
[2].imm
;
18521 /* This gets the bounds check, size encoding and immediate bits calculation
18525 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18526 VQMOVN.I<size> <Dd>, <Qm>. */
18529 inst
.operands
[2].present
= 0;
18530 inst
.instruction
= N_MNEM_vqmovn
;
18535 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18536 _("immediate out of range"));
18537 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18541 do_neon_rshift_sat_narrow_u (void)
18543 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18544 or unsigned. If operands are unsigned, results must also be unsigned. */
18545 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18546 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18547 int imm
= inst
.operands
[2].imm
;
18548 /* This gets the bounds check, size encoding and immediate bits calculation
18552 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18553 VQMOVUN.I<size> <Dd>, <Qm>. */
18556 inst
.operands
[2].present
= 0;
18557 inst
.instruction
= N_MNEM_vqmovun
;
18562 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18563 _("immediate out of range"));
18564 /* FIXME: The manual is kind of unclear about what value U should have in
18565 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18567 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18571 do_neon_movn (void)
18573 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18574 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18575 NEON_ENCODE (INTEGER
, inst
);
18576 neon_two_same (0, 1, et
.size
/ 2);
18580 do_neon_rshift_narrow (void)
18582 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18583 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18584 int imm
= inst
.operands
[2].imm
;
18585 /* This gets the bounds check, size encoding and immediate bits calculation
18589 /* If immediate is zero then we are a pseudo-instruction for
18590 VMOVN.I<size> <Dd>, <Qm> */
18593 inst
.operands
[2].present
= 0;
18594 inst
.instruction
= N_MNEM_vmovn
;
18599 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18600 _("immediate out of range for narrowing operation"));
18601 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18605 do_neon_shll (void)
18607 /* FIXME: Type checking when lengthening. */
18608 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18609 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18610 unsigned imm
= inst
.operands
[2].imm
;
18612 if (imm
== et
.size
)
18614 /* Maximum shift variant. */
18615 NEON_ENCODE (INTEGER
, inst
);
18616 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18617 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18618 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18619 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18620 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18622 neon_dp_fixup (&inst
);
18626 /* A more-specific type check for non-max versions. */
18627 et
= neon_check_type (2, NS_QDI
,
18628 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18629 NEON_ENCODE (IMMED
, inst
);
18630 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18634 /* Check the various types for the VCVT instruction, and return which version
18635 the current instruction is. */
18637 #define CVT_FLAVOUR_VAR \
18638 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18639 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18640 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18641 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18642 /* Half-precision conversions. */ \
18643 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18644 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18645 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18646 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18647 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18648 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18649 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18650 Compared with single/double precision variants, only the co-processor \
18651 field is different, so the encoding flow is reused here. */ \
18652 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18653 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18654 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18655 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18656 /* VFP instructions. */ \
18657 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18658 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18659 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18660 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18661 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18662 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18663 /* VFP instructions with bitshift. */ \
18664 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18665 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18666 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18667 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18668 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18669 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18670 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18671 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18673 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18674 neon_cvt_flavour_##C,
18676 /* The different types of conversions we can do. */
18677 enum neon_cvt_flavour
18680 neon_cvt_flavour_invalid
,
18681 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18686 static enum neon_cvt_flavour
18687 get_neon_cvt_flavour (enum neon_shape rs
)
18689 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18690 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18691 if (et.type != NT_invtype) \
18693 inst.error = NULL; \
18694 return (neon_cvt_flavour_##C); \
18697 struct neon_type_el et
;
18698 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18699 || rs
== NS_FF
) ? N_VFP
: 0;
18700 /* The instruction versions which take an immediate take one register
18701 argument, which is extended to the width of the full register. Thus the
18702 "source" and "destination" registers must have the same width. Hack that
18703 here by making the size equal to the key (wider, in this case) operand. */
18704 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18708 return neon_cvt_flavour_invalid
;
18723 /* Neon-syntax VFP conversions. */
18726 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18728 const char *opname
= 0;
18730 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18731 || rs
== NS_FHI
|| rs
== NS_HFI
)
18733 /* Conversions with immediate bitshift. */
18734 const char *enc
[] =
18736 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18742 if (flavour
< (int) ARRAY_SIZE (enc
))
18744 opname
= enc
[flavour
];
18745 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18746 _("operands 0 and 1 must be the same register"));
18747 inst
.operands
[1] = inst
.operands
[2];
18748 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18753 /* Conversions without bitshift. */
18754 const char *enc
[] =
18756 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18762 if (flavour
< (int) ARRAY_SIZE (enc
))
18763 opname
= enc
[flavour
];
18767 do_vfp_nsyn_opcode (opname
);
18769 /* ARMv8.2 fp16 VCVT instruction. */
18770 if (flavour
== neon_cvt_flavour_s32_f16
18771 || flavour
== neon_cvt_flavour_u32_f16
18772 || flavour
== neon_cvt_flavour_f16_u32
18773 || flavour
== neon_cvt_flavour_f16_s32
)
18774 do_scalar_fp16_v82_encode ();
18778 do_vfp_nsyn_cvtz (void)
18780 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18781 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18782 const char *enc
[] =
18784 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18790 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18791 do_vfp_nsyn_opcode (enc
[flavour
]);
18795 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18796 enum neon_cvt_mode mode
)
18801 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18802 D register operands. */
18803 if (flavour
== neon_cvt_flavour_s32_f64
18804 || flavour
== neon_cvt_flavour_u32_f64
)
18805 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18808 if (flavour
== neon_cvt_flavour_s32_f16
18809 || flavour
== neon_cvt_flavour_u32_f16
)
18810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18813 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18817 case neon_cvt_flavour_s32_f64
:
18821 case neon_cvt_flavour_s32_f32
:
18825 case neon_cvt_flavour_s32_f16
:
18829 case neon_cvt_flavour_u32_f64
:
18833 case neon_cvt_flavour_u32_f32
:
18837 case neon_cvt_flavour_u32_f16
:
18842 first_error (_("invalid instruction shape"));
18848 case neon_cvt_mode_a
: rm
= 0; break;
18849 case neon_cvt_mode_n
: rm
= 1; break;
18850 case neon_cvt_mode_p
: rm
= 2; break;
18851 case neon_cvt_mode_m
: rm
= 3; break;
18852 default: first_error (_("invalid rounding mode")); return;
18855 NEON_ENCODE (FPV8
, inst
);
18856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18857 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18858 inst
.instruction
|= sz
<< 8;
18860 /* ARMv8.2 fp16 VCVT instruction. */
18861 if (flavour
== neon_cvt_flavour_s32_f16
18862 ||flavour
== neon_cvt_flavour_u32_f16
)
18863 do_scalar_fp16_v82_encode ();
18864 inst
.instruction
|= op
<< 7;
18865 inst
.instruction
|= rm
<< 16;
18866 inst
.instruction
|= 0xf0000000;
18867 inst
.is_neon
= TRUE
;
18871 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18873 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18874 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18875 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18877 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18879 if (flavour
== neon_cvt_flavour_invalid
)
18882 /* PR11109: Handle round-to-zero for VCVT conversions. */
18883 if (mode
== neon_cvt_mode_z
18884 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18885 && (flavour
== neon_cvt_flavour_s16_f16
18886 || flavour
== neon_cvt_flavour_u16_f16
18887 || flavour
== neon_cvt_flavour_s32_f32
18888 || flavour
== neon_cvt_flavour_u32_f32
18889 || flavour
== neon_cvt_flavour_s32_f64
18890 || flavour
== neon_cvt_flavour_u32_f64
)
18891 && (rs
== NS_FD
|| rs
== NS_FF
))
18893 do_vfp_nsyn_cvtz ();
18897 /* ARMv8.2 fp16 VCVT conversions. */
18898 if (mode
== neon_cvt_mode_z
18899 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18900 && (flavour
== neon_cvt_flavour_s32_f16
18901 || flavour
== neon_cvt_flavour_u32_f16
)
18904 do_vfp_nsyn_cvtz ();
18905 do_scalar_fp16_v82_encode ();
18909 /* VFP rather than Neon conversions. */
18910 if (flavour
>= neon_cvt_flavour_first_fp
)
18912 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18913 do_vfp_nsyn_cvt (rs
, flavour
);
18915 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18923 if (mode
== neon_cvt_mode_z
18924 && (flavour
== neon_cvt_flavour_f16_s16
18925 || flavour
== neon_cvt_flavour_f16_u16
18926 || flavour
== neon_cvt_flavour_s16_f16
18927 || flavour
== neon_cvt_flavour_u16_f16
18928 || flavour
== neon_cvt_flavour_f32_u32
18929 || flavour
== neon_cvt_flavour_f32_s32
18930 || flavour
== neon_cvt_flavour_s32_f32
18931 || flavour
== neon_cvt_flavour_u32_f32
))
18933 if (!check_simd_pred_availability (TRUE
,
18934 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18937 else if (mode
== neon_cvt_mode_n
)
18939 /* We are dealing with vcvt with the 'ne' condition. */
18941 inst
.instruction
= N_MNEM_vcvt
;
18942 do_neon_cvt_1 (neon_cvt_mode_z
);
18945 /* fall through. */
18949 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18950 0x0000100, 0x1000100, 0x0, 0x1000000};
18952 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18953 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18956 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18958 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18959 _("immediate value out of range"));
18962 case neon_cvt_flavour_f16_s16
:
18963 case neon_cvt_flavour_f16_u16
:
18964 case neon_cvt_flavour_s16_f16
:
18965 case neon_cvt_flavour_u16_f16
:
18966 constraint (inst
.operands
[2].imm
> 16,
18967 _("immediate value out of range"));
18969 case neon_cvt_flavour_f32_u32
:
18970 case neon_cvt_flavour_f32_s32
:
18971 case neon_cvt_flavour_s32_f32
:
18972 case neon_cvt_flavour_u32_f32
:
18973 constraint (inst
.operands
[2].imm
> 32,
18974 _("immediate value out of range"));
18977 inst
.error
= BAD_FPU
;
18982 /* Fixed-point conversion with #0 immediate is encoded as an
18983 integer conversion. */
18984 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18986 NEON_ENCODE (IMMED
, inst
);
18987 if (flavour
!= neon_cvt_flavour_invalid
)
18988 inst
.instruction
|= enctab
[flavour
];
18989 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18990 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18991 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18992 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18993 inst
.instruction
|= neon_quad (rs
) << 6;
18994 inst
.instruction
|= 1 << 21;
18995 if (flavour
< neon_cvt_flavour_s16_f16
)
18997 inst
.instruction
|= 1 << 21;
18998 immbits
= 32 - inst
.operands
[2].imm
;
18999 inst
.instruction
|= immbits
<< 16;
19003 inst
.instruction
|= 3 << 20;
19004 immbits
= 16 - inst
.operands
[2].imm
;
19005 inst
.instruction
|= immbits
<< 16;
19006 inst
.instruction
&= ~(1 << 9);
19009 neon_dp_fixup (&inst
);
19014 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19015 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19016 && (flavour
== neon_cvt_flavour_s16_f16
19017 || flavour
== neon_cvt_flavour_u16_f16
19018 || flavour
== neon_cvt_flavour_s32_f32
19019 || flavour
== neon_cvt_flavour_u32_f32
))
19021 if (!check_simd_pred_availability (TRUE
,
19022 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19025 else if (mode
== neon_cvt_mode_z
19026 && (flavour
== neon_cvt_flavour_f16_s16
19027 || flavour
== neon_cvt_flavour_f16_u16
19028 || flavour
== neon_cvt_flavour_s16_f16
19029 || flavour
== neon_cvt_flavour_u16_f16
19030 || flavour
== neon_cvt_flavour_f32_u32
19031 || flavour
== neon_cvt_flavour_f32_s32
19032 || flavour
== neon_cvt_flavour_s32_f32
19033 || flavour
== neon_cvt_flavour_u32_f32
))
19035 if (!check_simd_pred_availability (TRUE
,
19036 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19039 /* fall through. */
19041 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19044 NEON_ENCODE (FLOAT
, inst
);
19045 if (!check_simd_pred_availability (TRUE
,
19046 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19049 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19050 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19051 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19052 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19053 inst
.instruction
|= neon_quad (rs
) << 6;
19054 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19055 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19056 inst
.instruction
|= mode
<< 8;
19057 if (flavour
== neon_cvt_flavour_u16_f16
19058 || flavour
== neon_cvt_flavour_s16_f16
)
19059 /* Mask off the original size bits and reencode them. */
19060 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19063 inst
.instruction
|= 0xfc000000;
19065 inst
.instruction
|= 0xf0000000;
19071 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19072 0x100, 0x180, 0x0, 0x080};
19074 NEON_ENCODE (INTEGER
, inst
);
19076 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19078 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19082 if (flavour
!= neon_cvt_flavour_invalid
)
19083 inst
.instruction
|= enctab
[flavour
];
19085 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19086 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19087 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19088 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19089 inst
.instruction
|= neon_quad (rs
) << 6;
19090 if (flavour
>= neon_cvt_flavour_s16_f16
19091 && flavour
<= neon_cvt_flavour_f16_u16
)
19092 /* Half precision. */
19093 inst
.instruction
|= 1 << 18;
19095 inst
.instruction
|= 2 << 18;
19097 neon_dp_fixup (&inst
);
19102 /* Half-precision conversions for Advanced SIMD -- neon. */
19105 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19109 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19111 as_bad (_("operand size must match register width"));
19116 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19118 as_bad (_("operand size must match register width"));
19123 inst
.instruction
= 0x3b60600;
19125 inst
.instruction
= 0x3b60700;
19127 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19128 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19129 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19130 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19131 neon_dp_fixup (&inst
);
19135 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19136 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19137 do_vfp_nsyn_cvt (rs
, flavour
);
19139 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19144 do_neon_cvtr (void)
19146 do_neon_cvt_1 (neon_cvt_mode_x
);
19152 do_neon_cvt_1 (neon_cvt_mode_z
);
19156 do_neon_cvta (void)
19158 do_neon_cvt_1 (neon_cvt_mode_a
);
19162 do_neon_cvtn (void)
19164 do_neon_cvt_1 (neon_cvt_mode_n
);
19168 do_neon_cvtp (void)
19170 do_neon_cvt_1 (neon_cvt_mode_p
);
19174 do_neon_cvtm (void)
19176 do_neon_cvt_1 (neon_cvt_mode_m
);
19180 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19183 mark_feature_used (&fpu_vfp_ext_armv8
);
19185 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19186 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19187 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19188 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19189 inst
.instruction
|= to
? 0x10000 : 0;
19190 inst
.instruction
|= t
? 0x80 : 0;
19191 inst
.instruction
|= is_double
? 0x100 : 0;
19192 do_vfp_cond_or_thumb ();
19196 do_neon_cvttb_1 (bfd_boolean t
)
19198 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19199 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19203 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19205 int single_to_half
= 0;
19206 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19209 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19211 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19212 && (flavour
== neon_cvt_flavour_u16_f16
19213 || flavour
== neon_cvt_flavour_s16_f16
19214 || flavour
== neon_cvt_flavour_f16_s16
19215 || flavour
== neon_cvt_flavour_f16_u16
19216 || flavour
== neon_cvt_flavour_u32_f32
19217 || flavour
== neon_cvt_flavour_s32_f32
19218 || flavour
== neon_cvt_flavour_f32_s32
19219 || flavour
== neon_cvt_flavour_f32_u32
))
19222 inst
.instruction
= N_MNEM_vcvt
;
19223 set_pred_insn_type (INSIDE_VPT_INSN
);
19224 do_neon_cvt_1 (neon_cvt_mode_z
);
19227 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19228 single_to_half
= 1;
19229 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19231 first_error (BAD_FPU
);
19235 inst
.instruction
= 0xee3f0e01;
19236 inst
.instruction
|= single_to_half
<< 28;
19237 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19239 inst
.instruction
|= t
<< 12;
19240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19244 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19247 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19249 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19252 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19254 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19256 /* The VCVTB and VCVTT instructions with D-register operands
19257 don't work for SP only targets. */
19258 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19262 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19264 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19266 /* The VCVTB and VCVTT instructions with D-register operands
19267 don't work for SP only targets. */
19268 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19272 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19279 do_neon_cvtb (void)
19281 do_neon_cvttb_1 (FALSE
);
19286 do_neon_cvtt (void)
19288 do_neon_cvttb_1 (TRUE
);
19292 neon_move_immediate (void)
19294 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19295 struct neon_type_el et
= neon_check_type (2, rs
,
19296 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19297 unsigned immlo
, immhi
= 0, immbits
;
19298 int op
, cmode
, float_p
;
19300 constraint (et
.type
== NT_invtype
,
19301 _("operand size must be specified for immediate VMOV"));
19303 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19304 op
= (inst
.instruction
& (1 << 5)) != 0;
19306 immlo
= inst
.operands
[1].imm
;
19307 if (inst
.operands
[1].regisimm
)
19308 immhi
= inst
.operands
[1].reg
;
19310 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19311 _("immediate has bits set outside the operand size"));
19313 float_p
= inst
.operands
[1].immisfloat
;
19315 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19316 et
.size
, et
.type
)) == FAIL
)
19318 /* Invert relevant bits only. */
19319 neon_invert_size (&immlo
, &immhi
, et
.size
);
19320 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19321 with one or the other; those cases are caught by
19322 neon_cmode_for_move_imm. */
19324 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19325 &op
, et
.size
, et
.type
)) == FAIL
)
19327 first_error (_("immediate out of range"));
19332 inst
.instruction
&= ~(1 << 5);
19333 inst
.instruction
|= op
<< 5;
19335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19337 inst
.instruction
|= neon_quad (rs
) << 6;
19338 inst
.instruction
|= cmode
<< 8;
19340 neon_write_immbits (immbits
);
19346 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19349 if (inst
.operands
[1].isreg
)
19351 enum neon_shape rs
;
19352 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19353 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19355 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19357 NEON_ENCODE (INTEGER
, inst
);
19358 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19359 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19360 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19361 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19362 inst
.instruction
|= neon_quad (rs
) << 6;
19366 NEON_ENCODE (IMMED
, inst
);
19367 neon_move_immediate ();
19370 neon_dp_fixup (&inst
);
19372 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19374 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19375 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19376 _("immediate value out of range"));
19380 /* Encode instructions of form:
19382 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19383 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19386 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19388 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19389 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19390 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19391 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19392 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19393 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19394 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19395 inst
.instruction
|= neon_logbits (size
) << 20;
19397 neon_dp_fixup (&inst
);
19401 do_neon_dyadic_long (void)
19403 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19406 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19409 NEON_ENCODE (INTEGER
, inst
);
19410 /* FIXME: Type checking for lengthening op. */
19411 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19412 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19413 neon_mixed_length (et
, et
.size
);
19415 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19416 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19418 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19419 in an IT block with le/lt conditions. */
19421 if (inst
.cond
== 0xf)
19423 else if (inst
.cond
== 0x10)
19426 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19428 if (inst
.instruction
== N_MNEM_vaddl
)
19430 inst
.instruction
= N_MNEM_vadd
;
19431 do_neon_addsub_if_i ();
19433 else if (inst
.instruction
== N_MNEM_vsubl
)
19435 inst
.instruction
= N_MNEM_vsub
;
19436 do_neon_addsub_if_i ();
19438 else if (inst
.instruction
== N_MNEM_vabdl
)
19440 inst
.instruction
= N_MNEM_vabd
;
19441 do_neon_dyadic_if_su ();
19445 first_error (BAD_FPU
);
19449 do_neon_abal (void)
19451 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19452 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19453 neon_mixed_length (et
, et
.size
);
19457 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19459 if (inst
.operands
[2].isscalar
)
19461 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19462 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19463 NEON_ENCODE (SCALAR
, inst
);
19464 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19468 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19469 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19470 NEON_ENCODE (INTEGER
, inst
);
19471 neon_mixed_length (et
, et
.size
);
19476 do_neon_mac_maybe_scalar_long (void)
19478 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19481 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19482 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19485 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19487 unsigned regno
= NEON_SCALAR_REG (scalar
);
19488 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19492 if (regno
> 7 || elno
> 3)
19495 return ((regno
& 0x7)
19496 | ((elno
& 0x1) << 3)
19497 | (((elno
>> 1) & 0x1) << 5));
19501 if (regno
> 15 || elno
> 1)
19504 return (((regno
& 0x1) << 5)
19505 | ((regno
>> 1) & 0x7)
19506 | ((elno
& 0x1) << 3));
19510 first_error (_("scalar out of range for multiply instruction"));
19515 do_neon_fmac_maybe_scalar_long (int subtype
)
19517 enum neon_shape rs
;
19519 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19520 field (bits[21:20]) has different meaning. For scalar index variant, it's
19521 used to differentiate add and subtract, otherwise it's with fixed value
19525 if (inst
.cond
!= COND_ALWAYS
)
19526 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19527 "behaviour is UNPREDICTABLE"));
19529 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19532 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19535 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19536 be a scalar index register. */
19537 if (inst
.operands
[2].isscalar
)
19539 high8
= 0xfe000000;
19542 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19546 high8
= 0xfc000000;
19549 inst
.instruction
|= (0x1 << 23);
19550 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19553 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19555 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19556 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19557 so we simply pass -1 as size. */
19558 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19559 neon_three_same (quad_p
, 0, size
);
19561 /* Undo neon_dp_fixup. Redo the high eight bits. */
19562 inst
.instruction
&= 0x00ffffff;
19563 inst
.instruction
|= high8
;
19565 #define LOW1(R) ((R) & 0x1)
19566 #define HI4(R) (((R) >> 1) & 0xf)
19567 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19568 whether the instruction is in Q form and whether Vm is a scalar indexed
19570 if (inst
.operands
[2].isscalar
)
19573 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19574 inst
.instruction
&= 0xffffffd0;
19575 inst
.instruction
|= rm
;
19579 /* Redo Rn as well. */
19580 inst
.instruction
&= 0xfff0ff7f;
19581 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19582 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19587 /* Redo Rn and Rm. */
19588 inst
.instruction
&= 0xfff0ff50;
19589 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19590 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19591 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19592 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19597 do_neon_vfmal (void)
19599 return do_neon_fmac_maybe_scalar_long (0);
19603 do_neon_vfmsl (void)
19605 return do_neon_fmac_maybe_scalar_long (1);
19609 do_neon_dyadic_wide (void)
19611 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19612 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19613 neon_mixed_length (et
, et
.size
);
19617 do_neon_dyadic_narrow (void)
19619 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19620 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19621 /* Operand sign is unimportant, and the U bit is part of the opcode,
19622 so force the operand type to integer. */
19623 et
.type
= NT_integer
;
19624 neon_mixed_length (et
, et
.size
/ 2);
19628 do_neon_mul_sat_scalar_long (void)
19630 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19634 do_neon_vmull (void)
19636 if (inst
.operands
[2].isscalar
)
19637 do_neon_mac_maybe_scalar_long ();
19640 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19641 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19643 if (et
.type
== NT_poly
)
19644 NEON_ENCODE (POLY
, inst
);
19646 NEON_ENCODE (INTEGER
, inst
);
19648 /* For polynomial encoding the U bit must be zero, and the size must
19649 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19650 obviously, as 0b10). */
19653 /* Check we're on the correct architecture. */
19654 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19656 _("Instruction form not available on this architecture.");
19661 neon_mixed_length (et
, et
.size
);
19668 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19669 struct neon_type_el et
= neon_check_type (3, rs
,
19670 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19671 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19673 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19674 _("shift out of range"));
19675 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19676 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19677 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19678 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19679 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19680 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19681 inst
.instruction
|= neon_quad (rs
) << 6;
19682 inst
.instruction
|= imm
<< 8;
19684 neon_dp_fixup (&inst
);
19690 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19693 enum neon_shape rs
;
19694 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19695 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19697 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19699 struct neon_type_el et
= neon_check_type (2, rs
,
19700 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19702 unsigned op
= (inst
.instruction
>> 7) & 3;
19703 /* N (width of reversed regions) is encoded as part of the bitmask. We
19704 extract it here to check the elements to be reversed are smaller.
19705 Otherwise we'd get a reserved instruction. */
19706 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19708 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19709 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19710 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19711 " operands makes instruction UNPREDICTABLE"));
19713 gas_assert (elsize
!= 0);
19714 constraint (et
.size
>= elsize
,
19715 _("elements must be smaller than reversal region"));
19716 neon_two_same (neon_quad (rs
), 1, et
.size
);
19722 if (inst
.operands
[1].isscalar
)
19724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19726 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19727 struct neon_type_el et
= neon_check_type (2, rs
,
19728 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19729 unsigned sizebits
= et
.size
>> 3;
19730 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19731 int logsize
= neon_logbits (et
.size
);
19732 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19734 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19737 NEON_ENCODE (SCALAR
, inst
);
19738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19740 inst
.instruction
|= LOW4 (dm
);
19741 inst
.instruction
|= HI1 (dm
) << 5;
19742 inst
.instruction
|= neon_quad (rs
) << 6;
19743 inst
.instruction
|= x
<< 17;
19744 inst
.instruction
|= sizebits
<< 16;
19746 neon_dp_fixup (&inst
);
19750 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19751 struct neon_type_el et
= neon_check_type (2, rs
,
19752 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19755 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19762 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19764 if (inst
.operands
[1].reg
== REG_SP
)
19765 as_tsktsk (MVE_BAD_SP
);
19766 else if (inst
.operands
[1].reg
== REG_PC
)
19767 as_tsktsk (MVE_BAD_PC
);
19770 /* Duplicate ARM register to lanes of vector. */
19771 NEON_ENCODE (ARMREG
, inst
);
19774 case 8: inst
.instruction
|= 0x400000; break;
19775 case 16: inst
.instruction
|= 0x000020; break;
19776 case 32: inst
.instruction
|= 0x000000; break;
19779 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19780 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19781 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19782 inst
.instruction
|= neon_quad (rs
) << 21;
19783 /* The encoding for this instruction is identical for the ARM and Thumb
19784 variants, except for the condition field. */
19785 do_vfp_cond_or_thumb ();
19790 do_mve_mov (int toQ
)
19792 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19794 if (inst
.cond
> COND_ALWAYS
)
19795 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19797 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19806 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19807 _("Index one must be [2,3] and index two must be two less than"
19809 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19810 _("General purpose registers may not be the same"));
19811 constraint (inst
.operands
[Rt
].reg
== REG_SP
19812 || inst
.operands
[Rt2
].reg
== REG_SP
,
19814 constraint (inst
.operands
[Rt
].reg
== REG_PC
19815 || inst
.operands
[Rt2
].reg
== REG_PC
,
19818 inst
.instruction
= 0xec000f00;
19819 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19820 inst
.instruction
|= !!toQ
<< 20;
19821 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19822 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19823 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19824 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19830 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19833 if (inst
.cond
> COND_ALWAYS
)
19834 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19836 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19838 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19841 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19842 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19843 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19844 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19845 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19850 /* VMOV has particularly many variations. It can be one of:
19851 0. VMOV<c><q> <Qd>, <Qm>
19852 1. VMOV<c><q> <Dd>, <Dm>
19853 (Register operations, which are VORR with Rm = Rn.)
19854 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19855 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19857 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19858 (ARM register to scalar.)
19859 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19860 (Two ARM registers to vector.)
19861 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19862 (Scalar to ARM register.)
19863 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19864 (Vector to two ARM registers.)
19865 8. VMOV.F32 <Sd>, <Sm>
19866 9. VMOV.F64 <Dd>, <Dm>
19867 (VFP register moves.)
19868 10. VMOV.F32 <Sd>, #imm
19869 11. VMOV.F64 <Dd>, #imm
19870 (VFP float immediate load.)
19871 12. VMOV <Rd>, <Sm>
19872 (VFP single to ARM reg.)
19873 13. VMOV <Sd>, <Rm>
19874 (ARM reg to VFP single.)
19875 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19876 (Two ARM regs to two VFP singles.)
19877 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19878 (Two VFP singles to two ARM regs.)
19879 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19880 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19881 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19882 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19884 These cases can be disambiguated using neon_select_shape, except cases 1/9
19885 and 3/11 which depend on the operand type too.
19887 All the encoded bits are hardcoded by this function.
19889 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19890 Cases 5, 7 may be used with VFPv2 and above.
19892 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19893 can specify a type where it doesn't make sense to, and is ignored). */
19898 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19899 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19900 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19901 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19903 struct neon_type_el et
;
19904 const char *ldconst
= 0;
19908 case NS_DD
: /* case 1/9. */
19909 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19910 /* It is not an error here if no type is given. */
19913 /* In MVE we interpret the following instructions as same, so ignoring
19914 the following type (float) and size (64) checks.
19915 a: VMOV<c><q> <Dd>, <Dm>
19916 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
19917 if ((et
.type
== NT_float
&& et
.size
== 64)
19918 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
19920 do_vfp_nsyn_opcode ("fcpyd");
19923 /* fall through. */
19925 case NS_QQ
: /* case 0/1. */
19927 if (!check_simd_pred_availability (FALSE
,
19928 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19930 /* The architecture manual I have doesn't explicitly state which
19931 value the U bit should have for register->register moves, but
19932 the equivalent VORR instruction has U = 0, so do that. */
19933 inst
.instruction
= 0x0200110;
19934 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19935 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19936 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19937 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19938 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19939 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19940 inst
.instruction
|= neon_quad (rs
) << 6;
19942 neon_dp_fixup (&inst
);
19946 case NS_DI
: /* case 3/11. */
19947 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19949 if (et
.type
== NT_float
&& et
.size
== 64)
19951 /* case 11 (fconstd). */
19952 ldconst
= "fconstd";
19953 goto encode_fconstd
;
19955 /* fall through. */
19957 case NS_QI
: /* case 2/3. */
19958 if (!check_simd_pred_availability (FALSE
,
19959 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19961 inst
.instruction
= 0x0800010;
19962 neon_move_immediate ();
19963 neon_dp_fixup (&inst
);
19966 case NS_SR
: /* case 4. */
19968 unsigned bcdebits
= 0;
19970 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19971 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19973 /* .<size> is optional here, defaulting to .32. */
19974 if (inst
.vectype
.elems
== 0
19975 && inst
.operands
[0].vectype
.type
== NT_invtype
19976 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19978 inst
.vectype
.el
[0].type
= NT_untyped
;
19979 inst
.vectype
.el
[0].size
= 32;
19980 inst
.vectype
.elems
= 1;
19983 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19984 logsize
= neon_logbits (et
.size
);
19988 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19989 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19994 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19995 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19999 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20001 if (inst
.operands
[1].reg
== REG_SP
)
20002 as_tsktsk (MVE_BAD_SP
);
20003 else if (inst
.operands
[1].reg
== REG_PC
)
20004 as_tsktsk (MVE_BAD_PC
);
20006 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20008 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20009 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20014 case 8: bcdebits
= 0x8; break;
20015 case 16: bcdebits
= 0x1; break;
20016 case 32: bcdebits
= 0x0; break;
20020 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20022 inst
.instruction
= 0xe000b10;
20023 do_vfp_cond_or_thumb ();
20024 inst
.instruction
|= LOW4 (dn
) << 16;
20025 inst
.instruction
|= HI1 (dn
) << 7;
20026 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20027 inst
.instruction
|= (bcdebits
& 3) << 5;
20028 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20029 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20033 case NS_DRR
: /* case 5 (fmdrr). */
20034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20035 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20038 inst
.instruction
= 0xc400b10;
20039 do_vfp_cond_or_thumb ();
20040 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20041 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20042 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20043 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20046 case NS_RS
: /* case 6. */
20049 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20050 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20051 unsigned abcdebits
= 0;
20053 /* .<dt> is optional here, defaulting to .32. */
20054 if (inst
.vectype
.elems
== 0
20055 && inst
.operands
[0].vectype
.type
== NT_invtype
20056 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20058 inst
.vectype
.el
[0].type
= NT_untyped
;
20059 inst
.vectype
.el
[0].size
= 32;
20060 inst
.vectype
.elems
= 1;
20063 et
= neon_check_type (2, NS_NULL
,
20064 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20065 logsize
= neon_logbits (et
.size
);
20069 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20070 && vfp_or_neon_is_neon (NEON_CHECK_CC
20071 | NEON_CHECK_ARCH
) == FAIL
)
20076 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20077 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20081 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20083 if (inst
.operands
[0].reg
== REG_SP
)
20084 as_tsktsk (MVE_BAD_SP
);
20085 else if (inst
.operands
[0].reg
== REG_PC
)
20086 as_tsktsk (MVE_BAD_PC
);
20089 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20091 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20092 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20096 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20097 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20098 case 32: abcdebits
= 0x00; break;
20102 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20103 inst
.instruction
= 0xe100b10;
20104 do_vfp_cond_or_thumb ();
20105 inst
.instruction
|= LOW4 (dn
) << 16;
20106 inst
.instruction
|= HI1 (dn
) << 7;
20107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20108 inst
.instruction
|= (abcdebits
& 3) << 5;
20109 inst
.instruction
|= (abcdebits
>> 2) << 21;
20110 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20114 case NS_RRD
: /* case 7 (fmrrd). */
20115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20116 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20119 inst
.instruction
= 0xc500b10;
20120 do_vfp_cond_or_thumb ();
20121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20122 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20123 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20124 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20127 case NS_FF
: /* case 8 (fcpys). */
20128 do_vfp_nsyn_opcode ("fcpys");
20132 case NS_FI
: /* case 10 (fconsts). */
20133 ldconst
= "fconsts";
20135 if (!inst
.operands
[1].immisfloat
)
20138 /* Immediate has to fit in 8 bits so float is enough. */
20139 float imm
= (float) inst
.operands
[1].imm
;
20140 memcpy (&new_imm
, &imm
, sizeof (float));
20141 /* But the assembly may have been written to provide an integer
20142 bit pattern that equates to a float, so check that the
20143 conversion has worked. */
20144 if (is_quarter_float (new_imm
))
20146 if (is_quarter_float (inst
.operands
[1].imm
))
20147 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20149 inst
.operands
[1].imm
= new_imm
;
20150 inst
.operands
[1].immisfloat
= 1;
20154 if (is_quarter_float (inst
.operands
[1].imm
))
20156 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20157 do_vfp_nsyn_opcode (ldconst
);
20159 /* ARMv8.2 fp16 vmov.f16 instruction. */
20161 do_scalar_fp16_v82_encode ();
20164 first_error (_("immediate out of range"));
20168 case NS_RF
: /* case 12 (fmrs). */
20169 do_vfp_nsyn_opcode ("fmrs");
20170 /* ARMv8.2 fp16 vmov.f16 instruction. */
20172 do_scalar_fp16_v82_encode ();
20176 case NS_FR
: /* case 13 (fmsr). */
20177 do_vfp_nsyn_opcode ("fmsr");
20178 /* ARMv8.2 fp16 vmov.f16 instruction. */
20180 do_scalar_fp16_v82_encode ();
20190 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20191 (one of which is a list), but we have parsed four. Do some fiddling to
20192 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20194 case NS_RRFF
: /* case 14 (fmrrs). */
20195 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20196 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20198 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20199 _("VFP registers must be adjacent"));
20200 inst
.operands
[2].imm
= 2;
20201 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20202 do_vfp_nsyn_opcode ("fmrrs");
20205 case NS_FFRR
: /* case 15 (fmsrr). */
20206 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20207 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20209 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20210 _("VFP registers must be adjacent"));
20211 inst
.operands
[1] = inst
.operands
[2];
20212 inst
.operands
[2] = inst
.operands
[3];
20213 inst
.operands
[0].imm
= 2;
20214 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20215 do_vfp_nsyn_opcode ("fmsrr");
20219 /* neon_select_shape has determined that the instruction
20220 shape is wrong and has already set the error message. */
20231 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20232 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20233 && !inst
.operands
[2].present
))
20235 inst
.instruction
= 0;
20238 set_pred_insn_type (INSIDE_IT_INSN
);
20243 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20246 if (inst
.cond
!= COND_ALWAYS
)
20247 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20249 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20250 | N_S16
| N_U16
| N_KEY
);
20252 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20253 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20254 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20255 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20256 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20257 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20262 do_neon_rshift_round_imm (void)
20264 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20267 enum neon_shape rs
;
20268 struct neon_type_el et
;
20270 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20272 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20273 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20277 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20278 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20280 int imm
= inst
.operands
[2].imm
;
20282 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20285 inst
.operands
[2].present
= 0;
20290 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20291 _("immediate out of range for shift"));
20292 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20297 do_neon_movhf (void)
20299 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20300 constraint (rs
!= NS_HH
, _("invalid suffix"));
20302 if (inst
.cond
!= COND_ALWAYS
)
20306 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20307 " the behaviour is UNPREDICTABLE"));
20311 inst
.error
= BAD_COND
;
20316 do_vfp_sp_monadic ();
20319 inst
.instruction
|= 0xf0000000;
20323 do_neon_movl (void)
20325 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20326 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20327 unsigned sizebits
= et
.size
>> 3;
20328 inst
.instruction
|= sizebits
<< 19;
20329 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20335 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20336 struct neon_type_el et
= neon_check_type (2, rs
,
20337 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20338 NEON_ENCODE (INTEGER
, inst
);
20339 neon_two_same (neon_quad (rs
), 1, et
.size
);
20343 do_neon_zip_uzp (void)
20345 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20346 struct neon_type_el et
= neon_check_type (2, rs
,
20347 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20348 if (rs
== NS_DD
&& et
.size
== 32)
20350 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20351 inst
.instruction
= N_MNEM_vtrn
;
20355 neon_two_same (neon_quad (rs
), 1, et
.size
);
20359 do_neon_sat_abs_neg (void)
20361 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20364 enum neon_shape rs
;
20365 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20366 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20368 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20369 struct neon_type_el et
= neon_check_type (2, rs
,
20370 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20371 neon_two_same (neon_quad (rs
), 1, et
.size
);
20375 do_neon_pair_long (void)
20377 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20378 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20379 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20380 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20381 neon_two_same (neon_quad (rs
), 1, et
.size
);
20385 do_neon_recip_est (void)
20387 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20388 struct neon_type_el et
= neon_check_type (2, rs
,
20389 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20390 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20391 neon_two_same (neon_quad (rs
), 1, et
.size
);
20397 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20400 enum neon_shape rs
;
20401 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20402 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20404 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20406 struct neon_type_el et
= neon_check_type (2, rs
,
20407 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20408 neon_two_same (neon_quad (rs
), 1, et
.size
);
20414 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20417 enum neon_shape rs
;
20418 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20419 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20421 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20423 struct neon_type_el et
= neon_check_type (2, rs
,
20424 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20425 neon_two_same (neon_quad (rs
), 1, et
.size
);
20431 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20432 struct neon_type_el et
= neon_check_type (2, rs
,
20433 N_EQK
| N_INT
, N_8
| N_KEY
);
20434 neon_two_same (neon_quad (rs
), 1, et
.size
);
20440 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20441 neon_two_same (neon_quad (rs
), 1, -1);
20445 do_neon_tbl_tbx (void)
20447 unsigned listlenbits
;
20448 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20450 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20452 first_error (_("bad list length for table lookup"));
20456 listlenbits
= inst
.operands
[1].imm
- 1;
20457 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20458 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20459 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20460 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20461 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20462 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20463 inst
.instruction
|= listlenbits
<< 8;
20465 neon_dp_fixup (&inst
);
20469 do_neon_ldm_stm (void)
20471 /* P, U and L bits are part of bitmask. */
20472 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20473 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20475 if (inst
.operands
[1].issingle
)
20477 do_vfp_nsyn_ldm_stm (is_dbmode
);
20481 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20482 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20484 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20485 _("register list must contain at least 1 and at most 16 "
20488 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20489 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20490 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20491 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20493 inst
.instruction
|= offsetbits
;
20495 do_vfp_cond_or_thumb ();
20499 do_neon_ldr_str (void)
20501 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20503 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20504 And is UNPREDICTABLE in thumb mode. */
20506 && inst
.operands
[1].reg
== REG_PC
20507 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20510 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20511 else if (warn_on_deprecated
)
20512 as_tsktsk (_("Use of PC here is deprecated"));
20515 if (inst
.operands
[0].issingle
)
20518 do_vfp_nsyn_opcode ("flds");
20520 do_vfp_nsyn_opcode ("fsts");
20522 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20523 if (inst
.vectype
.el
[0].size
== 16)
20524 do_scalar_fp16_v82_encode ();
20529 do_vfp_nsyn_opcode ("fldd");
20531 do_vfp_nsyn_opcode ("fstd");
20536 do_t_vldr_vstr_sysreg (void)
20538 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20539 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20541 /* Use of PC is UNPREDICTABLE. */
20542 if (inst
.operands
[1].reg
== REG_PC
)
20543 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20545 if (inst
.operands
[1].immisreg
)
20546 inst
.error
= _("instruction does not accept register index");
20548 if (!inst
.operands
[1].isreg
)
20549 inst
.error
= _("instruction does not accept PC-relative addressing");
20551 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20552 inst
.error
= _("immediate value out of range");
20554 inst
.instruction
= 0xec000f80;
20556 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20557 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20558 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20559 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20563 do_vldr_vstr (void)
20565 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20567 /* VLDR/VSTR (System Register). */
20570 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20571 as_bad (_("Instruction not permitted on this architecture"));
20573 do_t_vldr_vstr_sysreg ();
20578 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20579 as_bad (_("Instruction not permitted on this architecture"));
20580 do_neon_ldr_str ();
20584 /* "interleave" version also handles non-interleaving register VLD1/VST1
20588 do_neon_ld_st_interleave (void)
20590 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20591 N_8
| N_16
| N_32
| N_64
);
20592 unsigned alignbits
= 0;
20594 /* The bits in this table go:
20595 0: register stride of one (0) or two (1)
20596 1,2: register list length, minus one (1, 2, 3, 4).
20597 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20598 We use -1 for invalid entries. */
20599 const int typetable
[] =
20601 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20602 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20603 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20604 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20608 if (et
.type
== NT_invtype
)
20611 if (inst
.operands
[1].immisalign
)
20612 switch (inst
.operands
[1].imm
>> 8)
20614 case 64: alignbits
= 1; break;
20616 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20617 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20618 goto bad_alignment
;
20622 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20623 goto bad_alignment
;
20628 first_error (_("bad alignment"));
20632 inst
.instruction
|= alignbits
<< 4;
20633 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20635 /* Bits [4:6] of the immediate in a list specifier encode register stride
20636 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20637 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20638 up the right value for "type" in a table based on this value and the given
20639 list style, then stick it back. */
20640 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20641 | (((inst
.instruction
>> 8) & 3) << 3);
20643 typebits
= typetable
[idx
];
20645 constraint (typebits
== -1, _("bad list type for instruction"));
20646 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20649 inst
.instruction
&= ~0xf00;
20650 inst
.instruction
|= typebits
<< 8;
20653 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20654 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20655 otherwise. The variable arguments are a list of pairs of legal (size, align)
20656 values, terminated with -1. */
20659 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20662 int result
= FAIL
, thissize
, thisalign
;
20664 if (!inst
.operands
[1].immisalign
)
20670 va_start (ap
, do_alignment
);
20674 thissize
= va_arg (ap
, int);
20675 if (thissize
== -1)
20677 thisalign
= va_arg (ap
, int);
20679 if (size
== thissize
&& align
== thisalign
)
20682 while (result
!= SUCCESS
);
20686 if (result
== SUCCESS
)
20689 first_error (_("unsupported alignment for instruction"));
20695 do_neon_ld_st_lane (void)
20697 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20698 int align_good
, do_alignment
= 0;
20699 int logsize
= neon_logbits (et
.size
);
20700 int align
= inst
.operands
[1].imm
>> 8;
20701 int n
= (inst
.instruction
>> 8) & 3;
20702 int max_el
= 64 / et
.size
;
20704 if (et
.type
== NT_invtype
)
20707 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20708 _("bad list length"));
20709 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20710 _("scalar index out of range"));
20711 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20713 _("stride of 2 unavailable when element size is 8"));
20717 case 0: /* VLD1 / VST1. */
20718 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20720 if (align_good
== FAIL
)
20724 unsigned alignbits
= 0;
20727 case 16: alignbits
= 0x1; break;
20728 case 32: alignbits
= 0x3; break;
20731 inst
.instruction
|= alignbits
<< 4;
20735 case 1: /* VLD2 / VST2. */
20736 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20737 16, 32, 32, 64, -1);
20738 if (align_good
== FAIL
)
20741 inst
.instruction
|= 1 << 4;
20744 case 2: /* VLD3 / VST3. */
20745 constraint (inst
.operands
[1].immisalign
,
20746 _("can't use alignment with this instruction"));
20749 case 3: /* VLD4 / VST4. */
20750 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20751 16, 64, 32, 64, 32, 128, -1);
20752 if (align_good
== FAIL
)
20756 unsigned alignbits
= 0;
20759 case 8: alignbits
= 0x1; break;
20760 case 16: alignbits
= 0x1; break;
20761 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20764 inst
.instruction
|= alignbits
<< 4;
20771 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20772 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20773 inst
.instruction
|= 1 << (4 + logsize
);
20775 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20776 inst
.instruction
|= logsize
<< 10;
20779 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20782 do_neon_ld_dup (void)
20784 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20785 int align_good
, do_alignment
= 0;
20787 if (et
.type
== NT_invtype
)
20790 switch ((inst
.instruction
>> 8) & 3)
20792 case 0: /* VLD1. */
20793 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20794 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20795 &do_alignment
, 16, 16, 32, 32, -1);
20796 if (align_good
== FAIL
)
20798 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20801 case 2: inst
.instruction
|= 1 << 5; break;
20802 default: first_error (_("bad list length")); return;
20804 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20807 case 1: /* VLD2. */
20808 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20809 &do_alignment
, 8, 16, 16, 32, 32, 64,
20811 if (align_good
== FAIL
)
20813 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20814 _("bad list length"));
20815 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20816 inst
.instruction
|= 1 << 5;
20817 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20820 case 2: /* VLD3. */
20821 constraint (inst
.operands
[1].immisalign
,
20822 _("can't use alignment with this instruction"));
20823 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20824 _("bad list length"));
20825 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20826 inst
.instruction
|= 1 << 5;
20827 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20830 case 3: /* VLD4. */
20832 int align
= inst
.operands
[1].imm
>> 8;
20833 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20834 16, 64, 32, 64, 32, 128, -1);
20835 if (align_good
== FAIL
)
20837 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20838 _("bad list length"));
20839 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20840 inst
.instruction
|= 1 << 5;
20841 if (et
.size
== 32 && align
== 128)
20842 inst
.instruction
|= 0x3 << 6;
20844 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20851 inst
.instruction
|= do_alignment
<< 4;
20854 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20855 apart from bits [11:4]. */
20858 do_neon_ldx_stx (void)
20860 if (inst
.operands
[1].isreg
)
20861 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20863 switch (NEON_LANE (inst
.operands
[0].imm
))
20865 case NEON_INTERLEAVE_LANES
:
20866 NEON_ENCODE (INTERLV
, inst
);
20867 do_neon_ld_st_interleave ();
20870 case NEON_ALL_LANES
:
20871 NEON_ENCODE (DUP
, inst
);
20872 if (inst
.instruction
== N_INV
)
20874 first_error ("only loads support such operands");
20881 NEON_ENCODE (LANE
, inst
);
20882 do_neon_ld_st_lane ();
20885 /* L bit comes from bit mask. */
20886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20887 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20888 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20890 if (inst
.operands
[1].postind
)
20892 int postreg
= inst
.operands
[1].imm
& 0xf;
20893 constraint (!inst
.operands
[1].immisreg
,
20894 _("post-index must be a register"));
20895 constraint (postreg
== 0xd || postreg
== 0xf,
20896 _("bad register for post-index"));
20897 inst
.instruction
|= postreg
;
20901 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20902 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20903 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20906 if (inst
.operands
[1].writeback
)
20908 inst
.instruction
|= 0xd;
20911 inst
.instruction
|= 0xf;
20915 inst
.instruction
|= 0xf9000000;
20917 inst
.instruction
|= 0xf4000000;
20922 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20924 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20925 D register operands. */
20926 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20927 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20930 NEON_ENCODE (FPV8
, inst
);
20932 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20934 do_vfp_sp_dyadic ();
20936 /* ARMv8.2 fp16 instruction. */
20938 do_scalar_fp16_v82_encode ();
20941 do_vfp_dp_rd_rn_rm ();
20944 inst
.instruction
|= 0x100;
20946 inst
.instruction
|= 0xf0000000;
20952 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20954 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20955 first_error (_("invalid instruction shape"));
20961 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20962 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20964 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20967 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20970 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20974 do_vrint_1 (enum neon_cvt_mode mode
)
20976 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20977 struct neon_type_el et
;
20982 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20983 D register operands. */
20984 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20985 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20988 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20990 if (et
.type
!= NT_invtype
)
20992 /* VFP encodings. */
20993 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20994 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20995 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20997 NEON_ENCODE (FPV8
, inst
);
20998 if (rs
== NS_FF
|| rs
== NS_HH
)
20999 do_vfp_sp_monadic ();
21001 do_vfp_dp_rd_rm ();
21005 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21006 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21007 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21008 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21009 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21010 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21011 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21015 inst
.instruction
|= (rs
== NS_DD
) << 8;
21016 do_vfp_cond_or_thumb ();
21018 /* ARMv8.2 fp16 vrint instruction. */
21020 do_scalar_fp16_v82_encode ();
21024 /* Neon encodings (or something broken...). */
21026 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21028 if (et
.type
== NT_invtype
)
21031 if (!check_simd_pred_availability (TRUE
,
21032 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21035 NEON_ENCODE (FLOAT
, inst
);
21037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21038 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21039 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21040 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21041 inst
.instruction
|= neon_quad (rs
) << 6;
21042 /* Mask off the original size bits and reencode them. */
21043 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21044 | neon_logbits (et
.size
) << 18);
21048 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21049 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21050 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21051 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21052 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21053 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21054 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21059 inst
.instruction
|= 0xfc000000;
21061 inst
.instruction
|= 0xf0000000;
21068 do_vrint_1 (neon_cvt_mode_x
);
21074 do_vrint_1 (neon_cvt_mode_z
);
21080 do_vrint_1 (neon_cvt_mode_r
);
21086 do_vrint_1 (neon_cvt_mode_a
);
21092 do_vrint_1 (neon_cvt_mode_n
);
21098 do_vrint_1 (neon_cvt_mode_p
);
21104 do_vrint_1 (neon_cvt_mode_m
);
21108 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21110 unsigned regno
= NEON_SCALAR_REG (opnd
);
21111 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21113 if (elsize
== 16 && elno
< 2 && regno
< 16)
21114 return regno
| (elno
<< 4);
21115 else if (elsize
== 32 && elno
== 0)
21118 first_error (_("scalar out of range"));
21125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21126 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21127 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21128 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21129 _("expression too complex"));
21130 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21131 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21132 _("immediate out of range"));
21135 if (!check_simd_pred_availability (TRUE
,
21136 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21139 if (inst
.operands
[2].isscalar
)
21141 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21142 first_error (_("invalid instruction shape"));
21143 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21144 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21145 N_KEY
| N_F16
| N_F32
).size
;
21146 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21148 inst
.instruction
= 0xfe000800;
21149 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21150 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21151 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21152 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21153 inst
.instruction
|= LOW4 (m
);
21154 inst
.instruction
|= HI1 (m
) << 5;
21155 inst
.instruction
|= neon_quad (rs
) << 6;
21156 inst
.instruction
|= rot
<< 20;
21157 inst
.instruction
|= (size
== 32) << 23;
21161 enum neon_shape rs
;
21162 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21163 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21165 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21167 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21168 N_KEY
| N_F16
| N_F32
).size
;
21169 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21170 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21171 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21172 as_tsktsk (BAD_MVE_SRCDEST
);
21174 neon_three_same (neon_quad (rs
), 0, -1);
21175 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21176 inst
.instruction
|= 0xfc200800;
21177 inst
.instruction
|= rot
<< 23;
21178 inst
.instruction
|= (size
== 32) << 20;
21185 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21186 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21187 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21188 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21189 _("expression too complex"));
21191 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21192 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21193 enum neon_shape rs
;
21194 struct neon_type_el et
;
21195 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21197 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21198 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21202 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21203 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21205 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21206 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21207 "operand makes instruction UNPREDICTABLE"));
21210 if (et
.type
== NT_invtype
)
21213 if (!check_simd_pred_availability (et
.type
== NT_float
,
21214 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21217 if (et
.type
== NT_float
)
21219 neon_three_same (neon_quad (rs
), 0, -1);
21220 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21221 inst
.instruction
|= 0xfc800800;
21222 inst
.instruction
|= (rot
== 270) << 24;
21223 inst
.instruction
|= (et
.size
== 32) << 20;
21227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21228 inst
.instruction
= 0xfe000f00;
21229 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21230 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21231 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21233 inst
.instruction
|= (rot
== 270) << 12;
21234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21235 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21236 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21241 /* Dot Product instructions encoding support. */
21244 do_neon_dotproduct (int unsigned_p
)
21246 enum neon_shape rs
;
21247 unsigned scalar_oprd2
= 0;
21250 if (inst
.cond
!= COND_ALWAYS
)
21251 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21252 "is UNPREDICTABLE"));
21254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21257 /* Dot Product instructions are in three-same D/Q register format or the third
21258 operand can be a scalar index register. */
21259 if (inst
.operands
[2].isscalar
)
21261 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21262 high8
= 0xfe000000;
21263 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21267 high8
= 0xfc000000;
21268 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21272 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21274 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21276 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21277 Product instruction, so we pass 0 as the "ubit" parameter. And the
21278 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21279 neon_three_same (neon_quad (rs
), 0, 32);
21281 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21282 different NEON three-same encoding. */
21283 inst
.instruction
&= 0x00ffffff;
21284 inst
.instruction
|= high8
;
21285 /* Encode 'U' bit which indicates signedness. */
21286 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21287 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21288 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21289 the instruction encoding. */
21290 if (inst
.operands
[2].isscalar
)
21292 inst
.instruction
&= 0xffffffd0;
21293 inst
.instruction
|= LOW4 (scalar_oprd2
);
21294 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21298 /* Dot Product instructions for signed integer. */
21301 do_neon_dotproduct_s (void)
21303 return do_neon_dotproduct (0);
21306 /* Dot Product instructions for unsigned integer. */
21309 do_neon_dotproduct_u (void)
21311 return do_neon_dotproduct (1);
21314 /* Crypto v1 instructions. */
21316 do_crypto_2op_1 (unsigned elttype
, int op
)
21318 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21320 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21326 NEON_ENCODE (INTEGER
, inst
);
21327 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21328 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21329 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21330 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21332 inst
.instruction
|= op
<< 6;
21335 inst
.instruction
|= 0xfc000000;
21337 inst
.instruction
|= 0xf0000000;
21341 do_crypto_3op_1 (int u
, int op
)
21343 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21345 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21346 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21351 NEON_ENCODE (INTEGER
, inst
);
21352 neon_three_same (1, u
, 8 << op
);
21358 do_crypto_2op_1 (N_8
, 0);
21364 do_crypto_2op_1 (N_8
, 1);
21370 do_crypto_2op_1 (N_8
, 2);
21376 do_crypto_2op_1 (N_8
, 3);
21382 do_crypto_3op_1 (0, 0);
21388 do_crypto_3op_1 (0, 1);
21394 do_crypto_3op_1 (0, 2);
21400 do_crypto_3op_1 (0, 3);
21406 do_crypto_3op_1 (1, 0);
21412 do_crypto_3op_1 (1, 1);
21416 do_sha256su1 (void)
21418 do_crypto_3op_1 (1, 2);
21424 do_crypto_2op_1 (N_32
, -1);
21430 do_crypto_2op_1 (N_32
, 0);
21434 do_sha256su0 (void)
21436 do_crypto_2op_1 (N_32
, 1);
21440 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21442 unsigned int Rd
= inst
.operands
[0].reg
;
21443 unsigned int Rn
= inst
.operands
[1].reg
;
21444 unsigned int Rm
= inst
.operands
[2].reg
;
21446 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21447 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21448 inst
.instruction
|= LOW4 (Rn
) << 16;
21449 inst
.instruction
|= LOW4 (Rm
);
21450 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21451 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21453 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21454 as_warn (UNPRED_REG ("r15"));
21496 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21498 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21499 do_vfp_sp_dp_cvt ();
21500 do_vfp_cond_or_thumb ();
21504 /* Overall per-instruction processing. */
21506 /* We need to be able to fix up arbitrary expressions in some statements.
21507 This is so that we can handle symbols that are an arbitrary distance from
21508 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21509 which returns part of an address in a form which will be valid for
21510 a data instruction. We do this by pushing the expression into a symbol
21511 in the expr_section, and creating a fix for that. */
21514 fix_new_arm (fragS
* frag
,
21528 /* Create an absolute valued symbol, so we have something to
21529 refer to in the object file. Unfortunately for us, gas's
21530 generic expression parsing will already have folded out
21531 any use of .set foo/.type foo %function that may have
21532 been used to set type information of the target location,
21533 that's being specified symbolically. We have to presume
21534 the user knows what they are doing. */
21538 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21540 symbol
= symbol_find_or_make (name
);
21541 S_SET_SEGMENT (symbol
, absolute_section
);
21542 symbol_set_frag (symbol
, &zero_address_frag
);
21543 S_SET_VALUE (symbol
, exp
->X_add_number
);
21544 exp
->X_op
= O_symbol
;
21545 exp
->X_add_symbol
= symbol
;
21546 exp
->X_add_number
= 0;
21552 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21553 (enum bfd_reloc_code_real
) reloc
);
21557 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21558 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21562 /* Mark whether the fix is to a THUMB instruction, or an ARM
21564 new_fix
->tc_fix_data
= thumb_mode
;
21567 /* Create a frg for an instruction requiring relaxation. */
21569 output_relax_insn (void)
21575 /* The size of the instruction is unknown, so tie the debug info to the
21576 start of the instruction. */
21577 dwarf2_emit_insn (0);
21579 switch (inst
.relocs
[0].exp
.X_op
)
21582 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21583 offset
= inst
.relocs
[0].exp
.X_add_number
;
21587 offset
= inst
.relocs
[0].exp
.X_add_number
;
21590 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21594 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21595 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21596 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21599 /* Write a 32-bit thumb instruction to buf. */
21601 put_thumb32_insn (char * buf
, unsigned long insn
)
21603 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21604 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21608 output_inst (const char * str
)
21614 as_bad ("%s -- `%s'", inst
.error
, str
);
21619 output_relax_insn ();
21622 if (inst
.size
== 0)
21625 to
= frag_more (inst
.size
);
21626 /* PR 9814: Record the thumb mode into the current frag so that we know
21627 what type of NOP padding to use, if necessary. We override any previous
21628 setting so that if the mode has changed then the NOPS that we use will
21629 match the encoding of the last instruction in the frag. */
21630 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21632 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21634 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21635 put_thumb32_insn (to
, inst
.instruction
);
21637 else if (inst
.size
> INSN_SIZE
)
21639 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21640 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21641 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21644 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21647 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21649 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21650 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21651 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21652 inst
.relocs
[r
].type
);
21655 dwarf2_emit_insn (inst
.size
);
21659 output_it_inst (int cond
, int mask
, char * to
)
21661 unsigned long instruction
= 0xbf00;
21664 instruction
|= mask
;
21665 instruction
|= cond
<< 4;
21669 to
= frag_more (2);
21671 dwarf2_emit_insn (2);
21675 md_number_to_chars (to
, instruction
, 2);
21680 /* Tag values used in struct asm_opcode's tag field. */
21683 OT_unconditional
, /* Instruction cannot be conditionalized.
21684 The ARM condition field is still 0xE. */
21685 OT_unconditionalF
, /* Instruction cannot be conditionalized
21686 and carries 0xF in its ARM condition field. */
21687 OT_csuffix
, /* Instruction takes a conditional suffix. */
21688 OT_csuffixF
, /* Some forms of the instruction take a scalar
21689 conditional suffix, others place 0xF where the
21690 condition field would be, others take a vector
21691 conditional suffix. */
21692 OT_cinfix3
, /* Instruction takes a conditional infix,
21693 beginning at character index 3. (In
21694 unified mode, it becomes a suffix.) */
21695 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21696 tsts, cmps, cmns, and teqs. */
21697 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21698 character index 3, even in unified mode. Used for
21699 legacy instructions where suffix and infix forms
21700 may be ambiguous. */
21701 OT_csuf_or_in3
, /* Instruction takes either a conditional
21702 suffix or an infix at character index 3. */
21703 OT_odd_infix_unc
, /* This is the unconditional variant of an
21704 instruction that takes a conditional infix
21705 at an unusual position. In unified mode,
21706 this variant will accept a suffix. */
21707 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21708 are the conditional variants of instructions that
21709 take conditional infixes in unusual positions.
21710 The infix appears at character index
21711 (tag - OT_odd_infix_0). These are not accepted
21712 in unified mode. */
21715 /* Subroutine of md_assemble, responsible for looking up the primary
21716 opcode from the mnemonic the user wrote. STR points to the
21717 beginning of the mnemonic.
21719 This is not simply a hash table lookup, because of conditional
21720 variants. Most instructions have conditional variants, which are
21721 expressed with a _conditional affix_ to the mnemonic. If we were
21722 to encode each conditional variant as a literal string in the opcode
21723 table, it would have approximately 20,000 entries.
21725 Most mnemonics take this affix as a suffix, and in unified syntax,
21726 'most' is upgraded to 'all'. However, in the divided syntax, some
21727 instructions take the affix as an infix, notably the s-variants of
21728 the arithmetic instructions. Of those instructions, all but six
21729 have the infix appear after the third character of the mnemonic.
21731 Accordingly, the algorithm for looking up primary opcodes given
21734 1. Look up the identifier in the opcode table.
21735 If we find a match, go to step U.
21737 2. Look up the last two characters of the identifier in the
21738 conditions table. If we find a match, look up the first N-2
21739 characters of the identifier in the opcode table. If we
21740 find a match, go to step CE.
21742 3. Look up the fourth and fifth characters of the identifier in
21743 the conditions table. If we find a match, extract those
21744 characters from the identifier, and look up the remaining
21745 characters in the opcode table. If we find a match, go
21750 U. Examine the tag field of the opcode structure, in case this is
21751 one of the six instructions with its conditional infix in an
21752 unusual place. If it is, the tag tells us where to find the
21753 infix; look it up in the conditions table and set inst.cond
21754 accordingly. Otherwise, this is an unconditional instruction.
21755 Again set inst.cond accordingly. Return the opcode structure.
21757 CE. Examine the tag field to make sure this is an instruction that
21758 should receive a conditional suffix. If it is not, fail.
21759 Otherwise, set inst.cond from the suffix we already looked up,
21760 and return the opcode structure.
21762 CM. Examine the tag field to make sure this is an instruction that
21763 should receive a conditional infix after the third character.
21764 If it is not, fail. Otherwise, undo the edits to the current
21765 line of input and proceed as for case CE. */
21767 static const struct asm_opcode
*
21768 opcode_lookup (char **str
)
21772 const struct asm_opcode
*opcode
;
21773 const struct asm_cond
*cond
;
21776 /* Scan up to the end of the mnemonic, which must end in white space,
21777 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21778 for (base
= end
= *str
; *end
!= '\0'; end
++)
21779 if (*end
== ' ' || *end
== '.')
21785 /* Handle a possible width suffix and/or Neon type suffix. */
21790 /* The .w and .n suffixes are only valid if the unified syntax is in
21792 if (unified_syntax
&& end
[1] == 'w')
21794 else if (unified_syntax
&& end
[1] == 'n')
21799 inst
.vectype
.elems
= 0;
21801 *str
= end
+ offset
;
21803 if (end
[offset
] == '.')
21805 /* See if we have a Neon type suffix (possible in either unified or
21806 non-unified ARM syntax mode). */
21807 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21810 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21816 /* Look for unaffixed or special-case affixed mnemonic. */
21817 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21822 if (opcode
->tag
< OT_odd_infix_0
)
21824 inst
.cond
= COND_ALWAYS
;
21828 if (warn_on_deprecated
&& unified_syntax
)
21829 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21830 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21831 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21834 inst
.cond
= cond
->value
;
21837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21839 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21841 if (end
- base
< 2)
21844 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21845 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21847 /* If this opcode can not be vector predicated then don't accept it with a
21848 vector predication code. */
21849 if (opcode
&& !opcode
->mayBeVecPred
)
21852 if (!opcode
|| !cond
)
21854 /* Cannot have a conditional suffix on a mnemonic of less than two
21856 if (end
- base
< 3)
21859 /* Look for suffixed mnemonic. */
21861 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21862 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21866 if (opcode
&& cond
)
21869 switch (opcode
->tag
)
21871 case OT_cinfix3_legacy
:
21872 /* Ignore conditional suffixes matched on infix only mnemonics. */
21876 case OT_cinfix3_deprecated
:
21877 case OT_odd_infix_unc
:
21878 if (!unified_syntax
)
21880 /* Fall through. */
21884 case OT_csuf_or_in3
:
21885 inst
.cond
= cond
->value
;
21888 case OT_unconditional
:
21889 case OT_unconditionalF
:
21891 inst
.cond
= cond
->value
;
21894 /* Delayed diagnostic. */
21895 inst
.error
= BAD_COND
;
21896 inst
.cond
= COND_ALWAYS
;
21905 /* Cannot have a usual-position infix on a mnemonic of less than
21906 six characters (five would be a suffix). */
21907 if (end
- base
< 6)
21910 /* Look for infixed mnemonic in the usual position. */
21912 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21916 memcpy (save
, affix
, 2);
21917 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21918 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21920 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21921 memcpy (affix
, save
, 2);
21924 && (opcode
->tag
== OT_cinfix3
21925 || opcode
->tag
== OT_cinfix3_deprecated
21926 || opcode
->tag
== OT_csuf_or_in3
21927 || opcode
->tag
== OT_cinfix3_legacy
))
21930 if (warn_on_deprecated
&& unified_syntax
21931 && (opcode
->tag
== OT_cinfix3
21932 || opcode
->tag
== OT_cinfix3_deprecated
))
21933 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21935 inst
.cond
= cond
->value
;
21942 /* This function generates an initial IT instruction, leaving its block
21943 virtually open for the new instructions. Eventually,
21944 the mask will be updated by now_pred_add_mask () each time
21945 a new instruction needs to be included in the IT block.
21946 Finally, the block is closed with close_automatic_it_block ().
21947 The block closure can be requested either from md_assemble (),
21948 a tencode (), or due to a label hook. */
21951 new_automatic_it_block (int cond
)
21953 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21954 now_pred
.mask
= 0x18;
21955 now_pred
.cc
= cond
;
21956 now_pred
.block_length
= 1;
21957 mapping_state (MAP_THUMB
);
21958 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21959 now_pred
.warn_deprecated
= FALSE
;
21960 now_pred
.insn_cond
= TRUE
;
21963 /* Close an automatic IT block.
21964 See comments in new_automatic_it_block (). */
21967 close_automatic_it_block (void)
21969 now_pred
.mask
= 0x10;
21970 now_pred
.block_length
= 0;
21973 /* Update the mask of the current automatically-generated IT
21974 instruction. See comments in new_automatic_it_block (). */
21977 now_pred_add_mask (int cond
)
21979 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21980 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21981 | ((bitvalue) << (nbit)))
21982 const int resulting_bit
= (cond
& 1);
21984 now_pred
.mask
&= 0xf;
21985 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21987 (5 - now_pred
.block_length
));
21988 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21990 ((5 - now_pred
.block_length
) - 1));
21991 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21994 #undef SET_BIT_VALUE
21997 /* The IT blocks handling machinery is accessed through the these functions:
21998 it_fsm_pre_encode () from md_assemble ()
21999 set_pred_insn_type () optional, from the tencode functions
22000 set_pred_insn_type_last () ditto
22001 in_pred_block () ditto
22002 it_fsm_post_encode () from md_assemble ()
22003 force_automatic_it_block_close () from label handling functions
22006 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22007 initializing the IT insn type with a generic initial value depending
22008 on the inst.condition.
22009 2) During the tencode function, two things may happen:
22010 a) The tencode function overrides the IT insn type by
22011 calling either set_pred_insn_type (type) or
22012 set_pred_insn_type_last ().
22013 b) The tencode function queries the IT block state by
22014 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22016 Both set_pred_insn_type and in_pred_block run the internal FSM state
22017 handling function (handle_pred_state), because: a) setting the IT insn
22018 type may incur in an invalid state (exiting the function),
22019 and b) querying the state requires the FSM to be updated.
22020 Specifically we want to avoid creating an IT block for conditional
22021 branches, so it_fsm_pre_encode is actually a guess and we can't
22022 determine whether an IT block is required until the tencode () routine
22023 has decided what type of instruction this actually it.
22024 Because of this, if set_pred_insn_type and in_pred_block have to be
22025 used, set_pred_insn_type has to be called first.
22027 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22028 that determines the insn IT type depending on the inst.cond code.
22029 When a tencode () routine encodes an instruction that can be
22030 either outside an IT block, or, in the case of being inside, has to be
22031 the last one, set_pred_insn_type_last () will determine the proper
22032 IT instruction type based on the inst.cond code. Otherwise,
22033 set_pred_insn_type can be called for overriding that logic or
22034 for covering other cases.
22036 Calling handle_pred_state () may not transition the IT block state to
22037 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22038 still queried. Instead, if the FSM determines that the state should
22039 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22040 after the tencode () function: that's what it_fsm_post_encode () does.
22042 Since in_pred_block () calls the state handling function to get an
22043 updated state, an error may occur (due to invalid insns combination).
22044 In that case, inst.error is set.
22045 Therefore, inst.error has to be checked after the execution of
22046 the tencode () routine.
22048 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22049 any pending state change (if any) that didn't take place in
22050 handle_pred_state () as explained above. */
22053 it_fsm_pre_encode (void)
22055 if (inst
.cond
!= COND_ALWAYS
)
22056 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22058 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22060 now_pred
.state_handled
= 0;
22063 /* IT state FSM handling function. */
22064 /* MVE instructions and non-MVE instructions are handled differently because of
22065 the introduction of VPT blocks.
22066 Specifications say that any non-MVE instruction inside a VPT block is
22067 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22068 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22069 few exceptions we have MVE_UNPREDICABLE_INSN.
22070 The error messages provided depending on the different combinations possible
22071 are described in the cases below:
22072 For 'most' MVE instructions:
22073 1) In an IT block, with an IT code: syntax error
22074 2) In an IT block, with a VPT code: error: must be in a VPT block
22075 3) In an IT block, with no code: warning: UNPREDICTABLE
22076 4) In a VPT block, with an IT code: syntax error
22077 5) In a VPT block, with a VPT code: OK!
22078 6) In a VPT block, with no code: error: missing code
22079 7) Outside a pred block, with an IT code: error: syntax error
22080 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22081 9) Outside a pred block, with no code: OK!
22082 For non-MVE instructions:
22083 10) In an IT block, with an IT code: OK!
22084 11) In an IT block, with a VPT code: syntax error
22085 12) In an IT block, with no code: error: missing code
22086 13) In a VPT block, with an IT code: error: should be in an IT block
22087 14) In a VPT block, with a VPT code: syntax error
22088 15) In a VPT block, with no code: UNPREDICTABLE
22089 16) Outside a pred block, with an IT code: error: should be in an IT block
22090 17) Outside a pred block, with a VPT code: syntax error
22091 18) Outside a pred block, with no code: OK!
22096 handle_pred_state (void)
22098 now_pred
.state_handled
= 1;
22099 now_pred
.insn_cond
= FALSE
;
22101 switch (now_pred
.state
)
22103 case OUTSIDE_PRED_BLOCK
:
22104 switch (inst
.pred_insn_type
)
22106 case MVE_UNPREDICABLE_INSN
:
22107 case MVE_OUTSIDE_PRED_INSN
:
22108 if (inst
.cond
< COND_ALWAYS
)
22110 /* Case 7: Outside a pred block, with an IT code: error: syntax
22112 inst
.error
= BAD_SYNTAX
;
22115 /* Case 9: Outside a pred block, with no code: OK! */
22117 case OUTSIDE_PRED_INSN
:
22118 if (inst
.cond
> COND_ALWAYS
)
22120 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22122 inst
.error
= BAD_SYNTAX
;
22125 /* Case 18: Outside a pred block, with no code: OK! */
22128 case INSIDE_VPT_INSN
:
22129 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22131 inst
.error
= BAD_OUT_VPT
;
22134 case INSIDE_IT_INSN
:
22135 case INSIDE_IT_LAST_INSN
:
22136 if (inst
.cond
< COND_ALWAYS
)
22138 /* Case 16: Outside a pred block, with an IT code: error: should
22139 be in an IT block. */
22140 if (thumb_mode
== 0)
22143 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22144 as_tsktsk (_("Warning: conditional outside an IT block"\
22149 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22150 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22152 /* Automatically generate the IT instruction. */
22153 new_automatic_it_block (inst
.cond
);
22154 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22155 close_automatic_it_block ();
22159 inst
.error
= BAD_OUT_IT
;
22165 else if (inst
.cond
> COND_ALWAYS
)
22167 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22169 inst
.error
= BAD_SYNTAX
;
22174 case IF_INSIDE_IT_LAST_INSN
:
22175 case NEUTRAL_IT_INSN
:
22179 if (inst
.cond
!= COND_ALWAYS
)
22180 first_error (BAD_SYNTAX
);
22181 now_pred
.state
= MANUAL_PRED_BLOCK
;
22182 now_pred
.block_length
= 0;
22183 now_pred
.type
= VECTOR_PRED
;
22187 now_pred
.state
= MANUAL_PRED_BLOCK
;
22188 now_pred
.block_length
= 0;
22189 now_pred
.type
= SCALAR_PRED
;
22194 case AUTOMATIC_PRED_BLOCK
:
22195 /* Three things may happen now:
22196 a) We should increment current it block size;
22197 b) We should close current it block (closing insn or 4 insns);
22198 c) We should close current it block and start a new one (due
22199 to incompatible conditions or
22200 4 insns-length block reached). */
22202 switch (inst
.pred_insn_type
)
22204 case INSIDE_VPT_INSN
:
22206 case MVE_UNPREDICABLE_INSN
:
22207 case MVE_OUTSIDE_PRED_INSN
:
22209 case OUTSIDE_PRED_INSN
:
22210 /* The closure of the block shall happen immediately,
22211 so any in_pred_block () call reports the block as closed. */
22212 force_automatic_it_block_close ();
22215 case INSIDE_IT_INSN
:
22216 case INSIDE_IT_LAST_INSN
:
22217 case IF_INSIDE_IT_LAST_INSN
:
22218 now_pred
.block_length
++;
22220 if (now_pred
.block_length
> 4
22221 || !now_pred_compatible (inst
.cond
))
22223 force_automatic_it_block_close ();
22224 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22225 new_automatic_it_block (inst
.cond
);
22229 now_pred
.insn_cond
= TRUE
;
22230 now_pred_add_mask (inst
.cond
);
22233 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22234 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22235 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22236 close_automatic_it_block ();
22239 case NEUTRAL_IT_INSN
:
22240 now_pred
.block_length
++;
22241 now_pred
.insn_cond
= TRUE
;
22243 if (now_pred
.block_length
> 4)
22244 force_automatic_it_block_close ();
22246 now_pred_add_mask (now_pred
.cc
& 1);
22250 close_automatic_it_block ();
22251 now_pred
.state
= MANUAL_PRED_BLOCK
;
22256 case MANUAL_PRED_BLOCK
:
22259 if (now_pred
.type
== SCALAR_PRED
)
22261 /* Check conditional suffixes. */
22262 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22263 now_pred
.mask
<<= 1;
22264 now_pred
.mask
&= 0x1f;
22265 is_last
= (now_pred
.mask
== 0x10);
22269 now_pred
.cc
^= (now_pred
.mask
>> 4);
22270 cond
= now_pred
.cc
+ 0xf;
22271 now_pred
.mask
<<= 1;
22272 now_pred
.mask
&= 0x1f;
22273 is_last
= now_pred
.mask
== 0x10;
22275 now_pred
.insn_cond
= TRUE
;
22277 switch (inst
.pred_insn_type
)
22279 case OUTSIDE_PRED_INSN
:
22280 if (now_pred
.type
== SCALAR_PRED
)
22282 if (inst
.cond
== COND_ALWAYS
)
22284 /* Case 12: In an IT block, with no code: error: missing
22286 inst
.error
= BAD_NOT_IT
;
22289 else if (inst
.cond
> COND_ALWAYS
)
22291 /* Case 11: In an IT block, with a VPT code: syntax error.
22293 inst
.error
= BAD_SYNTAX
;
22296 else if (thumb_mode
)
22298 /* This is for some special cases where a non-MVE
22299 instruction is not allowed in an IT block, such as cbz,
22300 but are put into one with a condition code.
22301 You could argue this should be a syntax error, but we
22302 gave the 'not allowed in IT block' diagnostic in the
22303 past so we will keep doing so. */
22304 inst
.error
= BAD_NOT_IT
;
22311 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22312 as_tsktsk (MVE_NOT_VPT
);
22315 case MVE_OUTSIDE_PRED_INSN
:
22316 if (now_pred
.type
== SCALAR_PRED
)
22318 if (inst
.cond
== COND_ALWAYS
)
22320 /* Case 3: In an IT block, with no code: warning:
22322 as_tsktsk (MVE_NOT_IT
);
22325 else if (inst
.cond
< COND_ALWAYS
)
22327 /* Case 1: In an IT block, with an IT code: syntax error.
22329 inst
.error
= BAD_SYNTAX
;
22337 if (inst
.cond
< COND_ALWAYS
)
22339 /* Case 4: In a VPT block, with an IT code: syntax error.
22341 inst
.error
= BAD_SYNTAX
;
22344 else if (inst
.cond
== COND_ALWAYS
)
22346 /* Case 6: In a VPT block, with no code: error: missing
22348 inst
.error
= BAD_NOT_VPT
;
22356 case MVE_UNPREDICABLE_INSN
:
22357 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22359 case INSIDE_IT_INSN
:
22360 if (inst
.cond
> COND_ALWAYS
)
22362 /* Case 11: In an IT block, with a VPT code: syntax error. */
22363 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22364 inst
.error
= BAD_SYNTAX
;
22367 else if (now_pred
.type
== SCALAR_PRED
)
22369 /* Case 10: In an IT block, with an IT code: OK! */
22370 if (cond
!= inst
.cond
)
22372 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22379 /* Case 13: In a VPT block, with an IT code: error: should be
22381 inst
.error
= BAD_OUT_IT
;
22386 case INSIDE_VPT_INSN
:
22387 if (now_pred
.type
== SCALAR_PRED
)
22389 /* Case 2: In an IT block, with a VPT code: error: must be in a
22391 inst
.error
= BAD_OUT_VPT
;
22394 /* Case 5: In a VPT block, with a VPT code: OK! */
22395 else if (cond
!= inst
.cond
)
22397 inst
.error
= BAD_VPT_COND
;
22401 case INSIDE_IT_LAST_INSN
:
22402 case IF_INSIDE_IT_LAST_INSN
:
22403 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22405 /* Case 4: In a VPT block, with an IT code: syntax error. */
22406 /* Case 11: In an IT block, with a VPT code: syntax error. */
22407 inst
.error
= BAD_SYNTAX
;
22410 else if (cond
!= inst
.cond
)
22412 inst
.error
= BAD_IT_COND
;
22417 inst
.error
= BAD_BRANCH
;
22422 case NEUTRAL_IT_INSN
:
22423 /* The BKPT instruction is unconditional even in a IT or VPT
22428 if (now_pred
.type
== SCALAR_PRED
)
22430 inst
.error
= BAD_IT_IT
;
22433 /* fall through. */
22435 if (inst
.cond
== COND_ALWAYS
)
22437 /* Executing a VPT/VPST instruction inside an IT block or a
22438 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22440 if (now_pred
.type
== SCALAR_PRED
)
22441 as_tsktsk (MVE_NOT_IT
);
22443 as_tsktsk (MVE_NOT_VPT
);
22448 /* VPT/VPST do not accept condition codes. */
22449 inst
.error
= BAD_SYNTAX
;
22460 struct depr_insn_mask
22462 unsigned long pattern
;
22463 unsigned long mask
;
22464 const char* description
;
22467 /* List of 16-bit instruction patterns deprecated in an IT block in
22469 static const struct depr_insn_mask depr_it_insns
[] = {
22470 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22471 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22472 { 0xa000, 0xb800, N_("ADR") },
22473 { 0x4800, 0xf800, N_("Literal loads") },
22474 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22475 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22476 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22477 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22478 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22483 it_fsm_post_encode (void)
22487 if (!now_pred
.state_handled
)
22488 handle_pred_state ();
22490 if (now_pred
.insn_cond
22491 && !now_pred
.warn_deprecated
22492 && warn_on_deprecated
22493 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22494 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22496 if (inst
.instruction
>= 0x10000)
22498 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22499 "performance deprecated in ARMv8-A and ARMv8-R"));
22500 now_pred
.warn_deprecated
= TRUE
;
22504 const struct depr_insn_mask
*p
= depr_it_insns
;
22506 while (p
->mask
!= 0)
22508 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22510 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22511 "instructions of the following class are "
22512 "performance deprecated in ARMv8-A and "
22513 "ARMv8-R: %s"), p
->description
);
22514 now_pred
.warn_deprecated
= TRUE
;
22522 if (now_pred
.block_length
> 1)
22524 as_tsktsk (_("IT blocks containing more than one conditional "
22525 "instruction are performance deprecated in ARMv8-A and "
22527 now_pred
.warn_deprecated
= TRUE
;
22531 is_last
= (now_pred
.mask
== 0x10);
22534 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22540 force_automatic_it_block_close (void)
22542 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22544 close_automatic_it_block ();
22545 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22551 in_pred_block (void)
22553 if (!now_pred
.state_handled
)
22554 handle_pred_state ();
22556 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22559 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22560 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22561 here, hence the "known" in the function name. */
22564 known_t32_only_insn (const struct asm_opcode
*opcode
)
22566 /* Original Thumb-1 wide instruction. */
22567 if (opcode
->tencode
== do_t_blx
22568 || opcode
->tencode
== do_t_branch23
22569 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22570 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22573 /* Wide-only instruction added to ARMv8-M Baseline. */
22574 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22575 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22576 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22577 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22583 /* Whether wide instruction variant can be used if available for a valid OPCODE
22587 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22589 if (known_t32_only_insn (opcode
))
22592 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22593 of variant T3 of B.W is checked in do_t_branch. */
22594 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22595 && opcode
->tencode
== do_t_branch
)
22598 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22599 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22600 && opcode
->tencode
== do_t_mov_cmp
22601 /* Make sure CMP instruction is not affected. */
22602 && opcode
->aencode
== do_mov
)
22605 /* Wide instruction variants of all instructions with narrow *and* wide
22606 variants become available with ARMv6t2. Other opcodes are either
22607 narrow-only or wide-only and are thus available if OPCODE is valid. */
22608 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22611 /* OPCODE with narrow only instruction variant or wide variant not
22617 md_assemble (char *str
)
22620 const struct asm_opcode
* opcode
;
22622 /* Align the previous label if needed. */
22623 if (last_label_seen
!= NULL
)
22625 symbol_set_frag (last_label_seen
, frag_now
);
22626 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22627 S_SET_SEGMENT (last_label_seen
, now_seg
);
22630 memset (&inst
, '\0', sizeof (inst
));
22632 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22633 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22635 opcode
= opcode_lookup (&p
);
22638 /* It wasn't an instruction, but it might be a register alias of
22639 the form alias .req reg, or a Neon .dn/.qn directive. */
22640 if (! create_register_alias (str
, p
)
22641 && ! create_neon_reg_alias (str
, p
))
22642 as_bad (_("bad instruction `%s'"), str
);
22647 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22648 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22650 /* The value which unconditional instructions should have in place of the
22651 condition field. */
22652 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22656 arm_feature_set variant
;
22658 variant
= cpu_variant
;
22659 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22660 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22661 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22662 /* Check that this instruction is supported for this CPU. */
22663 if (!opcode
->tvariant
22664 || (thumb_mode
== 1
22665 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22667 if (opcode
->tencode
== do_t_swi
)
22668 as_bad (_("SVC is not permitted on this architecture"));
22670 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22673 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22674 && opcode
->tencode
!= do_t_branch
)
22676 as_bad (_("Thumb does not support conditional execution"));
22680 /* Two things are addressed here:
22681 1) Implicit require narrow instructions on Thumb-1.
22682 This avoids relaxation accidentally introducing Thumb-2
22684 2) Reject wide instructions in non Thumb-2 cores.
22686 Only instructions with narrow and wide variants need to be handled
22687 but selecting all non wide-only instructions is easier. */
22688 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22689 && !t32_insn_ok (variant
, opcode
))
22691 if (inst
.size_req
== 0)
22693 else if (inst
.size_req
== 4)
22695 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22696 as_bad (_("selected processor does not support 32bit wide "
22697 "variant of instruction `%s'"), str
);
22699 as_bad (_("selected processor does not support `%s' in "
22700 "Thumb-2 mode"), str
);
22705 inst
.instruction
= opcode
->tvalue
;
22707 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22709 /* Prepare the pred_insn_type for those encodings that don't set
22711 it_fsm_pre_encode ();
22713 opcode
->tencode ();
22715 it_fsm_post_encode ();
22718 if (!(inst
.error
|| inst
.relax
))
22720 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22721 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22722 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22724 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22729 /* Something has gone badly wrong if we try to relax a fixed size
22731 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22733 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22734 *opcode
->tvariant
);
22735 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22736 set those bits when Thumb-2 32-bit instructions are seen. The impact
22737 of relaxable instructions will be considered later after we finish all
22739 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22740 variant
= arm_arch_none
;
22742 variant
= cpu_variant
;
22743 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22744 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22747 check_neon_suffixes
;
22751 mapping_state (MAP_THUMB
);
22754 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22758 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22759 is_bx
= (opcode
->aencode
== do_bx
);
22761 /* Check that this instruction is supported for this CPU. */
22762 if (!(is_bx
&& fix_v4bx
)
22763 && !(opcode
->avariant
&&
22764 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22766 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22771 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22775 inst
.instruction
= opcode
->avalue
;
22776 if (opcode
->tag
== OT_unconditionalF
)
22777 inst
.instruction
|= 0xFU
<< 28;
22779 inst
.instruction
|= inst
.cond
<< 28;
22780 inst
.size
= INSN_SIZE
;
22781 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22783 it_fsm_pre_encode ();
22784 opcode
->aencode ();
22785 it_fsm_post_encode ();
22787 /* Arm mode bx is marked as both v4T and v5 because it's still required
22788 on a hypothetical non-thumb v5 core. */
22790 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22792 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22793 *opcode
->avariant
);
22795 check_neon_suffixes
;
22799 mapping_state (MAP_ARM
);
22804 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22812 check_pred_blocks_finished (void)
22817 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22818 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22819 == MANUAL_PRED_BLOCK
)
22821 if (now_pred
.type
== SCALAR_PRED
)
22822 as_warn (_("section '%s' finished with an open IT block."),
22825 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22829 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22831 if (now_pred
.type
== SCALAR_PRED
)
22832 as_warn (_("file finished with an open IT block."));
22834 as_warn (_("file finished with an open VPT/VPST block."));
22839 /* Various frobbings of labels and their addresses. */
22842 arm_start_line_hook (void)
22844 last_label_seen
= NULL
;
22848 arm_frob_label (symbolS
* sym
)
22850 last_label_seen
= sym
;
22852 ARM_SET_THUMB (sym
, thumb_mode
);
22854 #if defined OBJ_COFF || defined OBJ_ELF
22855 ARM_SET_INTERWORK (sym
, support_interwork
);
22858 force_automatic_it_block_close ();
22860 /* Note - do not allow local symbols (.Lxxx) to be labelled
22861 as Thumb functions. This is because these labels, whilst
22862 they exist inside Thumb code, are not the entry points for
22863 possible ARM->Thumb calls. Also, these labels can be used
22864 as part of a computed goto or switch statement. eg gcc
22865 can generate code that looks like this:
22867 ldr r2, [pc, .Laaa]
22877 The first instruction loads the address of the jump table.
22878 The second instruction converts a table index into a byte offset.
22879 The third instruction gets the jump address out of the table.
22880 The fourth instruction performs the jump.
22882 If the address stored at .Laaa is that of a symbol which has the
22883 Thumb_Func bit set, then the linker will arrange for this address
22884 to have the bottom bit set, which in turn would mean that the
22885 address computation performed by the third instruction would end
22886 up with the bottom bit set. Since the ARM is capable of unaligned
22887 word loads, the instruction would then load the incorrect address
22888 out of the jump table, and chaos would ensue. */
22889 if (label_is_thumb_function_name
22890 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22891 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
22893 /* When the address of a Thumb function is taken the bottom
22894 bit of that address should be set. This will allow
22895 interworking between Arm and Thumb functions to work
22898 THUMB_SET_FUNC (sym
, 1);
22900 label_is_thumb_function_name
= FALSE
;
22903 dwarf2_emit_label (sym
);
22907 arm_data_in_code (void)
22909 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22911 *input_line_pointer
= '/';
22912 input_line_pointer
+= 5;
22913 *input_line_pointer
= 0;
22921 arm_canonicalize_symbol_name (char * name
)
22925 if (thumb_mode
&& (len
= strlen (name
)) > 5
22926 && streq (name
+ len
- 5, "/data"))
22927 *(name
+ len
- 5) = 0;
22932 /* Table of all register names defined by default. The user can
22933 define additional names with .req. Note that all register names
22934 should appear in both upper and lowercase variants. Some registers
22935 also have mixed-case names. */
22937 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22938 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22939 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22940 #define REGSET(p,t) \
22941 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22942 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22943 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22944 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22945 #define REGSETH(p,t) \
22946 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22947 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22948 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22949 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22950 #define REGSET2(p,t) \
22951 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22952 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22953 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22954 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22955 #define SPLRBANK(base,bank,t) \
22956 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22957 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22958 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22959 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22960 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22961 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22963 static const struct reg_entry reg_names
[] =
22965 /* ARM integer registers. */
22966 REGSET(r
, RN
), REGSET(R
, RN
),
22968 /* ATPCS synonyms. */
22969 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22970 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22971 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22973 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22974 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22975 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22977 /* Well-known aliases. */
22978 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22979 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22981 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22982 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22984 /* Defining the new Zero register from ARMv8.1-M. */
22988 /* Coprocessor numbers. */
22989 REGSET(p
, CP
), REGSET(P
, CP
),
22991 /* Coprocessor register numbers. The "cr" variants are for backward
22993 REGSET(c
, CN
), REGSET(C
, CN
),
22994 REGSET(cr
, CN
), REGSET(CR
, CN
),
22996 /* ARM banked registers. */
22997 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22998 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22999 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23000 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23001 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23002 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23003 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23005 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23006 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23007 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23008 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23009 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23010 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23011 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23012 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23014 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23015 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23016 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23017 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23018 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23019 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23020 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23021 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23022 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23024 /* FPA registers. */
23025 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23026 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23028 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23029 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23031 /* VFP SP registers. */
23032 REGSET(s
,VFS
), REGSET(S
,VFS
),
23033 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23035 /* VFP DP Registers. */
23036 REGSET(d
,VFD
), REGSET(D
,VFD
),
23037 /* Extra Neon DP registers. */
23038 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23040 /* Neon QP registers. */
23041 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23043 /* VFP control registers. */
23044 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23045 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23046 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23047 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23048 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23049 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23050 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23051 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23052 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23053 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23054 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23056 /* Maverick DSP coprocessor registers. */
23057 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23058 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23060 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23061 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23062 REGDEF(dspsc
,0,DSPSC
),
23064 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23065 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23066 REGDEF(DSPSC
,0,DSPSC
),
23068 /* iWMMXt data registers - p0, c0-15. */
23069 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23071 /* iWMMXt control registers - p1, c0-3. */
23072 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23073 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23074 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23075 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23077 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23078 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23079 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23080 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23081 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23083 /* XScale accumulator registers. */
23084 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23090 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23091 within psr_required_here. */
23092 static const struct asm_psr psrs
[] =
23094 /* Backward compatibility notation. Note that "all" is no longer
23095 truly all possible PSR bits. */
23096 {"all", PSR_c
| PSR_f
},
23100 /* Individual flags. */
23106 /* Combinations of flags. */
23107 {"fs", PSR_f
| PSR_s
},
23108 {"fx", PSR_f
| PSR_x
},
23109 {"fc", PSR_f
| PSR_c
},
23110 {"sf", PSR_s
| PSR_f
},
23111 {"sx", PSR_s
| PSR_x
},
23112 {"sc", PSR_s
| PSR_c
},
23113 {"xf", PSR_x
| PSR_f
},
23114 {"xs", PSR_x
| PSR_s
},
23115 {"xc", PSR_x
| PSR_c
},
23116 {"cf", PSR_c
| PSR_f
},
23117 {"cs", PSR_c
| PSR_s
},
23118 {"cx", PSR_c
| PSR_x
},
23119 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23120 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23121 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23122 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23123 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23124 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23125 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23126 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23127 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23128 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23129 {"scf", PSR_s
| PSR_c
| PSR_f
},
23130 {"scx", PSR_s
| PSR_c
| PSR_x
},
23131 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23132 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23133 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23134 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23135 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23136 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23137 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23138 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23139 {"csf", PSR_c
| PSR_s
| PSR_f
},
23140 {"csx", PSR_c
| PSR_s
| PSR_x
},
23141 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23142 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23143 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23144 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23145 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23146 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23147 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23148 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23149 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23150 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23151 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23152 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23153 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23154 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23155 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23156 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23157 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23158 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23159 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23160 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23161 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23162 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23163 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23164 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23165 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23166 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23169 /* Table of V7M psr names. */
23170 static const struct asm_psr v7m_psrs
[] =
23172 {"apsr", 0x0 }, {"APSR", 0x0 },
23173 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23174 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23175 {"psr", 0x3 }, {"PSR", 0x3 },
23176 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23177 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23178 {"epsr", 0x6 }, {"EPSR", 0x6 },
23179 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23180 {"msp", 0x8 }, {"MSP", 0x8 },
23181 {"psp", 0x9 }, {"PSP", 0x9 },
23182 {"msplim", 0xa }, {"MSPLIM", 0xa },
23183 {"psplim", 0xb }, {"PSPLIM", 0xb },
23184 {"primask", 0x10}, {"PRIMASK", 0x10},
23185 {"basepri", 0x11}, {"BASEPRI", 0x11},
23186 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23187 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23188 {"control", 0x14}, {"CONTROL", 0x14},
23189 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23190 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23191 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23192 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23193 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23194 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23195 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23196 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23197 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23200 /* Table of all shift-in-operand names. */
23201 static const struct asm_shift_name shift_names
[] =
23203 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23204 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23205 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23206 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23207 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23208 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23209 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23212 /* Table of all explicit relocation names. */
23214 static struct reloc_entry reloc_names
[] =
23216 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23217 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23218 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23219 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23220 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23221 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23222 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23223 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23224 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23225 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23226 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23227 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23228 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23229 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23230 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23231 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23232 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23233 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23234 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23235 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23236 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23237 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23238 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23239 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23240 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23241 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23242 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23246 /* Table of all conditional affixes. */
23247 static const struct asm_cond conds
[] =
23251 {"cs", 0x2}, {"hs", 0x2},
23252 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23265 static const struct asm_cond vconds
[] =
23271 #define UL_BARRIER(L,U,CODE,FEAT) \
23272 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23273 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23275 static struct asm_barrier_opt barrier_opt_names
[] =
23277 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23278 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23279 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23280 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23281 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23282 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23283 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23284 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23285 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23286 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23287 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23288 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23289 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23290 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23291 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23292 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23297 /* Table of ARM-format instructions. */
23299 /* Macros for gluing together operand strings. N.B. In all cases
23300 other than OPS0, the trailing OP_stop comes from default
23301 zero-initialization of the unspecified elements of the array. */
23302 #define OPS0() { OP_stop, }
23303 #define OPS1(a) { OP_##a, }
23304 #define OPS2(a,b) { OP_##a,OP_##b, }
23305 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23306 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23307 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23308 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23310 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23311 This is useful when mixing operands for ARM and THUMB, i.e. using the
23312 MIX_ARM_THUMB_OPERANDS macro.
23313 In order to use these macros, prefix the number of operands with _
23315 #define OPS_1(a) { a, }
23316 #define OPS_2(a,b) { a,b, }
23317 #define OPS_3(a,b,c) { a,b,c, }
23318 #define OPS_4(a,b,c,d) { a,b,c,d, }
23319 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23320 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23322 /* These macros abstract out the exact format of the mnemonic table and
23323 save some repeated characters. */
23325 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23326 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23327 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23328 THUMB_VARIANT, do_##ae, do_##te, 0 }
23330 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23331 a T_MNEM_xyz enumerator. */
23332 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23333 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23334 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23335 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23337 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23338 infix after the third character. */
23339 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23340 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23341 THUMB_VARIANT, do_##ae, do_##te, 0 }
23342 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23343 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23344 THUMB_VARIANT, do_##ae, do_##te, 0 }
23345 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23346 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23347 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23348 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23349 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23350 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23351 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23352 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23354 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23355 field is still 0xE. Many of the Thumb variants can be executed
23356 conditionally, so this is checked separately. */
23357 #define TUE(mnem, op, top, nops, ops, ae, te) \
23358 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23359 THUMB_VARIANT, do_##ae, do_##te, 0 }
23361 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23362 Used by mnemonics that have very minimal differences in the encoding for
23363 ARM and Thumb variants and can be handled in a common function. */
23364 #define TUEc(mnem, op, top, nops, ops, en) \
23365 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23366 THUMB_VARIANT, do_##en, do_##en, 0 }
23368 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23369 condition code field. */
23370 #define TUF(mnem, op, top, nops, ops, ae, te) \
23371 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23372 THUMB_VARIANT, do_##ae, do_##te, 0 }
23374 /* ARM-only variants of all the above. */
23375 #define CE(mnem, op, nops, ops, ae) \
23376 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23378 #define C3(mnem, op, nops, ops, ae) \
23379 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23381 /* Thumb-only variants of TCE and TUE. */
23382 #define ToC(mnem, top, nops, ops, te) \
23383 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23386 #define ToU(mnem, top, nops, ops, te) \
23387 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23390 /* T_MNEM_xyz enumerator variants of ToC. */
23391 #define toC(mnem, top, nops, ops, te) \
23392 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23395 /* T_MNEM_xyz enumerator variants of ToU. */
23396 #define toU(mnem, top, nops, ops, te) \
23397 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23400 /* Legacy mnemonics that always have conditional infix after the third
23402 #define CL(mnem, op, nops, ops, ae) \
23403 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23404 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23406 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23407 #define cCE(mnem, op, nops, ops, ae) \
23408 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23410 /* mov instructions that are shared between coprocessor and MVE. */
23411 #define mcCE(mnem, op, nops, ops, ae) \
23412 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23414 /* Legacy coprocessor instructions where conditional infix and conditional
23415 suffix are ambiguous. For consistency this includes all FPA instructions,
23416 not just the potentially ambiguous ones. */
23417 #define cCL(mnem, op, nops, ops, ae) \
23418 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23419 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23421 /* Coprocessor, takes either a suffix or a position-3 infix
23422 (for an FPA corner case). */
23423 #define C3E(mnem, op, nops, ops, ae) \
23424 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23425 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23427 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23428 { m1 #m2 m3, OPS##nops ops, \
23429 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23430 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23432 #define CM(m1, m2, op, nops, ops, ae) \
23433 xCM_ (m1, , m2, op, nops, ops, ae), \
23434 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23435 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23436 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23437 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23438 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23439 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23440 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23441 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23442 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23443 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23444 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23445 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23446 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23447 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23448 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23449 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23450 xCM_ (m1, le, m2, op, nops, ops, ae), \
23451 xCM_ (m1, al, m2, op, nops, ops, ae)
23453 #define UE(mnem, op, nops, ops, ae) \
23454 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23456 #define UF(mnem, op, nops, ops, ae) \
23457 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23459 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23460 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23461 use the same encoding function for each. */
23462 #define NUF(mnem, op, nops, ops, enc) \
23463 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23464 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23466 /* Neon data processing, version which indirects through neon_enc_tab for
23467 the various overloaded versions of opcodes. */
23468 #define nUF(mnem, op, nops, ops, enc) \
23469 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23470 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23472 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23474 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23475 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23476 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23478 #define NCE(mnem, op, nops, ops, enc) \
23479 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23481 #define NCEF(mnem, op, nops, ops, enc) \
23482 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23484 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23485 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23486 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23487 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23489 #define nCE(mnem, op, nops, ops, enc) \
23490 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23492 #define nCEF(mnem, op, nops, ops, enc) \
23493 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23496 #define mCEF(mnem, op, nops, ops, enc) \
23497 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23498 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23501 /* nCEF but for MVE predicated instructions. */
23502 #define mnCEF(mnem, op, nops, ops, enc) \
23503 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23505 /* nCE but for MVE predicated instructions. */
23506 #define mnCE(mnem, op, nops, ops, enc) \
23507 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23509 /* NUF but for potentially MVE predicated instructions. */
23510 #define MNUF(mnem, op, nops, ops, enc) \
23511 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23512 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23514 /* nUF but for potentially MVE predicated instructions. */
23515 #define mnUF(mnem, op, nops, ops, enc) \
23516 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23517 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23519 /* ToC but for potentially MVE predicated instructions. */
23520 #define mToC(mnem, top, nops, ops, te) \
23521 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23524 /* NCE but for MVE predicated instructions. */
23525 #define MNCE(mnem, op, nops, ops, enc) \
23526 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23528 /* NCEF but for MVE predicated instructions. */
23529 #define MNCEF(mnem, op, nops, ops, enc) \
23530 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23533 static const struct asm_opcode insns
[] =
23535 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23536 #define THUMB_VARIANT & arm_ext_v4t
23537 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23538 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23539 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23540 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23541 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23542 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23543 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23544 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23545 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23546 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23547 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23548 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23549 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23550 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23551 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23552 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23554 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23555 for setting PSR flag bits. They are obsolete in V6 and do not
23556 have Thumb equivalents. */
23557 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23558 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23559 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23560 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23561 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23562 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23563 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23564 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23565 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23567 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23568 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23569 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23570 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23572 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23573 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23574 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23576 OP_ADDRGLDR
),ldst
, t_ldst
),
23577 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23579 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23580 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23581 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23582 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23583 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23584 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23586 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23587 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23590 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23591 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23592 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23593 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23595 /* Thumb-compatibility pseudo ops. */
23596 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23597 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23598 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23599 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23600 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23601 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23602 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23603 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23604 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23605 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23606 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23607 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23609 /* These may simplify to neg. */
23610 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23611 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23613 #undef THUMB_VARIANT
23614 #define THUMB_VARIANT & arm_ext_os
23616 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23617 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23619 #undef THUMB_VARIANT
23620 #define THUMB_VARIANT & arm_ext_v6
23622 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23624 /* V1 instructions with no Thumb analogue prior to V6T2. */
23625 #undef THUMB_VARIANT
23626 #define THUMB_VARIANT & arm_ext_v6t2
23628 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23629 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23630 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23632 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23633 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23634 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23635 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23637 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23638 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23640 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23641 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23643 /* V1 instructions with no Thumb analogue at all. */
23644 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23645 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23647 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23648 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23649 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23650 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23651 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23652 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23653 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23654 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23657 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23658 #undef THUMB_VARIANT
23659 #define THUMB_VARIANT & arm_ext_v4t
23661 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23662 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23664 #undef THUMB_VARIANT
23665 #define THUMB_VARIANT & arm_ext_v6t2
23667 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23668 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23670 /* Generic coprocessor instructions. */
23671 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23672 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23673 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23674 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23675 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23676 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23677 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23680 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23682 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23683 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23686 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23687 #undef THUMB_VARIANT
23688 #define THUMB_VARIANT & arm_ext_msr
23690 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23691 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23694 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23695 #undef THUMB_VARIANT
23696 #define THUMB_VARIANT & arm_ext_v6t2
23698 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23699 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23700 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23701 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23702 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23703 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23704 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23705 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23708 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23709 #undef THUMB_VARIANT
23710 #define THUMB_VARIANT & arm_ext_v4t
23712 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23713 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23714 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23715 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23716 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23717 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23720 #define ARM_VARIANT & arm_ext_v4t_5
23722 /* ARM Architecture 4T. */
23723 /* Note: bx (and blx) are required on V5, even if the processor does
23724 not support Thumb. */
23725 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23728 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23729 #undef THUMB_VARIANT
23730 #define THUMB_VARIANT & arm_ext_v5t
23732 /* Note: blx has 2 variants; the .value coded here is for
23733 BLX(2). Only this variant has conditional execution. */
23734 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23735 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23737 #undef THUMB_VARIANT
23738 #define THUMB_VARIANT & arm_ext_v6t2
23740 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23741 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23742 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23743 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23744 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23745 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23746 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23747 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23750 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23751 #undef THUMB_VARIANT
23752 #define THUMB_VARIANT & arm_ext_v5exp
23754 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23755 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23756 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23757 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23759 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23760 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23762 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23763 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23764 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23765 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23767 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23768 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23769 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23770 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23772 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23773 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23775 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23776 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23777 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23778 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23781 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23782 #undef THUMB_VARIANT
23783 #define THUMB_VARIANT & arm_ext_v6t2
23785 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23786 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23788 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23789 ADDRGLDRS
), ldrd
, t_ldstd
),
23791 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23792 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23795 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23797 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23800 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23801 #undef THUMB_VARIANT
23802 #define THUMB_VARIANT & arm_ext_v6
23804 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23805 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23806 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23807 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23808 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23809 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23810 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23811 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23812 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23813 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23815 #undef THUMB_VARIANT
23816 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23818 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23819 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23821 #undef THUMB_VARIANT
23822 #define THUMB_VARIANT & arm_ext_v6t2
23824 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23825 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23827 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23828 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23830 /* ARM V6 not included in V7M. */
23831 #undef THUMB_VARIANT
23832 #define THUMB_VARIANT & arm_ext_v6_notm
23833 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23834 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23835 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23836 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23837 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23838 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23839 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23840 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23841 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23842 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23843 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23844 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23845 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23846 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23847 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23848 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23849 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23850 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23851 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23853 /* ARM V6 not included in V7M (eg. integer SIMD). */
23854 #undef THUMB_VARIANT
23855 #define THUMB_VARIANT & arm_ext_v6_dsp
23856 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23857 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23858 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23859 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23860 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23861 /* Old name for QASX. */
23862 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23863 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23864 /* Old name for QSAX. */
23865 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23866 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23867 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23868 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23869 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23870 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23871 /* Old name for SASX. */
23872 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23873 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23874 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23875 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23876 /* Old name for SHASX. */
23877 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23878 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23879 /* Old name for SHSAX. */
23880 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23881 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23882 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23883 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23884 /* Old name for SSAX. */
23885 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23886 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23887 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23888 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23889 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23890 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23891 /* Old name for UASX. */
23892 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23893 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23894 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23895 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23896 /* Old name for UHASX. */
23897 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23898 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23899 /* Old name for UHSAX. */
23900 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23901 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23902 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23903 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23904 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23905 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23906 /* Old name for UQASX. */
23907 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23908 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23909 /* Old name for UQSAX. */
23910 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23911 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23912 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23913 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23914 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23915 /* Old name for USAX. */
23916 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23917 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23918 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23919 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23920 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23921 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23922 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23923 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23924 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23925 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23926 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23927 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23928 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23929 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23930 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23931 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23932 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23933 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23934 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23935 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23936 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23937 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23938 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23939 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23940 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23941 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23942 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23943 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23944 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23945 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23946 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23947 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23948 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23949 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23952 #define ARM_VARIANT & arm_ext_v6k_v6t2
23953 #undef THUMB_VARIANT
23954 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23956 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23957 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23958 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23959 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23961 #undef THUMB_VARIANT
23962 #define THUMB_VARIANT & arm_ext_v6_notm
23963 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23965 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23966 RRnpcb
), strexd
, t_strexd
),
23968 #undef THUMB_VARIANT
23969 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23970 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23972 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23974 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23976 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23978 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23981 #define ARM_VARIANT & arm_ext_sec
23982 #undef THUMB_VARIANT
23983 #define THUMB_VARIANT & arm_ext_sec
23985 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23988 #define ARM_VARIANT & arm_ext_virt
23989 #undef THUMB_VARIANT
23990 #define THUMB_VARIANT & arm_ext_virt
23992 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23993 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23996 #define ARM_VARIANT & arm_ext_pan
23997 #undef THUMB_VARIANT
23998 #define THUMB_VARIANT & arm_ext_pan
24000 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24003 #define ARM_VARIANT & arm_ext_v6t2
24004 #undef THUMB_VARIANT
24005 #define THUMB_VARIANT & arm_ext_v6t2
24007 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24008 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24009 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24010 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24012 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24013 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24015 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24016 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24017 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24018 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24021 #define ARM_VARIANT & arm_ext_v3
24022 #undef THUMB_VARIANT
24023 #define THUMB_VARIANT & arm_ext_v6t2
24025 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24026 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24027 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24030 #define ARM_VARIANT & arm_ext_v6t2
24031 #undef THUMB_VARIANT
24032 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24033 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24034 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24036 /* Thumb-only instructions. */
24038 #define ARM_VARIANT NULL
24039 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24040 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24042 /* ARM does not really have an IT instruction, so always allow it.
24043 The opcode is copied from Thumb in order to allow warnings in
24044 -mimplicit-it=[never | arm] modes. */
24046 #define ARM_VARIANT & arm_ext_v1
24047 #undef THUMB_VARIANT
24048 #define THUMB_VARIANT & arm_ext_v6t2
24050 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24051 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24052 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24053 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24054 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24055 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24056 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24057 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24058 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24059 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24060 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24061 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24062 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24063 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24064 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24065 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24066 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24067 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24069 /* Thumb2 only instructions. */
24071 #define ARM_VARIANT NULL
24073 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24074 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24075 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24076 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24077 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24078 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24080 /* Hardware division instructions. */
24082 #define ARM_VARIANT & arm_ext_adiv
24083 #undef THUMB_VARIANT
24084 #define THUMB_VARIANT & arm_ext_div
24086 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24087 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24089 /* ARM V6M/V7 instructions. */
24091 #define ARM_VARIANT & arm_ext_barrier
24092 #undef THUMB_VARIANT
24093 #define THUMB_VARIANT & arm_ext_barrier
24095 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24096 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24097 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24099 /* ARM V7 instructions. */
24101 #define ARM_VARIANT & arm_ext_v7
24102 #undef THUMB_VARIANT
24103 #define THUMB_VARIANT & arm_ext_v7
24105 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24106 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24109 #define ARM_VARIANT & arm_ext_mp
24110 #undef THUMB_VARIANT
24111 #define THUMB_VARIANT & arm_ext_mp
24113 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24115 /* AArchv8 instructions. */
24117 #define ARM_VARIANT & arm_ext_v8
24119 /* Instructions shared between armv8-a and armv8-m. */
24120 #undef THUMB_VARIANT
24121 #define THUMB_VARIANT & arm_ext_atomics
24123 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24124 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24125 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24126 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24127 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24128 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24129 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24130 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24131 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24132 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24134 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24136 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24138 #undef THUMB_VARIANT
24139 #define THUMB_VARIANT & arm_ext_v8
24141 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24142 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24144 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24147 /* Defined in V8 but is in undefined encoding space for earlier
24148 architectures. However earlier architectures are required to treat
24149 this instuction as a semihosting trap as well. Hence while not explicitly
24150 defined as such, it is in fact correct to define the instruction for all
24152 #undef THUMB_VARIANT
24153 #define THUMB_VARIANT & arm_ext_v1
24155 #define ARM_VARIANT & arm_ext_v1
24156 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24158 /* ARMv8 T32 only. */
24160 #define ARM_VARIANT NULL
24161 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24162 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24163 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24165 /* FP for ARMv8. */
24167 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24168 #undef THUMB_VARIANT
24169 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24171 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24172 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24173 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24174 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24175 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24176 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24177 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24178 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24179 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24180 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24181 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24183 /* Crypto v1 extensions. */
24185 #define ARM_VARIANT & fpu_crypto_ext_armv8
24186 #undef THUMB_VARIANT
24187 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24189 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24190 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24191 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24192 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24193 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24194 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24195 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24196 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24197 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24198 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24199 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24200 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24201 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24202 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24205 #define ARM_VARIANT & crc_ext_armv8
24206 #undef THUMB_VARIANT
24207 #define THUMB_VARIANT & crc_ext_armv8
24208 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24209 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24210 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24211 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24212 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24213 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24215 /* ARMv8.2 RAS extension. */
24217 #define ARM_VARIANT & arm_ext_ras
24218 #undef THUMB_VARIANT
24219 #define THUMB_VARIANT & arm_ext_ras
24220 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24223 #define ARM_VARIANT & arm_ext_v8_3
24224 #undef THUMB_VARIANT
24225 #define THUMB_VARIANT & arm_ext_v8_3
24226 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24229 #define ARM_VARIANT & fpu_neon_ext_dotprod
24230 #undef THUMB_VARIANT
24231 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24232 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24233 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24236 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24237 #undef THUMB_VARIANT
24238 #define THUMB_VARIANT NULL
24240 cCE("wfs", e200110
, 1, (RR
), rd
),
24241 cCE("rfs", e300110
, 1, (RR
), rd
),
24242 cCE("wfc", e400110
, 1, (RR
), rd
),
24243 cCE("rfc", e500110
, 1, (RR
), rd
),
24245 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24246 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24247 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24248 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24250 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24251 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24252 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24253 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24255 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24256 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24257 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24258 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24259 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24260 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24261 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24262 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24263 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24264 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24265 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24266 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24268 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24269 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24270 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24271 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24272 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24273 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24274 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24275 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24276 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24277 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24278 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24279 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24281 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24282 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24283 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24284 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24285 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24286 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24287 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24288 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24289 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24290 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24291 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24292 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24294 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24295 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24296 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24297 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24298 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24299 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24300 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24301 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24302 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24303 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24304 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24305 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24307 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24308 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24309 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24310 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24311 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24312 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24313 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24314 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24315 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24316 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24317 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24318 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24320 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24321 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24322 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24323 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24324 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24325 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24326 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24327 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24328 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24329 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24330 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24331 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24333 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24334 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24335 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24336 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24337 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24338 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24339 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24340 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24341 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24342 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24343 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24344 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24346 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24347 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24348 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24349 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24350 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24351 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24352 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24353 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24354 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24355 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24356 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24357 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24359 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24360 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24361 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24362 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24363 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24364 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24365 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24366 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24367 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24368 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24369 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24370 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24372 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24373 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24374 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24375 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24376 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24377 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24378 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24379 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24380 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24381 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24382 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24383 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24385 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24386 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24387 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24388 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24389 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24390 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24391 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24392 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24393 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24394 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24395 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24396 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24398 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24399 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24400 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24401 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24402 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24403 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24404 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24405 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24406 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24407 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24408 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24409 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24411 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24412 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24413 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24414 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24415 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24416 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24417 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24418 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24419 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24420 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24421 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24422 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24424 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24425 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24426 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24427 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24428 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24429 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24430 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24431 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24432 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24433 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24434 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24435 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24437 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24438 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24439 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24440 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24441 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24442 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24443 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24444 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24445 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24446 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24447 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24448 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24450 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24451 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24452 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24453 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24454 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24455 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24456 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24457 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24458 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24459 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24460 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24461 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24463 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24464 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24465 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24466 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24467 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24468 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24469 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24470 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24471 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24472 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24473 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24474 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24476 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24477 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24478 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24479 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24480 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24481 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24482 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24483 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24484 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24485 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24486 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24487 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24489 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24490 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24491 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24492 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24493 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24494 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24495 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24496 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24497 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24498 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24499 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24500 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24502 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24503 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24504 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24505 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24506 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24507 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24508 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24509 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24510 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24511 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24512 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24513 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24515 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24516 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24517 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24518 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24519 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24520 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24521 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24522 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24523 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24524 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24525 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24526 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24528 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24529 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24530 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24531 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24532 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24533 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24534 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24535 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24536 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24537 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24538 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24539 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24541 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24542 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24543 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24544 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24545 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24546 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24547 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24548 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24549 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24550 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24551 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24552 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24554 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24555 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24556 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24557 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24558 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24559 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24560 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24561 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24562 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24563 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24564 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24565 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24567 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24568 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24569 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24570 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24571 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24572 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24573 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24574 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24575 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24576 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24577 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24578 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24580 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24581 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24582 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24583 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24584 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24585 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24586 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24587 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24588 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24589 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24590 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24591 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24593 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24594 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24595 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24596 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24597 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24598 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24599 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24600 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24601 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24602 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24603 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24604 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24606 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24607 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24608 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24609 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24610 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24611 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24612 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24613 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24614 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24615 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24616 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24617 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24619 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24620 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24621 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24622 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24623 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24624 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24625 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24626 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24627 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24628 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24629 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24630 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24632 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24633 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24634 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24635 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24637 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24638 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24639 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24640 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24641 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24642 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24643 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24644 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24645 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24646 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24647 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24648 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24650 /* The implementation of the FIX instruction is broken on some
24651 assemblers, in that it accepts a precision specifier as well as a
24652 rounding specifier, despite the fact that this is meaningless.
24653 To be more compatible, we accept it as well, though of course it
24654 does not set any bits. */
24655 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24656 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24657 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24658 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24659 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24660 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24661 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24662 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24663 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24664 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24665 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24666 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24667 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24669 /* Instructions that were new with the real FPA, call them V2. */
24671 #define ARM_VARIANT & fpu_fpa_ext_v2
24673 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24674 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24675 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24676 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24677 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24678 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24681 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24682 #undef THUMB_VARIANT
24683 #define THUMB_VARIANT & arm_ext_v6t2
24684 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24685 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24686 #undef THUMB_VARIANT
24688 /* Moves and type conversions. */
24689 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24690 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24691 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24692 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24693 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24694 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24695 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24696 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24697 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24699 /* Memory operations. */
24700 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24701 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24702 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24703 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24704 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24705 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24706 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24707 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24708 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24709 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24710 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24711 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24712 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24713 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24714 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24715 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24716 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24717 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24719 /* Monadic operations. */
24720 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24721 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24722 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24724 /* Dyadic operations. */
24725 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24726 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24727 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24728 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24729 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24730 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24731 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24732 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24733 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24736 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24737 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24738 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24739 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24741 /* Double precision load/store are still present on single precision
24742 implementations. */
24743 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24744 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24745 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24746 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24747 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24748 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24749 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24750 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24751 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24752 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24755 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24757 /* Moves and type conversions. */
24758 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24759 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24760 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24761 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24762 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24763 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24764 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24765 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24766 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24767 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24768 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24769 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24771 /* Monadic operations. */
24772 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24773 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24774 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24776 /* Dyadic operations. */
24777 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24778 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24779 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24780 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24781 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24782 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24783 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24784 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24785 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24788 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24789 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24790 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24791 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24793 /* Instructions which may belong to either the Neon or VFP instruction sets.
24794 Individual encoder functions perform additional architecture checks. */
24796 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24797 #undef THUMB_VARIANT
24798 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24800 /* These mnemonics are unique to VFP. */
24801 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24802 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24803 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24804 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24805 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24806 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24807 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24808 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24810 /* Mnemonics shared by Neon and VFP. */
24811 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24813 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24814 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24815 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24816 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24817 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24818 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24820 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24821 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24822 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24823 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24826 /* NOTE: All VMOV encoding is special-cased! */
24827 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24829 #undef THUMB_VARIANT
24830 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24831 by different feature bits. Since we are setting the Thumb guard, we can
24832 require Thumb-1 which makes it a nop guard and set the right feature bit in
24833 do_vldr_vstr (). */
24834 #define THUMB_VARIANT & arm_ext_v4t
24835 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24836 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24839 #define ARM_VARIANT & arm_ext_fp16
24840 #undef THUMB_VARIANT
24841 #define THUMB_VARIANT & arm_ext_fp16
24842 /* New instructions added from v8.2, allowing the extraction and insertion of
24843 the upper 16 bits of a 32-bit vector register. */
24844 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24845 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24847 /* New backported fma/fms instructions optional in v8.2. */
24848 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24849 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24851 #undef THUMB_VARIANT
24852 #define THUMB_VARIANT & fpu_neon_ext_v1
24854 #define ARM_VARIANT & fpu_neon_ext_v1
24856 /* Data processing with three registers of the same length. */
24857 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24858 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24859 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24860 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24861 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24862 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24863 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24864 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24865 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24866 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24867 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24868 /* If not immediate, fall back to neon_dyadic_i64_su.
24869 shl should accept I8 I16 I32 I64,
24870 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24871 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24872 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24873 /* Logic ops, types optional & ignored. */
24874 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24875 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24876 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24877 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24878 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24879 /* Bitfield ops, untyped. */
24880 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24881 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24882 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24883 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24884 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24885 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24886 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24887 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24888 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24889 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24890 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24891 back to neon_dyadic_if_su. */
24892 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24893 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24894 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24895 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24896 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24897 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24898 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24899 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24900 /* Comparison. Type I8 I16 I32 F32. */
24901 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24902 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24903 /* As above, D registers only. */
24904 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24905 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24906 /* Int and float variants, signedness unimportant. */
24907 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24908 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24909 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24910 /* Add/sub take types I8 I16 I32 I64 F32. */
24911 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24912 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24913 /* vtst takes sizes 8, 16, 32. */
24914 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24915 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24916 /* VMUL takes I8 I16 I32 F32 P8. */
24917 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24918 /* VQD{R}MULH takes S16 S32. */
24919 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24920 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24921 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24922 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24923 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24924 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24925 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24926 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24927 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24928 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24929 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24930 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24931 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24932 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24933 /* ARM v8.1 extension. */
24934 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24935 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24936 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24938 /* Two address, int/float. Types S8 S16 S32 F32. */
24939 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24940 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24942 /* Data processing with two registers and a shift amount. */
24943 /* Right shifts, and variants with rounding.
24944 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24945 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24946 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24947 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24948 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24949 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24950 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24951 /* Shift and insert. Sizes accepted 8 16 32 64. */
24952 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24953 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24954 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24955 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24956 /* Right shift immediate, saturating & narrowing, with rounding variants.
24957 Types accepted S16 S32 S64 U16 U32 U64. */
24958 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24959 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24960 /* As above, unsigned. Types accepted S16 S32 S64. */
24961 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24962 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24963 /* Right shift narrowing. Types accepted I16 I32 I64. */
24964 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24965 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24966 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24967 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24968 /* CVT with optional immediate for fixed-point variant. */
24969 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24971 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24973 /* Data processing, three registers of different lengths. */
24974 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24975 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24976 /* If not scalar, fall back to neon_dyadic_long.
24977 Vector types as above, scalar types S16 S32 U16 U32. */
24978 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24979 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24980 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24981 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24982 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24983 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24984 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24985 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24986 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24987 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24988 /* Saturating doubling multiplies. Types S16 S32. */
24989 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24990 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24991 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24992 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24993 S16 S32 U16 U32. */
24994 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24996 /* Extract. Size 8. */
24997 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24998 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25000 /* Two registers, miscellaneous. */
25001 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25002 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25003 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25004 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25005 /* Vector replicate. Sizes 8 16 32. */
25006 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25007 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25008 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25009 /* VMOVN. Types I16 I32 I64. */
25010 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25011 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25012 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25013 /* VQMOVUN. Types S16 S32 S64. */
25014 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25015 /* VZIP / VUZP. Sizes 8 16 32. */
25016 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25017 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25018 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25019 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25020 /* VQABS / VQNEG. Types S8 S16 S32. */
25021 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25022 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25023 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25024 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25025 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25026 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25027 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25028 /* Reciprocal estimates. Types U32 F16 F32. */
25029 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25030 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25031 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25032 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25033 /* VCLS. Types S8 S16 S32. */
25034 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25035 /* VCLZ. Types I8 I16 I32. */
25036 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25037 /* VCNT. Size 8. */
25038 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25039 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25040 /* Two address, untyped. */
25041 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25042 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25043 /* VTRN. Sizes 8 16 32. */
25044 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25045 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25047 /* Table lookup. Size 8. */
25048 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25049 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25051 #undef THUMB_VARIANT
25052 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25054 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25056 /* Neon element/structure load/store. */
25057 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25058 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25059 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25060 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25061 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25062 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25063 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25064 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25066 #undef THUMB_VARIANT
25067 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25069 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25070 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25071 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25072 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25073 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25074 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25075 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25076 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25077 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25078 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25080 #undef THUMB_VARIANT
25081 #define THUMB_VARIANT & fpu_vfp_ext_v3
25083 #define ARM_VARIANT & fpu_vfp_ext_v3
25085 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25086 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25087 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25088 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25089 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25090 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25091 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25092 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25093 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25096 #define ARM_VARIANT & fpu_vfp_ext_fma
25097 #undef THUMB_VARIANT
25098 #define THUMB_VARIANT & fpu_vfp_ext_fma
25099 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
25100 VFP FMA variant; NEON and VFP FMA always includes the NEON
25101 FMA instructions. */
25102 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25103 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25105 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25106 the v form should always be used. */
25107 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25108 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25109 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25110 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25111 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25112 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25114 #undef THUMB_VARIANT
25116 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25118 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25119 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25120 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25121 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25122 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25123 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25124 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25125 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25128 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25130 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25131 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25132 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25133 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25134 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25135 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25136 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25137 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25138 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25139 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25140 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25141 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25142 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25143 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25144 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25145 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25146 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25147 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25148 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25149 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25150 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25151 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25152 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25153 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25154 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25155 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25156 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25157 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25158 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25159 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25160 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25161 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25162 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25163 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25164 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25165 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25166 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25167 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25168 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25169 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25170 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25171 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25172 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25173 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25174 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25175 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25176 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25177 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25178 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25179 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25180 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25181 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25182 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25183 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25184 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25185 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25186 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25187 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25188 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25189 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25190 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25191 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25192 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25193 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25194 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25195 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25196 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25197 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25198 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25199 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25200 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25201 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25202 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25203 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25204 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25205 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25206 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25207 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25208 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25209 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25210 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25211 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25212 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25213 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25214 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25215 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25216 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25217 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25218 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25219 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25220 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25221 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25222 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25223 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25224 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25225 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25226 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25227 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25228 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25229 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25230 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25231 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25232 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25233 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25234 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25235 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25236 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25237 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25238 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25239 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25240 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25241 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25242 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25243 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25244 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25245 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25246 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25247 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25248 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25249 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25250 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25251 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25252 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25253 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25254 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25255 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25256 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25257 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25258 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25259 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25260 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25261 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25262 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25263 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25264 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25265 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25266 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25267 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25268 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25269 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25270 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25271 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25272 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25273 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25274 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25275 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25276 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25277 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25278 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25279 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25280 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25281 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25282 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25283 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25284 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25285 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25286 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25287 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25288 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25289 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25290 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25291 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25294 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25296 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25297 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25298 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25299 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25300 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25301 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25302 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25303 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25304 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25305 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25306 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25307 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25308 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25309 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25310 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25311 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25312 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25313 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25314 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25315 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25316 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25317 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25318 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25319 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25320 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25321 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25322 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25323 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25324 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25325 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25326 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25327 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25328 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25329 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25330 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25331 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25332 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25333 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25334 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25335 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25336 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25337 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25338 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25339 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25340 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25341 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25342 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25343 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25344 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25345 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25346 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25347 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25348 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25349 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25350 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25351 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25352 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25355 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25357 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25358 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25359 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25360 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25361 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25362 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25363 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25364 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25365 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25366 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25367 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25368 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25369 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25370 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25371 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25372 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25373 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25374 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25375 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25376 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25377 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25378 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25379 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25380 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25381 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25382 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25383 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25384 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25385 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25386 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25387 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25388 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25389 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25390 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25391 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25392 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25393 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25394 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25395 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25396 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25397 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25398 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25399 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25400 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25401 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25402 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25403 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25404 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25405 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25406 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25407 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25408 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25409 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25410 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25411 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25412 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25413 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25414 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25415 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25416 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25417 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25418 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25419 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25420 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25421 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25422 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25423 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25424 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25425 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25426 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25427 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25428 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25429 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25430 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25431 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25432 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25434 /* ARMv8.5-A instructions. */
25436 #define ARM_VARIANT & arm_ext_sb
25437 #undef THUMB_VARIANT
25438 #define THUMB_VARIANT & arm_ext_sb
25439 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25442 #define ARM_VARIANT & arm_ext_predres
25443 #undef THUMB_VARIANT
25444 #define THUMB_VARIANT & arm_ext_predres
25445 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25446 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25447 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25449 /* ARMv8-M instructions. */
25451 #define ARM_VARIANT NULL
25452 #undef THUMB_VARIANT
25453 #define THUMB_VARIANT & arm_ext_v8m
25454 ToU("sg", e97fe97f
, 0, (), noargs
),
25455 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25456 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25457 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25458 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25459 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25460 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25462 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25463 instructions behave as nop if no VFP is present. */
25464 #undef THUMB_VARIANT
25465 #define THUMB_VARIANT & arm_ext_v8m_main
25466 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25467 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25469 /* Armv8.1-M Mainline instructions. */
25470 #undef THUMB_VARIANT
25471 #define THUMB_VARIANT & arm_ext_v8_1m_main
25472 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25473 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25474 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25475 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25476 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25477 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25478 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25479 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25480 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25482 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25483 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25484 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25485 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25486 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25488 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25489 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25490 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25492 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25493 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25495 #undef THUMB_VARIANT
25496 #define THUMB_VARIANT & mve_ext
25497 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25498 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25499 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25500 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25501 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25502 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25503 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25504 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25505 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25506 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25507 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25508 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25509 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25510 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25511 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25513 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25514 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25515 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25516 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25517 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25518 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25519 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25520 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25521 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25522 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25523 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25524 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25525 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25526 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25527 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25529 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25530 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25531 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25532 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25533 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25534 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25535 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25536 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25537 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25538 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25539 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25540 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25541 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25542 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25543 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25545 /* MVE and MVE FP only. */
25546 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25547 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
25548 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25549 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25550 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25551 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25552 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25553 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25554 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25555 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25556 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25557 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25558 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25559 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25560 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25561 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25562 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25563 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25565 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25566 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25567 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25568 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25569 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25570 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25571 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25572 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25573 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25574 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25575 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25576 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25577 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25578 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25579 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25580 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25581 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25582 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25583 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25584 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25586 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25587 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25588 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25589 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25590 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25591 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25592 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25593 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25594 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25595 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25596 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25597 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25598 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25599 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25600 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25601 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25602 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25604 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25605 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25606 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25607 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25608 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25609 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25610 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25611 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25612 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25613 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25614 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25615 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25616 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25617 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25618 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25619 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25620 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25621 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25622 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25623 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25625 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25626 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25627 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25628 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25629 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25631 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25632 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25633 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25634 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25635 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25636 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25637 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25638 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25639 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25640 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25641 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25642 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25643 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25644 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25645 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25646 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25647 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25649 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25650 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25651 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25652 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25653 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25654 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25655 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25656 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25657 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25658 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25659 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25660 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25662 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25663 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25664 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25666 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25667 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25668 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25669 toU("lctp", _lctp
, 0, (), t_loloop
),
25671 #undef THUMB_VARIANT
25672 #define THUMB_VARIANT & mve_fp_ext
25673 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25674 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25675 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25676 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25677 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25678 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25679 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25680 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25683 #define ARM_VARIANT & fpu_vfp_ext_v1
25684 #undef THUMB_VARIANT
25685 #define THUMB_VARIANT & arm_ext_v6t2
25686 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25687 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25689 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25692 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25694 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25695 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25696 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25697 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25699 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25700 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25701 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25703 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25704 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25706 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25707 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25709 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25710 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25713 #define ARM_VARIANT & fpu_vfp_ext_v2
25715 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25716 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25717 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25718 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25721 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25722 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25723 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25724 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25725 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25726 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25727 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25730 #define ARM_VARIANT & fpu_neon_ext_v1
25731 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25732 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25733 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25734 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25735 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25736 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25737 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25738 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25739 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25740 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25741 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25742 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25743 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25744 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25745 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25746 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25747 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25748 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25749 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25750 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25751 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25752 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25753 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25754 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25755 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25756 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25757 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25758 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25759 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25760 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25761 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25762 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25763 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25764 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25765 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25766 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25767 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25770 #define ARM_VARIANT & arm_ext_v8_3
25771 #undef THUMB_VARIANT
25772 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25773 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25774 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25777 #undef THUMB_VARIANT
25809 /* MD interface: bits in the object file. */
25811 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25812 for use in the a.out file, and stores them in the array pointed to by buf.
25813 This knows about the endian-ness of the target machine and does
25814 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25815 2 (short) and 4 (long) Floating numbers are put out as a series of
25816 LITTLENUMS (shorts, here at least). */
25819 md_number_to_chars (char * buf
, valueT val
, int n
)
25821 if (target_big_endian
)
25822 number_to_chars_bigendian (buf
, val
, n
);
25824 number_to_chars_littleendian (buf
, val
, n
);
25828 md_chars_to_number (char * buf
, int n
)
25831 unsigned char * where
= (unsigned char *) buf
;
25833 if (target_big_endian
)
25838 result
|= (*where
++ & 255);
25846 result
|= (where
[n
] & 255);
25853 /* MD interface: Sections. */
25855 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25856 that an rs_machine_dependent frag may reach. */
25859 arm_frag_max_var (fragS
*fragp
)
25861 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25862 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25864 Note that we generate relaxable instructions even for cases that don't
25865 really need it, like an immediate that's a trivial constant. So we're
25866 overestimating the instruction size for some of those cases. Rather
25867 than putting more intelligence here, it would probably be better to
25868 avoid generating a relaxation frag in the first place when it can be
25869 determined up front that a short instruction will suffice. */
25871 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25875 /* Estimate the size of a frag before relaxing. Assume everything fits in
25879 md_estimate_size_before_relax (fragS
* fragp
,
25880 segT segtype ATTRIBUTE_UNUSED
)
25886 /* Convert a machine dependent frag. */
25889 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25891 unsigned long insn
;
25892 unsigned long old_op
;
25900 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25902 old_op
= bfd_get_16(abfd
, buf
);
25903 if (fragp
->fr_symbol
)
25905 exp
.X_op
= O_symbol
;
25906 exp
.X_add_symbol
= fragp
->fr_symbol
;
25910 exp
.X_op
= O_constant
;
25912 exp
.X_add_number
= fragp
->fr_offset
;
25913 opcode
= fragp
->fr_subtype
;
25916 case T_MNEM_ldr_pc
:
25917 case T_MNEM_ldr_pc2
:
25918 case T_MNEM_ldr_sp
:
25919 case T_MNEM_str_sp
:
25926 if (fragp
->fr_var
== 4)
25928 insn
= THUMB_OP32 (opcode
);
25929 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25931 insn
|= (old_op
& 0x700) << 4;
25935 insn
|= (old_op
& 7) << 12;
25936 insn
|= (old_op
& 0x38) << 13;
25938 insn
|= 0x00000c00;
25939 put_thumb32_insn (buf
, insn
);
25940 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25944 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25946 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25949 if (fragp
->fr_var
== 4)
25951 insn
= THUMB_OP32 (opcode
);
25952 insn
|= (old_op
& 0xf0) << 4;
25953 put_thumb32_insn (buf
, insn
);
25954 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25958 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25959 exp
.X_add_number
-= 4;
25967 if (fragp
->fr_var
== 4)
25969 int r0off
= (opcode
== T_MNEM_mov
25970 || opcode
== T_MNEM_movs
) ? 0 : 8;
25971 insn
= THUMB_OP32 (opcode
);
25972 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25973 insn
|= (old_op
& 0x700) << r0off
;
25974 put_thumb32_insn (buf
, insn
);
25975 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25979 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25984 if (fragp
->fr_var
== 4)
25986 insn
= THUMB_OP32(opcode
);
25987 put_thumb32_insn (buf
, insn
);
25988 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25991 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25995 if (fragp
->fr_var
== 4)
25997 insn
= THUMB_OP32(opcode
);
25998 insn
|= (old_op
& 0xf00) << 14;
25999 put_thumb32_insn (buf
, insn
);
26000 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26003 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26006 case T_MNEM_add_sp
:
26007 case T_MNEM_add_pc
:
26008 case T_MNEM_inc_sp
:
26009 case T_MNEM_dec_sp
:
26010 if (fragp
->fr_var
== 4)
26012 /* ??? Choose between add and addw. */
26013 insn
= THUMB_OP32 (opcode
);
26014 insn
|= (old_op
& 0xf0) << 4;
26015 put_thumb32_insn (buf
, insn
);
26016 if (opcode
== T_MNEM_add_pc
)
26017 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26019 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26022 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26030 if (fragp
->fr_var
== 4)
26032 insn
= THUMB_OP32 (opcode
);
26033 insn
|= (old_op
& 0xf0) << 4;
26034 insn
|= (old_op
& 0xf) << 16;
26035 put_thumb32_insn (buf
, insn
);
26036 if (insn
& (1 << 20))
26037 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26039 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26042 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26048 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26049 (enum bfd_reloc_code_real
) reloc_type
);
26050 fixp
->fx_file
= fragp
->fr_file
;
26051 fixp
->fx_line
= fragp
->fr_line
;
26052 fragp
->fr_fix
+= fragp
->fr_var
;
26054 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26055 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26056 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26057 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26060 /* Return the size of a relaxable immediate operand instruction.
26061 SHIFT and SIZE specify the form of the allowable immediate. */
26063 relax_immediate (fragS
*fragp
, int size
, int shift
)
26069 /* ??? Should be able to do better than this. */
26070 if (fragp
->fr_symbol
)
26073 low
= (1 << shift
) - 1;
26074 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26075 offset
= fragp
->fr_offset
;
26076 /* Force misaligned offsets to 32-bit variant. */
26079 if (offset
& ~mask
)
26084 /* Get the address of a symbol during relaxation. */
26086 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26092 sym
= fragp
->fr_symbol
;
26093 sym_frag
= symbol_get_frag (sym
);
26094 know (S_GET_SEGMENT (sym
) != absolute_section
26095 || sym_frag
== &zero_address_frag
);
26096 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26098 /* If frag has yet to be reached on this pass, assume it will
26099 move by STRETCH just as we did. If this is not so, it will
26100 be because some frag between grows, and that will force
26104 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26108 /* Adjust stretch for any alignment frag. Note that if have
26109 been expanding the earlier code, the symbol may be
26110 defined in what appears to be an earlier frag. FIXME:
26111 This doesn't handle the fr_subtype field, which specifies
26112 a maximum number of bytes to skip when doing an
26114 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26116 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26119 stretch
= - ((- stretch
)
26120 & ~ ((1 << (int) f
->fr_offset
) - 1));
26122 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26134 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26137 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26142 /* Assume worst case for symbols not known to be in the same section. */
26143 if (fragp
->fr_symbol
== NULL
26144 || !S_IS_DEFINED (fragp
->fr_symbol
)
26145 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26146 || S_IS_WEAK (fragp
->fr_symbol
))
26149 val
= relaxed_symbol_addr (fragp
, stretch
);
26150 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26151 addr
= (addr
+ 4) & ~3;
26152 /* Force misaligned targets to 32-bit variant. */
26156 if (val
< 0 || val
> 1020)
26161 /* Return the size of a relaxable add/sub immediate instruction. */
26163 relax_addsub (fragS
*fragp
, asection
*sec
)
26168 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26169 op
= bfd_get_16(sec
->owner
, buf
);
26170 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26171 return relax_immediate (fragp
, 8, 0);
26173 return relax_immediate (fragp
, 3, 0);
26176 /* Return TRUE iff the definition of symbol S could be pre-empted
26177 (overridden) at link or load time. */
26179 symbol_preemptible (symbolS
*s
)
26181 /* Weak symbols can always be pre-empted. */
26185 /* Non-global symbols cannot be pre-empted. */
26186 if (! S_IS_EXTERNAL (s
))
26190 /* In ELF, a global symbol can be marked protected, or private. In that
26191 case it can't be pre-empted (other definitions in the same link unit
26192 would violate the ODR). */
26193 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26197 /* Other global symbols might be pre-empted. */
26201 /* Return the size of a relaxable branch instruction. BITS is the
26202 size of the offset field in the narrow instruction. */
26205 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26211 /* Assume worst case for symbols not known to be in the same section. */
26212 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26213 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26214 || S_IS_WEAK (fragp
->fr_symbol
))
26218 /* A branch to a function in ARM state will require interworking. */
26219 if (S_IS_DEFINED (fragp
->fr_symbol
)
26220 && ARM_IS_FUNC (fragp
->fr_symbol
))
26224 if (symbol_preemptible (fragp
->fr_symbol
))
26227 val
= relaxed_symbol_addr (fragp
, stretch
);
26228 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26231 /* Offset is a signed value *2 */
26233 if (val
>= limit
|| val
< -limit
)
26239 /* Relax a machine dependent frag. This returns the amount by which
26240 the current size of the frag should change. */
26243 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26248 oldsize
= fragp
->fr_var
;
26249 switch (fragp
->fr_subtype
)
26251 case T_MNEM_ldr_pc2
:
26252 newsize
= relax_adr (fragp
, sec
, stretch
);
26254 case T_MNEM_ldr_pc
:
26255 case T_MNEM_ldr_sp
:
26256 case T_MNEM_str_sp
:
26257 newsize
= relax_immediate (fragp
, 8, 2);
26261 newsize
= relax_immediate (fragp
, 5, 2);
26265 newsize
= relax_immediate (fragp
, 5, 1);
26269 newsize
= relax_immediate (fragp
, 5, 0);
26272 newsize
= relax_adr (fragp
, sec
, stretch
);
26278 newsize
= relax_immediate (fragp
, 8, 0);
26281 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26284 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26286 case T_MNEM_add_sp
:
26287 case T_MNEM_add_pc
:
26288 newsize
= relax_immediate (fragp
, 8, 2);
26290 case T_MNEM_inc_sp
:
26291 case T_MNEM_dec_sp
:
26292 newsize
= relax_immediate (fragp
, 7, 2);
26298 newsize
= relax_addsub (fragp
, sec
);
26304 fragp
->fr_var
= newsize
;
26305 /* Freeze wide instructions that are at or before the same location as
26306 in the previous pass. This avoids infinite loops.
26307 Don't freeze them unconditionally because targets may be artificially
26308 misaligned by the expansion of preceding frags. */
26309 if (stretch
<= 0 && newsize
> 2)
26311 md_convert_frag (sec
->owner
, sec
, fragp
);
26315 return newsize
- oldsize
;
26318 /* Round up a section size to the appropriate boundary. */
26321 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26327 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26328 of an rs_align_code fragment. */
26331 arm_handle_align (fragS
* fragP
)
26333 static unsigned char const arm_noop
[2][2][4] =
26336 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26337 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26340 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26341 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26344 static unsigned char const thumb_noop
[2][2][2] =
26347 {0xc0, 0x46}, /* LE */
26348 {0x46, 0xc0}, /* BE */
26351 {0x00, 0xbf}, /* LE */
26352 {0xbf, 0x00} /* BE */
26355 static unsigned char const wide_thumb_noop
[2][4] =
26356 { /* Wide Thumb-2 */
26357 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26358 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26361 unsigned bytes
, fix
, noop_size
;
26363 const unsigned char * noop
;
26364 const unsigned char *narrow_noop
= NULL
;
26369 if (fragP
->fr_type
!= rs_align_code
)
26372 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26373 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26376 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26377 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26379 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26381 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26383 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26384 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26386 narrow_noop
= thumb_noop
[1][target_big_endian
];
26387 noop
= wide_thumb_noop
[target_big_endian
];
26390 noop
= thumb_noop
[0][target_big_endian
];
26398 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26399 ? selected_cpu
: arm_arch_none
,
26401 [target_big_endian
];
26408 fragP
->fr_var
= noop_size
;
26410 if (bytes
& (noop_size
- 1))
26412 fix
= bytes
& (noop_size
- 1);
26414 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26416 memset (p
, 0, fix
);
26423 if (bytes
& noop_size
)
26425 /* Insert a narrow noop. */
26426 memcpy (p
, narrow_noop
, noop_size
);
26428 bytes
-= noop_size
;
26432 /* Use wide noops for the remainder */
26436 while (bytes
>= noop_size
)
26438 memcpy (p
, noop
, noop_size
);
26440 bytes
-= noop_size
;
26444 fragP
->fr_fix
+= fix
;
26447 /* Called from md_do_align. Used to create an alignment
26448 frag in a code section. */
26451 arm_frag_align_code (int n
, int max
)
26455 /* We assume that there will never be a requirement
26456 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26457 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26462 _("alignments greater than %d bytes not supported in .text sections."),
26463 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26464 as_fatal ("%s", err_msg
);
26467 p
= frag_var (rs_align_code
,
26468 MAX_MEM_FOR_RS_ALIGN_CODE
,
26470 (relax_substateT
) max
,
26477 /* Perform target specific initialisation of a frag.
26478 Note - despite the name this initialisation is not done when the frag
26479 is created, but only when its type is assigned. A frag can be created
26480 and used a long time before its type is set, so beware of assuming that
26481 this initialisation is performed first. */
26485 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26487 /* Record whether this frag is in an ARM or a THUMB area. */
26488 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26491 #else /* OBJ_ELF is defined. */
26493 arm_init_frag (fragS
* fragP
, int max_chars
)
26495 bfd_boolean frag_thumb_mode
;
26497 /* If the current ARM vs THUMB mode has not already
26498 been recorded into this frag then do so now. */
26499 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26500 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26502 /* PR 21809: Do not set a mapping state for debug sections
26503 - it just confuses other tools. */
26504 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
26507 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26509 /* Record a mapping symbol for alignment frags. We will delete this
26510 later if the alignment ends up empty. */
26511 switch (fragP
->fr_type
)
26514 case rs_align_test
:
26516 mapping_state_2 (MAP_DATA
, max_chars
);
26518 case rs_align_code
:
26519 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26526 /* When we change sections we need to issue a new mapping symbol. */
26529 arm_elf_change_section (void)
26531 /* Link an unlinked unwind index table section to the .text section. */
26532 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26533 && elf_linked_to_section (now_seg
) == NULL
)
26534 elf_linked_to_section (now_seg
) = text_section
;
26538 arm_elf_section_type (const char * str
, size_t len
)
26540 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26541 return SHT_ARM_EXIDX
;
26546 /* Code to deal with unwinding tables. */
26548 static void add_unwind_adjustsp (offsetT
);
26550 /* Generate any deferred unwind frame offset. */
26553 flush_pending_unwind (void)
26557 offset
= unwind
.pending_offset
;
26558 unwind
.pending_offset
= 0;
26560 add_unwind_adjustsp (offset
);
26563 /* Add an opcode to this list for this function. Two-byte opcodes should
26564 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26568 add_unwind_opcode (valueT op
, int length
)
26570 /* Add any deferred stack adjustment. */
26571 if (unwind
.pending_offset
)
26572 flush_pending_unwind ();
26574 unwind
.sp_restored
= 0;
26576 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26578 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26579 if (unwind
.opcodes
)
26580 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26581 unwind
.opcode_alloc
);
26583 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26588 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26590 unwind
.opcode_count
++;
26594 /* Add unwind opcodes to adjust the stack pointer. */
26597 add_unwind_adjustsp (offsetT offset
)
26601 if (offset
> 0x200)
26603 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26608 /* Long form: 0xb2, uleb128. */
26609 /* This might not fit in a word so add the individual bytes,
26610 remembering the list is built in reverse order. */
26611 o
= (valueT
) ((offset
- 0x204) >> 2);
26613 add_unwind_opcode (0, 1);
26615 /* Calculate the uleb128 encoding of the offset. */
26619 bytes
[n
] = o
& 0x7f;
26625 /* Add the insn. */
26627 add_unwind_opcode (bytes
[n
- 1], 1);
26628 add_unwind_opcode (0xb2, 1);
26630 else if (offset
> 0x100)
26632 /* Two short opcodes. */
26633 add_unwind_opcode (0x3f, 1);
26634 op
= (offset
- 0x104) >> 2;
26635 add_unwind_opcode (op
, 1);
26637 else if (offset
> 0)
26639 /* Short opcode. */
26640 op
= (offset
- 4) >> 2;
26641 add_unwind_opcode (op
, 1);
26643 else if (offset
< 0)
26646 while (offset
> 0x100)
26648 add_unwind_opcode (0x7f, 1);
26651 op
= ((offset
- 4) >> 2) | 0x40;
26652 add_unwind_opcode (op
, 1);
26656 /* Finish the list of unwind opcodes for this function. */
26659 finish_unwind_opcodes (void)
26663 if (unwind
.fp_used
)
26665 /* Adjust sp as necessary. */
26666 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26667 flush_pending_unwind ();
26669 /* After restoring sp from the frame pointer. */
26670 op
= 0x90 | unwind
.fp_reg
;
26671 add_unwind_opcode (op
, 1);
26674 flush_pending_unwind ();
26678 /* Start an exception table entry. If idx is nonzero this is an index table
26682 start_unwind_section (const segT text_seg
, int idx
)
26684 const char * text_name
;
26685 const char * prefix
;
26686 const char * prefix_once
;
26687 const char * group_name
;
26695 prefix
= ELF_STRING_ARM_unwind
;
26696 prefix_once
= ELF_STRING_ARM_unwind_once
;
26697 type
= SHT_ARM_EXIDX
;
26701 prefix
= ELF_STRING_ARM_unwind_info
;
26702 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26703 type
= SHT_PROGBITS
;
26706 text_name
= segment_name (text_seg
);
26707 if (streq (text_name
, ".text"))
26710 if (strncmp (text_name
, ".gnu.linkonce.t.",
26711 strlen (".gnu.linkonce.t.")) == 0)
26713 prefix
= prefix_once
;
26714 text_name
+= strlen (".gnu.linkonce.t.");
26717 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26723 /* Handle COMDAT group. */
26724 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26726 group_name
= elf_group_name (text_seg
);
26727 if (group_name
== NULL
)
26729 as_bad (_("Group section `%s' has no group signature"),
26730 segment_name (text_seg
));
26731 ignore_rest_of_line ();
26734 flags
|= SHF_GROUP
;
26738 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26741 /* Set the section link for index tables. */
26743 elf_linked_to_section (now_seg
) = text_seg
;
26747 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26748 personality routine data. Returns zero, or the index table value for
26749 an inline entry. */
26752 create_unwind_entry (int have_data
)
26757 /* The current word of data. */
26759 /* The number of bytes left in this word. */
26762 finish_unwind_opcodes ();
26764 /* Remember the current text section. */
26765 unwind
.saved_seg
= now_seg
;
26766 unwind
.saved_subseg
= now_subseg
;
26768 start_unwind_section (now_seg
, 0);
26770 if (unwind
.personality_routine
== NULL
)
26772 if (unwind
.personality_index
== -2)
26775 as_bad (_("handlerdata in cantunwind frame"));
26776 return 1; /* EXIDX_CANTUNWIND. */
26779 /* Use a default personality routine if none is specified. */
26780 if (unwind
.personality_index
== -1)
26782 if (unwind
.opcode_count
> 3)
26783 unwind
.personality_index
= 1;
26785 unwind
.personality_index
= 0;
26788 /* Space for the personality routine entry. */
26789 if (unwind
.personality_index
== 0)
26791 if (unwind
.opcode_count
> 3)
26792 as_bad (_("too many unwind opcodes for personality routine 0"));
26796 /* All the data is inline in the index table. */
26799 while (unwind
.opcode_count
> 0)
26801 unwind
.opcode_count
--;
26802 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26806 /* Pad with "finish" opcodes. */
26808 data
= (data
<< 8) | 0xb0;
26815 /* We get two opcodes "free" in the first word. */
26816 size
= unwind
.opcode_count
- 2;
26820 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26821 if (unwind
.personality_index
!= -1)
26823 as_bad (_("attempt to recreate an unwind entry"));
26827 /* An extra byte is required for the opcode count. */
26828 size
= unwind
.opcode_count
+ 1;
26831 size
= (size
+ 3) >> 2;
26833 as_bad (_("too many unwind opcodes"));
26835 frag_align (2, 0, 0);
26836 record_alignment (now_seg
, 2);
26837 unwind
.table_entry
= expr_build_dot ();
26839 /* Allocate the table entry. */
26840 ptr
= frag_more ((size
<< 2) + 4);
26841 /* PR 13449: Zero the table entries in case some of them are not used. */
26842 memset (ptr
, 0, (size
<< 2) + 4);
26843 where
= frag_now_fix () - ((size
<< 2) + 4);
26845 switch (unwind
.personality_index
)
26848 /* ??? Should this be a PLT generating relocation? */
26849 /* Custom personality routine. */
26850 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26851 BFD_RELOC_ARM_PREL31
);
26856 /* Set the first byte to the number of additional words. */
26857 data
= size
> 0 ? size
- 1 : 0;
26861 /* ABI defined personality routines. */
26863 /* Three opcodes bytes are packed into the first word. */
26870 /* The size and first two opcode bytes go in the first word. */
26871 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26876 /* Should never happen. */
26880 /* Pack the opcodes into words (MSB first), reversing the list at the same
26882 while (unwind
.opcode_count
> 0)
26886 md_number_to_chars (ptr
, data
, 4);
26891 unwind
.opcode_count
--;
26893 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26896 /* Finish off the last word. */
26899 /* Pad with "finish" opcodes. */
26901 data
= (data
<< 8) | 0xb0;
26903 md_number_to_chars (ptr
, data
, 4);
26908 /* Add an empty descriptor if there is no user-specified data. */
26909 ptr
= frag_more (4);
26910 md_number_to_chars (ptr
, 0, 4);
26917 /* Initialize the DWARF-2 unwind information for this procedure. */
26920 tc_arm_frame_initial_instructions (void)
26922 cfi_add_CFA_def_cfa (REG_SP
, 0);
26924 #endif /* OBJ_ELF */
26926 /* Convert REGNAME to a DWARF-2 register number. */
26929 tc_arm_regname_to_dw2regnum (char *regname
)
26931 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26935 /* PR 16694: Allow VFP registers as well. */
26936 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26940 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26949 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26953 exp
.X_op
= O_secrel
;
26954 exp
.X_add_symbol
= symbol
;
26955 exp
.X_add_number
= 0;
26956 emit_expr (&exp
, size
);
26960 /* MD interface: Symbol and relocation handling. */
26962 /* Return the address within the segment that a PC-relative fixup is
26963 relative to. For ARM, PC-relative fixups applied to instructions
26964 are generally relative to the location of the fixup plus 8 bytes.
26965 Thumb branches are offset by 4, and Thumb loads relative to PC
26966 require special handling. */
26969 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26971 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26973 /* If this is pc-relative and we are going to emit a relocation
26974 then we just want to put out any pipeline compensation that the linker
26975 will need. Otherwise we want to use the calculated base.
26976 For WinCE we skip the bias for externals as well, since this
26977 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26979 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26980 || (arm_force_relocation (fixP
)
26982 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26988 switch (fixP
->fx_r_type
)
26990 /* PC relative addressing on the Thumb is slightly odd as the
26991 bottom two bits of the PC are forced to zero for the
26992 calculation. This happens *after* application of the
26993 pipeline offset. However, Thumb adrl already adjusts for
26994 this, so we need not do it again. */
26995 case BFD_RELOC_ARM_THUMB_ADD
:
26998 case BFD_RELOC_ARM_THUMB_OFFSET
:
26999 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27000 case BFD_RELOC_ARM_T32_ADD_PC12
:
27001 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27002 return (base
+ 4) & ~3;
27004 /* Thumb branches are simply offset by +4. */
27005 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27006 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27007 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27008 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27009 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27010 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27011 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27012 case BFD_RELOC_ARM_THUMB_BF17
:
27013 case BFD_RELOC_ARM_THUMB_BF19
:
27014 case BFD_RELOC_ARM_THUMB_BF13
:
27015 case BFD_RELOC_ARM_THUMB_LOOP12
:
27018 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27020 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27021 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27022 && ARM_IS_FUNC (fixP
->fx_addsy
)
27023 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27024 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27027 /* BLX is like branches above, but forces the low two bits of PC to
27029 case BFD_RELOC_THUMB_PCREL_BLX
:
27031 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27032 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27033 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27034 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27035 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27036 return (base
+ 4) & ~3;
27038 /* ARM mode branches are offset by +8. However, the Windows CE
27039 loader expects the relocation not to take this into account. */
27040 case BFD_RELOC_ARM_PCREL_BLX
:
27042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27043 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27044 && ARM_IS_FUNC (fixP
->fx_addsy
)
27045 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27046 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27049 case BFD_RELOC_ARM_PCREL_CALL
:
27051 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27052 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27053 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27054 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27055 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27058 case BFD_RELOC_ARM_PCREL_BRANCH
:
27059 case BFD_RELOC_ARM_PCREL_JUMP
:
27060 case BFD_RELOC_ARM_PLT32
:
27062 /* When handling fixups immediately, because we have already
27063 discovered the value of a symbol, or the address of the frag involved
27064 we must account for the offset by +8, as the OS loader will never see the reloc.
27065 see fixup_segment() in write.c
27066 The S_IS_EXTERNAL test handles the case of global symbols.
27067 Those need the calculated base, not just the pipe compensation the linker will need. */
27069 && fixP
->fx_addsy
!= NULL
27070 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27071 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27079 /* ARM mode loads relative to PC are also offset by +8. Unlike
27080 branches, the Windows CE loader *does* expect the relocation
27081 to take this into account. */
27082 case BFD_RELOC_ARM_OFFSET_IMM
:
27083 case BFD_RELOC_ARM_OFFSET_IMM8
:
27084 case BFD_RELOC_ARM_HWLITERAL
:
27085 case BFD_RELOC_ARM_LITERAL
:
27086 case BFD_RELOC_ARM_CP_OFF_IMM
:
27090 /* Other PC-relative relocations are un-offset. */
27096 static bfd_boolean flag_warn_syms
= TRUE
;
27099 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27101 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27102 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27103 does mean that the resulting code might be very confusing to the reader.
27104 Also this warning can be triggered if the user omits an operand before
27105 an immediate address, eg:
27109 GAS treats this as an assignment of the value of the symbol foo to a
27110 symbol LDR, and so (without this code) it will not issue any kind of
27111 warning or error message.
27113 Note - ARM instructions are case-insensitive but the strings in the hash
27114 table are all stored in lower case, so we must first ensure that name is
27116 if (flag_warn_syms
&& arm_ops_hsh
)
27118 char * nbuf
= strdup (name
);
27121 for (p
= nbuf
; *p
; p
++)
27123 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27125 static struct hash_control
* already_warned
= NULL
;
27127 if (already_warned
== NULL
)
27128 already_warned
= hash_new ();
27129 /* Only warn about the symbol once. To keep the code
27130 simple we let hash_insert do the lookup for us. */
27131 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27132 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27141 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27142 Otherwise we have no need to default values of symbols. */
27145 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27148 if (name
[0] == '_' && name
[1] == 'G'
27149 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27153 if (symbol_find (name
))
27154 as_bad (_("GOT already in the symbol table"));
27156 GOT_symbol
= symbol_new (name
, undefined_section
,
27157 (valueT
) 0, & zero_address_frag
);
27167 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27168 computed as two separate immediate values, added together. We
27169 already know that this value cannot be computed by just one ARM
27172 static unsigned int
27173 validate_immediate_twopart (unsigned int val
,
27174 unsigned int * highpart
)
27179 for (i
= 0; i
< 32; i
+= 2)
27180 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27186 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27188 else if (a
& 0xff0000)
27190 if (a
& 0xff000000)
27192 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27196 gas_assert (a
& 0xff000000);
27197 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27200 return (a
& 0xff) | (i
<< 7);
27207 validate_offset_imm (unsigned int val
, int hwse
)
27209 if ((hwse
&& val
> 255) || val
> 4095)
27214 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27215 negative immediate constant by altering the instruction. A bit of
27220 by inverting the second operand, and
27223 by negating the second operand. */
27226 negate_data_op (unsigned long * instruction
,
27227 unsigned long value
)
27230 unsigned long negated
, inverted
;
27232 negated
= encode_arm_immediate (-value
);
27233 inverted
= encode_arm_immediate (~value
);
27235 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27238 /* First negates. */
27239 case OPCODE_SUB
: /* ADD <-> SUB */
27240 new_inst
= OPCODE_ADD
;
27245 new_inst
= OPCODE_SUB
;
27249 case OPCODE_CMP
: /* CMP <-> CMN */
27250 new_inst
= OPCODE_CMN
;
27255 new_inst
= OPCODE_CMP
;
27259 /* Now Inverted ops. */
27260 case OPCODE_MOV
: /* MOV <-> MVN */
27261 new_inst
= OPCODE_MVN
;
27266 new_inst
= OPCODE_MOV
;
27270 case OPCODE_AND
: /* AND <-> BIC */
27271 new_inst
= OPCODE_BIC
;
27276 new_inst
= OPCODE_AND
;
27280 case OPCODE_ADC
: /* ADC <-> SBC */
27281 new_inst
= OPCODE_SBC
;
27286 new_inst
= OPCODE_ADC
;
27290 /* We cannot do anything. */
27295 if (value
== (unsigned) FAIL
)
27298 *instruction
&= OPCODE_MASK
;
27299 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27303 /* Like negate_data_op, but for Thumb-2. */
27305 static unsigned int
27306 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27310 unsigned int negated
, inverted
;
27312 negated
= encode_thumb32_immediate (-value
);
27313 inverted
= encode_thumb32_immediate (~value
);
27315 rd
= (*instruction
>> 8) & 0xf;
27316 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27319 /* ADD <-> SUB. Includes CMP <-> CMN. */
27320 case T2_OPCODE_SUB
:
27321 new_inst
= T2_OPCODE_ADD
;
27325 case T2_OPCODE_ADD
:
27326 new_inst
= T2_OPCODE_SUB
;
27330 /* ORR <-> ORN. Includes MOV <-> MVN. */
27331 case T2_OPCODE_ORR
:
27332 new_inst
= T2_OPCODE_ORN
;
27336 case T2_OPCODE_ORN
:
27337 new_inst
= T2_OPCODE_ORR
;
27341 /* AND <-> BIC. TST has no inverted equivalent. */
27342 case T2_OPCODE_AND
:
27343 new_inst
= T2_OPCODE_BIC
;
27350 case T2_OPCODE_BIC
:
27351 new_inst
= T2_OPCODE_AND
;
27356 case T2_OPCODE_ADC
:
27357 new_inst
= T2_OPCODE_SBC
;
27361 case T2_OPCODE_SBC
:
27362 new_inst
= T2_OPCODE_ADC
;
27366 /* We cannot do anything. */
27371 if (value
== (unsigned int)FAIL
)
27374 *instruction
&= T2_OPCODE_MASK
;
27375 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27379 /* Read a 32-bit thumb instruction from buf. */
27381 static unsigned long
27382 get_thumb32_insn (char * buf
)
27384 unsigned long insn
;
27385 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27386 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27391 /* We usually want to set the low bit on the address of thumb function
27392 symbols. In particular .word foo - . should have the low bit set.
27393 Generic code tries to fold the difference of two symbols to
27394 a constant. Prevent this and force a relocation when the first symbols
27395 is a thumb function. */
27398 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27400 if (op
== O_subtract
27401 && l
->X_op
== O_symbol
27402 && r
->X_op
== O_symbol
27403 && THUMB_IS_FUNC (l
->X_add_symbol
))
27405 l
->X_op
= O_subtract
;
27406 l
->X_op_symbol
= r
->X_add_symbol
;
27407 l
->X_add_number
-= r
->X_add_number
;
27411 /* Process as normal. */
27415 /* Encode Thumb2 unconditional branches and calls. The encoding
27416 for the 2 are identical for the immediate values. */
27419 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27421 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27424 addressT S
, I1
, I2
, lo
, hi
;
27426 S
= (value
>> 24) & 0x01;
27427 I1
= (value
>> 23) & 0x01;
27428 I2
= (value
>> 22) & 0x01;
27429 hi
= (value
>> 12) & 0x3ff;
27430 lo
= (value
>> 1) & 0x7ff;
27431 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27432 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27433 newval
|= (S
<< 10) | hi
;
27434 newval2
&= ~T2I1I2MASK
;
27435 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27436 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27437 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27441 md_apply_fix (fixS
* fixP
,
27445 offsetT value
= * valP
;
27447 unsigned int newimm
;
27448 unsigned long temp
;
27450 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27452 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27454 /* Note whether this will delete the relocation. */
27456 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27459 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27460 consistency with the behaviour on 32-bit hosts. Remember value
27462 value
&= 0xffffffff;
27463 value
^= 0x80000000;
27464 value
-= 0x80000000;
27467 fixP
->fx_addnumber
= value
;
27469 /* Same treatment for fixP->fx_offset. */
27470 fixP
->fx_offset
&= 0xffffffff;
27471 fixP
->fx_offset
^= 0x80000000;
27472 fixP
->fx_offset
-= 0x80000000;
27474 switch (fixP
->fx_r_type
)
27476 case BFD_RELOC_NONE
:
27477 /* This will need to go in the object file. */
27481 case BFD_RELOC_ARM_IMMEDIATE
:
27482 /* We claim that this fixup has been processed here,
27483 even if in fact we generate an error because we do
27484 not have a reloc for it, so tc_gen_reloc will reject it. */
27487 if (fixP
->fx_addsy
)
27489 const char *msg
= 0;
27491 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27492 msg
= _("undefined symbol %s used as an immediate value");
27493 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27494 msg
= _("symbol %s is in a different section");
27495 else if (S_IS_WEAK (fixP
->fx_addsy
))
27496 msg
= _("symbol %s is weak and may be overridden later");
27500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27501 msg
, S_GET_NAME (fixP
->fx_addsy
));
27506 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27508 /* If the offset is negative, we should use encoding A2 for ADR. */
27509 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27510 newimm
= negate_data_op (&temp
, value
);
27513 newimm
= encode_arm_immediate (value
);
27515 /* If the instruction will fail, see if we can fix things up by
27516 changing the opcode. */
27517 if (newimm
== (unsigned int) FAIL
)
27518 newimm
= negate_data_op (&temp
, value
);
27519 /* MOV accepts both ARM modified immediate (A1 encoding) and
27520 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27521 When disassembling, MOV is preferred when there is no encoding
27523 if (newimm
== (unsigned int) FAIL
27524 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27525 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27526 && !((temp
>> SBIT_SHIFT
) & 0x1)
27527 && value
>= 0 && value
<= 0xffff)
27529 /* Clear bits[23:20] to change encoding from A1 to A2. */
27530 temp
&= 0xff0fffff;
27531 /* Encoding high 4bits imm. Code below will encode the remaining
27533 temp
|= (value
& 0x0000f000) << 4;
27534 newimm
= value
& 0x00000fff;
27538 if (newimm
== (unsigned int) FAIL
)
27540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27541 _("invalid constant (%lx) after fixup"),
27542 (unsigned long) value
);
27546 newimm
|= (temp
& 0xfffff000);
27547 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27550 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27552 unsigned int highpart
= 0;
27553 unsigned int newinsn
= 0xe1a00000; /* nop. */
27555 if (fixP
->fx_addsy
)
27557 const char *msg
= 0;
27559 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27560 msg
= _("undefined symbol %s used as an immediate value");
27561 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27562 msg
= _("symbol %s is in a different section");
27563 else if (S_IS_WEAK (fixP
->fx_addsy
))
27564 msg
= _("symbol %s is weak and may be overridden later");
27568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27569 msg
, S_GET_NAME (fixP
->fx_addsy
));
27574 newimm
= encode_arm_immediate (value
);
27575 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27577 /* If the instruction will fail, see if we can fix things up by
27578 changing the opcode. */
27579 if (newimm
== (unsigned int) FAIL
27580 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27582 /* No ? OK - try using two ADD instructions to generate
27584 newimm
= validate_immediate_twopart (value
, & highpart
);
27586 /* Yes - then make sure that the second instruction is
27588 if (newimm
!= (unsigned int) FAIL
)
27590 /* Still No ? Try using a negated value. */
27591 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27592 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27593 /* Otherwise - give up. */
27596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27597 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27602 /* Replace the first operand in the 2nd instruction (which
27603 is the PC) with the destination register. We have
27604 already added in the PC in the first instruction and we
27605 do not want to do it again. */
27606 newinsn
&= ~ 0xf0000;
27607 newinsn
|= ((newinsn
& 0x0f000) << 4);
27610 newimm
|= (temp
& 0xfffff000);
27611 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27613 highpart
|= (newinsn
& 0xfffff000);
27614 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27618 case BFD_RELOC_ARM_OFFSET_IMM
:
27619 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27621 /* Fall through. */
27623 case BFD_RELOC_ARM_LITERAL
:
27629 if (validate_offset_imm (value
, 0) == FAIL
)
27631 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27633 _("invalid literal constant: pool needs to be closer"));
27635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27636 _("bad immediate value for offset (%ld)"),
27641 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27643 newval
&= 0xfffff000;
27646 newval
&= 0xff7ff000;
27647 newval
|= value
| (sign
? INDEX_UP
: 0);
27649 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27652 case BFD_RELOC_ARM_OFFSET_IMM8
:
27653 case BFD_RELOC_ARM_HWLITERAL
:
27659 if (validate_offset_imm (value
, 1) == FAIL
)
27661 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27663 _("invalid literal constant: pool needs to be closer"));
27665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27666 _("bad immediate value for 8-bit offset (%ld)"),
27671 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27673 newval
&= 0xfffff0f0;
27676 newval
&= 0xff7ff0f0;
27677 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27679 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27682 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27683 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27685 _("bad immediate value for offset (%ld)"), (long) value
);
27688 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27690 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27693 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27694 /* This is a complicated relocation used for all varieties of Thumb32
27695 load/store instruction with immediate offset:
27697 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27698 *4, optional writeback(W)
27699 (doubleword load/store)
27701 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27702 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27703 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27704 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27705 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27707 Uppercase letters indicate bits that are already encoded at
27708 this point. Lowercase letters are our problem. For the
27709 second block of instructions, the secondary opcode nybble
27710 (bits 8..11) is present, and bit 23 is zero, even if this is
27711 a PC-relative operation. */
27712 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27714 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27716 if ((newval
& 0xf0000000) == 0xe0000000)
27718 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27720 newval
|= (1 << 23);
27723 if (value
% 4 != 0)
27725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27726 _("offset not a multiple of 4"));
27732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27733 _("offset out of range"));
27738 else if ((newval
& 0x000f0000) == 0x000f0000)
27740 /* PC-relative, 12-bit offset. */
27742 newval
|= (1 << 23);
27747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27748 _("offset out of range"));
27753 else if ((newval
& 0x00000100) == 0x00000100)
27755 /* Writeback: 8-bit, +/- offset. */
27757 newval
|= (1 << 9);
27762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27763 _("offset out of range"));
27768 else if ((newval
& 0x00000f00) == 0x00000e00)
27770 /* T-instruction: positive 8-bit offset. */
27771 if (value
< 0 || value
> 0xff)
27773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27774 _("offset out of range"));
27782 /* Positive 12-bit or negative 8-bit offset. */
27786 newval
|= (1 << 23);
27796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27797 _("offset out of range"));
27804 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27805 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27808 case BFD_RELOC_ARM_SHIFT_IMM
:
27809 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27810 if (((unsigned long) value
) > 32
27812 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27815 _("shift expression is too large"));
27820 /* Shifts of zero must be done as lsl. */
27822 else if (value
== 32)
27824 newval
&= 0xfffff07f;
27825 newval
|= (value
& 0x1f) << 7;
27826 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27829 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27830 case BFD_RELOC_ARM_T32_ADD_IMM
:
27831 case BFD_RELOC_ARM_T32_IMM12
:
27832 case BFD_RELOC_ARM_T32_ADD_PC12
:
27833 /* We claim that this fixup has been processed here,
27834 even if in fact we generate an error because we do
27835 not have a reloc for it, so tc_gen_reloc will reject it. */
27839 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27842 _("undefined symbol %s used as an immediate value"),
27843 S_GET_NAME (fixP
->fx_addsy
));
27847 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27849 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27852 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27853 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27854 Thumb2 modified immediate encoding (T2). */
27855 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27856 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27858 newimm
= encode_thumb32_immediate (value
);
27859 if (newimm
== (unsigned int) FAIL
)
27860 newimm
= thumb32_negate_data_op (&newval
, value
);
27862 if (newimm
== (unsigned int) FAIL
)
27864 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27866 /* Turn add/sum into addw/subw. */
27867 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27868 newval
= (newval
& 0xfeffffff) | 0x02000000;
27869 /* No flat 12-bit imm encoding for addsw/subsw. */
27870 if ((newval
& 0x00100000) == 0)
27872 /* 12 bit immediate for addw/subw. */
27876 newval
^= 0x00a00000;
27879 newimm
= (unsigned int) FAIL
;
27886 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27887 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27888 disassembling, MOV is preferred when there is no encoding
27890 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27891 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27892 but with the Rn field [19:16] set to 1111. */
27893 && (((newval
>> 16) & 0xf) == 0xf)
27894 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27895 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27896 && value
>= 0 && value
<= 0xffff)
27898 /* Toggle bit[25] to change encoding from T2 to T3. */
27900 /* Clear bits[19:16]. */
27901 newval
&= 0xfff0ffff;
27902 /* Encoding high 4bits imm. Code below will encode the
27903 remaining low 12bits. */
27904 newval
|= (value
& 0x0000f000) << 4;
27905 newimm
= value
& 0x00000fff;
27910 if (newimm
== (unsigned int)FAIL
)
27912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27913 _("invalid constant (%lx) after fixup"),
27914 (unsigned long) value
);
27918 newval
|= (newimm
& 0x800) << 15;
27919 newval
|= (newimm
& 0x700) << 4;
27920 newval
|= (newimm
& 0x0ff);
27922 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27923 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27926 case BFD_RELOC_ARM_SMC
:
27927 if (((unsigned long) value
) > 0xf)
27928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27929 _("invalid smc expression"));
27931 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27932 newval
|= (value
& 0xf);
27933 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27936 case BFD_RELOC_ARM_HVC
:
27937 if (((unsigned long) value
) > 0xffff)
27938 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27939 _("invalid hvc expression"));
27940 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27941 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27942 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27945 case BFD_RELOC_ARM_SWI
:
27946 if (fixP
->tc_fix_data
!= 0)
27948 if (((unsigned long) value
) > 0xff)
27949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27950 _("invalid swi expression"));
27951 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27953 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27957 if (((unsigned long) value
) > 0x00ffffff)
27958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27959 _("invalid swi expression"));
27960 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27962 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27966 case BFD_RELOC_ARM_MULTI
:
27967 if (((unsigned long) value
) > 0xffff)
27968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27969 _("invalid expression in load/store multiple"));
27970 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27971 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27975 case BFD_RELOC_ARM_PCREL_CALL
:
27977 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27979 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27980 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27981 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27982 /* Flip the bl to blx. This is a simple flip
27983 bit here because we generate PCREL_CALL for
27984 unconditional bls. */
27986 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27987 newval
= newval
| 0x10000000;
27988 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27994 goto arm_branch_common
;
27996 case BFD_RELOC_ARM_PCREL_JUMP
:
27997 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27999 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28000 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28001 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28003 /* This would map to a bl<cond>, b<cond>,
28004 b<always> to a Thumb function. We
28005 need to force a relocation for this particular
28007 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28010 /* Fall through. */
28012 case BFD_RELOC_ARM_PLT32
:
28014 case BFD_RELOC_ARM_PCREL_BRANCH
:
28016 goto arm_branch_common
;
28018 case BFD_RELOC_ARM_PCREL_BLX
:
28021 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28023 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28024 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28025 && ARM_IS_FUNC (fixP
->fx_addsy
))
28027 /* Flip the blx to a bl and warn. */
28028 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28029 newval
= 0xeb000000;
28030 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28031 _("blx to '%s' an ARM ISA state function changed to bl"),
28033 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28039 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28040 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28044 /* We are going to store value (shifted right by two) in the
28045 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28046 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28050 _("misaligned branch destination"));
28051 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28052 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28055 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28057 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28058 newval
|= (value
>> 2) & 0x00ffffff;
28059 /* Set the H bit on BLX instructions. */
28063 newval
|= 0x01000000;
28065 newval
&= ~0x01000000;
28067 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28071 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28072 /* CBZ can only branch forward. */
28074 /* Attempts to use CBZ to branch to the next instruction
28075 (which, strictly speaking, are prohibited) will be turned into
28078 FIXME: It may be better to remove the instruction completely and
28079 perform relaxation. */
28082 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28083 newval
= 0xbf00; /* NOP encoding T1 */
28084 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28091 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28093 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28094 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28095 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28100 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28101 if (out_of_range_p (value
, 8))
28102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28106 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28107 newval
|= (value
& 0x1ff) >> 1;
28108 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28112 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28113 if (out_of_range_p (value
, 11))
28114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28116 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28118 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28119 newval
|= (value
& 0xfff) >> 1;
28120 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28124 /* This relocation is misnamed, it should be BRANCH21. */
28125 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28127 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28128 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28129 && ARM_IS_FUNC (fixP
->fx_addsy
)
28130 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28132 /* Force a relocation for a branch 20 bits wide. */
28135 if (out_of_range_p (value
, 20))
28136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28137 _("conditional branch out of range"));
28139 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28142 addressT S
, J1
, J2
, lo
, hi
;
28144 S
= (value
& 0x00100000) >> 20;
28145 J2
= (value
& 0x00080000) >> 19;
28146 J1
= (value
& 0x00040000) >> 18;
28147 hi
= (value
& 0x0003f000) >> 12;
28148 lo
= (value
& 0x00000ffe) >> 1;
28150 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28151 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28152 newval
|= (S
<< 10) | hi
;
28153 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28154 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28155 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28159 case BFD_RELOC_THUMB_PCREL_BLX
:
28160 /* If there is a blx from a thumb state function to
28161 another thumb function flip this to a bl and warn
28165 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28166 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28167 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28169 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28170 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28171 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28173 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28174 newval
= newval
| 0x1000;
28175 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28176 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28181 goto thumb_bl_common
;
28183 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28184 /* A bl from Thumb state ISA to an internal ARM state function
28185 is converted to a blx. */
28187 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28188 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28189 && ARM_IS_FUNC (fixP
->fx_addsy
)
28190 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28192 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28193 newval
= newval
& ~0x1000;
28194 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28195 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28201 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28202 /* For a BLX instruction, make sure that the relocation is rounded up
28203 to a word boundary. This follows the semantics of the instruction
28204 which specifies that bit 1 of the target address will come from bit
28205 1 of the base address. */
28206 value
= (value
+ 3) & ~ 3;
28209 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28210 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28211 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28214 if (out_of_range_p (value
, 22))
28216 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28218 else if (out_of_range_p (value
, 24))
28219 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28220 _("Thumb2 branch out of range"));
28223 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28224 encode_thumb2_b_bl_offset (buf
, value
);
28228 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28229 if (out_of_range_p (value
, 24))
28230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28233 encode_thumb2_b_bl_offset (buf
, value
);
28238 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28243 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28244 md_number_to_chars (buf
, value
, 2);
28248 case BFD_RELOC_ARM_TLS_CALL
:
28249 case BFD_RELOC_ARM_THM_TLS_CALL
:
28250 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28251 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28252 case BFD_RELOC_ARM_TLS_GOTDESC
:
28253 case BFD_RELOC_ARM_TLS_GD32
:
28254 case BFD_RELOC_ARM_TLS_LE32
:
28255 case BFD_RELOC_ARM_TLS_IE32
:
28256 case BFD_RELOC_ARM_TLS_LDM32
:
28257 case BFD_RELOC_ARM_TLS_LDO32
:
28258 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28261 /* Same handling as above, but with the arm_fdpic guard. */
28262 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28263 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28264 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28267 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28272 _("Relocation supported only in FDPIC mode"));
28276 case BFD_RELOC_ARM_GOT32
:
28277 case BFD_RELOC_ARM_GOTOFF
:
28280 case BFD_RELOC_ARM_GOT_PREL
:
28281 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28282 md_number_to_chars (buf
, value
, 4);
28285 case BFD_RELOC_ARM_TARGET2
:
28286 /* TARGET2 is not partial-inplace, so we need to write the
28287 addend here for REL targets, because it won't be written out
28288 during reloc processing later. */
28289 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28290 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28293 /* Relocations for FDPIC. */
28294 case BFD_RELOC_ARM_GOTFUNCDESC
:
28295 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28296 case BFD_RELOC_ARM_FUNCDESC
:
28299 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28300 md_number_to_chars (buf
, 0, 4);
28304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28305 _("Relocation supported only in FDPIC mode"));
28310 case BFD_RELOC_RVA
:
28312 case BFD_RELOC_ARM_TARGET1
:
28313 case BFD_RELOC_ARM_ROSEGREL32
:
28314 case BFD_RELOC_ARM_SBREL32
:
28315 case BFD_RELOC_32_PCREL
:
28317 case BFD_RELOC_32_SECREL
:
28319 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28321 /* For WinCE we only do this for pcrel fixups. */
28322 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28324 md_number_to_chars (buf
, value
, 4);
28328 case BFD_RELOC_ARM_PREL31
:
28329 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28331 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28332 if ((value
^ (value
>> 1)) & 0x40000000)
28334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28335 _("rel31 relocation overflow"));
28337 newval
|= value
& 0x7fffffff;
28338 md_number_to_chars (buf
, newval
, 4);
28343 case BFD_RELOC_ARM_CP_OFF_IMM
:
28344 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28345 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28346 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28347 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28349 newval
= get_thumb32_insn (buf
);
28350 if ((newval
& 0x0f200f00) == 0x0d000900)
28352 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28353 has permitted values that are multiples of 2, in the range 0
28355 if (value
< -510 || value
> 510 || (value
& 1))
28356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28357 _("co-processor offset out of range"));
28359 else if ((newval
& 0xfe001f80) == 0xec000f80)
28361 if (value
< -511 || value
> 512 || (value
& 3))
28362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28363 _("co-processor offset out of range"));
28365 else if (value
< -1023 || value
> 1023 || (value
& 3))
28366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28367 _("co-processor offset out of range"));
28372 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28373 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28374 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28376 newval
= get_thumb32_insn (buf
);
28379 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28380 newval
&= 0xffffff80;
28382 newval
&= 0xffffff00;
28386 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28387 newval
&= 0xff7fff80;
28389 newval
&= 0xff7fff00;
28390 if ((newval
& 0x0f200f00) == 0x0d000900)
28392 /* This is a fp16 vstr/vldr.
28394 It requires the immediate offset in the instruction is shifted
28395 left by 1 to be a half-word offset.
28397 Here, left shift by 1 first, and later right shift by 2
28398 should get the right offset. */
28401 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28403 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28404 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28405 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28407 put_thumb32_insn (buf
, newval
);
28410 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28411 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28412 if (value
< -255 || value
> 255)
28413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28414 _("co-processor offset out of range"));
28416 goto cp_off_common
;
28418 case BFD_RELOC_ARM_THUMB_OFFSET
:
28419 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28420 /* Exactly what ranges, and where the offset is inserted depends
28421 on the type of instruction, we can establish this from the
28423 switch (newval
>> 12)
28425 case 4: /* PC load. */
28426 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28427 forced to zero for these loads; md_pcrel_from has already
28428 compensated for this. */
28430 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28431 _("invalid offset, target not word aligned (0x%08lX)"),
28432 (((unsigned long) fixP
->fx_frag
->fr_address
28433 + (unsigned long) fixP
->fx_where
) & ~3)
28434 + (unsigned long) value
);
28436 if (value
& ~0x3fc)
28437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28438 _("invalid offset, value too big (0x%08lX)"),
28441 newval
|= value
>> 2;
28444 case 9: /* SP load/store. */
28445 if (value
& ~0x3fc)
28446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28447 _("invalid offset, value too big (0x%08lX)"),
28449 newval
|= value
>> 2;
28452 case 6: /* Word load/store. */
28454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28455 _("invalid offset, value too big (0x%08lX)"),
28457 newval
|= value
<< 4; /* 6 - 2. */
28460 case 7: /* Byte load/store. */
28462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28463 _("invalid offset, value too big (0x%08lX)"),
28465 newval
|= value
<< 6;
28468 case 8: /* Halfword load/store. */
28470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28471 _("invalid offset, value too big (0x%08lX)"),
28473 newval
|= value
<< 5; /* 6 - 1. */
28477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28478 "Unable to process relocation for thumb opcode: %lx",
28479 (unsigned long) newval
);
28482 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28485 case BFD_RELOC_ARM_THUMB_ADD
:
28486 /* This is a complicated relocation, since we use it for all of
28487 the following immediate relocations:
28491 9bit ADD/SUB SP word-aligned
28492 10bit ADD PC/SP word-aligned
28494 The type of instruction being processed is encoded in the
28501 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28503 int rd
= (newval
>> 4) & 0xf;
28504 int rs
= newval
& 0xf;
28505 int subtract
= !!(newval
& 0x8000);
28507 /* Check for HI regs, only very restricted cases allowed:
28508 Adjusting SP, and using PC or SP to get an address. */
28509 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28510 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28512 _("invalid Hi register with immediate"));
28514 /* If value is negative, choose the opposite instruction. */
28518 subtract
= !subtract
;
28520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28521 _("immediate value out of range"));
28526 if (value
& ~0x1fc)
28527 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28528 _("invalid immediate for stack address calculation"));
28529 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28530 newval
|= value
>> 2;
28532 else if (rs
== REG_PC
|| rs
== REG_SP
)
28534 /* PR gas/18541. If the addition is for a defined symbol
28535 within range of an ADR instruction then accept it. */
28538 && fixP
->fx_addsy
!= NULL
)
28542 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28543 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28544 || S_IS_WEAK (fixP
->fx_addsy
))
28546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28547 _("address calculation needs a strongly defined nearby symbol"));
28551 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28553 /* Round up to the next 4-byte boundary. */
28558 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28563 _("symbol too far away"));
28573 if (subtract
|| value
& ~0x3fc)
28574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28575 _("invalid immediate for address calculation (value = 0x%08lX)"),
28576 (unsigned long) (subtract
? - value
: value
));
28577 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28579 newval
|= value
>> 2;
28584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28585 _("immediate value out of range"));
28586 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28587 newval
|= (rd
<< 8) | value
;
28592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28593 _("immediate value out of range"));
28594 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28595 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28598 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28601 case BFD_RELOC_ARM_THUMB_IMM
:
28602 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28603 if (value
< 0 || value
> 255)
28604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28605 _("invalid immediate: %ld is out of range"),
28608 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28611 case BFD_RELOC_ARM_THUMB_SHIFT
:
28612 /* 5bit shift value (0..32). LSL cannot take 32. */
28613 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28614 temp
= newval
& 0xf800;
28615 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28617 _("invalid shift value: %ld"), (long) value
);
28618 /* Shifts of zero must be encoded as LSL. */
28620 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28621 /* Shifts of 32 are encoded as zero. */
28622 else if (value
== 32)
28624 newval
|= value
<< 6;
28625 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28628 case BFD_RELOC_VTABLE_INHERIT
:
28629 case BFD_RELOC_VTABLE_ENTRY
:
28633 case BFD_RELOC_ARM_MOVW
:
28634 case BFD_RELOC_ARM_MOVT
:
28635 case BFD_RELOC_ARM_THUMB_MOVW
:
28636 case BFD_RELOC_ARM_THUMB_MOVT
:
28637 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28639 /* REL format relocations are limited to a 16-bit addend. */
28640 if (!fixP
->fx_done
)
28642 if (value
< -0x8000 || value
> 0x7fff)
28643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28644 _("offset out of range"));
28646 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28647 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28652 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28653 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28655 newval
= get_thumb32_insn (buf
);
28656 newval
&= 0xfbf08f00;
28657 newval
|= (value
& 0xf000) << 4;
28658 newval
|= (value
& 0x0800) << 15;
28659 newval
|= (value
& 0x0700) << 4;
28660 newval
|= (value
& 0x00ff);
28661 put_thumb32_insn (buf
, newval
);
28665 newval
= md_chars_to_number (buf
, 4);
28666 newval
&= 0xfff0f000;
28667 newval
|= value
& 0x0fff;
28668 newval
|= (value
& 0xf000) << 4;
28669 md_number_to_chars (buf
, newval
, 4);
28674 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28675 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28676 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28677 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28678 gas_assert (!fixP
->fx_done
);
28681 bfd_boolean is_mov
;
28682 bfd_vma encoded_addend
= value
;
28684 /* Check that addend can be encoded in instruction. */
28685 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28687 _("the offset 0x%08lX is not representable"),
28688 (unsigned long) encoded_addend
);
28690 /* Extract the instruction. */
28691 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28692 is_mov
= (insn
& 0xf800) == 0x2000;
28697 if (!seg
->use_rela_p
)
28698 insn
|= encoded_addend
;
28704 /* Extract the instruction. */
28705 /* Encoding is the following
28710 /* The following conditions must be true :
28715 rd
= (insn
>> 4) & 0xf;
28717 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28719 _("Unable to process relocation for thumb opcode: %lx"),
28720 (unsigned long) insn
);
28722 /* Encode as ADD immediate8 thumb 1 code. */
28723 insn
= 0x3000 | (rd
<< 8);
28725 /* Place the encoded addend into the first 8 bits of the
28727 if (!seg
->use_rela_p
)
28728 insn
|= encoded_addend
;
28731 /* Update the instruction. */
28732 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28736 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28737 case BFD_RELOC_ARM_ALU_PC_G0
:
28738 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28739 case BFD_RELOC_ARM_ALU_PC_G1
:
28740 case BFD_RELOC_ARM_ALU_PC_G2
:
28741 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28742 case BFD_RELOC_ARM_ALU_SB_G0
:
28743 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28744 case BFD_RELOC_ARM_ALU_SB_G1
:
28745 case BFD_RELOC_ARM_ALU_SB_G2
:
28746 gas_assert (!fixP
->fx_done
);
28747 if (!seg
->use_rela_p
)
28750 bfd_vma encoded_addend
;
28751 bfd_vma addend_abs
= llabs (value
);
28753 /* Check that the absolute value of the addend can be
28754 expressed as an 8-bit constant plus a rotation. */
28755 encoded_addend
= encode_arm_immediate (addend_abs
);
28756 if (encoded_addend
== (unsigned int) FAIL
)
28757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28758 _("the offset 0x%08lX is not representable"),
28759 (unsigned long) addend_abs
);
28761 /* Extract the instruction. */
28762 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28764 /* If the addend is positive, use an ADD instruction.
28765 Otherwise use a SUB. Take care not to destroy the S bit. */
28766 insn
&= 0xff1fffff;
28772 /* Place the encoded addend into the first 12 bits of the
28774 insn
&= 0xfffff000;
28775 insn
|= encoded_addend
;
28777 /* Update the instruction. */
28778 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28782 case BFD_RELOC_ARM_LDR_PC_G0
:
28783 case BFD_RELOC_ARM_LDR_PC_G1
:
28784 case BFD_RELOC_ARM_LDR_PC_G2
:
28785 case BFD_RELOC_ARM_LDR_SB_G0
:
28786 case BFD_RELOC_ARM_LDR_SB_G1
:
28787 case BFD_RELOC_ARM_LDR_SB_G2
:
28788 gas_assert (!fixP
->fx_done
);
28789 if (!seg
->use_rela_p
)
28792 bfd_vma addend_abs
= llabs (value
);
28794 /* Check that the absolute value of the addend can be
28795 encoded in 12 bits. */
28796 if (addend_abs
>= 0x1000)
28797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28798 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28799 (unsigned long) addend_abs
);
28801 /* Extract the instruction. */
28802 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28804 /* If the addend is negative, clear bit 23 of the instruction.
28805 Otherwise set it. */
28807 insn
&= ~(1 << 23);
28811 /* Place the absolute value of the addend into the first 12 bits
28812 of the instruction. */
28813 insn
&= 0xfffff000;
28814 insn
|= addend_abs
;
28816 /* Update the instruction. */
28817 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28821 case BFD_RELOC_ARM_LDRS_PC_G0
:
28822 case BFD_RELOC_ARM_LDRS_PC_G1
:
28823 case BFD_RELOC_ARM_LDRS_PC_G2
:
28824 case BFD_RELOC_ARM_LDRS_SB_G0
:
28825 case BFD_RELOC_ARM_LDRS_SB_G1
:
28826 case BFD_RELOC_ARM_LDRS_SB_G2
:
28827 gas_assert (!fixP
->fx_done
);
28828 if (!seg
->use_rela_p
)
28831 bfd_vma addend_abs
= llabs (value
);
28833 /* Check that the absolute value of the addend can be
28834 encoded in 8 bits. */
28835 if (addend_abs
>= 0x100)
28836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28837 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28838 (unsigned long) addend_abs
);
28840 /* Extract the instruction. */
28841 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28843 /* If the addend is negative, clear bit 23 of the instruction.
28844 Otherwise set it. */
28846 insn
&= ~(1 << 23);
28850 /* Place the first four bits of the absolute value of the addend
28851 into the first 4 bits of the instruction, and the remaining
28852 four into bits 8 .. 11. */
28853 insn
&= 0xfffff0f0;
28854 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28856 /* Update the instruction. */
28857 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28861 case BFD_RELOC_ARM_LDC_PC_G0
:
28862 case BFD_RELOC_ARM_LDC_PC_G1
:
28863 case BFD_RELOC_ARM_LDC_PC_G2
:
28864 case BFD_RELOC_ARM_LDC_SB_G0
:
28865 case BFD_RELOC_ARM_LDC_SB_G1
:
28866 case BFD_RELOC_ARM_LDC_SB_G2
:
28867 gas_assert (!fixP
->fx_done
);
28868 if (!seg
->use_rela_p
)
28871 bfd_vma addend_abs
= llabs (value
);
28873 /* Check that the absolute value of the addend is a multiple of
28874 four and, when divided by four, fits in 8 bits. */
28875 if (addend_abs
& 0x3)
28876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28877 _("bad offset 0x%08lX (must be word-aligned)"),
28878 (unsigned long) addend_abs
);
28880 if ((addend_abs
>> 2) > 0xff)
28881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28882 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28883 (unsigned long) addend_abs
);
28885 /* Extract the instruction. */
28886 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28888 /* If the addend is negative, clear bit 23 of the instruction.
28889 Otherwise set it. */
28891 insn
&= ~(1 << 23);
28895 /* Place the addend (divided by four) into the first eight
28896 bits of the instruction. */
28897 insn
&= 0xfffffff0;
28898 insn
|= addend_abs
>> 2;
28900 /* Update the instruction. */
28901 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28905 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28907 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28908 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28909 && ARM_IS_FUNC (fixP
->fx_addsy
)
28910 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28912 /* Force a relocation for a branch 5 bits wide. */
28915 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28919 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28921 addressT boff
= value
>> 1;
28923 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28924 newval
|= (boff
<< 7);
28925 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28929 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28931 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28932 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28933 && ARM_IS_FUNC (fixP
->fx_addsy
)
28934 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28938 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28940 _("branch out of range"));
28942 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28944 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28946 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28947 addressT diff
= value
- boff
;
28951 newval
|= 1 << 1; /* T bit. */
28953 else if (diff
!= 2)
28955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28956 _("out of range label-relative fixup value"));
28958 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28962 case BFD_RELOC_ARM_THUMB_BF17
:
28964 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28965 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28966 && ARM_IS_FUNC (fixP
->fx_addsy
)
28967 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28969 /* Force a relocation for a branch 17 bits wide. */
28973 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28977 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28980 addressT immA
, immB
, immC
;
28982 immA
= (value
& 0x0001f000) >> 12;
28983 immB
= (value
& 0x00000ffc) >> 2;
28984 immC
= (value
& 0x00000002) >> 1;
28986 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28987 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28989 newval2
|= (immC
<< 11) | (immB
<< 1);
28990 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28991 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28995 case BFD_RELOC_ARM_THUMB_BF19
:
28997 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28998 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28999 && ARM_IS_FUNC (fixP
->fx_addsy
)
29000 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29002 /* Force a relocation for a branch 19 bits wide. */
29006 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29010 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29013 addressT immA
, immB
, immC
;
29015 immA
= (value
& 0x0007f000) >> 12;
29016 immB
= (value
& 0x00000ffc) >> 2;
29017 immC
= (value
& 0x00000002) >> 1;
29019 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29020 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29022 newval2
|= (immC
<< 11) | (immB
<< 1);
29023 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29024 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29028 case BFD_RELOC_ARM_THUMB_BF13
:
29030 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29031 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29032 && ARM_IS_FUNC (fixP
->fx_addsy
)
29033 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29035 /* Force a relocation for a branch 13 bits wide. */
29039 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29043 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29046 addressT immA
, immB
, immC
;
29048 immA
= (value
& 0x00001000) >> 12;
29049 immB
= (value
& 0x00000ffc) >> 2;
29050 immC
= (value
& 0x00000002) >> 1;
29052 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29053 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29055 newval2
|= (immC
<< 11) | (immB
<< 1);
29056 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29057 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29061 case BFD_RELOC_ARM_THUMB_LOOP12
:
29063 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29064 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29065 && ARM_IS_FUNC (fixP
->fx_addsy
)
29066 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29068 /* Force a relocation for a branch 12 bits wide. */
29072 bfd_vma insn
= get_thumb32_insn (buf
);
29073 /* le lr, <label>, le <label> or letp lr, <label> */
29074 if (((insn
& 0xffffffff) == 0xf00fc001)
29075 || ((insn
& 0xffffffff) == 0xf02fc001)
29076 || ((insn
& 0xffffffff) == 0xf01fc001))
29079 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29082 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29084 addressT imml
, immh
;
29086 immh
= (value
& 0x00000ffc) >> 2;
29087 imml
= (value
& 0x00000002) >> 1;
29089 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29090 newval
|= (imml
<< 11) | (immh
<< 1);
29091 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29095 case BFD_RELOC_ARM_V4BX
:
29096 /* This will need to go in the object file. */
29100 case BFD_RELOC_UNUSED
:
29102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29103 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29107 /* Translate internal representation of relocation info to BFD target
29111 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29114 bfd_reloc_code_real_type code
;
29116 reloc
= XNEW (arelent
);
29118 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29119 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29120 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29122 if (fixp
->fx_pcrel
)
29124 if (section
->use_rela_p
)
29125 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29127 fixp
->fx_offset
= reloc
->address
;
29129 reloc
->addend
= fixp
->fx_offset
;
29131 switch (fixp
->fx_r_type
)
29134 if (fixp
->fx_pcrel
)
29136 code
= BFD_RELOC_8_PCREL
;
29139 /* Fall through. */
29142 if (fixp
->fx_pcrel
)
29144 code
= BFD_RELOC_16_PCREL
;
29147 /* Fall through. */
29150 if (fixp
->fx_pcrel
)
29152 code
= BFD_RELOC_32_PCREL
;
29155 /* Fall through. */
29157 case BFD_RELOC_ARM_MOVW
:
29158 if (fixp
->fx_pcrel
)
29160 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29163 /* Fall through. */
29165 case BFD_RELOC_ARM_MOVT
:
29166 if (fixp
->fx_pcrel
)
29168 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29171 /* Fall through. */
29173 case BFD_RELOC_ARM_THUMB_MOVW
:
29174 if (fixp
->fx_pcrel
)
29176 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29179 /* Fall through. */
29181 case BFD_RELOC_ARM_THUMB_MOVT
:
29182 if (fixp
->fx_pcrel
)
29184 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29187 /* Fall through. */
29189 case BFD_RELOC_NONE
:
29190 case BFD_RELOC_ARM_PCREL_BRANCH
:
29191 case BFD_RELOC_ARM_PCREL_BLX
:
29192 case BFD_RELOC_RVA
:
29193 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29194 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29195 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29196 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29197 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29198 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29199 case BFD_RELOC_VTABLE_ENTRY
:
29200 case BFD_RELOC_VTABLE_INHERIT
:
29202 case BFD_RELOC_32_SECREL
:
29204 code
= fixp
->fx_r_type
;
29207 case BFD_RELOC_THUMB_PCREL_BLX
:
29209 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29210 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29213 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29216 case BFD_RELOC_ARM_LITERAL
:
29217 case BFD_RELOC_ARM_HWLITERAL
:
29218 /* If this is called then the a literal has
29219 been referenced across a section boundary. */
29220 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29221 _("literal referenced across section boundary"));
29225 case BFD_RELOC_ARM_TLS_CALL
:
29226 case BFD_RELOC_ARM_THM_TLS_CALL
:
29227 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29228 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29229 case BFD_RELOC_ARM_GOT32
:
29230 case BFD_RELOC_ARM_GOTOFF
:
29231 case BFD_RELOC_ARM_GOT_PREL
:
29232 case BFD_RELOC_ARM_PLT32
:
29233 case BFD_RELOC_ARM_TARGET1
:
29234 case BFD_RELOC_ARM_ROSEGREL32
:
29235 case BFD_RELOC_ARM_SBREL32
:
29236 case BFD_RELOC_ARM_PREL31
:
29237 case BFD_RELOC_ARM_TARGET2
:
29238 case BFD_RELOC_ARM_TLS_LDO32
:
29239 case BFD_RELOC_ARM_PCREL_CALL
:
29240 case BFD_RELOC_ARM_PCREL_JUMP
:
29241 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29242 case BFD_RELOC_ARM_ALU_PC_G0
:
29243 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29244 case BFD_RELOC_ARM_ALU_PC_G1
:
29245 case BFD_RELOC_ARM_ALU_PC_G2
:
29246 case BFD_RELOC_ARM_LDR_PC_G0
:
29247 case BFD_RELOC_ARM_LDR_PC_G1
:
29248 case BFD_RELOC_ARM_LDR_PC_G2
:
29249 case BFD_RELOC_ARM_LDRS_PC_G0
:
29250 case BFD_RELOC_ARM_LDRS_PC_G1
:
29251 case BFD_RELOC_ARM_LDRS_PC_G2
:
29252 case BFD_RELOC_ARM_LDC_PC_G0
:
29253 case BFD_RELOC_ARM_LDC_PC_G1
:
29254 case BFD_RELOC_ARM_LDC_PC_G2
:
29255 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29256 case BFD_RELOC_ARM_ALU_SB_G0
:
29257 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29258 case BFD_RELOC_ARM_ALU_SB_G1
:
29259 case BFD_RELOC_ARM_ALU_SB_G2
:
29260 case BFD_RELOC_ARM_LDR_SB_G0
:
29261 case BFD_RELOC_ARM_LDR_SB_G1
:
29262 case BFD_RELOC_ARM_LDR_SB_G2
:
29263 case BFD_RELOC_ARM_LDRS_SB_G0
:
29264 case BFD_RELOC_ARM_LDRS_SB_G1
:
29265 case BFD_RELOC_ARM_LDRS_SB_G2
:
29266 case BFD_RELOC_ARM_LDC_SB_G0
:
29267 case BFD_RELOC_ARM_LDC_SB_G1
:
29268 case BFD_RELOC_ARM_LDC_SB_G2
:
29269 case BFD_RELOC_ARM_V4BX
:
29270 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29271 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29272 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29273 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29274 case BFD_RELOC_ARM_GOTFUNCDESC
:
29275 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29276 case BFD_RELOC_ARM_FUNCDESC
:
29277 case BFD_RELOC_ARM_THUMB_BF17
:
29278 case BFD_RELOC_ARM_THUMB_BF19
:
29279 case BFD_RELOC_ARM_THUMB_BF13
:
29280 code
= fixp
->fx_r_type
;
29283 case BFD_RELOC_ARM_TLS_GOTDESC
:
29284 case BFD_RELOC_ARM_TLS_GD32
:
29285 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29286 case BFD_RELOC_ARM_TLS_LE32
:
29287 case BFD_RELOC_ARM_TLS_IE32
:
29288 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29289 case BFD_RELOC_ARM_TLS_LDM32
:
29290 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29291 /* BFD will include the symbol's address in the addend.
29292 But we don't want that, so subtract it out again here. */
29293 if (!S_IS_COMMON (fixp
->fx_addsy
))
29294 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29295 code
= fixp
->fx_r_type
;
29299 case BFD_RELOC_ARM_IMMEDIATE
:
29300 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29301 _("internal relocation (type: IMMEDIATE) not fixed up"));
29304 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29305 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29306 _("ADRL used for a symbol not defined in the same file"));
29309 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29310 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29311 case BFD_RELOC_ARM_THUMB_LOOP12
:
29312 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29313 _("%s used for a symbol not defined in the same file"),
29314 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29317 case BFD_RELOC_ARM_OFFSET_IMM
:
29318 if (section
->use_rela_p
)
29320 code
= fixp
->fx_r_type
;
29324 if (fixp
->fx_addsy
!= NULL
29325 && !S_IS_DEFINED (fixp
->fx_addsy
)
29326 && S_IS_LOCAL (fixp
->fx_addsy
))
29328 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29329 _("undefined local label `%s'"),
29330 S_GET_NAME (fixp
->fx_addsy
));
29334 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29335 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29342 switch (fixp
->fx_r_type
)
29344 case BFD_RELOC_NONE
: type
= "NONE"; break;
29345 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29346 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29347 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29348 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29349 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29350 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29351 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29352 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29353 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29354 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29355 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29356 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29357 default: type
= _("<unknown>"); break;
29359 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29360 _("cannot represent %s relocation in this object file format"),
29367 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29369 && fixp
->fx_addsy
== GOT_symbol
)
29371 code
= BFD_RELOC_ARM_GOTPC
;
29372 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29376 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29378 if (reloc
->howto
== NULL
)
29380 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29381 _("cannot represent %s relocation in this object file format"),
29382 bfd_get_reloc_code_name (code
));
29386 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29387 vtable entry to be used in the relocation's section offset. */
29388 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29389 reloc
->address
= fixp
->fx_offset
;
29394 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29397 cons_fix_new_arm (fragS
* frag
,
29401 bfd_reloc_code_real_type reloc
)
29406 FIXME: @@ Should look at CPU word size. */
29410 reloc
= BFD_RELOC_8
;
29413 reloc
= BFD_RELOC_16
;
29417 reloc
= BFD_RELOC_32
;
29420 reloc
= BFD_RELOC_64
;
29425 if (exp
->X_op
== O_secrel
)
29427 exp
->X_op
= O_symbol
;
29428 reloc
= BFD_RELOC_32_SECREL
;
29432 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29435 #if defined (OBJ_COFF)
29437 arm_validate_fix (fixS
* fixP
)
29439 /* If the destination of the branch is a defined symbol which does not have
29440 the THUMB_FUNC attribute, then we must be calling a function which has
29441 the (interfacearm) attribute. We look for the Thumb entry point to that
29442 function and change the branch to refer to that function instead. */
29443 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29444 && fixP
->fx_addsy
!= NULL
29445 && S_IS_DEFINED (fixP
->fx_addsy
)
29446 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29448 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29455 arm_force_relocation (struct fix
* fixp
)
29457 #if defined (OBJ_COFF) && defined (TE_PE)
29458 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29462 /* In case we have a call or a branch to a function in ARM ISA mode from
29463 a thumb function or vice-versa force the relocation. These relocations
29464 are cleared off for some cores that might have blx and simple transformations
29468 switch (fixp
->fx_r_type
)
29470 case BFD_RELOC_ARM_PCREL_JUMP
:
29471 case BFD_RELOC_ARM_PCREL_CALL
:
29472 case BFD_RELOC_THUMB_PCREL_BLX
:
29473 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29477 case BFD_RELOC_ARM_PCREL_BLX
:
29478 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29479 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29480 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29481 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29490 /* Resolve these relocations even if the symbol is extern or weak.
29491 Technically this is probably wrong due to symbol preemption.
29492 In practice these relocations do not have enough range to be useful
29493 at dynamic link time, and some code (e.g. in the Linux kernel)
29494 expects these references to be resolved. */
29495 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29496 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29497 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29498 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29499 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29500 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29501 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29502 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29503 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29504 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29505 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29506 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29507 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29508 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29511 /* Always leave these relocations for the linker. */
29512 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29513 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29514 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29517 /* Always generate relocations against function symbols. */
29518 if (fixp
->fx_r_type
== BFD_RELOC_32
29520 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29523 return generic_force_reloc (fixp
);
29526 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29527 /* Relocations against function names must be left unadjusted,
29528 so that the linker can use this information to generate interworking
29529 stubs. The MIPS version of this function
29530 also prevents relocations that are mips-16 specific, but I do not
29531 know why it does this.
29534 There is one other problem that ought to be addressed here, but
29535 which currently is not: Taking the address of a label (rather
29536 than a function) and then later jumping to that address. Such
29537 addresses also ought to have their bottom bit set (assuming that
29538 they reside in Thumb code), but at the moment they will not. */
29541 arm_fix_adjustable (fixS
* fixP
)
29543 if (fixP
->fx_addsy
== NULL
)
29546 /* Preserve relocations against symbols with function type. */
29547 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29550 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29551 && fixP
->fx_subsy
== NULL
)
29554 /* We need the symbol name for the VTABLE entries. */
29555 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29556 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29559 /* Don't allow symbols to be discarded on GOT related relocs. */
29560 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29561 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29562 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29563 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29564 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29565 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29566 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29567 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29568 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29569 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29570 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29571 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29572 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29573 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29574 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29575 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29576 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29579 /* Similarly for group relocations. */
29580 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29581 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29582 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29585 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29586 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29587 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29588 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29589 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29590 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29591 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29592 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29593 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29596 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29597 offsets, so keep these symbols. */
29598 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29599 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29604 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29608 elf32_arm_target_format (void)
29611 return (target_big_endian
29612 ? "elf32-bigarm-symbian"
29613 : "elf32-littlearm-symbian");
29614 #elif defined (TE_VXWORKS)
29615 return (target_big_endian
29616 ? "elf32-bigarm-vxworks"
29617 : "elf32-littlearm-vxworks");
29618 #elif defined (TE_NACL)
29619 return (target_big_endian
29620 ? "elf32-bigarm-nacl"
29621 : "elf32-littlearm-nacl");
29625 if (target_big_endian
)
29626 return "elf32-bigarm-fdpic";
29628 return "elf32-littlearm-fdpic";
29632 if (target_big_endian
)
29633 return "elf32-bigarm";
29635 return "elf32-littlearm";
29641 armelf_frob_symbol (symbolS
* symp
,
29644 elf_frob_symbol (symp
, puntp
);
29648 /* MD interface: Finalization. */
29653 literal_pool
* pool
;
29655 /* Ensure that all the predication blocks are properly closed. */
29656 check_pred_blocks_finished ();
29658 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29660 /* Put it at the end of the relevant section. */
29661 subseg_set (pool
->section
, pool
->sub_section
);
29663 arm_elf_change_section ();
29670 /* Remove any excess mapping symbols generated for alignment frags in
29671 SEC. We may have created a mapping symbol before a zero byte
29672 alignment; remove it if there's a mapping symbol after the
29675 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29676 void *dummy ATTRIBUTE_UNUSED
)
29678 segment_info_type
*seginfo
= seg_info (sec
);
29681 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29684 for (fragp
= seginfo
->frchainP
->frch_root
;
29686 fragp
= fragp
->fr_next
)
29688 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29689 fragS
*next
= fragp
->fr_next
;
29691 /* Variable-sized frags have been converted to fixed size by
29692 this point. But if this was variable-sized to start with,
29693 there will be a fixed-size frag after it. So don't handle
29695 if (sym
== NULL
|| next
== NULL
)
29698 if (S_GET_VALUE (sym
) < next
->fr_address
)
29699 /* Not at the end of this frag. */
29701 know (S_GET_VALUE (sym
) == next
->fr_address
);
29705 if (next
->tc_frag_data
.first_map
!= NULL
)
29707 /* Next frag starts with a mapping symbol. Discard this
29709 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29713 if (next
->fr_next
== NULL
)
29715 /* This mapping symbol is at the end of the section. Discard
29717 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29718 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29722 /* As long as we have empty frags without any mapping symbols,
29724 /* If the next frag is non-empty and does not start with a
29725 mapping symbol, then this mapping symbol is required. */
29726 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29729 next
= next
->fr_next
;
29731 while (next
!= NULL
);
29736 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29740 arm_adjust_symtab (void)
29745 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29747 if (ARM_IS_THUMB (sym
))
29749 if (THUMB_IS_FUNC (sym
))
29751 /* Mark the symbol as a Thumb function. */
29752 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29753 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29754 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29756 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29757 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29759 as_bad (_("%s: unexpected function type: %d"),
29760 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29762 else switch (S_GET_STORAGE_CLASS (sym
))
29765 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29768 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29771 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29779 if (ARM_IS_INTERWORK (sym
))
29780 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29787 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29789 if (ARM_IS_THUMB (sym
))
29791 elf_symbol_type
* elf_sym
;
29793 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29794 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29796 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29797 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29799 /* If it's a .thumb_func, declare it as so,
29800 otherwise tag label as .code 16. */
29801 if (THUMB_IS_FUNC (sym
))
29802 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29803 ST_BRANCH_TO_THUMB
);
29804 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29805 elf_sym
->internal_elf_sym
.st_info
=
29806 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29811 /* Remove any overlapping mapping symbols generated by alignment frags. */
29812 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29813 /* Now do generic ELF adjustments. */
29814 elf_adjust_symtab ();
29818 /* MD interface: Initialization. */
29821 set_constant_flonums (void)
29825 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29826 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29830 /* Auto-select Thumb mode if it's the only available instruction set for the
29831 given architecture. */
29834 autoselect_thumb_from_cpu_variant (void)
29836 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29837 opcode_select (16);
29846 if ( (arm_ops_hsh
= hash_new ()) == NULL
29847 || (arm_cond_hsh
= hash_new ()) == NULL
29848 || (arm_vcond_hsh
= hash_new ()) == NULL
29849 || (arm_shift_hsh
= hash_new ()) == NULL
29850 || (arm_psr_hsh
= hash_new ()) == NULL
29851 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29852 || (arm_reg_hsh
= hash_new ()) == NULL
29853 || (arm_reloc_hsh
= hash_new ()) == NULL
29854 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29855 as_fatal (_("virtual memory exhausted"));
29857 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29858 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29859 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29860 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29861 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29862 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29863 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29864 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29865 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29866 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29867 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29868 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29869 (void *) (v7m_psrs
+ i
));
29870 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29871 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29873 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29875 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29876 (void *) (barrier_opt_names
+ i
));
29878 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29880 struct reloc_entry
* entry
= reloc_names
+ i
;
29882 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29883 /* This makes encode_branch() use the EABI versions of this relocation. */
29884 entry
->reloc
= BFD_RELOC_UNUSED
;
29886 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29890 set_constant_flonums ();
29892 /* Set the cpu variant based on the command-line options. We prefer
29893 -mcpu= over -march= if both are set (as for GCC); and we prefer
29894 -mfpu= over any other way of setting the floating point unit.
29895 Use of legacy options with new options are faulted. */
29898 if (mcpu_cpu_opt
|| march_cpu_opt
)
29899 as_bad (_("use of old and new-style options to set CPU type"));
29901 selected_arch
= *legacy_cpu
;
29903 else if (mcpu_cpu_opt
)
29905 selected_arch
= *mcpu_cpu_opt
;
29906 selected_ext
= *mcpu_ext_opt
;
29908 else if (march_cpu_opt
)
29910 selected_arch
= *march_cpu_opt
;
29911 selected_ext
= *march_ext_opt
;
29913 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29918 as_bad (_("use of old and new-style options to set FPU type"));
29920 selected_fpu
= *legacy_fpu
;
29923 selected_fpu
= *mfpu_opt
;
29926 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29927 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29928 /* Some environments specify a default FPU. If they don't, infer it
29929 from the processor. */
29931 selected_fpu
= *mcpu_fpu_opt
;
29932 else if (march_fpu_opt
)
29933 selected_fpu
= *march_fpu_opt
;
29935 selected_fpu
= fpu_default
;
29939 if (ARM_FEATURE_ZERO (selected_fpu
))
29941 if (!no_cpu_selected ())
29942 selected_fpu
= fpu_default
;
29944 selected_fpu
= fpu_arch_fpa
;
29948 if (ARM_FEATURE_ZERO (selected_arch
))
29950 selected_arch
= cpu_default
;
29951 selected_cpu
= selected_arch
;
29953 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29955 /* Autodection of feature mode: allow all features in cpu_variant but leave
29956 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29957 after all instruction have been processed and we can decide what CPU
29958 should be selected. */
29959 if (ARM_FEATURE_ZERO (selected_arch
))
29960 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29962 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29965 autoselect_thumb_from_cpu_variant ();
29967 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29969 #if defined OBJ_COFF || defined OBJ_ELF
29971 unsigned int flags
= 0;
29973 #if defined OBJ_ELF
29974 flags
= meabi_flags
;
29976 switch (meabi_flags
)
29978 case EF_ARM_EABI_UNKNOWN
:
29980 /* Set the flags in the private structure. */
29981 if (uses_apcs_26
) flags
|= F_APCS26
;
29982 if (support_interwork
) flags
|= F_INTERWORK
;
29983 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29984 if (pic_code
) flags
|= F_PIC
;
29985 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29986 flags
|= F_SOFT_FLOAT
;
29988 switch (mfloat_abi_opt
)
29990 case ARM_FLOAT_ABI_SOFT
:
29991 case ARM_FLOAT_ABI_SOFTFP
:
29992 flags
|= F_SOFT_FLOAT
;
29995 case ARM_FLOAT_ABI_HARD
:
29996 if (flags
& F_SOFT_FLOAT
)
29997 as_bad (_("hard-float conflicts with specified fpu"));
30001 /* Using pure-endian doubles (even if soft-float). */
30002 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30003 flags
|= F_VFP_FLOAT
;
30005 #if defined OBJ_ELF
30006 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30007 flags
|= EF_ARM_MAVERICK_FLOAT
;
30010 case EF_ARM_EABI_VER4
:
30011 case EF_ARM_EABI_VER5
:
30012 /* No additional flags to set. */
30019 bfd_set_private_flags (stdoutput
, flags
);
30021 /* We have run out flags in the COFF header to encode the
30022 status of ATPCS support, so instead we create a dummy,
30023 empty, debug section called .arm.atpcs. */
30028 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30032 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30033 bfd_set_section_size (sec
, 0);
30034 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30040 /* Record the CPU type as well. */
30041 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30042 mach
= bfd_mach_arm_iWMMXt2
;
30043 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30044 mach
= bfd_mach_arm_iWMMXt
;
30045 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30046 mach
= bfd_mach_arm_XScale
;
30047 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30048 mach
= bfd_mach_arm_ep9312
;
30049 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30050 mach
= bfd_mach_arm_5TE
;
30051 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30053 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30054 mach
= bfd_mach_arm_5T
;
30056 mach
= bfd_mach_arm_5
;
30058 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30060 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30061 mach
= bfd_mach_arm_4T
;
30063 mach
= bfd_mach_arm_4
;
30065 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30066 mach
= bfd_mach_arm_3M
;
30067 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30068 mach
= bfd_mach_arm_3
;
30069 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30070 mach
= bfd_mach_arm_2a
;
30071 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30072 mach
= bfd_mach_arm_2
;
30074 mach
= bfd_mach_arm_unknown
;
30076 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30079 /* Command line processing. */
30082 Invocation line includes a switch not recognized by the base assembler.
30083 See if it's a processor-specific option.
30085 This routine is somewhat complicated by the need for backwards
30086 compatibility (since older releases of gcc can't be changed).
30087 The new options try to make the interface as compatible as
30090 New options (supported) are:
30092 -mcpu=<cpu name> Assemble for selected processor
30093 -march=<architecture name> Assemble for selected architecture
30094 -mfpu=<fpu architecture> Assemble for selected FPU.
30095 -EB/-mbig-endian Big-endian
30096 -EL/-mlittle-endian Little-endian
30097 -k Generate PIC code
30098 -mthumb Start in Thumb mode
30099 -mthumb-interwork Code supports ARM/Thumb interworking
30101 -m[no-]warn-deprecated Warn about deprecated features
30102 -m[no-]warn-syms Warn when symbols match instructions
30104 For now we will also provide support for:
30106 -mapcs-32 32-bit Program counter
30107 -mapcs-26 26-bit Program counter
30108 -macps-float Floats passed in FP registers
30109 -mapcs-reentrant Reentrant code
30111 (sometime these will probably be replaced with -mapcs=<list of options>
30112 and -matpcs=<list of options>)
30114 The remaining options are only supported for back-wards compatibility.
30115 Cpu variants, the arm part is optional:
30116 -m[arm]1 Currently not supported.
30117 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30118 -m[arm]3 Arm 3 processor
30119 -m[arm]6[xx], Arm 6 processors
30120 -m[arm]7[xx][t][[d]m] Arm 7 processors
30121 -m[arm]8[10] Arm 8 processors
30122 -m[arm]9[20][tdmi] Arm 9 processors
30123 -mstrongarm[110[0]] StrongARM processors
30124 -mxscale XScale processors
30125 -m[arm]v[2345[t[e]]] Arm architectures
30126 -mall All (except the ARM1)
30128 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30129 -mfpe-old (No float load/store multiples)
30130 -mvfpxd VFP Single precision
30132 -mno-fpu Disable all floating point instructions
30134 The following CPU names are recognized:
30135 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30136 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30137 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30138 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30139 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30140 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30141 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30145 const char * md_shortopts
= "m:k";
30147 #ifdef ARM_BI_ENDIAN
30148 #define OPTION_EB (OPTION_MD_BASE + 0)
30149 #define OPTION_EL (OPTION_MD_BASE + 1)
30151 #if TARGET_BYTES_BIG_ENDIAN
30152 #define OPTION_EB (OPTION_MD_BASE + 0)
30154 #define OPTION_EL (OPTION_MD_BASE + 1)
30157 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30158 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30160 struct option md_longopts
[] =
30163 {"EB", no_argument
, NULL
, OPTION_EB
},
30166 {"EL", no_argument
, NULL
, OPTION_EL
},
30168 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30170 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30172 {NULL
, no_argument
, NULL
, 0}
30175 size_t md_longopts_size
= sizeof (md_longopts
);
30177 struct arm_option_table
30179 const char * option
; /* Option name to match. */
30180 const char * help
; /* Help information. */
30181 int * var
; /* Variable to change. */
30182 int value
; /* What to change it to. */
30183 const char * deprecated
; /* If non-null, print this message. */
30186 struct arm_option_table arm_opts
[] =
30188 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30189 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30190 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30191 &support_interwork
, 1, NULL
},
30192 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30193 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30194 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30196 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30197 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30198 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30199 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30202 /* These are recognized by the assembler, but have no affect on code. */
30203 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30204 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30206 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30207 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30208 &warn_on_deprecated
, 0, NULL
},
30209 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30210 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30211 {NULL
, NULL
, NULL
, 0, NULL
}
30214 struct arm_legacy_option_table
30216 const char * option
; /* Option name to match. */
30217 const arm_feature_set
** var
; /* Variable to change. */
30218 const arm_feature_set value
; /* What to change it to. */
30219 const char * deprecated
; /* If non-null, print this message. */
30222 const struct arm_legacy_option_table arm_legacy_opts
[] =
30224 /* DON'T add any new processors to this list -- we want the whole list
30225 to go away... Add them to the processors table instead. */
30226 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30227 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30228 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30229 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30230 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30231 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30232 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30233 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30234 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30235 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30236 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30237 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30238 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30239 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30240 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30241 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30242 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30243 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30244 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30245 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30246 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30247 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30248 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30249 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30250 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30251 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30252 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30253 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30254 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30255 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30256 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30257 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30258 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30259 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30260 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30261 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30262 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30263 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30264 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30265 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30266 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30267 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30268 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30269 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30270 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30271 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30272 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30273 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30274 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30275 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30276 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30277 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30278 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30279 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30280 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30281 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30282 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30283 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30284 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30285 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30286 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30287 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30288 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30289 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30290 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30291 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30292 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30293 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30294 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30295 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30296 N_("use -mcpu=strongarm110")},
30297 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30298 N_("use -mcpu=strongarm1100")},
30299 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30300 N_("use -mcpu=strongarm1110")},
30301 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30302 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30303 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30305 /* Architecture variants -- don't add any more to this list either. */
30306 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30307 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30308 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30309 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30310 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30311 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30312 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30313 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30314 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30315 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30316 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30317 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30318 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30319 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30320 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30321 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30322 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30323 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30325 /* Floating point variants -- don't add any more to this list either. */
30326 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30327 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30328 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30329 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30330 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30332 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30335 struct arm_cpu_option_table
30339 const arm_feature_set value
;
30340 const arm_feature_set ext
;
30341 /* For some CPUs we assume an FPU unless the user explicitly sets
30343 const arm_feature_set default_fpu
;
30344 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30346 const char * canonical_name
;
30349 /* This list should, at a minimum, contain all the cpu names
30350 recognized by GCC. */
30351 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30353 static const struct arm_cpu_option_table arm_cpus
[] =
30355 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30358 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30361 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30364 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30367 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30370 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30373 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30376 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30379 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30382 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30385 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30388 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30391 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30394 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30397 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30400 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30403 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30406 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30409 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30412 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30415 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30418 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30421 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30424 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30427 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30430 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30433 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30436 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30439 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30442 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30445 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30448 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30451 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30454 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30457 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30460 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30463 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30466 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30469 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30472 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30475 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30478 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30481 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30484 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30487 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30490 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30494 /* For V5 or later processors we default to using VFP; but the user
30495 should really set the FPU type explicitly. */
30496 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30499 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30502 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30505 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30508 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30511 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30514 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30517 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30520 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30523 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30526 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30529 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30532 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30535 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30538 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30541 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30544 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30547 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30550 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30553 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30556 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30559 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30562 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30565 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30568 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30571 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30574 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30577 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30580 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30583 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30586 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30589 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30592 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30595 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30598 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30601 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30604 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30605 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30607 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30609 FPU_ARCH_NEON_VFP_V4
),
30610 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30611 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30612 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30613 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30614 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30615 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30616 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30618 FPU_ARCH_NEON_VFP_V4
),
30619 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30621 FPU_ARCH_NEON_VFP_V4
),
30622 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30624 FPU_ARCH_NEON_VFP_V4
),
30625 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30626 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30627 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30628 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30629 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30630 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30631 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30632 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30633 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30634 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30635 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30636 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30637 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30638 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30639 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30640 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30641 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30642 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30643 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30644 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30645 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30646 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30647 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30648 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30649 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30650 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30651 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30652 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
30653 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30654 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30655 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
30656 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30657 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30658 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30659 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30660 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30661 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30664 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30666 FPU_ARCH_VFP_V3D16
),
30667 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30668 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30670 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30671 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30672 FPU_ARCH_VFP_V3D16
),
30673 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30674 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30675 FPU_ARCH_VFP_V3D16
),
30676 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30677 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30678 FPU_ARCH_NEON_VFP_ARMV8
),
30679 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
30680 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30682 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30683 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30685 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30688 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30691 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30694 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30697 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30700 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30703 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30706 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30707 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30708 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30709 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30710 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30711 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30712 /* ??? XSCALE is really an architecture. */
30713 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30717 /* ??? iwmmxt is not a processor. */
30718 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30721 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30724 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30729 ARM_CPU_OPT ("ep9312", "ARM920T",
30730 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30731 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30733 /* Marvell processors. */
30734 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30735 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30736 FPU_ARCH_VFP_V3D16
),
30737 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30738 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30739 FPU_ARCH_NEON_VFP_V4
),
30741 /* APM X-Gene family. */
30742 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30744 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30745 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30746 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30747 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30749 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30753 struct arm_ext_table
30757 const arm_feature_set merge
;
30758 const arm_feature_set clear
;
30761 struct arm_arch_option_table
30765 const arm_feature_set value
;
30766 const arm_feature_set default_fpu
;
30767 const struct arm_ext_table
* ext_table
;
30770 /* Used to add support for +E and +noE extension. */
30771 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30772 /* Used to add support for a +E extension. */
30773 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30774 /* Used to add support for a +noE extension. */
30775 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30777 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30778 ~0 & ~FPU_ENDIAN_PURE)
30780 static const struct arm_ext_table armv5te_ext_table
[] =
30782 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30783 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30786 static const struct arm_ext_table armv7_ext_table
[] =
30788 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30789 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30792 static const struct arm_ext_table armv7ve_ext_table
[] =
30794 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30795 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30796 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30797 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30798 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30799 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30800 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30802 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30803 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30805 /* Aliases for +simd. */
30806 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30808 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30809 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30810 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30812 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30815 static const struct arm_ext_table armv7a_ext_table
[] =
30817 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30818 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30819 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30820 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30821 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30822 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30823 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30825 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30826 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30828 /* Aliases for +simd. */
30829 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30830 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30832 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30833 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30835 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30836 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30837 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30840 static const struct arm_ext_table armv7r_ext_table
[] =
30842 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30843 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30844 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30845 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30846 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30847 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30848 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30849 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30850 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30853 static const struct arm_ext_table armv7em_ext_table
[] =
30855 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30856 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30857 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30858 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30859 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30860 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30861 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30864 static const struct arm_ext_table armv8a_ext_table
[] =
30866 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30867 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30868 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30869 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30871 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30872 should use the +simd option to turn on FP. */
30873 ARM_REMOVE ("fp", ALL_FP
),
30874 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30875 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30876 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30880 static const struct arm_ext_table armv81a_ext_table
[] =
30882 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30883 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30884 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30886 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30887 should use the +simd option to turn on FP. */
30888 ARM_REMOVE ("fp", ALL_FP
),
30889 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30890 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30891 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30894 static const struct arm_ext_table armv82a_ext_table
[] =
30896 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30897 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30898 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30899 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30900 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30901 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30903 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30904 should use the +simd option to turn on FP. */
30905 ARM_REMOVE ("fp", ALL_FP
),
30906 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30907 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30908 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30911 static const struct arm_ext_table armv84a_ext_table
[] =
30913 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30914 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30915 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30916 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30918 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30919 should use the +simd option to turn on FP. */
30920 ARM_REMOVE ("fp", ALL_FP
),
30921 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30922 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30923 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30926 static const struct arm_ext_table armv85a_ext_table
[] =
30928 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30929 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30930 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30931 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30933 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30934 should use the +simd option to turn on FP. */
30935 ARM_REMOVE ("fp", ALL_FP
),
30936 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30939 static const struct arm_ext_table armv8m_main_ext_table
[] =
30941 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30942 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30943 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30944 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30945 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30948 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30950 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30951 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30953 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30954 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30957 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30958 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30959 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30960 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30962 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30963 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30964 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30965 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30968 static const struct arm_ext_table armv8r_ext_table
[] =
30970 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30971 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30972 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30973 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30974 ARM_REMOVE ("fp", ALL_FP
),
30975 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30976 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30979 /* This list should, at a minimum, contain all the architecture names
30980 recognized by GCC. */
30981 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30982 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30983 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30985 static const struct arm_arch_option_table arm_archs
[] =
30987 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30988 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30989 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30990 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30991 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30992 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30993 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30994 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30995 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30996 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30997 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30998 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30999 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31000 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31001 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31002 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31003 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31004 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31005 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31006 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31007 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31008 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31009 kept to preserve existing behaviour. */
31010 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31011 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31012 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31013 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31014 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31015 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31016 kept to preserve existing behaviour. */
31017 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31018 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31019 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31020 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31021 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31022 /* The official spelling of the ARMv7 profile variants is the dashed form.
31023 Accept the non-dashed form for compatibility with old toolchains. */
31024 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31025 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31026 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31027 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31028 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31029 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31030 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31031 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31032 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31033 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31035 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31037 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31038 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31039 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31040 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31041 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31042 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31043 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31044 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31045 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31046 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31047 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31049 #undef ARM_ARCH_OPT
31051 /* ISA extensions in the co-processor and main instruction set space. */
31053 struct arm_option_extension_value_table
31057 const arm_feature_set merge_value
;
31058 const arm_feature_set clear_value
;
31059 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31060 indicates that an extension is available for all architectures while
31061 ARM_ANY marks an empty entry. */
31062 const arm_feature_set allowed_archs
[2];
31065 /* The following table must be in alphabetical order with a NULL last entry. */
31067 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31068 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31070 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31071 use the context sensitive approach using arm_ext_table's. */
31072 static const struct arm_option_extension_value_table arm_extensions
[] =
31074 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31075 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31076 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31077 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31078 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31079 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31080 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31082 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31083 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31084 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31085 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31086 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31087 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31088 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31090 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31091 | ARM_EXT2_FP16_FML
),
31092 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31093 | ARM_EXT2_FP16_FML
),
31095 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31096 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31097 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31098 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31099 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31100 Thumb divide instruction. Due to this having the same name as the
31101 previous entry, this will be ignored when doing command-line parsing and
31102 only considered by build attribute selection code. */
31103 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31104 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31105 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31106 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31107 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31108 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31109 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31110 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31111 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31112 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31113 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31114 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31115 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31116 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31117 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31118 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31119 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31120 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31121 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31122 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31123 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31125 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31126 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31127 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31128 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31129 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31130 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31131 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31132 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31134 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31135 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31136 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31137 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31138 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31139 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31140 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31141 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31143 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31144 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31145 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31146 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31147 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31151 /* ISA floating-point and Advanced SIMD extensions. */
31152 struct arm_option_fpu_value_table
31155 const arm_feature_set value
;
31158 /* This list should, at a minimum, contain all the fpu names
31159 recognized by GCC. */
31160 static const struct arm_option_fpu_value_table arm_fpus
[] =
31162 {"softfpa", FPU_NONE
},
31163 {"fpe", FPU_ARCH_FPE
},
31164 {"fpe2", FPU_ARCH_FPE
},
31165 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31166 {"fpa", FPU_ARCH_FPA
},
31167 {"fpa10", FPU_ARCH_FPA
},
31168 {"fpa11", FPU_ARCH_FPA
},
31169 {"arm7500fe", FPU_ARCH_FPA
},
31170 {"softvfp", FPU_ARCH_VFP
},
31171 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31172 {"vfp", FPU_ARCH_VFP_V2
},
31173 {"vfp9", FPU_ARCH_VFP_V2
},
31174 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31175 {"vfp10", FPU_ARCH_VFP_V2
},
31176 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31177 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31178 {"vfpv2", FPU_ARCH_VFP_V2
},
31179 {"vfpv3", FPU_ARCH_VFP_V3
},
31180 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31181 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31182 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31183 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31184 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31185 {"arm1020t", FPU_ARCH_VFP_V1
},
31186 {"arm1020e", FPU_ARCH_VFP_V2
},
31187 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31188 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31189 {"maverick", FPU_ARCH_MAVERICK
},
31190 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31191 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31192 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31193 {"vfpv4", FPU_ARCH_VFP_V4
},
31194 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31195 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31196 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31197 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31198 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31199 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31200 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31201 {"crypto-neon-fp-armv8",
31202 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31203 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31204 {"crypto-neon-fp-armv8.1",
31205 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31206 {NULL
, ARM_ARCH_NONE
}
31209 struct arm_option_value_table
31215 static const struct arm_option_value_table arm_float_abis
[] =
31217 {"hard", ARM_FLOAT_ABI_HARD
},
31218 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31219 {"soft", ARM_FLOAT_ABI_SOFT
},
31224 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31225 static const struct arm_option_value_table arm_eabis
[] =
31227 {"gnu", EF_ARM_EABI_UNKNOWN
},
31228 {"4", EF_ARM_EABI_VER4
},
31229 {"5", EF_ARM_EABI_VER5
},
31234 struct arm_long_option_table
31236 const char * option
; /* Substring to match. */
31237 const char * help
; /* Help information. */
31238 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31239 const char * deprecated
; /* If non-null, print this message. */
31243 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31244 arm_feature_set
*ext_set
,
31245 const struct arm_ext_table
*ext_table
)
31247 /* We insist on extensions being specified in alphabetical order, and with
31248 extensions being added before being removed. We achieve this by having
31249 the global ARM_EXTENSIONS table in alphabetical order, and using the
31250 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31251 or removing it (0) and only allowing it to change in the order
31253 const struct arm_option_extension_value_table
* opt
= NULL
;
31254 const arm_feature_set arm_any
= ARM_ANY
;
31255 int adding_value
= -1;
31257 while (str
!= NULL
&& *str
!= 0)
31264 as_bad (_("invalid architectural extension"));
31269 ext
= strchr (str
, '+');
31274 len
= strlen (str
);
31276 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31278 if (adding_value
!= 0)
31281 opt
= arm_extensions
;
31289 if (adding_value
== -1)
31292 opt
= arm_extensions
;
31294 else if (adding_value
!= 1)
31296 as_bad (_("must specify extensions to add before specifying "
31297 "those to remove"));
31304 as_bad (_("missing architectural extension"));
31308 gas_assert (adding_value
!= -1);
31309 gas_assert (opt
!= NULL
);
31311 if (ext_table
!= NULL
)
31313 const struct arm_ext_table
* ext_opt
= ext_table
;
31314 bfd_boolean found
= FALSE
;
31315 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31316 if (ext_opt
->name_len
== len
31317 && strncmp (ext_opt
->name
, str
, len
) == 0)
31321 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31322 /* TODO: Option not supported. When we remove the
31323 legacy table this case should error out. */
31326 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31330 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31331 /* TODO: Option not supported. When we remove the
31332 legacy table this case should error out. */
31334 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31346 /* Scan over the options table trying to find an exact match. */
31347 for (; opt
->name
!= NULL
; opt
++)
31348 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31350 int i
, nb_allowed_archs
=
31351 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31352 /* Check we can apply the extension to this architecture. */
31353 for (i
= 0; i
< nb_allowed_archs
; i
++)
31356 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31358 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31361 if (i
== nb_allowed_archs
)
31363 as_bad (_("extension does not apply to the base architecture"));
31367 /* Add or remove the extension. */
31369 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31371 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31373 /* Allowing Thumb division instructions for ARMv7 in autodetection
31374 rely on this break so that duplicate extensions (extensions
31375 with the same name as a previous extension in the list) are not
31376 considered for command-line parsing. */
31380 if (opt
->name
== NULL
)
31382 /* Did we fail to find an extension because it wasn't specified in
31383 alphabetical order, or because it does not exist? */
31385 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31386 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31389 if (opt
->name
== NULL
)
31390 as_bad (_("unknown architectural extension `%s'"), str
);
31392 as_bad (_("architectural extensions must be specified in "
31393 "alphabetical order"));
31399 /* We should skip the extension we've just matched the next time
31411 arm_parse_fp16_opt (const char *str
)
31413 if (strcasecmp (str
, "ieee") == 0)
31414 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31415 else if (strcasecmp (str
, "alternative") == 0)
31416 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31419 as_bad (_("unrecognised float16 format \"%s\""), str
);
31427 arm_parse_cpu (const char *str
)
31429 const struct arm_cpu_option_table
*opt
;
31430 const char *ext
= strchr (str
, '+');
31436 len
= strlen (str
);
31440 as_bad (_("missing cpu name `%s'"), str
);
31444 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31445 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31447 mcpu_cpu_opt
= &opt
->value
;
31448 if (mcpu_ext_opt
== NULL
)
31449 mcpu_ext_opt
= XNEW (arm_feature_set
);
31450 *mcpu_ext_opt
= opt
->ext
;
31451 mcpu_fpu_opt
= &opt
->default_fpu
;
31452 if (opt
->canonical_name
)
31454 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31455 strcpy (selected_cpu_name
, opt
->canonical_name
);
31461 if (len
>= sizeof selected_cpu_name
)
31462 len
= (sizeof selected_cpu_name
) - 1;
31464 for (i
= 0; i
< len
; i
++)
31465 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31466 selected_cpu_name
[i
] = 0;
31470 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31475 as_bad (_("unknown cpu `%s'"), str
);
31480 arm_parse_arch (const char *str
)
31482 const struct arm_arch_option_table
*opt
;
31483 const char *ext
= strchr (str
, '+');
31489 len
= strlen (str
);
31493 as_bad (_("missing architecture name `%s'"), str
);
31497 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31498 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31500 march_cpu_opt
= &opt
->value
;
31501 if (march_ext_opt
== NULL
)
31502 march_ext_opt
= XNEW (arm_feature_set
);
31503 *march_ext_opt
= arm_arch_none
;
31504 march_fpu_opt
= &opt
->default_fpu
;
31505 strcpy (selected_cpu_name
, opt
->name
);
31508 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31514 as_bad (_("unknown architecture `%s'\n"), str
);
31519 arm_parse_fpu (const char * str
)
31521 const struct arm_option_fpu_value_table
* opt
;
31523 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31524 if (streq (opt
->name
, str
))
31526 mfpu_opt
= &opt
->value
;
31530 as_bad (_("unknown floating point format `%s'\n"), str
);
31535 arm_parse_float_abi (const char * str
)
31537 const struct arm_option_value_table
* opt
;
31539 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31540 if (streq (opt
->name
, str
))
31542 mfloat_abi_opt
= opt
->value
;
31546 as_bad (_("unknown floating point abi `%s'\n"), str
);
31552 arm_parse_eabi (const char * str
)
31554 const struct arm_option_value_table
*opt
;
31556 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31557 if (streq (opt
->name
, str
))
31559 meabi_flags
= opt
->value
;
31562 as_bad (_("unknown EABI `%s'\n"), str
);
31568 arm_parse_it_mode (const char * str
)
31570 bfd_boolean ret
= TRUE
;
31572 if (streq ("arm", str
))
31573 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31574 else if (streq ("thumb", str
))
31575 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31576 else if (streq ("always", str
))
31577 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31578 else if (streq ("never", str
))
31579 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31582 as_bad (_("unknown implicit IT mode `%s', should be "\
31583 "arm, thumb, always, or never."), str
);
31591 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31593 codecomposer_syntax
= TRUE
;
31594 arm_comment_chars
[0] = ';';
31595 arm_line_separator_chars
[0] = 0;
31599 struct arm_long_option_table arm_long_opts
[] =
31601 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31602 arm_parse_cpu
, NULL
},
31603 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31604 arm_parse_arch
, NULL
},
31605 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31606 arm_parse_fpu
, NULL
},
31607 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31608 arm_parse_float_abi
, NULL
},
31610 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31611 arm_parse_eabi
, NULL
},
31613 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31614 arm_parse_it_mode
, NULL
},
31615 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31616 arm_ccs_mode
, NULL
},
31618 N_("[ieee|alternative]\n\
31619 set the encoding for half precision floating point "
31620 "numbers to IEEE\n\
31621 or Arm alternative format."),
31622 arm_parse_fp16_opt
, NULL
},
31623 {NULL
, NULL
, 0, NULL
}
31627 md_parse_option (int c
, const char * arg
)
31629 struct arm_option_table
*opt
;
31630 const struct arm_legacy_option_table
*fopt
;
31631 struct arm_long_option_table
*lopt
;
31637 target_big_endian
= 1;
31643 target_big_endian
= 0;
31647 case OPTION_FIX_V4BX
:
31655 #endif /* OBJ_ELF */
31658 /* Listing option. Just ignore these, we don't support additional
31663 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31665 if (c
== opt
->option
[0]
31666 && ((arg
== NULL
&& opt
->option
[1] == 0)
31667 || streq (arg
, opt
->option
+ 1)))
31669 /* If the option is deprecated, tell the user. */
31670 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31671 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31672 arg
? arg
: "", _(opt
->deprecated
));
31674 if (opt
->var
!= NULL
)
31675 *opt
->var
= opt
->value
;
31681 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31683 if (c
== fopt
->option
[0]
31684 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31685 || streq (arg
, fopt
->option
+ 1)))
31687 /* If the option is deprecated, tell the user. */
31688 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31689 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31690 arg
? arg
: "", _(fopt
->deprecated
));
31692 if (fopt
->var
!= NULL
)
31693 *fopt
->var
= &fopt
->value
;
31699 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31701 /* These options are expected to have an argument. */
31702 if (c
== lopt
->option
[0]
31704 && strncmp (arg
, lopt
->option
+ 1,
31705 strlen (lopt
->option
+ 1)) == 0)
31707 /* If the option is deprecated, tell the user. */
31708 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31709 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31710 _(lopt
->deprecated
));
31712 /* Call the sup-option parser. */
31713 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31724 md_show_usage (FILE * fp
)
31726 struct arm_option_table
*opt
;
31727 struct arm_long_option_table
*lopt
;
31729 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31731 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31732 if (opt
->help
!= NULL
)
31733 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31735 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31736 if (lopt
->help
!= NULL
)
31737 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31741 -EB assemble code for a big-endian cpu\n"));
31746 -EL assemble code for a little-endian cpu\n"));
31750 --fix-v4bx Allow BX in ARMv4 code\n"));
31754 --fdpic generate an FDPIC object file\n"));
31755 #endif /* OBJ_ELF */
31763 arm_feature_set flags
;
31764 } cpu_arch_ver_table
;
31766 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31767 chronologically for architectures, with an exception for ARMv6-M and
31768 ARMv6S-M due to legacy reasons. No new architecture should have a
31769 special case. This allows for build attribute selection results to be
31770 stable when new architectures are added. */
31771 static const cpu_arch_ver_table cpu_arch_ver
[] =
31773 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31774 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31775 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31776 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31777 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31778 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31779 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31780 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31781 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31782 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31783 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31784 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31785 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31786 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31787 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31788 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31789 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31790 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31791 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31792 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31793 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31794 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31795 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31796 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31798 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31799 always selected build attributes to match those of ARMv6-M
31800 (resp. ARMv6S-M). However, due to these architectures being a strict
31801 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31802 would be selected when fully respecting chronology of architectures.
31803 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31804 move them before ARMv7 architectures. */
31805 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31806 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31808 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31809 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31810 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31811 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31812 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31813 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31814 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31815 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31816 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31817 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31818 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31819 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31820 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31821 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31822 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31823 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31824 {-1, ARM_ARCH_NONE
}
31827 /* Set an attribute if it has not already been set by the user. */
31830 aeabi_set_attribute_int (int tag
, int value
)
31833 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31834 || !attributes_set_explicitly
[tag
])
31835 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31839 aeabi_set_attribute_string (int tag
, const char *value
)
31842 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31843 || !attributes_set_explicitly
[tag
])
31844 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31847 /* Return whether features in the *NEEDED feature set are available via
31848 extensions for the architecture whose feature set is *ARCH_FSET. */
31851 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31852 const arm_feature_set
*needed
)
31854 int i
, nb_allowed_archs
;
31855 arm_feature_set ext_fset
;
31856 const struct arm_option_extension_value_table
*opt
;
31858 ext_fset
= arm_arch_none
;
31859 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31861 /* Extension does not provide any feature we need. */
31862 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31866 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31867 for (i
= 0; i
< nb_allowed_archs
; i
++)
31870 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31873 /* Extension is available, add it. */
31874 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31875 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31879 /* Can we enable all features in *needed? */
31880 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31883 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31884 a given architecture feature set *ARCH_EXT_FSET including extension feature
31885 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31886 - if true, check for an exact match of the architecture modulo extensions;
31887 - otherwise, select build attribute value of the first superset
31888 architecture released so that results remains stable when new architectures
31890 For -march/-mcpu=all the build attribute value of the most featureful
31891 architecture is returned. Tag_CPU_arch_profile result is returned in
31895 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31896 const arm_feature_set
*ext_fset
,
31897 char *profile
, int exact_match
)
31899 arm_feature_set arch_fset
;
31900 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31902 /* Select most featureful architecture with all its extensions if building
31903 for -march=all as the feature sets used to set build attributes. */
31904 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31906 /* Force revisiting of decision for each new architecture. */
31907 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31909 return TAG_CPU_ARCH_V8
;
31912 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31914 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31916 arm_feature_set known_arch_fset
;
31918 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31921 /* Base architecture match user-specified architecture and
31922 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31923 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31928 /* Base architecture match user-specified architecture only
31929 (eg. ARMv6-M in the same case as above). Record it in case we
31930 find a match with above condition. */
31931 else if (p_ver_ret
== NULL
31932 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31938 /* Architecture has all features wanted. */
31939 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31941 arm_feature_set added_fset
;
31943 /* Compute features added by this architecture over the one
31944 recorded in p_ver_ret. */
31945 if (p_ver_ret
!= NULL
)
31946 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31948 /* First architecture that match incl. with extensions, or the
31949 only difference in features over the recorded match is
31950 features that were optional and are now mandatory. */
31951 if (p_ver_ret
== NULL
31952 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31958 else if (p_ver_ret
== NULL
)
31960 arm_feature_set needed_ext_fset
;
31962 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31964 /* Architecture has all features needed when using some
31965 extensions. Record it and continue searching in case there
31966 exist an architecture providing all needed features without
31967 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31969 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31976 if (p_ver_ret
== NULL
)
31980 /* Tag_CPU_arch_profile. */
31981 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31982 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31983 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31984 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31986 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31988 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31992 return p_ver_ret
->val
;
31995 /* Set the public EABI object attributes. */
31998 aeabi_set_public_attributes (void)
32000 char profile
= '\0';
32003 int fp16_optional
= 0;
32004 int skip_exact_match
= 0;
32005 arm_feature_set flags
, flags_arch
, flags_ext
;
32007 /* Autodetection mode, choose the architecture based the instructions
32009 if (no_cpu_selected ())
32011 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32013 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32014 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32016 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32017 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32019 /* Code run during relaxation relies on selected_cpu being set. */
32020 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32021 flags_ext
= arm_arch_none
;
32022 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32023 selected_ext
= flags_ext
;
32024 selected_cpu
= flags
;
32026 /* Otherwise, choose the architecture based on the capabilities of the
32030 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32031 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32032 flags_ext
= selected_ext
;
32033 flags
= selected_cpu
;
32035 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32037 /* Allow the user to override the reported architecture. */
32038 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32040 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32041 flags_ext
= arm_arch_none
;
32044 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32046 /* When this function is run again after relaxation has happened there is no
32047 way to determine whether an architecture or CPU was specified by the user:
32048 - selected_cpu is set above for relaxation to work;
32049 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32050 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32051 Therefore, if not in -march=all case we first try an exact match and fall
32052 back to autodetection. */
32053 if (!skip_exact_match
)
32054 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32056 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32058 as_bad (_("no architecture contains all the instructions used\n"));
32060 /* Tag_CPU_name. */
32061 if (selected_cpu_name
[0])
32065 q
= selected_cpu_name
;
32066 if (strncmp (q
, "armv", 4) == 0)
32071 for (i
= 0; q
[i
]; i
++)
32072 q
[i
] = TOUPPER (q
[i
]);
32074 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32077 /* Tag_CPU_arch. */
32078 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32080 /* Tag_CPU_arch_profile. */
32081 if (profile
!= '\0')
32082 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32084 /* Tag_DSP_extension. */
32085 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32086 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32088 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32089 /* Tag_ARM_ISA_use. */
32090 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32091 || ARM_FEATURE_ZERO (flags_arch
))
32092 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32094 /* Tag_THUMB_ISA_use. */
32095 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32096 || ARM_FEATURE_ZERO (flags_arch
))
32100 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32101 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32103 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32107 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32110 /* Tag_VFP_arch. */
32111 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32112 aeabi_set_attribute_int (Tag_VFP_arch
,
32113 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32115 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32116 aeabi_set_attribute_int (Tag_VFP_arch
,
32117 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32119 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32122 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32124 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32126 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32129 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32130 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32131 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32132 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32133 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32135 /* Tag_ABI_HardFP_use. */
32136 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32137 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32138 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32140 /* Tag_WMMX_arch. */
32141 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32142 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32143 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32144 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32146 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32147 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32148 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32149 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32150 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32151 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32153 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32155 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32159 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32164 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32165 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32166 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32167 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32169 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32170 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32171 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32175 We set Tag_DIV_use to two when integer divide instructions have been used
32176 in ARM state, or when Thumb integer divide instructions have been used,
32177 but we have no architecture profile set, nor have we any ARM instructions.
32179 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32180 by the base architecture.
32182 For new architectures we will have to check these tests. */
32183 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32184 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32185 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32186 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32187 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32188 || (profile
== '\0'
32189 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32190 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32191 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32193 /* Tag_MP_extension_use. */
32194 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32195 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32197 /* Tag Virtualization_use. */
32198 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32200 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32203 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32205 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32206 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32209 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32210 finished and free extension feature bits which will not be used anymore. */
32213 arm_md_post_relax (void)
32215 aeabi_set_public_attributes ();
32216 XDELETE (mcpu_ext_opt
);
32217 mcpu_ext_opt
= NULL
;
32218 XDELETE (march_ext_opt
);
32219 march_ext_opt
= NULL
;
32222 /* Add the default contents for the .ARM.attributes section. */
32227 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32230 aeabi_set_public_attributes ();
32232 #endif /* OBJ_ELF */
32234 /* Parse a .cpu directive. */
32237 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32239 const struct arm_cpu_option_table
*opt
;
32243 name
= input_line_pointer
;
32244 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32245 input_line_pointer
++;
32246 saved_char
= *input_line_pointer
;
32247 *input_line_pointer
= 0;
32249 /* Skip the first "all" entry. */
32250 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32251 if (streq (opt
->name
, name
))
32253 selected_arch
= opt
->value
;
32254 selected_ext
= opt
->ext
;
32255 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32256 if (opt
->canonical_name
)
32257 strcpy (selected_cpu_name
, opt
->canonical_name
);
32261 for (i
= 0; opt
->name
[i
]; i
++)
32262 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32264 selected_cpu_name
[i
] = 0;
32266 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32268 *input_line_pointer
= saved_char
;
32269 demand_empty_rest_of_line ();
32272 as_bad (_("unknown cpu `%s'"), name
);
32273 *input_line_pointer
= saved_char
;
32274 ignore_rest_of_line ();
32277 /* Parse a .arch directive. */
32280 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32282 const struct arm_arch_option_table
*opt
;
32286 name
= input_line_pointer
;
32287 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32288 input_line_pointer
++;
32289 saved_char
= *input_line_pointer
;
32290 *input_line_pointer
= 0;
32292 /* Skip the first "all" entry. */
32293 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32294 if (streq (opt
->name
, name
))
32296 selected_arch
= opt
->value
;
32297 selected_ext
= arm_arch_none
;
32298 selected_cpu
= selected_arch
;
32299 strcpy (selected_cpu_name
, opt
->name
);
32300 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32301 *input_line_pointer
= saved_char
;
32302 demand_empty_rest_of_line ();
32306 as_bad (_("unknown architecture `%s'\n"), name
);
32307 *input_line_pointer
= saved_char
;
32308 ignore_rest_of_line ();
32311 /* Parse a .object_arch directive. */
32314 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32316 const struct arm_arch_option_table
*opt
;
32320 name
= input_line_pointer
;
32321 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32322 input_line_pointer
++;
32323 saved_char
= *input_line_pointer
;
32324 *input_line_pointer
= 0;
32326 /* Skip the first "all" entry. */
32327 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32328 if (streq (opt
->name
, name
))
32330 selected_object_arch
= opt
->value
;
32331 *input_line_pointer
= saved_char
;
32332 demand_empty_rest_of_line ();
32336 as_bad (_("unknown architecture `%s'\n"), name
);
32337 *input_line_pointer
= saved_char
;
32338 ignore_rest_of_line ();
32341 /* Parse a .arch_extension directive. */
32344 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32346 const struct arm_option_extension_value_table
*opt
;
32349 int adding_value
= 1;
32351 name
= input_line_pointer
;
32352 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32353 input_line_pointer
++;
32354 saved_char
= *input_line_pointer
;
32355 *input_line_pointer
= 0;
32357 if (strlen (name
) >= 2
32358 && strncmp (name
, "no", 2) == 0)
32364 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32365 if (streq (opt
->name
, name
))
32367 int i
, nb_allowed_archs
=
32368 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32369 for (i
= 0; i
< nb_allowed_archs
; i
++)
32372 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32374 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32378 if (i
== nb_allowed_archs
)
32380 as_bad (_("architectural extension `%s' is not allowed for the "
32381 "current base architecture"), name
);
32386 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32389 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32391 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32392 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32393 *input_line_pointer
= saved_char
;
32394 demand_empty_rest_of_line ();
32395 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32396 on this return so that duplicate extensions (extensions with the
32397 same name as a previous extension in the list) are not considered
32398 for command-line parsing. */
32402 if (opt
->name
== NULL
)
32403 as_bad (_("unknown architecture extension `%s'\n"), name
);
32405 *input_line_pointer
= saved_char
;
32406 ignore_rest_of_line ();
32409 /* Parse a .fpu directive. */
32412 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32414 const struct arm_option_fpu_value_table
*opt
;
32418 name
= input_line_pointer
;
32419 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32420 input_line_pointer
++;
32421 saved_char
= *input_line_pointer
;
32422 *input_line_pointer
= 0;
32424 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32425 if (streq (opt
->name
, name
))
32427 selected_fpu
= opt
->value
;
32428 #ifndef CPU_DEFAULT
32429 if (no_cpu_selected ())
32430 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32433 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32434 *input_line_pointer
= saved_char
;
32435 demand_empty_rest_of_line ();
32439 as_bad (_("unknown floating point format `%s'\n"), name
);
32440 *input_line_pointer
= saved_char
;
32441 ignore_rest_of_line ();
32444 /* Copy symbol information. */
32447 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32449 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32453 /* Given a symbolic attribute NAME, return the proper integer value.
32454 Returns -1 if the attribute is not known. */
32457 arm_convert_symbolic_attribute (const char *name
)
32459 static const struct
32464 attribute_table
[] =
32466 /* When you modify this table you should
32467 also modify the list in doc/c-arm.texi. */
32468 #define T(tag) {#tag, tag}
32469 T (Tag_CPU_raw_name
),
32472 T (Tag_CPU_arch_profile
),
32473 T (Tag_ARM_ISA_use
),
32474 T (Tag_THUMB_ISA_use
),
32478 T (Tag_Advanced_SIMD_arch
),
32479 T (Tag_PCS_config
),
32480 T (Tag_ABI_PCS_R9_use
),
32481 T (Tag_ABI_PCS_RW_data
),
32482 T (Tag_ABI_PCS_RO_data
),
32483 T (Tag_ABI_PCS_GOT_use
),
32484 T (Tag_ABI_PCS_wchar_t
),
32485 T (Tag_ABI_FP_rounding
),
32486 T (Tag_ABI_FP_denormal
),
32487 T (Tag_ABI_FP_exceptions
),
32488 T (Tag_ABI_FP_user_exceptions
),
32489 T (Tag_ABI_FP_number_model
),
32490 T (Tag_ABI_align_needed
),
32491 T (Tag_ABI_align8_needed
),
32492 T (Tag_ABI_align_preserved
),
32493 T (Tag_ABI_align8_preserved
),
32494 T (Tag_ABI_enum_size
),
32495 T (Tag_ABI_HardFP_use
),
32496 T (Tag_ABI_VFP_args
),
32497 T (Tag_ABI_WMMX_args
),
32498 T (Tag_ABI_optimization_goals
),
32499 T (Tag_ABI_FP_optimization_goals
),
32500 T (Tag_compatibility
),
32501 T (Tag_CPU_unaligned_access
),
32502 T (Tag_FP_HP_extension
),
32503 T (Tag_VFP_HP_extension
),
32504 T (Tag_ABI_FP_16bit_format
),
32505 T (Tag_MPextension_use
),
32507 T (Tag_nodefaults
),
32508 T (Tag_also_compatible_with
),
32509 T (Tag_conformance
),
32511 T (Tag_Virtualization_use
),
32512 T (Tag_DSP_extension
),
32514 /* We deliberately do not include Tag_MPextension_use_legacy. */
32522 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32523 if (streq (name
, attribute_table
[i
].name
))
32524 return attribute_table
[i
].tag
;
32529 /* Apply sym value for relocations only in the case that they are for
32530 local symbols in the same segment as the fixup and you have the
32531 respective architectural feature for blx and simple switches. */
32534 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32537 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32538 /* PR 17444: If the local symbol is in a different section then a reloc
32539 will always be generated for it, so applying the symbol value now
32540 will result in a double offset being stored in the relocation. */
32541 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32542 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32544 switch (fixP
->fx_r_type
)
32546 case BFD_RELOC_ARM_PCREL_BLX
:
32547 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32548 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32552 case BFD_RELOC_ARM_PCREL_CALL
:
32553 case BFD_RELOC_THUMB_PCREL_BLX
:
32554 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32565 #endif /* OBJ_ELF */