1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 /* Instructions in ARMv8-M only found in M profile architectures. */
239 static const arm_feature_set arm_ext_v8m_m_only
=
240 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_v6t2_v8m
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
243 /* Instructions shared between ARMv8-A and ARMv8-M. */
244 static const arm_feature_set arm_ext_atomics
=
245 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
247 /* DSP instructions Tag_DSP_extension refers to. */
248 static const arm_feature_set arm_ext_dsp
=
249 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
251 static const arm_feature_set arm_ext_ras
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
253 /* FP16 instructions. */
254 static const arm_feature_set arm_ext_fp16
=
255 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
256 static const arm_feature_set arm_ext_fp16_fml
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
258 static const arm_feature_set arm_ext_v8_2
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
260 static const arm_feature_set arm_ext_v8_3
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
262 static const arm_feature_set arm_ext_sb
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
264 static const arm_feature_set arm_ext_predres
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
267 static const arm_feature_set arm_arch_any
= ARM_ANY
;
269 static const arm_feature_set fpu_any
= FPU_ANY
;
271 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
272 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
273 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
275 static const arm_feature_set arm_cext_iwmmxt2
=
276 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
277 static const arm_feature_set arm_cext_iwmmxt
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
279 static const arm_feature_set arm_cext_xscale
=
280 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
281 static const arm_feature_set arm_cext_maverick
=
282 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
283 static const arm_feature_set fpu_fpa_ext_v1
=
284 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
285 static const arm_feature_set fpu_fpa_ext_v2
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
287 static const arm_feature_set fpu_vfp_ext_v1xd
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
289 static const arm_feature_set fpu_vfp_ext_v1
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
291 static const arm_feature_set fpu_vfp_ext_v2
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
293 static const arm_feature_set fpu_vfp_ext_v3xd
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
295 static const arm_feature_set fpu_vfp_ext_v3
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
297 static const arm_feature_set fpu_vfp_ext_d32
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
299 static const arm_feature_set fpu_neon_ext_v1
=
300 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
301 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
304 static const arm_feature_set fpu_vfp_fp16
=
305 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
306 static const arm_feature_set fpu_neon_ext_fma
=
307 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
309 static const arm_feature_set fpu_vfp_ext_fma
=
310 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
311 static const arm_feature_set fpu_vfp_ext_armv8
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
313 static const arm_feature_set fpu_vfp_ext_armv8xd
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
315 static const arm_feature_set fpu_neon_ext_armv8
=
316 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
317 static const arm_feature_set fpu_crypto_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
319 static const arm_feature_set crc_ext_armv8
=
320 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
321 static const arm_feature_set fpu_neon_ext_v8_1
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
323 static const arm_feature_set fpu_neon_ext_dotprod
=
324 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
326 static int mfloat_abi_opt
= -1;
327 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
329 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
330 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
332 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
333 /* Feature bits selected by the last -mcpu/-march or by the combination of the
334 last .cpu/.arch directive .arch_extension directives since that
336 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
337 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
338 static arm_feature_set selected_fpu
= FPU_NONE
;
339 /* Feature bits selected by the last .object_arch directive. */
340 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
341 /* Must be long enough to hold any of the names in arm_cpus. */
342 static char selected_cpu_name
[20];
344 extern FLONUM_TYPE generic_floating_point_number
;
346 /* Return if no cpu was selected on command-line. */
348 no_cpu_selected (void)
350 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
355 static int meabi_flags
= EABI_DEFAULT
;
357 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
360 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
365 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
370 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
371 symbolS
* GOT_symbol
;
374 /* 0: assemble for ARM,
375 1: assemble for Thumb,
376 2: assemble for Thumb even though target CPU does not support thumb
378 static int thumb_mode
= 0;
379 /* A value distinct from the possible values for thumb_mode that we
380 can use to record whether thumb_mode has been copied into the
381 tc_frag_data field of a frag. */
382 #define MODE_RECORDED (1 << 4)
384 /* Specifies the intrinsic IT insn behavior mode. */
385 enum implicit_it_mode
387 IMPLICIT_IT_MODE_NEVER
= 0x00,
388 IMPLICIT_IT_MODE_ARM
= 0x01,
389 IMPLICIT_IT_MODE_THUMB
= 0x02,
390 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
392 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
394 /* If unified_syntax is true, we are processing the new unified
395 ARM/Thumb syntax. Important differences from the old ARM mode:
397 - Immediate operands do not require a # prefix.
398 - Conditional affixes always appear at the end of the
399 instruction. (For backward compatibility, those instructions
400 that formerly had them in the middle, continue to accept them
402 - The IT instruction may appear, and if it does is validated
403 against subsequent conditional affixes. It does not generate
406 Important differences from the old Thumb mode:
408 - Immediate operands do not require a # prefix.
409 - Most of the V6T2 instructions are only available in unified mode.
410 - The .N and .W suffixes are recognized and honored (it is an error
411 if they cannot be honored).
412 - All instructions set the flags if and only if they have an 's' affix.
413 - Conditional affixes may be used. They are validated against
414 preceding IT instructions. Unlike ARM mode, you cannot use a
415 conditional affix except in the scope of an IT instruction. */
417 static bfd_boolean unified_syntax
= FALSE
;
419 /* An immediate operand can start with #, and ld*, st*, pld operands
420 can contain [ and ]. We need to tell APP not to elide whitespace
421 before a [, which can appear as the first operand for pld.
422 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
423 const char arm_symbol_chars
[] = "#[]{}";
438 enum neon_el_type type
;
442 #define NEON_MAX_TYPE_ELS 4
446 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
450 enum it_instruction_type
455 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
456 if inside, should be the last one. */
457 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
458 i.e. BKPT and NOP. */
459 IT_INSN
/* The IT insn has been parsed. */
462 /* The maximum number of operands we need. */
463 #define ARM_IT_MAX_OPERANDS 6
468 unsigned long instruction
;
472 /* "uncond_value" is set to the value in place of the conditional field in
473 unconditional versions of the instruction, or -1 if nothing is
476 struct neon_type vectype
;
477 /* This does not indicate an actual NEON instruction, only that
478 the mnemonic accepts neon-style type suffixes. */
480 /* Set to the opcode if the instruction needs relaxation.
481 Zero if the instruction is not relaxed. */
485 bfd_reloc_code_real_type type
;
490 enum it_instruction_type it_insn_type
;
496 struct neon_type_el vectype
;
497 unsigned present
: 1; /* Operand present. */
498 unsigned isreg
: 1; /* Operand was a register. */
499 unsigned immisreg
: 1; /* .imm field is a second register. */
500 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
501 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
502 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
503 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
504 instructions. This allows us to disambiguate ARM <-> vector insns. */
505 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
506 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
507 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
508 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
509 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
510 unsigned writeback
: 1; /* Operand has trailing ! */
511 unsigned preind
: 1; /* Preindexed address. */
512 unsigned postind
: 1; /* Postindexed address. */
513 unsigned negative
: 1; /* Index register was negated. */
514 unsigned shifted
: 1; /* Shift applied to operation. */
515 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
516 } operands
[ARM_IT_MAX_OPERANDS
];
519 static struct arm_it inst
;
521 #define NUM_FLOAT_VALS 8
523 const char * fp_const
[] =
525 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
528 /* Number of littlenums required to hold an extended precision number. */
529 #define MAX_LITTLENUMS 6
531 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
541 #define CP_T_X 0x00008000
542 #define CP_T_Y 0x00400000
544 #define CONDS_BIT 0x00100000
545 #define LOAD_BIT 0x00100000
547 #define DOUBLE_LOAD_FLAG 0x00000001
551 const char * template_name
;
555 #define COND_ALWAYS 0xE
559 const char * template_name
;
563 struct asm_barrier_opt
565 const char * template_name
;
567 const arm_feature_set arch
;
570 /* The bit that distinguishes CPSR and SPSR. */
571 #define SPSR_BIT (1 << 22)
573 /* The individual PSR flag bits. */
574 #define PSR_c (1 << 16)
575 #define PSR_x (1 << 17)
576 #define PSR_s (1 << 18)
577 #define PSR_f (1 << 19)
582 bfd_reloc_code_real_type reloc
;
587 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
588 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
593 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
596 /* Bits for DEFINED field in neon_typed_alias. */
597 #define NTA_HASTYPE 1
598 #define NTA_HASINDEX 2
600 struct neon_typed_alias
602 unsigned char defined
;
604 struct neon_type_el eltype
;
607 /* ARM register categories. This includes coprocessor numbers and various
608 architecture extensions' registers. Each entry should have an error message
609 in reg_expected_msgs below. */
637 /* Structure for a hash table entry for a register.
638 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
639 information which states whether a vector type or index is specified (for a
640 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
646 unsigned char builtin
;
647 struct neon_typed_alias
* neon
;
650 /* Diagnostics used when we don't get a register of the expected type. */
651 const char * const reg_expected_msgs
[] =
653 [REG_TYPE_RN
] = N_("ARM register expected"),
654 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
655 [REG_TYPE_CN
] = N_("co-processor register expected"),
656 [REG_TYPE_FN
] = N_("FPA register expected"),
657 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
658 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
659 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
660 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
661 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
662 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
663 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
665 [REG_TYPE_VFC
] = N_("VFP system register expected"),
666 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
667 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
668 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
669 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
670 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
671 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
672 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
673 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
674 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
675 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
676 [REG_TYPE_RNB
] = N_("")
679 /* Some well known registers that we refer to directly elsewhere. */
685 /* ARM instructions take 4bytes in the object file, Thumb instructions
691 /* Basic string to match. */
692 const char * template_name
;
694 /* Parameters to instruction. */
695 unsigned int operands
[8];
697 /* Conditional tag - see opcode_lookup. */
698 unsigned int tag
: 4;
700 /* Basic instruction code. */
701 unsigned int avalue
: 28;
703 /* Thumb-format instruction code. */
706 /* Which architecture variant provides this instruction. */
707 const arm_feature_set
* avariant
;
708 const arm_feature_set
* tvariant
;
710 /* Function to call to encode instruction in ARM format. */
711 void (* aencode
) (void);
713 /* Function to call to encode instruction in Thumb format. */
714 void (* tencode
) (void);
717 /* Defines for various bits that we will want to toggle. */
718 #define INST_IMMEDIATE 0x02000000
719 #define OFFSET_REG 0x02000000
720 #define HWOFFSET_IMM 0x00400000
721 #define SHIFT_BY_REG 0x00000010
722 #define PRE_INDEX 0x01000000
723 #define INDEX_UP 0x00800000
724 #define WRITE_BACK 0x00200000
725 #define LDM_TYPE_2_OR_3 0x00400000
726 #define CPSI_MMOD 0x00020000
728 #define LITERAL_MASK 0xf000f000
729 #define OPCODE_MASK 0xfe1fffff
730 #define V4_STR_BIT 0x00000020
731 #define VLDR_VMOV_SAME 0x0040f000
733 #define T2_SUBS_PC_LR 0xf3de8f00
735 #define DATA_OP_SHIFT 21
736 #define SBIT_SHIFT 20
738 #define T2_OPCODE_MASK 0xfe1fffff
739 #define T2_DATA_OP_SHIFT 21
740 #define T2_SBIT_SHIFT 20
742 #define A_COND_MASK 0xf0000000
743 #define A_PUSH_POP_OP_MASK 0x0fff0000
745 /* Opcodes for pushing/poping registers to/from the stack. */
746 #define A1_OPCODE_PUSH 0x092d0000
747 #define A2_OPCODE_PUSH 0x052d0004
748 #define A2_OPCODE_POP 0x049d0004
750 /* Codes to distinguish the arithmetic instructions. */
761 #define OPCODE_CMP 10
762 #define OPCODE_CMN 11
763 #define OPCODE_ORR 12
764 #define OPCODE_MOV 13
765 #define OPCODE_BIC 14
766 #define OPCODE_MVN 15
768 #define T2_OPCODE_AND 0
769 #define T2_OPCODE_BIC 1
770 #define T2_OPCODE_ORR 2
771 #define T2_OPCODE_ORN 3
772 #define T2_OPCODE_EOR 4
773 #define T2_OPCODE_ADD 8
774 #define T2_OPCODE_ADC 10
775 #define T2_OPCODE_SBC 11
776 #define T2_OPCODE_SUB 13
777 #define T2_OPCODE_RSB 14
779 #define T_OPCODE_MUL 0x4340
780 #define T_OPCODE_TST 0x4200
781 #define T_OPCODE_CMN 0x42c0
782 #define T_OPCODE_NEG 0x4240
783 #define T_OPCODE_MVN 0x43c0
785 #define T_OPCODE_ADD_R3 0x1800
786 #define T_OPCODE_SUB_R3 0x1a00
787 #define T_OPCODE_ADD_HI 0x4400
788 #define T_OPCODE_ADD_ST 0xb000
789 #define T_OPCODE_SUB_ST 0xb080
790 #define T_OPCODE_ADD_SP 0xa800
791 #define T_OPCODE_ADD_PC 0xa000
792 #define T_OPCODE_ADD_I8 0x3000
793 #define T_OPCODE_SUB_I8 0x3800
794 #define T_OPCODE_ADD_I3 0x1c00
795 #define T_OPCODE_SUB_I3 0x1e00
797 #define T_OPCODE_ASR_R 0x4100
798 #define T_OPCODE_LSL_R 0x4080
799 #define T_OPCODE_LSR_R 0x40c0
800 #define T_OPCODE_ROR_R 0x41c0
801 #define T_OPCODE_ASR_I 0x1000
802 #define T_OPCODE_LSL_I 0x0000
803 #define T_OPCODE_LSR_I 0x0800
805 #define T_OPCODE_MOV_I8 0x2000
806 #define T_OPCODE_CMP_I8 0x2800
807 #define T_OPCODE_CMP_LR 0x4280
808 #define T_OPCODE_MOV_HR 0x4600
809 #define T_OPCODE_CMP_HR 0x4500
811 #define T_OPCODE_LDR_PC 0x4800
812 #define T_OPCODE_LDR_SP 0x9800
813 #define T_OPCODE_STR_SP 0x9000
814 #define T_OPCODE_LDR_IW 0x6800
815 #define T_OPCODE_STR_IW 0x6000
816 #define T_OPCODE_LDR_IH 0x8800
817 #define T_OPCODE_STR_IH 0x8000
818 #define T_OPCODE_LDR_IB 0x7800
819 #define T_OPCODE_STR_IB 0x7000
820 #define T_OPCODE_LDR_RW 0x5800
821 #define T_OPCODE_STR_RW 0x5000
822 #define T_OPCODE_LDR_RH 0x5a00
823 #define T_OPCODE_STR_RH 0x5200
824 #define T_OPCODE_LDR_RB 0x5c00
825 #define T_OPCODE_STR_RB 0x5400
827 #define T_OPCODE_PUSH 0xb400
828 #define T_OPCODE_POP 0xbc00
830 #define T_OPCODE_BRANCH 0xe000
832 #define THUMB_SIZE 2 /* Size of thumb instruction. */
833 #define THUMB_PP_PC_LR 0x0100
834 #define THUMB_LOAD_BIT 0x0800
835 #define THUMB2_LOAD_BIT 0x00100000
837 #define BAD_ARGS _("bad arguments to instruction")
838 #define BAD_SP _("r13 not allowed here")
839 #define BAD_PC _("r15 not allowed here")
840 #define BAD_COND _("instruction cannot be conditional")
841 #define BAD_OVERLAP _("registers may not be the same")
842 #define BAD_HIREG _("lo register required")
843 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
844 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
845 #define BAD_BRANCH _("branch must be last instruction in IT block")
846 #define BAD_NOT_IT _("instruction not allowed in IT block")
847 #define BAD_FPU _("selected FPU does not support instruction")
848 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
849 #define BAD_IT_COND _("incorrect condition in IT block")
850 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
851 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
852 #define BAD_PC_ADDRESSING \
853 _("cannot use register index with PC-relative addressing")
854 #define BAD_PC_WRITEBACK \
855 _("cannot use writeback with PC-relative addressing")
856 #define BAD_RANGE _("branch out of range")
857 #define BAD_FP16 _("selected processor does not support fp16 instruction")
858 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
859 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
861 static struct hash_control
* arm_ops_hsh
;
862 static struct hash_control
* arm_cond_hsh
;
863 static struct hash_control
* arm_shift_hsh
;
864 static struct hash_control
* arm_psr_hsh
;
865 static struct hash_control
* arm_v7m_psr_hsh
;
866 static struct hash_control
* arm_reg_hsh
;
867 static struct hash_control
* arm_reloc_hsh
;
868 static struct hash_control
* arm_barrier_opt_hsh
;
870 /* Stuff needed to resolve the label ambiguity
879 symbolS
* last_label_seen
;
880 static int label_is_thumb_function_name
= FALSE
;
882 /* Literal pool structure. Held on a per-section
883 and per-sub-section basis. */
885 #define MAX_LITERAL_POOL_SIZE 1024
886 typedef struct literal_pool
888 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
889 unsigned int next_free_entry
;
895 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
897 struct literal_pool
* next
;
898 unsigned int alignment
;
901 /* Pointer to a linked list of literal pools. */
902 literal_pool
* list_of_pools
= NULL
;
904 typedef enum asmfunc_states
907 WAITING_ASMFUNC_NAME
,
911 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
914 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
916 static struct current_it now_it
;
920 now_it_compatible (int cond
)
922 return (cond
& ~1) == (now_it
.cc
& ~1);
926 conditional_insn (void)
928 return inst
.cond
!= COND_ALWAYS
;
931 static int in_it_block (void);
933 static int handle_it_state (void);
935 static void force_automatic_it_block_close (void);
937 static void it_fsm_post_encode (void);
939 #define set_it_insn_type(type) \
942 inst.it_insn_type = type; \
943 if (handle_it_state () == FAIL) \
948 #define set_it_insn_type_nonvoid(type, failret) \
951 inst.it_insn_type = type; \
952 if (handle_it_state () == FAIL) \
957 #define set_it_insn_type_last() \
960 if (inst.cond == COND_ALWAYS) \
961 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
963 set_it_insn_type (INSIDE_IT_LAST_INSN); \
969 /* This array holds the chars that always start a comment. If the
970 pre-processor is disabled, these aren't very useful. */
971 char arm_comment_chars
[] = "@";
973 /* This array holds the chars that only start a comment at the beginning of
974 a line. If the line seems to have the form '# 123 filename'
975 .line and .file directives will appear in the pre-processed output. */
976 /* Note that input_file.c hand checks for '#' at the beginning of the
977 first line of the input file. This is because the compiler outputs
978 #NO_APP at the beginning of its output. */
979 /* Also note that comments like this one will always work. */
980 const char line_comment_chars
[] = "#";
982 char arm_line_separator_chars
[] = ";";
984 /* Chars that can be used to separate mant
985 from exp in floating point numbers. */
986 const char EXP_CHARS
[] = "eE";
988 /* Chars that mean this number is a floating point constant. */
992 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
994 /* Prefix characters that indicate the start of an immediate
996 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
998 /* Separator character handling. */
1000 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1003 skip_past_char (char ** str
, char c
)
1005 /* PR gas/14987: Allow for whitespace before the expected character. */
1006 skip_whitespace (*str
);
1017 #define skip_past_comma(str) skip_past_char (str, ',')
1019 /* Arithmetic expressions (possibly involving symbols). */
1021 /* Return TRUE if anything in the expression is a bignum. */
1024 walk_no_bignums (symbolS
* sp
)
1026 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1029 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1031 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1032 || (symbol_get_value_expression (sp
)->X_op_symbol
1033 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1039 static bfd_boolean in_my_get_expression
= FALSE
;
1041 /* Third argument to my_get_expression. */
1042 #define GE_NO_PREFIX 0
1043 #define GE_IMM_PREFIX 1
1044 #define GE_OPT_PREFIX 2
1045 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1046 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1047 #define GE_OPT_PREFIX_BIG 3
1050 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1054 /* In unified syntax, all prefixes are optional. */
1056 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1059 switch (prefix_mode
)
1061 case GE_NO_PREFIX
: break;
1063 if (!is_immediate_prefix (**str
))
1065 inst
.error
= _("immediate expression requires a # prefix");
1071 case GE_OPT_PREFIX_BIG
:
1072 if (is_immediate_prefix (**str
))
1079 memset (ep
, 0, sizeof (expressionS
));
1081 save_in
= input_line_pointer
;
1082 input_line_pointer
= *str
;
1083 in_my_get_expression
= TRUE
;
1085 in_my_get_expression
= FALSE
;
1087 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1089 /* We found a bad or missing expression in md_operand(). */
1090 *str
= input_line_pointer
;
1091 input_line_pointer
= save_in
;
1092 if (inst
.error
== NULL
)
1093 inst
.error
= (ep
->X_op
== O_absent
1094 ? _("missing expression") :_("bad expression"));
1098 /* Get rid of any bignums now, so that we don't generate an error for which
1099 we can't establish a line number later on. Big numbers are never valid
1100 in instructions, which is where this routine is always called. */
1101 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1102 && (ep
->X_op
== O_big
1103 || (ep
->X_add_symbol
1104 && (walk_no_bignums (ep
->X_add_symbol
)
1106 && walk_no_bignums (ep
->X_op_symbol
))))))
1108 inst
.error
= _("invalid constant");
1109 *str
= input_line_pointer
;
1110 input_line_pointer
= save_in
;
1114 *str
= input_line_pointer
;
1115 input_line_pointer
= save_in
;
1119 /* Turn a string in input_line_pointer into a floating point constant
1120 of type TYPE, and store the appropriate bytes in *LITP. The number
1121 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1122 returned, or NULL on OK.
1124 Note that fp constants aren't represent in the normal way on the ARM.
1125 In big endian mode, things are as expected. However, in little endian
1126 mode fp constants are big-endian word-wise, and little-endian byte-wise
1127 within the words. For example, (double) 1.1 in big endian mode is
1128 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1129 the byte sequence 99 99 f1 3f 9a 99 99 99.
1131 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1134 md_atof (int type
, char * litP
, int * sizeP
)
1137 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1169 return _("Unrecognized or unsupported floating point constant");
1172 t
= atof_ieee (input_line_pointer
, type
, words
);
1174 input_line_pointer
= t
;
1175 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1177 if (target_big_endian
)
1179 for (i
= 0; i
< prec
; i
++)
1181 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1182 litP
+= sizeof (LITTLENUM_TYPE
);
1187 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1188 for (i
= prec
- 1; i
>= 0; i
--)
1190 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1191 litP
+= sizeof (LITTLENUM_TYPE
);
1194 /* For a 4 byte float the order of elements in `words' is 1 0.
1195 For an 8 byte float the order is 1 0 3 2. */
1196 for (i
= 0; i
< prec
; i
+= 2)
1198 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1199 sizeof (LITTLENUM_TYPE
));
1200 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1201 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1202 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1209 /* We handle all bad expressions here, so that we can report the faulty
1210 instruction in the error message. */
1213 md_operand (expressionS
* exp
)
1215 if (in_my_get_expression
)
1216 exp
->X_op
= O_illegal
;
1219 /* Immediate values. */
1222 /* Generic immediate-value read function for use in directives.
1223 Accepts anything that 'expression' can fold to a constant.
1224 *val receives the number. */
1227 immediate_for_directive (int *val
)
1230 exp
.X_op
= O_illegal
;
1232 if (is_immediate_prefix (*input_line_pointer
))
1234 input_line_pointer
++;
1238 if (exp
.X_op
!= O_constant
)
1240 as_bad (_("expected #constant"));
1241 ignore_rest_of_line ();
1244 *val
= exp
.X_add_number
;
1249 /* Register parsing. */
1251 /* Generic register parser. CCP points to what should be the
1252 beginning of a register name. If it is indeed a valid register
1253 name, advance CCP over it and return the reg_entry structure;
1254 otherwise return NULL. Does not issue diagnostics. */
1256 static struct reg_entry
*
1257 arm_reg_parse_multi (char **ccp
)
1261 struct reg_entry
*reg
;
1263 skip_whitespace (start
);
1265 #ifdef REGISTER_PREFIX
1266 if (*start
!= REGISTER_PREFIX
)
1270 #ifdef OPTIONAL_REGISTER_PREFIX
1271 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1276 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1281 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1283 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1293 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1294 enum arm_reg_type type
)
1296 /* Alternative syntaxes are accepted for a few register classes. */
1303 /* Generic coprocessor register names are allowed for these. */
1304 if (reg
&& reg
->type
== REG_TYPE_CN
)
1309 /* For backward compatibility, a bare number is valid here. */
1311 unsigned long processor
= strtoul (start
, ccp
, 10);
1312 if (*ccp
!= start
&& processor
<= 15)
1317 case REG_TYPE_MMXWC
:
1318 /* WC includes WCG. ??? I'm not sure this is true for all
1319 instructions that take WC registers. */
1320 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1331 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1332 return value is the register number or FAIL. */
1335 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1338 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1341 /* Do not allow a scalar (reg+index) to parse as a register. */
1342 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1345 if (reg
&& reg
->type
== type
)
1348 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1355 /* Parse a Neon type specifier. *STR should point at the leading '.'
1356 character. Does no verification at this stage that the type fits the opcode
1363 Can all be legally parsed by this function.
1365 Fills in neon_type struct pointer with parsed information, and updates STR
1366 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1367 type, FAIL if not. */
1370 parse_neon_type (struct neon_type
*type
, char **str
)
1377 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1379 enum neon_el_type thistype
= NT_untyped
;
1380 unsigned thissize
= -1u;
1387 /* Just a size without an explicit type. */
1391 switch (TOLOWER (*ptr
))
1393 case 'i': thistype
= NT_integer
; break;
1394 case 'f': thistype
= NT_float
; break;
1395 case 'p': thistype
= NT_poly
; break;
1396 case 's': thistype
= NT_signed
; break;
1397 case 'u': thistype
= NT_unsigned
; break;
1399 thistype
= NT_float
;
1404 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1410 /* .f is an abbreviation for .f32. */
1411 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1416 thissize
= strtoul (ptr
, &ptr
, 10);
1418 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1421 as_bad (_("bad size %d in type specifier"), thissize
);
1429 type
->el
[type
->elems
].type
= thistype
;
1430 type
->el
[type
->elems
].size
= thissize
;
1435 /* Empty/missing type is not a successful parse. */
1436 if (type
->elems
== 0)
1444 /* Errors may be set multiple times during parsing or bit encoding
1445 (particularly in the Neon bits), but usually the earliest error which is set
1446 will be the most meaningful. Avoid overwriting it with later (cascading)
1447 errors by calling this function. */
1450 first_error (const char *err
)
1456 /* Parse a single type, e.g. ".s32", leading period included. */
1458 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1461 struct neon_type optype
;
1465 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1467 if (optype
.elems
== 1)
1468 *vectype
= optype
.el
[0];
1471 first_error (_("only one type should be specified for operand"));
1477 first_error (_("vector type expected"));
1489 /* Special meanings for indices (which have a range of 0-7), which will fit into
1492 #define NEON_ALL_LANES 15
1493 #define NEON_INTERLEAVE_LANES 14
1495 /* Parse either a register or a scalar, with an optional type. Return the
1496 register number, and optionally fill in the actual type of the register
1497 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1498 type/index information in *TYPEINFO. */
1501 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1502 enum arm_reg_type
*rtype
,
1503 struct neon_typed_alias
*typeinfo
)
1506 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1507 struct neon_typed_alias atype
;
1508 struct neon_type_el parsetype
;
1512 atype
.eltype
.type
= NT_invtype
;
1513 atype
.eltype
.size
= -1;
1515 /* Try alternate syntax for some types of register. Note these are mutually
1516 exclusive with the Neon syntax extensions. */
1519 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1527 /* Undo polymorphism when a set of register types may be accepted. */
1528 if ((type
== REG_TYPE_NDQ
1529 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1530 || (type
== REG_TYPE_VFSD
1531 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1532 || (type
== REG_TYPE_NSDQ
1533 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1534 || reg
->type
== REG_TYPE_NQ
))
1535 || (type
== REG_TYPE_NSD
1536 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1537 || (type
== REG_TYPE_MMXWC
1538 && (reg
->type
== REG_TYPE_MMXWCG
)))
1539 type
= (enum arm_reg_type
) reg
->type
;
1541 if (type
!= reg
->type
)
1547 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1549 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1551 first_error (_("can't redefine type for operand"));
1554 atype
.defined
|= NTA_HASTYPE
;
1555 atype
.eltype
= parsetype
;
1558 if (skip_past_char (&str
, '[') == SUCCESS
)
1560 if (type
!= REG_TYPE_VFD
1561 && !(type
== REG_TYPE_VFS
1562 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1564 first_error (_("only D registers may be indexed"));
1568 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1570 first_error (_("can't change index for operand"));
1574 atype
.defined
|= NTA_HASINDEX
;
1576 if (skip_past_char (&str
, ']') == SUCCESS
)
1577 atype
.index
= NEON_ALL_LANES
;
1582 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1584 if (exp
.X_op
!= O_constant
)
1586 first_error (_("constant expression required"));
1590 if (skip_past_char (&str
, ']') == FAIL
)
1593 atype
.index
= exp
.X_add_number
;
1608 /* Like arm_reg_parse, but allow allow the following extra features:
1609 - If RTYPE is non-zero, return the (possibly restricted) type of the
1610 register (e.g. Neon double or quad reg when either has been requested).
1611 - If this is a Neon vector type with additional type information, fill
1612 in the struct pointed to by VECTYPE (if non-NULL).
1613 This function will fault on encountering a scalar. */
1616 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1617 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1619 struct neon_typed_alias atype
;
1621 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1626 /* Do not allow regname(... to parse as a register. */
1630 /* Do not allow a scalar (reg+index) to parse as a register. */
1631 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1633 first_error (_("register operand expected, but got scalar"));
1638 *vectype
= atype
.eltype
;
1645 #define NEON_SCALAR_REG(X) ((X) >> 4)
1646 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1648 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1649 have enough information to be able to do a good job bounds-checking. So, we
1650 just do easy checks here, and do further checks later. */
1653 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1657 struct neon_typed_alias atype
;
1658 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1661 reg_type
= REG_TYPE_VFS
;
1663 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1665 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1668 if (atype
.index
== NEON_ALL_LANES
)
1670 first_error (_("scalar must have an index"));
1673 else if (atype
.index
>= 64 / elsize
)
1675 first_error (_("scalar index out of range"));
1680 *type
= atype
.eltype
;
1684 return reg
* 16 + atype
.index
;
1687 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1690 parse_reg_list (char ** strp
)
1692 char * str
= * strp
;
1696 /* We come back here if we get ranges concatenated by '+' or '|'. */
1699 skip_whitespace (str
);
1713 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1715 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1725 first_error (_("bad range in register list"));
1729 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1731 if (range
& (1 << i
))
1733 (_("Warning: duplicated register (r%d) in register list"),
1741 if (range
& (1 << reg
))
1742 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1744 else if (reg
<= cur_reg
)
1745 as_tsktsk (_("Warning: register range not in ascending order"));
1750 while (skip_past_comma (&str
) != FAIL
1751 || (in_range
= 1, *str
++ == '-'));
1754 if (skip_past_char (&str
, '}') == FAIL
)
1756 first_error (_("missing `}'"));
1764 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1767 if (exp
.X_op
== O_constant
)
1769 if (exp
.X_add_number
1770 != (exp
.X_add_number
& 0x0000ffff))
1772 inst
.error
= _("invalid register mask");
1776 if ((range
& exp
.X_add_number
) != 0)
1778 int regno
= range
& exp
.X_add_number
;
1781 regno
= (1 << regno
) - 1;
1783 (_("Warning: duplicated register (r%d) in register list"),
1787 range
|= exp
.X_add_number
;
1791 if (inst
.reloc
.type
!= 0)
1793 inst
.error
= _("expression too complex");
1797 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1798 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1799 inst
.reloc
.pc_rel
= 0;
1803 if (*str
== '|' || *str
== '+')
1809 while (another_range
);
1815 /* Types of registers in a list. */
1824 /* Parse a VFP register list. If the string is invalid return FAIL.
1825 Otherwise return the number of registers, and set PBASE to the first
1826 register. Parses registers of type ETYPE.
1827 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1828 - Q registers can be used to specify pairs of D registers
1829 - { } can be omitted from around a singleton register list
1830 FIXME: This is not implemented, as it would require backtracking in
1833 This could be done (the meaning isn't really ambiguous), but doesn't
1834 fit in well with the current parsing framework.
1835 - 32 D registers may be used (also true for VFPv3).
1836 FIXME: Types are ignored in these register lists, which is probably a
1840 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1845 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1849 unsigned long mask
= 0;
1852 if (skip_past_char (&str
, '{') == FAIL
)
1854 inst
.error
= _("expecting {");
1861 regtype
= REG_TYPE_VFS
;
1866 regtype
= REG_TYPE_VFD
;
1869 case REGLIST_NEON_D
:
1870 regtype
= REG_TYPE_NDQ
;
1874 if (etype
!= REGLIST_VFP_S
)
1876 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1877 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1881 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1884 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1891 base_reg
= max_regs
;
1895 int setmask
= 1, addregs
= 1;
1897 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1899 if (new_base
== FAIL
)
1901 first_error (_(reg_expected_msgs
[regtype
]));
1905 if (new_base
>= max_regs
)
1907 first_error (_("register out of range in list"));
1911 /* Note: a value of 2 * n is returned for the register Q<n>. */
1912 if (regtype
== REG_TYPE_NQ
)
1918 if (new_base
< base_reg
)
1919 base_reg
= new_base
;
1921 if (mask
& (setmask
<< new_base
))
1923 first_error (_("invalid register list"));
1927 if ((mask
>> new_base
) != 0 && ! warned
)
1929 as_tsktsk (_("register list not in ascending order"));
1933 mask
|= setmask
<< new_base
;
1936 if (*str
== '-') /* We have the start of a range expression */
1942 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1945 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1949 if (high_range
>= max_regs
)
1951 first_error (_("register out of range in list"));
1955 if (regtype
== REG_TYPE_NQ
)
1956 high_range
= high_range
+ 1;
1958 if (high_range
<= new_base
)
1960 inst
.error
= _("register range not in ascending order");
1964 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1966 if (mask
& (setmask
<< new_base
))
1968 inst
.error
= _("invalid register list");
1972 mask
|= setmask
<< new_base
;
1977 while (skip_past_comma (&str
) != FAIL
);
1981 /* Sanity check -- should have raised a parse error above. */
1982 if (count
== 0 || count
> max_regs
)
1987 /* Final test -- the registers must be consecutive. */
1989 for (i
= 0; i
< count
; i
++)
1991 if ((mask
& (1u << i
)) == 0)
1993 inst
.error
= _("non-contiguous register range");
2003 /* True if two alias types are the same. */
2006 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2014 if (a
->defined
!= b
->defined
)
2017 if ((a
->defined
& NTA_HASTYPE
) != 0
2018 && (a
->eltype
.type
!= b
->eltype
.type
2019 || a
->eltype
.size
!= b
->eltype
.size
))
2022 if ((a
->defined
& NTA_HASINDEX
) != 0
2023 && (a
->index
!= b
->index
))
2029 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2030 The base register is put in *PBASE.
2031 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2033 The register stride (minus one) is put in bit 4 of the return value.
2034 Bits [6:5] encode the list length (minus one).
2035 The type of the list elements is put in *ELTYPE, if non-NULL. */
2037 #define NEON_LANE(X) ((X) & 0xf)
2038 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2039 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2042 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2043 struct neon_type_el
*eltype
)
2050 int leading_brace
= 0;
2051 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2052 const char *const incr_error
= _("register stride must be 1 or 2");
2053 const char *const type_error
= _("mismatched element/structure types in list");
2054 struct neon_typed_alias firsttype
;
2055 firsttype
.defined
= 0;
2056 firsttype
.eltype
.type
= NT_invtype
;
2057 firsttype
.eltype
.size
= -1;
2058 firsttype
.index
= -1;
2060 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2065 struct neon_typed_alias atype
;
2066 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2070 first_error (_(reg_expected_msgs
[rtype
]));
2077 if (rtype
== REG_TYPE_NQ
)
2083 else if (reg_incr
== -1)
2085 reg_incr
= getreg
- base_reg
;
2086 if (reg_incr
< 1 || reg_incr
> 2)
2088 first_error (_(incr_error
));
2092 else if (getreg
!= base_reg
+ reg_incr
* count
)
2094 first_error (_(incr_error
));
2098 if (! neon_alias_types_same (&atype
, &firsttype
))
2100 first_error (_(type_error
));
2104 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2108 struct neon_typed_alias htype
;
2109 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2111 lane
= NEON_INTERLEAVE_LANES
;
2112 else if (lane
!= NEON_INTERLEAVE_LANES
)
2114 first_error (_(type_error
));
2119 else if (reg_incr
!= 1)
2121 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2125 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2128 first_error (_(reg_expected_msgs
[rtype
]));
2131 if (! neon_alias_types_same (&htype
, &firsttype
))
2133 first_error (_(type_error
));
2136 count
+= hireg
+ dregs
- getreg
;
2140 /* If we're using Q registers, we can't use [] or [n] syntax. */
2141 if (rtype
== REG_TYPE_NQ
)
2147 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2151 else if (lane
!= atype
.index
)
2153 first_error (_(type_error
));
2157 else if (lane
== -1)
2158 lane
= NEON_INTERLEAVE_LANES
;
2159 else if (lane
!= NEON_INTERLEAVE_LANES
)
2161 first_error (_(type_error
));
2166 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2168 /* No lane set by [x]. We must be interleaving structures. */
2170 lane
= NEON_INTERLEAVE_LANES
;
2173 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2174 || (count
> 1 && reg_incr
== -1))
2176 first_error (_("error parsing element/structure list"));
2180 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2182 first_error (_("expected }"));
2190 *eltype
= firsttype
.eltype
;
2195 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2198 /* Parse an explicit relocation suffix on an expression. This is
2199 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2200 arm_reloc_hsh contains no entries, so this function can only
2201 succeed if there is no () after the word. Returns -1 on error,
2202 BFD_RELOC_UNUSED if there wasn't any suffix. */
2205 parse_reloc (char **str
)
2207 struct reloc_entry
*r
;
2211 return BFD_RELOC_UNUSED
;
2216 while (*q
&& *q
!= ')' && *q
!= ',')
2221 if ((r
= (struct reloc_entry
*)
2222 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2229 /* Directives: register aliases. */
2231 static struct reg_entry
*
2232 insert_reg_alias (char *str
, unsigned number
, int type
)
2234 struct reg_entry
*new_reg
;
2237 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2239 if (new_reg
->builtin
)
2240 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2242 /* Only warn about a redefinition if it's not defined as the
2244 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2245 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2250 name
= xstrdup (str
);
2251 new_reg
= XNEW (struct reg_entry
);
2253 new_reg
->name
= name
;
2254 new_reg
->number
= number
;
2255 new_reg
->type
= type
;
2256 new_reg
->builtin
= FALSE
;
2257 new_reg
->neon
= NULL
;
2259 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2266 insert_neon_reg_alias (char *str
, int number
, int type
,
2267 struct neon_typed_alias
*atype
)
2269 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2273 first_error (_("attempt to redefine typed alias"));
2279 reg
->neon
= XNEW (struct neon_typed_alias
);
2280 *reg
->neon
= *atype
;
2284 /* Look for the .req directive. This is of the form:
2286 new_register_name .req existing_register_name
2288 If we find one, or if it looks sufficiently like one that we want to
2289 handle any error here, return TRUE. Otherwise return FALSE. */
2292 create_register_alias (char * newname
, char *p
)
2294 struct reg_entry
*old
;
2295 char *oldname
, *nbuf
;
2298 /* The input scrubber ensures that whitespace after the mnemonic is
2299 collapsed to single spaces. */
2301 if (strncmp (oldname
, " .req ", 6) != 0)
2305 if (*oldname
== '\0')
2308 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2311 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2315 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2316 the desired alias name, and p points to its end. If not, then
2317 the desired alias name is in the global original_case_string. */
2318 #ifdef TC_CASE_SENSITIVE
2321 newname
= original_case_string
;
2322 nlen
= strlen (newname
);
2325 nbuf
= xmemdup0 (newname
, nlen
);
2327 /* Create aliases under the new name as stated; an all-lowercase
2328 version of the new name; and an all-uppercase version of the new
2330 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2332 for (p
= nbuf
; *p
; p
++)
2335 if (strncmp (nbuf
, newname
, nlen
))
2337 /* If this attempt to create an additional alias fails, do not bother
2338 trying to create the all-lower case alias. We will fail and issue
2339 a second, duplicate error message. This situation arises when the
2340 programmer does something like:
2343 The second .req creates the "Foo" alias but then fails to create
2344 the artificial FOO alias because it has already been created by the
2346 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2353 for (p
= nbuf
; *p
; p
++)
2356 if (strncmp (nbuf
, newname
, nlen
))
2357 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2364 /* Create a Neon typed/indexed register alias using directives, e.g.:
2369 These typed registers can be used instead of the types specified after the
2370 Neon mnemonic, so long as all operands given have types. Types can also be
2371 specified directly, e.g.:
2372 vadd d0.s32, d1.s32, d2.s32 */
2375 create_neon_reg_alias (char *newname
, char *p
)
2377 enum arm_reg_type basetype
;
2378 struct reg_entry
*basereg
;
2379 struct reg_entry mybasereg
;
2380 struct neon_type ntype
;
2381 struct neon_typed_alias typeinfo
;
2382 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2385 typeinfo
.defined
= 0;
2386 typeinfo
.eltype
.type
= NT_invtype
;
2387 typeinfo
.eltype
.size
= -1;
2388 typeinfo
.index
= -1;
2392 if (strncmp (p
, " .dn ", 5) == 0)
2393 basetype
= REG_TYPE_VFD
;
2394 else if (strncmp (p
, " .qn ", 5) == 0)
2395 basetype
= REG_TYPE_NQ
;
2404 basereg
= arm_reg_parse_multi (&p
);
2406 if (basereg
&& basereg
->type
!= basetype
)
2408 as_bad (_("bad type for register"));
2412 if (basereg
== NULL
)
2415 /* Try parsing as an integer. */
2416 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2417 if (exp
.X_op
!= O_constant
)
2419 as_bad (_("expression must be constant"));
2422 basereg
= &mybasereg
;
2423 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2429 typeinfo
= *basereg
->neon
;
2431 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2433 /* We got a type. */
2434 if (typeinfo
.defined
& NTA_HASTYPE
)
2436 as_bad (_("can't redefine the type of a register alias"));
2440 typeinfo
.defined
|= NTA_HASTYPE
;
2441 if (ntype
.elems
!= 1)
2443 as_bad (_("you must specify a single type only"));
2446 typeinfo
.eltype
= ntype
.el
[0];
2449 if (skip_past_char (&p
, '[') == SUCCESS
)
2452 /* We got a scalar index. */
2454 if (typeinfo
.defined
& NTA_HASINDEX
)
2456 as_bad (_("can't redefine the index of a scalar alias"));
2460 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2462 if (exp
.X_op
!= O_constant
)
2464 as_bad (_("scalar index must be constant"));
2468 typeinfo
.defined
|= NTA_HASINDEX
;
2469 typeinfo
.index
= exp
.X_add_number
;
2471 if (skip_past_char (&p
, ']') == FAIL
)
2473 as_bad (_("expecting ]"));
2478 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2479 the desired alias name, and p points to its end. If not, then
2480 the desired alias name is in the global original_case_string. */
2481 #ifdef TC_CASE_SENSITIVE
2482 namelen
= nameend
- newname
;
2484 newname
= original_case_string
;
2485 namelen
= strlen (newname
);
2488 namebuf
= xmemdup0 (newname
, namelen
);
2490 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2491 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2493 /* Insert name in all uppercase. */
2494 for (p
= namebuf
; *p
; p
++)
2497 if (strncmp (namebuf
, newname
, namelen
))
2498 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2499 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2501 /* Insert name in all lowercase. */
2502 for (p
= namebuf
; *p
; p
++)
2505 if (strncmp (namebuf
, newname
, namelen
))
2506 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2507 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2513 /* Should never be called, as .req goes between the alias and the
2514 register name, not at the beginning of the line. */
2517 s_req (int a ATTRIBUTE_UNUSED
)
2519 as_bad (_("invalid syntax for .req directive"));
2523 s_dn (int a ATTRIBUTE_UNUSED
)
2525 as_bad (_("invalid syntax for .dn directive"));
2529 s_qn (int a ATTRIBUTE_UNUSED
)
2531 as_bad (_("invalid syntax for .qn directive"));
2534 /* The .unreq directive deletes an alias which was previously defined
2535 by .req. For example:
2541 s_unreq (int a ATTRIBUTE_UNUSED
)
2546 name
= input_line_pointer
;
2548 while (*input_line_pointer
!= 0
2549 && *input_line_pointer
!= ' '
2550 && *input_line_pointer
!= '\n')
2551 ++input_line_pointer
;
2553 saved_char
= *input_line_pointer
;
2554 *input_line_pointer
= 0;
2557 as_bad (_("invalid syntax for .unreq directive"));
2560 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2564 as_bad (_("unknown register alias '%s'"), name
);
2565 else if (reg
->builtin
)
2566 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2573 hash_delete (arm_reg_hsh
, name
, FALSE
);
2574 free ((char *) reg
->name
);
2579 /* Also locate the all upper case and all lower case versions.
2580 Do not complain if we cannot find one or the other as it
2581 was probably deleted above. */
2583 nbuf
= strdup (name
);
2584 for (p
= nbuf
; *p
; p
++)
2586 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2589 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2590 free ((char *) reg
->name
);
2596 for (p
= nbuf
; *p
; p
++)
2598 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2601 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2602 free ((char *) reg
->name
);
2612 *input_line_pointer
= saved_char
;
2613 demand_empty_rest_of_line ();
2616 /* Directives: Instruction set selection. */
2619 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2620 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2621 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2622 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2624 /* Create a new mapping symbol for the transition to STATE. */
2627 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2630 const char * symname
;
2637 type
= BSF_NO_FLAGS
;
2641 type
= BSF_NO_FLAGS
;
2645 type
= BSF_NO_FLAGS
;
2651 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2652 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2657 THUMB_SET_FUNC (symbolP
, 0);
2658 ARM_SET_THUMB (symbolP
, 0);
2659 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2663 THUMB_SET_FUNC (symbolP
, 1);
2664 ARM_SET_THUMB (symbolP
, 1);
2665 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2673 /* Save the mapping symbols for future reference. Also check that
2674 we do not place two mapping symbols at the same offset within a
2675 frag. We'll handle overlap between frags in
2676 check_mapping_symbols.
2678 If .fill or other data filling directive generates zero sized data,
2679 the mapping symbol for the following code will have the same value
2680 as the one generated for the data filling directive. In this case,
2681 we replace the old symbol with the new one at the same address. */
2684 if (frag
->tc_frag_data
.first_map
!= NULL
)
2686 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2687 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2689 frag
->tc_frag_data
.first_map
= symbolP
;
2691 if (frag
->tc_frag_data
.last_map
!= NULL
)
2693 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2694 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2695 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2697 frag
->tc_frag_data
.last_map
= symbolP
;
2700 /* We must sometimes convert a region marked as code to data during
2701 code alignment, if an odd number of bytes have to be padded. The
2702 code mapping symbol is pushed to an aligned address. */
2705 insert_data_mapping_symbol (enum mstate state
,
2706 valueT value
, fragS
*frag
, offsetT bytes
)
2708 /* If there was already a mapping symbol, remove it. */
2709 if (frag
->tc_frag_data
.last_map
!= NULL
2710 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2712 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2716 know (frag
->tc_frag_data
.first_map
== symp
);
2717 frag
->tc_frag_data
.first_map
= NULL
;
2719 frag
->tc_frag_data
.last_map
= NULL
;
2720 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2723 make_mapping_symbol (MAP_DATA
, value
, frag
);
2724 make_mapping_symbol (state
, value
+ bytes
, frag
);
2727 static void mapping_state_2 (enum mstate state
, int max_chars
);
2729 /* Set the mapping state to STATE. Only call this when about to
2730 emit some STATE bytes to the file. */
2732 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2734 mapping_state (enum mstate state
)
2736 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2738 if (mapstate
== state
)
2739 /* The mapping symbol has already been emitted.
2740 There is nothing else to do. */
2743 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2745 All ARM instructions require 4-byte alignment.
2746 (Almost) all Thumb instructions require 2-byte alignment.
2748 When emitting instructions into any section, mark the section
2751 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2752 but themselves require 2-byte alignment; this applies to some
2753 PC- relative forms. However, these cases will involve implicit
2754 literal pool generation or an explicit .align >=2, both of
2755 which will cause the section to me marked with sufficient
2756 alignment. Thus, we don't handle those cases here. */
2757 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2759 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2760 /* This case will be evaluated later. */
2763 mapping_state_2 (state
, 0);
2766 /* Same as mapping_state, but MAX_CHARS bytes have already been
2767 allocated. Put the mapping symbol that far back. */
2770 mapping_state_2 (enum mstate state
, int max_chars
)
2772 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2774 if (!SEG_NORMAL (now_seg
))
2777 if (mapstate
== state
)
2778 /* The mapping symbol has already been emitted.
2779 There is nothing else to do. */
2782 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2783 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2785 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2786 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2789 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2792 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2793 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2797 #define mapping_state(x) ((void)0)
2798 #define mapping_state_2(x, y) ((void)0)
2801 /* Find the real, Thumb encoded start of a Thumb function. */
2805 find_real_start (symbolS
* symbolP
)
2808 const char * name
= S_GET_NAME (symbolP
);
2809 symbolS
* new_target
;
2811 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2812 #define STUB_NAME ".real_start_of"
2817 /* The compiler may generate BL instructions to local labels because
2818 it needs to perform a branch to a far away location. These labels
2819 do not have a corresponding ".real_start_of" label. We check
2820 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2821 the ".real_start_of" convention for nonlocal branches. */
2822 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2825 real_start
= concat (STUB_NAME
, name
, NULL
);
2826 new_target
= symbol_find (real_start
);
2829 if (new_target
== NULL
)
2831 as_warn (_("Failed to find real start of function: %s\n"), name
);
2832 new_target
= symbolP
;
2840 opcode_select (int width
)
2847 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2848 as_bad (_("selected processor does not support THUMB opcodes"));
2851 /* No need to force the alignment, since we will have been
2852 coming from ARM mode, which is word-aligned. */
2853 record_alignment (now_seg
, 1);
2860 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2861 as_bad (_("selected processor does not support ARM opcodes"));
2866 frag_align (2, 0, 0);
2868 record_alignment (now_seg
, 1);
2873 as_bad (_("invalid instruction size selected (%d)"), width
);
2878 s_arm (int ignore ATTRIBUTE_UNUSED
)
2881 demand_empty_rest_of_line ();
2885 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2888 demand_empty_rest_of_line ();
2892 s_code (int unused ATTRIBUTE_UNUSED
)
2896 temp
= get_absolute_expression ();
2901 opcode_select (temp
);
2905 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2910 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2912 /* If we are not already in thumb mode go into it, EVEN if
2913 the target processor does not support thumb instructions.
2914 This is used by gcc/config/arm/lib1funcs.asm for example
2915 to compile interworking support functions even if the
2916 target processor should not support interworking. */
2920 record_alignment (now_seg
, 1);
2923 demand_empty_rest_of_line ();
2927 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2931 /* The following label is the name/address of the start of a Thumb function.
2932 We need to know this for the interworking support. */
2933 label_is_thumb_function_name
= TRUE
;
2936 /* Perform a .set directive, but also mark the alias as
2937 being a thumb function. */
2940 s_thumb_set (int equiv
)
2942 /* XXX the following is a duplicate of the code for s_set() in read.c
2943 We cannot just call that code as we need to get at the symbol that
2950 /* Especial apologies for the random logic:
2951 This just grew, and could be parsed much more simply!
2953 delim
= get_symbol_name (& name
);
2954 end_name
= input_line_pointer
;
2955 (void) restore_line_pointer (delim
);
2957 if (*input_line_pointer
!= ',')
2960 as_bad (_("expected comma after name \"%s\""), name
);
2962 ignore_rest_of_line ();
2966 input_line_pointer
++;
2969 if (name
[0] == '.' && name
[1] == '\0')
2971 /* XXX - this should not happen to .thumb_set. */
2975 if ((symbolP
= symbol_find (name
)) == NULL
2976 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2979 /* When doing symbol listings, play games with dummy fragments living
2980 outside the normal fragment chain to record the file and line info
2982 if (listing
& LISTING_SYMBOLS
)
2984 extern struct list_info_struct
* listing_tail
;
2985 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2987 memset (dummy_frag
, 0, sizeof (fragS
));
2988 dummy_frag
->fr_type
= rs_fill
;
2989 dummy_frag
->line
= listing_tail
;
2990 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2991 dummy_frag
->fr_symbol
= symbolP
;
2995 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2998 /* "set" symbols are local unless otherwise specified. */
2999 SF_SET_LOCAL (symbolP
);
3000 #endif /* OBJ_COFF */
3001 } /* Make a new symbol. */
3003 symbol_table_insert (symbolP
);
3008 && S_IS_DEFINED (symbolP
)
3009 && S_GET_SEGMENT (symbolP
) != reg_section
)
3010 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3012 pseudo_set (symbolP
);
3014 demand_empty_rest_of_line ();
3016 /* XXX Now we come to the Thumb specific bit of code. */
3018 THUMB_SET_FUNC (symbolP
, 1);
3019 ARM_SET_THUMB (symbolP
, 1);
3020 #if defined OBJ_ELF || defined OBJ_COFF
3021 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3025 /* Directives: Mode selection. */
3027 /* .syntax [unified|divided] - choose the new unified syntax
3028 (same for Arm and Thumb encoding, modulo slight differences in what
3029 can be represented) or the old divergent syntax for each mode. */
3031 s_syntax (int unused ATTRIBUTE_UNUSED
)
3035 delim
= get_symbol_name (& name
);
3037 if (!strcasecmp (name
, "unified"))
3038 unified_syntax
= TRUE
;
3039 else if (!strcasecmp (name
, "divided"))
3040 unified_syntax
= FALSE
;
3043 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3046 (void) restore_line_pointer (delim
);
3047 demand_empty_rest_of_line ();
3050 /* Directives: sectioning and alignment. */
3053 s_bss (int ignore ATTRIBUTE_UNUSED
)
3055 /* We don't support putting frags in the BSS segment, we fake it by
3056 marking in_bss, then looking at s_skip for clues. */
3057 subseg_set (bss_section
, 0);
3058 demand_empty_rest_of_line ();
3060 #ifdef md_elf_section_change_hook
3061 md_elf_section_change_hook ();
3066 s_even (int ignore ATTRIBUTE_UNUSED
)
3068 /* Never make frag if expect extra pass. */
3070 frag_align (1, 0, 0);
3072 record_alignment (now_seg
, 1);
3074 demand_empty_rest_of_line ();
3077 /* Directives: CodeComposer Studio. */
3079 /* .ref (for CodeComposer Studio syntax only). */
3081 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3083 if (codecomposer_syntax
)
3084 ignore_rest_of_line ();
3086 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3089 /* If name is not NULL, then it is used for marking the beginning of a
3090 function, whereas if it is NULL then it means the function end. */
3092 asmfunc_debug (const char * name
)
3094 static const char * last_name
= NULL
;
3098 gas_assert (last_name
== NULL
);
3101 if (debug_type
== DEBUG_STABS
)
3102 stabs_generate_asm_func (name
, name
);
3106 gas_assert (last_name
!= NULL
);
3108 if (debug_type
== DEBUG_STABS
)
3109 stabs_generate_asm_endfunc (last_name
, last_name
);
3116 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3118 if (codecomposer_syntax
)
3120 switch (asmfunc_state
)
3122 case OUTSIDE_ASMFUNC
:
3123 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3126 case WAITING_ASMFUNC_NAME
:
3127 as_bad (_(".asmfunc repeated."));
3130 case WAITING_ENDASMFUNC
:
3131 as_bad (_(".asmfunc without function."));
3134 demand_empty_rest_of_line ();
3137 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3141 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3143 if (codecomposer_syntax
)
3145 switch (asmfunc_state
)
3147 case OUTSIDE_ASMFUNC
:
3148 as_bad (_(".endasmfunc without a .asmfunc."));
3151 case WAITING_ASMFUNC_NAME
:
3152 as_bad (_(".endasmfunc without function."));
3155 case WAITING_ENDASMFUNC
:
3156 asmfunc_state
= OUTSIDE_ASMFUNC
;
3157 asmfunc_debug (NULL
);
3160 demand_empty_rest_of_line ();
3163 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3167 s_ccs_def (int name
)
3169 if (codecomposer_syntax
)
3172 as_bad (_(".def pseudo-op only available with -mccs flag."));
3175 /* Directives: Literal pools. */
3177 static literal_pool
*
3178 find_literal_pool (void)
3180 literal_pool
* pool
;
3182 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3184 if (pool
->section
== now_seg
3185 && pool
->sub_section
== now_subseg
)
3192 static literal_pool
*
3193 find_or_make_literal_pool (void)
3195 /* Next literal pool ID number. */
3196 static unsigned int latest_pool_num
= 1;
3197 literal_pool
* pool
;
3199 pool
= find_literal_pool ();
3203 /* Create a new pool. */
3204 pool
= XNEW (literal_pool
);
3208 pool
->next_free_entry
= 0;
3209 pool
->section
= now_seg
;
3210 pool
->sub_section
= now_subseg
;
3211 pool
->next
= list_of_pools
;
3212 pool
->symbol
= NULL
;
3213 pool
->alignment
= 2;
3215 /* Add it to the list. */
3216 list_of_pools
= pool
;
3219 /* New pools, and emptied pools, will have a NULL symbol. */
3220 if (pool
->symbol
== NULL
)
3222 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3223 (valueT
) 0, &zero_address_frag
);
3224 pool
->id
= latest_pool_num
++;
3231 /* Add the literal in the global 'inst'
3232 structure to the relevant literal pool. */
3235 add_to_lit_pool (unsigned int nbytes
)
3237 #define PADDING_SLOT 0x1
3238 #define LIT_ENTRY_SIZE_MASK 0xFF
3239 literal_pool
* pool
;
3240 unsigned int entry
, pool_size
= 0;
3241 bfd_boolean padding_slot_p
= FALSE
;
3247 imm1
= inst
.operands
[1].imm
;
3248 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3249 : inst
.reloc
.exp
.X_unsigned
? 0
3250 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3251 if (target_big_endian
)
3254 imm2
= inst
.operands
[1].imm
;
3258 pool
= find_or_make_literal_pool ();
3260 /* Check if this literal value is already in the pool. */
3261 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3265 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3266 && (inst
.reloc
.exp
.X_op
== O_constant
)
3267 && (pool
->literals
[entry
].X_add_number
3268 == inst
.reloc
.exp
.X_add_number
)
3269 && (pool
->literals
[entry
].X_md
== nbytes
)
3270 && (pool
->literals
[entry
].X_unsigned
3271 == inst
.reloc
.exp
.X_unsigned
))
3274 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3275 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3276 && (pool
->literals
[entry
].X_add_number
3277 == inst
.reloc
.exp
.X_add_number
)
3278 && (pool
->literals
[entry
].X_add_symbol
3279 == inst
.reloc
.exp
.X_add_symbol
)
3280 && (pool
->literals
[entry
].X_op_symbol
3281 == inst
.reloc
.exp
.X_op_symbol
)
3282 && (pool
->literals
[entry
].X_md
== nbytes
))
3285 else if ((nbytes
== 8)
3286 && !(pool_size
& 0x7)
3287 && ((entry
+ 1) != pool
->next_free_entry
)
3288 && (pool
->literals
[entry
].X_op
== O_constant
)
3289 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3290 && (pool
->literals
[entry
].X_unsigned
3291 == inst
.reloc
.exp
.X_unsigned
)
3292 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3293 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3294 && (pool
->literals
[entry
+ 1].X_unsigned
3295 == inst
.reloc
.exp
.X_unsigned
))
3298 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3299 if (padding_slot_p
&& (nbytes
== 4))
3305 /* Do we need to create a new entry? */
3306 if (entry
== pool
->next_free_entry
)
3308 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3310 inst
.error
= _("literal pool overflow");
3316 /* For 8-byte entries, we align to an 8-byte boundary,
3317 and split it into two 4-byte entries, because on 32-bit
3318 host, 8-byte constants are treated as big num, thus
3319 saved in "generic_bignum" which will be overwritten
3320 by later assignments.
3322 We also need to make sure there is enough space for
3325 We also check to make sure the literal operand is a
3327 if (!(inst
.reloc
.exp
.X_op
== O_constant
3328 || inst
.reloc
.exp
.X_op
== O_big
))
3330 inst
.error
= _("invalid type for literal pool");
3333 else if (pool_size
& 0x7)
3335 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3337 inst
.error
= _("literal pool overflow");
3341 pool
->literals
[entry
] = inst
.reloc
.exp
;
3342 pool
->literals
[entry
].X_op
= O_constant
;
3343 pool
->literals
[entry
].X_add_number
= 0;
3344 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3345 pool
->next_free_entry
+= 1;
3348 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3350 inst
.error
= _("literal pool overflow");
3354 pool
->literals
[entry
] = inst
.reloc
.exp
;
3355 pool
->literals
[entry
].X_op
= O_constant
;
3356 pool
->literals
[entry
].X_add_number
= imm1
;
3357 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3358 pool
->literals
[entry
++].X_md
= 4;
3359 pool
->literals
[entry
] = inst
.reloc
.exp
;
3360 pool
->literals
[entry
].X_op
= O_constant
;
3361 pool
->literals
[entry
].X_add_number
= imm2
;
3362 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3363 pool
->literals
[entry
].X_md
= 4;
3364 pool
->alignment
= 3;
3365 pool
->next_free_entry
+= 1;
3369 pool
->literals
[entry
] = inst
.reloc
.exp
;
3370 pool
->literals
[entry
].X_md
= 4;
3374 /* PR ld/12974: Record the location of the first source line to reference
3375 this entry in the literal pool. If it turns out during linking that the
3376 symbol does not exist we will be able to give an accurate line number for
3377 the (first use of the) missing reference. */
3378 if (debug_type
== DEBUG_DWARF2
)
3379 dwarf2_where (pool
->locs
+ entry
);
3381 pool
->next_free_entry
+= 1;
3383 else if (padding_slot_p
)
3385 pool
->literals
[entry
] = inst
.reloc
.exp
;
3386 pool
->literals
[entry
].X_md
= nbytes
;
3389 inst
.reloc
.exp
.X_op
= O_symbol
;
3390 inst
.reloc
.exp
.X_add_number
= pool_size
;
3391 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3397 tc_start_label_without_colon (void)
3399 bfd_boolean ret
= TRUE
;
3401 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3403 const char *label
= input_line_pointer
;
3405 while (!is_end_of_line
[(int) label
[-1]])
3410 as_bad (_("Invalid label '%s'"), label
);
3414 asmfunc_debug (label
);
3416 asmfunc_state
= WAITING_ENDASMFUNC
;
3422 /* Can't use symbol_new here, so have to create a symbol and then at
3423 a later date assign it a value. That's what these functions do. */
3426 symbol_locate (symbolS
* symbolP
,
3427 const char * name
, /* It is copied, the caller can modify. */
3428 segT segment
, /* Segment identifier (SEG_<something>). */
3429 valueT valu
, /* Symbol value. */
3430 fragS
* frag
) /* Associated fragment. */
3433 char * preserved_copy_of_name
;
3435 name_length
= strlen (name
) + 1; /* +1 for \0. */
3436 obstack_grow (¬es
, name
, name_length
);
3437 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3439 #ifdef tc_canonicalize_symbol_name
3440 preserved_copy_of_name
=
3441 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3444 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3446 S_SET_SEGMENT (symbolP
, segment
);
3447 S_SET_VALUE (symbolP
, valu
);
3448 symbol_clear_list_pointers (symbolP
);
3450 symbol_set_frag (symbolP
, frag
);
3452 /* Link to end of symbol chain. */
3454 extern int symbol_table_frozen
;
3456 if (symbol_table_frozen
)
3460 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3462 obj_symbol_new_hook (symbolP
);
3464 #ifdef tc_symbol_new_hook
3465 tc_symbol_new_hook (symbolP
);
3469 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3470 #endif /* DEBUG_SYMS */
3474 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3477 literal_pool
* pool
;
3480 pool
= find_literal_pool ();
3482 || pool
->symbol
== NULL
3483 || pool
->next_free_entry
== 0)
3486 /* Align pool as you have word accesses.
3487 Only make a frag if we have to. */
3489 frag_align (pool
->alignment
, 0, 0);
3491 record_alignment (now_seg
, 2);
3494 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3495 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3497 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3499 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3500 (valueT
) frag_now_fix (), frag_now
);
3501 symbol_table_insert (pool
->symbol
);
3503 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3505 #if defined OBJ_COFF || defined OBJ_ELF
3506 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3509 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3512 if (debug_type
== DEBUG_DWARF2
)
3513 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3515 /* First output the expression in the instruction to the pool. */
3516 emit_expr (&(pool
->literals
[entry
]),
3517 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3520 /* Mark the pool as empty. */
3521 pool
->next_free_entry
= 0;
3522 pool
->symbol
= NULL
;
3526 /* Forward declarations for functions below, in the MD interface
3528 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3529 static valueT
create_unwind_entry (int);
3530 static void start_unwind_section (const segT
, int);
3531 static void add_unwind_opcode (valueT
, int);
3532 static void flush_pending_unwind (void);
3534 /* Directives: Data. */
3537 s_arm_elf_cons (int nbytes
)
3541 #ifdef md_flush_pending_output
3542 md_flush_pending_output ();
3545 if (is_it_end_of_statement ())
3547 demand_empty_rest_of_line ();
3551 #ifdef md_cons_align
3552 md_cons_align (nbytes
);
3555 mapping_state (MAP_DATA
);
3559 char *base
= input_line_pointer
;
3563 if (exp
.X_op
!= O_symbol
)
3564 emit_expr (&exp
, (unsigned int) nbytes
);
3567 char *before_reloc
= input_line_pointer
;
3568 reloc
= parse_reloc (&input_line_pointer
);
3571 as_bad (_("unrecognized relocation suffix"));
3572 ignore_rest_of_line ();
3575 else if (reloc
== BFD_RELOC_UNUSED
)
3576 emit_expr (&exp
, (unsigned int) nbytes
);
3579 reloc_howto_type
*howto
= (reloc_howto_type
*)
3580 bfd_reloc_type_lookup (stdoutput
,
3581 (bfd_reloc_code_real_type
) reloc
);
3582 int size
= bfd_get_reloc_size (howto
);
3584 if (reloc
== BFD_RELOC_ARM_PLT32
)
3586 as_bad (_("(plt) is only valid on branch targets"));
3587 reloc
= BFD_RELOC_UNUSED
;
3592 as_bad (ngettext ("%s relocations do not fit in %d byte",
3593 "%s relocations do not fit in %d bytes",
3595 howto
->name
, nbytes
);
3598 /* We've parsed an expression stopping at O_symbol.
3599 But there may be more expression left now that we
3600 have parsed the relocation marker. Parse it again.
3601 XXX Surely there is a cleaner way to do this. */
3602 char *p
= input_line_pointer
;
3604 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3606 memcpy (save_buf
, base
, input_line_pointer
- base
);
3607 memmove (base
+ (input_line_pointer
- before_reloc
),
3608 base
, before_reloc
- base
);
3610 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3612 memcpy (base
, save_buf
, p
- base
);
3614 offset
= nbytes
- size
;
3615 p
= frag_more (nbytes
);
3616 memset (p
, 0, nbytes
);
3617 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3618 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3624 while (*input_line_pointer
++ == ',');
3626 /* Put terminator back into stream. */
3627 input_line_pointer
--;
3628 demand_empty_rest_of_line ();
3631 /* Emit an expression containing a 32-bit thumb instruction.
3632 Implementation based on put_thumb32_insn. */
3635 emit_thumb32_expr (expressionS
* exp
)
3637 expressionS exp_high
= *exp
;
3639 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3640 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3641 exp
->X_add_number
&= 0xffff;
3642 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3645 /* Guess the instruction size based on the opcode. */
3648 thumb_insn_size (int opcode
)
3650 if ((unsigned int) opcode
< 0xe800u
)
3652 else if ((unsigned int) opcode
>= 0xe8000000u
)
3659 emit_insn (expressionS
*exp
, int nbytes
)
3663 if (exp
->X_op
== O_constant
)
3668 size
= thumb_insn_size (exp
->X_add_number
);
3672 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3674 as_bad (_(".inst.n operand too big. "\
3675 "Use .inst.w instead"));
3680 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3681 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3683 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3685 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3686 emit_thumb32_expr (exp
);
3688 emit_expr (exp
, (unsigned int) size
);
3690 it_fsm_post_encode ();
3694 as_bad (_("cannot determine Thumb instruction size. " \
3695 "Use .inst.n/.inst.w instead"));
3698 as_bad (_("constant expression required"));
3703 /* Like s_arm_elf_cons but do not use md_cons_align and
3704 set the mapping state to MAP_ARM/MAP_THUMB. */
3707 s_arm_elf_inst (int nbytes
)
3709 if (is_it_end_of_statement ())
3711 demand_empty_rest_of_line ();
3715 /* Calling mapping_state () here will not change ARM/THUMB,
3716 but will ensure not to be in DATA state. */
3719 mapping_state (MAP_THUMB
);
3724 as_bad (_("width suffixes are invalid in ARM mode"));
3725 ignore_rest_of_line ();
3731 mapping_state (MAP_ARM
);
3740 if (! emit_insn (& exp
, nbytes
))
3742 ignore_rest_of_line ();
3746 while (*input_line_pointer
++ == ',');
3748 /* Put terminator back into stream. */
3749 input_line_pointer
--;
3750 demand_empty_rest_of_line ();
3753 /* Parse a .rel31 directive. */
3756 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3763 if (*input_line_pointer
== '1')
3764 highbit
= 0x80000000;
3765 else if (*input_line_pointer
!= '0')
3766 as_bad (_("expected 0 or 1"));
3768 input_line_pointer
++;
3769 if (*input_line_pointer
!= ',')
3770 as_bad (_("missing comma"));
3771 input_line_pointer
++;
3773 #ifdef md_flush_pending_output
3774 md_flush_pending_output ();
3777 #ifdef md_cons_align
3781 mapping_state (MAP_DATA
);
3786 md_number_to_chars (p
, highbit
, 4);
3787 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3788 BFD_RELOC_ARM_PREL31
);
3790 demand_empty_rest_of_line ();
3793 /* Directives: AEABI stack-unwind tables. */
3795 /* Parse an unwind_fnstart directive. Simply records the current location. */
3798 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3800 demand_empty_rest_of_line ();
3801 if (unwind
.proc_start
)
3803 as_bad (_("duplicate .fnstart directive"));
3807 /* Mark the start of the function. */
3808 unwind
.proc_start
= expr_build_dot ();
3810 /* Reset the rest of the unwind info. */
3811 unwind
.opcode_count
= 0;
3812 unwind
.table_entry
= NULL
;
3813 unwind
.personality_routine
= NULL
;
3814 unwind
.personality_index
= -1;
3815 unwind
.frame_size
= 0;
3816 unwind
.fp_offset
= 0;
3817 unwind
.fp_reg
= REG_SP
;
3819 unwind
.sp_restored
= 0;
3823 /* Parse a handlerdata directive. Creates the exception handling table entry
3824 for the function. */
3827 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3829 demand_empty_rest_of_line ();
3830 if (!unwind
.proc_start
)
3831 as_bad (MISSING_FNSTART
);
3833 if (unwind
.table_entry
)
3834 as_bad (_("duplicate .handlerdata directive"));
3836 create_unwind_entry (1);
3839 /* Parse an unwind_fnend directive. Generates the index table entry. */
3842 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3847 unsigned int marked_pr_dependency
;
3849 demand_empty_rest_of_line ();
3851 if (!unwind
.proc_start
)
3853 as_bad (_(".fnend directive without .fnstart"));
3857 /* Add eh table entry. */
3858 if (unwind
.table_entry
== NULL
)
3859 val
= create_unwind_entry (0);
3863 /* Add index table entry. This is two words. */
3864 start_unwind_section (unwind
.saved_seg
, 1);
3865 frag_align (2, 0, 0);
3866 record_alignment (now_seg
, 2);
3868 ptr
= frag_more (8);
3870 where
= frag_now_fix () - 8;
3872 /* Self relative offset of the function start. */
3873 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3874 BFD_RELOC_ARM_PREL31
);
3876 /* Indicate dependency on EHABI-defined personality routines to the
3877 linker, if it hasn't been done already. */
3878 marked_pr_dependency
3879 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3880 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3881 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3883 static const char *const name
[] =
3885 "__aeabi_unwind_cpp_pr0",
3886 "__aeabi_unwind_cpp_pr1",
3887 "__aeabi_unwind_cpp_pr2"
3889 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3890 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3891 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3892 |= 1 << unwind
.personality_index
;
3896 /* Inline exception table entry. */
3897 md_number_to_chars (ptr
+ 4, val
, 4);
3899 /* Self relative offset of the table entry. */
3900 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3901 BFD_RELOC_ARM_PREL31
);
3903 /* Restore the original section. */
3904 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3906 unwind
.proc_start
= NULL
;
3910 /* Parse an unwind_cantunwind directive. */
3913 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3915 demand_empty_rest_of_line ();
3916 if (!unwind
.proc_start
)
3917 as_bad (MISSING_FNSTART
);
3919 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3920 as_bad (_("personality routine specified for cantunwind frame"));
3922 unwind
.personality_index
= -2;
3926 /* Parse a personalityindex directive. */
3929 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3933 if (!unwind
.proc_start
)
3934 as_bad (MISSING_FNSTART
);
3936 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3937 as_bad (_("duplicate .personalityindex directive"));
3941 if (exp
.X_op
!= O_constant
3942 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3944 as_bad (_("bad personality routine number"));
3945 ignore_rest_of_line ();
3949 unwind
.personality_index
= exp
.X_add_number
;
3951 demand_empty_rest_of_line ();
3955 /* Parse a personality directive. */
3958 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3962 if (!unwind
.proc_start
)
3963 as_bad (MISSING_FNSTART
);
3965 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3966 as_bad (_("duplicate .personality directive"));
3968 c
= get_symbol_name (& name
);
3969 p
= input_line_pointer
;
3971 ++ input_line_pointer
;
3972 unwind
.personality_routine
= symbol_find_or_make (name
);
3974 demand_empty_rest_of_line ();
3978 /* Parse a directive saving core registers. */
3981 s_arm_unwind_save_core (void)
3987 range
= parse_reg_list (&input_line_pointer
);
3990 as_bad (_("expected register list"));
3991 ignore_rest_of_line ();
3995 demand_empty_rest_of_line ();
3997 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3998 into .unwind_save {..., sp...}. We aren't bothered about the value of
3999 ip because it is clobbered by calls. */
4000 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4001 && (range
& 0x3000) == 0x1000)
4003 unwind
.opcode_count
--;
4004 unwind
.sp_restored
= 0;
4005 range
= (range
| 0x2000) & ~0x1000;
4006 unwind
.pending_offset
= 0;
4012 /* See if we can use the short opcodes. These pop a block of up to 8
4013 registers starting with r4, plus maybe r14. */
4014 for (n
= 0; n
< 8; n
++)
4016 /* Break at the first non-saved register. */
4017 if ((range
& (1 << (n
+ 4))) == 0)
4020 /* See if there are any other bits set. */
4021 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4023 /* Use the long form. */
4024 op
= 0x8000 | ((range
>> 4) & 0xfff);
4025 add_unwind_opcode (op
, 2);
4029 /* Use the short form. */
4031 op
= 0xa8; /* Pop r14. */
4033 op
= 0xa0; /* Do not pop r14. */
4035 add_unwind_opcode (op
, 1);
4042 op
= 0xb100 | (range
& 0xf);
4043 add_unwind_opcode (op
, 2);
4046 /* Record the number of bytes pushed. */
4047 for (n
= 0; n
< 16; n
++)
4049 if (range
& (1 << n
))
4050 unwind
.frame_size
+= 4;
4055 /* Parse a directive saving FPA registers. */
4058 s_arm_unwind_save_fpa (int reg
)
4064 /* Get Number of registers to transfer. */
4065 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4068 exp
.X_op
= O_illegal
;
4070 if (exp
.X_op
!= O_constant
)
4072 as_bad (_("expected , <constant>"));
4073 ignore_rest_of_line ();
4077 num_regs
= exp
.X_add_number
;
4079 if (num_regs
< 1 || num_regs
> 4)
4081 as_bad (_("number of registers must be in the range [1:4]"));
4082 ignore_rest_of_line ();
4086 demand_empty_rest_of_line ();
4091 op
= 0xb4 | (num_regs
- 1);
4092 add_unwind_opcode (op
, 1);
4097 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4098 add_unwind_opcode (op
, 2);
4100 unwind
.frame_size
+= num_regs
* 12;
4104 /* Parse a directive saving VFP registers for ARMv6 and above. */
4107 s_arm_unwind_save_vfp_armv6 (void)
4112 int num_vfpv3_regs
= 0;
4113 int num_regs_below_16
;
4115 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4118 as_bad (_("expected register list"));
4119 ignore_rest_of_line ();
4123 demand_empty_rest_of_line ();
4125 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4126 than FSTMX/FLDMX-style ones). */
4128 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4130 num_vfpv3_regs
= count
;
4131 else if (start
+ count
> 16)
4132 num_vfpv3_regs
= start
+ count
- 16;
4134 if (num_vfpv3_regs
> 0)
4136 int start_offset
= start
> 16 ? start
- 16 : 0;
4137 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4138 add_unwind_opcode (op
, 2);
4141 /* Generate opcode for registers numbered in the range 0 .. 15. */
4142 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4143 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4144 if (num_regs_below_16
> 0)
4146 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4147 add_unwind_opcode (op
, 2);
4150 unwind
.frame_size
+= count
* 8;
4154 /* Parse a directive saving VFP registers for pre-ARMv6. */
4157 s_arm_unwind_save_vfp (void)
4163 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4166 as_bad (_("expected register list"));
4167 ignore_rest_of_line ();
4171 demand_empty_rest_of_line ();
4176 op
= 0xb8 | (count
- 1);
4177 add_unwind_opcode (op
, 1);
4182 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4183 add_unwind_opcode (op
, 2);
4185 unwind
.frame_size
+= count
* 8 + 4;
4189 /* Parse a directive saving iWMMXt data registers. */
4192 s_arm_unwind_save_mmxwr (void)
4200 if (*input_line_pointer
== '{')
4201 input_line_pointer
++;
4205 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4209 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4214 as_tsktsk (_("register list not in ascending order"));
4217 if (*input_line_pointer
== '-')
4219 input_line_pointer
++;
4220 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4223 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4226 else if (reg
>= hi_reg
)
4228 as_bad (_("bad register range"));
4231 for (; reg
< hi_reg
; reg
++)
4235 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4237 skip_past_char (&input_line_pointer
, '}');
4239 demand_empty_rest_of_line ();
4241 /* Generate any deferred opcodes because we're going to be looking at
4243 flush_pending_unwind ();
4245 for (i
= 0; i
< 16; i
++)
4247 if (mask
& (1 << i
))
4248 unwind
.frame_size
+= 8;
4251 /* Attempt to combine with a previous opcode. We do this because gcc
4252 likes to output separate unwind directives for a single block of
4254 if (unwind
.opcode_count
> 0)
4256 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4257 if ((i
& 0xf8) == 0xc0)
4260 /* Only merge if the blocks are contiguous. */
4263 if ((mask
& 0xfe00) == (1 << 9))
4265 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4266 unwind
.opcode_count
--;
4269 else if (i
== 6 && unwind
.opcode_count
>= 2)
4271 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4275 op
= 0xffff << (reg
- 1);
4277 && ((mask
& op
) == (1u << (reg
- 1))))
4279 op
= (1 << (reg
+ i
+ 1)) - 1;
4280 op
&= ~((1 << reg
) - 1);
4282 unwind
.opcode_count
-= 2;
4289 /* We want to generate opcodes in the order the registers have been
4290 saved, ie. descending order. */
4291 for (reg
= 15; reg
>= -1; reg
--)
4293 /* Save registers in blocks. */
4295 || !(mask
& (1 << reg
)))
4297 /* We found an unsaved reg. Generate opcodes to save the
4304 op
= 0xc0 | (hi_reg
- 10);
4305 add_unwind_opcode (op
, 1);
4310 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4311 add_unwind_opcode (op
, 2);
4320 ignore_rest_of_line ();
4324 s_arm_unwind_save_mmxwcg (void)
4331 if (*input_line_pointer
== '{')
4332 input_line_pointer
++;
4334 skip_whitespace (input_line_pointer
);
4338 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4342 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4348 as_tsktsk (_("register list not in ascending order"));
4351 if (*input_line_pointer
== '-')
4353 input_line_pointer
++;
4354 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4357 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4360 else if (reg
>= hi_reg
)
4362 as_bad (_("bad register range"));
4365 for (; reg
< hi_reg
; reg
++)
4369 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4371 skip_past_char (&input_line_pointer
, '}');
4373 demand_empty_rest_of_line ();
4375 /* Generate any deferred opcodes because we're going to be looking at
4377 flush_pending_unwind ();
4379 for (reg
= 0; reg
< 16; reg
++)
4381 if (mask
& (1 << reg
))
4382 unwind
.frame_size
+= 4;
4385 add_unwind_opcode (op
, 2);
4388 ignore_rest_of_line ();
4392 /* Parse an unwind_save directive.
4393 If the argument is non-zero, this is a .vsave directive. */
4396 s_arm_unwind_save (int arch_v6
)
4399 struct reg_entry
*reg
;
4400 bfd_boolean had_brace
= FALSE
;
4402 if (!unwind
.proc_start
)
4403 as_bad (MISSING_FNSTART
);
4405 /* Figure out what sort of save we have. */
4406 peek
= input_line_pointer
;
4414 reg
= arm_reg_parse_multi (&peek
);
4418 as_bad (_("register expected"));
4419 ignore_rest_of_line ();
4428 as_bad (_("FPA .unwind_save does not take a register list"));
4429 ignore_rest_of_line ();
4432 input_line_pointer
= peek
;
4433 s_arm_unwind_save_fpa (reg
->number
);
4437 s_arm_unwind_save_core ();
4442 s_arm_unwind_save_vfp_armv6 ();
4444 s_arm_unwind_save_vfp ();
4447 case REG_TYPE_MMXWR
:
4448 s_arm_unwind_save_mmxwr ();
4451 case REG_TYPE_MMXWCG
:
4452 s_arm_unwind_save_mmxwcg ();
4456 as_bad (_(".unwind_save does not support this kind of register"));
4457 ignore_rest_of_line ();
4462 /* Parse an unwind_movsp directive. */
4465 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4471 if (!unwind
.proc_start
)
4472 as_bad (MISSING_FNSTART
);
4474 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4477 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4478 ignore_rest_of_line ();
4482 /* Optional constant. */
4483 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4485 if (immediate_for_directive (&offset
) == FAIL
)
4491 demand_empty_rest_of_line ();
4493 if (reg
== REG_SP
|| reg
== REG_PC
)
4495 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4499 if (unwind
.fp_reg
!= REG_SP
)
4500 as_bad (_("unexpected .unwind_movsp directive"));
4502 /* Generate opcode to restore the value. */
4504 add_unwind_opcode (op
, 1);
4506 /* Record the information for later. */
4507 unwind
.fp_reg
= reg
;
4508 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4509 unwind
.sp_restored
= 1;
4512 /* Parse an unwind_pad directive. */
4515 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4519 if (!unwind
.proc_start
)
4520 as_bad (MISSING_FNSTART
);
4522 if (immediate_for_directive (&offset
) == FAIL
)
4527 as_bad (_("stack increment must be multiple of 4"));
4528 ignore_rest_of_line ();
4532 /* Don't generate any opcodes, just record the details for later. */
4533 unwind
.frame_size
+= offset
;
4534 unwind
.pending_offset
+= offset
;
4536 demand_empty_rest_of_line ();
4539 /* Parse an unwind_setfp directive. */
4542 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4548 if (!unwind
.proc_start
)
4549 as_bad (MISSING_FNSTART
);
4551 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4552 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4555 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4557 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4559 as_bad (_("expected <reg>, <reg>"));
4560 ignore_rest_of_line ();
4564 /* Optional constant. */
4565 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4567 if (immediate_for_directive (&offset
) == FAIL
)
4573 demand_empty_rest_of_line ();
4575 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4577 as_bad (_("register must be either sp or set by a previous"
4578 "unwind_movsp directive"));
4582 /* Don't generate any opcodes, just record the information for later. */
4583 unwind
.fp_reg
= fp_reg
;
4585 if (sp_reg
== REG_SP
)
4586 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4588 unwind
.fp_offset
-= offset
;
4591 /* Parse an unwind_raw directive. */
4594 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4597 /* This is an arbitrary limit. */
4598 unsigned char op
[16];
4601 if (!unwind
.proc_start
)
4602 as_bad (MISSING_FNSTART
);
4605 if (exp
.X_op
== O_constant
4606 && skip_past_comma (&input_line_pointer
) != FAIL
)
4608 unwind
.frame_size
+= exp
.X_add_number
;
4612 exp
.X_op
= O_illegal
;
4614 if (exp
.X_op
!= O_constant
)
4616 as_bad (_("expected <offset>, <opcode>"));
4617 ignore_rest_of_line ();
4623 /* Parse the opcode. */
4628 as_bad (_("unwind opcode too long"));
4629 ignore_rest_of_line ();
4631 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4633 as_bad (_("invalid unwind opcode"));
4634 ignore_rest_of_line ();
4637 op
[count
++] = exp
.X_add_number
;
4639 /* Parse the next byte. */
4640 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4646 /* Add the opcode bytes in reverse order. */
4648 add_unwind_opcode (op
[count
], 1);
4650 demand_empty_rest_of_line ();
4654 /* Parse a .eabi_attribute directive. */
4657 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4659 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4661 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4662 attributes_set_explicitly
[tag
] = 1;
4665 /* Emit a tls fix for the symbol. */
4668 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4672 #ifdef md_flush_pending_output
4673 md_flush_pending_output ();
4676 #ifdef md_cons_align
4680 /* Since we're just labelling the code, there's no need to define a
4683 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4684 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4685 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4686 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4688 #endif /* OBJ_ELF */
4690 static void s_arm_arch (int);
4691 static void s_arm_object_arch (int);
4692 static void s_arm_cpu (int);
4693 static void s_arm_fpu (int);
4694 static void s_arm_arch_extension (int);
4699 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4706 if (exp
.X_op
== O_symbol
)
4707 exp
.X_op
= O_secrel
;
4709 emit_expr (&exp
, 4);
4711 while (*input_line_pointer
++ == ',');
4713 input_line_pointer
--;
4714 demand_empty_rest_of_line ();
4718 /* This table describes all the machine specific pseudo-ops the assembler
4719 has to support. The fields are:
4720 pseudo-op name without dot
4721 function to call to execute this pseudo-op
4722 Integer arg to pass to the function. */
4724 const pseudo_typeS md_pseudo_table
[] =
4726 /* Never called because '.req' does not start a line. */
4727 { "req", s_req
, 0 },
4728 /* Following two are likewise never called. */
4731 { "unreq", s_unreq
, 0 },
4732 { "bss", s_bss
, 0 },
4733 { "align", s_align_ptwo
, 2 },
4734 { "arm", s_arm
, 0 },
4735 { "thumb", s_thumb
, 0 },
4736 { "code", s_code
, 0 },
4737 { "force_thumb", s_force_thumb
, 0 },
4738 { "thumb_func", s_thumb_func
, 0 },
4739 { "thumb_set", s_thumb_set
, 0 },
4740 { "even", s_even
, 0 },
4741 { "ltorg", s_ltorg
, 0 },
4742 { "pool", s_ltorg
, 0 },
4743 { "syntax", s_syntax
, 0 },
4744 { "cpu", s_arm_cpu
, 0 },
4745 { "arch", s_arm_arch
, 0 },
4746 { "object_arch", s_arm_object_arch
, 0 },
4747 { "fpu", s_arm_fpu
, 0 },
4748 { "arch_extension", s_arm_arch_extension
, 0 },
4750 { "word", s_arm_elf_cons
, 4 },
4751 { "long", s_arm_elf_cons
, 4 },
4752 { "inst.n", s_arm_elf_inst
, 2 },
4753 { "inst.w", s_arm_elf_inst
, 4 },
4754 { "inst", s_arm_elf_inst
, 0 },
4755 { "rel31", s_arm_rel31
, 0 },
4756 { "fnstart", s_arm_unwind_fnstart
, 0 },
4757 { "fnend", s_arm_unwind_fnend
, 0 },
4758 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4759 { "personality", s_arm_unwind_personality
, 0 },
4760 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4761 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4762 { "save", s_arm_unwind_save
, 0 },
4763 { "vsave", s_arm_unwind_save
, 1 },
4764 { "movsp", s_arm_unwind_movsp
, 0 },
4765 { "pad", s_arm_unwind_pad
, 0 },
4766 { "setfp", s_arm_unwind_setfp
, 0 },
4767 { "unwind_raw", s_arm_unwind_raw
, 0 },
4768 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4769 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4773 /* These are used for dwarf. */
4777 /* These are used for dwarf2. */
4778 { "file", dwarf2_directive_file
, 0 },
4779 { "loc", dwarf2_directive_loc
, 0 },
4780 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4782 { "extend", float_cons
, 'x' },
4783 { "ldouble", float_cons
, 'x' },
4784 { "packed", float_cons
, 'p' },
4786 {"secrel32", pe_directive_secrel
, 0},
4789 /* These are for compatibility with CodeComposer Studio. */
4790 {"ref", s_ccs_ref
, 0},
4791 {"def", s_ccs_def
, 0},
4792 {"asmfunc", s_ccs_asmfunc
, 0},
4793 {"endasmfunc", s_ccs_endasmfunc
, 0},
4798 /* Parser functions used exclusively in instruction operands. */
4800 /* Generic immediate-value read function for use in insn parsing.
4801 STR points to the beginning of the immediate (the leading #);
4802 VAL receives the value; if the value is outside [MIN, MAX]
4803 issue an error. PREFIX_OPT is true if the immediate prefix is
4807 parse_immediate (char **str
, int *val
, int min
, int max
,
4808 bfd_boolean prefix_opt
)
4812 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4813 if (exp
.X_op
!= O_constant
)
4815 inst
.error
= _("constant expression required");
4819 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4821 inst
.error
= _("immediate value out of range");
4825 *val
= exp
.X_add_number
;
4829 /* Less-generic immediate-value read function with the possibility of loading a
4830 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4831 instructions. Puts the result directly in inst.operands[i]. */
4834 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4835 bfd_boolean allow_symbol_p
)
4838 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4841 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4843 if (exp_p
->X_op
== O_constant
)
4845 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4846 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4847 O_constant. We have to be careful not to break compilation for
4848 32-bit X_add_number, though. */
4849 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4851 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4852 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4854 inst
.operands
[i
].regisimm
= 1;
4857 else if (exp_p
->X_op
== O_big
4858 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4860 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4862 /* Bignums have their least significant bits in
4863 generic_bignum[0]. Make sure we put 32 bits in imm and
4864 32 bits in reg, in a (hopefully) portable way. */
4865 gas_assert (parts
!= 0);
4867 /* Make sure that the number is not too big.
4868 PR 11972: Bignums can now be sign-extended to the
4869 size of a .octa so check that the out of range bits
4870 are all zero or all one. */
4871 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4873 LITTLENUM_TYPE m
= -1;
4875 if (generic_bignum
[parts
* 2] != 0
4876 && generic_bignum
[parts
* 2] != m
)
4879 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4880 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4884 inst
.operands
[i
].imm
= 0;
4885 for (j
= 0; j
< parts
; j
++, idx
++)
4886 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4887 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4888 inst
.operands
[i
].reg
= 0;
4889 for (j
= 0; j
< parts
; j
++, idx
++)
4890 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4891 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4892 inst
.operands
[i
].regisimm
= 1;
4894 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4902 /* Returns the pseudo-register number of an FPA immediate constant,
4903 or FAIL if there isn't a valid constant here. */
4906 parse_fpa_immediate (char ** str
)
4908 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4914 /* First try and match exact strings, this is to guarantee
4915 that some formats will work even for cross assembly. */
4917 for (i
= 0; fp_const
[i
]; i
++)
4919 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4923 *str
+= strlen (fp_const
[i
]);
4924 if (is_end_of_line
[(unsigned char) **str
])
4930 /* Just because we didn't get a match doesn't mean that the constant
4931 isn't valid, just that it is in a format that we don't
4932 automatically recognize. Try parsing it with the standard
4933 expression routines. */
4935 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4937 /* Look for a raw floating point number. */
4938 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4939 && is_end_of_line
[(unsigned char) *save_in
])
4941 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4943 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4945 if (words
[j
] != fp_values
[i
][j
])
4949 if (j
== MAX_LITTLENUMS
)
4957 /* Try and parse a more complex expression, this will probably fail
4958 unless the code uses a floating point prefix (eg "0f"). */
4959 save_in
= input_line_pointer
;
4960 input_line_pointer
= *str
;
4961 if (expression (&exp
) == absolute_section
4962 && exp
.X_op
== O_big
4963 && exp
.X_add_number
< 0)
4965 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4967 #define X_PRECISION 5
4968 #define E_PRECISION 15L
4969 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4971 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4973 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4975 if (words
[j
] != fp_values
[i
][j
])
4979 if (j
== MAX_LITTLENUMS
)
4981 *str
= input_line_pointer
;
4982 input_line_pointer
= save_in
;
4989 *str
= input_line_pointer
;
4990 input_line_pointer
= save_in
;
4991 inst
.error
= _("invalid FPA immediate expression");
4995 /* Returns 1 if a number has "quarter-precision" float format
4996 0baBbbbbbc defgh000 00000000 00000000. */
4999 is_quarter_float (unsigned imm
)
5001 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5002 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5006 /* Detect the presence of a floating point or integer zero constant,
5010 parse_ifimm_zero (char **in
)
5014 if (!is_immediate_prefix (**in
))
5016 /* In unified syntax, all prefixes are optional. */
5017 if (!unified_syntax
)
5023 /* Accept #0x0 as a synonym for #0. */
5024 if (strncmp (*in
, "0x", 2) == 0)
5027 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5032 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5033 &generic_floating_point_number
);
5036 && generic_floating_point_number
.sign
== '+'
5037 && (generic_floating_point_number
.low
5038 > generic_floating_point_number
.leader
))
5044 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5045 0baBbbbbbc defgh000 00000000 00000000.
5046 The zero and minus-zero cases need special handling, since they can't be
5047 encoded in the "quarter-precision" float format, but can nonetheless be
5048 loaded as integer constants. */
5051 parse_qfloat_immediate (char **ccp
, int *immed
)
5055 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5056 int found_fpchar
= 0;
5058 skip_past_char (&str
, '#');
5060 /* We must not accidentally parse an integer as a floating-point number. Make
5061 sure that the value we parse is not an integer by checking for special
5062 characters '.' or 'e'.
5063 FIXME: This is a horrible hack, but doing better is tricky because type
5064 information isn't in a very usable state at parse time. */
5066 skip_whitespace (fpnum
);
5068 if (strncmp (fpnum
, "0x", 2) == 0)
5072 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5073 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5083 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5085 unsigned fpword
= 0;
5088 /* Our FP word must be 32 bits (single-precision FP). */
5089 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5091 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5095 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5108 /* Shift operands. */
5111 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5114 struct asm_shift_name
5117 enum shift_kind kind
;
5120 /* Third argument to parse_shift. */
5121 enum parse_shift_mode
5123 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5124 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5125 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5126 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5127 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5130 /* Parse a <shift> specifier on an ARM data processing instruction.
5131 This has three forms:
5133 (LSL|LSR|ASL|ASR|ROR) Rs
5134 (LSL|LSR|ASL|ASR|ROR) #imm
5137 Note that ASL is assimilated to LSL in the instruction encoding, and
5138 RRX to ROR #0 (which cannot be written as such). */
5141 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5143 const struct asm_shift_name
*shift_name
;
5144 enum shift_kind shift
;
5149 for (p
= *str
; ISALPHA (*p
); p
++)
5154 inst
.error
= _("shift expression expected");
5158 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5161 if (shift_name
== NULL
)
5163 inst
.error
= _("shift expression expected");
5167 shift
= shift_name
->kind
;
5171 case NO_SHIFT_RESTRICT
:
5172 case SHIFT_IMMEDIATE
: break;
5174 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5175 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5177 inst
.error
= _("'LSL' or 'ASR' required");
5182 case SHIFT_LSL_IMMEDIATE
:
5183 if (shift
!= SHIFT_LSL
)
5185 inst
.error
= _("'LSL' required");
5190 case SHIFT_ASR_IMMEDIATE
:
5191 if (shift
!= SHIFT_ASR
)
5193 inst
.error
= _("'ASR' required");
5201 if (shift
!= SHIFT_RRX
)
5203 /* Whitespace can appear here if the next thing is a bare digit. */
5204 skip_whitespace (p
);
5206 if (mode
== NO_SHIFT_RESTRICT
5207 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5209 inst
.operands
[i
].imm
= reg
;
5210 inst
.operands
[i
].immisreg
= 1;
5212 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5215 inst
.operands
[i
].shift_kind
= shift
;
5216 inst
.operands
[i
].shifted
= 1;
5221 /* Parse a <shifter_operand> for an ARM data processing instruction:
5224 #<immediate>, <rotate>
5228 where <shift> is defined by parse_shift above, and <rotate> is a
5229 multiple of 2 between 0 and 30. Validation of immediate operands
5230 is deferred to md_apply_fix. */
5233 parse_shifter_operand (char **str
, int i
)
5238 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5240 inst
.operands
[i
].reg
= value
;
5241 inst
.operands
[i
].isreg
= 1;
5243 /* parse_shift will override this if appropriate */
5244 inst
.reloc
.exp
.X_op
= O_constant
;
5245 inst
.reloc
.exp
.X_add_number
= 0;
5247 if (skip_past_comma (str
) == FAIL
)
5250 /* Shift operation on register. */
5251 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5254 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5257 if (skip_past_comma (str
) == SUCCESS
)
5259 /* #x, y -- ie explicit rotation by Y. */
5260 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5263 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5265 inst
.error
= _("constant expression expected");
5269 value
= exp
.X_add_number
;
5270 if (value
< 0 || value
> 30 || value
% 2 != 0)
5272 inst
.error
= _("invalid rotation");
5275 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5277 inst
.error
= _("invalid constant");
5281 /* Encode as specified. */
5282 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5286 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5287 inst
.reloc
.pc_rel
= 0;
5291 /* Group relocation information. Each entry in the table contains the
5292 textual name of the relocation as may appear in assembler source
5293 and must end with a colon.
5294 Along with this textual name are the relocation codes to be used if
5295 the corresponding instruction is an ALU instruction (ADD or SUB only),
5296 an LDR, an LDRS, or an LDC. */
5298 struct group_reloc_table_entry
5309 /* Varieties of non-ALU group relocation. */
5316 static struct group_reloc_table_entry group_reloc_table
[] =
5317 { /* Program counter relative: */
5319 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5324 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5325 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5326 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5327 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5329 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5334 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5335 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5336 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5337 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5339 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5340 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5341 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5342 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5343 /* Section base relative */
5345 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5350 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5351 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5352 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5353 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5355 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5360 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5361 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5362 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5363 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5365 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5366 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5367 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5368 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5369 /* Absolute thumb alu relocations. */
5371 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5376 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5381 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5386 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5391 /* Given the address of a pointer pointing to the textual name of a group
5392 relocation as may appear in assembler source, attempt to find its details
5393 in group_reloc_table. The pointer will be updated to the character after
5394 the trailing colon. On failure, FAIL will be returned; SUCCESS
5395 otherwise. On success, *entry will be updated to point at the relevant
5396 group_reloc_table entry. */
5399 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5402 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5404 int length
= strlen (group_reloc_table
[i
].name
);
5406 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5407 && (*str
)[length
] == ':')
5409 *out
= &group_reloc_table
[i
];
5410 *str
+= (length
+ 1);
5418 /* Parse a <shifter_operand> for an ARM data processing instruction
5419 (as for parse_shifter_operand) where group relocations are allowed:
5422 #<immediate>, <rotate>
5423 #:<group_reloc>:<expression>
5427 where <group_reloc> is one of the strings defined in group_reloc_table.
5428 The hashes are optional.
5430 Everything else is as for parse_shifter_operand. */
5432 static parse_operand_result
5433 parse_shifter_operand_group_reloc (char **str
, int i
)
5435 /* Determine if we have the sequence of characters #: or just :
5436 coming next. If we do, then we check for a group relocation.
5437 If we don't, punt the whole lot to parse_shifter_operand. */
5439 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5440 || (*str
)[0] == ':')
5442 struct group_reloc_table_entry
*entry
;
5444 if ((*str
)[0] == '#')
5449 /* Try to parse a group relocation. Anything else is an error. */
5450 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5452 inst
.error
= _("unknown group relocation");
5453 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5456 /* We now have the group relocation table entry corresponding to
5457 the name in the assembler source. Next, we parse the expression. */
5458 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5459 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5461 /* Record the relocation type (always the ALU variant here). */
5462 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5463 gas_assert (inst
.reloc
.type
!= 0);
5465 return PARSE_OPERAND_SUCCESS
;
5468 return parse_shifter_operand (str
, i
) == SUCCESS
5469 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5471 /* Never reached. */
5474 /* Parse a Neon alignment expression. Information is written to
5475 inst.operands[i]. We assume the initial ':' has been skipped.
5477 align .imm = align << 8, .immisalign=1, .preind=0 */
5478 static parse_operand_result
5479 parse_neon_alignment (char **str
, int i
)
5484 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5486 if (exp
.X_op
!= O_constant
)
5488 inst
.error
= _("alignment must be constant");
5489 return PARSE_OPERAND_FAIL
;
5492 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5493 inst
.operands
[i
].immisalign
= 1;
5494 /* Alignments are not pre-indexes. */
5495 inst
.operands
[i
].preind
= 0;
5498 return PARSE_OPERAND_SUCCESS
;
5501 /* Parse all forms of an ARM address expression. Information is written
5502 to inst.operands[i] and/or inst.reloc.
5504 Preindexed addressing (.preind=1):
5506 [Rn, #offset] .reg=Rn .reloc.exp=offset
5507 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5508 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5509 .shift_kind=shift .reloc.exp=shift_imm
5511 These three may have a trailing ! which causes .writeback to be set also.
5513 Postindexed addressing (.postind=1, .writeback=1):
5515 [Rn], #offset .reg=Rn .reloc.exp=offset
5516 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5517 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5518 .shift_kind=shift .reloc.exp=shift_imm
5520 Unindexed addressing (.preind=0, .postind=0):
5522 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5526 [Rn]{!} shorthand for [Rn,#0]{!}
5527 =immediate .isreg=0 .reloc.exp=immediate
5528 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5530 It is the caller's responsibility to check for addressing modes not
5531 supported by the instruction, and to set inst.reloc.type. */
5533 static parse_operand_result
5534 parse_address_main (char **str
, int i
, int group_relocations
,
5535 group_reloc_type group_type
)
5540 if (skip_past_char (&p
, '[') == FAIL
)
5542 if (skip_past_char (&p
, '=') == FAIL
)
5544 /* Bare address - translate to PC-relative offset. */
5545 inst
.reloc
.pc_rel
= 1;
5546 inst
.operands
[i
].reg
= REG_PC
;
5547 inst
.operands
[i
].isreg
= 1;
5548 inst
.operands
[i
].preind
= 1;
5550 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5551 return PARSE_OPERAND_FAIL
;
5553 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5554 /*allow_symbol_p=*/TRUE
))
5555 return PARSE_OPERAND_FAIL
;
5558 return PARSE_OPERAND_SUCCESS
;
5561 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5562 skip_whitespace (p
);
5564 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5566 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5567 return PARSE_OPERAND_FAIL
;
5569 inst
.operands
[i
].reg
= reg
;
5570 inst
.operands
[i
].isreg
= 1;
5572 if (skip_past_comma (&p
) == SUCCESS
)
5574 inst
.operands
[i
].preind
= 1;
5577 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5579 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5581 inst
.operands
[i
].imm
= reg
;
5582 inst
.operands
[i
].immisreg
= 1;
5584 if (skip_past_comma (&p
) == SUCCESS
)
5585 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5586 return PARSE_OPERAND_FAIL
;
5588 else if (skip_past_char (&p
, ':') == SUCCESS
)
5590 /* FIXME: '@' should be used here, but it's filtered out by generic
5591 code before we get to see it here. This may be subject to
5593 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5595 if (result
!= PARSE_OPERAND_SUCCESS
)
5600 if (inst
.operands
[i
].negative
)
5602 inst
.operands
[i
].negative
= 0;
5606 if (group_relocations
5607 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5609 struct group_reloc_table_entry
*entry
;
5611 /* Skip over the #: or : sequence. */
5617 /* Try to parse a group relocation. Anything else is an
5619 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5621 inst
.error
= _("unknown group relocation");
5622 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5625 /* We now have the group relocation table entry corresponding to
5626 the name in the assembler source. Next, we parse the
5628 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5629 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5631 /* Record the relocation type. */
5635 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5639 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5643 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5650 if (inst
.reloc
.type
== 0)
5652 inst
.error
= _("this group relocation is not allowed on this instruction");
5653 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5660 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5661 return PARSE_OPERAND_FAIL
;
5662 /* If the offset is 0, find out if it's a +0 or -0. */
5663 if (inst
.reloc
.exp
.X_op
== O_constant
5664 && inst
.reloc
.exp
.X_add_number
== 0)
5666 skip_whitespace (q
);
5670 skip_whitespace (q
);
5673 inst
.operands
[i
].negative
= 1;
5678 else if (skip_past_char (&p
, ':') == SUCCESS
)
5680 /* FIXME: '@' should be used here, but it's filtered out by generic code
5681 before we get to see it here. This may be subject to change. */
5682 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5684 if (result
!= PARSE_OPERAND_SUCCESS
)
5688 if (skip_past_char (&p
, ']') == FAIL
)
5690 inst
.error
= _("']' expected");
5691 return PARSE_OPERAND_FAIL
;
5694 if (skip_past_char (&p
, '!') == SUCCESS
)
5695 inst
.operands
[i
].writeback
= 1;
5697 else if (skip_past_comma (&p
) == SUCCESS
)
5699 if (skip_past_char (&p
, '{') == SUCCESS
)
5701 /* [Rn], {expr} - unindexed, with option */
5702 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5703 0, 255, TRUE
) == FAIL
)
5704 return PARSE_OPERAND_FAIL
;
5706 if (skip_past_char (&p
, '}') == FAIL
)
5708 inst
.error
= _("'}' expected at end of 'option' field");
5709 return PARSE_OPERAND_FAIL
;
5711 if (inst
.operands
[i
].preind
)
5713 inst
.error
= _("cannot combine index with option");
5714 return PARSE_OPERAND_FAIL
;
5717 return PARSE_OPERAND_SUCCESS
;
5721 inst
.operands
[i
].postind
= 1;
5722 inst
.operands
[i
].writeback
= 1;
5724 if (inst
.operands
[i
].preind
)
5726 inst
.error
= _("cannot combine pre- and post-indexing");
5727 return PARSE_OPERAND_FAIL
;
5731 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5733 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5735 /* We might be using the immediate for alignment already. If we
5736 are, OR the register number into the low-order bits. */
5737 if (inst
.operands
[i
].immisalign
)
5738 inst
.operands
[i
].imm
|= reg
;
5740 inst
.operands
[i
].imm
= reg
;
5741 inst
.operands
[i
].immisreg
= 1;
5743 if (skip_past_comma (&p
) == SUCCESS
)
5744 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5745 return PARSE_OPERAND_FAIL
;
5751 if (inst
.operands
[i
].negative
)
5753 inst
.operands
[i
].negative
= 0;
5756 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5757 return PARSE_OPERAND_FAIL
;
5758 /* If the offset is 0, find out if it's a +0 or -0. */
5759 if (inst
.reloc
.exp
.X_op
== O_constant
5760 && inst
.reloc
.exp
.X_add_number
== 0)
5762 skip_whitespace (q
);
5766 skip_whitespace (q
);
5769 inst
.operands
[i
].negative
= 1;
5775 /* If at this point neither .preind nor .postind is set, we have a
5776 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5777 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5779 inst
.operands
[i
].preind
= 1;
5780 inst
.reloc
.exp
.X_op
= O_constant
;
5781 inst
.reloc
.exp
.X_add_number
= 0;
5784 return PARSE_OPERAND_SUCCESS
;
5788 parse_address (char **str
, int i
)
5790 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5794 static parse_operand_result
5795 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5797 return parse_address_main (str
, i
, 1, type
);
5800 /* Parse an operand for a MOVW or MOVT instruction. */
5802 parse_half (char **str
)
5807 skip_past_char (&p
, '#');
5808 if (strncasecmp (p
, ":lower16:", 9) == 0)
5809 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5810 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5811 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5813 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5816 skip_whitespace (p
);
5819 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5822 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5824 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5826 inst
.error
= _("constant expression expected");
5829 if (inst
.reloc
.exp
.X_add_number
< 0
5830 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5832 inst
.error
= _("immediate value out of range");
5840 /* Miscellaneous. */
5842 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5843 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5845 parse_psr (char **str
, bfd_boolean lhs
)
5848 unsigned long psr_field
;
5849 const struct asm_psr
*psr
;
5851 bfd_boolean is_apsr
= FALSE
;
5852 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5854 /* PR gas/12698: If the user has specified -march=all then m_profile will
5855 be TRUE, but we want to ignore it in this case as we are building for any
5856 CPU type, including non-m variants. */
5857 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5860 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5861 feature for ease of use and backwards compatibility. */
5863 if (strncasecmp (p
, "SPSR", 4) == 0)
5866 goto unsupported_psr
;
5868 psr_field
= SPSR_BIT
;
5870 else if (strncasecmp (p
, "CPSR", 4) == 0)
5873 goto unsupported_psr
;
5877 else if (strncasecmp (p
, "APSR", 4) == 0)
5879 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5880 and ARMv7-R architecture CPUs. */
5889 while (ISALNUM (*p
) || *p
== '_');
5891 if (strncasecmp (start
, "iapsr", 5) == 0
5892 || strncasecmp (start
, "eapsr", 5) == 0
5893 || strncasecmp (start
, "xpsr", 4) == 0
5894 || strncasecmp (start
, "psr", 3) == 0)
5895 p
= start
+ strcspn (start
, "rR") + 1;
5897 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5903 /* If APSR is being written, a bitfield may be specified. Note that
5904 APSR itself is handled above. */
5905 if (psr
->field
<= 3)
5907 psr_field
= psr
->field
;
5913 /* M-profile MSR instructions have the mask field set to "10", except
5914 *PSR variants which modify APSR, which may use a different mask (and
5915 have been handled already). Do that by setting the PSR_f field
5917 return psr
->field
| (lhs
? PSR_f
: 0);
5920 goto unsupported_psr
;
5926 /* A suffix follows. */
5932 while (ISALNUM (*p
) || *p
== '_');
5936 /* APSR uses a notation for bits, rather than fields. */
5937 unsigned int nzcvq_bits
= 0;
5938 unsigned int g_bit
= 0;
5941 for (bit
= start
; bit
!= p
; bit
++)
5943 switch (TOLOWER (*bit
))
5946 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5950 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5954 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5958 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5962 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5966 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5970 inst
.error
= _("unexpected bit specified after APSR");
5975 if (nzcvq_bits
== 0x1f)
5980 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5982 inst
.error
= _("selected processor does not "
5983 "support DSP extension");
5990 if ((nzcvq_bits
& 0x20) != 0
5991 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5992 || (g_bit
& 0x2) != 0)
5994 inst
.error
= _("bad bitmask specified after APSR");
6000 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6005 psr_field
|= psr
->field
;
6011 goto error
; /* Garbage after "[CS]PSR". */
6013 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6014 is deprecated, but allow it anyway. */
6018 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6021 else if (!m_profile
)
6022 /* These bits are never right for M-profile devices: don't set them
6023 (only code paths which read/write APSR reach here). */
6024 psr_field
|= (PSR_c
| PSR_f
);
6030 inst
.error
= _("selected processor does not support requested special "
6031 "purpose register");
6035 inst
.error
= _("flag for {c}psr instruction expected");
6039 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6040 value suitable for splatting into the AIF field of the instruction. */
6043 parse_cps_flags (char **str
)
6052 case '\0': case ',':
6055 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6056 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6057 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6060 inst
.error
= _("unrecognized CPS flag");
6065 if (saw_a_flag
== 0)
6067 inst
.error
= _("missing CPS flags");
6075 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6076 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6079 parse_endian_specifier (char **str
)
6084 if (strncasecmp (s
, "BE", 2))
6086 else if (strncasecmp (s
, "LE", 2))
6090 inst
.error
= _("valid endian specifiers are be or le");
6094 if (ISALNUM (s
[2]) || s
[2] == '_')
6096 inst
.error
= _("valid endian specifiers are be or le");
6101 return little_endian
;
6104 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6105 value suitable for poking into the rotate field of an sxt or sxta
6106 instruction, or FAIL on error. */
6109 parse_ror (char **str
)
6114 if (strncasecmp (s
, "ROR", 3) == 0)
6118 inst
.error
= _("missing rotation field after comma");
6122 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6127 case 0: *str
= s
; return 0x0;
6128 case 8: *str
= s
; return 0x1;
6129 case 16: *str
= s
; return 0x2;
6130 case 24: *str
= s
; return 0x3;
6133 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6138 /* Parse a conditional code (from conds[] below). The value returned is in the
6139 range 0 .. 14, or FAIL. */
6141 parse_cond (char **str
)
6144 const struct asm_cond
*c
;
6146 /* Condition codes are always 2 characters, so matching up to
6147 3 characters is sufficient. */
6152 while (ISALPHA (*q
) && n
< 3)
6154 cond
[n
] = TOLOWER (*q
);
6159 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6162 inst
.error
= _("condition required");
6170 /* Record a use of the given feature. */
6172 record_feature_use (const arm_feature_set
*feature
)
6175 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6177 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6180 /* If the given feature is currently allowed, mark it as used and return TRUE.
6181 Return FALSE otherwise. */
6183 mark_feature_used (const arm_feature_set
*feature
)
6185 /* Ensure the option is currently allowed. */
6186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6189 /* Add the appropriate architecture feature for the barrier option used. */
6190 record_feature_use (feature
);
6195 /* Parse an option for a barrier instruction. Returns the encoding for the
6198 parse_barrier (char **str
)
6201 const struct asm_barrier_opt
*o
;
6204 while (ISALPHA (*q
))
6207 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6212 if (!mark_feature_used (&o
->arch
))
6219 /* Parse the operands of a table branch instruction. Similar to a memory
6222 parse_tb (char **str
)
6227 if (skip_past_char (&p
, '[') == FAIL
)
6229 inst
.error
= _("'[' expected");
6233 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6235 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6238 inst
.operands
[0].reg
= reg
;
6240 if (skip_past_comma (&p
) == FAIL
)
6242 inst
.error
= _("',' expected");
6246 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6248 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6251 inst
.operands
[0].imm
= reg
;
6253 if (skip_past_comma (&p
) == SUCCESS
)
6255 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6257 if (inst
.reloc
.exp
.X_add_number
!= 1)
6259 inst
.error
= _("invalid shift");
6262 inst
.operands
[0].shifted
= 1;
6265 if (skip_past_char (&p
, ']') == FAIL
)
6267 inst
.error
= _("']' expected");
6274 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6275 information on the types the operands can take and how they are encoded.
6276 Up to four operands may be read; this function handles setting the
6277 ".present" field for each read operand itself.
6278 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6279 else returns FAIL. */
6282 parse_neon_mov (char **str
, int *which_operand
)
6284 int i
= *which_operand
, val
;
6285 enum arm_reg_type rtype
;
6287 struct neon_type_el optype
;
6289 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6291 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6292 inst
.operands
[i
].reg
= val
;
6293 inst
.operands
[i
].isscalar
= 1;
6294 inst
.operands
[i
].vectype
= optype
;
6295 inst
.operands
[i
++].present
= 1;
6297 if (skip_past_comma (&ptr
) == FAIL
)
6300 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
].present
= 1;
6307 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6310 /* Cases 0, 1, 2, 3, 5 (D only). */
6311 if (skip_past_comma (&ptr
) == FAIL
)
6314 inst
.operands
[i
].reg
= val
;
6315 inst
.operands
[i
].isreg
= 1;
6316 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6317 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6318 inst
.operands
[i
].isvec
= 1;
6319 inst
.operands
[i
].vectype
= optype
;
6320 inst
.operands
[i
++].present
= 1;
6322 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6324 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6325 Case 13: VMOV <Sd>, <Rm> */
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6328 inst
.operands
[i
].present
= 1;
6330 if (rtype
== REG_TYPE_NQ
)
6332 first_error (_("can't use Neon quad register here"));
6335 else if (rtype
!= REG_TYPE_VFS
)
6338 if (skip_past_comma (&ptr
) == FAIL
)
6340 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6342 inst
.operands
[i
].reg
= val
;
6343 inst
.operands
[i
].isreg
= 1;
6344 inst
.operands
[i
].present
= 1;
6347 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6350 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6351 Case 1: VMOV<c><q> <Dd>, <Dm>
6352 Case 8: VMOV.F32 <Sd>, <Sm>
6353 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6355 inst
.operands
[i
].reg
= val
;
6356 inst
.operands
[i
].isreg
= 1;
6357 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6358 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6359 inst
.operands
[i
].isvec
= 1;
6360 inst
.operands
[i
].vectype
= optype
;
6361 inst
.operands
[i
].present
= 1;
6363 if (skip_past_comma (&ptr
) == SUCCESS
)
6368 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6371 inst
.operands
[i
].reg
= val
;
6372 inst
.operands
[i
].isreg
= 1;
6373 inst
.operands
[i
++].present
= 1;
6375 if (skip_past_comma (&ptr
) == FAIL
)
6378 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6381 inst
.operands
[i
].reg
= val
;
6382 inst
.operands
[i
].isreg
= 1;
6383 inst
.operands
[i
].present
= 1;
6386 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6387 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6388 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6389 Case 10: VMOV.F32 <Sd>, #<imm>
6390 Case 11: VMOV.F64 <Dd>, #<imm> */
6391 inst
.operands
[i
].immisfloat
= 1;
6392 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6394 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6395 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6399 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6403 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6406 inst
.operands
[i
].reg
= val
;
6407 inst
.operands
[i
].isreg
= 1;
6408 inst
.operands
[i
++].present
= 1;
6410 if (skip_past_comma (&ptr
) == FAIL
)
6413 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6415 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6416 inst
.operands
[i
].reg
= val
;
6417 inst
.operands
[i
].isscalar
= 1;
6418 inst
.operands
[i
].present
= 1;
6419 inst
.operands
[i
].vectype
= optype
;
6421 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6423 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6424 inst
.operands
[i
].reg
= val
;
6425 inst
.operands
[i
].isreg
= 1;
6426 inst
.operands
[i
++].present
= 1;
6428 if (skip_past_comma (&ptr
) == FAIL
)
6431 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6434 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6438 inst
.operands
[i
].reg
= val
;
6439 inst
.operands
[i
].isreg
= 1;
6440 inst
.operands
[i
].isvec
= 1;
6441 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6442 inst
.operands
[i
].vectype
= optype
;
6443 inst
.operands
[i
].present
= 1;
6445 if (rtype
== REG_TYPE_VFS
)
6449 if (skip_past_comma (&ptr
) == FAIL
)
6451 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6454 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6457 inst
.operands
[i
].reg
= val
;
6458 inst
.operands
[i
].isreg
= 1;
6459 inst
.operands
[i
].isvec
= 1;
6460 inst
.operands
[i
].issingle
= 1;
6461 inst
.operands
[i
].vectype
= optype
;
6462 inst
.operands
[i
].present
= 1;
6465 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6469 inst
.operands
[i
].reg
= val
;
6470 inst
.operands
[i
].isreg
= 1;
6471 inst
.operands
[i
].isvec
= 1;
6472 inst
.operands
[i
].issingle
= 1;
6473 inst
.operands
[i
].vectype
= optype
;
6474 inst
.operands
[i
].present
= 1;
6479 first_error (_("parse error"));
6483 /* Successfully parsed the operands. Update args. */
6489 first_error (_("expected comma"));
6493 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6497 /* Use this macro when the operand constraints are different
6498 for ARM and THUMB (e.g. ldrd). */
6499 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6500 ((arm_operand) | ((thumb_operand) << 16))
6502 /* Matcher codes for parse_operands. */
6503 enum operand_parse_code
6505 OP_stop
, /* end of line */
6507 OP_RR
, /* ARM register */
6508 OP_RRnpc
, /* ARM register, not r15 */
6509 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6510 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6511 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6512 optional trailing ! */
6513 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6514 OP_RCP
, /* Coprocessor number */
6515 OP_RCN
, /* Coprocessor register */
6516 OP_RF
, /* FPA register */
6517 OP_RVS
, /* VFP single precision register */
6518 OP_RVD
, /* VFP double precision register (0..15) */
6519 OP_RND
, /* Neon double precision register (0..31) */
6520 OP_RNQ
, /* Neon quad precision register */
6521 OP_RVSD
, /* VFP single or double precision register */
6522 OP_RNSD
, /* Neon single or double precision register */
6523 OP_RNDQ
, /* Neon double or quad precision register */
6524 OP_RNSDQ
, /* Neon single, double or quad precision register */
6525 OP_RNSC
, /* Neon scalar D[X] */
6526 OP_RVC
, /* VFP control register */
6527 OP_RMF
, /* Maverick F register */
6528 OP_RMD
, /* Maverick D register */
6529 OP_RMFX
, /* Maverick FX register */
6530 OP_RMDX
, /* Maverick DX register */
6531 OP_RMAX
, /* Maverick AX register */
6532 OP_RMDS
, /* Maverick DSPSC register */
6533 OP_RIWR
, /* iWMMXt wR register */
6534 OP_RIWC
, /* iWMMXt wC register */
6535 OP_RIWG
, /* iWMMXt wCG register */
6536 OP_RXA
, /* XScale accumulator register */
6538 OP_REGLST
, /* ARM register list */
6539 OP_VRSLST
, /* VFP single-precision register list */
6540 OP_VRDLST
, /* VFP double-precision register list */
6541 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6542 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6543 OP_NSTRLST
, /* Neon element/structure list */
6545 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6546 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6547 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6548 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6549 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6550 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6551 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6552 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6553 OP_VMOV
, /* Neon VMOV operands. */
6554 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6555 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6556 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6558 OP_I0
, /* immediate zero */
6559 OP_I7
, /* immediate value 0 .. 7 */
6560 OP_I15
, /* 0 .. 15 */
6561 OP_I16
, /* 1 .. 16 */
6562 OP_I16z
, /* 0 .. 16 */
6563 OP_I31
, /* 0 .. 31 */
6564 OP_I31w
, /* 0 .. 31, optional trailing ! */
6565 OP_I32
, /* 1 .. 32 */
6566 OP_I32z
, /* 0 .. 32 */
6567 OP_I63
, /* 0 .. 63 */
6568 OP_I63s
, /* -64 .. 63 */
6569 OP_I64
, /* 1 .. 64 */
6570 OP_I64z
, /* 0 .. 64 */
6571 OP_I255
, /* 0 .. 255 */
6573 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6574 OP_I7b
, /* 0 .. 7 */
6575 OP_I15b
, /* 0 .. 15 */
6576 OP_I31b
, /* 0 .. 31 */
6578 OP_SH
, /* shifter operand */
6579 OP_SHG
, /* shifter operand with possible group relocation */
6580 OP_ADDR
, /* Memory address expression (any mode) */
6581 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6582 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6583 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6584 OP_EXP
, /* arbitrary expression */
6585 OP_EXPi
, /* same, with optional immediate prefix */
6586 OP_EXPr
, /* same, with optional relocation suffix */
6587 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6588 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6589 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6591 OP_CPSF
, /* CPS flags */
6592 OP_ENDI
, /* Endianness specifier */
6593 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6594 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6595 OP_COND
, /* conditional code */
6596 OP_TB
, /* Table branch. */
6598 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6600 OP_RRnpc_I0
, /* ARM register or literal 0 */
6601 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6602 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6603 OP_RF_IF
, /* FPA register or immediate */
6604 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6605 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6607 /* Optional operands. */
6608 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6609 OP_oI31b
, /* 0 .. 31 */
6610 OP_oI32b
, /* 1 .. 32 */
6611 OP_oI32z
, /* 0 .. 32 */
6612 OP_oIffffb
, /* 0 .. 65535 */
6613 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6615 OP_oRR
, /* ARM register */
6616 OP_oRRnpc
, /* ARM register, not the PC */
6617 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6618 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6619 OP_oRND
, /* Optional Neon double precision register */
6620 OP_oRNQ
, /* Optional Neon quad precision register */
6621 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6622 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6623 OP_oSHll
, /* LSL immediate */
6624 OP_oSHar
, /* ASR immediate */
6625 OP_oSHllar
, /* LSL or ASR immediate */
6626 OP_oROR
, /* ROR 0/8/16/24 */
6627 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6629 /* Some pre-defined mixed (ARM/THUMB) operands. */
6630 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6631 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6632 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6634 OP_FIRST_OPTIONAL
= OP_oI7b
6637 /* Generic instruction operand parser. This does no encoding and no
6638 semantic validation; it merely squirrels values away in the inst
6639 structure. Returns SUCCESS or FAIL depending on whether the
6640 specified grammar matched. */
6642 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6644 unsigned const int *upat
= pattern
;
6645 char *backtrack_pos
= 0;
6646 const char *backtrack_error
= 0;
6647 int i
, val
= 0, backtrack_index
= 0;
6648 enum arm_reg_type rtype
;
6649 parse_operand_result result
;
6650 unsigned int op_parse_code
;
6652 #define po_char_or_fail(chr) \
6655 if (skip_past_char (&str, chr) == FAIL) \
6660 #define po_reg_or_fail(regtype) \
6663 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6664 & inst.operands[i].vectype); \
6667 first_error (_(reg_expected_msgs[regtype])); \
6670 inst.operands[i].reg = val; \
6671 inst.operands[i].isreg = 1; \
6672 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6673 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6674 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6675 || rtype == REG_TYPE_VFD \
6676 || rtype == REG_TYPE_NQ); \
6680 #define po_reg_or_goto(regtype, label) \
6683 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6684 & inst.operands[i].vectype); \
6688 inst.operands[i].reg = val; \
6689 inst.operands[i].isreg = 1; \
6690 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6691 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6692 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6693 || rtype == REG_TYPE_VFD \
6694 || rtype == REG_TYPE_NQ); \
6698 #define po_imm_or_fail(min, max, popt) \
6701 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6703 inst.operands[i].imm = val; \
6707 #define po_scalar_or_goto(elsz, label) \
6710 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6713 inst.operands[i].reg = val; \
6714 inst.operands[i].isscalar = 1; \
6718 #define po_misc_or_fail(expr) \
6726 #define po_misc_or_fail_no_backtrack(expr) \
6730 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6731 backtrack_pos = 0; \
6732 if (result != PARSE_OPERAND_SUCCESS) \
6737 #define po_barrier_or_imm(str) \
6740 val = parse_barrier (&str); \
6741 if (val == FAIL && ! ISALPHA (*str)) \
6744 /* ISB can only take SY as an option. */ \
6745 || ((inst.instruction & 0xf0) == 0x60 \
6748 inst.error = _("invalid barrier type"); \
6749 backtrack_pos = 0; \
6755 skip_whitespace (str
);
6757 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6759 op_parse_code
= upat
[i
];
6760 if (op_parse_code
>= 1<<16)
6761 op_parse_code
= thumb
? (op_parse_code
>> 16)
6762 : (op_parse_code
& ((1<<16)-1));
6764 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6766 /* Remember where we are in case we need to backtrack. */
6767 gas_assert (!backtrack_pos
);
6768 backtrack_pos
= str
;
6769 backtrack_error
= inst
.error
;
6770 backtrack_index
= i
;
6773 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6774 po_char_or_fail (',');
6776 switch (op_parse_code
)
6784 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6785 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6786 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6787 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6788 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6789 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6791 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6793 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6795 /* Also accept generic coprocessor regs for unknown registers. */
6797 po_reg_or_fail (REG_TYPE_CN
);
6799 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6800 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6801 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6802 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6803 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6804 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6805 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6806 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6807 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6808 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6810 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6811 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6813 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6814 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6816 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6818 /* Neon scalar. Using an element size of 8 means that some invalid
6819 scalars are accepted here, so deal with those in later code. */
6820 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6824 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6827 po_imm_or_fail (0, 0, TRUE
);
6832 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6837 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6840 if (parse_ifimm_zero (&str
))
6841 inst
.operands
[i
].imm
= 0;
6845 = _("only floating point zero is allowed as immediate value");
6853 po_scalar_or_goto (8, try_rr
);
6856 po_reg_or_fail (REG_TYPE_RN
);
6862 po_scalar_or_goto (8, try_nsdq
);
6865 po_reg_or_fail (REG_TYPE_NSDQ
);
6871 po_scalar_or_goto (8, try_s_scalar
);
6874 po_scalar_or_goto (4, try_nsd
);
6877 po_reg_or_fail (REG_TYPE_NSD
);
6883 po_scalar_or_goto (8, try_ndq
);
6886 po_reg_or_fail (REG_TYPE_NDQ
);
6892 po_scalar_or_goto (8, try_vfd
);
6895 po_reg_or_fail (REG_TYPE_VFD
);
6900 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6901 not careful then bad things might happen. */
6902 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6907 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6910 /* There's a possibility of getting a 64-bit immediate here, so
6911 we need special handling. */
6912 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6915 inst
.error
= _("immediate value is out of range");
6923 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6926 po_imm_or_fail (0, 63, TRUE
);
6931 po_char_or_fail ('[');
6932 po_reg_or_fail (REG_TYPE_RN
);
6933 po_char_or_fail (']');
6939 po_reg_or_fail (REG_TYPE_RN
);
6940 if (skip_past_char (&str
, '!') == SUCCESS
)
6941 inst
.operands
[i
].writeback
= 1;
6945 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6946 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6947 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6948 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6949 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6950 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6951 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6952 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6953 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6954 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6955 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6956 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6958 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6960 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6961 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6963 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6964 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6965 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6966 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6968 /* Immediate variants */
6970 po_char_or_fail ('{');
6971 po_imm_or_fail (0, 255, TRUE
);
6972 po_char_or_fail ('}');
6976 /* The expression parser chokes on a trailing !, so we have
6977 to find it first and zap it. */
6980 while (*s
&& *s
!= ',')
6985 inst
.operands
[i
].writeback
= 1;
6987 po_imm_or_fail (0, 31, TRUE
);
6995 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7000 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7005 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7007 if (inst
.reloc
.exp
.X_op
== O_symbol
)
7009 val
= parse_reloc (&str
);
7012 inst
.error
= _("unrecognized relocation suffix");
7015 else if (val
!= BFD_RELOC_UNUSED
)
7017 inst
.operands
[i
].imm
= val
;
7018 inst
.operands
[i
].hasreloc
= 1;
7023 /* Operand for MOVW or MOVT. */
7025 po_misc_or_fail (parse_half (&str
));
7028 /* Register or expression. */
7029 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7030 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7032 /* Register or immediate. */
7033 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7034 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7036 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7038 if (!is_immediate_prefix (*str
))
7041 val
= parse_fpa_immediate (&str
);
7044 /* FPA immediates are encoded as registers 8-15.
7045 parse_fpa_immediate has already applied the offset. */
7046 inst
.operands
[i
].reg
= val
;
7047 inst
.operands
[i
].isreg
= 1;
7050 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7051 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7053 /* Two kinds of register. */
7056 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7058 || (rege
->type
!= REG_TYPE_MMXWR
7059 && rege
->type
!= REG_TYPE_MMXWC
7060 && rege
->type
!= REG_TYPE_MMXWCG
))
7062 inst
.error
= _("iWMMXt data or control register expected");
7065 inst
.operands
[i
].reg
= rege
->number
;
7066 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7072 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7074 || (rege
->type
!= REG_TYPE_MMXWC
7075 && rege
->type
!= REG_TYPE_MMXWCG
))
7077 inst
.error
= _("iWMMXt control register expected");
7080 inst
.operands
[i
].reg
= rege
->number
;
7081 inst
.operands
[i
].isreg
= 1;
7086 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7087 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7088 case OP_oROR
: val
= parse_ror (&str
); break;
7089 case OP_COND
: val
= parse_cond (&str
); break;
7090 case OP_oBARRIER_I15
:
7091 po_barrier_or_imm (str
); break;
7093 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7099 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7100 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7102 inst
.error
= _("Banked registers are not available with this "
7108 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7112 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7115 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7117 if (strncasecmp (str
, "APSR_", 5) == 0)
7124 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7125 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7126 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7127 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7128 default: found
= 16;
7132 inst
.operands
[i
].isvec
= 1;
7133 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7134 inst
.operands
[i
].reg
= REG_PC
;
7141 po_misc_or_fail (parse_tb (&str
));
7144 /* Register lists. */
7146 val
= parse_reg_list (&str
);
7149 inst
.operands
[i
].writeback
= 1;
7155 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7159 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7163 /* Allow Q registers too. */
7164 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7169 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7171 inst
.operands
[i
].issingle
= 1;
7176 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7181 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7182 &inst
.operands
[i
].vectype
);
7185 /* Addressing modes */
7187 po_misc_or_fail (parse_address (&str
, i
));
7191 po_misc_or_fail_no_backtrack (
7192 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7196 po_misc_or_fail_no_backtrack (
7197 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7201 po_misc_or_fail_no_backtrack (
7202 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7206 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7210 po_misc_or_fail_no_backtrack (
7211 parse_shifter_operand_group_reloc (&str
, i
));
7215 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7219 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7223 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7227 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7230 /* Various value-based sanity checks and shared operations. We
7231 do not signal immediate failures for the register constraints;
7232 this allows a syntax error to take precedence. */
7233 switch (op_parse_code
)
7241 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7242 inst
.error
= BAD_PC
;
7247 if (inst
.operands
[i
].isreg
)
7249 if (inst
.operands
[i
].reg
== REG_PC
)
7250 inst
.error
= BAD_PC
;
7251 else if (inst
.operands
[i
].reg
== REG_SP
7252 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7253 relaxed since ARMv8-A. */
7254 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7257 inst
.error
= BAD_SP
;
7263 if (inst
.operands
[i
].isreg
7264 && inst
.operands
[i
].reg
== REG_PC
7265 && (inst
.operands
[i
].writeback
|| thumb
))
7266 inst
.error
= BAD_PC
;
7275 case OP_oBARRIER_I15
:
7284 inst
.operands
[i
].imm
= val
;
7291 /* If we get here, this operand was successfully parsed. */
7292 inst
.operands
[i
].present
= 1;
7296 inst
.error
= BAD_ARGS
;
7301 /* The parse routine should already have set inst.error, but set a
7302 default here just in case. */
7304 inst
.error
= _("syntax error");
7308 /* Do not backtrack over a trailing optional argument that
7309 absorbed some text. We will only fail again, with the
7310 'garbage following instruction' error message, which is
7311 probably less helpful than the current one. */
7312 if (backtrack_index
== i
&& backtrack_pos
!= str
7313 && upat
[i
+1] == OP_stop
)
7316 inst
.error
= _("syntax error");
7320 /* Try again, skipping the optional argument at backtrack_pos. */
7321 str
= backtrack_pos
;
7322 inst
.error
= backtrack_error
;
7323 inst
.operands
[backtrack_index
].present
= 0;
7324 i
= backtrack_index
;
7328 /* Check that we have parsed all the arguments. */
7329 if (*str
!= '\0' && !inst
.error
)
7330 inst
.error
= _("garbage following instruction");
7332 return inst
.error
? FAIL
: SUCCESS
;
7335 #undef po_char_or_fail
7336 #undef po_reg_or_fail
7337 #undef po_reg_or_goto
7338 #undef po_imm_or_fail
7339 #undef po_scalar_or_fail
7340 #undef po_barrier_or_imm
7342 /* Shorthand macro for instruction encoding functions issuing errors. */
7343 #define constraint(expr, err) \
7354 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7355 instructions are unpredictable if these registers are used. This
7356 is the BadReg predicate in ARM's Thumb-2 documentation.
7358 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7359 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7360 #define reject_bad_reg(reg) \
7362 if (reg == REG_PC) \
7364 inst.error = BAD_PC; \
7367 else if (reg == REG_SP \
7368 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7370 inst.error = BAD_SP; \
7375 /* If REG is R13 (the stack pointer), warn that its use is
7377 #define warn_deprecated_sp(reg) \
7379 if (warn_on_deprecated && reg == REG_SP) \
7380 as_tsktsk (_("use of r13 is deprecated")); \
7383 /* Functions for operand encoding. ARM, then Thumb. */
7385 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7387 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7389 The only binary encoding difference is the Coprocessor number. Coprocessor
7390 9 is used for half-precision calculations or conversions. The format of the
7391 instruction is the same as the equivalent Coprocessor 10 instruction that
7392 exists for Single-Precision operation. */
7395 do_scalar_fp16_v82_encode (void)
7397 if (inst
.cond
!= COND_ALWAYS
)
7398 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7399 " the behaviour is UNPREDICTABLE"));
7400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7403 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7404 mark_feature_used (&arm_ext_fp16
);
7407 /* If VAL can be encoded in the immediate field of an ARM instruction,
7408 return the encoded form. Otherwise, return FAIL. */
7411 encode_arm_immediate (unsigned int val
)
7418 for (i
= 2; i
< 32; i
+= 2)
7419 if ((a
= rotate_left (val
, i
)) <= 0xff)
7420 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7425 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7426 return the encoded form. Otherwise, return FAIL. */
7428 encode_thumb32_immediate (unsigned int val
)
7435 for (i
= 1; i
<= 24; i
++)
7438 if ((val
& ~(0xff << i
)) == 0)
7439 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7443 if (val
== ((a
<< 16) | a
))
7445 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7449 if (val
== ((a
<< 16) | a
))
7450 return 0x200 | (a
>> 8);
7454 /* Encode a VFP SP or DP register number into inst.instruction. */
7457 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7459 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7462 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7465 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7468 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7473 first_error (_("D register out of range for selected VFP version"));
7481 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7485 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7489 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7493 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7497 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7501 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7509 /* Encode a <shift> in an ARM-format instruction. The immediate,
7510 if any, is handled by md_apply_fix. */
7512 encode_arm_shift (int i
)
7514 /* register-shifted register. */
7515 if (inst
.operands
[i
].immisreg
)
7518 for (op_index
= 0; op_index
<= i
; ++op_index
)
7520 /* Check the operand only when it's presented. In pre-UAL syntax,
7521 if the destination register is the same as the first operand, two
7522 register form of the instruction can be used. */
7523 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7524 && inst
.operands
[op_index
].reg
== REG_PC
)
7525 as_warn (UNPRED_REG ("r15"));
7528 if (inst
.operands
[i
].imm
== REG_PC
)
7529 as_warn (UNPRED_REG ("r15"));
7532 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7533 inst
.instruction
|= SHIFT_ROR
<< 5;
7536 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7537 if (inst
.operands
[i
].immisreg
)
7539 inst
.instruction
|= SHIFT_BY_REG
;
7540 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7543 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7548 encode_arm_shifter_operand (int i
)
7550 if (inst
.operands
[i
].isreg
)
7552 inst
.instruction
|= inst
.operands
[i
].reg
;
7553 encode_arm_shift (i
);
7557 inst
.instruction
|= INST_IMMEDIATE
;
7558 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7559 inst
.instruction
|= inst
.operands
[i
].imm
;
7563 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7565 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7568 Generate an error if the operand is not a register. */
7569 constraint (!inst
.operands
[i
].isreg
,
7570 _("Instruction does not support =N addresses"));
7572 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7574 if (inst
.operands
[i
].preind
)
7578 inst
.error
= _("instruction does not accept preindexed addressing");
7581 inst
.instruction
|= PRE_INDEX
;
7582 if (inst
.operands
[i
].writeback
)
7583 inst
.instruction
|= WRITE_BACK
;
7586 else if (inst
.operands
[i
].postind
)
7588 gas_assert (inst
.operands
[i
].writeback
);
7590 inst
.instruction
|= WRITE_BACK
;
7592 else /* unindexed - only for coprocessor */
7594 inst
.error
= _("instruction does not accept unindexed addressing");
7598 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7599 && (((inst
.instruction
& 0x000f0000) >> 16)
7600 == ((inst
.instruction
& 0x0000f000) >> 12)))
7601 as_warn ((inst
.instruction
& LOAD_BIT
)
7602 ? _("destination register same as write-back base")
7603 : _("source register same as write-back base"));
7606 /* inst.operands[i] was set up by parse_address. Encode it into an
7607 ARM-format mode 2 load or store instruction. If is_t is true,
7608 reject forms that cannot be used with a T instruction (i.e. not
7611 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7613 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7615 encode_arm_addr_mode_common (i
, is_t
);
7617 if (inst
.operands
[i
].immisreg
)
7619 constraint ((inst
.operands
[i
].imm
== REG_PC
7620 || (is_pc
&& inst
.operands
[i
].writeback
)),
7622 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7623 inst
.instruction
|= inst
.operands
[i
].imm
;
7624 if (!inst
.operands
[i
].negative
)
7625 inst
.instruction
|= INDEX_UP
;
7626 if (inst
.operands
[i
].shifted
)
7628 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7629 inst
.instruction
|= SHIFT_ROR
<< 5;
7632 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7633 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7637 else /* immediate offset in inst.reloc */
7639 if (is_pc
&& !inst
.reloc
.pc_rel
)
7641 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7643 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7644 cannot use PC in addressing.
7645 PC cannot be used in writeback addressing, either. */
7646 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7649 /* Use of PC in str is deprecated for ARMv7. */
7650 if (warn_on_deprecated
7652 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7653 as_tsktsk (_("use of PC in this instruction is deprecated"));
7656 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7658 /* Prefer + for zero encoded value. */
7659 if (!inst
.operands
[i
].negative
)
7660 inst
.instruction
|= INDEX_UP
;
7661 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7666 /* inst.operands[i] was set up by parse_address. Encode it into an
7667 ARM-format mode 3 load or store instruction. Reject forms that
7668 cannot be used with such instructions. If is_t is true, reject
7669 forms that cannot be used with a T instruction (i.e. not
7672 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7674 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7676 inst
.error
= _("instruction does not accept scaled register index");
7680 encode_arm_addr_mode_common (i
, is_t
);
7682 if (inst
.operands
[i
].immisreg
)
7684 constraint ((inst
.operands
[i
].imm
== REG_PC
7685 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7687 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7689 inst
.instruction
|= inst
.operands
[i
].imm
;
7690 if (!inst
.operands
[i
].negative
)
7691 inst
.instruction
|= INDEX_UP
;
7693 else /* immediate offset in inst.reloc */
7695 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7696 && inst
.operands
[i
].writeback
),
7698 inst
.instruction
|= HWOFFSET_IMM
;
7699 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7701 /* Prefer + for zero encoded value. */
7702 if (!inst
.operands
[i
].negative
)
7703 inst
.instruction
|= INDEX_UP
;
7705 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7710 /* Write immediate bits [7:0] to the following locations:
7712 |28/24|23 19|18 16|15 4|3 0|
7713 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7715 This function is used by VMOV/VMVN/VORR/VBIC. */
7718 neon_write_immbits (unsigned immbits
)
7720 inst
.instruction
|= immbits
& 0xf;
7721 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7722 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7725 /* Invert low-order SIZE bits of XHI:XLO. */
7728 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7730 unsigned immlo
= xlo
? *xlo
: 0;
7731 unsigned immhi
= xhi
? *xhi
: 0;
7736 immlo
= (~immlo
) & 0xff;
7740 immlo
= (~immlo
) & 0xffff;
7744 immhi
= (~immhi
) & 0xffffffff;
7748 immlo
= (~immlo
) & 0xffffffff;
7762 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7766 neon_bits_same_in_bytes (unsigned imm
)
7768 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7769 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7770 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7771 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7774 /* For immediate of above form, return 0bABCD. */
7777 neon_squash_bits (unsigned imm
)
7779 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7780 | ((imm
& 0x01000000) >> 21);
7783 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7786 neon_qfloat_bits (unsigned imm
)
7788 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7791 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7792 the instruction. *OP is passed as the initial value of the op field, and
7793 may be set to a different value depending on the constant (i.e.
7794 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7795 MVN). If the immediate looks like a repeated pattern then also
7796 try smaller element sizes. */
7799 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7800 unsigned *immbits
, int *op
, int size
,
7801 enum neon_el_type type
)
7803 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7805 if (type
== NT_float
&& !float_p
)
7808 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7810 if (size
!= 32 || *op
== 1)
7812 *immbits
= neon_qfloat_bits (immlo
);
7818 if (neon_bits_same_in_bytes (immhi
)
7819 && neon_bits_same_in_bytes (immlo
))
7823 *immbits
= (neon_squash_bits (immhi
) << 4)
7824 | neon_squash_bits (immlo
);
7835 if (immlo
== (immlo
& 0x000000ff))
7840 else if (immlo
== (immlo
& 0x0000ff00))
7842 *immbits
= immlo
>> 8;
7845 else if (immlo
== (immlo
& 0x00ff0000))
7847 *immbits
= immlo
>> 16;
7850 else if (immlo
== (immlo
& 0xff000000))
7852 *immbits
= immlo
>> 24;
7855 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7857 *immbits
= (immlo
>> 8) & 0xff;
7860 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7862 *immbits
= (immlo
>> 16) & 0xff;
7866 if ((immlo
& 0xffff) != (immlo
>> 16))
7873 if (immlo
== (immlo
& 0x000000ff))
7878 else if (immlo
== (immlo
& 0x0000ff00))
7880 *immbits
= immlo
>> 8;
7884 if ((immlo
& 0xff) != (immlo
>> 8))
7889 if (immlo
== (immlo
& 0x000000ff))
7891 /* Don't allow MVN with 8-bit immediate. */
7901 #if defined BFD_HOST_64_BIT
7902 /* Returns TRUE if double precision value V may be cast
7903 to single precision without loss of accuracy. */
7906 is_double_a_single (bfd_int64_t v
)
7908 int exp
= (int)((v
>> 52) & 0x7FF);
7909 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7911 return (exp
== 0 || exp
== 0x7FF
7912 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7913 && (mantissa
& 0x1FFFFFFFl
) == 0;
7916 /* Returns a double precision value casted to single precision
7917 (ignoring the least significant bits in exponent and mantissa). */
7920 double_to_single (bfd_int64_t v
)
7922 int sign
= (int) ((v
>> 63) & 1l);
7923 int exp
= (int) ((v
>> 52) & 0x7FF);
7924 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7930 exp
= exp
- 1023 + 127;
7939 /* No denormalized numbers. */
7945 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7947 #endif /* BFD_HOST_64_BIT */
7956 static void do_vfp_nsyn_opcode (const char *);
7958 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7959 Determine whether it can be performed with a move instruction; if
7960 it can, convert inst.instruction to that move instruction and
7961 return TRUE; if it can't, convert inst.instruction to a literal-pool
7962 load and return FALSE. If this is not a valid thing to do in the
7963 current context, set inst.error and return TRUE.
7965 inst.operands[i] describes the destination register. */
7968 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7971 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7972 bfd_boolean arm_p
= (t
== CONST_ARM
);
7975 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7979 if ((inst
.instruction
& tbit
) == 0)
7981 inst
.error
= _("invalid pseudo operation");
7985 if (inst
.reloc
.exp
.X_op
!= O_constant
7986 && inst
.reloc
.exp
.X_op
!= O_symbol
7987 && inst
.reloc
.exp
.X_op
!= O_big
)
7989 inst
.error
= _("constant expression expected");
7993 if (inst
.reloc
.exp
.X_op
== O_constant
7994 || inst
.reloc
.exp
.X_op
== O_big
)
7996 #if defined BFD_HOST_64_BIT
8001 if (inst
.reloc
.exp
.X_op
== O_big
)
8003 LITTLENUM_TYPE w
[X_PRECISION
];
8006 if (inst
.reloc
.exp
.X_add_number
== -1)
8008 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8010 /* FIXME: Should we check words w[2..5] ? */
8015 #if defined BFD_HOST_64_BIT
8017 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8018 << LITTLENUM_NUMBER_OF_BITS
)
8019 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8020 << LITTLENUM_NUMBER_OF_BITS
)
8021 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8022 << LITTLENUM_NUMBER_OF_BITS
)
8023 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8025 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8026 | (l
[0] & LITTLENUM_MASK
);
8030 v
= inst
.reloc
.exp
.X_add_number
;
8032 if (!inst
.operands
[i
].issingle
)
8036 /* LDR should not use lead in a flag-setting instruction being
8037 chosen so we do not check whether movs can be used. */
8039 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8040 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8041 && inst
.operands
[i
].reg
!= 13
8042 && inst
.operands
[i
].reg
!= 15)
8044 /* Check if on thumb2 it can be done with a mov.w, mvn or
8045 movw instruction. */
8046 unsigned int newimm
;
8047 bfd_boolean isNegated
;
8049 newimm
= encode_thumb32_immediate (v
);
8050 if (newimm
!= (unsigned int) FAIL
)
8054 newimm
= encode_thumb32_immediate (~v
);
8055 if (newimm
!= (unsigned int) FAIL
)
8059 /* The number can be loaded with a mov.w or mvn
8061 if (newimm
!= (unsigned int) FAIL
8062 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8064 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8065 | (inst
.operands
[i
].reg
<< 8));
8066 /* Change to MOVN. */
8067 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8068 inst
.instruction
|= (newimm
& 0x800) << 15;
8069 inst
.instruction
|= (newimm
& 0x700) << 4;
8070 inst
.instruction
|= (newimm
& 0x0ff);
8073 /* The number can be loaded with a movw instruction. */
8074 else if ((v
& ~0xFFFF) == 0
8075 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8077 int imm
= v
& 0xFFFF;
8079 inst
.instruction
= 0xf2400000; /* MOVW. */
8080 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8081 inst
.instruction
|= (imm
& 0xf000) << 4;
8082 inst
.instruction
|= (imm
& 0x0800) << 15;
8083 inst
.instruction
|= (imm
& 0x0700) << 4;
8084 inst
.instruction
|= (imm
& 0x00ff);
8091 int value
= encode_arm_immediate (v
);
8095 /* This can be done with a mov instruction. */
8096 inst
.instruction
&= LITERAL_MASK
;
8097 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8098 inst
.instruction
|= value
& 0xfff;
8102 value
= encode_arm_immediate (~ v
);
8105 /* This can be done with a mvn instruction. */
8106 inst
.instruction
&= LITERAL_MASK
;
8107 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8108 inst
.instruction
|= value
& 0xfff;
8112 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8115 unsigned immbits
= 0;
8116 unsigned immlo
= inst
.operands
[1].imm
;
8117 unsigned immhi
= inst
.operands
[1].regisimm
8118 ? inst
.operands
[1].reg
8119 : inst
.reloc
.exp
.X_unsigned
8121 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8122 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8123 &op
, 64, NT_invtype
);
8127 neon_invert_size (&immlo
, &immhi
, 64);
8129 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8130 &op
, 64, NT_invtype
);
8135 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8141 /* Fill other bits in vmov encoding for both thumb and arm. */
8143 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8145 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8146 neon_write_immbits (immbits
);
8154 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8155 if (inst
.operands
[i
].issingle
8156 && is_quarter_float (inst
.operands
[1].imm
)
8157 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8159 inst
.operands
[1].imm
=
8160 neon_qfloat_bits (v
);
8161 do_vfp_nsyn_opcode ("fconsts");
8165 /* If our host does not support a 64-bit type then we cannot perform
8166 the following optimization. This mean that there will be a
8167 discrepancy between the output produced by an assembler built for
8168 a 32-bit-only host and the output produced from a 64-bit host, but
8169 this cannot be helped. */
8170 #if defined BFD_HOST_64_BIT
8171 else if (!inst
.operands
[1].issingle
8172 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8174 if (is_double_a_single (v
)
8175 && is_quarter_float (double_to_single (v
)))
8177 inst
.operands
[1].imm
=
8178 neon_qfloat_bits (double_to_single (v
));
8179 do_vfp_nsyn_opcode ("fconstd");
8187 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8188 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8191 inst
.operands
[1].reg
= REG_PC
;
8192 inst
.operands
[1].isreg
= 1;
8193 inst
.operands
[1].preind
= 1;
8194 inst
.reloc
.pc_rel
= 1;
8195 inst
.reloc
.type
= (thumb_p
8196 ? BFD_RELOC_ARM_THUMB_OFFSET
8198 ? BFD_RELOC_ARM_HWLITERAL
8199 : BFD_RELOC_ARM_LITERAL
));
8203 /* inst.operands[i] was set up by parse_address. Encode it into an
8204 ARM-format instruction. Reject all forms which cannot be encoded
8205 into a coprocessor load/store instruction. If wb_ok is false,
8206 reject use of writeback; if unind_ok is false, reject use of
8207 unindexed addressing. If reloc_override is not 0, use it instead
8208 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8209 (in which case it is preserved). */
8212 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8214 if (!inst
.operands
[i
].isreg
)
8217 if (! inst
.operands
[0].isvec
)
8219 inst
.error
= _("invalid co-processor operand");
8222 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8226 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8228 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8230 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8232 gas_assert (!inst
.operands
[i
].writeback
);
8235 inst
.error
= _("instruction does not support unindexed addressing");
8238 inst
.instruction
|= inst
.operands
[i
].imm
;
8239 inst
.instruction
|= INDEX_UP
;
8243 if (inst
.operands
[i
].preind
)
8244 inst
.instruction
|= PRE_INDEX
;
8246 if (inst
.operands
[i
].writeback
)
8248 if (inst
.operands
[i
].reg
== REG_PC
)
8250 inst
.error
= _("pc may not be used with write-back");
8255 inst
.error
= _("instruction does not support writeback");
8258 inst
.instruction
|= WRITE_BACK
;
8262 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8263 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8264 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8265 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8268 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8270 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8273 /* Prefer + for zero encoded value. */
8274 if (!inst
.operands
[i
].negative
)
8275 inst
.instruction
|= INDEX_UP
;
8280 /* Functions for instruction encoding, sorted by sub-architecture.
8281 First some generics; their names are taken from the conventional
8282 bit positions for register arguments in ARM format instructions. */
8292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8305 inst
.instruction
|= inst
.operands
[1].reg
;
8311 inst
.instruction
|= inst
.operands
[0].reg
;
8312 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8319 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8325 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8326 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8332 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8333 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8337 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8339 if (ARM_CPU_IS_ANY (cpu_variant
))
8341 as_tsktsk ("%s", msg
);
8344 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8356 unsigned Rn
= inst
.operands
[2].reg
;
8357 /* Enforce restrictions on SWP instruction. */
8358 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8360 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8361 _("Rn must not overlap other operands"));
8363 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8365 if (!check_obsolete (&arm_ext_v8
,
8366 _("swp{b} use is obsoleted for ARMv8 and later"))
8367 && warn_on_deprecated
8368 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8369 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8373 inst
.instruction
|= inst
.operands
[1].reg
;
8374 inst
.instruction
|= Rn
<< 16;
8380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8381 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8382 inst
.instruction
|= inst
.operands
[2].reg
;
8388 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8389 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8390 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8391 || inst
.reloc
.exp
.X_add_number
!= 0),
8393 inst
.instruction
|= inst
.operands
[0].reg
;
8394 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8395 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8401 inst
.instruction
|= inst
.operands
[0].imm
;
8407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8408 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8411 /* ARM instructions, in alphabetical order by function name (except
8412 that wrapper functions appear immediately after the function they
8415 /* This is a pseudo-op of the form "adr rd, label" to be converted
8416 into a relative address of the form "add rd, pc, #label-.-8". */
8421 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8423 /* Frag hacking will turn this into a sub instruction if the offset turns
8424 out to be negative. */
8425 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8426 inst
.reloc
.pc_rel
= 1;
8427 inst
.reloc
.exp
.X_add_number
-= 8;
8429 if (support_interwork
8430 && inst
.reloc
.exp
.X_op
== O_symbol
8431 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8432 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8433 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8434 inst
.reloc
.exp
.X_add_number
|= 1;
8437 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8438 into a relative address of the form:
8439 add rd, pc, #low(label-.-8)"
8440 add rd, rd, #high(label-.-8)" */
8445 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8447 /* Frag hacking will turn this into a sub instruction if the offset turns
8448 out to be negative. */
8449 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8450 inst
.reloc
.pc_rel
= 1;
8451 inst
.size
= INSN_SIZE
* 2;
8452 inst
.reloc
.exp
.X_add_number
-= 8;
8454 if (support_interwork
8455 && inst
.reloc
.exp
.X_op
== O_symbol
8456 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8457 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8458 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8459 inst
.reloc
.exp
.X_add_number
|= 1;
8465 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8466 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8468 if (!inst
.operands
[1].present
)
8469 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8471 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8472 encode_arm_shifter_operand (2);
8478 if (inst
.operands
[0].present
)
8479 inst
.instruction
|= inst
.operands
[0].imm
;
8481 inst
.instruction
|= 0xf;
8487 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8488 constraint (msb
> 32, _("bit-field extends past end of register"));
8489 /* The instruction encoding stores the LSB and MSB,
8490 not the LSB and width. */
8491 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8492 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8493 inst
.instruction
|= (msb
- 1) << 16;
8501 /* #0 in second position is alternative syntax for bfc, which is
8502 the same instruction but with REG_PC in the Rm field. */
8503 if (!inst
.operands
[1].isreg
)
8504 inst
.operands
[1].reg
= REG_PC
;
8506 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8507 constraint (msb
> 32, _("bit-field extends past end of register"));
8508 /* The instruction encoding stores the LSB and MSB,
8509 not the LSB and width. */
8510 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8511 inst
.instruction
|= inst
.operands
[1].reg
;
8512 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8513 inst
.instruction
|= (msb
- 1) << 16;
8519 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8520 _("bit-field extends past end of register"));
8521 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8522 inst
.instruction
|= inst
.operands
[1].reg
;
8523 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8524 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8527 /* ARM V5 breakpoint instruction (argument parse)
8528 BKPT <16 bit unsigned immediate>
8529 Instruction is not conditional.
8530 The bit pattern given in insns[] has the COND_ALWAYS condition,
8531 and it is an error if the caller tried to override that. */
8536 /* Top 12 of 16 bits to bits 19:8. */
8537 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8539 /* Bottom 4 of 16 bits to bits 3:0. */
8540 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8544 encode_branch (int default_reloc
)
8546 if (inst
.operands
[0].hasreloc
)
8548 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8549 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8550 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8551 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8552 ? BFD_RELOC_ARM_PLT32
8553 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8556 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8557 inst
.reloc
.pc_rel
= 1;
8564 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8565 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8568 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8575 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8577 if (inst
.cond
== COND_ALWAYS
)
8578 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8580 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8584 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8587 /* ARM V5 branch-link-exchange instruction (argument parse)
8588 BLX <target_addr> ie BLX(1)
8589 BLX{<condition>} <Rm> ie BLX(2)
8590 Unfortunately, there are two different opcodes for this mnemonic.
8591 So, the insns[].value is not used, and the code here zaps values
8592 into inst.instruction.
8593 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8598 if (inst
.operands
[0].isreg
)
8600 /* Arg is a register; the opcode provided by insns[] is correct.
8601 It is not illegal to do "blx pc", just useless. */
8602 if (inst
.operands
[0].reg
== REG_PC
)
8603 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8605 inst
.instruction
|= inst
.operands
[0].reg
;
8609 /* Arg is an address; this instruction cannot be executed
8610 conditionally, and the opcode must be adjusted.
8611 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8612 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8613 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8614 inst
.instruction
= 0xfa000000;
8615 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8622 bfd_boolean want_reloc
;
8624 if (inst
.operands
[0].reg
== REG_PC
)
8625 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8627 inst
.instruction
|= inst
.operands
[0].reg
;
8628 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8629 it is for ARMv4t or earlier. */
8630 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8631 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8632 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8636 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8641 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8645 /* ARM v5TEJ. Jump to Jazelle code. */
8650 if (inst
.operands
[0].reg
== REG_PC
)
8651 as_tsktsk (_("use of r15 in bxj is not really useful"));
8653 inst
.instruction
|= inst
.operands
[0].reg
;
8656 /* Co-processor data operation:
8657 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8658 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8662 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8663 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8664 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8665 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8666 inst
.instruction
|= inst
.operands
[4].reg
;
8667 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8673 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8674 encode_arm_shifter_operand (1);
8677 /* Transfer between coprocessor and ARM registers.
8678 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8683 No special properties. */
8685 struct deprecated_coproc_regs_s
8692 arm_feature_set deprecated
;
8693 arm_feature_set obsoleted
;
8694 const char *dep_msg
;
8695 const char *obs_msg
;
8698 #define DEPR_ACCESS_V8 \
8699 N_("This coprocessor register access is deprecated in ARMv8")
8701 /* Table of all deprecated coprocessor registers. */
8702 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8704 {15, 0, 7, 10, 5, /* CP15DMB. */
8705 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8706 DEPR_ACCESS_V8
, NULL
},
8707 {15, 0, 7, 10, 4, /* CP15DSB. */
8708 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8709 DEPR_ACCESS_V8
, NULL
},
8710 {15, 0, 7, 5, 4, /* CP15ISB. */
8711 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8712 DEPR_ACCESS_V8
, NULL
},
8713 {14, 6, 1, 0, 0, /* TEEHBR. */
8714 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8715 DEPR_ACCESS_V8
, NULL
},
8716 {14, 6, 0, 0, 0, /* TEECR. */
8717 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8718 DEPR_ACCESS_V8
, NULL
},
8721 #undef DEPR_ACCESS_V8
8723 static const size_t deprecated_coproc_reg_count
=
8724 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8732 Rd
= inst
.operands
[2].reg
;
8735 if (inst
.instruction
== 0xee000010
8736 || inst
.instruction
== 0xfe000010)
8738 reject_bad_reg (Rd
);
8739 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8741 constraint (Rd
== REG_SP
, BAD_SP
);
8746 if (inst
.instruction
== 0xe000010)
8747 constraint (Rd
== REG_PC
, BAD_PC
);
8750 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8752 const struct deprecated_coproc_regs_s
*r
=
8753 deprecated_coproc_regs
+ i
;
8755 if (inst
.operands
[0].reg
== r
->cp
8756 && inst
.operands
[1].imm
== r
->opc1
8757 && inst
.operands
[3].reg
== r
->crn
8758 && inst
.operands
[4].reg
== r
->crm
8759 && inst
.operands
[5].imm
== r
->opc2
)
8761 if (! ARM_CPU_IS_ANY (cpu_variant
)
8762 && warn_on_deprecated
8763 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8764 as_tsktsk ("%s", r
->dep_msg
);
8768 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8769 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8770 inst
.instruction
|= Rd
<< 12;
8771 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8772 inst
.instruction
|= inst
.operands
[4].reg
;
8773 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8776 /* Transfer between coprocessor register and pair of ARM registers.
8777 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8782 Two XScale instructions are special cases of these:
8784 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8785 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8787 Result unpredictable if Rd or Rn is R15. */
8794 Rd
= inst
.operands
[2].reg
;
8795 Rn
= inst
.operands
[3].reg
;
8799 reject_bad_reg (Rd
);
8800 reject_bad_reg (Rn
);
8804 constraint (Rd
== REG_PC
, BAD_PC
);
8805 constraint (Rn
== REG_PC
, BAD_PC
);
8808 /* Only check the MRRC{2} variants. */
8809 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8811 /* If Rd == Rn, error that the operation is
8812 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8813 constraint (Rd
== Rn
, BAD_OVERLAP
);
8816 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8817 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8818 inst
.instruction
|= Rd
<< 12;
8819 inst
.instruction
|= Rn
<< 16;
8820 inst
.instruction
|= inst
.operands
[4].reg
;
8826 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8827 if (inst
.operands
[1].present
)
8829 inst
.instruction
|= CPSI_MMOD
;
8830 inst
.instruction
|= inst
.operands
[1].imm
;
8837 inst
.instruction
|= inst
.operands
[0].imm
;
8843 unsigned Rd
, Rn
, Rm
;
8845 Rd
= inst
.operands
[0].reg
;
8846 Rn
= (inst
.operands
[1].present
8847 ? inst
.operands
[1].reg
: Rd
);
8848 Rm
= inst
.operands
[2].reg
;
8850 constraint ((Rd
== REG_PC
), BAD_PC
);
8851 constraint ((Rn
== REG_PC
), BAD_PC
);
8852 constraint ((Rm
== REG_PC
), BAD_PC
);
8854 inst
.instruction
|= Rd
<< 16;
8855 inst
.instruction
|= Rn
<< 0;
8856 inst
.instruction
|= Rm
<< 8;
8862 /* There is no IT instruction in ARM mode. We
8863 process it to do the validation as if in
8864 thumb mode, just in case the code gets
8865 assembled for thumb using the unified syntax. */
8870 set_it_insn_type (IT_INSN
);
8871 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8872 now_it
.cc
= inst
.operands
[0].imm
;
8876 /* If there is only one register in the register list,
8877 then return its register number. Otherwise return -1. */
8879 only_one_reg_in_list (int range
)
8881 int i
= ffs (range
) - 1;
8882 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8886 encode_ldmstm(int from_push_pop_mnem
)
8888 int base_reg
= inst
.operands
[0].reg
;
8889 int range
= inst
.operands
[1].imm
;
8892 inst
.instruction
|= base_reg
<< 16;
8893 inst
.instruction
|= range
;
8895 if (inst
.operands
[1].writeback
)
8896 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8898 if (inst
.operands
[0].writeback
)
8900 inst
.instruction
|= WRITE_BACK
;
8901 /* Check for unpredictable uses of writeback. */
8902 if (inst
.instruction
& LOAD_BIT
)
8904 /* Not allowed in LDM type 2. */
8905 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8906 && ((range
& (1 << REG_PC
)) == 0))
8907 as_warn (_("writeback of base register is UNPREDICTABLE"));
8908 /* Only allowed if base reg not in list for other types. */
8909 else if (range
& (1 << base_reg
))
8910 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8914 /* Not allowed for type 2. */
8915 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8916 as_warn (_("writeback of base register is UNPREDICTABLE"));
8917 /* Only allowed if base reg not in list, or first in list. */
8918 else if ((range
& (1 << base_reg
))
8919 && (range
& ((1 << base_reg
) - 1)))
8920 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8924 /* If PUSH/POP has only one register, then use the A2 encoding. */
8925 one_reg
= only_one_reg_in_list (range
);
8926 if (from_push_pop_mnem
&& one_reg
>= 0)
8928 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8930 if (is_push
&& one_reg
== 13 /* SP */)
8931 /* PR 22483: The A2 encoding cannot be used when
8932 pushing the stack pointer as this is UNPREDICTABLE. */
8935 inst
.instruction
&= A_COND_MASK
;
8936 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8937 inst
.instruction
|= one_reg
<< 12;
8944 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8947 /* ARMv5TE load-consecutive (argument parse)
8956 constraint (inst
.operands
[0].reg
% 2 != 0,
8957 _("first transfer register must be even"));
8958 constraint (inst
.operands
[1].present
8959 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8960 _("can only transfer two consecutive registers"));
8961 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8962 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8964 if (!inst
.operands
[1].present
)
8965 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8967 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8968 register and the first register written; we have to diagnose
8969 overlap between the base and the second register written here. */
8971 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8972 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8973 as_warn (_("base register written back, and overlaps "
8974 "second transfer register"));
8976 if (!(inst
.instruction
& V4_STR_BIT
))
8978 /* For an index-register load, the index register must not overlap the
8979 destination (even if not write-back). */
8980 if (inst
.operands
[2].immisreg
8981 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8982 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8983 as_warn (_("index register overlaps transfer register"));
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8986 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8992 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8993 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8994 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8995 || inst
.operands
[1].negative
8996 /* This can arise if the programmer has written
8998 or if they have mistakenly used a register name as the last
9001 It is very difficult to distinguish between these two cases
9002 because "rX" might actually be a label. ie the register
9003 name has been occluded by a symbol of the same name. So we
9004 just generate a general 'bad addressing mode' type error
9005 message and leave it up to the programmer to discover the
9006 true cause and fix their mistake. */
9007 || (inst
.operands
[1].reg
== REG_PC
),
9010 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9011 || inst
.reloc
.exp
.X_add_number
!= 0,
9012 _("offset must be zero in ARM encoding"));
9014 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9017 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9018 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9024 constraint (inst
.operands
[0].reg
% 2 != 0,
9025 _("even register required"));
9026 constraint (inst
.operands
[1].present
9027 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9028 _("can only load two consecutive registers"));
9029 /* If op 1 were present and equal to PC, this function wouldn't
9030 have been called in the first place. */
9031 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9034 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9037 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9038 which is not a multiple of four is UNPREDICTABLE. */
9040 check_ldr_r15_aligned (void)
9042 constraint (!(inst
.operands
[1].immisreg
)
9043 && (inst
.operands
[0].reg
== REG_PC
9044 && inst
.operands
[1].reg
== REG_PC
9045 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9046 _("ldr to register 15 must be 4-byte aligned"));
9052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9053 if (!inst
.operands
[1].isreg
)
9054 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9056 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9057 check_ldr_r15_aligned ();
9063 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9065 if (inst
.operands
[1].preind
)
9067 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9068 || inst
.reloc
.exp
.X_add_number
!= 0,
9069 _("this instruction requires a post-indexed address"));
9071 inst
.operands
[1].preind
= 0;
9072 inst
.operands
[1].postind
= 1;
9073 inst
.operands
[1].writeback
= 1;
9075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9076 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9079 /* Halfword and signed-byte load/store operations. */
9084 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9086 if (!inst
.operands
[1].isreg
)
9087 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9089 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9095 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9097 if (inst
.operands
[1].preind
)
9099 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9100 || inst
.reloc
.exp
.X_add_number
!= 0,
9101 _("this instruction requires a post-indexed address"));
9103 inst
.operands
[1].preind
= 0;
9104 inst
.operands
[1].postind
= 1;
9105 inst
.operands
[1].writeback
= 1;
9107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9108 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9111 /* Co-processor register load/store.
9112 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9116 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9117 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9118 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9124 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9125 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9126 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9127 && !(inst
.instruction
& 0x00400000))
9128 as_tsktsk (_("Rd and Rm should be different in mla"));
9130 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9131 inst
.instruction
|= inst
.operands
[1].reg
;
9132 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9133 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9139 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9140 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9142 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9143 encode_arm_shifter_operand (1);
9146 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9153 top
= (inst
.instruction
& 0x00400000) != 0;
9154 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9155 _(":lower16: not allowed in this instruction"));
9156 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9157 _(":upper16: not allowed in this instruction"));
9158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9159 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9161 imm
= inst
.reloc
.exp
.X_add_number
;
9162 /* The value is in two pieces: 0:11, 16:19. */
9163 inst
.instruction
|= (imm
& 0x00000fff);
9164 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9169 do_vfp_nsyn_mrs (void)
9171 if (inst
.operands
[0].isvec
)
9173 if (inst
.operands
[1].reg
!= 1)
9174 first_error (_("operand 1 must be FPSCR"));
9175 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9176 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9177 do_vfp_nsyn_opcode ("fmstat");
9179 else if (inst
.operands
[1].isvec
)
9180 do_vfp_nsyn_opcode ("fmrx");
9188 do_vfp_nsyn_msr (void)
9190 if (inst
.operands
[0].isvec
)
9191 do_vfp_nsyn_opcode ("fmxr");
9201 unsigned Rt
= inst
.operands
[0].reg
;
9203 if (thumb_mode
&& Rt
== REG_SP
)
9205 inst
.error
= BAD_SP
;
9209 /* MVFR2 is only valid at ARMv8-A. */
9210 if (inst
.operands
[1].reg
== 5)
9211 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9214 /* APSR_ sets isvec. All other refs to PC are illegal. */
9215 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9217 inst
.error
= BAD_PC
;
9221 /* If we get through parsing the register name, we just insert the number
9222 generated into the instruction without further validation. */
9223 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9224 inst
.instruction
|= (Rt
<< 12);
9230 unsigned Rt
= inst
.operands
[1].reg
;
9233 reject_bad_reg (Rt
);
9234 else if (Rt
== REG_PC
)
9236 inst
.error
= BAD_PC
;
9240 /* MVFR2 is only valid for ARMv8-A. */
9241 if (inst
.operands
[0].reg
== 5)
9242 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9245 /* If we get through parsing the register name, we just insert the number
9246 generated into the instruction without further validation. */
9247 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9248 inst
.instruction
|= (Rt
<< 12);
9256 if (do_vfp_nsyn_mrs () == SUCCESS
)
9259 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9260 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9262 if (inst
.operands
[1].isreg
)
9264 br
= inst
.operands
[1].reg
;
9265 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9266 as_bad (_("bad register for mrs"));
9270 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9271 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9273 _("'APSR', 'CPSR' or 'SPSR' expected"));
9274 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9277 inst
.instruction
|= br
;
9280 /* Two possible forms:
9281 "{C|S}PSR_<field>, Rm",
9282 "{C|S}PSR_f, #expression". */
9287 if (do_vfp_nsyn_msr () == SUCCESS
)
9290 inst
.instruction
|= inst
.operands
[0].imm
;
9291 if (inst
.operands
[1].isreg
)
9292 inst
.instruction
|= inst
.operands
[1].reg
;
9295 inst
.instruction
|= INST_IMMEDIATE
;
9296 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9297 inst
.reloc
.pc_rel
= 0;
9304 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9306 if (!inst
.operands
[2].present
)
9307 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9308 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9309 inst
.instruction
|= inst
.operands
[1].reg
;
9310 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9312 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9313 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9314 as_tsktsk (_("Rd and Rm should be different in mul"));
9317 /* Long Multiply Parser
9318 UMULL RdLo, RdHi, Rm, Rs
9319 SMULL RdLo, RdHi, Rm, Rs
9320 UMLAL RdLo, RdHi, Rm, Rs
9321 SMLAL RdLo, RdHi, Rm, Rs. */
9326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9327 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9328 inst
.instruction
|= inst
.operands
[2].reg
;
9329 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9331 /* rdhi and rdlo must be different. */
9332 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9333 as_tsktsk (_("rdhi and rdlo must be different"));
9335 /* rdhi, rdlo and rm must all be different before armv6. */
9336 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9337 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9338 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9339 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9345 if (inst
.operands
[0].present
9346 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9348 /* Architectural NOP hints are CPSR sets with no bits selected. */
9349 inst
.instruction
&= 0xf0000000;
9350 inst
.instruction
|= 0x0320f000;
9351 if (inst
.operands
[0].present
)
9352 inst
.instruction
|= inst
.operands
[0].imm
;
9356 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9357 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9358 Condition defaults to COND_ALWAYS.
9359 Error if Rd, Rn or Rm are R15. */
9364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9365 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9366 inst
.instruction
|= inst
.operands
[2].reg
;
9367 if (inst
.operands
[3].present
)
9368 encode_arm_shift (3);
9371 /* ARM V6 PKHTB (Argument Parse). */
9376 if (!inst
.operands
[3].present
)
9378 /* If the shift specifier is omitted, turn the instruction
9379 into pkhbt rd, rm, rn. */
9380 inst
.instruction
&= 0xfff00010;
9381 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9382 inst
.instruction
|= inst
.operands
[1].reg
;
9383 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9388 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9389 inst
.instruction
|= inst
.operands
[2].reg
;
9390 encode_arm_shift (3);
9394 /* ARMv5TE: Preload-Cache
9395 MP Extensions: Preload for write
9399 Syntactically, like LDR with B=1, W=0, L=1. */
9404 constraint (!inst
.operands
[0].isreg
,
9405 _("'[' expected after PLD mnemonic"));
9406 constraint (inst
.operands
[0].postind
,
9407 _("post-indexed expression used in preload instruction"));
9408 constraint (inst
.operands
[0].writeback
,
9409 _("writeback used in preload instruction"));
9410 constraint (!inst
.operands
[0].preind
,
9411 _("unindexed addressing used in preload instruction"));
9412 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9415 /* ARMv7: PLI <addr_mode> */
9419 constraint (!inst
.operands
[0].isreg
,
9420 _("'[' expected after PLI mnemonic"));
9421 constraint (inst
.operands
[0].postind
,
9422 _("post-indexed expression used in preload instruction"));
9423 constraint (inst
.operands
[0].writeback
,
9424 _("writeback used in preload instruction"));
9425 constraint (!inst
.operands
[0].preind
,
9426 _("unindexed addressing used in preload instruction"));
9427 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9428 inst
.instruction
&= ~PRE_INDEX
;
9434 constraint (inst
.operands
[0].writeback
,
9435 _("push/pop do not support {reglist}^"));
9436 inst
.operands
[1] = inst
.operands
[0];
9437 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9438 inst
.operands
[0].isreg
= 1;
9439 inst
.operands
[0].writeback
= 1;
9440 inst
.operands
[0].reg
= REG_SP
;
9441 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9444 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9445 word at the specified address and the following word
9447 Unconditionally executed.
9448 Error if Rn is R15. */
9453 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9454 if (inst
.operands
[0].writeback
)
9455 inst
.instruction
|= WRITE_BACK
;
9458 /* ARM V6 ssat (argument parse). */
9463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9464 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9465 inst
.instruction
|= inst
.operands
[2].reg
;
9467 if (inst
.operands
[3].present
)
9468 encode_arm_shift (3);
9471 /* ARM V6 usat (argument parse). */
9476 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9477 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9478 inst
.instruction
|= inst
.operands
[2].reg
;
9480 if (inst
.operands
[3].present
)
9481 encode_arm_shift (3);
9484 /* ARM V6 ssat16 (argument parse). */
9489 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9490 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9491 inst
.instruction
|= inst
.operands
[2].reg
;
9497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9498 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9499 inst
.instruction
|= inst
.operands
[2].reg
;
9502 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9503 preserving the other bits.
9505 setend <endian_specifier>, where <endian_specifier> is either
9511 if (warn_on_deprecated
9512 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9513 as_tsktsk (_("setend use is deprecated for ARMv8"));
9515 if (inst
.operands
[0].imm
)
9516 inst
.instruction
|= 0x200;
9522 unsigned int Rm
= (inst
.operands
[1].present
9523 ? inst
.operands
[1].reg
9524 : inst
.operands
[0].reg
);
9526 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9527 inst
.instruction
|= Rm
;
9528 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9530 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9531 inst
.instruction
|= SHIFT_BY_REG
;
9532 /* PR 12854: Error on extraneous shifts. */
9533 constraint (inst
.operands
[2].shifted
,
9534 _("extraneous shift as part of operand to shift insn"));
9537 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9543 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9544 inst
.reloc
.pc_rel
= 0;
9550 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9551 inst
.reloc
.pc_rel
= 0;
9557 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9558 inst
.reloc
.pc_rel
= 0;
9564 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9565 _("selected processor does not support SETPAN instruction"));
9567 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9573 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9574 _("selected processor does not support SETPAN instruction"));
9576 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9579 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9580 SMLAxy{cond} Rd,Rm,Rs,Rn
9581 SMLAWy{cond} Rd,Rm,Rs,Rn
9582 Error if any register is R15. */
9587 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9588 inst
.instruction
|= inst
.operands
[1].reg
;
9589 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9590 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9593 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9594 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9595 Error if any register is R15.
9596 Warning if Rdlo == Rdhi. */
9601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9602 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9603 inst
.instruction
|= inst
.operands
[2].reg
;
9604 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9606 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9607 as_tsktsk (_("rdhi and rdlo must be different"));
9610 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9611 SMULxy{cond} Rd,Rm,Rs
9612 Error if any register is R15. */
9617 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9618 inst
.instruction
|= inst
.operands
[1].reg
;
9619 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9622 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9623 the same for both ARM and Thumb-2. */
9630 if (inst
.operands
[0].present
)
9632 reg
= inst
.operands
[0].reg
;
9633 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9638 inst
.instruction
|= reg
<< 16;
9639 inst
.instruction
|= inst
.operands
[1].imm
;
9640 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9641 inst
.instruction
|= WRITE_BACK
;
9644 /* ARM V6 strex (argument parse). */
9649 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9650 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9651 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9652 || inst
.operands
[2].negative
9653 /* See comment in do_ldrex(). */
9654 || (inst
.operands
[2].reg
== REG_PC
),
9657 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9658 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9660 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9661 || inst
.reloc
.exp
.X_add_number
!= 0,
9662 _("offset must be zero in ARM encoding"));
9664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9665 inst
.instruction
|= inst
.operands
[1].reg
;
9666 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9667 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9673 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9674 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9675 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9676 || inst
.operands
[2].negative
,
9679 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9680 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9688 constraint (inst
.operands
[1].reg
% 2 != 0,
9689 _("even register required"));
9690 constraint (inst
.operands
[2].present
9691 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9692 _("can only store two consecutive registers"));
9693 /* If op 2 were present and equal to PC, this function wouldn't
9694 have been called in the first place. */
9695 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9697 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9698 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9699 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9702 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9703 inst
.instruction
|= inst
.operands
[1].reg
;
9704 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9711 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9712 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9720 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9721 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9726 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9727 extends it to 32-bits, and adds the result to a value in another
9728 register. You can specify a rotation by 0, 8, 16, or 24 bits
9729 before extracting the 16-bit value.
9730 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9731 Condition defaults to COND_ALWAYS.
9732 Error if any register uses R15. */
9737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9738 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9739 inst
.instruction
|= inst
.operands
[2].reg
;
9740 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9745 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9746 Condition defaults to COND_ALWAYS.
9747 Error if any register uses R15. */
9752 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9753 inst
.instruction
|= inst
.operands
[1].reg
;
9754 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9757 /* VFP instructions. In a logical order: SP variant first, monad
9758 before dyad, arithmetic then move then load/store. */
9761 do_vfp_sp_monadic (void)
9763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9764 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9768 do_vfp_sp_dyadic (void)
9770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9771 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9772 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9776 do_vfp_sp_compare_z (void)
9778 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9782 do_vfp_dp_sp_cvt (void)
9784 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9785 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9789 do_vfp_sp_dp_cvt (void)
9791 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9792 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9796 do_vfp_reg_from_sp (void)
9798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9799 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9803 do_vfp_reg2_from_sp2 (void)
9805 constraint (inst
.operands
[2].imm
!= 2,
9806 _("only two consecutive VFP SP registers allowed here"));
9807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9808 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9809 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9813 do_vfp_sp_from_reg (void)
9815 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9816 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9820 do_vfp_sp2_from_reg2 (void)
9822 constraint (inst
.operands
[0].imm
!= 2,
9823 _("only two consecutive VFP SP registers allowed here"));
9824 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9825 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9826 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9830 do_vfp_sp_ldst (void)
9832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9833 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9837 do_vfp_dp_ldst (void)
9839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9840 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9845 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9847 if (inst
.operands
[0].writeback
)
9848 inst
.instruction
|= WRITE_BACK
;
9850 constraint (ldstm_type
!= VFP_LDSTMIA
,
9851 _("this addressing mode requires base-register writeback"));
9852 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9853 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9854 inst
.instruction
|= inst
.operands
[1].imm
;
9858 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9862 if (inst
.operands
[0].writeback
)
9863 inst
.instruction
|= WRITE_BACK
;
9865 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9866 _("this addressing mode requires base-register writeback"));
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9869 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9871 count
= inst
.operands
[1].imm
<< 1;
9872 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9875 inst
.instruction
|= count
;
9879 do_vfp_sp_ldstmia (void)
9881 vfp_sp_ldstm (VFP_LDSTMIA
);
9885 do_vfp_sp_ldstmdb (void)
9887 vfp_sp_ldstm (VFP_LDSTMDB
);
9891 do_vfp_dp_ldstmia (void)
9893 vfp_dp_ldstm (VFP_LDSTMIA
);
9897 do_vfp_dp_ldstmdb (void)
9899 vfp_dp_ldstm (VFP_LDSTMDB
);
9903 do_vfp_xp_ldstmia (void)
9905 vfp_dp_ldstm (VFP_LDSTMIAX
);
9909 do_vfp_xp_ldstmdb (void)
9911 vfp_dp_ldstm (VFP_LDSTMDBX
);
9915 do_vfp_dp_rd_rm (void)
9917 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9918 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9922 do_vfp_dp_rn_rd (void)
9924 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9925 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9929 do_vfp_dp_rd_rn (void)
9931 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9932 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9936 do_vfp_dp_rd_rn_rm (void)
9938 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9939 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9940 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9946 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9950 do_vfp_dp_rm_rd_rn (void)
9952 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9953 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9954 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9957 /* VFPv3 instructions. */
9959 do_vfp_sp_const (void)
9961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9962 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9963 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9967 do_vfp_dp_const (void)
9969 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9970 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9971 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9975 vfp_conv (int srcsize
)
9977 int immbits
= srcsize
- inst
.operands
[1].imm
;
9979 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9981 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9982 i.e. immbits must be in range 0 - 16. */
9983 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9986 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9988 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9989 i.e. immbits must be in range 0 - 31. */
9990 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9994 inst
.instruction
|= (immbits
& 1) << 5;
9995 inst
.instruction
|= (immbits
>> 1);
9999 do_vfp_sp_conv_16 (void)
10001 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10006 do_vfp_dp_conv_16 (void)
10008 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10013 do_vfp_sp_conv_32 (void)
10015 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10020 do_vfp_dp_conv_32 (void)
10022 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10026 /* FPA instructions. Also in a logical order. */
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10032 inst
.instruction
|= inst
.operands
[1].reg
;
10036 do_fpa_ldmstm (void)
10038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10039 switch (inst
.operands
[1].imm
)
10041 case 1: inst
.instruction
|= CP_T_X
; break;
10042 case 2: inst
.instruction
|= CP_T_Y
; break;
10043 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10048 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10050 /* The instruction specified "ea" or "fd", so we can only accept
10051 [Rn]{!}. The instruction does not really support stacking or
10052 unstacking, so we have to emulate these by setting appropriate
10053 bits and offsets. */
10054 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10055 || inst
.reloc
.exp
.X_add_number
!= 0,
10056 _("this instruction does not support indexing"));
10058 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10059 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10061 if (!(inst
.instruction
& INDEX_UP
))
10062 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10064 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10066 inst
.operands
[2].preind
= 0;
10067 inst
.operands
[2].postind
= 1;
10071 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10074 /* iWMMXt instructions: strictly in alphabetical order. */
10077 do_iwmmxt_tandorc (void)
10079 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10083 do_iwmmxt_textrc (void)
10085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10086 inst
.instruction
|= inst
.operands
[1].imm
;
10090 do_iwmmxt_textrm (void)
10092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10093 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10094 inst
.instruction
|= inst
.operands
[2].imm
;
10098 do_iwmmxt_tinsr (void)
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10101 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10102 inst
.instruction
|= inst
.operands
[2].imm
;
10106 do_iwmmxt_tmia (void)
10108 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10109 inst
.instruction
|= inst
.operands
[1].reg
;
10110 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10114 do_iwmmxt_waligni (void)
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10118 inst
.instruction
|= inst
.operands
[2].reg
;
10119 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10123 do_iwmmxt_wmerge (void)
10125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10126 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10127 inst
.instruction
|= inst
.operands
[2].reg
;
10128 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10132 do_iwmmxt_wmov (void)
10134 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10137 inst
.instruction
|= inst
.operands
[1].reg
;
10141 do_iwmmxt_wldstbh (void)
10144 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10146 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10148 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10149 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10153 do_iwmmxt_wldstw (void)
10155 /* RIWR_RIWC clears .isreg for a control register. */
10156 if (!inst
.operands
[0].isreg
)
10158 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10159 inst
.instruction
|= 0xf0000000;
10162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10163 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10167 do_iwmmxt_wldstd (void)
10169 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10171 && inst
.operands
[1].immisreg
)
10173 inst
.instruction
&= ~0x1a000ff;
10174 inst
.instruction
|= (0xfU
<< 28);
10175 if (inst
.operands
[1].preind
)
10176 inst
.instruction
|= PRE_INDEX
;
10177 if (!inst
.operands
[1].negative
)
10178 inst
.instruction
|= INDEX_UP
;
10179 if (inst
.operands
[1].writeback
)
10180 inst
.instruction
|= WRITE_BACK
;
10181 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10182 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10183 inst
.instruction
|= inst
.operands
[1].imm
;
10186 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10190 do_iwmmxt_wshufh (void)
10192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10193 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10194 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10195 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10199 do_iwmmxt_wzero (void)
10201 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10202 inst
.instruction
|= inst
.operands
[0].reg
;
10203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10204 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10208 do_iwmmxt_wrwrwr_or_imm5 (void)
10210 if (inst
.operands
[2].isreg
)
10213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10214 _("immediate operand requires iWMMXt2"));
10216 if (inst
.operands
[2].imm
== 0)
10218 switch ((inst
.instruction
>> 20) & 0xf)
10224 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10225 inst
.operands
[2].imm
= 16;
10226 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10232 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10233 inst
.operands
[2].imm
= 32;
10234 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10241 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10243 wrn
= (inst
.instruction
>> 16) & 0xf;
10244 inst
.instruction
&= 0xff0fff0f;
10245 inst
.instruction
|= wrn
;
10246 /* Bail out here; the instruction is now assembled. */
10251 /* Map 32 -> 0, etc. */
10252 inst
.operands
[2].imm
&= 0x1f;
10253 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10257 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10258 operations first, then control, shift, and load/store. */
10260 /* Insns like "foo X,Y,Z". */
10263 do_mav_triple (void)
10265 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10266 inst
.instruction
|= inst
.operands
[1].reg
;
10267 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10270 /* Insns like "foo W,X,Y,Z".
10271 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10276 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10277 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10278 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10279 inst
.instruction
|= inst
.operands
[3].reg
;
10282 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10284 do_mav_dspsc (void)
10286 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10289 /* Maverick shift immediate instructions.
10290 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10291 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10294 do_mav_shift (void)
10296 int imm
= inst
.operands
[2].imm
;
10298 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10299 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10301 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10302 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10303 Bit 4 should be 0. */
10304 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10306 inst
.instruction
|= imm
;
10309 /* XScale instructions. Also sorted arithmetic before move. */
10311 /* Xscale multiply-accumulate (argument parse)
10314 MIAxycc acc0,Rm,Rs. */
10319 inst
.instruction
|= inst
.operands
[1].reg
;
10320 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10323 /* Xscale move-accumulator-register (argument parse)
10325 MARcc acc0,RdLo,RdHi. */
10330 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10331 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10334 /* Xscale move-register-accumulator (argument parse)
10336 MRAcc RdLo,RdHi,acc0. */
10341 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10343 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10346 /* Encoding functions relevant only to Thumb. */
10348 /* inst.operands[i] is a shifted-register operand; encode
10349 it into inst.instruction in the format used by Thumb32. */
10352 encode_thumb32_shifted_operand (int i
)
10354 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10355 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10357 constraint (inst
.operands
[i
].immisreg
,
10358 _("shift by register not allowed in thumb mode"));
10359 inst
.instruction
|= inst
.operands
[i
].reg
;
10360 if (shift
== SHIFT_RRX
)
10361 inst
.instruction
|= SHIFT_ROR
<< 4;
10364 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10365 _("expression too complex"));
10367 constraint (value
> 32
10368 || (value
== 32 && (shift
== SHIFT_LSL
10369 || shift
== SHIFT_ROR
)),
10370 _("shift expression is too large"));
10374 else if (value
== 32)
10377 inst
.instruction
|= shift
<< 4;
10378 inst
.instruction
|= (value
& 0x1c) << 10;
10379 inst
.instruction
|= (value
& 0x03) << 6;
10384 /* inst.operands[i] was set up by parse_address. Encode it into a
10385 Thumb32 format load or store instruction. Reject forms that cannot
10386 be used with such instructions. If is_t is true, reject forms that
10387 cannot be used with a T instruction; if is_d is true, reject forms
10388 that cannot be used with a D instruction. If it is a store insn,
10389 reject PC in Rn. */
10392 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10394 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10396 constraint (!inst
.operands
[i
].isreg
,
10397 _("Instruction does not support =N addresses"));
10399 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10400 if (inst
.operands
[i
].immisreg
)
10402 constraint (is_pc
, BAD_PC_ADDRESSING
);
10403 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10404 constraint (inst
.operands
[i
].negative
,
10405 _("Thumb does not support negative register indexing"));
10406 constraint (inst
.operands
[i
].postind
,
10407 _("Thumb does not support register post-indexing"));
10408 constraint (inst
.operands
[i
].writeback
,
10409 _("Thumb does not support register indexing with writeback"));
10410 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10411 _("Thumb supports only LSL in shifted register indexing"));
10413 inst
.instruction
|= inst
.operands
[i
].imm
;
10414 if (inst
.operands
[i
].shifted
)
10416 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10417 _("expression too complex"));
10418 constraint (inst
.reloc
.exp
.X_add_number
< 0
10419 || inst
.reloc
.exp
.X_add_number
> 3,
10420 _("shift out of range"));
10421 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10423 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10425 else if (inst
.operands
[i
].preind
)
10427 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10428 constraint (is_t
&& inst
.operands
[i
].writeback
,
10429 _("cannot use writeback with this instruction"));
10430 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10431 BAD_PC_ADDRESSING
);
10435 inst
.instruction
|= 0x01000000;
10436 if (inst
.operands
[i
].writeback
)
10437 inst
.instruction
|= 0x00200000;
10441 inst
.instruction
|= 0x00000c00;
10442 if (inst
.operands
[i
].writeback
)
10443 inst
.instruction
|= 0x00000100;
10445 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10447 else if (inst
.operands
[i
].postind
)
10449 gas_assert (inst
.operands
[i
].writeback
);
10450 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10451 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10454 inst
.instruction
|= 0x00200000;
10456 inst
.instruction
|= 0x00000900;
10457 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10459 else /* unindexed - only for coprocessor */
10460 inst
.error
= _("instruction does not accept unindexed addressing");
10463 /* Table of Thumb instructions which exist in both 16- and 32-bit
10464 encodings (the latter only in post-V6T2 cores). The index is the
10465 value used in the insns table below. When there is more than one
10466 possible 16-bit encoding for the instruction, this table always
10468 Also contains several pseudo-instructions used during relaxation. */
10469 #define T16_32_TAB \
10470 X(_adc, 4140, eb400000), \
10471 X(_adcs, 4140, eb500000), \
10472 X(_add, 1c00, eb000000), \
10473 X(_adds, 1c00, eb100000), \
10474 X(_addi, 0000, f1000000), \
10475 X(_addis, 0000, f1100000), \
10476 X(_add_pc,000f, f20f0000), \
10477 X(_add_sp,000d, f10d0000), \
10478 X(_adr, 000f, f20f0000), \
10479 X(_and, 4000, ea000000), \
10480 X(_ands, 4000, ea100000), \
10481 X(_asr, 1000, fa40f000), \
10482 X(_asrs, 1000, fa50f000), \
10483 X(_b, e000, f000b000), \
10484 X(_bcond, d000, f0008000), \
10485 X(_bic, 4380, ea200000), \
10486 X(_bics, 4380, ea300000), \
10487 X(_cmn, 42c0, eb100f00), \
10488 X(_cmp, 2800, ebb00f00), \
10489 X(_cpsie, b660, f3af8400), \
10490 X(_cpsid, b670, f3af8600), \
10491 X(_cpy, 4600, ea4f0000), \
10492 X(_dec_sp,80dd, f1ad0d00), \
10493 X(_eor, 4040, ea800000), \
10494 X(_eors, 4040, ea900000), \
10495 X(_inc_sp,00dd, f10d0d00), \
10496 X(_ldmia, c800, e8900000), \
10497 X(_ldr, 6800, f8500000), \
10498 X(_ldrb, 7800, f8100000), \
10499 X(_ldrh, 8800, f8300000), \
10500 X(_ldrsb, 5600, f9100000), \
10501 X(_ldrsh, 5e00, f9300000), \
10502 X(_ldr_pc,4800, f85f0000), \
10503 X(_ldr_pc2,4800, f85f0000), \
10504 X(_ldr_sp,9800, f85d0000), \
10505 X(_lsl, 0000, fa00f000), \
10506 X(_lsls, 0000, fa10f000), \
10507 X(_lsr, 0800, fa20f000), \
10508 X(_lsrs, 0800, fa30f000), \
10509 X(_mov, 2000, ea4f0000), \
10510 X(_movs, 2000, ea5f0000), \
10511 X(_mul, 4340, fb00f000), \
10512 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10513 X(_mvn, 43c0, ea6f0000), \
10514 X(_mvns, 43c0, ea7f0000), \
10515 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10516 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10517 X(_orr, 4300, ea400000), \
10518 X(_orrs, 4300, ea500000), \
10519 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10520 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10521 X(_rev, ba00, fa90f080), \
10522 X(_rev16, ba40, fa90f090), \
10523 X(_revsh, bac0, fa90f0b0), \
10524 X(_ror, 41c0, fa60f000), \
10525 X(_rors, 41c0, fa70f000), \
10526 X(_sbc, 4180, eb600000), \
10527 X(_sbcs, 4180, eb700000), \
10528 X(_stmia, c000, e8800000), \
10529 X(_str, 6000, f8400000), \
10530 X(_strb, 7000, f8000000), \
10531 X(_strh, 8000, f8200000), \
10532 X(_str_sp,9000, f84d0000), \
10533 X(_sub, 1e00, eba00000), \
10534 X(_subs, 1e00, ebb00000), \
10535 X(_subi, 8000, f1a00000), \
10536 X(_subis, 8000, f1b00000), \
10537 X(_sxtb, b240, fa4ff080), \
10538 X(_sxth, b200, fa0ff080), \
10539 X(_tst, 4200, ea100f00), \
10540 X(_uxtb, b2c0, fa5ff080), \
10541 X(_uxth, b280, fa1ff080), \
10542 X(_nop, bf00, f3af8000), \
10543 X(_yield, bf10, f3af8001), \
10544 X(_wfe, bf20, f3af8002), \
10545 X(_wfi, bf30, f3af8003), \
10546 X(_sev, bf40, f3af8004), \
10547 X(_sevl, bf50, f3af8005), \
10548 X(_udf, de00, f7f0a000)
10550 /* To catch errors in encoding functions, the codes are all offset by
10551 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10552 as 16-bit instructions. */
10553 #define X(a,b,c) T_MNEM##a
10554 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10557 #define X(a,b,c) 0x##b
10558 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10559 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10562 #define X(a,b,c) 0x##c
10563 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10564 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10565 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10569 /* Thumb instruction encoders, in alphabetical order. */
10571 /* ADDW or SUBW. */
10574 do_t_add_sub_w (void)
10578 Rd
= inst
.operands
[0].reg
;
10579 Rn
= inst
.operands
[1].reg
;
10581 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10582 is the SP-{plus,minus}-immediate form of the instruction. */
10584 constraint (Rd
== REG_PC
, BAD_PC
);
10586 reject_bad_reg (Rd
);
10588 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10589 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10592 /* Parse an add or subtract instruction. We get here with inst.instruction
10593 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10596 do_t_add_sub (void)
10600 Rd
= inst
.operands
[0].reg
;
10601 Rs
= (inst
.operands
[1].present
10602 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10603 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10606 set_it_insn_type_last ();
10608 if (unified_syntax
)
10611 bfd_boolean narrow
;
10614 flags
= (inst
.instruction
== T_MNEM_adds
10615 || inst
.instruction
== T_MNEM_subs
);
10617 narrow
= !in_it_block ();
10619 narrow
= in_it_block ();
10620 if (!inst
.operands
[2].isreg
)
10624 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10625 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10627 add
= (inst
.instruction
== T_MNEM_add
10628 || inst
.instruction
== T_MNEM_adds
);
10630 if (inst
.size_req
!= 4)
10632 /* Attempt to use a narrow opcode, with relaxation if
10634 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10635 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10636 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10637 opcode
= T_MNEM_add_sp
;
10638 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10639 opcode
= T_MNEM_add_pc
;
10640 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10643 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10645 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10649 inst
.instruction
= THUMB_OP16(opcode
);
10650 inst
.instruction
|= (Rd
<< 4) | Rs
;
10651 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10652 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10654 if (inst
.size_req
== 2)
10655 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10657 inst
.relax
= opcode
;
10661 constraint (inst
.size_req
== 2, BAD_HIREG
);
10663 if (inst
.size_req
== 4
10664 || (inst
.size_req
!= 2 && !opcode
))
10666 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10667 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10668 THUMB1_RELOC_ONLY
);
10671 constraint (add
, BAD_PC
);
10672 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10673 _("only SUBS PC, LR, #const allowed"));
10674 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10675 _("expression too complex"));
10676 constraint (inst
.reloc
.exp
.X_add_number
< 0
10677 || inst
.reloc
.exp
.X_add_number
> 0xff,
10678 _("immediate value out of range"));
10679 inst
.instruction
= T2_SUBS_PC_LR
10680 | inst
.reloc
.exp
.X_add_number
;
10681 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10684 else if (Rs
== REG_PC
)
10686 /* Always use addw/subw. */
10687 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10688 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10692 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10693 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10696 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10698 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10700 inst
.instruction
|= Rd
<< 8;
10701 inst
.instruction
|= Rs
<< 16;
10706 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10707 unsigned int shift
= inst
.operands
[2].shift_kind
;
10709 Rn
= inst
.operands
[2].reg
;
10710 /* See if we can do this with a 16-bit instruction. */
10711 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10713 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10718 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10719 || inst
.instruction
== T_MNEM_add
)
10721 : T_OPCODE_SUB_R3
);
10722 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10726 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10728 /* Thumb-1 cores (except v6-M) require at least one high
10729 register in a narrow non flag setting add. */
10730 if (Rd
> 7 || Rn
> 7
10731 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10732 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10739 inst
.instruction
= T_OPCODE_ADD_HI
;
10740 inst
.instruction
|= (Rd
& 8) << 4;
10741 inst
.instruction
|= (Rd
& 7);
10742 inst
.instruction
|= Rn
<< 3;
10748 constraint (Rd
== REG_PC
, BAD_PC
);
10749 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10750 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10751 constraint (Rs
== REG_PC
, BAD_PC
);
10752 reject_bad_reg (Rn
);
10754 /* If we get here, it can't be done in 16 bits. */
10755 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10756 _("shift must be constant"));
10757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10758 inst
.instruction
|= Rd
<< 8;
10759 inst
.instruction
|= Rs
<< 16;
10760 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10761 _("shift value over 3 not allowed in thumb mode"));
10762 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10763 _("only LSL shift allowed in thumb mode"));
10764 encode_thumb32_shifted_operand (2);
10769 constraint (inst
.instruction
== T_MNEM_adds
10770 || inst
.instruction
== T_MNEM_subs
,
10773 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10775 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10776 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10779 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10780 ? 0x0000 : 0x8000);
10781 inst
.instruction
|= (Rd
<< 4) | Rs
;
10782 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10786 Rn
= inst
.operands
[2].reg
;
10787 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10789 /* We now have Rd, Rs, and Rn set to registers. */
10790 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10792 /* Can't do this for SUB. */
10793 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10794 inst
.instruction
= T_OPCODE_ADD_HI
;
10795 inst
.instruction
|= (Rd
& 8) << 4;
10796 inst
.instruction
|= (Rd
& 7);
10798 inst
.instruction
|= Rn
<< 3;
10800 inst
.instruction
|= Rs
<< 3;
10802 constraint (1, _("dest must overlap one source register"));
10806 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10807 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10808 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10818 Rd
= inst
.operands
[0].reg
;
10819 reject_bad_reg (Rd
);
10821 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10823 /* Defer to section relaxation. */
10824 inst
.relax
= inst
.instruction
;
10825 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10826 inst
.instruction
|= Rd
<< 4;
10828 else if (unified_syntax
&& inst
.size_req
!= 2)
10830 /* Generate a 32-bit opcode. */
10831 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10832 inst
.instruction
|= Rd
<< 8;
10833 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10834 inst
.reloc
.pc_rel
= 1;
10838 /* Generate a 16-bit opcode. */
10839 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10840 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10841 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10842 inst
.reloc
.pc_rel
= 1;
10843 inst
.instruction
|= Rd
<< 4;
10846 if (inst
.reloc
.exp
.X_op
== O_symbol
10847 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10848 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10849 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10850 inst
.reloc
.exp
.X_add_number
+= 1;
10853 /* Arithmetic instructions for which there is just one 16-bit
10854 instruction encoding, and it allows only two low registers.
10855 For maximal compatibility with ARM syntax, we allow three register
10856 operands even when Thumb-32 instructions are not available, as long
10857 as the first two are identical. For instance, both "sbc r0,r1" and
10858 "sbc r0,r0,r1" are allowed. */
10864 Rd
= inst
.operands
[0].reg
;
10865 Rs
= (inst
.operands
[1].present
10866 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10867 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10868 Rn
= inst
.operands
[2].reg
;
10870 reject_bad_reg (Rd
);
10871 reject_bad_reg (Rs
);
10872 if (inst
.operands
[2].isreg
)
10873 reject_bad_reg (Rn
);
10875 if (unified_syntax
)
10877 if (!inst
.operands
[2].isreg
)
10879 /* For an immediate, we always generate a 32-bit opcode;
10880 section relaxation will shrink it later if possible. */
10881 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10882 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10883 inst
.instruction
|= Rd
<< 8;
10884 inst
.instruction
|= Rs
<< 16;
10885 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10889 bfd_boolean narrow
;
10891 /* See if we can do this with a 16-bit instruction. */
10892 if (THUMB_SETS_FLAGS (inst
.instruction
))
10893 narrow
= !in_it_block ();
10895 narrow
= in_it_block ();
10897 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10899 if (inst
.operands
[2].shifted
)
10901 if (inst
.size_req
== 4)
10907 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10908 inst
.instruction
|= Rd
;
10909 inst
.instruction
|= Rn
<< 3;
10913 /* If we get here, it can't be done in 16 bits. */
10914 constraint (inst
.operands
[2].shifted
10915 && inst
.operands
[2].immisreg
,
10916 _("shift must be constant"));
10917 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10918 inst
.instruction
|= Rd
<< 8;
10919 inst
.instruction
|= Rs
<< 16;
10920 encode_thumb32_shifted_operand (2);
10925 /* On its face this is a lie - the instruction does set the
10926 flags. However, the only supported mnemonic in this mode
10927 says it doesn't. */
10928 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10930 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10931 _("unshifted register required"));
10932 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10933 constraint (Rd
!= Rs
,
10934 _("dest and source1 must be the same register"));
10936 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10937 inst
.instruction
|= Rd
;
10938 inst
.instruction
|= Rn
<< 3;
10942 /* Similarly, but for instructions where the arithmetic operation is
10943 commutative, so we can allow either of them to be different from
10944 the destination operand in a 16-bit instruction. For instance, all
10945 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10952 Rd
= inst
.operands
[0].reg
;
10953 Rs
= (inst
.operands
[1].present
10954 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10955 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10956 Rn
= inst
.operands
[2].reg
;
10958 reject_bad_reg (Rd
);
10959 reject_bad_reg (Rs
);
10960 if (inst
.operands
[2].isreg
)
10961 reject_bad_reg (Rn
);
10963 if (unified_syntax
)
10965 if (!inst
.operands
[2].isreg
)
10967 /* For an immediate, we always generate a 32-bit opcode;
10968 section relaxation will shrink it later if possible. */
10969 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10970 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10971 inst
.instruction
|= Rd
<< 8;
10972 inst
.instruction
|= Rs
<< 16;
10973 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10977 bfd_boolean narrow
;
10979 /* See if we can do this with a 16-bit instruction. */
10980 if (THUMB_SETS_FLAGS (inst
.instruction
))
10981 narrow
= !in_it_block ();
10983 narrow
= in_it_block ();
10985 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10987 if (inst
.operands
[2].shifted
)
10989 if (inst
.size_req
== 4)
10996 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10997 inst
.instruction
|= Rd
;
10998 inst
.instruction
|= Rn
<< 3;
11003 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11004 inst
.instruction
|= Rd
;
11005 inst
.instruction
|= Rs
<< 3;
11010 /* If we get here, it can't be done in 16 bits. */
11011 constraint (inst
.operands
[2].shifted
11012 && inst
.operands
[2].immisreg
,
11013 _("shift must be constant"));
11014 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11015 inst
.instruction
|= Rd
<< 8;
11016 inst
.instruction
|= Rs
<< 16;
11017 encode_thumb32_shifted_operand (2);
11022 /* On its face this is a lie - the instruction does set the
11023 flags. However, the only supported mnemonic in this mode
11024 says it doesn't. */
11025 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11027 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11028 _("unshifted register required"));
11029 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11031 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11032 inst
.instruction
|= Rd
;
11035 inst
.instruction
|= Rn
<< 3;
11037 inst
.instruction
|= Rs
<< 3;
11039 constraint (1, _("dest must overlap one source register"));
11047 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11048 constraint (msb
> 32, _("bit-field extends past end of register"));
11049 /* The instruction encoding stores the LSB and MSB,
11050 not the LSB and width. */
11051 Rd
= inst
.operands
[0].reg
;
11052 reject_bad_reg (Rd
);
11053 inst
.instruction
|= Rd
<< 8;
11054 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11055 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11056 inst
.instruction
|= msb
- 1;
11065 Rd
= inst
.operands
[0].reg
;
11066 reject_bad_reg (Rd
);
11068 /* #0 in second position is alternative syntax for bfc, which is
11069 the same instruction but with REG_PC in the Rm field. */
11070 if (!inst
.operands
[1].isreg
)
11074 Rn
= inst
.operands
[1].reg
;
11075 reject_bad_reg (Rn
);
11078 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11079 constraint (msb
> 32, _("bit-field extends past end of register"));
11080 /* The instruction encoding stores the LSB and MSB,
11081 not the LSB and width. */
11082 inst
.instruction
|= Rd
<< 8;
11083 inst
.instruction
|= Rn
<< 16;
11084 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11085 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11086 inst
.instruction
|= msb
- 1;
11094 Rd
= inst
.operands
[0].reg
;
11095 Rn
= inst
.operands
[1].reg
;
11097 reject_bad_reg (Rd
);
11098 reject_bad_reg (Rn
);
11100 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11101 _("bit-field extends past end of register"));
11102 inst
.instruction
|= Rd
<< 8;
11103 inst
.instruction
|= Rn
<< 16;
11104 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11105 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11106 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11109 /* ARM V5 Thumb BLX (argument parse)
11110 BLX <target_addr> which is BLX(1)
11111 BLX <Rm> which is BLX(2)
11112 Unfortunately, there are two different opcodes for this mnemonic.
11113 So, the insns[].value is not used, and the code here zaps values
11114 into inst.instruction.
11116 ??? How to take advantage of the additional two bits of displacement
11117 available in Thumb32 mode? Need new relocation? */
11122 set_it_insn_type_last ();
11124 if (inst
.operands
[0].isreg
)
11126 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11127 /* We have a register, so this is BLX(2). */
11128 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11132 /* No register. This must be BLX(1). */
11133 inst
.instruction
= 0xf000e800;
11134 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11143 bfd_reloc_code_real_type reloc
;
11146 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11148 if (in_it_block ())
11150 /* Conditional branches inside IT blocks are encoded as unconditional
11152 cond
= COND_ALWAYS
;
11157 if (cond
!= COND_ALWAYS
)
11158 opcode
= T_MNEM_bcond
;
11160 opcode
= inst
.instruction
;
11163 && (inst
.size_req
== 4
11164 || (inst
.size_req
!= 2
11165 && (inst
.operands
[0].hasreloc
11166 || inst
.reloc
.exp
.X_op
== O_constant
))))
11168 inst
.instruction
= THUMB_OP32(opcode
);
11169 if (cond
== COND_ALWAYS
)
11170 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11173 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11174 _("selected architecture does not support "
11175 "wide conditional branch instruction"));
11177 gas_assert (cond
!= 0xF);
11178 inst
.instruction
|= cond
<< 22;
11179 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11184 inst
.instruction
= THUMB_OP16(opcode
);
11185 if (cond
== COND_ALWAYS
)
11186 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11189 inst
.instruction
|= cond
<< 8;
11190 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11192 /* Allow section relaxation. */
11193 if (unified_syntax
&& inst
.size_req
!= 2)
11194 inst
.relax
= opcode
;
11196 inst
.reloc
.type
= reloc
;
11197 inst
.reloc
.pc_rel
= 1;
11200 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11201 between the two is the maximum immediate allowed - which is passed in
11204 do_t_bkpt_hlt1 (int range
)
11206 constraint (inst
.cond
!= COND_ALWAYS
,
11207 _("instruction is always unconditional"));
11208 if (inst
.operands
[0].present
)
11210 constraint (inst
.operands
[0].imm
> range
,
11211 _("immediate value out of range"));
11212 inst
.instruction
|= inst
.operands
[0].imm
;
11215 set_it_insn_type (NEUTRAL_IT_INSN
);
11221 do_t_bkpt_hlt1 (63);
11227 do_t_bkpt_hlt1 (255);
11231 do_t_branch23 (void)
11233 set_it_insn_type_last ();
11234 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11236 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11237 this file. We used to simply ignore the PLT reloc type here --
11238 the branch encoding is now needed to deal with TLSCALL relocs.
11239 So if we see a PLT reloc now, put it back to how it used to be to
11240 keep the preexisting behaviour. */
11241 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11242 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11244 #if defined(OBJ_COFF)
11245 /* If the destination of the branch is a defined symbol which does not have
11246 the THUMB_FUNC attribute, then we must be calling a function which has
11247 the (interfacearm) attribute. We look for the Thumb entry point to that
11248 function and change the branch to refer to that function instead. */
11249 if ( inst
.reloc
.exp
.X_op
== O_symbol
11250 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11251 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11252 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11253 inst
.reloc
.exp
.X_add_symbol
=
11254 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11261 set_it_insn_type_last ();
11262 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11263 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11264 should cause the alignment to be checked once it is known. This is
11265 because BX PC only works if the instruction is word aligned. */
11273 set_it_insn_type_last ();
11274 Rm
= inst
.operands
[0].reg
;
11275 reject_bad_reg (Rm
);
11276 inst
.instruction
|= Rm
<< 16;
11285 Rd
= inst
.operands
[0].reg
;
11286 Rm
= inst
.operands
[1].reg
;
11288 reject_bad_reg (Rd
);
11289 reject_bad_reg (Rm
);
11291 inst
.instruction
|= Rd
<< 8;
11292 inst
.instruction
|= Rm
<< 16;
11293 inst
.instruction
|= Rm
;
11299 set_it_insn_type (OUTSIDE_IT_INSN
);
11305 set_it_insn_type (OUTSIDE_IT_INSN
);
11306 inst
.instruction
|= inst
.operands
[0].imm
;
11312 set_it_insn_type (OUTSIDE_IT_INSN
);
11314 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11315 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11317 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11318 inst
.instruction
= 0xf3af8000;
11319 inst
.instruction
|= imod
<< 9;
11320 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11321 if (inst
.operands
[1].present
)
11322 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11327 && (inst
.operands
[0].imm
& 4),
11328 _("selected processor does not support 'A' form "
11329 "of this instruction"));
11330 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11331 _("Thumb does not support the 2-argument "
11332 "form of this instruction"));
11333 inst
.instruction
|= inst
.operands
[0].imm
;
11337 /* THUMB CPY instruction (argument parse). */
11342 if (inst
.size_req
== 4)
11344 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11345 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11346 inst
.instruction
|= inst
.operands
[1].reg
;
11350 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11351 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11352 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11359 set_it_insn_type (OUTSIDE_IT_INSN
);
11360 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11361 inst
.instruction
|= inst
.operands
[0].reg
;
11362 inst
.reloc
.pc_rel
= 1;
11363 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11369 inst
.instruction
|= inst
.operands
[0].imm
;
11375 unsigned Rd
, Rn
, Rm
;
11377 Rd
= inst
.operands
[0].reg
;
11378 Rn
= (inst
.operands
[1].present
11379 ? inst
.operands
[1].reg
: Rd
);
11380 Rm
= inst
.operands
[2].reg
;
11382 reject_bad_reg (Rd
);
11383 reject_bad_reg (Rn
);
11384 reject_bad_reg (Rm
);
11386 inst
.instruction
|= Rd
<< 8;
11387 inst
.instruction
|= Rn
<< 16;
11388 inst
.instruction
|= Rm
;
11394 if (unified_syntax
&& inst
.size_req
== 4)
11395 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11397 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11403 unsigned int cond
= inst
.operands
[0].imm
;
11405 set_it_insn_type (IT_INSN
);
11406 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11408 now_it
.warn_deprecated
= FALSE
;
11410 /* If the condition is a negative condition, invert the mask. */
11411 if ((cond
& 0x1) == 0x0)
11413 unsigned int mask
= inst
.instruction
& 0x000f;
11415 if ((mask
& 0x7) == 0)
11417 /* No conversion needed. */
11418 now_it
.block_length
= 1;
11420 else if ((mask
& 0x3) == 0)
11423 now_it
.block_length
= 2;
11425 else if ((mask
& 0x1) == 0)
11428 now_it
.block_length
= 3;
11433 now_it
.block_length
= 4;
11436 inst
.instruction
&= 0xfff0;
11437 inst
.instruction
|= mask
;
11440 inst
.instruction
|= cond
<< 4;
11443 /* Helper function used for both push/pop and ldm/stm. */
11445 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11449 load
= (inst
.instruction
& (1 << 20)) != 0;
11451 if (mask
& (1 << 13))
11452 inst
.error
= _("SP not allowed in register list");
11454 if ((mask
& (1 << base
)) != 0
11456 inst
.error
= _("having the base register in the register list when "
11457 "using write back is UNPREDICTABLE");
11461 if (mask
& (1 << 15))
11463 if (mask
& (1 << 14))
11464 inst
.error
= _("LR and PC should not both be in register list");
11466 set_it_insn_type_last ();
11471 if (mask
& (1 << 15))
11472 inst
.error
= _("PC not allowed in register list");
11475 if ((mask
& (mask
- 1)) == 0)
11477 /* Single register transfers implemented as str/ldr. */
11480 if (inst
.instruction
& (1 << 23))
11481 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11483 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11487 if (inst
.instruction
& (1 << 23))
11488 inst
.instruction
= 0x00800000; /* ia -> [base] */
11490 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11493 inst
.instruction
|= 0xf8400000;
11495 inst
.instruction
|= 0x00100000;
11497 mask
= ffs (mask
) - 1;
11500 else if (writeback
)
11501 inst
.instruction
|= WRITE_BACK
;
11503 inst
.instruction
|= mask
;
11504 inst
.instruction
|= base
<< 16;
11510 /* This really doesn't seem worth it. */
11511 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11512 _("expression too complex"));
11513 constraint (inst
.operands
[1].writeback
,
11514 _("Thumb load/store multiple does not support {reglist}^"));
11516 if (unified_syntax
)
11518 bfd_boolean narrow
;
11522 /* See if we can use a 16-bit instruction. */
11523 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11524 && inst
.size_req
!= 4
11525 && !(inst
.operands
[1].imm
& ~0xff))
11527 mask
= 1 << inst
.operands
[0].reg
;
11529 if (inst
.operands
[0].reg
<= 7)
11531 if (inst
.instruction
== T_MNEM_stmia
11532 ? inst
.operands
[0].writeback
11533 : (inst
.operands
[0].writeback
11534 == !(inst
.operands
[1].imm
& mask
)))
11536 if (inst
.instruction
== T_MNEM_stmia
11537 && (inst
.operands
[1].imm
& mask
)
11538 && (inst
.operands
[1].imm
& (mask
- 1)))
11539 as_warn (_("value stored for r%d is UNKNOWN"),
11540 inst
.operands
[0].reg
);
11542 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11543 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11544 inst
.instruction
|= inst
.operands
[1].imm
;
11547 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11549 /* This means 1 register in reg list one of 3 situations:
11550 1. Instruction is stmia, but without writeback.
11551 2. lmdia without writeback, but with Rn not in
11553 3. ldmia with writeback, but with Rn in reglist.
11554 Case 3 is UNPREDICTABLE behaviour, so we handle
11555 case 1 and 2 which can be converted into a 16-bit
11556 str or ldr. The SP cases are handled below. */
11557 unsigned long opcode
;
11558 /* First, record an error for Case 3. */
11559 if (inst
.operands
[1].imm
& mask
11560 && inst
.operands
[0].writeback
)
11562 _("having the base register in the register list when "
11563 "using write back is UNPREDICTABLE");
11565 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11567 inst
.instruction
= THUMB_OP16 (opcode
);
11568 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11569 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11573 else if (inst
.operands
[0] .reg
== REG_SP
)
11575 if (inst
.operands
[0].writeback
)
11578 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11579 ? T_MNEM_push
: T_MNEM_pop
);
11580 inst
.instruction
|= inst
.operands
[1].imm
;
11583 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11586 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11587 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11588 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11596 if (inst
.instruction
< 0xffff)
11597 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11599 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11600 inst
.operands
[0].writeback
);
11605 constraint (inst
.operands
[0].reg
> 7
11606 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11607 constraint (inst
.instruction
!= T_MNEM_ldmia
11608 && inst
.instruction
!= T_MNEM_stmia
,
11609 _("Thumb-2 instruction only valid in unified syntax"));
11610 if (inst
.instruction
== T_MNEM_stmia
)
11612 if (!inst
.operands
[0].writeback
)
11613 as_warn (_("this instruction will write back the base register"));
11614 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11615 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11616 as_warn (_("value stored for r%d is UNKNOWN"),
11617 inst
.operands
[0].reg
);
11621 if (!inst
.operands
[0].writeback
11622 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11623 as_warn (_("this instruction will write back the base register"));
11624 else if (inst
.operands
[0].writeback
11625 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11626 as_warn (_("this instruction will not write back the base register"));
11629 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11630 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11631 inst
.instruction
|= inst
.operands
[1].imm
;
11638 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11639 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11640 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11641 || inst
.operands
[1].negative
,
11644 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11647 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11648 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11654 if (!inst
.operands
[1].present
)
11656 constraint (inst
.operands
[0].reg
== REG_LR
,
11657 _("r14 not allowed as first register "
11658 "when second register is omitted"));
11659 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11661 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11665 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11666 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11672 unsigned long opcode
;
11675 if (inst
.operands
[0].isreg
11676 && !inst
.operands
[0].preind
11677 && inst
.operands
[0].reg
== REG_PC
)
11678 set_it_insn_type_last ();
11680 opcode
= inst
.instruction
;
11681 if (unified_syntax
)
11683 if (!inst
.operands
[1].isreg
)
11685 if (opcode
<= 0xffff)
11686 inst
.instruction
= THUMB_OP32 (opcode
);
11687 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11690 if (inst
.operands
[1].isreg
11691 && !inst
.operands
[1].writeback
11692 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11693 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11694 && opcode
<= 0xffff
11695 && inst
.size_req
!= 4)
11697 /* Insn may have a 16-bit form. */
11698 Rn
= inst
.operands
[1].reg
;
11699 if (inst
.operands
[1].immisreg
)
11701 inst
.instruction
= THUMB_OP16 (opcode
);
11703 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11705 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11706 reject_bad_reg (inst
.operands
[1].imm
);
11708 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11709 && opcode
!= T_MNEM_ldrsb
)
11710 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11711 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11718 if (inst
.reloc
.pc_rel
)
11719 opcode
= T_MNEM_ldr_pc2
;
11721 opcode
= T_MNEM_ldr_pc
;
11725 if (opcode
== T_MNEM_ldr
)
11726 opcode
= T_MNEM_ldr_sp
;
11728 opcode
= T_MNEM_str_sp
;
11730 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11734 inst
.instruction
= inst
.operands
[0].reg
;
11735 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11737 inst
.instruction
|= THUMB_OP16 (opcode
);
11738 if (inst
.size_req
== 2)
11739 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11741 inst
.relax
= opcode
;
11745 /* Definitely a 32-bit variant. */
11747 /* Warning for Erratum 752419. */
11748 if (opcode
== T_MNEM_ldr
11749 && inst
.operands
[0].reg
== REG_SP
11750 && inst
.operands
[1].writeback
== 1
11751 && !inst
.operands
[1].immisreg
)
11753 if (no_cpu_selected ()
11754 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11755 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11756 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11757 as_warn (_("This instruction may be unpredictable "
11758 "if executed on M-profile cores "
11759 "with interrupts enabled."));
11762 /* Do some validations regarding addressing modes. */
11763 if (inst
.operands
[1].immisreg
)
11764 reject_bad_reg (inst
.operands
[1].imm
);
11766 constraint (inst
.operands
[1].writeback
== 1
11767 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11770 inst
.instruction
= THUMB_OP32 (opcode
);
11771 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11772 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11773 check_ldr_r15_aligned ();
11777 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11779 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11781 /* Only [Rn,Rm] is acceptable. */
11782 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11783 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11784 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11785 || inst
.operands
[1].negative
,
11786 _("Thumb does not support this addressing mode"));
11787 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11791 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11792 if (!inst
.operands
[1].isreg
)
11793 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11796 constraint (!inst
.operands
[1].preind
11797 || inst
.operands
[1].shifted
11798 || inst
.operands
[1].writeback
,
11799 _("Thumb does not support this addressing mode"));
11800 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11802 constraint (inst
.instruction
& 0x0600,
11803 _("byte or halfword not valid for base register"));
11804 constraint (inst
.operands
[1].reg
== REG_PC
11805 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11806 _("r15 based store not allowed"));
11807 constraint (inst
.operands
[1].immisreg
,
11808 _("invalid base register for register offset"));
11810 if (inst
.operands
[1].reg
== REG_PC
)
11811 inst
.instruction
= T_OPCODE_LDR_PC
;
11812 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11813 inst
.instruction
= T_OPCODE_LDR_SP
;
11815 inst
.instruction
= T_OPCODE_STR_SP
;
11817 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11818 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11822 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11823 if (!inst
.operands
[1].immisreg
)
11825 /* Immediate offset. */
11826 inst
.instruction
|= inst
.operands
[0].reg
;
11827 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11828 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11832 /* Register offset. */
11833 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11834 constraint (inst
.operands
[1].negative
,
11835 _("Thumb does not support this addressing mode"));
11838 switch (inst
.instruction
)
11840 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11841 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11842 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11843 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11844 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11845 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11846 case 0x5600 /* ldrsb */:
11847 case 0x5e00 /* ldrsh */: break;
11851 inst
.instruction
|= inst
.operands
[0].reg
;
11852 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11853 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11859 if (!inst
.operands
[1].present
)
11861 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11862 constraint (inst
.operands
[0].reg
== REG_LR
,
11863 _("r14 not allowed here"));
11864 constraint (inst
.operands
[0].reg
== REG_R12
,
11865 _("r12 not allowed here"));
11868 if (inst
.operands
[2].writeback
11869 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11870 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11871 as_warn (_("base register written back, and overlaps "
11872 "one of transfer registers"));
11874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11875 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11876 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11883 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11889 unsigned Rd
, Rn
, Rm
, Ra
;
11891 Rd
= inst
.operands
[0].reg
;
11892 Rn
= inst
.operands
[1].reg
;
11893 Rm
= inst
.operands
[2].reg
;
11894 Ra
= inst
.operands
[3].reg
;
11896 reject_bad_reg (Rd
);
11897 reject_bad_reg (Rn
);
11898 reject_bad_reg (Rm
);
11899 reject_bad_reg (Ra
);
11901 inst
.instruction
|= Rd
<< 8;
11902 inst
.instruction
|= Rn
<< 16;
11903 inst
.instruction
|= Rm
;
11904 inst
.instruction
|= Ra
<< 12;
11910 unsigned RdLo
, RdHi
, Rn
, Rm
;
11912 RdLo
= inst
.operands
[0].reg
;
11913 RdHi
= inst
.operands
[1].reg
;
11914 Rn
= inst
.operands
[2].reg
;
11915 Rm
= inst
.operands
[3].reg
;
11917 reject_bad_reg (RdLo
);
11918 reject_bad_reg (RdHi
);
11919 reject_bad_reg (Rn
);
11920 reject_bad_reg (Rm
);
11922 inst
.instruction
|= RdLo
<< 12;
11923 inst
.instruction
|= RdHi
<< 8;
11924 inst
.instruction
|= Rn
<< 16;
11925 inst
.instruction
|= Rm
;
11929 do_t_mov_cmp (void)
11933 Rn
= inst
.operands
[0].reg
;
11934 Rm
= inst
.operands
[1].reg
;
11937 set_it_insn_type_last ();
11939 if (unified_syntax
)
11941 int r0off
= (inst
.instruction
== T_MNEM_mov
11942 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11943 unsigned long opcode
;
11944 bfd_boolean narrow
;
11945 bfd_boolean low_regs
;
11947 low_regs
= (Rn
<= 7 && Rm
<= 7);
11948 opcode
= inst
.instruction
;
11949 if (in_it_block ())
11950 narrow
= opcode
!= T_MNEM_movs
;
11952 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11953 if (inst
.size_req
== 4
11954 || inst
.operands
[1].shifted
)
11957 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11958 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11959 && !inst
.operands
[1].shifted
11963 inst
.instruction
= T2_SUBS_PC_LR
;
11967 if (opcode
== T_MNEM_cmp
)
11969 constraint (Rn
== REG_PC
, BAD_PC
);
11972 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11974 warn_deprecated_sp (Rm
);
11975 /* R15 was documented as a valid choice for Rm in ARMv6,
11976 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11977 tools reject R15, so we do too. */
11978 constraint (Rm
== REG_PC
, BAD_PC
);
11981 reject_bad_reg (Rm
);
11983 else if (opcode
== T_MNEM_mov
11984 || opcode
== T_MNEM_movs
)
11986 if (inst
.operands
[1].isreg
)
11988 if (opcode
== T_MNEM_movs
)
11990 reject_bad_reg (Rn
);
11991 reject_bad_reg (Rm
);
11995 /* This is mov.n. */
11996 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11997 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11999 as_tsktsk (_("Use of r%u as a source register is "
12000 "deprecated when r%u is the destination "
12001 "register."), Rm
, Rn
);
12006 /* This is mov.w. */
12007 constraint (Rn
== REG_PC
, BAD_PC
);
12008 constraint (Rm
== REG_PC
, BAD_PC
);
12009 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12010 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12014 reject_bad_reg (Rn
);
12017 if (!inst
.operands
[1].isreg
)
12019 /* Immediate operand. */
12020 if (!in_it_block () && opcode
== T_MNEM_mov
)
12022 if (low_regs
&& narrow
)
12024 inst
.instruction
= THUMB_OP16 (opcode
);
12025 inst
.instruction
|= Rn
<< 8;
12026 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12027 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12029 if (inst
.size_req
== 2)
12030 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12032 inst
.relax
= opcode
;
12037 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12038 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12039 THUMB1_RELOC_ONLY
);
12041 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12042 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12043 inst
.instruction
|= Rn
<< r0off
;
12044 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12047 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12048 && (inst
.instruction
== T_MNEM_mov
12049 || inst
.instruction
== T_MNEM_movs
))
12051 /* Register shifts are encoded as separate shift instructions. */
12052 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12054 if (in_it_block ())
12059 if (inst
.size_req
== 4)
12062 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12068 switch (inst
.operands
[1].shift_kind
)
12071 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12074 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12077 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12080 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12086 inst
.instruction
= opcode
;
12089 inst
.instruction
|= Rn
;
12090 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12095 inst
.instruction
|= CONDS_BIT
;
12097 inst
.instruction
|= Rn
<< 8;
12098 inst
.instruction
|= Rm
<< 16;
12099 inst
.instruction
|= inst
.operands
[1].imm
;
12104 /* Some mov with immediate shift have narrow variants.
12105 Register shifts are handled above. */
12106 if (low_regs
&& inst
.operands
[1].shifted
12107 && (inst
.instruction
== T_MNEM_mov
12108 || inst
.instruction
== T_MNEM_movs
))
12110 if (in_it_block ())
12111 narrow
= (inst
.instruction
== T_MNEM_mov
);
12113 narrow
= (inst
.instruction
== T_MNEM_movs
);
12118 switch (inst
.operands
[1].shift_kind
)
12120 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12121 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12122 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12123 default: narrow
= FALSE
; break;
12129 inst
.instruction
|= Rn
;
12130 inst
.instruction
|= Rm
<< 3;
12131 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12135 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12136 inst
.instruction
|= Rn
<< r0off
;
12137 encode_thumb32_shifted_operand (1);
12141 switch (inst
.instruction
)
12144 /* In v4t or v5t a move of two lowregs produces unpredictable
12145 results. Don't allow this. */
12148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12149 "MOV Rd, Rs with two low registers is not "
12150 "permitted on this architecture");
12151 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12155 inst
.instruction
= T_OPCODE_MOV_HR
;
12156 inst
.instruction
|= (Rn
& 0x8) << 4;
12157 inst
.instruction
|= (Rn
& 0x7);
12158 inst
.instruction
|= Rm
<< 3;
12162 /* We know we have low registers at this point.
12163 Generate LSLS Rd, Rs, #0. */
12164 inst
.instruction
= T_OPCODE_LSL_I
;
12165 inst
.instruction
|= Rn
;
12166 inst
.instruction
|= Rm
<< 3;
12172 inst
.instruction
= T_OPCODE_CMP_LR
;
12173 inst
.instruction
|= Rn
;
12174 inst
.instruction
|= Rm
<< 3;
12178 inst
.instruction
= T_OPCODE_CMP_HR
;
12179 inst
.instruction
|= (Rn
& 0x8) << 4;
12180 inst
.instruction
|= (Rn
& 0x7);
12181 inst
.instruction
|= Rm
<< 3;
12188 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12190 /* PR 10443: Do not silently ignore shifted operands. */
12191 constraint (inst
.operands
[1].shifted
,
12192 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12194 if (inst
.operands
[1].isreg
)
12196 if (Rn
< 8 && Rm
< 8)
12198 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12199 since a MOV instruction produces unpredictable results. */
12200 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12201 inst
.instruction
= T_OPCODE_ADD_I3
;
12203 inst
.instruction
= T_OPCODE_CMP_LR
;
12205 inst
.instruction
|= Rn
;
12206 inst
.instruction
|= Rm
<< 3;
12210 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12211 inst
.instruction
= T_OPCODE_MOV_HR
;
12213 inst
.instruction
= T_OPCODE_CMP_HR
;
12219 constraint (Rn
> 7,
12220 _("only lo regs allowed with immediate"));
12221 inst
.instruction
|= Rn
<< 8;
12222 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12233 top
= (inst
.instruction
& 0x00800000) != 0;
12234 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12236 constraint (top
, _(":lower16: not allowed in this instruction"));
12237 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12239 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12241 constraint (!top
, _(":upper16: not allowed in this instruction"));
12242 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12245 Rd
= inst
.operands
[0].reg
;
12246 reject_bad_reg (Rd
);
12248 inst
.instruction
|= Rd
<< 8;
12249 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12251 imm
= inst
.reloc
.exp
.X_add_number
;
12252 inst
.instruction
|= (imm
& 0xf000) << 4;
12253 inst
.instruction
|= (imm
& 0x0800) << 15;
12254 inst
.instruction
|= (imm
& 0x0700) << 4;
12255 inst
.instruction
|= (imm
& 0x00ff);
12260 do_t_mvn_tst (void)
12264 Rn
= inst
.operands
[0].reg
;
12265 Rm
= inst
.operands
[1].reg
;
12267 if (inst
.instruction
== T_MNEM_cmp
12268 || inst
.instruction
== T_MNEM_cmn
)
12269 constraint (Rn
== REG_PC
, BAD_PC
);
12271 reject_bad_reg (Rn
);
12272 reject_bad_reg (Rm
);
12274 if (unified_syntax
)
12276 int r0off
= (inst
.instruction
== T_MNEM_mvn
12277 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12278 bfd_boolean narrow
;
12280 if (inst
.size_req
== 4
12281 || inst
.instruction
> 0xffff
12282 || inst
.operands
[1].shifted
12283 || Rn
> 7 || Rm
> 7)
12285 else if (inst
.instruction
== T_MNEM_cmn
12286 || inst
.instruction
== T_MNEM_tst
)
12288 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12289 narrow
= !in_it_block ();
12291 narrow
= in_it_block ();
12293 if (!inst
.operands
[1].isreg
)
12295 /* For an immediate, we always generate a 32-bit opcode;
12296 section relaxation will shrink it later if possible. */
12297 if (inst
.instruction
< 0xffff)
12298 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12299 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12300 inst
.instruction
|= Rn
<< r0off
;
12301 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12305 /* See if we can do this with a 16-bit instruction. */
12308 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12309 inst
.instruction
|= Rn
;
12310 inst
.instruction
|= Rm
<< 3;
12314 constraint (inst
.operands
[1].shifted
12315 && inst
.operands
[1].immisreg
,
12316 _("shift must be constant"));
12317 if (inst
.instruction
< 0xffff)
12318 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12319 inst
.instruction
|= Rn
<< r0off
;
12320 encode_thumb32_shifted_operand (1);
12326 constraint (inst
.instruction
> 0xffff
12327 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12328 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12329 _("unshifted register required"));
12330 constraint (Rn
> 7 || Rm
> 7,
12333 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12334 inst
.instruction
|= Rn
;
12335 inst
.instruction
|= Rm
<< 3;
12344 if (do_vfp_nsyn_mrs () == SUCCESS
)
12347 Rd
= inst
.operands
[0].reg
;
12348 reject_bad_reg (Rd
);
12349 inst
.instruction
|= Rd
<< 8;
12351 if (inst
.operands
[1].isreg
)
12353 unsigned br
= inst
.operands
[1].reg
;
12354 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12355 as_bad (_("bad register for mrs"));
12357 inst
.instruction
|= br
& (0xf << 16);
12358 inst
.instruction
|= (br
& 0x300) >> 4;
12359 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12363 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12365 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12367 /* PR gas/12698: The constraint is only applied for m_profile.
12368 If the user has specified -march=all, we want to ignore it as
12369 we are building for any CPU type, including non-m variants. */
12370 bfd_boolean m_profile
=
12371 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12372 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12373 "not support requested special purpose register"));
12376 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12378 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12379 _("'APSR', 'CPSR' or 'SPSR' expected"));
12381 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12382 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12383 inst
.instruction
|= 0xf0000;
12393 if (do_vfp_nsyn_msr () == SUCCESS
)
12396 constraint (!inst
.operands
[1].isreg
,
12397 _("Thumb encoding does not support an immediate here"));
12399 if (inst
.operands
[0].isreg
)
12400 flags
= (int)(inst
.operands
[0].reg
);
12402 flags
= inst
.operands
[0].imm
;
12404 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12406 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12408 /* PR gas/12698: The constraint is only applied for m_profile.
12409 If the user has specified -march=all, we want to ignore it as
12410 we are building for any CPU type, including non-m variants. */
12411 bfd_boolean m_profile
=
12412 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12413 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12414 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12415 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12416 && bits
!= PSR_f
)) && m_profile
,
12417 _("selected processor does not support requested special "
12418 "purpose register"));
12421 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12422 "requested special purpose register"));
12424 Rn
= inst
.operands
[1].reg
;
12425 reject_bad_reg (Rn
);
12427 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12428 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12429 inst
.instruction
|= (flags
& 0x300) >> 4;
12430 inst
.instruction
|= (flags
& 0xff);
12431 inst
.instruction
|= Rn
<< 16;
12437 bfd_boolean narrow
;
12438 unsigned Rd
, Rn
, Rm
;
12440 if (!inst
.operands
[2].present
)
12441 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12443 Rd
= inst
.operands
[0].reg
;
12444 Rn
= inst
.operands
[1].reg
;
12445 Rm
= inst
.operands
[2].reg
;
12447 if (unified_syntax
)
12449 if (inst
.size_req
== 4
12455 else if (inst
.instruction
== T_MNEM_muls
)
12456 narrow
= !in_it_block ();
12458 narrow
= in_it_block ();
12462 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12463 constraint (Rn
> 7 || Rm
> 7,
12470 /* 16-bit MULS/Conditional MUL. */
12471 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12472 inst
.instruction
|= Rd
;
12475 inst
.instruction
|= Rm
<< 3;
12477 inst
.instruction
|= Rn
<< 3;
12479 constraint (1, _("dest must overlap one source register"));
12483 constraint (inst
.instruction
!= T_MNEM_mul
,
12484 _("Thumb-2 MUL must not set flags"));
12486 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12487 inst
.instruction
|= Rd
<< 8;
12488 inst
.instruction
|= Rn
<< 16;
12489 inst
.instruction
|= Rm
<< 0;
12491 reject_bad_reg (Rd
);
12492 reject_bad_reg (Rn
);
12493 reject_bad_reg (Rm
);
12500 unsigned RdLo
, RdHi
, Rn
, Rm
;
12502 RdLo
= inst
.operands
[0].reg
;
12503 RdHi
= inst
.operands
[1].reg
;
12504 Rn
= inst
.operands
[2].reg
;
12505 Rm
= inst
.operands
[3].reg
;
12507 reject_bad_reg (RdLo
);
12508 reject_bad_reg (RdHi
);
12509 reject_bad_reg (Rn
);
12510 reject_bad_reg (Rm
);
12512 inst
.instruction
|= RdLo
<< 12;
12513 inst
.instruction
|= RdHi
<< 8;
12514 inst
.instruction
|= Rn
<< 16;
12515 inst
.instruction
|= Rm
;
12518 as_tsktsk (_("rdhi and rdlo must be different"));
12524 set_it_insn_type (NEUTRAL_IT_INSN
);
12526 if (unified_syntax
)
12528 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12530 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12531 inst
.instruction
|= inst
.operands
[0].imm
;
12535 /* PR9722: Check for Thumb2 availability before
12536 generating a thumb2 nop instruction. */
12537 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12540 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12543 inst
.instruction
= 0x46c0;
12548 constraint (inst
.operands
[0].present
,
12549 _("Thumb does not support NOP with hints"));
12550 inst
.instruction
= 0x46c0;
12557 if (unified_syntax
)
12559 bfd_boolean narrow
;
12561 if (THUMB_SETS_FLAGS (inst
.instruction
))
12562 narrow
= !in_it_block ();
12564 narrow
= in_it_block ();
12565 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12567 if (inst
.size_req
== 4)
12572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12574 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12578 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12579 inst
.instruction
|= inst
.operands
[0].reg
;
12580 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12585 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12587 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12589 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12590 inst
.instruction
|= inst
.operands
[0].reg
;
12591 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12600 Rd
= inst
.operands
[0].reg
;
12601 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12603 reject_bad_reg (Rd
);
12604 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12605 reject_bad_reg (Rn
);
12607 inst
.instruction
|= Rd
<< 8;
12608 inst
.instruction
|= Rn
<< 16;
12610 if (!inst
.operands
[2].isreg
)
12612 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12613 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12619 Rm
= inst
.operands
[2].reg
;
12620 reject_bad_reg (Rm
);
12622 constraint (inst
.operands
[2].shifted
12623 && inst
.operands
[2].immisreg
,
12624 _("shift must be constant"));
12625 encode_thumb32_shifted_operand (2);
12632 unsigned Rd
, Rn
, Rm
;
12634 Rd
= inst
.operands
[0].reg
;
12635 Rn
= inst
.operands
[1].reg
;
12636 Rm
= inst
.operands
[2].reg
;
12638 reject_bad_reg (Rd
);
12639 reject_bad_reg (Rn
);
12640 reject_bad_reg (Rm
);
12642 inst
.instruction
|= Rd
<< 8;
12643 inst
.instruction
|= Rn
<< 16;
12644 inst
.instruction
|= Rm
;
12645 if (inst
.operands
[3].present
)
12647 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12648 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12649 _("expression too complex"));
12650 inst
.instruction
|= (val
& 0x1c) << 10;
12651 inst
.instruction
|= (val
& 0x03) << 6;
12658 if (!inst
.operands
[3].present
)
12662 inst
.instruction
&= ~0x00000020;
12664 /* PR 10168. Swap the Rm and Rn registers. */
12665 Rtmp
= inst
.operands
[1].reg
;
12666 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12667 inst
.operands
[2].reg
= Rtmp
;
12675 if (inst
.operands
[0].immisreg
)
12676 reject_bad_reg (inst
.operands
[0].imm
);
12678 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12682 do_t_push_pop (void)
12686 constraint (inst
.operands
[0].writeback
,
12687 _("push/pop do not support {reglist}^"));
12688 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12689 _("expression too complex"));
12691 mask
= inst
.operands
[0].imm
;
12692 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12693 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12694 else if (inst
.size_req
!= 4
12695 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12696 ? REG_LR
: REG_PC
)))
12698 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12699 inst
.instruction
|= THUMB_PP_PC_LR
;
12700 inst
.instruction
|= mask
& 0xff;
12702 else if (unified_syntax
)
12704 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12705 encode_thumb2_ldmstm (13, mask
, TRUE
);
12709 inst
.error
= _("invalid register list to push/pop instruction");
12719 Rd
= inst
.operands
[0].reg
;
12720 Rm
= inst
.operands
[1].reg
;
12722 reject_bad_reg (Rd
);
12723 reject_bad_reg (Rm
);
12725 inst
.instruction
|= Rd
<< 8;
12726 inst
.instruction
|= Rm
<< 16;
12727 inst
.instruction
|= Rm
;
12735 Rd
= inst
.operands
[0].reg
;
12736 Rm
= inst
.operands
[1].reg
;
12738 reject_bad_reg (Rd
);
12739 reject_bad_reg (Rm
);
12741 if (Rd
<= 7 && Rm
<= 7
12742 && inst
.size_req
!= 4)
12744 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12745 inst
.instruction
|= Rd
;
12746 inst
.instruction
|= Rm
<< 3;
12748 else if (unified_syntax
)
12750 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12751 inst
.instruction
|= Rd
<< 8;
12752 inst
.instruction
|= Rm
<< 16;
12753 inst
.instruction
|= Rm
;
12756 inst
.error
= BAD_HIREG
;
12764 Rd
= inst
.operands
[0].reg
;
12765 Rm
= inst
.operands
[1].reg
;
12767 reject_bad_reg (Rd
);
12768 reject_bad_reg (Rm
);
12770 inst
.instruction
|= Rd
<< 8;
12771 inst
.instruction
|= Rm
;
12779 Rd
= inst
.operands
[0].reg
;
12780 Rs
= (inst
.operands
[1].present
12781 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12782 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12784 reject_bad_reg (Rd
);
12785 reject_bad_reg (Rs
);
12786 if (inst
.operands
[2].isreg
)
12787 reject_bad_reg (inst
.operands
[2].reg
);
12789 inst
.instruction
|= Rd
<< 8;
12790 inst
.instruction
|= Rs
<< 16;
12791 if (!inst
.operands
[2].isreg
)
12793 bfd_boolean narrow
;
12795 if ((inst
.instruction
& 0x00100000) != 0)
12796 narrow
= !in_it_block ();
12798 narrow
= in_it_block ();
12800 if (Rd
> 7 || Rs
> 7)
12803 if (inst
.size_req
== 4 || !unified_syntax
)
12806 if (inst
.reloc
.exp
.X_op
!= O_constant
12807 || inst
.reloc
.exp
.X_add_number
!= 0)
12810 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12811 relaxation, but it doesn't seem worth the hassle. */
12814 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12815 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12816 inst
.instruction
|= Rs
<< 3;
12817 inst
.instruction
|= Rd
;
12821 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12822 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12826 encode_thumb32_shifted_operand (2);
12832 if (warn_on_deprecated
12833 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12834 as_tsktsk (_("setend use is deprecated for ARMv8"));
12836 set_it_insn_type (OUTSIDE_IT_INSN
);
12837 if (inst
.operands
[0].imm
)
12838 inst
.instruction
|= 0x8;
12844 if (!inst
.operands
[1].present
)
12845 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12847 if (unified_syntax
)
12849 bfd_boolean narrow
;
12852 switch (inst
.instruction
)
12855 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12857 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12859 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12861 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12865 if (THUMB_SETS_FLAGS (inst
.instruction
))
12866 narrow
= !in_it_block ();
12868 narrow
= in_it_block ();
12869 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12871 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12873 if (inst
.operands
[2].isreg
12874 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12875 || inst
.operands
[2].reg
> 7))
12877 if (inst
.size_req
== 4)
12880 reject_bad_reg (inst
.operands
[0].reg
);
12881 reject_bad_reg (inst
.operands
[1].reg
);
12885 if (inst
.operands
[2].isreg
)
12887 reject_bad_reg (inst
.operands
[2].reg
);
12888 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12889 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12890 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12891 inst
.instruction
|= inst
.operands
[2].reg
;
12893 /* PR 12854: Error on extraneous shifts. */
12894 constraint (inst
.operands
[2].shifted
,
12895 _("extraneous shift as part of operand to shift insn"));
12899 inst
.operands
[1].shifted
= 1;
12900 inst
.operands
[1].shift_kind
= shift_kind
;
12901 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12902 ? T_MNEM_movs
: T_MNEM_mov
);
12903 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12904 encode_thumb32_shifted_operand (1);
12905 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12906 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12911 if (inst
.operands
[2].isreg
)
12913 switch (shift_kind
)
12915 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12916 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12917 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12918 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12922 inst
.instruction
|= inst
.operands
[0].reg
;
12923 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12925 /* PR 12854: Error on extraneous shifts. */
12926 constraint (inst
.operands
[2].shifted
,
12927 _("extraneous shift as part of operand to shift insn"));
12931 switch (shift_kind
)
12933 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12934 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12935 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12938 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12939 inst
.instruction
|= inst
.operands
[0].reg
;
12940 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12946 constraint (inst
.operands
[0].reg
> 7
12947 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12948 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12950 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12952 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12953 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12954 _("source1 and dest must be same register"));
12956 switch (inst
.instruction
)
12958 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12959 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12960 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12961 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12965 inst
.instruction
|= inst
.operands
[0].reg
;
12966 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12968 /* PR 12854: Error on extraneous shifts. */
12969 constraint (inst
.operands
[2].shifted
,
12970 _("extraneous shift as part of operand to shift insn"));
12974 switch (inst
.instruction
)
12976 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12977 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12978 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12979 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12982 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12983 inst
.instruction
|= inst
.operands
[0].reg
;
12984 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12992 unsigned Rd
, Rn
, Rm
;
12994 Rd
= inst
.operands
[0].reg
;
12995 Rn
= inst
.operands
[1].reg
;
12996 Rm
= inst
.operands
[2].reg
;
12998 reject_bad_reg (Rd
);
12999 reject_bad_reg (Rn
);
13000 reject_bad_reg (Rm
);
13002 inst
.instruction
|= Rd
<< 8;
13003 inst
.instruction
|= Rn
<< 16;
13004 inst
.instruction
|= Rm
;
13010 unsigned Rd
, Rn
, Rm
;
13012 Rd
= inst
.operands
[0].reg
;
13013 Rm
= inst
.operands
[1].reg
;
13014 Rn
= inst
.operands
[2].reg
;
13016 reject_bad_reg (Rd
);
13017 reject_bad_reg (Rn
);
13018 reject_bad_reg (Rm
);
13020 inst
.instruction
|= Rd
<< 8;
13021 inst
.instruction
|= Rn
<< 16;
13022 inst
.instruction
|= Rm
;
13028 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13030 _("SMC is not permitted on this architecture"));
13031 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13032 _("expression too complex"));
13033 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13034 inst
.instruction
|= (value
& 0xf000) >> 12;
13035 inst
.instruction
|= (value
& 0x0ff0);
13036 inst
.instruction
|= (value
& 0x000f) << 16;
13037 /* PR gas/15623: SMC instructions must be last in an IT block. */
13038 set_it_insn_type_last ();
13044 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13046 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13047 inst
.instruction
|= (value
& 0x0fff);
13048 inst
.instruction
|= (value
& 0xf000) << 4;
13052 do_t_ssat_usat (int bias
)
13056 Rd
= inst
.operands
[0].reg
;
13057 Rn
= inst
.operands
[2].reg
;
13059 reject_bad_reg (Rd
);
13060 reject_bad_reg (Rn
);
13062 inst
.instruction
|= Rd
<< 8;
13063 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13064 inst
.instruction
|= Rn
<< 16;
13066 if (inst
.operands
[3].present
)
13068 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13070 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13072 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13073 _("expression too complex"));
13075 if (shift_amount
!= 0)
13077 constraint (shift_amount
> 31,
13078 _("shift expression is too large"));
13080 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13081 inst
.instruction
|= 0x00200000; /* sh bit. */
13083 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13084 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13092 do_t_ssat_usat (1);
13100 Rd
= inst
.operands
[0].reg
;
13101 Rn
= inst
.operands
[2].reg
;
13103 reject_bad_reg (Rd
);
13104 reject_bad_reg (Rn
);
13106 inst
.instruction
|= Rd
<< 8;
13107 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13108 inst
.instruction
|= Rn
<< 16;
13114 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13115 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13116 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13117 || inst
.operands
[2].negative
,
13120 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13122 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13123 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13124 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13125 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13131 if (!inst
.operands
[2].present
)
13132 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13134 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13135 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13136 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13139 inst
.instruction
|= inst
.operands
[0].reg
;
13140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13141 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13142 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13148 unsigned Rd
, Rn
, Rm
;
13150 Rd
= inst
.operands
[0].reg
;
13151 Rn
= inst
.operands
[1].reg
;
13152 Rm
= inst
.operands
[2].reg
;
13154 reject_bad_reg (Rd
);
13155 reject_bad_reg (Rn
);
13156 reject_bad_reg (Rm
);
13158 inst
.instruction
|= Rd
<< 8;
13159 inst
.instruction
|= Rn
<< 16;
13160 inst
.instruction
|= Rm
;
13161 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13169 Rd
= inst
.operands
[0].reg
;
13170 Rm
= inst
.operands
[1].reg
;
13172 reject_bad_reg (Rd
);
13173 reject_bad_reg (Rm
);
13175 if (inst
.instruction
<= 0xffff
13176 && inst
.size_req
!= 4
13177 && Rd
<= 7 && Rm
<= 7
13178 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13180 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13181 inst
.instruction
|= Rd
;
13182 inst
.instruction
|= Rm
<< 3;
13184 else if (unified_syntax
)
13186 if (inst
.instruction
<= 0xffff)
13187 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13188 inst
.instruction
|= Rd
<< 8;
13189 inst
.instruction
|= Rm
;
13190 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13194 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13195 _("Thumb encoding does not support rotation"));
13196 constraint (1, BAD_HIREG
);
13203 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13212 half
= (inst
.instruction
& 0x10) != 0;
13213 set_it_insn_type_last ();
13214 constraint (inst
.operands
[0].immisreg
,
13215 _("instruction requires register index"));
13217 Rn
= inst
.operands
[0].reg
;
13218 Rm
= inst
.operands
[0].imm
;
13220 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13221 constraint (Rn
== REG_SP
, BAD_SP
);
13222 reject_bad_reg (Rm
);
13224 constraint (!half
&& inst
.operands
[0].shifted
,
13225 _("instruction does not allow shifted index"));
13226 inst
.instruction
|= (Rn
<< 16) | Rm
;
13232 if (!inst
.operands
[0].present
)
13233 inst
.operands
[0].imm
= 0;
13235 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13237 constraint (inst
.size_req
== 2,
13238 _("immediate value out of range"));
13239 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13240 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13241 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13245 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13246 inst
.instruction
|= inst
.operands
[0].imm
;
13249 set_it_insn_type (NEUTRAL_IT_INSN
);
13256 do_t_ssat_usat (0);
13264 Rd
= inst
.operands
[0].reg
;
13265 Rn
= inst
.operands
[2].reg
;
13267 reject_bad_reg (Rd
);
13268 reject_bad_reg (Rn
);
13270 inst
.instruction
|= Rd
<< 8;
13271 inst
.instruction
|= inst
.operands
[1].imm
;
13272 inst
.instruction
|= Rn
<< 16;
13275 /* Neon instruction encoder helpers. */
13277 /* Encodings for the different types for various Neon opcodes. */
13279 /* An "invalid" code for the following tables. */
13282 struct neon_tab_entry
13285 unsigned float_or_poly
;
13286 unsigned scalar_or_imm
;
13289 /* Map overloaded Neon opcodes to their respective encodings. */
13290 #define NEON_ENC_TAB \
13291 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13292 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13293 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13294 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13295 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13296 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13297 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13298 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13299 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13300 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13301 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13302 /* Register variants of the following two instructions are encoded as
13303 vcge / vcgt with the operands reversed. */ \
13304 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13305 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13306 X(vfma, N_INV, 0x0000c10, N_INV), \
13307 X(vfms, N_INV, 0x0200c10, N_INV), \
13308 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13309 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13310 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13311 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13312 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13313 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13314 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13315 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13316 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13317 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13318 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13319 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13320 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13321 X(vshl, 0x0000400, N_INV, 0x0800510), \
13322 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13323 X(vand, 0x0000110, N_INV, 0x0800030), \
13324 X(vbic, 0x0100110, N_INV, 0x0800030), \
13325 X(veor, 0x1000110, N_INV, N_INV), \
13326 X(vorn, 0x0300110, N_INV, 0x0800010), \
13327 X(vorr, 0x0200110, N_INV, 0x0800010), \
13328 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13329 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13330 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13331 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13332 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13333 X(vst1, 0x0000000, 0x0800000, N_INV), \
13334 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13335 X(vst2, 0x0000100, 0x0800100, N_INV), \
13336 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13337 X(vst3, 0x0000200, 0x0800200, N_INV), \
13338 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13339 X(vst4, 0x0000300, 0x0800300, N_INV), \
13340 X(vmovn, 0x1b20200, N_INV, N_INV), \
13341 X(vtrn, 0x1b20080, N_INV, N_INV), \
13342 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13343 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13344 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13345 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13346 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13347 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13348 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13349 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13350 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13351 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13352 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13353 X(vseleq, 0xe000a00, N_INV, N_INV), \
13354 X(vselvs, 0xe100a00, N_INV, N_INV), \
13355 X(vselge, 0xe200a00, N_INV, N_INV), \
13356 X(vselgt, 0xe300a00, N_INV, N_INV), \
13357 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13358 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13359 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13360 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13361 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13362 X(aes, 0x3b00300, N_INV, N_INV), \
13363 X(sha3op, 0x2000c00, N_INV, N_INV), \
13364 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13365 X(sha2op, 0x3ba0380, N_INV, N_INV)
13369 #define X(OPC,I,F,S) N_MNEM_##OPC
13374 static const struct neon_tab_entry neon_enc_tab
[] =
13376 #define X(OPC,I,F,S) { (I), (F), (S) }
13381 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13382 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13383 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13384 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13385 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13386 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13387 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13388 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13389 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13390 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13391 #define NEON_ENC_SINGLE_(X) \
13392 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13393 #define NEON_ENC_DOUBLE_(X) \
13394 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13395 #define NEON_ENC_FPV8_(X) \
13396 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13398 #define NEON_ENCODE(type, inst) \
13401 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13402 inst.is_neon = 1; \
13406 #define check_neon_suffixes \
13409 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13411 as_bad (_("invalid neon suffix for non neon instruction")); \
13417 /* Define shapes for instruction operands. The following mnemonic characters
13418 are used in this table:
13420 F - VFP S<n> register
13421 D - Neon D<n> register
13422 Q - Neon Q<n> register
13426 L - D<n> register list
13428 This table is used to generate various data:
13429 - enumerations of the form NS_DDR to be used as arguments to
13431 - a table classifying shapes into single, double, quad, mixed.
13432 - a table used to drive neon_select_shape. */
13434 #define NEON_SHAPE_DEF \
13435 X(3, (D, D, D), DOUBLE), \
13436 X(3, (Q, Q, Q), QUAD), \
13437 X(3, (D, D, I), DOUBLE), \
13438 X(3, (Q, Q, I), QUAD), \
13439 X(3, (D, D, S), DOUBLE), \
13440 X(3, (Q, Q, S), QUAD), \
13441 X(2, (D, D), DOUBLE), \
13442 X(2, (Q, Q), QUAD), \
13443 X(2, (D, S), DOUBLE), \
13444 X(2, (Q, S), QUAD), \
13445 X(2, (D, R), DOUBLE), \
13446 X(2, (Q, R), QUAD), \
13447 X(2, (D, I), DOUBLE), \
13448 X(2, (Q, I), QUAD), \
13449 X(3, (D, L, D), DOUBLE), \
13450 X(2, (D, Q), MIXED), \
13451 X(2, (Q, D), MIXED), \
13452 X(3, (D, Q, I), MIXED), \
13453 X(3, (Q, D, I), MIXED), \
13454 X(3, (Q, D, D), MIXED), \
13455 X(3, (D, Q, Q), MIXED), \
13456 X(3, (Q, Q, D), MIXED), \
13457 X(3, (Q, D, S), MIXED), \
13458 X(3, (D, Q, S), MIXED), \
13459 X(4, (D, D, D, I), DOUBLE), \
13460 X(4, (Q, Q, Q, I), QUAD), \
13461 X(4, (D, D, S, I), DOUBLE), \
13462 X(4, (Q, Q, S, I), QUAD), \
13463 X(2, (F, F), SINGLE), \
13464 X(3, (F, F, F), SINGLE), \
13465 X(2, (F, I), SINGLE), \
13466 X(2, (F, D), MIXED), \
13467 X(2, (D, F), MIXED), \
13468 X(3, (F, F, I), MIXED), \
13469 X(4, (R, R, F, F), SINGLE), \
13470 X(4, (F, F, R, R), SINGLE), \
13471 X(3, (D, R, R), DOUBLE), \
13472 X(3, (R, R, D), DOUBLE), \
13473 X(2, (S, R), SINGLE), \
13474 X(2, (R, S), SINGLE), \
13475 X(2, (F, R), SINGLE), \
13476 X(2, (R, F), SINGLE), \
13477 /* Half float shape supported so far. */\
13478 X (2, (H, D), MIXED), \
13479 X (2, (D, H), MIXED), \
13480 X (2, (H, F), MIXED), \
13481 X (2, (F, H), MIXED), \
13482 X (2, (H, H), HALF), \
13483 X (2, (H, R), HALF), \
13484 X (2, (R, H), HALF), \
13485 X (2, (H, I), HALF), \
13486 X (3, (H, H, H), HALF), \
13487 X (3, (H, F, I), MIXED), \
13488 X (3, (F, H, I), MIXED), \
13489 X (3, (D, H, H), MIXED), \
13490 X (3, (D, H, S), MIXED)
13492 #define S2(A,B) NS_##A##B
13493 #define S3(A,B,C) NS_##A##B##C
13494 #define S4(A,B,C,D) NS_##A##B##C##D
13496 #define X(N, L, C) S##N L
13509 enum neon_shape_class
13518 #define X(N, L, C) SC_##C
13520 static enum neon_shape_class neon_shape_class
[] =
13539 /* Register widths of above. */
13540 static unsigned neon_shape_el_size
[] =
13552 struct neon_shape_info
13555 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13558 #define S2(A,B) { SE_##A, SE_##B }
13559 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13560 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13562 #define X(N, L, C) { N, S##N L }
13564 static struct neon_shape_info neon_shape_tab
[] =
13574 /* Bit masks used in type checking given instructions.
13575 'N_EQK' means the type must be the same as (or based on in some way) the key
13576 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13577 set, various other bits can be set as well in order to modify the meaning of
13578 the type constraint. */
13580 enum neon_type_mask
13604 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13605 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13606 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13607 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13608 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13609 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13610 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13611 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13612 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13613 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13614 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13616 N_MAX_NONSPECIAL
= N_P64
13619 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13621 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13622 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13623 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13624 #define N_S_32 (N_S8 | N_S16 | N_S32)
13625 #define N_F_16_32 (N_F16 | N_F32)
13626 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13627 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13628 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13629 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13631 /* Pass this as the first type argument to neon_check_type to ignore types
13633 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13635 /* Select a "shape" for the current instruction (describing register types or
13636 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13637 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13638 function of operand parsing, so this function doesn't need to be called.
13639 Shapes should be listed in order of decreasing length. */
13641 static enum neon_shape
13642 neon_select_shape (enum neon_shape shape
, ...)
13645 enum neon_shape first_shape
= shape
;
13647 /* Fix missing optional operands. FIXME: we don't know at this point how
13648 many arguments we should have, so this makes the assumption that we have
13649 > 1. This is true of all current Neon opcodes, I think, but may not be
13650 true in the future. */
13651 if (!inst
.operands
[1].present
)
13652 inst
.operands
[1] = inst
.operands
[0];
13654 va_start (ap
, shape
);
13656 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13661 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13663 if (!inst
.operands
[j
].present
)
13669 switch (neon_shape_tab
[shape
].el
[j
])
13671 /* If a .f16, .16, .u16, .s16 type specifier is given over
13672 a VFP single precision register operand, it's essentially
13673 means only half of the register is used.
13675 If the type specifier is given after the mnemonics, the
13676 information is stored in inst.vectype. If the type specifier
13677 is given after register operand, the information is stored
13678 in inst.operands[].vectype.
13680 When there is only one type specifier, and all the register
13681 operands are the same type of hardware register, the type
13682 specifier applies to all register operands.
13684 If no type specifier is given, the shape is inferred from
13685 operand information.
13688 vadd.f16 s0, s1, s2: NS_HHH
13689 vabs.f16 s0, s1: NS_HH
13690 vmov.f16 s0, r1: NS_HR
13691 vmov.f16 r0, s1: NS_RH
13692 vcvt.f16 r0, s1: NS_RH
13693 vcvt.f16.s32 s2, s2, #29: NS_HFI
13694 vcvt.f16.s32 s2, s2: NS_HF
13697 if (!(inst
.operands
[j
].isreg
13698 && inst
.operands
[j
].isvec
13699 && inst
.operands
[j
].issingle
13700 && !inst
.operands
[j
].isquad
13701 && ((inst
.vectype
.elems
== 1
13702 && inst
.vectype
.el
[0].size
== 16)
13703 || (inst
.vectype
.elems
> 1
13704 && inst
.vectype
.el
[j
].size
== 16)
13705 || (inst
.vectype
.elems
== 0
13706 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13707 && inst
.operands
[j
].vectype
.size
== 16))))
13712 if (!(inst
.operands
[j
].isreg
13713 && inst
.operands
[j
].isvec
13714 && inst
.operands
[j
].issingle
13715 && !inst
.operands
[j
].isquad
13716 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13717 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13718 || (inst
.vectype
.elems
== 0
13719 && (inst
.operands
[j
].vectype
.size
== 32
13720 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13725 if (!(inst
.operands
[j
].isreg
13726 && inst
.operands
[j
].isvec
13727 && !inst
.operands
[j
].isquad
13728 && !inst
.operands
[j
].issingle
))
13733 if (!(inst
.operands
[j
].isreg
13734 && !inst
.operands
[j
].isvec
))
13739 if (!(inst
.operands
[j
].isreg
13740 && inst
.operands
[j
].isvec
13741 && inst
.operands
[j
].isquad
13742 && !inst
.operands
[j
].issingle
))
13747 if (!(!inst
.operands
[j
].isreg
13748 && !inst
.operands
[j
].isscalar
))
13753 if (!(!inst
.operands
[j
].isreg
13754 && inst
.operands
[j
].isscalar
))
13764 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13765 /* We've matched all the entries in the shape table, and we don't
13766 have any left over operands which have not been matched. */
13772 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13773 first_error (_("invalid instruction shape"));
13778 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13779 means the Q bit should be set). */
13782 neon_quad (enum neon_shape shape
)
13784 return neon_shape_class
[shape
] == SC_QUAD
;
13788 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13791 /* Allow modification to be made to types which are constrained to be
13792 based on the key element, based on bits set alongside N_EQK. */
13793 if ((typebits
& N_EQK
) != 0)
13795 if ((typebits
& N_HLF
) != 0)
13797 else if ((typebits
& N_DBL
) != 0)
13799 if ((typebits
& N_SGN
) != 0)
13800 *g_type
= NT_signed
;
13801 else if ((typebits
& N_UNS
) != 0)
13802 *g_type
= NT_unsigned
;
13803 else if ((typebits
& N_INT
) != 0)
13804 *g_type
= NT_integer
;
13805 else if ((typebits
& N_FLT
) != 0)
13806 *g_type
= NT_float
;
13807 else if ((typebits
& N_SIZ
) != 0)
13808 *g_type
= NT_untyped
;
13812 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13813 operand type, i.e. the single type specified in a Neon instruction when it
13814 is the only one given. */
13816 static struct neon_type_el
13817 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13819 struct neon_type_el dest
= *key
;
13821 gas_assert ((thisarg
& N_EQK
) != 0);
13823 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13828 /* Convert Neon type and size into compact bitmask representation. */
13830 static enum neon_type_mask
13831 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13838 case 8: return N_8
;
13839 case 16: return N_16
;
13840 case 32: return N_32
;
13841 case 64: return N_64
;
13849 case 8: return N_I8
;
13850 case 16: return N_I16
;
13851 case 32: return N_I32
;
13852 case 64: return N_I64
;
13860 case 16: return N_F16
;
13861 case 32: return N_F32
;
13862 case 64: return N_F64
;
13870 case 8: return N_P8
;
13871 case 16: return N_P16
;
13872 case 64: return N_P64
;
13880 case 8: return N_S8
;
13881 case 16: return N_S16
;
13882 case 32: return N_S32
;
13883 case 64: return N_S64
;
13891 case 8: return N_U8
;
13892 case 16: return N_U16
;
13893 case 32: return N_U32
;
13894 case 64: return N_U64
;
13905 /* Convert compact Neon bitmask type representation to a type and size. Only
13906 handles the case where a single bit is set in the mask. */
13909 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13910 enum neon_type_mask mask
)
13912 if ((mask
& N_EQK
) != 0)
13915 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13917 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13919 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13921 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13926 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13928 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13929 *type
= NT_unsigned
;
13930 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13931 *type
= NT_integer
;
13932 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13933 *type
= NT_untyped
;
13934 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13936 else if ((mask
& (N_F_ALL
)) != 0)
13944 /* Modify a bitmask of allowed types. This is only needed for type
13948 modify_types_allowed (unsigned allowed
, unsigned mods
)
13951 enum neon_el_type type
;
13957 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13959 if (el_type_of_type_chk (&type
, &size
,
13960 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13962 neon_modify_type_size (mods
, &type
, &size
);
13963 destmask
|= type_chk_of_el_type (type
, size
);
13970 /* Check type and return type classification.
13971 The manual states (paraphrase): If one datatype is given, it indicates the
13973 - the second operand, if there is one
13974 - the operand, if there is no second operand
13975 - the result, if there are no operands.
13976 This isn't quite good enough though, so we use a concept of a "key" datatype
13977 which is set on a per-instruction basis, which is the one which matters when
13978 only one data type is written.
13979 Note: this function has side-effects (e.g. filling in missing operands). All
13980 Neon instructions should call it before performing bit encoding. */
13982 static struct neon_type_el
13983 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13986 unsigned i
, pass
, key_el
= 0;
13987 unsigned types
[NEON_MAX_TYPE_ELS
];
13988 enum neon_el_type k_type
= NT_invtype
;
13989 unsigned k_size
= -1u;
13990 struct neon_type_el badtype
= {NT_invtype
, -1};
13991 unsigned key_allowed
= 0;
13993 /* Optional registers in Neon instructions are always (not) in operand 1.
13994 Fill in the missing operand here, if it was omitted. */
13995 if (els
> 1 && !inst
.operands
[1].present
)
13996 inst
.operands
[1] = inst
.operands
[0];
13998 /* Suck up all the varargs. */
14000 for (i
= 0; i
< els
; i
++)
14002 unsigned thisarg
= va_arg (ap
, unsigned);
14003 if (thisarg
== N_IGNORE_TYPE
)
14008 types
[i
] = thisarg
;
14009 if ((thisarg
& N_KEY
) != 0)
14014 if (inst
.vectype
.elems
> 0)
14015 for (i
= 0; i
< els
; i
++)
14016 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14018 first_error (_("types specified in both the mnemonic and operands"));
14022 /* Duplicate inst.vectype elements here as necessary.
14023 FIXME: No idea if this is exactly the same as the ARM assembler,
14024 particularly when an insn takes one register and one non-register
14026 if (inst
.vectype
.elems
== 1 && els
> 1)
14029 inst
.vectype
.elems
= els
;
14030 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14031 for (j
= 0; j
< els
; j
++)
14033 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14036 else if (inst
.vectype
.elems
== 0 && els
> 0)
14039 /* No types were given after the mnemonic, so look for types specified
14040 after each operand. We allow some flexibility here; as long as the
14041 "key" operand has a type, we can infer the others. */
14042 for (j
= 0; j
< els
; j
++)
14043 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14044 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14046 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14048 for (j
= 0; j
< els
; j
++)
14049 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14050 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14055 first_error (_("operand types can't be inferred"));
14059 else if (inst
.vectype
.elems
!= els
)
14061 first_error (_("type specifier has the wrong number of parts"));
14065 for (pass
= 0; pass
< 2; pass
++)
14067 for (i
= 0; i
< els
; i
++)
14069 unsigned thisarg
= types
[i
];
14070 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14071 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14072 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14073 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14075 /* Decay more-specific signed & unsigned types to sign-insensitive
14076 integer types if sign-specific variants are unavailable. */
14077 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14078 && (types_allowed
& N_SU_ALL
) == 0)
14079 g_type
= NT_integer
;
14081 /* If only untyped args are allowed, decay any more specific types to
14082 them. Some instructions only care about signs for some element
14083 sizes, so handle that properly. */
14084 if (((types_allowed
& N_UNT
) == 0)
14085 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14086 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14087 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14088 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14089 g_type
= NT_untyped
;
14093 if ((thisarg
& N_KEY
) != 0)
14097 key_allowed
= thisarg
& ~N_KEY
;
14099 /* Check architecture constraint on FP16 extension. */
14101 && k_type
== NT_float
14102 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14104 inst
.error
= _(BAD_FP16
);
14111 if ((thisarg
& N_VFP
) != 0)
14113 enum neon_shape_el regshape
;
14114 unsigned regwidth
, match
;
14116 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14119 first_error (_("invalid instruction shape"));
14122 regshape
= neon_shape_tab
[ns
].el
[i
];
14123 regwidth
= neon_shape_el_size
[regshape
];
14125 /* In VFP mode, operands must match register widths. If we
14126 have a key operand, use its width, else use the width of
14127 the current operand. */
14133 /* FP16 will use a single precision register. */
14134 if (regwidth
== 32 && match
== 16)
14136 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14140 inst
.error
= _(BAD_FP16
);
14145 if (regwidth
!= match
)
14147 first_error (_("operand size must match register width"));
14152 if ((thisarg
& N_EQK
) == 0)
14154 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14156 if ((given_type
& types_allowed
) == 0)
14158 first_error (_("bad type in Neon instruction"));
14164 enum neon_el_type mod_k_type
= k_type
;
14165 unsigned mod_k_size
= k_size
;
14166 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14167 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14169 first_error (_("inconsistent types in Neon instruction"));
14177 return inst
.vectype
.el
[key_el
];
14180 /* Neon-style VFP instruction forwarding. */
14182 /* Thumb VFP instructions have 0xE in the condition field. */
14185 do_vfp_cond_or_thumb (void)
14190 inst
.instruction
|= 0xe0000000;
14192 inst
.instruction
|= inst
.cond
<< 28;
14195 /* Look up and encode a simple mnemonic, for use as a helper function for the
14196 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14197 etc. It is assumed that operand parsing has already been done, and that the
14198 operands are in the form expected by the given opcode (this isn't necessarily
14199 the same as the form in which they were parsed, hence some massaging must
14200 take place before this function is called).
14201 Checks current arch version against that in the looked-up opcode. */
14204 do_vfp_nsyn_opcode (const char *opname
)
14206 const struct asm_opcode
*opcode
;
14208 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14214 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14221 inst
.instruction
= opcode
->tvalue
;
14222 opcode
->tencode ();
14226 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14227 opcode
->aencode ();
14232 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14234 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14236 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14239 do_vfp_nsyn_opcode ("fadds");
14241 do_vfp_nsyn_opcode ("fsubs");
14243 /* ARMv8.2 fp16 instruction. */
14245 do_scalar_fp16_v82_encode ();
14250 do_vfp_nsyn_opcode ("faddd");
14252 do_vfp_nsyn_opcode ("fsubd");
14256 /* Check operand types to see if this is a VFP instruction, and if so call
14260 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14262 enum neon_shape rs
;
14263 struct neon_type_el et
;
14268 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14269 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14273 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14274 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14275 N_F_ALL
| N_KEY
| N_VFP
);
14282 if (et
.type
!= NT_invtype
)
14293 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14295 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14297 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14300 do_vfp_nsyn_opcode ("fmacs");
14302 do_vfp_nsyn_opcode ("fnmacs");
14304 /* ARMv8.2 fp16 instruction. */
14306 do_scalar_fp16_v82_encode ();
14311 do_vfp_nsyn_opcode ("fmacd");
14313 do_vfp_nsyn_opcode ("fnmacd");
14318 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14320 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14322 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14325 do_vfp_nsyn_opcode ("ffmas");
14327 do_vfp_nsyn_opcode ("ffnmas");
14329 /* ARMv8.2 fp16 instruction. */
14331 do_scalar_fp16_v82_encode ();
14336 do_vfp_nsyn_opcode ("ffmad");
14338 do_vfp_nsyn_opcode ("ffnmad");
14343 do_vfp_nsyn_mul (enum neon_shape rs
)
14345 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14347 do_vfp_nsyn_opcode ("fmuls");
14349 /* ARMv8.2 fp16 instruction. */
14351 do_scalar_fp16_v82_encode ();
14354 do_vfp_nsyn_opcode ("fmuld");
14358 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14360 int is_neg
= (inst
.instruction
& 0x80) != 0;
14361 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14363 if (rs
== NS_FF
|| rs
== NS_HH
)
14366 do_vfp_nsyn_opcode ("fnegs");
14368 do_vfp_nsyn_opcode ("fabss");
14370 /* ARMv8.2 fp16 instruction. */
14372 do_scalar_fp16_v82_encode ();
14377 do_vfp_nsyn_opcode ("fnegd");
14379 do_vfp_nsyn_opcode ("fabsd");
14383 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14384 insns belong to Neon, and are handled elsewhere. */
14387 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14389 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14393 do_vfp_nsyn_opcode ("fldmdbs");
14395 do_vfp_nsyn_opcode ("fldmias");
14400 do_vfp_nsyn_opcode ("fstmdbs");
14402 do_vfp_nsyn_opcode ("fstmias");
14407 do_vfp_nsyn_sqrt (void)
14409 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14410 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14412 if (rs
== NS_FF
|| rs
== NS_HH
)
14414 do_vfp_nsyn_opcode ("fsqrts");
14416 /* ARMv8.2 fp16 instruction. */
14418 do_scalar_fp16_v82_encode ();
14421 do_vfp_nsyn_opcode ("fsqrtd");
14425 do_vfp_nsyn_div (void)
14427 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14428 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14429 N_F_ALL
| N_KEY
| N_VFP
);
14431 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14433 do_vfp_nsyn_opcode ("fdivs");
14435 /* ARMv8.2 fp16 instruction. */
14437 do_scalar_fp16_v82_encode ();
14440 do_vfp_nsyn_opcode ("fdivd");
14444 do_vfp_nsyn_nmul (void)
14446 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14447 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14448 N_F_ALL
| N_KEY
| N_VFP
);
14450 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14452 NEON_ENCODE (SINGLE
, inst
);
14453 do_vfp_sp_dyadic ();
14455 /* ARMv8.2 fp16 instruction. */
14457 do_scalar_fp16_v82_encode ();
14461 NEON_ENCODE (DOUBLE
, inst
);
14462 do_vfp_dp_rd_rn_rm ();
14464 do_vfp_cond_or_thumb ();
14469 do_vfp_nsyn_cmp (void)
14471 enum neon_shape rs
;
14472 if (inst
.operands
[1].isreg
)
14474 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14475 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14477 if (rs
== NS_FF
|| rs
== NS_HH
)
14479 NEON_ENCODE (SINGLE
, inst
);
14480 do_vfp_sp_monadic ();
14484 NEON_ENCODE (DOUBLE
, inst
);
14485 do_vfp_dp_rd_rm ();
14490 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14491 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14493 switch (inst
.instruction
& 0x0fffffff)
14496 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14499 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14505 if (rs
== NS_FI
|| rs
== NS_HI
)
14507 NEON_ENCODE (SINGLE
, inst
);
14508 do_vfp_sp_compare_z ();
14512 NEON_ENCODE (DOUBLE
, inst
);
14516 do_vfp_cond_or_thumb ();
14518 /* ARMv8.2 fp16 instruction. */
14519 if (rs
== NS_HI
|| rs
== NS_HH
)
14520 do_scalar_fp16_v82_encode ();
14524 nsyn_insert_sp (void)
14526 inst
.operands
[1] = inst
.operands
[0];
14527 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14528 inst
.operands
[0].reg
= REG_SP
;
14529 inst
.operands
[0].isreg
= 1;
14530 inst
.operands
[0].writeback
= 1;
14531 inst
.operands
[0].present
= 1;
14535 do_vfp_nsyn_push (void)
14539 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14540 _("register list must contain at least 1 and at most 16 "
14543 if (inst
.operands
[1].issingle
)
14544 do_vfp_nsyn_opcode ("fstmdbs");
14546 do_vfp_nsyn_opcode ("fstmdbd");
14550 do_vfp_nsyn_pop (void)
14554 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14555 _("register list must contain at least 1 and at most 16 "
14558 if (inst
.operands
[1].issingle
)
14559 do_vfp_nsyn_opcode ("fldmias");
14561 do_vfp_nsyn_opcode ("fldmiad");
14564 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14565 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14568 neon_dp_fixup (struct arm_it
* insn
)
14570 unsigned int i
= insn
->instruction
;
14575 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14586 insn
->instruction
= i
;
14589 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14593 neon_logbits (unsigned x
)
14595 return ffs (x
) - 4;
14598 #define LOW4(R) ((R) & 0xf)
14599 #define HI1(R) (((R) >> 4) & 1)
14601 /* Encode insns with bit pattern:
14603 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14604 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14606 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14607 different meaning for some instruction. */
14610 neon_three_same (int isquad
, int ubit
, int size
)
14612 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14613 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14614 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14615 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14616 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14617 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14618 inst
.instruction
|= (isquad
!= 0) << 6;
14619 inst
.instruction
|= (ubit
!= 0) << 24;
14621 inst
.instruction
|= neon_logbits (size
) << 20;
14623 neon_dp_fixup (&inst
);
14626 /* Encode instructions of the form:
14628 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14629 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14631 Don't write size if SIZE == -1. */
14634 neon_two_same (int qbit
, int ubit
, int size
)
14636 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14637 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14638 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14639 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14640 inst
.instruction
|= (qbit
!= 0) << 6;
14641 inst
.instruction
|= (ubit
!= 0) << 24;
14644 inst
.instruction
|= neon_logbits (size
) << 18;
14646 neon_dp_fixup (&inst
);
14649 /* Neon instruction encoders, in approximate order of appearance. */
14652 do_neon_dyadic_i_su (void)
14654 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14655 struct neon_type_el et
= neon_check_type (3, rs
,
14656 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14657 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14661 do_neon_dyadic_i64_su (void)
14663 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14664 struct neon_type_el et
= neon_check_type (3, rs
,
14665 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14666 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14670 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14673 unsigned size
= et
.size
>> 3;
14674 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14675 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14676 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14677 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14678 inst
.instruction
|= (isquad
!= 0) << 6;
14679 inst
.instruction
|= immbits
<< 16;
14680 inst
.instruction
|= (size
>> 3) << 7;
14681 inst
.instruction
|= (size
& 0x7) << 19;
14683 inst
.instruction
|= (uval
!= 0) << 24;
14685 neon_dp_fixup (&inst
);
14689 do_neon_shl_imm (void)
14691 if (!inst
.operands
[2].isreg
)
14693 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14694 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14695 int imm
= inst
.operands
[2].imm
;
14697 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14698 _("immediate out of range for shift"));
14699 NEON_ENCODE (IMMED
, inst
);
14700 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14704 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14705 struct neon_type_el et
= neon_check_type (3, rs
,
14706 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14709 /* VSHL/VQSHL 3-register variants have syntax such as:
14711 whereas other 3-register operations encoded by neon_three_same have
14714 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14716 tmp
= inst
.operands
[2].reg
;
14717 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14718 inst
.operands
[1].reg
= tmp
;
14719 NEON_ENCODE (INTEGER
, inst
);
14720 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14725 do_neon_qshl_imm (void)
14727 if (!inst
.operands
[2].isreg
)
14729 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14730 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14731 int imm
= inst
.operands
[2].imm
;
14733 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14734 _("immediate out of range for shift"));
14735 NEON_ENCODE (IMMED
, inst
);
14736 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14740 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14741 struct neon_type_el et
= neon_check_type (3, rs
,
14742 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14745 /* See note in do_neon_shl_imm. */
14746 tmp
= inst
.operands
[2].reg
;
14747 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14748 inst
.operands
[1].reg
= tmp
;
14749 NEON_ENCODE (INTEGER
, inst
);
14750 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14755 do_neon_rshl (void)
14757 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14758 struct neon_type_el et
= neon_check_type (3, rs
,
14759 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14762 tmp
= inst
.operands
[2].reg
;
14763 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14764 inst
.operands
[1].reg
= tmp
;
14765 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14769 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14771 /* Handle .I8 pseudo-instructions. */
14774 /* Unfortunately, this will make everything apart from zero out-of-range.
14775 FIXME is this the intended semantics? There doesn't seem much point in
14776 accepting .I8 if so. */
14777 immediate
|= immediate
<< 8;
14783 if (immediate
== (immediate
& 0x000000ff))
14785 *immbits
= immediate
;
14788 else if (immediate
== (immediate
& 0x0000ff00))
14790 *immbits
= immediate
>> 8;
14793 else if (immediate
== (immediate
& 0x00ff0000))
14795 *immbits
= immediate
>> 16;
14798 else if (immediate
== (immediate
& 0xff000000))
14800 *immbits
= immediate
>> 24;
14803 if ((immediate
& 0xffff) != (immediate
>> 16))
14804 goto bad_immediate
;
14805 immediate
&= 0xffff;
14808 if (immediate
== (immediate
& 0x000000ff))
14810 *immbits
= immediate
;
14813 else if (immediate
== (immediate
& 0x0000ff00))
14815 *immbits
= immediate
>> 8;
14820 first_error (_("immediate value out of range"));
14825 do_neon_logic (void)
14827 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14829 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14830 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14831 /* U bit and size field were set as part of the bitmask. */
14832 NEON_ENCODE (INTEGER
, inst
);
14833 neon_three_same (neon_quad (rs
), 0, -1);
14837 const int three_ops_form
= (inst
.operands
[2].present
14838 && !inst
.operands
[2].isreg
);
14839 const int immoperand
= (three_ops_form
? 2 : 1);
14840 enum neon_shape rs
= (three_ops_form
14841 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14842 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14843 struct neon_type_el et
= neon_check_type (2, rs
,
14844 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14845 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14849 if (et
.type
== NT_invtype
)
14852 if (three_ops_form
)
14853 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14854 _("first and second operands shall be the same register"));
14856 NEON_ENCODE (IMMED
, inst
);
14858 immbits
= inst
.operands
[immoperand
].imm
;
14861 /* .i64 is a pseudo-op, so the immediate must be a repeating
14863 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14864 inst
.operands
[immoperand
].reg
: 0))
14866 /* Set immbits to an invalid constant. */
14867 immbits
= 0xdeadbeef;
14874 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14878 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14882 /* Pseudo-instruction for VBIC. */
14883 neon_invert_size (&immbits
, 0, et
.size
);
14884 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14888 /* Pseudo-instruction for VORR. */
14889 neon_invert_size (&immbits
, 0, et
.size
);
14890 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14900 inst
.instruction
|= neon_quad (rs
) << 6;
14901 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14903 inst
.instruction
|= cmode
<< 8;
14904 neon_write_immbits (immbits
);
14906 neon_dp_fixup (&inst
);
14911 do_neon_bitfield (void)
14913 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14914 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14915 neon_three_same (neon_quad (rs
), 0, -1);
14919 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14922 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14923 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14925 if (et
.type
== NT_float
)
14927 NEON_ENCODE (FLOAT
, inst
);
14928 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14932 NEON_ENCODE (INTEGER
, inst
);
14933 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14938 do_neon_dyadic_if_su (void)
14940 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14944 do_neon_dyadic_if_su_d (void)
14946 /* This version only allow D registers, but that constraint is enforced during
14947 operand parsing so we don't need to do anything extra here. */
14948 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14952 do_neon_dyadic_if_i_d (void)
14954 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14955 affected if we specify unsigned args. */
14956 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14959 enum vfp_or_neon_is_neon_bits
14962 NEON_CHECK_ARCH
= 2,
14963 NEON_CHECK_ARCH8
= 4
14966 /* Call this function if an instruction which may have belonged to the VFP or
14967 Neon instruction sets, but turned out to be a Neon instruction (due to the
14968 operand types involved, etc.). We have to check and/or fix-up a couple of
14971 - Make sure the user hasn't attempted to make a Neon instruction
14973 - Alter the value in the condition code field if necessary.
14974 - Make sure that the arch supports Neon instructions.
14976 Which of these operations take place depends on bits from enum
14977 vfp_or_neon_is_neon_bits.
14979 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14980 current instruction's condition is COND_ALWAYS, the condition field is
14981 changed to inst.uncond_value. This is necessary because instructions shared
14982 between VFP and Neon may be conditional for the VFP variants only, and the
14983 unconditional Neon version must have, e.g., 0xF in the condition field. */
14986 vfp_or_neon_is_neon (unsigned check
)
14988 /* Conditions are always legal in Thumb mode (IT blocks). */
14989 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14991 if (inst
.cond
!= COND_ALWAYS
)
14993 first_error (_(BAD_COND
));
14996 if (inst
.uncond_value
!= -1)
14997 inst
.instruction
|= inst
.uncond_value
<< 28;
15000 if ((check
& NEON_CHECK_ARCH
)
15001 && !mark_feature_used (&fpu_neon_ext_v1
))
15003 first_error (_(BAD_FPU
));
15007 if ((check
& NEON_CHECK_ARCH8
)
15008 && !mark_feature_used (&fpu_neon_ext_armv8
))
15010 first_error (_(BAD_FPU
));
15018 do_neon_addsub_if_i (void)
15020 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15023 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15026 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15027 affected if we specify unsigned args. */
15028 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15031 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15033 V<op> A,B (A is operand 0, B is operand 2)
15038 so handle that case specially. */
15041 neon_exchange_operands (void)
15043 if (inst
.operands
[1].present
)
15045 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15047 /* Swap operands[1] and operands[2]. */
15048 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15049 inst
.operands
[1] = inst
.operands
[2];
15050 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15055 inst
.operands
[1] = inst
.operands
[2];
15056 inst
.operands
[2] = inst
.operands
[0];
15061 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15063 if (inst
.operands
[2].isreg
)
15066 neon_exchange_operands ();
15067 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15071 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15072 struct neon_type_el et
= neon_check_type (2, rs
,
15073 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15075 NEON_ENCODE (IMMED
, inst
);
15076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15077 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15080 inst
.instruction
|= neon_quad (rs
) << 6;
15081 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15082 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15084 neon_dp_fixup (&inst
);
15091 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15095 do_neon_cmp_inv (void)
15097 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15103 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15106 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15107 scalars, which are encoded in 5 bits, M : Rm.
15108 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15109 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15112 Dot Product instructions are similar to multiply instructions except elsize
15113 should always be 32.
15115 This function translates SCALAR, which is GAS's internal encoding of indexed
15116 scalar register, to raw encoding. There is also register and index range
15117 check based on ELSIZE. */
15120 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15122 unsigned regno
= NEON_SCALAR_REG (scalar
);
15123 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15128 if (regno
> 7 || elno
> 3)
15130 return regno
| (elno
<< 3);
15133 if (regno
> 15 || elno
> 1)
15135 return regno
| (elno
<< 4);
15139 first_error (_("scalar out of range for multiply instruction"));
15145 /* Encode multiply / multiply-accumulate scalar instructions. */
15148 neon_mul_mac (struct neon_type_el et
, int ubit
)
15152 /* Give a more helpful error message if we have an invalid type. */
15153 if (et
.type
== NT_invtype
)
15156 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15157 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15158 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15159 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15160 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15161 inst
.instruction
|= LOW4 (scalar
);
15162 inst
.instruction
|= HI1 (scalar
) << 5;
15163 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15164 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15165 inst
.instruction
|= (ubit
!= 0) << 24;
15167 neon_dp_fixup (&inst
);
15171 do_neon_mac_maybe_scalar (void)
15173 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15176 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15179 if (inst
.operands
[2].isscalar
)
15181 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15182 struct neon_type_el et
= neon_check_type (3, rs
,
15183 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15184 NEON_ENCODE (SCALAR
, inst
);
15185 neon_mul_mac (et
, neon_quad (rs
));
15189 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15190 affected if we specify unsigned args. */
15191 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15196 do_neon_fmac (void)
15198 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15201 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15204 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15210 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15211 struct neon_type_el et
= neon_check_type (3, rs
,
15212 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15213 neon_three_same (neon_quad (rs
), 0, et
.size
);
15216 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15217 same types as the MAC equivalents. The polynomial type for this instruction
15218 is encoded the same as the integer type. */
15223 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15226 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15229 if (inst
.operands
[2].isscalar
)
15230 do_neon_mac_maybe_scalar ();
15232 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15236 do_neon_qdmulh (void)
15238 if (inst
.operands
[2].isscalar
)
15240 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15241 struct neon_type_el et
= neon_check_type (3, rs
,
15242 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15243 NEON_ENCODE (SCALAR
, inst
);
15244 neon_mul_mac (et
, neon_quad (rs
));
15248 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15249 struct neon_type_el et
= neon_check_type (3, rs
,
15250 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15251 NEON_ENCODE (INTEGER
, inst
);
15252 /* The U bit (rounding) comes from bit mask. */
15253 neon_three_same (neon_quad (rs
), 0, et
.size
);
15258 do_neon_qrdmlah (void)
15260 /* Check we're on the correct architecture. */
15261 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15263 _("instruction form not available on this architecture.");
15264 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15266 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15267 record_feature_use (&fpu_neon_ext_v8_1
);
15270 if (inst
.operands
[2].isscalar
)
15272 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15273 struct neon_type_el et
= neon_check_type (3, rs
,
15274 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15275 NEON_ENCODE (SCALAR
, inst
);
15276 neon_mul_mac (et
, neon_quad (rs
));
15280 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15281 struct neon_type_el et
= neon_check_type (3, rs
,
15282 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15283 NEON_ENCODE (INTEGER
, inst
);
15284 /* The U bit (rounding) comes from bit mask. */
15285 neon_three_same (neon_quad (rs
), 0, et
.size
);
15290 do_neon_fcmp_absolute (void)
15292 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15293 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15294 N_F_16_32
| N_KEY
);
15295 /* Size field comes from bit mask. */
15296 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15300 do_neon_fcmp_absolute_inv (void)
15302 neon_exchange_operands ();
15303 do_neon_fcmp_absolute ();
15307 do_neon_step (void)
15309 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15310 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15311 N_F_16_32
| N_KEY
);
15312 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15316 do_neon_abs_neg (void)
15318 enum neon_shape rs
;
15319 struct neon_type_el et
;
15321 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15324 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15327 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15328 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15330 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15331 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15332 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15333 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15334 inst
.instruction
|= neon_quad (rs
) << 6;
15335 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15336 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15338 neon_dp_fixup (&inst
);
15344 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15345 struct neon_type_el et
= neon_check_type (2, rs
,
15346 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15347 int imm
= inst
.operands
[2].imm
;
15348 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15349 _("immediate out of range for insert"));
15350 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15356 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15357 struct neon_type_el et
= neon_check_type (2, rs
,
15358 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15359 int imm
= inst
.operands
[2].imm
;
15360 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15361 _("immediate out of range for insert"));
15362 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15366 do_neon_qshlu_imm (void)
15368 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15369 struct neon_type_el et
= neon_check_type (2, rs
,
15370 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15371 int imm
= inst
.operands
[2].imm
;
15372 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15373 _("immediate out of range for shift"));
15374 /* Only encodes the 'U present' variant of the instruction.
15375 In this case, signed types have OP (bit 8) set to 0.
15376 Unsigned types have OP set to 1. */
15377 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15378 /* The rest of the bits are the same as other immediate shifts. */
15379 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15383 do_neon_qmovn (void)
15385 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15386 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15387 /* Saturating move where operands can be signed or unsigned, and the
15388 destination has the same signedness. */
15389 NEON_ENCODE (INTEGER
, inst
);
15390 if (et
.type
== NT_unsigned
)
15391 inst
.instruction
|= 0xc0;
15393 inst
.instruction
|= 0x80;
15394 neon_two_same (0, 1, et
.size
/ 2);
15398 do_neon_qmovun (void)
15400 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15401 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15402 /* Saturating move with unsigned results. Operands must be signed. */
15403 NEON_ENCODE (INTEGER
, inst
);
15404 neon_two_same (0, 1, et
.size
/ 2);
15408 do_neon_rshift_sat_narrow (void)
15410 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15411 or unsigned. If operands are unsigned, results must also be unsigned. */
15412 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15413 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15414 int imm
= inst
.operands
[2].imm
;
15415 /* This gets the bounds check, size encoding and immediate bits calculation
15419 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15420 VQMOVN.I<size> <Dd>, <Qm>. */
15423 inst
.operands
[2].present
= 0;
15424 inst
.instruction
= N_MNEM_vqmovn
;
15429 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15430 _("immediate out of range"));
15431 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15435 do_neon_rshift_sat_narrow_u (void)
15437 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15438 or unsigned. If operands are unsigned, results must also be unsigned. */
15439 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15440 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15441 int imm
= inst
.operands
[2].imm
;
15442 /* This gets the bounds check, size encoding and immediate bits calculation
15446 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15447 VQMOVUN.I<size> <Dd>, <Qm>. */
15450 inst
.operands
[2].present
= 0;
15451 inst
.instruction
= N_MNEM_vqmovun
;
15456 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15457 _("immediate out of range"));
15458 /* FIXME: The manual is kind of unclear about what value U should have in
15459 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15461 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15465 do_neon_movn (void)
15467 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15468 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15469 NEON_ENCODE (INTEGER
, inst
);
15470 neon_two_same (0, 1, et
.size
/ 2);
15474 do_neon_rshift_narrow (void)
15476 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15477 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15478 int imm
= inst
.operands
[2].imm
;
15479 /* This gets the bounds check, size encoding and immediate bits calculation
15483 /* If immediate is zero then we are a pseudo-instruction for
15484 VMOVN.I<size> <Dd>, <Qm> */
15487 inst
.operands
[2].present
= 0;
15488 inst
.instruction
= N_MNEM_vmovn
;
15493 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15494 _("immediate out of range for narrowing operation"));
15495 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15499 do_neon_shll (void)
15501 /* FIXME: Type checking when lengthening. */
15502 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15503 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15504 unsigned imm
= inst
.operands
[2].imm
;
15506 if (imm
== et
.size
)
15508 /* Maximum shift variant. */
15509 NEON_ENCODE (INTEGER
, inst
);
15510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15511 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15512 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15513 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15514 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15516 neon_dp_fixup (&inst
);
15520 /* A more-specific type check for non-max versions. */
15521 et
= neon_check_type (2, NS_QDI
,
15522 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15523 NEON_ENCODE (IMMED
, inst
);
15524 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15528 /* Check the various types for the VCVT instruction, and return which version
15529 the current instruction is. */
15531 #define CVT_FLAVOUR_VAR \
15532 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15533 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15534 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15535 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15536 /* Half-precision conversions. */ \
15537 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15538 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15539 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15540 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15541 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15542 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15543 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15544 Compared with single/double precision variants, only the co-processor \
15545 field is different, so the encoding flow is reused here. */ \
15546 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15547 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15548 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15549 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15550 /* VFP instructions. */ \
15551 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15552 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15553 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15554 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15555 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15556 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15557 /* VFP instructions with bitshift. */ \
15558 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15559 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15560 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15561 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15562 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15563 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15564 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15565 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15567 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15568 neon_cvt_flavour_##C,
15570 /* The different types of conversions we can do. */
15571 enum neon_cvt_flavour
15574 neon_cvt_flavour_invalid
,
15575 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15580 static enum neon_cvt_flavour
15581 get_neon_cvt_flavour (enum neon_shape rs
)
15583 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15584 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15585 if (et.type != NT_invtype) \
15587 inst.error = NULL; \
15588 return (neon_cvt_flavour_##C); \
15591 struct neon_type_el et
;
15592 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15593 || rs
== NS_FF
) ? N_VFP
: 0;
15594 /* The instruction versions which take an immediate take one register
15595 argument, which is extended to the width of the full register. Thus the
15596 "source" and "destination" registers must have the same width. Hack that
15597 here by making the size equal to the key (wider, in this case) operand. */
15598 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15602 return neon_cvt_flavour_invalid
;
15617 /* Neon-syntax VFP conversions. */
15620 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15622 const char *opname
= 0;
15624 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15625 || rs
== NS_FHI
|| rs
== NS_HFI
)
15627 /* Conversions with immediate bitshift. */
15628 const char *enc
[] =
15630 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15636 if (flavour
< (int) ARRAY_SIZE (enc
))
15638 opname
= enc
[flavour
];
15639 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15640 _("operands 0 and 1 must be the same register"));
15641 inst
.operands
[1] = inst
.operands
[2];
15642 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15647 /* Conversions without bitshift. */
15648 const char *enc
[] =
15650 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15656 if (flavour
< (int) ARRAY_SIZE (enc
))
15657 opname
= enc
[flavour
];
15661 do_vfp_nsyn_opcode (opname
);
15663 /* ARMv8.2 fp16 VCVT instruction. */
15664 if (flavour
== neon_cvt_flavour_s32_f16
15665 || flavour
== neon_cvt_flavour_u32_f16
15666 || flavour
== neon_cvt_flavour_f16_u32
15667 || flavour
== neon_cvt_flavour_f16_s32
)
15668 do_scalar_fp16_v82_encode ();
15672 do_vfp_nsyn_cvtz (void)
15674 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15675 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15676 const char *enc
[] =
15678 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15684 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15685 do_vfp_nsyn_opcode (enc
[flavour
]);
15689 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15690 enum neon_cvt_mode mode
)
15695 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15696 D register operands. */
15697 if (flavour
== neon_cvt_flavour_s32_f64
15698 || flavour
== neon_cvt_flavour_u32_f64
)
15699 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15702 if (flavour
== neon_cvt_flavour_s32_f16
15703 || flavour
== neon_cvt_flavour_u32_f16
)
15704 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15707 set_it_insn_type (OUTSIDE_IT_INSN
);
15711 case neon_cvt_flavour_s32_f64
:
15715 case neon_cvt_flavour_s32_f32
:
15719 case neon_cvt_flavour_s32_f16
:
15723 case neon_cvt_flavour_u32_f64
:
15727 case neon_cvt_flavour_u32_f32
:
15731 case neon_cvt_flavour_u32_f16
:
15736 first_error (_("invalid instruction shape"));
15742 case neon_cvt_mode_a
: rm
= 0; break;
15743 case neon_cvt_mode_n
: rm
= 1; break;
15744 case neon_cvt_mode_p
: rm
= 2; break;
15745 case neon_cvt_mode_m
: rm
= 3; break;
15746 default: first_error (_("invalid rounding mode")); return;
15749 NEON_ENCODE (FPV8
, inst
);
15750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15751 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15752 inst
.instruction
|= sz
<< 8;
15754 /* ARMv8.2 fp16 VCVT instruction. */
15755 if (flavour
== neon_cvt_flavour_s32_f16
15756 ||flavour
== neon_cvt_flavour_u32_f16
)
15757 do_scalar_fp16_v82_encode ();
15758 inst
.instruction
|= op
<< 7;
15759 inst
.instruction
|= rm
<< 16;
15760 inst
.instruction
|= 0xf0000000;
15761 inst
.is_neon
= TRUE
;
15765 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15767 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15768 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15769 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15771 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15773 if (flavour
== neon_cvt_flavour_invalid
)
15776 /* PR11109: Handle round-to-zero for VCVT conversions. */
15777 if (mode
== neon_cvt_mode_z
15778 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15779 && (flavour
== neon_cvt_flavour_s16_f16
15780 || flavour
== neon_cvt_flavour_u16_f16
15781 || flavour
== neon_cvt_flavour_s32_f32
15782 || flavour
== neon_cvt_flavour_u32_f32
15783 || flavour
== neon_cvt_flavour_s32_f64
15784 || flavour
== neon_cvt_flavour_u32_f64
)
15785 && (rs
== NS_FD
|| rs
== NS_FF
))
15787 do_vfp_nsyn_cvtz ();
15791 /* ARMv8.2 fp16 VCVT conversions. */
15792 if (mode
== neon_cvt_mode_z
15793 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15794 && (flavour
== neon_cvt_flavour_s32_f16
15795 || flavour
== neon_cvt_flavour_u32_f16
)
15798 do_vfp_nsyn_cvtz ();
15799 do_scalar_fp16_v82_encode ();
15803 /* VFP rather than Neon conversions. */
15804 if (flavour
>= neon_cvt_flavour_first_fp
)
15806 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15807 do_vfp_nsyn_cvt (rs
, flavour
);
15809 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15820 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15821 0x0000100, 0x1000100, 0x0, 0x1000000};
15823 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15826 /* Fixed-point conversion with #0 immediate is encoded as an
15827 integer conversion. */
15828 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15830 NEON_ENCODE (IMMED
, inst
);
15831 if (flavour
!= neon_cvt_flavour_invalid
)
15832 inst
.instruction
|= enctab
[flavour
];
15833 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15834 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15835 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15836 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15837 inst
.instruction
|= neon_quad (rs
) << 6;
15838 inst
.instruction
|= 1 << 21;
15839 if (flavour
< neon_cvt_flavour_s16_f16
)
15841 inst
.instruction
|= 1 << 21;
15842 immbits
= 32 - inst
.operands
[2].imm
;
15843 inst
.instruction
|= immbits
<< 16;
15847 inst
.instruction
|= 3 << 20;
15848 immbits
= 16 - inst
.operands
[2].imm
;
15849 inst
.instruction
|= immbits
<< 16;
15850 inst
.instruction
&= ~(1 << 9);
15853 neon_dp_fixup (&inst
);
15859 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15861 NEON_ENCODE (FLOAT
, inst
);
15862 set_it_insn_type (OUTSIDE_IT_INSN
);
15864 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15867 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15868 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15869 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15870 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15871 inst
.instruction
|= neon_quad (rs
) << 6;
15872 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15873 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15874 inst
.instruction
|= mode
<< 8;
15875 if (flavour
== neon_cvt_flavour_u16_f16
15876 || flavour
== neon_cvt_flavour_s16_f16
)
15877 /* Mask off the original size bits and reencode them. */
15878 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15881 inst
.instruction
|= 0xfc000000;
15883 inst
.instruction
|= 0xf0000000;
15889 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15890 0x100, 0x180, 0x0, 0x080};
15892 NEON_ENCODE (INTEGER
, inst
);
15894 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15897 if (flavour
!= neon_cvt_flavour_invalid
)
15898 inst
.instruction
|= enctab
[flavour
];
15900 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15901 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15902 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15903 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15904 inst
.instruction
|= neon_quad (rs
) << 6;
15905 if (flavour
>= neon_cvt_flavour_s16_f16
15906 && flavour
<= neon_cvt_flavour_f16_u16
)
15907 /* Half precision. */
15908 inst
.instruction
|= 1 << 18;
15910 inst
.instruction
|= 2 << 18;
15912 neon_dp_fixup (&inst
);
15917 /* Half-precision conversions for Advanced SIMD -- neon. */
15920 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15924 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15926 as_bad (_("operand size must match register width"));
15931 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15933 as_bad (_("operand size must match register width"));
15938 inst
.instruction
= 0x3b60600;
15940 inst
.instruction
= 0x3b60700;
15942 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15943 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15944 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15945 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15946 neon_dp_fixup (&inst
);
15950 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15951 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15952 do_vfp_nsyn_cvt (rs
, flavour
);
15954 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15959 do_neon_cvtr (void)
15961 do_neon_cvt_1 (neon_cvt_mode_x
);
15967 do_neon_cvt_1 (neon_cvt_mode_z
);
15971 do_neon_cvta (void)
15973 do_neon_cvt_1 (neon_cvt_mode_a
);
15977 do_neon_cvtn (void)
15979 do_neon_cvt_1 (neon_cvt_mode_n
);
15983 do_neon_cvtp (void)
15985 do_neon_cvt_1 (neon_cvt_mode_p
);
15989 do_neon_cvtm (void)
15991 do_neon_cvt_1 (neon_cvt_mode_m
);
15995 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15998 mark_feature_used (&fpu_vfp_ext_armv8
);
16000 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16001 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16002 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16003 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16004 inst
.instruction
|= to
? 0x10000 : 0;
16005 inst
.instruction
|= t
? 0x80 : 0;
16006 inst
.instruction
|= is_double
? 0x100 : 0;
16007 do_vfp_cond_or_thumb ();
16011 do_neon_cvttb_1 (bfd_boolean t
)
16013 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16014 NS_DF
, NS_DH
, NS_NULL
);
16018 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16021 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16023 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16026 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16028 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16030 /* The VCVTB and VCVTT instructions with D-register operands
16031 don't work for SP only targets. */
16032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16036 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16038 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16040 /* The VCVTB and VCVTT instructions with D-register operands
16041 don't work for SP only targets. */
16042 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16046 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16053 do_neon_cvtb (void)
16055 do_neon_cvttb_1 (FALSE
);
16060 do_neon_cvtt (void)
16062 do_neon_cvttb_1 (TRUE
);
16066 neon_move_immediate (void)
16068 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16069 struct neon_type_el et
= neon_check_type (2, rs
,
16070 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16071 unsigned immlo
, immhi
= 0, immbits
;
16072 int op
, cmode
, float_p
;
16074 constraint (et
.type
== NT_invtype
,
16075 _("operand size must be specified for immediate VMOV"));
16077 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16078 op
= (inst
.instruction
& (1 << 5)) != 0;
16080 immlo
= inst
.operands
[1].imm
;
16081 if (inst
.operands
[1].regisimm
)
16082 immhi
= inst
.operands
[1].reg
;
16084 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16085 _("immediate has bits set outside the operand size"));
16087 float_p
= inst
.operands
[1].immisfloat
;
16089 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16090 et
.size
, et
.type
)) == FAIL
)
16092 /* Invert relevant bits only. */
16093 neon_invert_size (&immlo
, &immhi
, et
.size
);
16094 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16095 with one or the other; those cases are caught by
16096 neon_cmode_for_move_imm. */
16098 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16099 &op
, et
.size
, et
.type
)) == FAIL
)
16101 first_error (_("immediate out of range"));
16106 inst
.instruction
&= ~(1 << 5);
16107 inst
.instruction
|= op
<< 5;
16109 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16110 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16111 inst
.instruction
|= neon_quad (rs
) << 6;
16112 inst
.instruction
|= cmode
<< 8;
16114 neon_write_immbits (immbits
);
16120 if (inst
.operands
[1].isreg
)
16122 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16124 NEON_ENCODE (INTEGER
, inst
);
16125 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16126 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16127 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16128 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16129 inst
.instruction
|= neon_quad (rs
) << 6;
16133 NEON_ENCODE (IMMED
, inst
);
16134 neon_move_immediate ();
16137 neon_dp_fixup (&inst
);
16140 /* Encode instructions of form:
16142 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16143 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16146 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16148 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16152 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16153 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16154 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16155 inst
.instruction
|= neon_logbits (size
) << 20;
16157 neon_dp_fixup (&inst
);
16161 do_neon_dyadic_long (void)
16163 /* FIXME: Type checking for lengthening op. */
16164 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16165 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16166 neon_mixed_length (et
, et
.size
);
16170 do_neon_abal (void)
16172 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16173 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16174 neon_mixed_length (et
, et
.size
);
16178 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16180 if (inst
.operands
[2].isscalar
)
16182 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16183 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16184 NEON_ENCODE (SCALAR
, inst
);
16185 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16189 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16190 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16191 NEON_ENCODE (INTEGER
, inst
);
16192 neon_mixed_length (et
, et
.size
);
16197 do_neon_mac_maybe_scalar_long (void)
16199 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16202 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16203 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16206 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16208 unsigned regno
= NEON_SCALAR_REG (scalar
);
16209 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16213 if (regno
> 7 || elno
> 3)
16216 return ((regno
& 0x7)
16217 | ((elno
& 0x1) << 3)
16218 | (((elno
>> 1) & 0x1) << 5));
16222 if (regno
> 15 || elno
> 1)
16225 return (((regno
& 0x1) << 5)
16226 | ((regno
>> 1) & 0x7)
16227 | ((elno
& 0x1) << 3));
16231 first_error (_("scalar out of range for multiply instruction"));
16236 do_neon_fmac_maybe_scalar_long (int subtype
)
16238 enum neon_shape rs
;
16240 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16241 field (bits[21:20]) has different meaning. For scalar index variant, it's
16242 used to differentiate add and subtract, otherwise it's with fixed value
16246 if (inst
.cond
!= COND_ALWAYS
)
16247 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16248 "behaviour is UNPREDICTABLE"));
16250 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16253 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16256 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16257 be a scalar index register. */
16258 if (inst
.operands
[2].isscalar
)
16260 high8
= 0xfe000000;
16263 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16267 high8
= 0xfc000000;
16270 inst
.instruction
|= (0x1 << 23);
16271 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16274 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16276 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16277 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16278 so we simply pass -1 as size. */
16279 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16280 neon_three_same (quad_p
, 0, size
);
16282 /* Undo neon_dp_fixup. Redo the high eight bits. */
16283 inst
.instruction
&= 0x00ffffff;
16284 inst
.instruction
|= high8
;
16286 #define LOW1(R) ((R) & 0x1)
16287 #define HI4(R) (((R) >> 1) & 0xf)
16288 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16289 whether the instruction is in Q form and whether Vm is a scalar indexed
16291 if (inst
.operands
[2].isscalar
)
16294 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16295 inst
.instruction
&= 0xffffffd0;
16296 inst
.instruction
|= rm
;
16300 /* Redo Rn as well. */
16301 inst
.instruction
&= 0xfff0ff7f;
16302 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16303 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16308 /* Redo Rn and Rm. */
16309 inst
.instruction
&= 0xfff0ff50;
16310 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16311 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16312 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16313 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16318 do_neon_vfmal (void)
16320 return do_neon_fmac_maybe_scalar_long (0);
16324 do_neon_vfmsl (void)
16326 return do_neon_fmac_maybe_scalar_long (1);
16330 do_neon_dyadic_wide (void)
16332 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16333 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16334 neon_mixed_length (et
, et
.size
);
16338 do_neon_dyadic_narrow (void)
16340 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16341 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16342 /* Operand sign is unimportant, and the U bit is part of the opcode,
16343 so force the operand type to integer. */
16344 et
.type
= NT_integer
;
16345 neon_mixed_length (et
, et
.size
/ 2);
16349 do_neon_mul_sat_scalar_long (void)
16351 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16355 do_neon_vmull (void)
16357 if (inst
.operands
[2].isscalar
)
16358 do_neon_mac_maybe_scalar_long ();
16361 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16362 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16364 if (et
.type
== NT_poly
)
16365 NEON_ENCODE (POLY
, inst
);
16367 NEON_ENCODE (INTEGER
, inst
);
16369 /* For polynomial encoding the U bit must be zero, and the size must
16370 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16371 obviously, as 0b10). */
16374 /* Check we're on the correct architecture. */
16375 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16377 _("Instruction form not available on this architecture.");
16382 neon_mixed_length (et
, et
.size
);
16389 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16390 struct neon_type_el et
= neon_check_type (3, rs
,
16391 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16392 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16394 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16395 _("shift out of range"));
16396 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16397 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16398 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16399 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16400 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16401 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16402 inst
.instruction
|= neon_quad (rs
) << 6;
16403 inst
.instruction
|= imm
<< 8;
16405 neon_dp_fixup (&inst
);
16411 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16412 struct neon_type_el et
= neon_check_type (2, rs
,
16413 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16414 unsigned op
= (inst
.instruction
>> 7) & 3;
16415 /* N (width of reversed regions) is encoded as part of the bitmask. We
16416 extract it here to check the elements to be reversed are smaller.
16417 Otherwise we'd get a reserved instruction. */
16418 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16419 gas_assert (elsize
!= 0);
16420 constraint (et
.size
>= elsize
,
16421 _("elements must be smaller than reversal region"));
16422 neon_two_same (neon_quad (rs
), 1, et
.size
);
16428 if (inst
.operands
[1].isscalar
)
16430 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16431 struct neon_type_el et
= neon_check_type (2, rs
,
16432 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16433 unsigned sizebits
= et
.size
>> 3;
16434 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16435 int logsize
= neon_logbits (et
.size
);
16436 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16438 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16441 NEON_ENCODE (SCALAR
, inst
);
16442 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16443 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16444 inst
.instruction
|= LOW4 (dm
);
16445 inst
.instruction
|= HI1 (dm
) << 5;
16446 inst
.instruction
|= neon_quad (rs
) << 6;
16447 inst
.instruction
|= x
<< 17;
16448 inst
.instruction
|= sizebits
<< 16;
16450 neon_dp_fixup (&inst
);
16454 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16455 struct neon_type_el et
= neon_check_type (2, rs
,
16456 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16457 /* Duplicate ARM register to lanes of vector. */
16458 NEON_ENCODE (ARMREG
, inst
);
16461 case 8: inst
.instruction
|= 0x400000; break;
16462 case 16: inst
.instruction
|= 0x000020; break;
16463 case 32: inst
.instruction
|= 0x000000; break;
16466 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16467 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16468 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16469 inst
.instruction
|= neon_quad (rs
) << 21;
16470 /* The encoding for this instruction is identical for the ARM and Thumb
16471 variants, except for the condition field. */
16472 do_vfp_cond_or_thumb ();
16476 /* VMOV has particularly many variations. It can be one of:
16477 0. VMOV<c><q> <Qd>, <Qm>
16478 1. VMOV<c><q> <Dd>, <Dm>
16479 (Register operations, which are VORR with Rm = Rn.)
16480 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16481 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16483 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16484 (ARM register to scalar.)
16485 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16486 (Two ARM registers to vector.)
16487 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16488 (Scalar to ARM register.)
16489 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16490 (Vector to two ARM registers.)
16491 8. VMOV.F32 <Sd>, <Sm>
16492 9. VMOV.F64 <Dd>, <Dm>
16493 (VFP register moves.)
16494 10. VMOV.F32 <Sd>, #imm
16495 11. VMOV.F64 <Dd>, #imm
16496 (VFP float immediate load.)
16497 12. VMOV <Rd>, <Sm>
16498 (VFP single to ARM reg.)
16499 13. VMOV <Sd>, <Rm>
16500 (ARM reg to VFP single.)
16501 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16502 (Two ARM regs to two VFP singles.)
16503 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16504 (Two VFP singles to two ARM regs.)
16506 These cases can be disambiguated using neon_select_shape, except cases 1/9
16507 and 3/11 which depend on the operand type too.
16509 All the encoded bits are hardcoded by this function.
16511 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16512 Cases 5, 7 may be used with VFPv2 and above.
16514 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16515 can specify a type where it doesn't make sense to, and is ignored). */
16520 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16521 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16522 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16523 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16524 struct neon_type_el et
;
16525 const char *ldconst
= 0;
16529 case NS_DD
: /* case 1/9. */
16530 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16531 /* It is not an error here if no type is given. */
16533 if (et
.type
== NT_float
&& et
.size
== 64)
16535 do_vfp_nsyn_opcode ("fcpyd");
16538 /* fall through. */
16540 case NS_QQ
: /* case 0/1. */
16542 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16544 /* The architecture manual I have doesn't explicitly state which
16545 value the U bit should have for register->register moves, but
16546 the equivalent VORR instruction has U = 0, so do that. */
16547 inst
.instruction
= 0x0200110;
16548 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16549 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16550 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16551 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16552 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16553 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16554 inst
.instruction
|= neon_quad (rs
) << 6;
16556 neon_dp_fixup (&inst
);
16560 case NS_DI
: /* case 3/11. */
16561 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16563 if (et
.type
== NT_float
&& et
.size
== 64)
16565 /* case 11 (fconstd). */
16566 ldconst
= "fconstd";
16567 goto encode_fconstd
;
16569 /* fall through. */
16571 case NS_QI
: /* case 2/3. */
16572 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16574 inst
.instruction
= 0x0800010;
16575 neon_move_immediate ();
16576 neon_dp_fixup (&inst
);
16579 case NS_SR
: /* case 4. */
16581 unsigned bcdebits
= 0;
16583 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16584 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16586 /* .<size> is optional here, defaulting to .32. */
16587 if (inst
.vectype
.elems
== 0
16588 && inst
.operands
[0].vectype
.type
== NT_invtype
16589 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16591 inst
.vectype
.el
[0].type
= NT_untyped
;
16592 inst
.vectype
.el
[0].size
= 32;
16593 inst
.vectype
.elems
= 1;
16596 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16597 logsize
= neon_logbits (et
.size
);
16599 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16601 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16602 && et
.size
!= 32, _(BAD_FPU
));
16603 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16604 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16608 case 8: bcdebits
= 0x8; break;
16609 case 16: bcdebits
= 0x1; break;
16610 case 32: bcdebits
= 0x0; break;
16614 bcdebits
|= x
<< logsize
;
16616 inst
.instruction
= 0xe000b10;
16617 do_vfp_cond_or_thumb ();
16618 inst
.instruction
|= LOW4 (dn
) << 16;
16619 inst
.instruction
|= HI1 (dn
) << 7;
16620 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16621 inst
.instruction
|= (bcdebits
& 3) << 5;
16622 inst
.instruction
|= (bcdebits
>> 2) << 21;
16626 case NS_DRR
: /* case 5 (fmdrr). */
16627 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16630 inst
.instruction
= 0xc400b10;
16631 do_vfp_cond_or_thumb ();
16632 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16633 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16634 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16635 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16638 case NS_RS
: /* case 6. */
16641 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16642 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16643 unsigned abcdebits
= 0;
16645 /* .<dt> is optional here, defaulting to .32. */
16646 if (inst
.vectype
.elems
== 0
16647 && inst
.operands
[0].vectype
.type
== NT_invtype
16648 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16650 inst
.vectype
.el
[0].type
= NT_untyped
;
16651 inst
.vectype
.el
[0].size
= 32;
16652 inst
.vectype
.elems
= 1;
16655 et
= neon_check_type (2, NS_NULL
,
16656 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16657 logsize
= neon_logbits (et
.size
);
16659 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16661 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16662 && et
.size
!= 32, _(BAD_FPU
));
16663 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16664 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16668 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16669 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16670 case 32: abcdebits
= 0x00; break;
16674 abcdebits
|= x
<< logsize
;
16675 inst
.instruction
= 0xe100b10;
16676 do_vfp_cond_or_thumb ();
16677 inst
.instruction
|= LOW4 (dn
) << 16;
16678 inst
.instruction
|= HI1 (dn
) << 7;
16679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16680 inst
.instruction
|= (abcdebits
& 3) << 5;
16681 inst
.instruction
|= (abcdebits
>> 2) << 21;
16685 case NS_RRD
: /* case 7 (fmrrd). */
16686 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16689 inst
.instruction
= 0xc500b10;
16690 do_vfp_cond_or_thumb ();
16691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16692 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16693 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16694 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16697 case NS_FF
: /* case 8 (fcpys). */
16698 do_vfp_nsyn_opcode ("fcpys");
16702 case NS_FI
: /* case 10 (fconsts). */
16703 ldconst
= "fconsts";
16705 if (!inst
.operands
[1].immisfloat
)
16708 /* Immediate has to fit in 8 bits so float is enough. */
16709 float imm
= (float) inst
.operands
[1].imm
;
16710 memcpy (&new_imm
, &imm
, sizeof (float));
16711 /* But the assembly may have been written to provide an integer
16712 bit pattern that equates to a float, so check that the
16713 conversion has worked. */
16714 if (is_quarter_float (new_imm
))
16716 if (is_quarter_float (inst
.operands
[1].imm
))
16717 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16719 inst
.operands
[1].imm
= new_imm
;
16720 inst
.operands
[1].immisfloat
= 1;
16724 if (is_quarter_float (inst
.operands
[1].imm
))
16726 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16727 do_vfp_nsyn_opcode (ldconst
);
16729 /* ARMv8.2 fp16 vmov.f16 instruction. */
16731 do_scalar_fp16_v82_encode ();
16734 first_error (_("immediate out of range"));
16738 case NS_RF
: /* case 12 (fmrs). */
16739 do_vfp_nsyn_opcode ("fmrs");
16740 /* ARMv8.2 fp16 vmov.f16 instruction. */
16742 do_scalar_fp16_v82_encode ();
16746 case NS_FR
: /* case 13 (fmsr). */
16747 do_vfp_nsyn_opcode ("fmsr");
16748 /* ARMv8.2 fp16 vmov.f16 instruction. */
16750 do_scalar_fp16_v82_encode ();
16753 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16754 (one of which is a list), but we have parsed four. Do some fiddling to
16755 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16757 case NS_RRFF
: /* case 14 (fmrrs). */
16758 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16759 _("VFP registers must be adjacent"));
16760 inst
.operands
[2].imm
= 2;
16761 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16762 do_vfp_nsyn_opcode ("fmrrs");
16765 case NS_FFRR
: /* case 15 (fmsrr). */
16766 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16767 _("VFP registers must be adjacent"));
16768 inst
.operands
[1] = inst
.operands
[2];
16769 inst
.operands
[2] = inst
.operands
[3];
16770 inst
.operands
[0].imm
= 2;
16771 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16772 do_vfp_nsyn_opcode ("fmsrr");
16776 /* neon_select_shape has determined that the instruction
16777 shape is wrong and has already set the error message. */
16786 do_neon_rshift_round_imm (void)
16788 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16789 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16790 int imm
= inst
.operands
[2].imm
;
16792 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16795 inst
.operands
[2].present
= 0;
16800 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16801 _("immediate out of range for shift"));
16802 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16807 do_neon_movhf (void)
16809 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16810 constraint (rs
!= NS_HH
, _("invalid suffix"));
16812 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16815 if (inst
.cond
!= COND_ALWAYS
)
16819 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16820 " the behaviour is UNPREDICTABLE"));
16824 inst
.error
= BAD_COND
;
16829 do_vfp_sp_monadic ();
16832 inst
.instruction
|= 0xf0000000;
16836 do_neon_movl (void)
16838 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16839 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16840 unsigned sizebits
= et
.size
>> 3;
16841 inst
.instruction
|= sizebits
<< 19;
16842 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16848 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16849 struct neon_type_el et
= neon_check_type (2, rs
,
16850 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16851 NEON_ENCODE (INTEGER
, inst
);
16852 neon_two_same (neon_quad (rs
), 1, et
.size
);
16856 do_neon_zip_uzp (void)
16858 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16859 struct neon_type_el et
= neon_check_type (2, rs
,
16860 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16861 if (rs
== NS_DD
&& et
.size
== 32)
16863 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16864 inst
.instruction
= N_MNEM_vtrn
;
16868 neon_two_same (neon_quad (rs
), 1, et
.size
);
16872 do_neon_sat_abs_neg (void)
16874 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16875 struct neon_type_el et
= neon_check_type (2, rs
,
16876 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16877 neon_two_same (neon_quad (rs
), 1, et
.size
);
16881 do_neon_pair_long (void)
16883 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16884 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16885 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16886 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16887 neon_two_same (neon_quad (rs
), 1, et
.size
);
16891 do_neon_recip_est (void)
16893 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16894 struct neon_type_el et
= neon_check_type (2, rs
,
16895 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16896 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16897 neon_two_same (neon_quad (rs
), 1, et
.size
);
16903 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16904 struct neon_type_el et
= neon_check_type (2, rs
,
16905 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16906 neon_two_same (neon_quad (rs
), 1, et
.size
);
16912 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16913 struct neon_type_el et
= neon_check_type (2, rs
,
16914 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16915 neon_two_same (neon_quad (rs
), 1, et
.size
);
16921 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16922 struct neon_type_el et
= neon_check_type (2, rs
,
16923 N_EQK
| N_INT
, N_8
| N_KEY
);
16924 neon_two_same (neon_quad (rs
), 1, et
.size
);
16930 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16931 neon_two_same (neon_quad (rs
), 1, -1);
16935 do_neon_tbl_tbx (void)
16937 unsigned listlenbits
;
16938 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16940 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16942 first_error (_("bad list length for table lookup"));
16946 listlenbits
= inst
.operands
[1].imm
- 1;
16947 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16948 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16949 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16950 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16951 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16952 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16953 inst
.instruction
|= listlenbits
<< 8;
16955 neon_dp_fixup (&inst
);
16959 do_neon_ldm_stm (void)
16961 /* P, U and L bits are part of bitmask. */
16962 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16963 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16965 if (inst
.operands
[1].issingle
)
16967 do_vfp_nsyn_ldm_stm (is_dbmode
);
16971 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16972 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16974 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16975 _("register list must contain at least 1 and at most 16 "
16978 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16979 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16980 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16983 inst
.instruction
|= offsetbits
;
16985 do_vfp_cond_or_thumb ();
16989 do_neon_ldr_str (void)
16991 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16993 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16994 And is UNPREDICTABLE in thumb mode. */
16996 && inst
.operands
[1].reg
== REG_PC
16997 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17000 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17001 else if (warn_on_deprecated
)
17002 as_tsktsk (_("Use of PC here is deprecated"));
17005 if (inst
.operands
[0].issingle
)
17008 do_vfp_nsyn_opcode ("flds");
17010 do_vfp_nsyn_opcode ("fsts");
17012 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17013 if (inst
.vectype
.el
[0].size
== 16)
17014 do_scalar_fp16_v82_encode ();
17019 do_vfp_nsyn_opcode ("fldd");
17021 do_vfp_nsyn_opcode ("fstd");
17025 /* "interleave" version also handles non-interleaving register VLD1/VST1
17029 do_neon_ld_st_interleave (void)
17031 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17032 N_8
| N_16
| N_32
| N_64
);
17033 unsigned alignbits
= 0;
17035 /* The bits in this table go:
17036 0: register stride of one (0) or two (1)
17037 1,2: register list length, minus one (1, 2, 3, 4).
17038 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17039 We use -1 for invalid entries. */
17040 const int typetable
[] =
17042 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17043 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17044 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17045 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17049 if (et
.type
== NT_invtype
)
17052 if (inst
.operands
[1].immisalign
)
17053 switch (inst
.operands
[1].imm
>> 8)
17055 case 64: alignbits
= 1; break;
17057 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17058 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17059 goto bad_alignment
;
17063 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17064 goto bad_alignment
;
17069 first_error (_("bad alignment"));
17073 inst
.instruction
|= alignbits
<< 4;
17074 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17076 /* Bits [4:6] of the immediate in a list specifier encode register stride
17077 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17078 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17079 up the right value for "type" in a table based on this value and the given
17080 list style, then stick it back. */
17081 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17082 | (((inst
.instruction
>> 8) & 3) << 3);
17084 typebits
= typetable
[idx
];
17086 constraint (typebits
== -1, _("bad list type for instruction"));
17087 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17088 _("bad element type for instruction"));
17090 inst
.instruction
&= ~0xf00;
17091 inst
.instruction
|= typebits
<< 8;
17094 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17095 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17096 otherwise. The variable arguments are a list of pairs of legal (size, align)
17097 values, terminated with -1. */
17100 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17103 int result
= FAIL
, thissize
, thisalign
;
17105 if (!inst
.operands
[1].immisalign
)
17111 va_start (ap
, do_alignment
);
17115 thissize
= va_arg (ap
, int);
17116 if (thissize
== -1)
17118 thisalign
= va_arg (ap
, int);
17120 if (size
== thissize
&& align
== thisalign
)
17123 while (result
!= SUCCESS
);
17127 if (result
== SUCCESS
)
17130 first_error (_("unsupported alignment for instruction"));
17136 do_neon_ld_st_lane (void)
17138 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17139 int align_good
, do_alignment
= 0;
17140 int logsize
= neon_logbits (et
.size
);
17141 int align
= inst
.operands
[1].imm
>> 8;
17142 int n
= (inst
.instruction
>> 8) & 3;
17143 int max_el
= 64 / et
.size
;
17145 if (et
.type
== NT_invtype
)
17148 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17149 _("bad list length"));
17150 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17151 _("scalar index out of range"));
17152 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17154 _("stride of 2 unavailable when element size is 8"));
17158 case 0: /* VLD1 / VST1. */
17159 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17161 if (align_good
== FAIL
)
17165 unsigned alignbits
= 0;
17168 case 16: alignbits
= 0x1; break;
17169 case 32: alignbits
= 0x3; break;
17172 inst
.instruction
|= alignbits
<< 4;
17176 case 1: /* VLD2 / VST2. */
17177 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17178 16, 32, 32, 64, -1);
17179 if (align_good
== FAIL
)
17182 inst
.instruction
|= 1 << 4;
17185 case 2: /* VLD3 / VST3. */
17186 constraint (inst
.operands
[1].immisalign
,
17187 _("can't use alignment with this instruction"));
17190 case 3: /* VLD4 / VST4. */
17191 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17192 16, 64, 32, 64, 32, 128, -1);
17193 if (align_good
== FAIL
)
17197 unsigned alignbits
= 0;
17200 case 8: alignbits
= 0x1; break;
17201 case 16: alignbits
= 0x1; break;
17202 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17205 inst
.instruction
|= alignbits
<< 4;
17212 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17213 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17214 inst
.instruction
|= 1 << (4 + logsize
);
17216 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17217 inst
.instruction
|= logsize
<< 10;
17220 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17223 do_neon_ld_dup (void)
17225 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17226 int align_good
, do_alignment
= 0;
17228 if (et
.type
== NT_invtype
)
17231 switch ((inst
.instruction
>> 8) & 3)
17233 case 0: /* VLD1. */
17234 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17235 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17236 &do_alignment
, 16, 16, 32, 32, -1);
17237 if (align_good
== FAIL
)
17239 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17242 case 2: inst
.instruction
|= 1 << 5; break;
17243 default: first_error (_("bad list length")); return;
17245 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17248 case 1: /* VLD2. */
17249 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17250 &do_alignment
, 8, 16, 16, 32, 32, 64,
17252 if (align_good
== FAIL
)
17254 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17255 _("bad list length"));
17256 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17257 inst
.instruction
|= 1 << 5;
17258 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17261 case 2: /* VLD3. */
17262 constraint (inst
.operands
[1].immisalign
,
17263 _("can't use alignment with this instruction"));
17264 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17265 _("bad list length"));
17266 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17267 inst
.instruction
|= 1 << 5;
17268 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17271 case 3: /* VLD4. */
17273 int align
= inst
.operands
[1].imm
>> 8;
17274 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17275 16, 64, 32, 64, 32, 128, -1);
17276 if (align_good
== FAIL
)
17278 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17279 _("bad list length"));
17280 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17281 inst
.instruction
|= 1 << 5;
17282 if (et
.size
== 32 && align
== 128)
17283 inst
.instruction
|= 0x3 << 6;
17285 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17292 inst
.instruction
|= do_alignment
<< 4;
17295 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17296 apart from bits [11:4]. */
17299 do_neon_ldx_stx (void)
17301 if (inst
.operands
[1].isreg
)
17302 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17304 switch (NEON_LANE (inst
.operands
[0].imm
))
17306 case NEON_INTERLEAVE_LANES
:
17307 NEON_ENCODE (INTERLV
, inst
);
17308 do_neon_ld_st_interleave ();
17311 case NEON_ALL_LANES
:
17312 NEON_ENCODE (DUP
, inst
);
17313 if (inst
.instruction
== N_INV
)
17315 first_error ("only loads support such operands");
17322 NEON_ENCODE (LANE
, inst
);
17323 do_neon_ld_st_lane ();
17326 /* L bit comes from bit mask. */
17327 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17328 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17329 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17331 if (inst
.operands
[1].postind
)
17333 int postreg
= inst
.operands
[1].imm
& 0xf;
17334 constraint (!inst
.operands
[1].immisreg
,
17335 _("post-index must be a register"));
17336 constraint (postreg
== 0xd || postreg
== 0xf,
17337 _("bad register for post-index"));
17338 inst
.instruction
|= postreg
;
17342 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17343 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17344 || inst
.reloc
.exp
.X_add_number
!= 0,
17347 if (inst
.operands
[1].writeback
)
17349 inst
.instruction
|= 0xd;
17352 inst
.instruction
|= 0xf;
17356 inst
.instruction
|= 0xf9000000;
17358 inst
.instruction
|= 0xf4000000;
17363 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17365 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17366 D register operands. */
17367 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17371 NEON_ENCODE (FPV8
, inst
);
17373 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17375 do_vfp_sp_dyadic ();
17377 /* ARMv8.2 fp16 instruction. */
17379 do_scalar_fp16_v82_encode ();
17382 do_vfp_dp_rd_rn_rm ();
17385 inst
.instruction
|= 0x100;
17387 inst
.instruction
|= 0xf0000000;
17393 set_it_insn_type (OUTSIDE_IT_INSN
);
17395 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17396 first_error (_("invalid instruction shape"));
17402 set_it_insn_type (OUTSIDE_IT_INSN
);
17404 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17407 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17410 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17414 do_vrint_1 (enum neon_cvt_mode mode
)
17416 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17417 struct neon_type_el et
;
17422 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17423 D register operands. */
17424 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17428 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17430 if (et
.type
!= NT_invtype
)
17432 /* VFP encodings. */
17433 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17434 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17435 set_it_insn_type (OUTSIDE_IT_INSN
);
17437 NEON_ENCODE (FPV8
, inst
);
17438 if (rs
== NS_FF
|| rs
== NS_HH
)
17439 do_vfp_sp_monadic ();
17441 do_vfp_dp_rd_rm ();
17445 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17446 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17447 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17448 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17449 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17450 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17451 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17455 inst
.instruction
|= (rs
== NS_DD
) << 8;
17456 do_vfp_cond_or_thumb ();
17458 /* ARMv8.2 fp16 vrint instruction. */
17460 do_scalar_fp16_v82_encode ();
17464 /* Neon encodings (or something broken...). */
17466 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17468 if (et
.type
== NT_invtype
)
17471 set_it_insn_type (OUTSIDE_IT_INSN
);
17472 NEON_ENCODE (FLOAT
, inst
);
17474 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17477 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17478 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17479 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17480 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17481 inst
.instruction
|= neon_quad (rs
) << 6;
17482 /* Mask off the original size bits and reencode them. */
17483 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17484 | neon_logbits (et
.size
) << 18);
17488 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17489 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17490 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17491 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17492 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17493 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17494 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17499 inst
.instruction
|= 0xfc000000;
17501 inst
.instruction
|= 0xf0000000;
17508 do_vrint_1 (neon_cvt_mode_x
);
17514 do_vrint_1 (neon_cvt_mode_z
);
17520 do_vrint_1 (neon_cvt_mode_r
);
17526 do_vrint_1 (neon_cvt_mode_a
);
17532 do_vrint_1 (neon_cvt_mode_n
);
17538 do_vrint_1 (neon_cvt_mode_p
);
17544 do_vrint_1 (neon_cvt_mode_m
);
17548 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17550 unsigned regno
= NEON_SCALAR_REG (opnd
);
17551 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17553 if (elsize
== 16 && elno
< 2 && regno
< 16)
17554 return regno
| (elno
<< 4);
17555 else if (elsize
== 32 && elno
== 0)
17558 first_error (_("scalar out of range"));
17565 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17567 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17568 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17569 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17570 _("immediate out of range"));
17572 if (inst
.operands
[2].isscalar
)
17574 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17575 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17576 N_KEY
| N_F16
| N_F32
).size
;
17577 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17579 inst
.instruction
= 0xfe000800;
17580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17584 inst
.instruction
|= LOW4 (m
);
17585 inst
.instruction
|= HI1 (m
) << 5;
17586 inst
.instruction
|= neon_quad (rs
) << 6;
17587 inst
.instruction
|= rot
<< 20;
17588 inst
.instruction
|= (size
== 32) << 23;
17592 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17593 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17594 N_KEY
| N_F16
| N_F32
).size
;
17595 neon_three_same (neon_quad (rs
), 0, -1);
17596 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17597 inst
.instruction
|= 0xfc200800;
17598 inst
.instruction
|= rot
<< 23;
17599 inst
.instruction
|= (size
== 32) << 20;
17606 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17608 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17609 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17610 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17611 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17612 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17613 N_KEY
| N_F16
| N_F32
).size
;
17614 neon_three_same (neon_quad (rs
), 0, -1);
17615 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17616 inst
.instruction
|= 0xfc800800;
17617 inst
.instruction
|= (rot
== 270) << 24;
17618 inst
.instruction
|= (size
== 32) << 20;
17621 /* Dot Product instructions encoding support. */
17624 do_neon_dotproduct (int unsigned_p
)
17626 enum neon_shape rs
;
17627 unsigned scalar_oprd2
= 0;
17630 if (inst
.cond
!= COND_ALWAYS
)
17631 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17632 "is UNPREDICTABLE"));
17634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17637 /* Dot Product instructions are in three-same D/Q register format or the third
17638 operand can be a scalar index register. */
17639 if (inst
.operands
[2].isscalar
)
17641 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17642 high8
= 0xfe000000;
17643 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17647 high8
= 0xfc000000;
17648 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17652 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17654 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17656 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17657 Product instruction, so we pass 0 as the "ubit" parameter. And the
17658 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17659 neon_three_same (neon_quad (rs
), 0, 32);
17661 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17662 different NEON three-same encoding. */
17663 inst
.instruction
&= 0x00ffffff;
17664 inst
.instruction
|= high8
;
17665 /* Encode 'U' bit which indicates signedness. */
17666 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17667 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17668 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17669 the instruction encoding. */
17670 if (inst
.operands
[2].isscalar
)
17672 inst
.instruction
&= 0xffffffd0;
17673 inst
.instruction
|= LOW4 (scalar_oprd2
);
17674 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17678 /* Dot Product instructions for signed integer. */
17681 do_neon_dotproduct_s (void)
17683 return do_neon_dotproduct (0);
17686 /* Dot Product instructions for unsigned integer. */
17689 do_neon_dotproduct_u (void)
17691 return do_neon_dotproduct (1);
17694 /* Crypto v1 instructions. */
17696 do_crypto_2op_1 (unsigned elttype
, int op
)
17698 set_it_insn_type (OUTSIDE_IT_INSN
);
17700 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17706 NEON_ENCODE (INTEGER
, inst
);
17707 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17708 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17709 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17710 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17712 inst
.instruction
|= op
<< 6;
17715 inst
.instruction
|= 0xfc000000;
17717 inst
.instruction
|= 0xf0000000;
17721 do_crypto_3op_1 (int u
, int op
)
17723 set_it_insn_type (OUTSIDE_IT_INSN
);
17725 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17726 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17731 NEON_ENCODE (INTEGER
, inst
);
17732 neon_three_same (1, u
, 8 << op
);
17738 do_crypto_2op_1 (N_8
, 0);
17744 do_crypto_2op_1 (N_8
, 1);
17750 do_crypto_2op_1 (N_8
, 2);
17756 do_crypto_2op_1 (N_8
, 3);
17762 do_crypto_3op_1 (0, 0);
17768 do_crypto_3op_1 (0, 1);
17774 do_crypto_3op_1 (0, 2);
17780 do_crypto_3op_1 (0, 3);
17786 do_crypto_3op_1 (1, 0);
17792 do_crypto_3op_1 (1, 1);
17796 do_sha256su1 (void)
17798 do_crypto_3op_1 (1, 2);
17804 do_crypto_2op_1 (N_32
, -1);
17810 do_crypto_2op_1 (N_32
, 0);
17814 do_sha256su0 (void)
17816 do_crypto_2op_1 (N_32
, 1);
17820 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17822 unsigned int Rd
= inst
.operands
[0].reg
;
17823 unsigned int Rn
= inst
.operands
[1].reg
;
17824 unsigned int Rm
= inst
.operands
[2].reg
;
17826 set_it_insn_type (OUTSIDE_IT_INSN
);
17827 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17828 inst
.instruction
|= LOW4 (Rn
) << 16;
17829 inst
.instruction
|= LOW4 (Rm
);
17830 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17831 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17833 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17834 as_warn (UNPRED_REG ("r15"));
17876 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17878 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17879 do_vfp_sp_dp_cvt ();
17880 do_vfp_cond_or_thumb ();
17884 /* Overall per-instruction processing. */
17886 /* We need to be able to fix up arbitrary expressions in some statements.
17887 This is so that we can handle symbols that are an arbitrary distance from
17888 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17889 which returns part of an address in a form which will be valid for
17890 a data instruction. We do this by pushing the expression into a symbol
17891 in the expr_section, and creating a fix for that. */
17894 fix_new_arm (fragS
* frag
,
17908 /* Create an absolute valued symbol, so we have something to
17909 refer to in the object file. Unfortunately for us, gas's
17910 generic expression parsing will already have folded out
17911 any use of .set foo/.type foo %function that may have
17912 been used to set type information of the target location,
17913 that's being specified symbolically. We have to presume
17914 the user knows what they are doing. */
17918 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17920 symbol
= symbol_find_or_make (name
);
17921 S_SET_SEGMENT (symbol
, absolute_section
);
17922 symbol_set_frag (symbol
, &zero_address_frag
);
17923 S_SET_VALUE (symbol
, exp
->X_add_number
);
17924 exp
->X_op
= O_symbol
;
17925 exp
->X_add_symbol
= symbol
;
17926 exp
->X_add_number
= 0;
17932 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17933 (enum bfd_reloc_code_real
) reloc
);
17937 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17938 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17942 /* Mark whether the fix is to a THUMB instruction, or an ARM
17944 new_fix
->tc_fix_data
= thumb_mode
;
17947 /* Create a frg for an instruction requiring relaxation. */
17949 output_relax_insn (void)
17955 /* The size of the instruction is unknown, so tie the debug info to the
17956 start of the instruction. */
17957 dwarf2_emit_insn (0);
17959 switch (inst
.reloc
.exp
.X_op
)
17962 sym
= inst
.reloc
.exp
.X_add_symbol
;
17963 offset
= inst
.reloc
.exp
.X_add_number
;
17967 offset
= inst
.reloc
.exp
.X_add_number
;
17970 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17974 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17975 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17976 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17979 /* Write a 32-bit thumb instruction to buf. */
17981 put_thumb32_insn (char * buf
, unsigned long insn
)
17983 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17984 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17988 output_inst (const char * str
)
17994 as_bad ("%s -- `%s'", inst
.error
, str
);
17999 output_relax_insn ();
18002 if (inst
.size
== 0)
18005 to
= frag_more (inst
.size
);
18006 /* PR 9814: Record the thumb mode into the current frag so that we know
18007 what type of NOP padding to use, if necessary. We override any previous
18008 setting so that if the mode has changed then the NOPS that we use will
18009 match the encoding of the last instruction in the frag. */
18010 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18012 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18014 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18015 put_thumb32_insn (to
, inst
.instruction
);
18017 else if (inst
.size
> INSN_SIZE
)
18019 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18020 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18021 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18024 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18026 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
18027 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18028 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
18031 dwarf2_emit_insn (inst
.size
);
18035 output_it_inst (int cond
, int mask
, char * to
)
18037 unsigned long instruction
= 0xbf00;
18040 instruction
|= mask
;
18041 instruction
|= cond
<< 4;
18045 to
= frag_more (2);
18047 dwarf2_emit_insn (2);
18051 md_number_to_chars (to
, instruction
, 2);
18056 /* Tag values used in struct asm_opcode's tag field. */
18059 OT_unconditional
, /* Instruction cannot be conditionalized.
18060 The ARM condition field is still 0xE. */
18061 OT_unconditionalF
, /* Instruction cannot be conditionalized
18062 and carries 0xF in its ARM condition field. */
18063 OT_csuffix
, /* Instruction takes a conditional suffix. */
18064 OT_csuffixF
, /* Some forms of the instruction take a conditional
18065 suffix, others place 0xF where the condition field
18067 OT_cinfix3
, /* Instruction takes a conditional infix,
18068 beginning at character index 3. (In
18069 unified mode, it becomes a suffix.) */
18070 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18071 tsts, cmps, cmns, and teqs. */
18072 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18073 character index 3, even in unified mode. Used for
18074 legacy instructions where suffix and infix forms
18075 may be ambiguous. */
18076 OT_csuf_or_in3
, /* Instruction takes either a conditional
18077 suffix or an infix at character index 3. */
18078 OT_odd_infix_unc
, /* This is the unconditional variant of an
18079 instruction that takes a conditional infix
18080 at an unusual position. In unified mode,
18081 this variant will accept a suffix. */
18082 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18083 are the conditional variants of instructions that
18084 take conditional infixes in unusual positions.
18085 The infix appears at character index
18086 (tag - OT_odd_infix_0). These are not accepted
18087 in unified mode. */
18090 /* Subroutine of md_assemble, responsible for looking up the primary
18091 opcode from the mnemonic the user wrote. STR points to the
18092 beginning of the mnemonic.
18094 This is not simply a hash table lookup, because of conditional
18095 variants. Most instructions have conditional variants, which are
18096 expressed with a _conditional affix_ to the mnemonic. If we were
18097 to encode each conditional variant as a literal string in the opcode
18098 table, it would have approximately 20,000 entries.
18100 Most mnemonics take this affix as a suffix, and in unified syntax,
18101 'most' is upgraded to 'all'. However, in the divided syntax, some
18102 instructions take the affix as an infix, notably the s-variants of
18103 the arithmetic instructions. Of those instructions, all but six
18104 have the infix appear after the third character of the mnemonic.
18106 Accordingly, the algorithm for looking up primary opcodes given
18109 1. Look up the identifier in the opcode table.
18110 If we find a match, go to step U.
18112 2. Look up the last two characters of the identifier in the
18113 conditions table. If we find a match, look up the first N-2
18114 characters of the identifier in the opcode table. If we
18115 find a match, go to step CE.
18117 3. Look up the fourth and fifth characters of the identifier in
18118 the conditions table. If we find a match, extract those
18119 characters from the identifier, and look up the remaining
18120 characters in the opcode table. If we find a match, go
18125 U. Examine the tag field of the opcode structure, in case this is
18126 one of the six instructions with its conditional infix in an
18127 unusual place. If it is, the tag tells us where to find the
18128 infix; look it up in the conditions table and set inst.cond
18129 accordingly. Otherwise, this is an unconditional instruction.
18130 Again set inst.cond accordingly. Return the opcode structure.
18132 CE. Examine the tag field to make sure this is an instruction that
18133 should receive a conditional suffix. If it is not, fail.
18134 Otherwise, set inst.cond from the suffix we already looked up,
18135 and return the opcode structure.
18137 CM. Examine the tag field to make sure this is an instruction that
18138 should receive a conditional infix after the third character.
18139 If it is not, fail. Otherwise, undo the edits to the current
18140 line of input and proceed as for case CE. */
18142 static const struct asm_opcode
*
18143 opcode_lookup (char **str
)
18147 const struct asm_opcode
*opcode
;
18148 const struct asm_cond
*cond
;
18151 /* Scan up to the end of the mnemonic, which must end in white space,
18152 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18153 for (base
= end
= *str
; *end
!= '\0'; end
++)
18154 if (*end
== ' ' || *end
== '.')
18160 /* Handle a possible width suffix and/or Neon type suffix. */
18165 /* The .w and .n suffixes are only valid if the unified syntax is in
18167 if (unified_syntax
&& end
[1] == 'w')
18169 else if (unified_syntax
&& end
[1] == 'n')
18174 inst
.vectype
.elems
= 0;
18176 *str
= end
+ offset
;
18178 if (end
[offset
] == '.')
18180 /* See if we have a Neon type suffix (possible in either unified or
18181 non-unified ARM syntax mode). */
18182 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18185 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18191 /* Look for unaffixed or special-case affixed mnemonic. */
18192 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18197 if (opcode
->tag
< OT_odd_infix_0
)
18199 inst
.cond
= COND_ALWAYS
;
18203 if (warn_on_deprecated
&& unified_syntax
)
18204 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18205 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18206 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18209 inst
.cond
= cond
->value
;
18213 /* Cannot have a conditional suffix on a mnemonic of less than two
18215 if (end
- base
< 3)
18218 /* Look for suffixed mnemonic. */
18220 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18221 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18223 if (opcode
&& cond
)
18226 switch (opcode
->tag
)
18228 case OT_cinfix3_legacy
:
18229 /* Ignore conditional suffixes matched on infix only mnemonics. */
18233 case OT_cinfix3_deprecated
:
18234 case OT_odd_infix_unc
:
18235 if (!unified_syntax
)
18237 /* Fall through. */
18241 case OT_csuf_or_in3
:
18242 inst
.cond
= cond
->value
;
18245 case OT_unconditional
:
18246 case OT_unconditionalF
:
18248 inst
.cond
= cond
->value
;
18251 /* Delayed diagnostic. */
18252 inst
.error
= BAD_COND
;
18253 inst
.cond
= COND_ALWAYS
;
18262 /* Cannot have a usual-position infix on a mnemonic of less than
18263 six characters (five would be a suffix). */
18264 if (end
- base
< 6)
18267 /* Look for infixed mnemonic in the usual position. */
18269 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18273 memcpy (save
, affix
, 2);
18274 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18275 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18277 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18278 memcpy (affix
, save
, 2);
18281 && (opcode
->tag
== OT_cinfix3
18282 || opcode
->tag
== OT_cinfix3_deprecated
18283 || opcode
->tag
== OT_csuf_or_in3
18284 || opcode
->tag
== OT_cinfix3_legacy
))
18287 if (warn_on_deprecated
&& unified_syntax
18288 && (opcode
->tag
== OT_cinfix3
18289 || opcode
->tag
== OT_cinfix3_deprecated
))
18290 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18292 inst
.cond
= cond
->value
;
18299 /* This function generates an initial IT instruction, leaving its block
18300 virtually open for the new instructions. Eventually,
18301 the mask will be updated by now_it_add_mask () each time
18302 a new instruction needs to be included in the IT block.
18303 Finally, the block is closed with close_automatic_it_block ().
18304 The block closure can be requested either from md_assemble (),
18305 a tencode (), or due to a label hook. */
18308 new_automatic_it_block (int cond
)
18310 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18311 now_it
.mask
= 0x18;
18313 now_it
.block_length
= 1;
18314 mapping_state (MAP_THUMB
);
18315 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18316 now_it
.warn_deprecated
= FALSE
;
18317 now_it
.insn_cond
= TRUE
;
18320 /* Close an automatic IT block.
18321 See comments in new_automatic_it_block (). */
18324 close_automatic_it_block (void)
18326 now_it
.mask
= 0x10;
18327 now_it
.block_length
= 0;
18330 /* Update the mask of the current automatically-generated IT
18331 instruction. See comments in new_automatic_it_block (). */
18334 now_it_add_mask (int cond
)
18336 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18337 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18338 | ((bitvalue) << (nbit)))
18339 const int resulting_bit
= (cond
& 1);
18341 now_it
.mask
&= 0xf;
18342 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18344 (5 - now_it
.block_length
));
18345 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18347 ((5 - now_it
.block_length
) - 1) );
18348 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18351 #undef SET_BIT_VALUE
18354 /* The IT blocks handling machinery is accessed through the these functions:
18355 it_fsm_pre_encode () from md_assemble ()
18356 set_it_insn_type () optional, from the tencode functions
18357 set_it_insn_type_last () ditto
18358 in_it_block () ditto
18359 it_fsm_post_encode () from md_assemble ()
18360 force_automatic_it_block_close () from label handling functions
18363 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18364 initializing the IT insn type with a generic initial value depending
18365 on the inst.condition.
18366 2) During the tencode function, two things may happen:
18367 a) The tencode function overrides the IT insn type by
18368 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18369 b) The tencode function queries the IT block state by
18370 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18372 Both set_it_insn_type and in_it_block run the internal FSM state
18373 handling function (handle_it_state), because: a) setting the IT insn
18374 type may incur in an invalid state (exiting the function),
18375 and b) querying the state requires the FSM to be updated.
18376 Specifically we want to avoid creating an IT block for conditional
18377 branches, so it_fsm_pre_encode is actually a guess and we can't
18378 determine whether an IT block is required until the tencode () routine
18379 has decided what type of instruction this actually it.
18380 Because of this, if set_it_insn_type and in_it_block have to be used,
18381 set_it_insn_type has to be called first.
18383 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18384 determines the insn IT type depending on the inst.cond code.
18385 When a tencode () routine encodes an instruction that can be
18386 either outside an IT block, or, in the case of being inside, has to be
18387 the last one, set_it_insn_type_last () will determine the proper
18388 IT instruction type based on the inst.cond code. Otherwise,
18389 set_it_insn_type can be called for overriding that logic or
18390 for covering other cases.
18392 Calling handle_it_state () may not transition the IT block state to
18393 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18394 still queried. Instead, if the FSM determines that the state should
18395 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18396 after the tencode () function: that's what it_fsm_post_encode () does.
18398 Since in_it_block () calls the state handling function to get an
18399 updated state, an error may occur (due to invalid insns combination).
18400 In that case, inst.error is set.
18401 Therefore, inst.error has to be checked after the execution of
18402 the tencode () routine.
18404 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18405 any pending state change (if any) that didn't take place in
18406 handle_it_state () as explained above. */
18409 it_fsm_pre_encode (void)
18411 if (inst
.cond
!= COND_ALWAYS
)
18412 inst
.it_insn_type
= INSIDE_IT_INSN
;
18414 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18416 now_it
.state_handled
= 0;
18419 /* IT state FSM handling function. */
18422 handle_it_state (void)
18424 now_it
.state_handled
= 1;
18425 now_it
.insn_cond
= FALSE
;
18427 switch (now_it
.state
)
18429 case OUTSIDE_IT_BLOCK
:
18430 switch (inst
.it_insn_type
)
18432 case OUTSIDE_IT_INSN
:
18435 case INSIDE_IT_INSN
:
18436 case INSIDE_IT_LAST_INSN
:
18437 if (thumb_mode
== 0)
18440 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18441 as_tsktsk (_("Warning: conditional outside an IT block"\
18446 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18447 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18449 /* Automatically generate the IT instruction. */
18450 new_automatic_it_block (inst
.cond
);
18451 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18452 close_automatic_it_block ();
18456 inst
.error
= BAD_OUT_IT
;
18462 case IF_INSIDE_IT_LAST_INSN
:
18463 case NEUTRAL_IT_INSN
:
18467 now_it
.state
= MANUAL_IT_BLOCK
;
18468 now_it
.block_length
= 0;
18473 case AUTOMATIC_IT_BLOCK
:
18474 /* Three things may happen now:
18475 a) We should increment current it block size;
18476 b) We should close current it block (closing insn or 4 insns);
18477 c) We should close current it block and start a new one (due
18478 to incompatible conditions or
18479 4 insns-length block reached). */
18481 switch (inst
.it_insn_type
)
18483 case OUTSIDE_IT_INSN
:
18484 /* The closure of the block shall happen immediately,
18485 so any in_it_block () call reports the block as closed. */
18486 force_automatic_it_block_close ();
18489 case INSIDE_IT_INSN
:
18490 case INSIDE_IT_LAST_INSN
:
18491 case IF_INSIDE_IT_LAST_INSN
:
18492 now_it
.block_length
++;
18494 if (now_it
.block_length
> 4
18495 || !now_it_compatible (inst
.cond
))
18497 force_automatic_it_block_close ();
18498 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18499 new_automatic_it_block (inst
.cond
);
18503 now_it
.insn_cond
= TRUE
;
18504 now_it_add_mask (inst
.cond
);
18507 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18508 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18509 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18510 close_automatic_it_block ();
18513 case NEUTRAL_IT_INSN
:
18514 now_it
.block_length
++;
18515 now_it
.insn_cond
= TRUE
;
18517 if (now_it
.block_length
> 4)
18518 force_automatic_it_block_close ();
18520 now_it_add_mask (now_it
.cc
& 1);
18524 close_automatic_it_block ();
18525 now_it
.state
= MANUAL_IT_BLOCK
;
18530 case MANUAL_IT_BLOCK
:
18532 /* Check conditional suffixes. */
18533 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18536 now_it
.mask
&= 0x1f;
18537 is_last
= (now_it
.mask
== 0x10);
18538 now_it
.insn_cond
= TRUE
;
18540 switch (inst
.it_insn_type
)
18542 case OUTSIDE_IT_INSN
:
18543 inst
.error
= BAD_NOT_IT
;
18546 case INSIDE_IT_INSN
:
18547 if (cond
!= inst
.cond
)
18549 inst
.error
= BAD_IT_COND
;
18554 case INSIDE_IT_LAST_INSN
:
18555 case IF_INSIDE_IT_LAST_INSN
:
18556 if (cond
!= inst
.cond
)
18558 inst
.error
= BAD_IT_COND
;
18563 inst
.error
= BAD_BRANCH
;
18568 case NEUTRAL_IT_INSN
:
18569 /* The BKPT instruction is unconditional even in an IT block. */
18573 inst
.error
= BAD_IT_IT
;
18583 struct depr_insn_mask
18585 unsigned long pattern
;
18586 unsigned long mask
;
18587 const char* description
;
18590 /* List of 16-bit instruction patterns deprecated in an IT block in
18592 static const struct depr_insn_mask depr_it_insns
[] = {
18593 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18594 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18595 { 0xa000, 0xb800, N_("ADR") },
18596 { 0x4800, 0xf800, N_("Literal loads") },
18597 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18598 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18599 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18600 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18601 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18606 it_fsm_post_encode (void)
18610 if (!now_it
.state_handled
)
18611 handle_it_state ();
18613 if (now_it
.insn_cond
18614 && !now_it
.warn_deprecated
18615 && warn_on_deprecated
18616 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18617 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18619 if (inst
.instruction
>= 0x10000)
18621 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18622 "performance deprecated in ARMv8-A and ARMv8-R"));
18623 now_it
.warn_deprecated
= TRUE
;
18627 const struct depr_insn_mask
*p
= depr_it_insns
;
18629 while (p
->mask
!= 0)
18631 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18633 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18634 "instructions of the following class are "
18635 "performance deprecated in ARMv8-A and "
18636 "ARMv8-R: %s"), p
->description
);
18637 now_it
.warn_deprecated
= TRUE
;
18645 if (now_it
.block_length
> 1)
18647 as_tsktsk (_("IT blocks containing more than one conditional "
18648 "instruction are performance deprecated in ARMv8-A and "
18650 now_it
.warn_deprecated
= TRUE
;
18654 is_last
= (now_it
.mask
== 0x10);
18657 now_it
.state
= OUTSIDE_IT_BLOCK
;
18663 force_automatic_it_block_close (void)
18665 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18667 close_automatic_it_block ();
18668 now_it
.state
= OUTSIDE_IT_BLOCK
;
18676 if (!now_it
.state_handled
)
18677 handle_it_state ();
18679 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18682 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18683 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18684 here, hence the "known" in the function name. */
18687 known_t32_only_insn (const struct asm_opcode
*opcode
)
18689 /* Original Thumb-1 wide instruction. */
18690 if (opcode
->tencode
== do_t_blx
18691 || opcode
->tencode
== do_t_branch23
18692 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18693 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18696 /* Wide-only instruction added to ARMv8-M Baseline. */
18697 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18698 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18699 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18700 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18706 /* Whether wide instruction variant can be used if available for a valid OPCODE
18710 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18712 if (known_t32_only_insn (opcode
))
18715 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18716 of variant T3 of B.W is checked in do_t_branch. */
18717 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18718 && opcode
->tencode
== do_t_branch
)
18721 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18722 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18723 && opcode
->tencode
== do_t_mov_cmp
18724 /* Make sure CMP instruction is not affected. */
18725 && opcode
->aencode
== do_mov
)
18728 /* Wide instruction variants of all instructions with narrow *and* wide
18729 variants become available with ARMv6t2. Other opcodes are either
18730 narrow-only or wide-only and are thus available if OPCODE is valid. */
18731 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18734 /* OPCODE with narrow only instruction variant or wide variant not
18740 md_assemble (char *str
)
18743 const struct asm_opcode
* opcode
;
18745 /* Align the previous label if needed. */
18746 if (last_label_seen
!= NULL
)
18748 symbol_set_frag (last_label_seen
, frag_now
);
18749 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18750 S_SET_SEGMENT (last_label_seen
, now_seg
);
18753 memset (&inst
, '\0', sizeof (inst
));
18754 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18756 opcode
= opcode_lookup (&p
);
18759 /* It wasn't an instruction, but it might be a register alias of
18760 the form alias .req reg, or a Neon .dn/.qn directive. */
18761 if (! create_register_alias (str
, p
)
18762 && ! create_neon_reg_alias (str
, p
))
18763 as_bad (_("bad instruction `%s'"), str
);
18768 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18769 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18771 /* The value which unconditional instructions should have in place of the
18772 condition field. */
18773 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18777 arm_feature_set variant
;
18779 variant
= cpu_variant
;
18780 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18781 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18782 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18783 /* Check that this instruction is supported for this CPU. */
18784 if (!opcode
->tvariant
18785 || (thumb_mode
== 1
18786 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18788 if (opcode
->tencode
== do_t_swi
)
18789 as_bad (_("SVC is not permitted on this architecture"));
18791 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18794 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18795 && opcode
->tencode
!= do_t_branch
)
18797 as_bad (_("Thumb does not support conditional execution"));
18801 /* Two things are addressed here:
18802 1) Implicit require narrow instructions on Thumb-1.
18803 This avoids relaxation accidentally introducing Thumb-2
18805 2) Reject wide instructions in non Thumb-2 cores.
18807 Only instructions with narrow and wide variants need to be handled
18808 but selecting all non wide-only instructions is easier. */
18809 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18810 && !t32_insn_ok (variant
, opcode
))
18812 if (inst
.size_req
== 0)
18814 else if (inst
.size_req
== 4)
18816 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18817 as_bad (_("selected processor does not support 32bit wide "
18818 "variant of instruction `%s'"), str
);
18820 as_bad (_("selected processor does not support `%s' in "
18821 "Thumb-2 mode"), str
);
18826 inst
.instruction
= opcode
->tvalue
;
18828 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18830 /* Prepare the it_insn_type for those encodings that don't set
18832 it_fsm_pre_encode ();
18834 opcode
->tencode ();
18836 it_fsm_post_encode ();
18839 if (!(inst
.error
|| inst
.relax
))
18841 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18842 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18843 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18845 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18850 /* Something has gone badly wrong if we try to relax a fixed size
18852 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18854 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18855 *opcode
->tvariant
);
18856 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18857 set those bits when Thumb-2 32-bit instructions are seen. The impact
18858 of relaxable instructions will be considered later after we finish all
18860 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18861 variant
= arm_arch_none
;
18863 variant
= cpu_variant
;
18864 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18865 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18868 check_neon_suffixes
;
18872 mapping_state (MAP_THUMB
);
18875 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18879 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18880 is_bx
= (opcode
->aencode
== do_bx
);
18882 /* Check that this instruction is supported for this CPU. */
18883 if (!(is_bx
&& fix_v4bx
)
18884 && !(opcode
->avariant
&&
18885 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18887 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18892 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18896 inst
.instruction
= opcode
->avalue
;
18897 if (opcode
->tag
== OT_unconditionalF
)
18898 inst
.instruction
|= 0xFU
<< 28;
18900 inst
.instruction
|= inst
.cond
<< 28;
18901 inst
.size
= INSN_SIZE
;
18902 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18904 it_fsm_pre_encode ();
18905 opcode
->aencode ();
18906 it_fsm_post_encode ();
18908 /* Arm mode bx is marked as both v4T and v5 because it's still required
18909 on a hypothetical non-thumb v5 core. */
18911 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18913 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18914 *opcode
->avariant
);
18916 check_neon_suffixes
;
18920 mapping_state (MAP_ARM
);
18925 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18933 check_it_blocks_finished (void)
18938 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18939 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18940 == MANUAL_IT_BLOCK
)
18942 as_warn (_("section '%s' finished with an open IT block."),
18946 if (now_it
.state
== MANUAL_IT_BLOCK
)
18947 as_warn (_("file finished with an open IT block."));
18951 /* Various frobbings of labels and their addresses. */
18954 arm_start_line_hook (void)
18956 last_label_seen
= NULL
;
18960 arm_frob_label (symbolS
* sym
)
18962 last_label_seen
= sym
;
18964 ARM_SET_THUMB (sym
, thumb_mode
);
18966 #if defined OBJ_COFF || defined OBJ_ELF
18967 ARM_SET_INTERWORK (sym
, support_interwork
);
18970 force_automatic_it_block_close ();
18972 /* Note - do not allow local symbols (.Lxxx) to be labelled
18973 as Thumb functions. This is because these labels, whilst
18974 they exist inside Thumb code, are not the entry points for
18975 possible ARM->Thumb calls. Also, these labels can be used
18976 as part of a computed goto or switch statement. eg gcc
18977 can generate code that looks like this:
18979 ldr r2, [pc, .Laaa]
18989 The first instruction loads the address of the jump table.
18990 The second instruction converts a table index into a byte offset.
18991 The third instruction gets the jump address out of the table.
18992 The fourth instruction performs the jump.
18994 If the address stored at .Laaa is that of a symbol which has the
18995 Thumb_Func bit set, then the linker will arrange for this address
18996 to have the bottom bit set, which in turn would mean that the
18997 address computation performed by the third instruction would end
18998 up with the bottom bit set. Since the ARM is capable of unaligned
18999 word loads, the instruction would then load the incorrect address
19000 out of the jump table, and chaos would ensue. */
19001 if (label_is_thumb_function_name
19002 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19003 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19005 /* When the address of a Thumb function is taken the bottom
19006 bit of that address should be set. This will allow
19007 interworking between Arm and Thumb functions to work
19010 THUMB_SET_FUNC (sym
, 1);
19012 label_is_thumb_function_name
= FALSE
;
19015 dwarf2_emit_label (sym
);
19019 arm_data_in_code (void)
19021 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19023 *input_line_pointer
= '/';
19024 input_line_pointer
+= 5;
19025 *input_line_pointer
= 0;
19033 arm_canonicalize_symbol_name (char * name
)
19037 if (thumb_mode
&& (len
= strlen (name
)) > 5
19038 && streq (name
+ len
- 5, "/data"))
19039 *(name
+ len
- 5) = 0;
19044 /* Table of all register names defined by default. The user can
19045 define additional names with .req. Note that all register names
19046 should appear in both upper and lowercase variants. Some registers
19047 also have mixed-case names. */
19049 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19050 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19051 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19052 #define REGSET(p,t) \
19053 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19054 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19055 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19056 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19057 #define REGSETH(p,t) \
19058 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19059 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19060 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19061 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19062 #define REGSET2(p,t) \
19063 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19064 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19065 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19066 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19067 #define SPLRBANK(base,bank,t) \
19068 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19069 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19070 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19071 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19072 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19073 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19075 static const struct reg_entry reg_names
[] =
19077 /* ARM integer registers. */
19078 REGSET(r
, RN
), REGSET(R
, RN
),
19080 /* ATPCS synonyms. */
19081 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19082 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19083 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19085 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19086 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19087 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19089 /* Well-known aliases. */
19090 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19091 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19093 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19094 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19096 /* Coprocessor numbers. */
19097 REGSET(p
, CP
), REGSET(P
, CP
),
19099 /* Coprocessor register numbers. The "cr" variants are for backward
19101 REGSET(c
, CN
), REGSET(C
, CN
),
19102 REGSET(cr
, CN
), REGSET(CR
, CN
),
19104 /* ARM banked registers. */
19105 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19106 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19107 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19108 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19109 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19110 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19111 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19113 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19114 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19115 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19116 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19117 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19118 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19119 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19120 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19122 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19123 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19124 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19125 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19126 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19127 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19128 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19129 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19130 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19132 /* FPA registers. */
19133 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19134 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19136 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19137 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19139 /* VFP SP registers. */
19140 REGSET(s
,VFS
), REGSET(S
,VFS
),
19141 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19143 /* VFP DP Registers. */
19144 REGSET(d
,VFD
), REGSET(D
,VFD
),
19145 /* Extra Neon DP registers. */
19146 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19148 /* Neon QP registers. */
19149 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19151 /* VFP control registers. */
19152 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19153 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19154 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19155 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19156 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19157 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19158 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19160 /* Maverick DSP coprocessor registers. */
19161 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19162 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19164 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19165 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19166 REGDEF(dspsc
,0,DSPSC
),
19168 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19169 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19170 REGDEF(DSPSC
,0,DSPSC
),
19172 /* iWMMXt data registers - p0, c0-15. */
19173 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19175 /* iWMMXt control registers - p1, c0-3. */
19176 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19177 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19178 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19179 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19181 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19182 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19183 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19184 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19185 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19187 /* XScale accumulator registers. */
19188 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19194 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19195 within psr_required_here. */
19196 static const struct asm_psr psrs
[] =
19198 /* Backward compatibility notation. Note that "all" is no longer
19199 truly all possible PSR bits. */
19200 {"all", PSR_c
| PSR_f
},
19204 /* Individual flags. */
19210 /* Combinations of flags. */
19211 {"fs", PSR_f
| PSR_s
},
19212 {"fx", PSR_f
| PSR_x
},
19213 {"fc", PSR_f
| PSR_c
},
19214 {"sf", PSR_s
| PSR_f
},
19215 {"sx", PSR_s
| PSR_x
},
19216 {"sc", PSR_s
| PSR_c
},
19217 {"xf", PSR_x
| PSR_f
},
19218 {"xs", PSR_x
| PSR_s
},
19219 {"xc", PSR_x
| PSR_c
},
19220 {"cf", PSR_c
| PSR_f
},
19221 {"cs", PSR_c
| PSR_s
},
19222 {"cx", PSR_c
| PSR_x
},
19223 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19224 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19225 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19226 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19227 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19228 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19229 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19230 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19231 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19232 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19233 {"scf", PSR_s
| PSR_c
| PSR_f
},
19234 {"scx", PSR_s
| PSR_c
| PSR_x
},
19235 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19236 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19237 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19238 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19239 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19240 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19241 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19242 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19243 {"csf", PSR_c
| PSR_s
| PSR_f
},
19244 {"csx", PSR_c
| PSR_s
| PSR_x
},
19245 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19246 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19247 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19248 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19249 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19250 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19251 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19252 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19253 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19254 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19255 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19256 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19257 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19258 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19259 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19260 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19261 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19262 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19263 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19264 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19265 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19266 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19267 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19268 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19269 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19270 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19273 /* Table of V7M psr names. */
19274 static const struct asm_psr v7m_psrs
[] =
19276 {"apsr", 0x0 }, {"APSR", 0x0 },
19277 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19278 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19279 {"psr", 0x3 }, {"PSR", 0x3 },
19280 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19281 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19282 {"epsr", 0x6 }, {"EPSR", 0x6 },
19283 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19284 {"msp", 0x8 }, {"MSP", 0x8 },
19285 {"psp", 0x9 }, {"PSP", 0x9 },
19286 {"msplim", 0xa }, {"MSPLIM", 0xa },
19287 {"psplim", 0xb }, {"PSPLIM", 0xb },
19288 {"primask", 0x10}, {"PRIMASK", 0x10},
19289 {"basepri", 0x11}, {"BASEPRI", 0x11},
19290 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19291 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19292 {"control", 0x14}, {"CONTROL", 0x14},
19293 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19294 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19295 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19296 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19297 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19298 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19299 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19300 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19301 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19304 /* Table of all shift-in-operand names. */
19305 static const struct asm_shift_name shift_names
[] =
19307 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19308 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19309 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19310 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19311 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19312 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19315 /* Table of all explicit relocation names. */
19317 static struct reloc_entry reloc_names
[] =
19319 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19320 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19321 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19322 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19323 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19324 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19325 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19326 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19327 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19328 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19329 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19330 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19331 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19332 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19333 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19334 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19335 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19336 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19337 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19338 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19339 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19340 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19341 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19342 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19343 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19344 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19345 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19349 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19350 static const struct asm_cond conds
[] =
19354 {"cs", 0x2}, {"hs", 0x2},
19355 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19369 #define UL_BARRIER(L,U,CODE,FEAT) \
19370 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19371 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19373 static struct asm_barrier_opt barrier_opt_names
[] =
19375 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19376 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19377 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19378 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19379 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19380 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19381 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19382 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19383 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19384 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19385 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19386 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19387 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19388 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19389 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19390 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19395 /* Table of ARM-format instructions. */
19397 /* Macros for gluing together operand strings. N.B. In all cases
19398 other than OPS0, the trailing OP_stop comes from default
19399 zero-initialization of the unspecified elements of the array. */
19400 #define OPS0() { OP_stop, }
19401 #define OPS1(a) { OP_##a, }
19402 #define OPS2(a,b) { OP_##a,OP_##b, }
19403 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19404 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19405 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19406 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19408 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19409 This is useful when mixing operands for ARM and THUMB, i.e. using the
19410 MIX_ARM_THUMB_OPERANDS macro.
19411 In order to use these macros, prefix the number of operands with _
19413 #define OPS_1(a) { a, }
19414 #define OPS_2(a,b) { a,b, }
19415 #define OPS_3(a,b,c) { a,b,c, }
19416 #define OPS_4(a,b,c,d) { a,b,c,d, }
19417 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19418 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19420 /* These macros abstract out the exact format of the mnemonic table and
19421 save some repeated characters. */
19423 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19424 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19425 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19426 THUMB_VARIANT, do_##ae, do_##te }
19428 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19429 a T_MNEM_xyz enumerator. */
19430 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19431 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19432 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19433 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19435 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19436 infix after the third character. */
19437 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19438 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19439 THUMB_VARIANT, do_##ae, do_##te }
19440 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19441 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19442 THUMB_VARIANT, do_##ae, do_##te }
19443 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19444 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19445 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19446 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19447 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19448 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19449 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19450 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19452 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19453 field is still 0xE. Many of the Thumb variants can be executed
19454 conditionally, so this is checked separately. */
19455 #define TUE(mnem, op, top, nops, ops, ae, te) \
19456 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19457 THUMB_VARIANT, do_##ae, do_##te }
19459 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19460 Used by mnemonics that have very minimal differences in the encoding for
19461 ARM and Thumb variants and can be handled in a common function. */
19462 #define TUEc(mnem, op, top, nops, ops, en) \
19463 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19464 THUMB_VARIANT, do_##en, do_##en }
19466 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19467 condition code field. */
19468 #define TUF(mnem, op, top, nops, ops, ae, te) \
19469 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19470 THUMB_VARIANT, do_##ae, do_##te }
19472 /* ARM-only variants of all the above. */
19473 #define CE(mnem, op, nops, ops, ae) \
19474 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19476 #define C3(mnem, op, nops, ops, ae) \
19477 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19479 /* Thumb-only variants of TCE and TUE. */
19480 #define ToC(mnem, top, nops, ops, te) \
19481 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19484 #define ToU(mnem, top, nops, ops, te) \
19485 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19488 /* Legacy mnemonics that always have conditional infix after the third
19490 #define CL(mnem, op, nops, ops, ae) \
19491 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19492 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19494 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19495 #define cCE(mnem, op, nops, ops, ae) \
19496 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19498 /* Legacy coprocessor instructions where conditional infix and conditional
19499 suffix are ambiguous. For consistency this includes all FPA instructions,
19500 not just the potentially ambiguous ones. */
19501 #define cCL(mnem, op, nops, ops, ae) \
19502 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19503 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19505 /* Coprocessor, takes either a suffix or a position-3 infix
19506 (for an FPA corner case). */
19507 #define C3E(mnem, op, nops, ops, ae) \
19508 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19509 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19511 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19512 { m1 #m2 m3, OPS##nops ops, \
19513 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19514 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19516 #define CM(m1, m2, op, nops, ops, ae) \
19517 xCM_ (m1, , m2, op, nops, ops, ae), \
19518 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19519 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19520 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19521 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19522 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19523 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19524 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19525 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19526 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19527 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19528 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19529 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19530 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19531 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19532 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19533 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19534 xCM_ (m1, le, m2, op, nops, ops, ae), \
19535 xCM_ (m1, al, m2, op, nops, ops, ae)
19537 #define UE(mnem, op, nops, ops, ae) \
19538 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19540 #define UF(mnem, op, nops, ops, ae) \
19541 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19543 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19544 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19545 use the same encoding function for each. */
19546 #define NUF(mnem, op, nops, ops, enc) \
19547 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19548 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19550 /* Neon data processing, version which indirects through neon_enc_tab for
19551 the various overloaded versions of opcodes. */
19552 #define nUF(mnem, op, nops, ops, enc) \
19553 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19554 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19556 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19558 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19559 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19560 THUMB_VARIANT, do_##enc, do_##enc }
19562 #define NCE(mnem, op, nops, ops, enc) \
19563 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19565 #define NCEF(mnem, op, nops, ops, enc) \
19566 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19568 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19569 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19570 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19571 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19573 #define nCE(mnem, op, nops, ops, enc) \
19574 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19576 #define nCEF(mnem, op, nops, ops, enc) \
19577 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19581 static const struct asm_opcode insns
[] =
19583 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19584 #define THUMB_VARIANT & arm_ext_v4t
19585 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19586 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19587 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19588 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19589 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19590 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19591 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19592 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19593 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19594 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19595 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19596 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19597 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19598 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19599 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19600 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19602 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19603 for setting PSR flag bits. They are obsolete in V6 and do not
19604 have Thumb equivalents. */
19605 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19606 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19607 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19608 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19609 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19610 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19611 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19612 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19613 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19615 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19616 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19617 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19618 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19620 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19621 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19622 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19624 OP_ADDRGLDR
),ldst
, t_ldst
),
19625 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19627 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19628 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19629 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19630 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19631 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19632 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19634 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19635 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19638 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19639 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19640 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19641 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19643 /* Thumb-compatibility pseudo ops. */
19644 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19645 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19646 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19647 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19648 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19649 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19650 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19651 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19652 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19653 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19654 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19655 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19657 /* These may simplify to neg. */
19658 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19659 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19661 #undef THUMB_VARIANT
19662 #define THUMB_VARIANT & arm_ext_os
19664 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19665 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19667 #undef THUMB_VARIANT
19668 #define THUMB_VARIANT & arm_ext_v6
19670 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19672 /* V1 instructions with no Thumb analogue prior to V6T2. */
19673 #undef THUMB_VARIANT
19674 #define THUMB_VARIANT & arm_ext_v6t2
19676 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19677 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19678 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19680 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19681 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19682 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19683 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19685 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19686 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19688 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19689 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19691 /* V1 instructions with no Thumb analogue at all. */
19692 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19693 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19695 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19696 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19697 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19698 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19699 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19700 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19701 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19702 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19705 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19706 #undef THUMB_VARIANT
19707 #define THUMB_VARIANT & arm_ext_v4t
19709 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19710 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19712 #undef THUMB_VARIANT
19713 #define THUMB_VARIANT & arm_ext_v6t2
19715 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19716 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19718 /* Generic coprocessor instructions. */
19719 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19720 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19721 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19722 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19723 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19724 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19725 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19728 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19730 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19731 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19734 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19735 #undef THUMB_VARIANT
19736 #define THUMB_VARIANT & arm_ext_msr
19738 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19739 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19742 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19743 #undef THUMB_VARIANT
19744 #define THUMB_VARIANT & arm_ext_v6t2
19746 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19747 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19748 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19749 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19750 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19751 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19752 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19753 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19756 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19757 #undef THUMB_VARIANT
19758 #define THUMB_VARIANT & arm_ext_v4t
19760 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19761 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19762 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19763 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19764 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19765 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19768 #define ARM_VARIANT & arm_ext_v4t_5
19770 /* ARM Architecture 4T. */
19771 /* Note: bx (and blx) are required on V5, even if the processor does
19772 not support Thumb. */
19773 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19776 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_v5t
19780 /* Note: blx has 2 variants; the .value coded here is for
19781 BLX(2). Only this variant has conditional execution. */
19782 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19783 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19785 #undef THUMB_VARIANT
19786 #define THUMB_VARIANT & arm_ext_v6t2
19788 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19789 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19790 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19791 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19792 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19793 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19794 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19795 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19798 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19799 #undef THUMB_VARIANT
19800 #define THUMB_VARIANT & arm_ext_v5exp
19802 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19803 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19804 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19805 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19807 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19808 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19810 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19811 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19812 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19813 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19815 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19816 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19817 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19818 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19820 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19821 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19823 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19824 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19825 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19826 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19829 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19830 #undef THUMB_VARIANT
19831 #define THUMB_VARIANT & arm_ext_v6t2
19833 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19834 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19836 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19837 ADDRGLDRS
), ldrd
, t_ldstd
),
19839 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19840 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19843 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19845 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19848 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19849 #undef THUMB_VARIANT
19850 #define THUMB_VARIANT & arm_ext_v6
19852 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19853 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19854 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19855 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19856 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19857 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19858 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19859 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19860 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19861 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19863 #undef THUMB_VARIANT
19864 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19866 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19867 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19869 #undef THUMB_VARIANT
19870 #define THUMB_VARIANT & arm_ext_v6t2
19872 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19873 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19875 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19876 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19878 /* ARM V6 not included in V7M. */
19879 #undef THUMB_VARIANT
19880 #define THUMB_VARIANT & arm_ext_v6_notm
19881 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19882 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19883 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19884 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19885 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19886 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19887 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19888 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19889 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19890 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19891 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19892 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19893 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19894 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19895 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19896 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19897 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19898 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19899 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19901 /* ARM V6 not included in V7M (eg. integer SIMD). */
19902 #undef THUMB_VARIANT
19903 #define THUMB_VARIANT & arm_ext_v6_dsp
19904 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19905 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19906 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19907 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19908 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19909 /* Old name for QASX. */
19910 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19911 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19912 /* Old name for QSAX. */
19913 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19914 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19915 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19916 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19917 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19918 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19919 /* Old name for SASX. */
19920 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19921 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19922 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19923 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19924 /* Old name for SHASX. */
19925 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19926 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19927 /* Old name for SHSAX. */
19928 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19929 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19930 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19931 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19932 /* Old name for SSAX. */
19933 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19934 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19935 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19936 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19937 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19938 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19939 /* Old name for UASX. */
19940 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19941 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19942 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19943 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19944 /* Old name for UHASX. */
19945 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19946 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19947 /* Old name for UHSAX. */
19948 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19949 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19950 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19951 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19952 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19953 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19954 /* Old name for UQASX. */
19955 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19956 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19957 /* Old name for UQSAX. */
19958 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19959 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19960 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19961 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19962 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19963 /* Old name for USAX. */
19964 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19965 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19966 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19967 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19968 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19969 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19970 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19971 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19972 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19973 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19974 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19975 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19976 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19977 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19978 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19979 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19980 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19981 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19982 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19983 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19984 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19985 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19986 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19987 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19988 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19989 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19990 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19991 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19992 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19993 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19994 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19995 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19996 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19997 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
20000 #define ARM_VARIANT & arm_ext_v6k_v6t2
20001 #undef THUMB_VARIANT
20002 #define THUMB_VARIANT & arm_ext_v6k_v6t2
20004 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
20005 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
20006 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
20007 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20009 #undef THUMB_VARIANT
20010 #define THUMB_VARIANT & arm_ext_v6_notm
20011 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20013 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20014 RRnpcb
), strexd
, t_strexd
),
20016 #undef THUMB_VARIANT
20017 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20018 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20020 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20022 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20024 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20026 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20029 #define ARM_VARIANT & arm_ext_sec
20030 #undef THUMB_VARIANT
20031 #define THUMB_VARIANT & arm_ext_sec
20033 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20036 #define ARM_VARIANT & arm_ext_virt
20037 #undef THUMB_VARIANT
20038 #define THUMB_VARIANT & arm_ext_virt
20040 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20041 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20044 #define ARM_VARIANT & arm_ext_pan
20045 #undef THUMB_VARIANT
20046 #define THUMB_VARIANT & arm_ext_pan
20048 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20051 #define ARM_VARIANT & arm_ext_v6t2
20052 #undef THUMB_VARIANT
20053 #define THUMB_VARIANT & arm_ext_v6t2
20055 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20056 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20057 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20058 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20060 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20061 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20063 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20064 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20065 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20066 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20069 #define ARM_VARIANT & arm_ext_v3
20070 #undef THUMB_VARIANT
20071 #define THUMB_VARIANT & arm_ext_v6t2
20073 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20074 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20075 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20078 #define ARM_VARIANT & arm_ext_v6t2
20079 #undef THUMB_VARIANT
20080 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20081 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20082 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20084 /* Thumb-only instructions. */
20086 #define ARM_VARIANT NULL
20087 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20088 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20090 /* ARM does not really have an IT instruction, so always allow it.
20091 The opcode is copied from Thumb in order to allow warnings in
20092 -mimplicit-it=[never | arm] modes. */
20094 #define ARM_VARIANT & arm_ext_v1
20095 #undef THUMB_VARIANT
20096 #define THUMB_VARIANT & arm_ext_v6t2
20098 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20099 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20100 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20101 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20102 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20103 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20104 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20105 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20106 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20107 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20108 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20109 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20110 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20111 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20112 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20113 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20114 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20115 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20117 /* Thumb2 only instructions. */
20119 #define ARM_VARIANT NULL
20121 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20122 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20123 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20124 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20125 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20126 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20128 /* Hardware division instructions. */
20130 #define ARM_VARIANT & arm_ext_adiv
20131 #undef THUMB_VARIANT
20132 #define THUMB_VARIANT & arm_ext_div
20134 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20135 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20137 /* ARM V6M/V7 instructions. */
20139 #define ARM_VARIANT & arm_ext_barrier
20140 #undef THUMB_VARIANT
20141 #define THUMB_VARIANT & arm_ext_barrier
20143 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20144 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20145 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20147 /* ARM V7 instructions. */
20149 #define ARM_VARIANT & arm_ext_v7
20150 #undef THUMB_VARIANT
20151 #define THUMB_VARIANT & arm_ext_v7
20153 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20154 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20157 #define ARM_VARIANT & arm_ext_mp
20158 #undef THUMB_VARIANT
20159 #define THUMB_VARIANT & arm_ext_mp
20161 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20163 /* AArchv8 instructions. */
20165 #define ARM_VARIANT & arm_ext_v8
20167 /* Instructions shared between armv8-a and armv8-m. */
20168 #undef THUMB_VARIANT
20169 #define THUMB_VARIANT & arm_ext_atomics
20171 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20172 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20173 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20174 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20175 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20176 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20177 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20178 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20179 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20180 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20182 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20184 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20186 #undef THUMB_VARIANT
20187 #define THUMB_VARIANT & arm_ext_v8
20189 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20190 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20192 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20195 /* Defined in V8 but is in undefined encoding space for earlier
20196 architectures. However earlier architectures are required to treat
20197 this instuction as a semihosting trap as well. Hence while not explicitly
20198 defined as such, it is in fact correct to define the instruction for all
20200 #undef THUMB_VARIANT
20201 #define THUMB_VARIANT & arm_ext_v1
20203 #define ARM_VARIANT & arm_ext_v1
20204 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20206 /* ARMv8 T32 only. */
20208 #define ARM_VARIANT NULL
20209 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20210 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20211 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20213 /* FP for ARMv8. */
20215 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20216 #undef THUMB_VARIANT
20217 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20219 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20220 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20221 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20222 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20223 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20224 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20225 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20226 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20227 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20228 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20229 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20230 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20231 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20232 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20233 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20234 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20235 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20237 /* Crypto v1 extensions. */
20239 #define ARM_VARIANT & fpu_crypto_ext_armv8
20240 #undef THUMB_VARIANT
20241 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20243 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20244 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20245 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20246 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20247 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20248 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20249 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20250 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20251 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20252 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20253 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20254 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20255 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20256 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20259 #define ARM_VARIANT & crc_ext_armv8
20260 #undef THUMB_VARIANT
20261 #define THUMB_VARIANT & crc_ext_armv8
20262 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20263 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20264 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20265 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20266 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20267 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20269 /* ARMv8.2 RAS extension. */
20271 #define ARM_VARIANT & arm_ext_ras
20272 #undef THUMB_VARIANT
20273 #define THUMB_VARIANT & arm_ext_ras
20274 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20277 #define ARM_VARIANT & arm_ext_v8_3
20278 #undef THUMB_VARIANT
20279 #define THUMB_VARIANT & arm_ext_v8_3
20280 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20281 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20282 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20285 #define ARM_VARIANT & fpu_neon_ext_dotprod
20286 #undef THUMB_VARIANT
20287 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20288 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20289 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20292 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20293 #undef THUMB_VARIANT
20294 #define THUMB_VARIANT NULL
20296 cCE("wfs", e200110
, 1, (RR
), rd
),
20297 cCE("rfs", e300110
, 1, (RR
), rd
),
20298 cCE("wfc", e400110
, 1, (RR
), rd
),
20299 cCE("rfc", e500110
, 1, (RR
), rd
),
20301 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20302 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20303 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20304 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20306 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20307 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20308 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20309 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20311 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20314 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20316 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20319 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20324 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20327 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20329 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20337 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20340 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20350 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20353 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20363 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20366 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20376 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20379 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20389 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20392 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20402 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20405 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20407 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20408 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20410 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20412 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20413 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20415 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20416 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20417 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20418 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20419 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20420 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20421 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20422 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20423 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20424 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20425 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20426 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20428 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20429 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20430 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20431 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20432 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20433 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20434 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20435 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20436 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20437 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20438 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20439 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20441 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20442 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20443 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20444 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20445 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20446 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20447 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20448 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20449 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20450 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20451 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20452 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20454 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20455 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20456 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20457 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20458 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20459 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20460 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20461 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20462 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20463 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20464 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20465 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20467 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20468 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20469 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20470 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20471 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20472 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20473 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20474 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20475 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20476 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20477 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20478 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20480 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20481 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20482 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20483 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20484 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20485 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20486 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20487 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20488 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20489 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20490 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20491 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20493 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20494 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20495 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20496 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20497 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20498 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20499 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20500 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20501 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20502 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20503 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20504 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20506 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20507 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20508 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20509 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20510 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20511 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20512 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20513 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20514 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20515 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20516 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20517 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20519 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20522 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20524 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20527 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20532 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20535 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20537 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20545 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20548 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20558 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20561 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20571 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20574 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20576 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20577 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20579 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20581 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20582 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20584 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20585 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20586 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20587 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20588 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20589 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20590 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20591 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20592 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20593 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20594 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20595 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20597 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20598 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20599 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20600 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20601 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20602 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20603 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20604 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20605 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20606 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20607 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20608 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20610 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20611 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20612 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20613 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20614 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20615 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20616 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20617 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20618 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20619 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20620 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20621 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20623 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20624 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20625 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20626 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20627 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20628 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20629 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20630 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20631 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20632 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20633 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20634 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20636 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20637 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20638 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20639 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20640 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20641 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20642 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20643 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20644 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20645 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20646 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20647 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20649 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20650 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20651 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20652 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20653 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20654 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20655 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20656 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20657 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20658 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20659 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20660 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20662 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20663 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20664 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20665 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20666 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20667 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20668 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20669 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20670 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20671 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20672 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20673 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20675 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20676 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20677 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20678 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20679 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20680 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20681 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20682 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20683 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20684 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20685 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20686 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20688 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20689 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20690 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20691 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20693 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20694 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20695 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20696 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20697 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20698 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20699 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20700 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20701 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20702 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20703 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20704 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20706 /* The implementation of the FIX instruction is broken on some
20707 assemblers, in that it accepts a precision specifier as well as a
20708 rounding specifier, despite the fact that this is meaningless.
20709 To be more compatible, we accept it as well, though of course it
20710 does not set any bits. */
20711 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20712 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20713 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20714 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20715 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20716 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20717 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20718 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20719 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20720 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20721 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20722 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20723 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20725 /* Instructions that were new with the real FPA, call them V2. */
20727 #define ARM_VARIANT & fpu_fpa_ext_v2
20729 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20730 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20731 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20732 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20733 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20734 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20737 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20739 /* Moves and type conversions. */
20740 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20741 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20742 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20743 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20744 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20745 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20746 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20747 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20748 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20749 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20750 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20751 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20752 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20753 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20755 /* Memory operations. */
20756 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20757 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20758 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20759 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20760 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20761 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20762 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20763 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20764 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20765 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20766 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20767 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20768 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20769 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20770 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20771 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20772 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20773 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20775 /* Monadic operations. */
20776 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20777 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20778 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20780 /* Dyadic operations. */
20781 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20782 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20783 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20784 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20785 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20786 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20787 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20788 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20789 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20792 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20793 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20794 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20795 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20797 /* Double precision load/store are still present on single precision
20798 implementations. */
20799 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20800 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20801 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20802 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20803 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20804 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20805 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20806 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20807 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20808 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20811 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20813 /* Moves and type conversions. */
20814 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20815 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20816 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20817 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20818 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20819 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20820 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20821 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20822 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20823 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20824 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20825 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20826 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20828 /* Monadic operations. */
20829 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20830 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20831 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20833 /* Dyadic operations. */
20834 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20835 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20836 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20837 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20838 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20839 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20840 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20841 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20842 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20845 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20846 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20847 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20848 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20851 #define ARM_VARIANT & fpu_vfp_ext_v2
20853 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20854 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20855 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20856 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20858 /* Instructions which may belong to either the Neon or VFP instruction sets.
20859 Individual encoder functions perform additional architecture checks. */
20861 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20862 #undef THUMB_VARIANT
20863 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20865 /* These mnemonics are unique to VFP. */
20866 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20867 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20868 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20869 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20870 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20871 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20872 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20873 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20874 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20875 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20877 /* Mnemonics shared by Neon and VFP. */
20878 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20879 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20880 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20882 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20883 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20885 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20886 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20888 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20889 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20890 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20891 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20892 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20893 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20894 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20895 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20897 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20898 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20899 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20900 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20903 /* NOTE: All VMOV encoding is special-cased! */
20904 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20905 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20908 #define ARM_VARIANT & arm_ext_fp16
20909 #undef THUMB_VARIANT
20910 #define THUMB_VARIANT & arm_ext_fp16
20911 /* New instructions added from v8.2, allowing the extraction and insertion of
20912 the upper 16 bits of a 32-bit vector register. */
20913 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20914 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20916 /* New backported fma/fms instructions optional in v8.2. */
20917 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20918 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20920 #undef THUMB_VARIANT
20921 #define THUMB_VARIANT & fpu_neon_ext_v1
20923 #define ARM_VARIANT & fpu_neon_ext_v1
20925 /* Data processing with three registers of the same length. */
20926 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20927 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20928 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20929 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20930 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20931 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20932 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20933 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20934 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20935 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20936 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20937 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20938 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20939 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20940 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20941 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20942 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20943 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20944 /* If not immediate, fall back to neon_dyadic_i64_su.
20945 shl_imm should accept I8 I16 I32 I64,
20946 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20947 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20948 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20949 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20950 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20951 /* Logic ops, types optional & ignored. */
20952 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20953 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20954 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20955 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20956 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20957 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20958 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20959 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20960 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20961 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20962 /* Bitfield ops, untyped. */
20963 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20964 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20965 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20966 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20967 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20968 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20969 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20970 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20971 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20972 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20973 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20974 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20975 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20976 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20977 back to neon_dyadic_if_su. */
20978 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20979 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20980 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20981 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20982 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20983 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20984 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20985 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20986 /* Comparison. Type I8 I16 I32 F32. */
20987 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20988 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20989 /* As above, D registers only. */
20990 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20991 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20992 /* Int and float variants, signedness unimportant. */
20993 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20994 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20995 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20996 /* Add/sub take types I8 I16 I32 I64 F32. */
20997 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20998 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20999 /* vtst takes sizes 8, 16, 32. */
21000 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
21001 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
21002 /* VMUL takes I8 I16 I32 F32 P8. */
21003 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
21004 /* VQD{R}MULH takes S16 S32. */
21005 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21006 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21007 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21008 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21009 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21010 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21011 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21012 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21013 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21014 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21015 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21016 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21017 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21018 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21019 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21020 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21021 /* ARM v8.1 extension. */
21022 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21023 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21024 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21025 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21027 /* Two address, int/float. Types S8 S16 S32 F32. */
21028 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21029 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21031 /* Data processing with two registers and a shift amount. */
21032 /* Right shifts, and variants with rounding.
21033 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21034 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21035 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21036 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21037 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21038 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21039 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21040 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21041 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21042 /* Shift and insert. Sizes accepted 8 16 32 64. */
21043 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21044 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21045 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21046 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21047 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21048 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21049 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21050 /* Right shift immediate, saturating & narrowing, with rounding variants.
21051 Types accepted S16 S32 S64 U16 U32 U64. */
21052 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21053 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21054 /* As above, unsigned. Types accepted S16 S32 S64. */
21055 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21056 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21057 /* Right shift narrowing. Types accepted I16 I32 I64. */
21058 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21059 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21060 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21061 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21062 /* CVT with optional immediate for fixed-point variant. */
21063 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21065 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21066 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21068 /* Data processing, three registers of different lengths. */
21069 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21070 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21071 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21072 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21073 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21074 /* If not scalar, fall back to neon_dyadic_long.
21075 Vector types as above, scalar types S16 S32 U16 U32. */
21076 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21077 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21078 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21079 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21080 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21081 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21082 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21083 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21084 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21085 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21086 /* Saturating doubling multiplies. Types S16 S32. */
21087 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21088 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21089 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21090 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21091 S16 S32 U16 U32. */
21092 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21094 /* Extract. Size 8. */
21095 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21096 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21098 /* Two registers, miscellaneous. */
21099 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21100 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21101 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21102 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21103 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21104 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21105 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21106 /* Vector replicate. Sizes 8 16 32. */
21107 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21108 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21109 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21110 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21111 /* VMOVN. Types I16 I32 I64. */
21112 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21113 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21114 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21115 /* VQMOVUN. Types S16 S32 S64. */
21116 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21117 /* VZIP / VUZP. Sizes 8 16 32. */
21118 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21119 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21120 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21121 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21122 /* VQABS / VQNEG. Types S8 S16 S32. */
21123 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21124 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21125 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21126 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21127 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21128 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21129 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21130 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21131 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21132 /* Reciprocal estimates. Types U32 F16 F32. */
21133 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21134 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21135 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21136 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21137 /* VCLS. Types S8 S16 S32. */
21138 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21139 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21140 /* VCLZ. Types I8 I16 I32. */
21141 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21142 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21143 /* VCNT. Size 8. */
21144 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21145 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21146 /* Two address, untyped. */
21147 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21148 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21149 /* VTRN. Sizes 8 16 32. */
21150 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21151 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21153 /* Table lookup. Size 8. */
21154 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21155 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21157 #undef THUMB_VARIANT
21158 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21160 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21162 /* Neon element/structure load/store. */
21163 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21164 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21165 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21166 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21167 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21168 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21169 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21170 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21172 #undef THUMB_VARIANT
21173 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21175 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21176 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21177 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21178 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21179 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21180 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21181 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21182 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21183 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21184 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21186 #undef THUMB_VARIANT
21187 #define THUMB_VARIANT & fpu_vfp_ext_v3
21189 #define ARM_VARIANT & fpu_vfp_ext_v3
21191 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21192 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21193 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21194 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21195 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21196 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21197 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21198 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21199 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21202 #define ARM_VARIANT & fpu_vfp_ext_fma
21203 #undef THUMB_VARIANT
21204 #define THUMB_VARIANT & fpu_vfp_ext_fma
21205 /* Mnemonics shared by Neon and VFP. These are included in the
21206 VFP FMA variant; NEON and VFP FMA always includes the NEON
21207 FMA instructions. */
21208 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21209 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21210 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21211 the v form should always be used. */
21212 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21213 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21214 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21215 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21216 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21217 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21219 #undef THUMB_VARIANT
21221 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21223 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21224 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21225 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21226 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21227 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21228 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21229 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21230 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21233 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21235 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21236 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21237 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21238 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21239 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21240 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21241 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21242 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21243 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21244 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21245 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21246 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21247 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21248 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21249 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21250 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21251 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21252 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21253 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21254 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21255 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21256 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21257 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21258 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21259 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21260 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21261 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21262 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21263 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21264 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21265 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21266 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21267 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21268 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21269 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21270 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21271 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21272 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21273 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21274 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21275 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21276 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21277 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21278 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21279 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21280 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21281 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21282 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21283 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21284 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21285 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21286 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21287 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21288 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21289 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21290 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21291 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21292 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21293 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21294 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21295 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21296 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21297 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21298 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21299 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21300 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21301 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21302 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21303 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21304 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21305 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21309 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21311 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21312 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21313 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21314 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21315 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21316 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21317 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21318 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21319 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21320 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21321 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21322 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21323 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21324 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21325 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21326 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21327 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21328 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21329 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21330 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21331 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21332 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21333 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21336 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21337 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21338 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21339 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21340 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21341 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21342 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21343 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21344 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21345 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21346 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21347 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21348 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21349 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21350 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21351 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21352 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21353 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21354 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21355 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21356 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21357 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21358 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21359 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21360 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21361 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21362 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21363 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21364 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21365 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21366 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21367 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21368 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21369 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21370 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21371 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21372 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21373 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21374 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21375 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21376 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21377 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21378 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21379 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21380 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21381 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21382 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21383 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21384 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21385 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21386 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21387 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21388 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21389 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21390 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21391 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21392 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21393 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21394 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21395 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21396 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21399 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21401 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21402 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21403 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21404 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21405 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21406 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21407 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21408 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21409 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21410 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21411 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21412 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21413 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21414 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21415 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21416 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21417 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21418 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21419 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21420 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21421 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21422 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21423 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21424 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21425 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21426 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21427 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21428 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21429 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21430 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21431 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21432 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21433 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21434 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21435 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21436 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21437 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21438 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21439 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21440 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21441 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21442 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21443 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21444 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21445 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21446 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21447 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21448 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21449 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21450 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21451 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21452 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21453 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21454 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21455 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21456 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21457 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21460 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21462 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21463 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21464 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21465 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21466 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21467 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21468 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21469 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21470 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21471 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21472 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21473 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21474 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21475 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21476 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21477 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21478 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21479 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21480 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21481 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21482 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21483 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21484 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21485 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21486 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21487 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21488 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21489 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21490 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21491 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21492 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21493 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21494 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21495 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21496 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21497 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21498 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21499 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21500 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21501 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21502 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21503 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21504 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21505 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21506 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21507 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21508 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21509 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21510 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21511 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21512 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21513 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21514 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21515 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21516 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21517 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21518 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21519 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21520 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21521 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21522 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21523 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21524 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21525 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21526 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21527 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21528 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21529 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21530 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21531 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21532 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21533 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21534 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21535 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21536 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21537 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21539 /* ARMv8.5-A instructions. */
21541 #define ARM_VARIANT & arm_ext_sb
21542 #undef THUMB_VARIANT
21543 #define THUMB_VARIANT & arm_ext_sb
21544 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
21547 #define ARM_VARIANT & arm_ext_predres
21548 #undef THUMB_VARIANT
21549 #define THUMB_VARIANT & arm_ext_predres
21550 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
21551 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
21552 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
21554 /* ARMv8-M instructions. */
21556 #define ARM_VARIANT NULL
21557 #undef THUMB_VARIANT
21558 #define THUMB_VARIANT & arm_ext_v8m
21559 ToU("sg", e97fe97f
, 0, (), noargs
),
21560 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21561 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21562 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21563 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21564 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21565 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21567 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21568 instructions behave as nop if no VFP is present. */
21569 #undef THUMB_VARIANT
21570 #define THUMB_VARIANT & arm_ext_v8m_main
21571 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21572 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21575 #undef THUMB_VARIANT
21601 /* MD interface: bits in the object file. */
21603 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21604 for use in the a.out file, and stores them in the array pointed to by buf.
21605 This knows about the endian-ness of the target machine and does
21606 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21607 2 (short) and 4 (long) Floating numbers are put out as a series of
21608 LITTLENUMS (shorts, here at least). */
21611 md_number_to_chars (char * buf
, valueT val
, int n
)
21613 if (target_big_endian
)
21614 number_to_chars_bigendian (buf
, val
, n
);
21616 number_to_chars_littleendian (buf
, val
, n
);
21620 md_chars_to_number (char * buf
, int n
)
21623 unsigned char * where
= (unsigned char *) buf
;
21625 if (target_big_endian
)
21630 result
|= (*where
++ & 255);
21638 result
|= (where
[n
] & 255);
21645 /* MD interface: Sections. */
21647 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21648 that an rs_machine_dependent frag may reach. */
21651 arm_frag_max_var (fragS
*fragp
)
21653 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21654 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21656 Note that we generate relaxable instructions even for cases that don't
21657 really need it, like an immediate that's a trivial constant. So we're
21658 overestimating the instruction size for some of those cases. Rather
21659 than putting more intelligence here, it would probably be better to
21660 avoid generating a relaxation frag in the first place when it can be
21661 determined up front that a short instruction will suffice. */
21663 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21667 /* Estimate the size of a frag before relaxing. Assume everything fits in
21671 md_estimate_size_before_relax (fragS
* fragp
,
21672 segT segtype ATTRIBUTE_UNUSED
)
21678 /* Convert a machine dependent frag. */
21681 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21683 unsigned long insn
;
21684 unsigned long old_op
;
21692 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21694 old_op
= bfd_get_16(abfd
, buf
);
21695 if (fragp
->fr_symbol
)
21697 exp
.X_op
= O_symbol
;
21698 exp
.X_add_symbol
= fragp
->fr_symbol
;
21702 exp
.X_op
= O_constant
;
21704 exp
.X_add_number
= fragp
->fr_offset
;
21705 opcode
= fragp
->fr_subtype
;
21708 case T_MNEM_ldr_pc
:
21709 case T_MNEM_ldr_pc2
:
21710 case T_MNEM_ldr_sp
:
21711 case T_MNEM_str_sp
:
21718 if (fragp
->fr_var
== 4)
21720 insn
= THUMB_OP32 (opcode
);
21721 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21723 insn
|= (old_op
& 0x700) << 4;
21727 insn
|= (old_op
& 7) << 12;
21728 insn
|= (old_op
& 0x38) << 13;
21730 insn
|= 0x00000c00;
21731 put_thumb32_insn (buf
, insn
);
21732 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21736 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21738 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21741 if (fragp
->fr_var
== 4)
21743 insn
= THUMB_OP32 (opcode
);
21744 insn
|= (old_op
& 0xf0) << 4;
21745 put_thumb32_insn (buf
, insn
);
21746 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21750 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21751 exp
.X_add_number
-= 4;
21759 if (fragp
->fr_var
== 4)
21761 int r0off
= (opcode
== T_MNEM_mov
21762 || opcode
== T_MNEM_movs
) ? 0 : 8;
21763 insn
= THUMB_OP32 (opcode
);
21764 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21765 insn
|= (old_op
& 0x700) << r0off
;
21766 put_thumb32_insn (buf
, insn
);
21767 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21771 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21776 if (fragp
->fr_var
== 4)
21778 insn
= THUMB_OP32(opcode
);
21779 put_thumb32_insn (buf
, insn
);
21780 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21783 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21787 if (fragp
->fr_var
== 4)
21789 insn
= THUMB_OP32(opcode
);
21790 insn
|= (old_op
& 0xf00) << 14;
21791 put_thumb32_insn (buf
, insn
);
21792 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21795 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21798 case T_MNEM_add_sp
:
21799 case T_MNEM_add_pc
:
21800 case T_MNEM_inc_sp
:
21801 case T_MNEM_dec_sp
:
21802 if (fragp
->fr_var
== 4)
21804 /* ??? Choose between add and addw. */
21805 insn
= THUMB_OP32 (opcode
);
21806 insn
|= (old_op
& 0xf0) << 4;
21807 put_thumb32_insn (buf
, insn
);
21808 if (opcode
== T_MNEM_add_pc
)
21809 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21811 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21814 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21822 if (fragp
->fr_var
== 4)
21824 insn
= THUMB_OP32 (opcode
);
21825 insn
|= (old_op
& 0xf0) << 4;
21826 insn
|= (old_op
& 0xf) << 16;
21827 put_thumb32_insn (buf
, insn
);
21828 if (insn
& (1 << 20))
21829 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21831 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21834 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21840 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21841 (enum bfd_reloc_code_real
) reloc_type
);
21842 fixp
->fx_file
= fragp
->fr_file
;
21843 fixp
->fx_line
= fragp
->fr_line
;
21844 fragp
->fr_fix
+= fragp
->fr_var
;
21846 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21847 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21848 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21849 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21852 /* Return the size of a relaxable immediate operand instruction.
21853 SHIFT and SIZE specify the form of the allowable immediate. */
21855 relax_immediate (fragS
*fragp
, int size
, int shift
)
21861 /* ??? Should be able to do better than this. */
21862 if (fragp
->fr_symbol
)
21865 low
= (1 << shift
) - 1;
21866 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21867 offset
= fragp
->fr_offset
;
21868 /* Force misaligned offsets to 32-bit variant. */
21871 if (offset
& ~mask
)
21876 /* Get the address of a symbol during relaxation. */
21878 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21884 sym
= fragp
->fr_symbol
;
21885 sym_frag
= symbol_get_frag (sym
);
21886 know (S_GET_SEGMENT (sym
) != absolute_section
21887 || sym_frag
== &zero_address_frag
);
21888 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21890 /* If frag has yet to be reached on this pass, assume it will
21891 move by STRETCH just as we did. If this is not so, it will
21892 be because some frag between grows, and that will force
21896 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21900 /* Adjust stretch for any alignment frag. Note that if have
21901 been expanding the earlier code, the symbol may be
21902 defined in what appears to be an earlier frag. FIXME:
21903 This doesn't handle the fr_subtype field, which specifies
21904 a maximum number of bytes to skip when doing an
21906 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21908 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21911 stretch
= - ((- stretch
)
21912 & ~ ((1 << (int) f
->fr_offset
) - 1));
21914 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21926 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21929 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21934 /* Assume worst case for symbols not known to be in the same section. */
21935 if (fragp
->fr_symbol
== NULL
21936 || !S_IS_DEFINED (fragp
->fr_symbol
)
21937 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21938 || S_IS_WEAK (fragp
->fr_symbol
))
21941 val
= relaxed_symbol_addr (fragp
, stretch
);
21942 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21943 addr
= (addr
+ 4) & ~3;
21944 /* Force misaligned targets to 32-bit variant. */
21948 if (val
< 0 || val
> 1020)
21953 /* Return the size of a relaxable add/sub immediate instruction. */
21955 relax_addsub (fragS
*fragp
, asection
*sec
)
21960 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21961 op
= bfd_get_16(sec
->owner
, buf
);
21962 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21963 return relax_immediate (fragp
, 8, 0);
21965 return relax_immediate (fragp
, 3, 0);
21968 /* Return TRUE iff the definition of symbol S could be pre-empted
21969 (overridden) at link or load time. */
21971 symbol_preemptible (symbolS
*s
)
21973 /* Weak symbols can always be pre-empted. */
21977 /* Non-global symbols cannot be pre-empted. */
21978 if (! S_IS_EXTERNAL (s
))
21982 /* In ELF, a global symbol can be marked protected, or private. In that
21983 case it can't be pre-empted (other definitions in the same link unit
21984 would violate the ODR). */
21985 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21989 /* Other global symbols might be pre-empted. */
21993 /* Return the size of a relaxable branch instruction. BITS is the
21994 size of the offset field in the narrow instruction. */
21997 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
22003 /* Assume worst case for symbols not known to be in the same section. */
22004 if (!S_IS_DEFINED (fragp
->fr_symbol
)
22005 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22006 || S_IS_WEAK (fragp
->fr_symbol
))
22010 /* A branch to a function in ARM state will require interworking. */
22011 if (S_IS_DEFINED (fragp
->fr_symbol
)
22012 && ARM_IS_FUNC (fragp
->fr_symbol
))
22016 if (symbol_preemptible (fragp
->fr_symbol
))
22019 val
= relaxed_symbol_addr (fragp
, stretch
);
22020 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
22023 /* Offset is a signed value *2 */
22025 if (val
>= limit
|| val
< -limit
)
22031 /* Relax a machine dependent frag. This returns the amount by which
22032 the current size of the frag should change. */
22035 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22040 oldsize
= fragp
->fr_var
;
22041 switch (fragp
->fr_subtype
)
22043 case T_MNEM_ldr_pc2
:
22044 newsize
= relax_adr (fragp
, sec
, stretch
);
22046 case T_MNEM_ldr_pc
:
22047 case T_MNEM_ldr_sp
:
22048 case T_MNEM_str_sp
:
22049 newsize
= relax_immediate (fragp
, 8, 2);
22053 newsize
= relax_immediate (fragp
, 5, 2);
22057 newsize
= relax_immediate (fragp
, 5, 1);
22061 newsize
= relax_immediate (fragp
, 5, 0);
22064 newsize
= relax_adr (fragp
, sec
, stretch
);
22070 newsize
= relax_immediate (fragp
, 8, 0);
22073 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22076 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22078 case T_MNEM_add_sp
:
22079 case T_MNEM_add_pc
:
22080 newsize
= relax_immediate (fragp
, 8, 2);
22082 case T_MNEM_inc_sp
:
22083 case T_MNEM_dec_sp
:
22084 newsize
= relax_immediate (fragp
, 7, 2);
22090 newsize
= relax_addsub (fragp
, sec
);
22096 fragp
->fr_var
= newsize
;
22097 /* Freeze wide instructions that are at or before the same location as
22098 in the previous pass. This avoids infinite loops.
22099 Don't freeze them unconditionally because targets may be artificially
22100 misaligned by the expansion of preceding frags. */
22101 if (stretch
<= 0 && newsize
> 2)
22103 md_convert_frag (sec
->owner
, sec
, fragp
);
22107 return newsize
- oldsize
;
22110 /* Round up a section size to the appropriate boundary. */
22113 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22119 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22120 of an rs_align_code fragment. */
22123 arm_handle_align (fragS
* fragP
)
22125 static unsigned char const arm_noop
[2][2][4] =
22128 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22129 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22132 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22133 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22136 static unsigned char const thumb_noop
[2][2][2] =
22139 {0xc0, 0x46}, /* LE */
22140 {0x46, 0xc0}, /* BE */
22143 {0x00, 0xbf}, /* LE */
22144 {0xbf, 0x00} /* BE */
22147 static unsigned char const wide_thumb_noop
[2][4] =
22148 { /* Wide Thumb-2 */
22149 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22150 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22153 unsigned bytes
, fix
, noop_size
;
22155 const unsigned char * noop
;
22156 const unsigned char *narrow_noop
= NULL
;
22161 if (fragP
->fr_type
!= rs_align_code
)
22164 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22165 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22168 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22169 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22171 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22173 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22175 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22176 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22178 narrow_noop
= thumb_noop
[1][target_big_endian
];
22179 noop
= wide_thumb_noop
[target_big_endian
];
22182 noop
= thumb_noop
[0][target_big_endian
];
22190 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22191 ? selected_cpu
: arm_arch_none
,
22193 [target_big_endian
];
22200 fragP
->fr_var
= noop_size
;
22202 if (bytes
& (noop_size
- 1))
22204 fix
= bytes
& (noop_size
- 1);
22206 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22208 memset (p
, 0, fix
);
22215 if (bytes
& noop_size
)
22217 /* Insert a narrow noop. */
22218 memcpy (p
, narrow_noop
, noop_size
);
22220 bytes
-= noop_size
;
22224 /* Use wide noops for the remainder */
22228 while (bytes
>= noop_size
)
22230 memcpy (p
, noop
, noop_size
);
22232 bytes
-= noop_size
;
22236 fragP
->fr_fix
+= fix
;
22239 /* Called from md_do_align. Used to create an alignment
22240 frag in a code section. */
22243 arm_frag_align_code (int n
, int max
)
22247 /* We assume that there will never be a requirement
22248 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22249 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22254 _("alignments greater than %d bytes not supported in .text sections."),
22255 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22256 as_fatal ("%s", err_msg
);
22259 p
= frag_var (rs_align_code
,
22260 MAX_MEM_FOR_RS_ALIGN_CODE
,
22262 (relax_substateT
) max
,
22269 /* Perform target specific initialisation of a frag.
22270 Note - despite the name this initialisation is not done when the frag
22271 is created, but only when its type is assigned. A frag can be created
22272 and used a long time before its type is set, so beware of assuming that
22273 this initialisation is performed first. */
22277 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22279 /* Record whether this frag is in an ARM or a THUMB area. */
22280 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22283 #else /* OBJ_ELF is defined. */
22285 arm_init_frag (fragS
* fragP
, int max_chars
)
22287 bfd_boolean frag_thumb_mode
;
22289 /* If the current ARM vs THUMB mode has not already
22290 been recorded into this frag then do so now. */
22291 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22292 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22294 /* PR 21809: Do not set a mapping state for debug sections
22295 - it just confuses other tools. */
22296 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22299 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22301 /* Record a mapping symbol for alignment frags. We will delete this
22302 later if the alignment ends up empty. */
22303 switch (fragP
->fr_type
)
22306 case rs_align_test
:
22308 mapping_state_2 (MAP_DATA
, max_chars
);
22310 case rs_align_code
:
22311 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22318 /* When we change sections we need to issue a new mapping symbol. */
22321 arm_elf_change_section (void)
22323 /* Link an unlinked unwind index table section to the .text section. */
22324 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22325 && elf_linked_to_section (now_seg
) == NULL
)
22326 elf_linked_to_section (now_seg
) = text_section
;
22330 arm_elf_section_type (const char * str
, size_t len
)
22332 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22333 return SHT_ARM_EXIDX
;
22338 /* Code to deal with unwinding tables. */
22340 static void add_unwind_adjustsp (offsetT
);
22342 /* Generate any deferred unwind frame offset. */
22345 flush_pending_unwind (void)
22349 offset
= unwind
.pending_offset
;
22350 unwind
.pending_offset
= 0;
22352 add_unwind_adjustsp (offset
);
22355 /* Add an opcode to this list for this function. Two-byte opcodes should
22356 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22360 add_unwind_opcode (valueT op
, int length
)
22362 /* Add any deferred stack adjustment. */
22363 if (unwind
.pending_offset
)
22364 flush_pending_unwind ();
22366 unwind
.sp_restored
= 0;
22368 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22370 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22371 if (unwind
.opcodes
)
22372 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22373 unwind
.opcode_alloc
);
22375 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22380 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22382 unwind
.opcode_count
++;
22386 /* Add unwind opcodes to adjust the stack pointer. */
22389 add_unwind_adjustsp (offsetT offset
)
22393 if (offset
> 0x200)
22395 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22400 /* Long form: 0xb2, uleb128. */
22401 /* This might not fit in a word so add the individual bytes,
22402 remembering the list is built in reverse order. */
22403 o
= (valueT
) ((offset
- 0x204) >> 2);
22405 add_unwind_opcode (0, 1);
22407 /* Calculate the uleb128 encoding of the offset. */
22411 bytes
[n
] = o
& 0x7f;
22417 /* Add the insn. */
22419 add_unwind_opcode (bytes
[n
- 1], 1);
22420 add_unwind_opcode (0xb2, 1);
22422 else if (offset
> 0x100)
22424 /* Two short opcodes. */
22425 add_unwind_opcode (0x3f, 1);
22426 op
= (offset
- 0x104) >> 2;
22427 add_unwind_opcode (op
, 1);
22429 else if (offset
> 0)
22431 /* Short opcode. */
22432 op
= (offset
- 4) >> 2;
22433 add_unwind_opcode (op
, 1);
22435 else if (offset
< 0)
22438 while (offset
> 0x100)
22440 add_unwind_opcode (0x7f, 1);
22443 op
= ((offset
- 4) >> 2) | 0x40;
22444 add_unwind_opcode (op
, 1);
22448 /* Finish the list of unwind opcodes for this function. */
22451 finish_unwind_opcodes (void)
22455 if (unwind
.fp_used
)
22457 /* Adjust sp as necessary. */
22458 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22459 flush_pending_unwind ();
22461 /* After restoring sp from the frame pointer. */
22462 op
= 0x90 | unwind
.fp_reg
;
22463 add_unwind_opcode (op
, 1);
22466 flush_pending_unwind ();
22470 /* Start an exception table entry. If idx is nonzero this is an index table
22474 start_unwind_section (const segT text_seg
, int idx
)
22476 const char * text_name
;
22477 const char * prefix
;
22478 const char * prefix_once
;
22479 const char * group_name
;
22487 prefix
= ELF_STRING_ARM_unwind
;
22488 prefix_once
= ELF_STRING_ARM_unwind_once
;
22489 type
= SHT_ARM_EXIDX
;
22493 prefix
= ELF_STRING_ARM_unwind_info
;
22494 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22495 type
= SHT_PROGBITS
;
22498 text_name
= segment_name (text_seg
);
22499 if (streq (text_name
, ".text"))
22502 if (strncmp (text_name
, ".gnu.linkonce.t.",
22503 strlen (".gnu.linkonce.t.")) == 0)
22505 prefix
= prefix_once
;
22506 text_name
+= strlen (".gnu.linkonce.t.");
22509 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22515 /* Handle COMDAT group. */
22516 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22518 group_name
= elf_group_name (text_seg
);
22519 if (group_name
== NULL
)
22521 as_bad (_("Group section `%s' has no group signature"),
22522 segment_name (text_seg
));
22523 ignore_rest_of_line ();
22526 flags
|= SHF_GROUP
;
22530 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22533 /* Set the section link for index tables. */
22535 elf_linked_to_section (now_seg
) = text_seg
;
22539 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22540 personality routine data. Returns zero, or the index table value for
22541 an inline entry. */
22544 create_unwind_entry (int have_data
)
22549 /* The current word of data. */
22551 /* The number of bytes left in this word. */
22554 finish_unwind_opcodes ();
22556 /* Remember the current text section. */
22557 unwind
.saved_seg
= now_seg
;
22558 unwind
.saved_subseg
= now_subseg
;
22560 start_unwind_section (now_seg
, 0);
22562 if (unwind
.personality_routine
== NULL
)
22564 if (unwind
.personality_index
== -2)
22567 as_bad (_("handlerdata in cantunwind frame"));
22568 return 1; /* EXIDX_CANTUNWIND. */
22571 /* Use a default personality routine if none is specified. */
22572 if (unwind
.personality_index
== -1)
22574 if (unwind
.opcode_count
> 3)
22575 unwind
.personality_index
= 1;
22577 unwind
.personality_index
= 0;
22580 /* Space for the personality routine entry. */
22581 if (unwind
.personality_index
== 0)
22583 if (unwind
.opcode_count
> 3)
22584 as_bad (_("too many unwind opcodes for personality routine 0"));
22588 /* All the data is inline in the index table. */
22591 while (unwind
.opcode_count
> 0)
22593 unwind
.opcode_count
--;
22594 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22598 /* Pad with "finish" opcodes. */
22600 data
= (data
<< 8) | 0xb0;
22607 /* We get two opcodes "free" in the first word. */
22608 size
= unwind
.opcode_count
- 2;
22612 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22613 if (unwind
.personality_index
!= -1)
22615 as_bad (_("attempt to recreate an unwind entry"));
22619 /* An extra byte is required for the opcode count. */
22620 size
= unwind
.opcode_count
+ 1;
22623 size
= (size
+ 3) >> 2;
22625 as_bad (_("too many unwind opcodes"));
22627 frag_align (2, 0, 0);
22628 record_alignment (now_seg
, 2);
22629 unwind
.table_entry
= expr_build_dot ();
22631 /* Allocate the table entry. */
22632 ptr
= frag_more ((size
<< 2) + 4);
22633 /* PR 13449: Zero the table entries in case some of them are not used. */
22634 memset (ptr
, 0, (size
<< 2) + 4);
22635 where
= frag_now_fix () - ((size
<< 2) + 4);
22637 switch (unwind
.personality_index
)
22640 /* ??? Should this be a PLT generating relocation? */
22641 /* Custom personality routine. */
22642 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22643 BFD_RELOC_ARM_PREL31
);
22648 /* Set the first byte to the number of additional words. */
22649 data
= size
> 0 ? size
- 1 : 0;
22653 /* ABI defined personality routines. */
22655 /* Three opcodes bytes are packed into the first word. */
22662 /* The size and first two opcode bytes go in the first word. */
22663 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22668 /* Should never happen. */
22672 /* Pack the opcodes into words (MSB first), reversing the list at the same
22674 while (unwind
.opcode_count
> 0)
22678 md_number_to_chars (ptr
, data
, 4);
22683 unwind
.opcode_count
--;
22685 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22688 /* Finish off the last word. */
22691 /* Pad with "finish" opcodes. */
22693 data
= (data
<< 8) | 0xb0;
22695 md_number_to_chars (ptr
, data
, 4);
22700 /* Add an empty descriptor if there is no user-specified data. */
22701 ptr
= frag_more (4);
22702 md_number_to_chars (ptr
, 0, 4);
22709 /* Initialize the DWARF-2 unwind information for this procedure. */
22712 tc_arm_frame_initial_instructions (void)
22714 cfi_add_CFA_def_cfa (REG_SP
, 0);
22716 #endif /* OBJ_ELF */
22718 /* Convert REGNAME to a DWARF-2 register number. */
22721 tc_arm_regname_to_dw2regnum (char *regname
)
22723 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22727 /* PR 16694: Allow VFP registers as well. */
22728 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22732 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22741 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22745 exp
.X_op
= O_secrel
;
22746 exp
.X_add_symbol
= symbol
;
22747 exp
.X_add_number
= 0;
22748 emit_expr (&exp
, size
);
22752 /* MD interface: Symbol and relocation handling. */
22754 /* Return the address within the segment that a PC-relative fixup is
22755 relative to. For ARM, PC-relative fixups applied to instructions
22756 are generally relative to the location of the fixup plus 8 bytes.
22757 Thumb branches are offset by 4, and Thumb loads relative to PC
22758 require special handling. */
22761 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22763 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22765 /* If this is pc-relative and we are going to emit a relocation
22766 then we just want to put out any pipeline compensation that the linker
22767 will need. Otherwise we want to use the calculated base.
22768 For WinCE we skip the bias for externals as well, since this
22769 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22771 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22772 || (arm_force_relocation (fixP
)
22774 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22780 switch (fixP
->fx_r_type
)
22782 /* PC relative addressing on the Thumb is slightly odd as the
22783 bottom two bits of the PC are forced to zero for the
22784 calculation. This happens *after* application of the
22785 pipeline offset. However, Thumb adrl already adjusts for
22786 this, so we need not do it again. */
22787 case BFD_RELOC_ARM_THUMB_ADD
:
22790 case BFD_RELOC_ARM_THUMB_OFFSET
:
22791 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22792 case BFD_RELOC_ARM_T32_ADD_PC12
:
22793 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22794 return (base
+ 4) & ~3;
22796 /* Thumb branches are simply offset by +4. */
22797 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22798 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22799 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22800 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22801 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22804 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22806 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22807 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22808 && ARM_IS_FUNC (fixP
->fx_addsy
)
22809 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22810 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22813 /* BLX is like branches above, but forces the low two bits of PC to
22815 case BFD_RELOC_THUMB_PCREL_BLX
:
22817 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22818 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22819 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22820 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22821 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22822 return (base
+ 4) & ~3;
22824 /* ARM mode branches are offset by +8. However, the Windows CE
22825 loader expects the relocation not to take this into account. */
22826 case BFD_RELOC_ARM_PCREL_BLX
:
22828 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22829 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22830 && ARM_IS_FUNC (fixP
->fx_addsy
)
22831 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22832 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22835 case BFD_RELOC_ARM_PCREL_CALL
:
22837 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22838 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22839 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22840 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22841 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22844 case BFD_RELOC_ARM_PCREL_BRANCH
:
22845 case BFD_RELOC_ARM_PCREL_JUMP
:
22846 case BFD_RELOC_ARM_PLT32
:
22848 /* When handling fixups immediately, because we have already
22849 discovered the value of a symbol, or the address of the frag involved
22850 we must account for the offset by +8, as the OS loader will never see the reloc.
22851 see fixup_segment() in write.c
22852 The S_IS_EXTERNAL test handles the case of global symbols.
22853 Those need the calculated base, not just the pipe compensation the linker will need. */
22855 && fixP
->fx_addsy
!= NULL
22856 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22857 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22865 /* ARM mode loads relative to PC are also offset by +8. Unlike
22866 branches, the Windows CE loader *does* expect the relocation
22867 to take this into account. */
22868 case BFD_RELOC_ARM_OFFSET_IMM
:
22869 case BFD_RELOC_ARM_OFFSET_IMM8
:
22870 case BFD_RELOC_ARM_HWLITERAL
:
22871 case BFD_RELOC_ARM_LITERAL
:
22872 case BFD_RELOC_ARM_CP_OFF_IMM
:
22876 /* Other PC-relative relocations are un-offset. */
22882 static bfd_boolean flag_warn_syms
= TRUE
;
22885 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22887 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22888 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22889 does mean that the resulting code might be very confusing to the reader.
22890 Also this warning can be triggered if the user omits an operand before
22891 an immediate address, eg:
22895 GAS treats this as an assignment of the value of the symbol foo to a
22896 symbol LDR, and so (without this code) it will not issue any kind of
22897 warning or error message.
22899 Note - ARM instructions are case-insensitive but the strings in the hash
22900 table are all stored in lower case, so we must first ensure that name is
22902 if (flag_warn_syms
&& arm_ops_hsh
)
22904 char * nbuf
= strdup (name
);
22907 for (p
= nbuf
; *p
; p
++)
22909 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22911 static struct hash_control
* already_warned
= NULL
;
22913 if (already_warned
== NULL
)
22914 already_warned
= hash_new ();
22915 /* Only warn about the symbol once. To keep the code
22916 simple we let hash_insert do the lookup for us. */
22917 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22918 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22927 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22928 Otherwise we have no need to default values of symbols. */
22931 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22934 if (name
[0] == '_' && name
[1] == 'G'
22935 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22939 if (symbol_find (name
))
22940 as_bad (_("GOT already in the symbol table"));
22942 GOT_symbol
= symbol_new (name
, undefined_section
,
22943 (valueT
) 0, & zero_address_frag
);
22953 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22954 computed as two separate immediate values, added together. We
22955 already know that this value cannot be computed by just one ARM
22958 static unsigned int
22959 validate_immediate_twopart (unsigned int val
,
22960 unsigned int * highpart
)
22965 for (i
= 0; i
< 32; i
+= 2)
22966 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22972 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22974 else if (a
& 0xff0000)
22976 if (a
& 0xff000000)
22978 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22982 gas_assert (a
& 0xff000000);
22983 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22986 return (a
& 0xff) | (i
<< 7);
22993 validate_offset_imm (unsigned int val
, int hwse
)
22995 if ((hwse
&& val
> 255) || val
> 4095)
23000 /* Subroutine of md_apply_fix. Do those data_ops which can take a
23001 negative immediate constant by altering the instruction. A bit of
23006 by inverting the second operand, and
23009 by negating the second operand. */
23012 negate_data_op (unsigned long * instruction
,
23013 unsigned long value
)
23016 unsigned long negated
, inverted
;
23018 negated
= encode_arm_immediate (-value
);
23019 inverted
= encode_arm_immediate (~value
);
23021 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
23024 /* First negates. */
23025 case OPCODE_SUB
: /* ADD <-> SUB */
23026 new_inst
= OPCODE_ADD
;
23031 new_inst
= OPCODE_SUB
;
23035 case OPCODE_CMP
: /* CMP <-> CMN */
23036 new_inst
= OPCODE_CMN
;
23041 new_inst
= OPCODE_CMP
;
23045 /* Now Inverted ops. */
23046 case OPCODE_MOV
: /* MOV <-> MVN */
23047 new_inst
= OPCODE_MVN
;
23052 new_inst
= OPCODE_MOV
;
23056 case OPCODE_AND
: /* AND <-> BIC */
23057 new_inst
= OPCODE_BIC
;
23062 new_inst
= OPCODE_AND
;
23066 case OPCODE_ADC
: /* ADC <-> SBC */
23067 new_inst
= OPCODE_SBC
;
23072 new_inst
= OPCODE_ADC
;
23076 /* We cannot do anything. */
23081 if (value
== (unsigned) FAIL
)
23084 *instruction
&= OPCODE_MASK
;
23085 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23089 /* Like negate_data_op, but for Thumb-2. */
23091 static unsigned int
23092 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23096 unsigned int negated
, inverted
;
23098 negated
= encode_thumb32_immediate (-value
);
23099 inverted
= encode_thumb32_immediate (~value
);
23101 rd
= (*instruction
>> 8) & 0xf;
23102 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23105 /* ADD <-> SUB. Includes CMP <-> CMN. */
23106 case T2_OPCODE_SUB
:
23107 new_inst
= T2_OPCODE_ADD
;
23111 case T2_OPCODE_ADD
:
23112 new_inst
= T2_OPCODE_SUB
;
23116 /* ORR <-> ORN. Includes MOV <-> MVN. */
23117 case T2_OPCODE_ORR
:
23118 new_inst
= T2_OPCODE_ORN
;
23122 case T2_OPCODE_ORN
:
23123 new_inst
= T2_OPCODE_ORR
;
23127 /* AND <-> BIC. TST has no inverted equivalent. */
23128 case T2_OPCODE_AND
:
23129 new_inst
= T2_OPCODE_BIC
;
23136 case T2_OPCODE_BIC
:
23137 new_inst
= T2_OPCODE_AND
;
23142 case T2_OPCODE_ADC
:
23143 new_inst
= T2_OPCODE_SBC
;
23147 case T2_OPCODE_SBC
:
23148 new_inst
= T2_OPCODE_ADC
;
23152 /* We cannot do anything. */
23157 if (value
== (unsigned int)FAIL
)
23160 *instruction
&= T2_OPCODE_MASK
;
23161 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23165 /* Read a 32-bit thumb instruction from buf. */
23167 static unsigned long
23168 get_thumb32_insn (char * buf
)
23170 unsigned long insn
;
23171 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23172 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23177 /* We usually want to set the low bit on the address of thumb function
23178 symbols. In particular .word foo - . should have the low bit set.
23179 Generic code tries to fold the difference of two symbols to
23180 a constant. Prevent this and force a relocation when the first symbols
23181 is a thumb function. */
23184 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23186 if (op
== O_subtract
23187 && l
->X_op
== O_symbol
23188 && r
->X_op
== O_symbol
23189 && THUMB_IS_FUNC (l
->X_add_symbol
))
23191 l
->X_op
= O_subtract
;
23192 l
->X_op_symbol
= r
->X_add_symbol
;
23193 l
->X_add_number
-= r
->X_add_number
;
23197 /* Process as normal. */
23201 /* Encode Thumb2 unconditional branches and calls. The encoding
23202 for the 2 are identical for the immediate values. */
23205 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23207 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23210 addressT S
, I1
, I2
, lo
, hi
;
23212 S
= (value
>> 24) & 0x01;
23213 I1
= (value
>> 23) & 0x01;
23214 I2
= (value
>> 22) & 0x01;
23215 hi
= (value
>> 12) & 0x3ff;
23216 lo
= (value
>> 1) & 0x7ff;
23217 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23218 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23219 newval
|= (S
<< 10) | hi
;
23220 newval2
&= ~T2I1I2MASK
;
23221 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23222 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23223 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23227 md_apply_fix (fixS
* fixP
,
23231 offsetT value
= * valP
;
23233 unsigned int newimm
;
23234 unsigned long temp
;
23236 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23238 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23240 /* Note whether this will delete the relocation. */
23242 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23245 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23246 consistency with the behaviour on 32-bit hosts. Remember value
23248 value
&= 0xffffffff;
23249 value
^= 0x80000000;
23250 value
-= 0x80000000;
23253 fixP
->fx_addnumber
= value
;
23255 /* Same treatment for fixP->fx_offset. */
23256 fixP
->fx_offset
&= 0xffffffff;
23257 fixP
->fx_offset
^= 0x80000000;
23258 fixP
->fx_offset
-= 0x80000000;
23260 switch (fixP
->fx_r_type
)
23262 case BFD_RELOC_NONE
:
23263 /* This will need to go in the object file. */
23267 case BFD_RELOC_ARM_IMMEDIATE
:
23268 /* We claim that this fixup has been processed here,
23269 even if in fact we generate an error because we do
23270 not have a reloc for it, so tc_gen_reloc will reject it. */
23273 if (fixP
->fx_addsy
)
23275 const char *msg
= 0;
23277 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23278 msg
= _("undefined symbol %s used as an immediate value");
23279 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23280 msg
= _("symbol %s is in a different section");
23281 else if (S_IS_WEAK (fixP
->fx_addsy
))
23282 msg
= _("symbol %s is weak and may be overridden later");
23286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23287 msg
, S_GET_NAME (fixP
->fx_addsy
));
23292 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23294 /* If the offset is negative, we should use encoding A2 for ADR. */
23295 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23296 newimm
= negate_data_op (&temp
, value
);
23299 newimm
= encode_arm_immediate (value
);
23301 /* If the instruction will fail, see if we can fix things up by
23302 changing the opcode. */
23303 if (newimm
== (unsigned int) FAIL
)
23304 newimm
= negate_data_op (&temp
, value
);
23305 /* MOV accepts both ARM modified immediate (A1 encoding) and
23306 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23307 When disassembling, MOV is preferred when there is no encoding
23309 if (newimm
== (unsigned int) FAIL
23310 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23311 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23312 && !((temp
>> SBIT_SHIFT
) & 0x1)
23313 && value
>= 0 && value
<= 0xffff)
23315 /* Clear bits[23:20] to change encoding from A1 to A2. */
23316 temp
&= 0xff0fffff;
23317 /* Encoding high 4bits imm. Code below will encode the remaining
23319 temp
|= (value
& 0x0000f000) << 4;
23320 newimm
= value
& 0x00000fff;
23324 if (newimm
== (unsigned int) FAIL
)
23326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23327 _("invalid constant (%lx) after fixup"),
23328 (unsigned long) value
);
23332 newimm
|= (temp
& 0xfffff000);
23333 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23336 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23338 unsigned int highpart
= 0;
23339 unsigned int newinsn
= 0xe1a00000; /* nop. */
23341 if (fixP
->fx_addsy
)
23343 const char *msg
= 0;
23345 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23346 msg
= _("undefined symbol %s used as an immediate value");
23347 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23348 msg
= _("symbol %s is in a different section");
23349 else if (S_IS_WEAK (fixP
->fx_addsy
))
23350 msg
= _("symbol %s is weak and may be overridden later");
23354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23355 msg
, S_GET_NAME (fixP
->fx_addsy
));
23360 newimm
= encode_arm_immediate (value
);
23361 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23363 /* If the instruction will fail, see if we can fix things up by
23364 changing the opcode. */
23365 if (newimm
== (unsigned int) FAIL
23366 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23368 /* No ? OK - try using two ADD instructions to generate
23370 newimm
= validate_immediate_twopart (value
, & highpart
);
23372 /* Yes - then make sure that the second instruction is
23374 if (newimm
!= (unsigned int) FAIL
)
23376 /* Still No ? Try using a negated value. */
23377 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23378 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23379 /* Otherwise - give up. */
23382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23383 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23388 /* Replace the first operand in the 2nd instruction (which
23389 is the PC) with the destination register. We have
23390 already added in the PC in the first instruction and we
23391 do not want to do it again. */
23392 newinsn
&= ~ 0xf0000;
23393 newinsn
|= ((newinsn
& 0x0f000) << 4);
23396 newimm
|= (temp
& 0xfffff000);
23397 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23399 highpart
|= (newinsn
& 0xfffff000);
23400 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23404 case BFD_RELOC_ARM_OFFSET_IMM
:
23405 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23407 /* Fall through. */
23409 case BFD_RELOC_ARM_LITERAL
:
23415 if (validate_offset_imm (value
, 0) == FAIL
)
23417 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23419 _("invalid literal constant: pool needs to be closer"));
23421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23422 _("bad immediate value for offset (%ld)"),
23427 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23429 newval
&= 0xfffff000;
23432 newval
&= 0xff7ff000;
23433 newval
|= value
| (sign
? INDEX_UP
: 0);
23435 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23438 case BFD_RELOC_ARM_OFFSET_IMM8
:
23439 case BFD_RELOC_ARM_HWLITERAL
:
23445 if (validate_offset_imm (value
, 1) == FAIL
)
23447 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23449 _("invalid literal constant: pool needs to be closer"));
23451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23452 _("bad immediate value for 8-bit offset (%ld)"),
23457 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23459 newval
&= 0xfffff0f0;
23462 newval
&= 0xff7ff0f0;
23463 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23465 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23468 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23469 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23471 _("bad immediate value for offset (%ld)"), (long) value
);
23474 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23476 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23479 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23480 /* This is a complicated relocation used for all varieties of Thumb32
23481 load/store instruction with immediate offset:
23483 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23484 *4, optional writeback(W)
23485 (doubleword load/store)
23487 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23488 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23489 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23490 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23491 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23493 Uppercase letters indicate bits that are already encoded at
23494 this point. Lowercase letters are our problem. For the
23495 second block of instructions, the secondary opcode nybble
23496 (bits 8..11) is present, and bit 23 is zero, even if this is
23497 a PC-relative operation. */
23498 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23500 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23502 if ((newval
& 0xf0000000) == 0xe0000000)
23504 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23506 newval
|= (1 << 23);
23509 if (value
% 4 != 0)
23511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23512 _("offset not a multiple of 4"));
23518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23519 _("offset out of range"));
23524 else if ((newval
& 0x000f0000) == 0x000f0000)
23526 /* PC-relative, 12-bit offset. */
23528 newval
|= (1 << 23);
23533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23534 _("offset out of range"));
23539 else if ((newval
& 0x00000100) == 0x00000100)
23541 /* Writeback: 8-bit, +/- offset. */
23543 newval
|= (1 << 9);
23548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23549 _("offset out of range"));
23554 else if ((newval
& 0x00000f00) == 0x00000e00)
23556 /* T-instruction: positive 8-bit offset. */
23557 if (value
< 0 || value
> 0xff)
23559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23560 _("offset out of range"));
23568 /* Positive 12-bit or negative 8-bit offset. */
23572 newval
|= (1 << 23);
23582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23583 _("offset out of range"));
23590 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23591 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23594 case BFD_RELOC_ARM_SHIFT_IMM
:
23595 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23596 if (((unsigned long) value
) > 32
23598 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23601 _("shift expression is too large"));
23606 /* Shifts of zero must be done as lsl. */
23608 else if (value
== 32)
23610 newval
&= 0xfffff07f;
23611 newval
|= (value
& 0x1f) << 7;
23612 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23615 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23616 case BFD_RELOC_ARM_T32_ADD_IMM
:
23617 case BFD_RELOC_ARM_T32_IMM12
:
23618 case BFD_RELOC_ARM_T32_ADD_PC12
:
23619 /* We claim that this fixup has been processed here,
23620 even if in fact we generate an error because we do
23621 not have a reloc for it, so tc_gen_reloc will reject it. */
23625 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23628 _("undefined symbol %s used as an immediate value"),
23629 S_GET_NAME (fixP
->fx_addsy
));
23633 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23635 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23638 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23639 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23640 Thumb2 modified immediate encoding (T2). */
23641 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23642 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23644 newimm
= encode_thumb32_immediate (value
);
23645 if (newimm
== (unsigned int) FAIL
)
23646 newimm
= thumb32_negate_data_op (&newval
, value
);
23648 if (newimm
== (unsigned int) FAIL
)
23650 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23652 /* Turn add/sum into addw/subw. */
23653 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23654 newval
= (newval
& 0xfeffffff) | 0x02000000;
23655 /* No flat 12-bit imm encoding for addsw/subsw. */
23656 if ((newval
& 0x00100000) == 0)
23658 /* 12 bit immediate for addw/subw. */
23662 newval
^= 0x00a00000;
23665 newimm
= (unsigned int) FAIL
;
23672 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23673 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23674 disassembling, MOV is preferred when there is no encoding
23676 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23677 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23678 but with the Rn field [19:16] set to 1111. */
23679 && (((newval
>> 16) & 0xf) == 0xf)
23680 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23681 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23682 && value
>= 0 && value
<= 0xffff)
23684 /* Toggle bit[25] to change encoding from T2 to T3. */
23686 /* Clear bits[19:16]. */
23687 newval
&= 0xfff0ffff;
23688 /* Encoding high 4bits imm. Code below will encode the
23689 remaining low 12bits. */
23690 newval
|= (value
& 0x0000f000) << 4;
23691 newimm
= value
& 0x00000fff;
23696 if (newimm
== (unsigned int)FAIL
)
23698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23699 _("invalid constant (%lx) after fixup"),
23700 (unsigned long) value
);
23704 newval
|= (newimm
& 0x800) << 15;
23705 newval
|= (newimm
& 0x700) << 4;
23706 newval
|= (newimm
& 0x0ff);
23708 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23709 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23712 case BFD_RELOC_ARM_SMC
:
23713 if (((unsigned long) value
) > 0xffff)
23714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23715 _("invalid smc expression"));
23716 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23717 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23718 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23721 case BFD_RELOC_ARM_HVC
:
23722 if (((unsigned long) value
) > 0xffff)
23723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23724 _("invalid hvc expression"));
23725 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23726 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23727 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23730 case BFD_RELOC_ARM_SWI
:
23731 if (fixP
->tc_fix_data
!= 0)
23733 if (((unsigned long) value
) > 0xff)
23734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23735 _("invalid swi expression"));
23736 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23738 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23742 if (((unsigned long) value
) > 0x00ffffff)
23743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23744 _("invalid swi expression"));
23745 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23747 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23751 case BFD_RELOC_ARM_MULTI
:
23752 if (((unsigned long) value
) > 0xffff)
23753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23754 _("invalid expression in load/store multiple"));
23755 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23756 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23760 case BFD_RELOC_ARM_PCREL_CALL
:
23762 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23764 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23765 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23766 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23767 /* Flip the bl to blx. This is a simple flip
23768 bit here because we generate PCREL_CALL for
23769 unconditional bls. */
23771 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23772 newval
= newval
| 0x10000000;
23773 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23779 goto arm_branch_common
;
23781 case BFD_RELOC_ARM_PCREL_JUMP
:
23782 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23784 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23785 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23786 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23788 /* This would map to a bl<cond>, b<cond>,
23789 b<always> to a Thumb function. We
23790 need to force a relocation for this particular
23792 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23795 /* Fall through. */
23797 case BFD_RELOC_ARM_PLT32
:
23799 case BFD_RELOC_ARM_PCREL_BRANCH
:
23801 goto arm_branch_common
;
23803 case BFD_RELOC_ARM_PCREL_BLX
:
23806 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23808 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23809 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23810 && ARM_IS_FUNC (fixP
->fx_addsy
))
23812 /* Flip the blx to a bl and warn. */
23813 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23814 newval
= 0xeb000000;
23815 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23816 _("blx to '%s' an ARM ISA state function changed to bl"),
23818 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23824 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23825 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23829 /* We are going to store value (shifted right by two) in the
23830 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23831 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23835 _("misaligned branch destination"));
23836 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23837 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23840 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23842 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23843 newval
|= (value
>> 2) & 0x00ffffff;
23844 /* Set the H bit on BLX instructions. */
23848 newval
|= 0x01000000;
23850 newval
&= ~0x01000000;
23852 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23856 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23857 /* CBZ can only branch forward. */
23859 /* Attempts to use CBZ to branch to the next instruction
23860 (which, strictly speaking, are prohibited) will be turned into
23863 FIXME: It may be better to remove the instruction completely and
23864 perform relaxation. */
23867 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23868 newval
= 0xbf00; /* NOP encoding T1 */
23869 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23876 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23878 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23879 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23880 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23885 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23886 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23889 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23891 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23892 newval
|= (value
& 0x1ff) >> 1;
23893 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23897 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23898 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23901 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23903 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23904 newval
|= (value
& 0xfff) >> 1;
23905 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23909 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23911 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23912 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23913 && ARM_IS_FUNC (fixP
->fx_addsy
)
23914 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23916 /* Force a relocation for a branch 20 bits wide. */
23919 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23921 _("conditional branch out of range"));
23923 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23926 addressT S
, J1
, J2
, lo
, hi
;
23928 S
= (value
& 0x00100000) >> 20;
23929 J2
= (value
& 0x00080000) >> 19;
23930 J1
= (value
& 0x00040000) >> 18;
23931 hi
= (value
& 0x0003f000) >> 12;
23932 lo
= (value
& 0x00000ffe) >> 1;
23934 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23935 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23936 newval
|= (S
<< 10) | hi
;
23937 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23938 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23939 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23943 case BFD_RELOC_THUMB_PCREL_BLX
:
23944 /* If there is a blx from a thumb state function to
23945 another thumb function flip this to a bl and warn
23949 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23950 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23951 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23953 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23954 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23955 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23957 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23958 newval
= newval
| 0x1000;
23959 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23960 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23965 goto thumb_bl_common
;
23967 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23968 /* A bl from Thumb state ISA to an internal ARM state function
23969 is converted to a blx. */
23971 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23972 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23973 && ARM_IS_FUNC (fixP
->fx_addsy
)
23974 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23976 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23977 newval
= newval
& ~0x1000;
23978 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23979 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23985 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23986 /* For a BLX instruction, make sure that the relocation is rounded up
23987 to a word boundary. This follows the semantics of the instruction
23988 which specifies that bit 1 of the target address will come from bit
23989 1 of the base address. */
23990 value
= (value
+ 3) & ~ 3;
23993 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23994 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23995 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23998 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
24000 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
24001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24002 else if ((value
& ~0x1ffffff)
24003 && ((value
& ~0x1ffffff) != ~0x1ffffff))
24004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24005 _("Thumb2 branch out of range"));
24008 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24009 encode_thumb2_b_bl_offset (buf
, value
);
24013 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24014 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
24015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24017 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24018 encode_thumb2_b_bl_offset (buf
, value
);
24023 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24028 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24029 md_number_to_chars (buf
, value
, 2);
24033 case BFD_RELOC_ARM_TLS_CALL
:
24034 case BFD_RELOC_ARM_THM_TLS_CALL
:
24035 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24036 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24037 case BFD_RELOC_ARM_TLS_GOTDESC
:
24038 case BFD_RELOC_ARM_TLS_GD32
:
24039 case BFD_RELOC_ARM_TLS_LE32
:
24040 case BFD_RELOC_ARM_TLS_IE32
:
24041 case BFD_RELOC_ARM_TLS_LDM32
:
24042 case BFD_RELOC_ARM_TLS_LDO32
:
24043 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24046 /* Same handling as above, but with the arm_fdpic guard. */
24047 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24048 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24049 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24052 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24057 _("Relocation supported only in FDPIC mode"));
24061 case BFD_RELOC_ARM_GOT32
:
24062 case BFD_RELOC_ARM_GOTOFF
:
24065 case BFD_RELOC_ARM_GOT_PREL
:
24066 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24067 md_number_to_chars (buf
, value
, 4);
24070 case BFD_RELOC_ARM_TARGET2
:
24071 /* TARGET2 is not partial-inplace, so we need to write the
24072 addend here for REL targets, because it won't be written out
24073 during reloc processing later. */
24074 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24075 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24078 /* Relocations for FDPIC. */
24079 case BFD_RELOC_ARM_GOTFUNCDESC
:
24080 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24081 case BFD_RELOC_ARM_FUNCDESC
:
24084 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24085 md_number_to_chars (buf
, 0, 4);
24089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24090 _("Relocation supported only in FDPIC mode"));
24095 case BFD_RELOC_RVA
:
24097 case BFD_RELOC_ARM_TARGET1
:
24098 case BFD_RELOC_ARM_ROSEGREL32
:
24099 case BFD_RELOC_ARM_SBREL32
:
24100 case BFD_RELOC_32_PCREL
:
24102 case BFD_RELOC_32_SECREL
:
24104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24106 /* For WinCE we only do this for pcrel fixups. */
24107 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24109 md_number_to_chars (buf
, value
, 4);
24113 case BFD_RELOC_ARM_PREL31
:
24114 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24116 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24117 if ((value
^ (value
>> 1)) & 0x40000000)
24119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24120 _("rel31 relocation overflow"));
24122 newval
|= value
& 0x7fffffff;
24123 md_number_to_chars (buf
, newval
, 4);
24128 case BFD_RELOC_ARM_CP_OFF_IMM
:
24129 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24130 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24131 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24133 newval
= get_thumb32_insn (buf
);
24134 if ((newval
& 0x0f200f00) == 0x0d000900)
24136 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24137 has permitted values that are multiples of 2, in the range 0
24139 if (value
< -510 || value
> 510 || (value
& 1))
24140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24141 _("co-processor offset out of range"));
24143 else if (value
< -1023 || value
> 1023 || (value
& 3))
24144 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24145 _("co-processor offset out of range"));
24150 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24151 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24152 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24154 newval
= get_thumb32_insn (buf
);
24156 newval
&= 0xffffff00;
24159 newval
&= 0xff7fff00;
24160 if ((newval
& 0x0f200f00) == 0x0d000900)
24162 /* This is a fp16 vstr/vldr.
24164 It requires the immediate offset in the instruction is shifted
24165 left by 1 to be a half-word offset.
24167 Here, left shift by 1 first, and later right shift by 2
24168 should get the right offset. */
24171 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24173 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24174 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24175 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24177 put_thumb32_insn (buf
, newval
);
24180 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24181 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24182 if (value
< -255 || value
> 255)
24183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24184 _("co-processor offset out of range"));
24186 goto cp_off_common
;
24188 case BFD_RELOC_ARM_THUMB_OFFSET
:
24189 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24190 /* Exactly what ranges, and where the offset is inserted depends
24191 on the type of instruction, we can establish this from the
24193 switch (newval
>> 12)
24195 case 4: /* PC load. */
24196 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24197 forced to zero for these loads; md_pcrel_from has already
24198 compensated for this. */
24200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24201 _("invalid offset, target not word aligned (0x%08lX)"),
24202 (((unsigned long) fixP
->fx_frag
->fr_address
24203 + (unsigned long) fixP
->fx_where
) & ~3)
24204 + (unsigned long) value
);
24206 if (value
& ~0x3fc)
24207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24208 _("invalid offset, value too big (0x%08lX)"),
24211 newval
|= value
>> 2;
24214 case 9: /* SP load/store. */
24215 if (value
& ~0x3fc)
24216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24217 _("invalid offset, value too big (0x%08lX)"),
24219 newval
|= value
>> 2;
24222 case 6: /* Word load/store. */
24224 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24225 _("invalid offset, value too big (0x%08lX)"),
24227 newval
|= value
<< 4; /* 6 - 2. */
24230 case 7: /* Byte load/store. */
24232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24233 _("invalid offset, value too big (0x%08lX)"),
24235 newval
|= value
<< 6;
24238 case 8: /* Halfword load/store. */
24240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24241 _("invalid offset, value too big (0x%08lX)"),
24243 newval
|= value
<< 5; /* 6 - 1. */
24247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24248 "Unable to process relocation for thumb opcode: %lx",
24249 (unsigned long) newval
);
24252 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24255 case BFD_RELOC_ARM_THUMB_ADD
:
24256 /* This is a complicated relocation, since we use it for all of
24257 the following immediate relocations:
24261 9bit ADD/SUB SP word-aligned
24262 10bit ADD PC/SP word-aligned
24264 The type of instruction being processed is encoded in the
24271 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24273 int rd
= (newval
>> 4) & 0xf;
24274 int rs
= newval
& 0xf;
24275 int subtract
= !!(newval
& 0x8000);
24277 /* Check for HI regs, only very restricted cases allowed:
24278 Adjusting SP, and using PC or SP to get an address. */
24279 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24280 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24281 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24282 _("invalid Hi register with immediate"));
24284 /* If value is negative, choose the opposite instruction. */
24288 subtract
= !subtract
;
24290 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24291 _("immediate value out of range"));
24296 if (value
& ~0x1fc)
24297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24298 _("invalid immediate for stack address calculation"));
24299 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24300 newval
|= value
>> 2;
24302 else if (rs
== REG_PC
|| rs
== REG_SP
)
24304 /* PR gas/18541. If the addition is for a defined symbol
24305 within range of an ADR instruction then accept it. */
24308 && fixP
->fx_addsy
!= NULL
)
24312 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24313 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24314 || S_IS_WEAK (fixP
->fx_addsy
))
24316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24317 _("address calculation needs a strongly defined nearby symbol"));
24321 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24323 /* Round up to the next 4-byte boundary. */
24328 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24333 _("symbol too far away"));
24343 if (subtract
|| value
& ~0x3fc)
24344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24345 _("invalid immediate for address calculation (value = 0x%08lX)"),
24346 (unsigned long) (subtract
? - value
: value
));
24347 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24349 newval
|= value
>> 2;
24354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24355 _("immediate value out of range"));
24356 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24357 newval
|= (rd
<< 8) | value
;
24362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24363 _("immediate value out of range"));
24364 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24365 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24368 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24371 case BFD_RELOC_ARM_THUMB_IMM
:
24372 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24373 if (value
< 0 || value
> 255)
24374 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24375 _("invalid immediate: %ld is out of range"),
24378 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24381 case BFD_RELOC_ARM_THUMB_SHIFT
:
24382 /* 5bit shift value (0..32). LSL cannot take 32. */
24383 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24384 temp
= newval
& 0xf800;
24385 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24387 _("invalid shift value: %ld"), (long) value
);
24388 /* Shifts of zero must be encoded as LSL. */
24390 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24391 /* Shifts of 32 are encoded as zero. */
24392 else if (value
== 32)
24394 newval
|= value
<< 6;
24395 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24398 case BFD_RELOC_VTABLE_INHERIT
:
24399 case BFD_RELOC_VTABLE_ENTRY
:
24403 case BFD_RELOC_ARM_MOVW
:
24404 case BFD_RELOC_ARM_MOVT
:
24405 case BFD_RELOC_ARM_THUMB_MOVW
:
24406 case BFD_RELOC_ARM_THUMB_MOVT
:
24407 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24409 /* REL format relocations are limited to a 16-bit addend. */
24410 if (!fixP
->fx_done
)
24412 if (value
< -0x8000 || value
> 0x7fff)
24413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24414 _("offset out of range"));
24416 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24417 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24422 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24423 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24425 newval
= get_thumb32_insn (buf
);
24426 newval
&= 0xfbf08f00;
24427 newval
|= (value
& 0xf000) << 4;
24428 newval
|= (value
& 0x0800) << 15;
24429 newval
|= (value
& 0x0700) << 4;
24430 newval
|= (value
& 0x00ff);
24431 put_thumb32_insn (buf
, newval
);
24435 newval
= md_chars_to_number (buf
, 4);
24436 newval
&= 0xfff0f000;
24437 newval
|= value
& 0x0fff;
24438 newval
|= (value
& 0xf000) << 4;
24439 md_number_to_chars (buf
, newval
, 4);
24444 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24445 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24446 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24447 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24448 gas_assert (!fixP
->fx_done
);
24451 bfd_boolean is_mov
;
24452 bfd_vma encoded_addend
= value
;
24454 /* Check that addend can be encoded in instruction. */
24455 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24457 _("the offset 0x%08lX is not representable"),
24458 (unsigned long) encoded_addend
);
24460 /* Extract the instruction. */
24461 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24462 is_mov
= (insn
& 0xf800) == 0x2000;
24467 if (!seg
->use_rela_p
)
24468 insn
|= encoded_addend
;
24474 /* Extract the instruction. */
24475 /* Encoding is the following
24480 /* The following conditions must be true :
24485 rd
= (insn
>> 4) & 0xf;
24487 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24489 _("Unable to process relocation for thumb opcode: %lx"),
24490 (unsigned long) insn
);
24492 /* Encode as ADD immediate8 thumb 1 code. */
24493 insn
= 0x3000 | (rd
<< 8);
24495 /* Place the encoded addend into the first 8 bits of the
24497 if (!seg
->use_rela_p
)
24498 insn
|= encoded_addend
;
24501 /* Update the instruction. */
24502 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24506 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24507 case BFD_RELOC_ARM_ALU_PC_G0
:
24508 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24509 case BFD_RELOC_ARM_ALU_PC_G1
:
24510 case BFD_RELOC_ARM_ALU_PC_G2
:
24511 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24512 case BFD_RELOC_ARM_ALU_SB_G0
:
24513 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24514 case BFD_RELOC_ARM_ALU_SB_G1
:
24515 case BFD_RELOC_ARM_ALU_SB_G2
:
24516 gas_assert (!fixP
->fx_done
);
24517 if (!seg
->use_rela_p
)
24520 bfd_vma encoded_addend
;
24521 bfd_vma addend_abs
= llabs (value
);
24523 /* Check that the absolute value of the addend can be
24524 expressed as an 8-bit constant plus a rotation. */
24525 encoded_addend
= encode_arm_immediate (addend_abs
);
24526 if (encoded_addend
== (unsigned int) FAIL
)
24527 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24528 _("the offset 0x%08lX is not representable"),
24529 (unsigned long) addend_abs
);
24531 /* Extract the instruction. */
24532 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24534 /* If the addend is positive, use an ADD instruction.
24535 Otherwise use a SUB. Take care not to destroy the S bit. */
24536 insn
&= 0xff1fffff;
24542 /* Place the encoded addend into the first 12 bits of the
24544 insn
&= 0xfffff000;
24545 insn
|= encoded_addend
;
24547 /* Update the instruction. */
24548 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24552 case BFD_RELOC_ARM_LDR_PC_G0
:
24553 case BFD_RELOC_ARM_LDR_PC_G1
:
24554 case BFD_RELOC_ARM_LDR_PC_G2
:
24555 case BFD_RELOC_ARM_LDR_SB_G0
:
24556 case BFD_RELOC_ARM_LDR_SB_G1
:
24557 case BFD_RELOC_ARM_LDR_SB_G2
:
24558 gas_assert (!fixP
->fx_done
);
24559 if (!seg
->use_rela_p
)
24562 bfd_vma addend_abs
= llabs (value
);
24564 /* Check that the absolute value of the addend can be
24565 encoded in 12 bits. */
24566 if (addend_abs
>= 0x1000)
24567 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24568 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24569 (unsigned long) addend_abs
);
24571 /* Extract the instruction. */
24572 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24574 /* If the addend is negative, clear bit 23 of the instruction.
24575 Otherwise set it. */
24577 insn
&= ~(1 << 23);
24581 /* Place the absolute value of the addend into the first 12 bits
24582 of the instruction. */
24583 insn
&= 0xfffff000;
24584 insn
|= addend_abs
;
24586 /* Update the instruction. */
24587 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24591 case BFD_RELOC_ARM_LDRS_PC_G0
:
24592 case BFD_RELOC_ARM_LDRS_PC_G1
:
24593 case BFD_RELOC_ARM_LDRS_PC_G2
:
24594 case BFD_RELOC_ARM_LDRS_SB_G0
:
24595 case BFD_RELOC_ARM_LDRS_SB_G1
:
24596 case BFD_RELOC_ARM_LDRS_SB_G2
:
24597 gas_assert (!fixP
->fx_done
);
24598 if (!seg
->use_rela_p
)
24601 bfd_vma addend_abs
= llabs (value
);
24603 /* Check that the absolute value of the addend can be
24604 encoded in 8 bits. */
24605 if (addend_abs
>= 0x100)
24606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24607 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24608 (unsigned long) addend_abs
);
24610 /* Extract the instruction. */
24611 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24613 /* If the addend is negative, clear bit 23 of the instruction.
24614 Otherwise set it. */
24616 insn
&= ~(1 << 23);
24620 /* Place the first four bits of the absolute value of the addend
24621 into the first 4 bits of the instruction, and the remaining
24622 four into bits 8 .. 11. */
24623 insn
&= 0xfffff0f0;
24624 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24626 /* Update the instruction. */
24627 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24631 case BFD_RELOC_ARM_LDC_PC_G0
:
24632 case BFD_RELOC_ARM_LDC_PC_G1
:
24633 case BFD_RELOC_ARM_LDC_PC_G2
:
24634 case BFD_RELOC_ARM_LDC_SB_G0
:
24635 case BFD_RELOC_ARM_LDC_SB_G1
:
24636 case BFD_RELOC_ARM_LDC_SB_G2
:
24637 gas_assert (!fixP
->fx_done
);
24638 if (!seg
->use_rela_p
)
24641 bfd_vma addend_abs
= llabs (value
);
24643 /* Check that the absolute value of the addend is a multiple of
24644 four and, when divided by four, fits in 8 bits. */
24645 if (addend_abs
& 0x3)
24646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24647 _("bad offset 0x%08lX (must be word-aligned)"),
24648 (unsigned long) addend_abs
);
24650 if ((addend_abs
>> 2) > 0xff)
24651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24652 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24653 (unsigned long) addend_abs
);
24655 /* Extract the instruction. */
24656 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24658 /* If the addend is negative, clear bit 23 of the instruction.
24659 Otherwise set it. */
24661 insn
&= ~(1 << 23);
24665 /* Place the addend (divided by four) into the first eight
24666 bits of the instruction. */
24667 insn
&= 0xfffffff0;
24668 insn
|= addend_abs
>> 2;
24670 /* Update the instruction. */
24671 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24675 case BFD_RELOC_ARM_V4BX
:
24676 /* This will need to go in the object file. */
24680 case BFD_RELOC_UNUSED
:
24682 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24683 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24687 /* Translate internal representation of relocation info to BFD target
24691 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24694 bfd_reloc_code_real_type code
;
24696 reloc
= XNEW (arelent
);
24698 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24699 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24700 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24702 if (fixp
->fx_pcrel
)
24704 if (section
->use_rela_p
)
24705 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24707 fixp
->fx_offset
= reloc
->address
;
24709 reloc
->addend
= fixp
->fx_offset
;
24711 switch (fixp
->fx_r_type
)
24714 if (fixp
->fx_pcrel
)
24716 code
= BFD_RELOC_8_PCREL
;
24719 /* Fall through. */
24722 if (fixp
->fx_pcrel
)
24724 code
= BFD_RELOC_16_PCREL
;
24727 /* Fall through. */
24730 if (fixp
->fx_pcrel
)
24732 code
= BFD_RELOC_32_PCREL
;
24735 /* Fall through. */
24737 case BFD_RELOC_ARM_MOVW
:
24738 if (fixp
->fx_pcrel
)
24740 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24743 /* Fall through. */
24745 case BFD_RELOC_ARM_MOVT
:
24746 if (fixp
->fx_pcrel
)
24748 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24751 /* Fall through. */
24753 case BFD_RELOC_ARM_THUMB_MOVW
:
24754 if (fixp
->fx_pcrel
)
24756 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24759 /* Fall through. */
24761 case BFD_RELOC_ARM_THUMB_MOVT
:
24762 if (fixp
->fx_pcrel
)
24764 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24767 /* Fall through. */
24769 case BFD_RELOC_NONE
:
24770 case BFD_RELOC_ARM_PCREL_BRANCH
:
24771 case BFD_RELOC_ARM_PCREL_BLX
:
24772 case BFD_RELOC_RVA
:
24773 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24774 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24775 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24776 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24777 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24778 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24779 case BFD_RELOC_VTABLE_ENTRY
:
24780 case BFD_RELOC_VTABLE_INHERIT
:
24782 case BFD_RELOC_32_SECREL
:
24784 code
= fixp
->fx_r_type
;
24787 case BFD_RELOC_THUMB_PCREL_BLX
:
24789 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24790 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24793 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24796 case BFD_RELOC_ARM_LITERAL
:
24797 case BFD_RELOC_ARM_HWLITERAL
:
24798 /* If this is called then the a literal has
24799 been referenced across a section boundary. */
24800 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24801 _("literal referenced across section boundary"));
24805 case BFD_RELOC_ARM_TLS_CALL
:
24806 case BFD_RELOC_ARM_THM_TLS_CALL
:
24807 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24808 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24809 case BFD_RELOC_ARM_GOT32
:
24810 case BFD_RELOC_ARM_GOTOFF
:
24811 case BFD_RELOC_ARM_GOT_PREL
:
24812 case BFD_RELOC_ARM_PLT32
:
24813 case BFD_RELOC_ARM_TARGET1
:
24814 case BFD_RELOC_ARM_ROSEGREL32
:
24815 case BFD_RELOC_ARM_SBREL32
:
24816 case BFD_RELOC_ARM_PREL31
:
24817 case BFD_RELOC_ARM_TARGET2
:
24818 case BFD_RELOC_ARM_TLS_LDO32
:
24819 case BFD_RELOC_ARM_PCREL_CALL
:
24820 case BFD_RELOC_ARM_PCREL_JUMP
:
24821 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24822 case BFD_RELOC_ARM_ALU_PC_G0
:
24823 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24824 case BFD_RELOC_ARM_ALU_PC_G1
:
24825 case BFD_RELOC_ARM_ALU_PC_G2
:
24826 case BFD_RELOC_ARM_LDR_PC_G0
:
24827 case BFD_RELOC_ARM_LDR_PC_G1
:
24828 case BFD_RELOC_ARM_LDR_PC_G2
:
24829 case BFD_RELOC_ARM_LDRS_PC_G0
:
24830 case BFD_RELOC_ARM_LDRS_PC_G1
:
24831 case BFD_RELOC_ARM_LDRS_PC_G2
:
24832 case BFD_RELOC_ARM_LDC_PC_G0
:
24833 case BFD_RELOC_ARM_LDC_PC_G1
:
24834 case BFD_RELOC_ARM_LDC_PC_G2
:
24835 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24836 case BFD_RELOC_ARM_ALU_SB_G0
:
24837 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24838 case BFD_RELOC_ARM_ALU_SB_G1
:
24839 case BFD_RELOC_ARM_ALU_SB_G2
:
24840 case BFD_RELOC_ARM_LDR_SB_G0
:
24841 case BFD_RELOC_ARM_LDR_SB_G1
:
24842 case BFD_RELOC_ARM_LDR_SB_G2
:
24843 case BFD_RELOC_ARM_LDRS_SB_G0
:
24844 case BFD_RELOC_ARM_LDRS_SB_G1
:
24845 case BFD_RELOC_ARM_LDRS_SB_G2
:
24846 case BFD_RELOC_ARM_LDC_SB_G0
:
24847 case BFD_RELOC_ARM_LDC_SB_G1
:
24848 case BFD_RELOC_ARM_LDC_SB_G2
:
24849 case BFD_RELOC_ARM_V4BX
:
24850 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24851 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24852 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24853 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24854 case BFD_RELOC_ARM_GOTFUNCDESC
:
24855 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24856 case BFD_RELOC_ARM_FUNCDESC
:
24857 code
= fixp
->fx_r_type
;
24860 case BFD_RELOC_ARM_TLS_GOTDESC
:
24861 case BFD_RELOC_ARM_TLS_GD32
:
24862 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24863 case BFD_RELOC_ARM_TLS_LE32
:
24864 case BFD_RELOC_ARM_TLS_IE32
:
24865 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24866 case BFD_RELOC_ARM_TLS_LDM32
:
24867 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24868 /* BFD will include the symbol's address in the addend.
24869 But we don't want that, so subtract it out again here. */
24870 if (!S_IS_COMMON (fixp
->fx_addsy
))
24871 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24872 code
= fixp
->fx_r_type
;
24876 case BFD_RELOC_ARM_IMMEDIATE
:
24877 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24878 _("internal relocation (type: IMMEDIATE) not fixed up"));
24881 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24882 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24883 _("ADRL used for a symbol not defined in the same file"));
24886 case BFD_RELOC_ARM_OFFSET_IMM
:
24887 if (section
->use_rela_p
)
24889 code
= fixp
->fx_r_type
;
24893 if (fixp
->fx_addsy
!= NULL
24894 && !S_IS_DEFINED (fixp
->fx_addsy
)
24895 && S_IS_LOCAL (fixp
->fx_addsy
))
24897 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24898 _("undefined local label `%s'"),
24899 S_GET_NAME (fixp
->fx_addsy
));
24903 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24904 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24911 switch (fixp
->fx_r_type
)
24913 case BFD_RELOC_NONE
: type
= "NONE"; break;
24914 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24915 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24916 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24917 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24918 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24919 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24920 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24921 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24922 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24923 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24924 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24925 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24926 default: type
= _("<unknown>"); break;
24928 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24929 _("cannot represent %s relocation in this object file format"),
24936 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24938 && fixp
->fx_addsy
== GOT_symbol
)
24940 code
= BFD_RELOC_ARM_GOTPC
;
24941 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24945 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24947 if (reloc
->howto
== NULL
)
24949 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24950 _("cannot represent %s relocation in this object file format"),
24951 bfd_get_reloc_code_name (code
));
24955 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24956 vtable entry to be used in the relocation's section offset. */
24957 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24958 reloc
->address
= fixp
->fx_offset
;
24963 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24966 cons_fix_new_arm (fragS
* frag
,
24970 bfd_reloc_code_real_type reloc
)
24975 FIXME: @@ Should look at CPU word size. */
24979 reloc
= BFD_RELOC_8
;
24982 reloc
= BFD_RELOC_16
;
24986 reloc
= BFD_RELOC_32
;
24989 reloc
= BFD_RELOC_64
;
24994 if (exp
->X_op
== O_secrel
)
24996 exp
->X_op
= O_symbol
;
24997 reloc
= BFD_RELOC_32_SECREL
;
25001 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
25004 #if defined (OBJ_COFF)
25006 arm_validate_fix (fixS
* fixP
)
25008 /* If the destination of the branch is a defined symbol which does not have
25009 the THUMB_FUNC attribute, then we must be calling a function which has
25010 the (interfacearm) attribute. We look for the Thumb entry point to that
25011 function and change the branch to refer to that function instead. */
25012 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
25013 && fixP
->fx_addsy
!= NULL
25014 && S_IS_DEFINED (fixP
->fx_addsy
)
25015 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
25017 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
25024 arm_force_relocation (struct fix
* fixp
)
25026 #if defined (OBJ_COFF) && defined (TE_PE)
25027 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
25031 /* In case we have a call or a branch to a function in ARM ISA mode from
25032 a thumb function or vice-versa force the relocation. These relocations
25033 are cleared off for some cores that might have blx and simple transformations
25037 switch (fixp
->fx_r_type
)
25039 case BFD_RELOC_ARM_PCREL_JUMP
:
25040 case BFD_RELOC_ARM_PCREL_CALL
:
25041 case BFD_RELOC_THUMB_PCREL_BLX
:
25042 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25046 case BFD_RELOC_ARM_PCREL_BLX
:
25047 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25048 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25049 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25050 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25059 /* Resolve these relocations even if the symbol is extern or weak.
25060 Technically this is probably wrong due to symbol preemption.
25061 In practice these relocations do not have enough range to be useful
25062 at dynamic link time, and some code (e.g. in the Linux kernel)
25063 expects these references to be resolved. */
25064 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25065 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25066 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25067 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25068 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25069 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25070 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25071 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25072 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25073 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25074 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25075 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25076 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25077 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25080 /* Always leave these relocations for the linker. */
25081 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25082 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25083 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25086 /* Always generate relocations against function symbols. */
25087 if (fixp
->fx_r_type
== BFD_RELOC_32
25089 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25092 return generic_force_reloc (fixp
);
25095 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25096 /* Relocations against function names must be left unadjusted,
25097 so that the linker can use this information to generate interworking
25098 stubs. The MIPS version of this function
25099 also prevents relocations that are mips-16 specific, but I do not
25100 know why it does this.
25103 There is one other problem that ought to be addressed here, but
25104 which currently is not: Taking the address of a label (rather
25105 than a function) and then later jumping to that address. Such
25106 addresses also ought to have their bottom bit set (assuming that
25107 they reside in Thumb code), but at the moment they will not. */
25110 arm_fix_adjustable (fixS
* fixP
)
25112 if (fixP
->fx_addsy
== NULL
)
25115 /* Preserve relocations against symbols with function type. */
25116 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25119 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25120 && fixP
->fx_subsy
== NULL
)
25123 /* We need the symbol name for the VTABLE entries. */
25124 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25125 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25128 /* Don't allow symbols to be discarded on GOT related relocs. */
25129 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25130 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25131 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25132 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25133 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25134 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25135 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25136 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25137 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25138 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25139 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25140 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25141 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25142 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25143 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25144 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25145 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25148 /* Similarly for group relocations. */
25149 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25150 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25151 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25154 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25155 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25156 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25157 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25158 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25159 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25160 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25161 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25162 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25165 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25166 offsets, so keep these symbols. */
25167 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25168 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25173 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25177 elf32_arm_target_format (void)
25180 return (target_big_endian
25181 ? "elf32-bigarm-symbian"
25182 : "elf32-littlearm-symbian");
25183 #elif defined (TE_VXWORKS)
25184 return (target_big_endian
25185 ? "elf32-bigarm-vxworks"
25186 : "elf32-littlearm-vxworks");
25187 #elif defined (TE_NACL)
25188 return (target_big_endian
25189 ? "elf32-bigarm-nacl"
25190 : "elf32-littlearm-nacl");
25194 if (target_big_endian
)
25195 return "elf32-bigarm-fdpic";
25197 return "elf32-littlearm-fdpic";
25201 if (target_big_endian
)
25202 return "elf32-bigarm";
25204 return "elf32-littlearm";
25210 armelf_frob_symbol (symbolS
* symp
,
25213 elf_frob_symbol (symp
, puntp
);
25217 /* MD interface: Finalization. */
25222 literal_pool
* pool
;
25224 /* Ensure that all the IT blocks are properly closed. */
25225 check_it_blocks_finished ();
25227 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25229 /* Put it at the end of the relevant section. */
25230 subseg_set (pool
->section
, pool
->sub_section
);
25232 arm_elf_change_section ();
25239 /* Remove any excess mapping symbols generated for alignment frags in
25240 SEC. We may have created a mapping symbol before a zero byte
25241 alignment; remove it if there's a mapping symbol after the
25244 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25245 void *dummy ATTRIBUTE_UNUSED
)
25247 segment_info_type
*seginfo
= seg_info (sec
);
25250 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25253 for (fragp
= seginfo
->frchainP
->frch_root
;
25255 fragp
= fragp
->fr_next
)
25257 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25258 fragS
*next
= fragp
->fr_next
;
25260 /* Variable-sized frags have been converted to fixed size by
25261 this point. But if this was variable-sized to start with,
25262 there will be a fixed-size frag after it. So don't handle
25264 if (sym
== NULL
|| next
== NULL
)
25267 if (S_GET_VALUE (sym
) < next
->fr_address
)
25268 /* Not at the end of this frag. */
25270 know (S_GET_VALUE (sym
) == next
->fr_address
);
25274 if (next
->tc_frag_data
.first_map
!= NULL
)
25276 /* Next frag starts with a mapping symbol. Discard this
25278 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25282 if (next
->fr_next
== NULL
)
25284 /* This mapping symbol is at the end of the section. Discard
25286 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25287 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25291 /* As long as we have empty frags without any mapping symbols,
25293 /* If the next frag is non-empty and does not start with a
25294 mapping symbol, then this mapping symbol is required. */
25295 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25298 next
= next
->fr_next
;
25300 while (next
!= NULL
);
25305 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25309 arm_adjust_symtab (void)
25314 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25316 if (ARM_IS_THUMB (sym
))
25318 if (THUMB_IS_FUNC (sym
))
25320 /* Mark the symbol as a Thumb function. */
25321 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25322 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25323 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25325 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25326 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25328 as_bad (_("%s: unexpected function type: %d"),
25329 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25331 else switch (S_GET_STORAGE_CLASS (sym
))
25334 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25337 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25340 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25348 if (ARM_IS_INTERWORK (sym
))
25349 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25356 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25358 if (ARM_IS_THUMB (sym
))
25360 elf_symbol_type
* elf_sym
;
25362 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25363 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25365 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25366 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25368 /* If it's a .thumb_func, declare it as so,
25369 otherwise tag label as .code 16. */
25370 if (THUMB_IS_FUNC (sym
))
25371 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25372 ST_BRANCH_TO_THUMB
);
25373 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25374 elf_sym
->internal_elf_sym
.st_info
=
25375 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25380 /* Remove any overlapping mapping symbols generated by alignment frags. */
25381 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25382 /* Now do generic ELF adjustments. */
25383 elf_adjust_symtab ();
25387 /* MD interface: Initialization. */
25390 set_constant_flonums (void)
25394 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25395 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25399 /* Auto-select Thumb mode if it's the only available instruction set for the
25400 given architecture. */
25403 autoselect_thumb_from_cpu_variant (void)
25405 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25406 opcode_select (16);
25415 if ( (arm_ops_hsh
= hash_new ()) == NULL
25416 || (arm_cond_hsh
= hash_new ()) == NULL
25417 || (arm_shift_hsh
= hash_new ()) == NULL
25418 || (arm_psr_hsh
= hash_new ()) == NULL
25419 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25420 || (arm_reg_hsh
= hash_new ()) == NULL
25421 || (arm_reloc_hsh
= hash_new ()) == NULL
25422 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25423 as_fatal (_("virtual memory exhausted"));
25425 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25426 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25427 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25428 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25429 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25430 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25431 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25432 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25433 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25434 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25435 (void *) (v7m_psrs
+ i
));
25436 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25437 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25439 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25441 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25442 (void *) (barrier_opt_names
+ i
));
25444 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25446 struct reloc_entry
* entry
= reloc_names
+ i
;
25448 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25449 /* This makes encode_branch() use the EABI versions of this relocation. */
25450 entry
->reloc
= BFD_RELOC_UNUSED
;
25452 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25456 set_constant_flonums ();
25458 /* Set the cpu variant based on the command-line options. We prefer
25459 -mcpu= over -march= if both are set (as for GCC); and we prefer
25460 -mfpu= over any other way of setting the floating point unit.
25461 Use of legacy options with new options are faulted. */
25464 if (mcpu_cpu_opt
|| march_cpu_opt
)
25465 as_bad (_("use of old and new-style options to set CPU type"));
25467 selected_arch
= *legacy_cpu
;
25469 else if (mcpu_cpu_opt
)
25471 selected_arch
= *mcpu_cpu_opt
;
25472 selected_ext
= *mcpu_ext_opt
;
25474 else if (march_cpu_opt
)
25476 selected_arch
= *march_cpu_opt
;
25477 selected_ext
= *march_ext_opt
;
25479 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25484 as_bad (_("use of old and new-style options to set FPU type"));
25486 selected_fpu
= *legacy_fpu
;
25489 selected_fpu
= *mfpu_opt
;
25492 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25493 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25494 /* Some environments specify a default FPU. If they don't, infer it
25495 from the processor. */
25497 selected_fpu
= *mcpu_fpu_opt
;
25498 else if (march_fpu_opt
)
25499 selected_fpu
= *march_fpu_opt
;
25501 selected_fpu
= fpu_default
;
25505 if (ARM_FEATURE_ZERO (selected_fpu
))
25507 if (!no_cpu_selected ())
25508 selected_fpu
= fpu_default
;
25510 selected_fpu
= fpu_arch_fpa
;
25514 if (ARM_FEATURE_ZERO (selected_arch
))
25516 selected_arch
= cpu_default
;
25517 selected_cpu
= selected_arch
;
25519 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25521 /* Autodection of feature mode: allow all features in cpu_variant but leave
25522 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25523 after all instruction have been processed and we can decide what CPU
25524 should be selected. */
25525 if (ARM_FEATURE_ZERO (selected_arch
))
25526 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25528 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25531 autoselect_thumb_from_cpu_variant ();
25533 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25535 #if defined OBJ_COFF || defined OBJ_ELF
25537 unsigned int flags
= 0;
25539 #if defined OBJ_ELF
25540 flags
= meabi_flags
;
25542 switch (meabi_flags
)
25544 case EF_ARM_EABI_UNKNOWN
:
25546 /* Set the flags in the private structure. */
25547 if (uses_apcs_26
) flags
|= F_APCS26
;
25548 if (support_interwork
) flags
|= F_INTERWORK
;
25549 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25550 if (pic_code
) flags
|= F_PIC
;
25551 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25552 flags
|= F_SOFT_FLOAT
;
25554 switch (mfloat_abi_opt
)
25556 case ARM_FLOAT_ABI_SOFT
:
25557 case ARM_FLOAT_ABI_SOFTFP
:
25558 flags
|= F_SOFT_FLOAT
;
25561 case ARM_FLOAT_ABI_HARD
:
25562 if (flags
& F_SOFT_FLOAT
)
25563 as_bad (_("hard-float conflicts with specified fpu"));
25567 /* Using pure-endian doubles (even if soft-float). */
25568 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25569 flags
|= F_VFP_FLOAT
;
25571 #if defined OBJ_ELF
25572 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25573 flags
|= EF_ARM_MAVERICK_FLOAT
;
25576 case EF_ARM_EABI_VER4
:
25577 case EF_ARM_EABI_VER5
:
25578 /* No additional flags to set. */
25585 bfd_set_private_flags (stdoutput
, flags
);
25587 /* We have run out flags in the COFF header to encode the
25588 status of ATPCS support, so instead we create a dummy,
25589 empty, debug section called .arm.atpcs. */
25594 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25598 bfd_set_section_flags
25599 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25600 bfd_set_section_size (stdoutput
, sec
, 0);
25601 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25607 /* Record the CPU type as well. */
25608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25609 mach
= bfd_mach_arm_iWMMXt2
;
25610 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25611 mach
= bfd_mach_arm_iWMMXt
;
25612 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25613 mach
= bfd_mach_arm_XScale
;
25614 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25615 mach
= bfd_mach_arm_ep9312
;
25616 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25617 mach
= bfd_mach_arm_5TE
;
25618 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25620 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25621 mach
= bfd_mach_arm_5T
;
25623 mach
= bfd_mach_arm_5
;
25625 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25627 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25628 mach
= bfd_mach_arm_4T
;
25630 mach
= bfd_mach_arm_4
;
25632 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25633 mach
= bfd_mach_arm_3M
;
25634 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25635 mach
= bfd_mach_arm_3
;
25636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25637 mach
= bfd_mach_arm_2a
;
25638 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25639 mach
= bfd_mach_arm_2
;
25641 mach
= bfd_mach_arm_unknown
;
25643 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25646 /* Command line processing. */
25649 Invocation line includes a switch not recognized by the base assembler.
25650 See if it's a processor-specific option.
25652 This routine is somewhat complicated by the need for backwards
25653 compatibility (since older releases of gcc can't be changed).
25654 The new options try to make the interface as compatible as
25657 New options (supported) are:
25659 -mcpu=<cpu name> Assemble for selected processor
25660 -march=<architecture name> Assemble for selected architecture
25661 -mfpu=<fpu architecture> Assemble for selected FPU.
25662 -EB/-mbig-endian Big-endian
25663 -EL/-mlittle-endian Little-endian
25664 -k Generate PIC code
25665 -mthumb Start in Thumb mode
25666 -mthumb-interwork Code supports ARM/Thumb interworking
25668 -m[no-]warn-deprecated Warn about deprecated features
25669 -m[no-]warn-syms Warn when symbols match instructions
25671 For now we will also provide support for:
25673 -mapcs-32 32-bit Program counter
25674 -mapcs-26 26-bit Program counter
25675 -macps-float Floats passed in FP registers
25676 -mapcs-reentrant Reentrant code
25678 (sometime these will probably be replaced with -mapcs=<list of options>
25679 and -matpcs=<list of options>)
25681 The remaining options are only supported for back-wards compatibility.
25682 Cpu variants, the arm part is optional:
25683 -m[arm]1 Currently not supported.
25684 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25685 -m[arm]3 Arm 3 processor
25686 -m[arm]6[xx], Arm 6 processors
25687 -m[arm]7[xx][t][[d]m] Arm 7 processors
25688 -m[arm]8[10] Arm 8 processors
25689 -m[arm]9[20][tdmi] Arm 9 processors
25690 -mstrongarm[110[0]] StrongARM processors
25691 -mxscale XScale processors
25692 -m[arm]v[2345[t[e]]] Arm architectures
25693 -mall All (except the ARM1)
25695 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25696 -mfpe-old (No float load/store multiples)
25697 -mvfpxd VFP Single precision
25699 -mno-fpu Disable all floating point instructions
25701 The following CPU names are recognized:
25702 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25703 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25704 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25705 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25706 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25707 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25708 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25712 const char * md_shortopts
= "m:k";
25714 #ifdef ARM_BI_ENDIAN
25715 #define OPTION_EB (OPTION_MD_BASE + 0)
25716 #define OPTION_EL (OPTION_MD_BASE + 1)
25718 #if TARGET_BYTES_BIG_ENDIAN
25719 #define OPTION_EB (OPTION_MD_BASE + 0)
25721 #define OPTION_EL (OPTION_MD_BASE + 1)
25724 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25725 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
25727 struct option md_longopts
[] =
25730 {"EB", no_argument
, NULL
, OPTION_EB
},
25733 {"EL", no_argument
, NULL
, OPTION_EL
},
25735 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25737 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
25739 {NULL
, no_argument
, NULL
, 0}
25742 size_t md_longopts_size
= sizeof (md_longopts
);
25744 struct arm_option_table
25746 const char * option
; /* Option name to match. */
25747 const char * help
; /* Help information. */
25748 int * var
; /* Variable to change. */
25749 int value
; /* What to change it to. */
25750 const char * deprecated
; /* If non-null, print this message. */
25753 struct arm_option_table arm_opts
[] =
25755 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25756 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25757 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25758 &support_interwork
, 1, NULL
},
25759 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25760 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25761 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25763 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25764 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25765 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25766 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25769 /* These are recognized by the assembler, but have no affect on code. */
25770 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25771 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25773 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25774 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25775 &warn_on_deprecated
, 0, NULL
},
25776 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25777 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25778 {NULL
, NULL
, NULL
, 0, NULL
}
25781 struct arm_legacy_option_table
25783 const char * option
; /* Option name to match. */
25784 const arm_feature_set
** var
; /* Variable to change. */
25785 const arm_feature_set value
; /* What to change it to. */
25786 const char * deprecated
; /* If non-null, print this message. */
25789 const struct arm_legacy_option_table arm_legacy_opts
[] =
25791 /* DON'T add any new processors to this list -- we want the whole list
25792 to go away... Add them to the processors table instead. */
25793 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25794 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25795 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25796 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25797 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25798 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25799 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25800 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25801 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25802 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25803 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25804 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25805 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25806 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25807 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25808 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25809 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25810 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25811 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25812 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25813 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25814 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25815 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25816 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25817 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25818 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25819 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25820 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25821 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25822 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25823 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25824 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25825 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25826 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25827 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25828 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25829 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25830 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25831 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25832 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25833 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25834 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25835 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25836 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25837 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25838 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25839 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25840 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25841 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25842 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25843 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25844 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25845 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25846 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25847 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25848 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25849 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25850 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25851 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25852 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25853 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25854 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25855 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25856 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25857 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25858 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25859 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25860 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25861 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25862 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25863 N_("use -mcpu=strongarm110")},
25864 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25865 N_("use -mcpu=strongarm1100")},
25866 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25867 N_("use -mcpu=strongarm1110")},
25868 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25869 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25870 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25872 /* Architecture variants -- don't add any more to this list either. */
25873 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25874 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25875 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25876 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25877 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25878 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25879 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25880 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25881 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25882 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25883 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25884 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25885 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25886 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25887 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25888 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25889 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25890 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25892 /* Floating point variants -- don't add any more to this list either. */
25893 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25894 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25895 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25896 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25897 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25899 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25902 struct arm_cpu_option_table
25906 const arm_feature_set value
;
25907 const arm_feature_set ext
;
25908 /* For some CPUs we assume an FPU unless the user explicitly sets
25910 const arm_feature_set default_fpu
;
25911 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25913 const char * canonical_name
;
25916 /* This list should, at a minimum, contain all the cpu names
25917 recognized by GCC. */
25918 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25920 static const struct arm_cpu_option_table arm_cpus
[] =
25922 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25925 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25928 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25931 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25934 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25937 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25940 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25943 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25946 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25949 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25952 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25955 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25958 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25961 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25964 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25967 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25970 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25973 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25976 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25979 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25982 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25985 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25988 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25991 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25994 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25997 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
26000 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
26003 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
26006 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
26009 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
26012 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
26015 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
26018 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
26021 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
26024 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
26027 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
26030 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
26033 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26036 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26039 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26042 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26045 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26048 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26051 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26054 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26057 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26061 /* For V5 or later processors we default to using VFP; but the user
26062 should really set the FPU type explicitly. */
26063 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26066 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26069 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26072 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26075 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26078 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26081 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26084 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26087 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26090 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26093 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26096 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26099 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26102 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26105 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26108 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26111 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26114 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26117 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26120 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26123 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26126 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26129 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26132 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26135 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26138 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26141 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26144 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26147 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26150 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26153 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26156 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26159 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26162 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26165 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26168 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26171 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26172 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26174 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26176 FPU_ARCH_NEON_VFP_V4
),
26177 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26178 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26179 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26180 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26181 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26182 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26183 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26185 FPU_ARCH_NEON_VFP_V4
),
26186 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26188 FPU_ARCH_NEON_VFP_V4
),
26189 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26191 FPU_ARCH_NEON_VFP_V4
),
26192 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26193 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26194 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26195 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26196 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26197 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26198 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26199 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26200 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26201 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26202 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26203 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26204 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26205 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26206 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26207 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26208 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26209 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26210 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26211 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26212 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26213 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26214 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26215 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26216 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26217 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26218 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26219 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
26220 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26221 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26222 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26225 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26227 FPU_ARCH_VFP_V3D16
),
26228 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26229 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26231 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26232 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26233 FPU_ARCH_VFP_V3D16
),
26234 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26235 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26236 FPU_ARCH_VFP_V3D16
),
26237 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26238 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26239 FPU_ARCH_NEON_VFP_ARMV8
),
26240 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26241 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26243 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26246 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26249 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26252 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26255 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26258 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26261 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26264 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26265 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26266 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26267 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
26268 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26269 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26270 /* ??? XSCALE is really an architecture. */
26271 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26275 /* ??? iwmmxt is not a processor. */
26276 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26279 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26282 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26287 ARM_CPU_OPT ("ep9312", "ARM920T",
26288 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26289 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26291 /* Marvell processors. */
26292 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26293 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26294 FPU_ARCH_VFP_V3D16
),
26295 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26296 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26297 FPU_ARCH_NEON_VFP_V4
),
26299 /* APM X-Gene family. */
26300 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26302 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26303 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26304 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26305 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26307 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26311 struct arm_ext_table
26315 const arm_feature_set merge
;
26316 const arm_feature_set clear
;
26319 struct arm_arch_option_table
26323 const arm_feature_set value
;
26324 const arm_feature_set default_fpu
;
26325 const struct arm_ext_table
* ext_table
;
26328 /* Used to add support for +E and +noE extension. */
26329 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
26330 /* Used to add support for a +E extension. */
26331 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
26332 /* Used to add support for a +noE extension. */
26333 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
26335 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
26336 ~0 & ~FPU_ENDIAN_PURE)
26338 static const struct arm_ext_table armv5te_ext_table
[] =
26340 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
26341 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26344 static const struct arm_ext_table armv7_ext_table
[] =
26346 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26347 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26350 static const struct arm_ext_table armv7ve_ext_table
[] =
26352 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
26353 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
26354 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26355 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26356 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26357 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
26358 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26360 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
26361 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26363 /* Aliases for +simd. */
26364 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26366 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26367 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26368 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26370 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26373 static const struct arm_ext_table armv7a_ext_table
[] =
26375 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26376 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26377 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26378 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26379 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26380 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
26381 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26383 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
26384 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26386 /* Aliases for +simd. */
26387 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26388 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26390 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26391 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26393 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
26394 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
26395 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26398 static const struct arm_ext_table armv7r_ext_table
[] =
26400 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
26401 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
26402 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26403 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26404 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
26405 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26406 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26407 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
26408 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26411 static const struct arm_ext_table armv7em_ext_table
[] =
26413 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
26414 /* Alias for +fp, used to be known as fpv4-sp-d16. */
26415 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
26416 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
26417 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26418 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
26419 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26422 static const struct arm_ext_table armv8a_ext_table
[] =
26424 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26425 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26426 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26427 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26429 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26430 should use the +simd option to turn on FP. */
26431 ARM_REMOVE ("fp", ALL_FP
),
26432 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26433 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26434 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26438 static const struct arm_ext_table armv81a_ext_table
[] =
26440 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26441 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26442 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26444 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26445 should use the +simd option to turn on FP. */
26446 ARM_REMOVE ("fp", ALL_FP
),
26447 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26448 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26449 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26452 static const struct arm_ext_table armv82a_ext_table
[] =
26454 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26455 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
26456 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
26457 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26458 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26459 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26461 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26462 should use the +simd option to turn on FP. */
26463 ARM_REMOVE ("fp", ALL_FP
),
26464 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26465 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26466 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26469 static const struct arm_ext_table armv84a_ext_table
[] =
26471 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26472 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26473 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26474 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26476 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26477 should use the +simd option to turn on FP. */
26478 ARM_REMOVE ("fp", ALL_FP
),
26479 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26480 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26481 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26484 static const struct arm_ext_table armv85a_ext_table
[] =
26486 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26487 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26488 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26489 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26491 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26492 should use the +simd option to turn on FP. */
26493 ARM_REMOVE ("fp", ALL_FP
),
26494 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26497 static const struct arm_ext_table armv8m_main_ext_table
[] =
26499 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26500 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26501 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
26502 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26503 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26506 static const struct arm_ext_table armv8r_ext_table
[] =
26508 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26509 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26510 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26511 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26512 ARM_REMOVE ("fp", ALL_FP
),
26513 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
26514 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26517 /* This list should, at a minimum, contain all the architecture names
26518 recognized by GCC. */
26519 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
26520 #define ARM_ARCH_OPT2(N, V, DF, ext) \
26521 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
26523 static const struct arm_arch_option_table arm_archs
[] =
26525 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26526 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26527 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26528 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26529 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26530 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26531 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26532 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26533 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26534 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26535 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26536 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26537 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26538 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26539 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
26540 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
26541 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
26542 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26543 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26544 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
26545 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
26546 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26547 kept to preserve existing behaviour. */
26548 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26549 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26550 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
26551 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
26552 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
26553 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26554 kept to preserve existing behaviour. */
26555 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26556 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26557 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26558 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26559 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
26560 /* The official spelling of the ARMv7 profile variants is the dashed form.
26561 Accept the non-dashed form for compatibility with old toolchains. */
26562 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26563 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
26564 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26565 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26566 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26567 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26568 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26569 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
26570 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26571 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
26573 ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
),
26574 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
26575 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
26576 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
26577 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
26578 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
26579 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
26580 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
26581 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26582 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26583 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
26584 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26586 #undef ARM_ARCH_OPT
26588 /* ISA extensions in the co-processor and main instruction set space. */
26590 struct arm_option_extension_value_table
26594 const arm_feature_set merge_value
;
26595 const arm_feature_set clear_value
;
26596 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26597 indicates that an extension is available for all architectures while
26598 ARM_ANY marks an empty entry. */
26599 const arm_feature_set allowed_archs
[2];
26602 /* The following table must be in alphabetical order with a NULL last entry. */
26604 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26605 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26607 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
26608 use the context sensitive approach using arm_ext_table's. */
26609 static const struct arm_option_extension_value_table arm_extensions
[] =
26611 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26612 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26613 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26614 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26615 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26616 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26617 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26619 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26620 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26621 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26622 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26623 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26624 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26625 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26627 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26628 | ARM_EXT2_FP16_FML
),
26629 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26630 | ARM_EXT2_FP16_FML
),
26632 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26633 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26634 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26635 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26636 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26637 Thumb divide instruction. Due to this having the same name as the
26638 previous entry, this will be ignored when doing command-line parsing and
26639 only considered by build attribute selection code. */
26640 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26641 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26642 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26643 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26644 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26645 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26646 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26647 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26648 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26649 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26650 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26651 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26652 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26653 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26654 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26655 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26656 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26657 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26658 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26659 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
26660 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
26662 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26663 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26664 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26665 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26666 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26667 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26668 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
26669 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
26671 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26672 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26673 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26674 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26675 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26676 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26677 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26678 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26680 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26681 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26682 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26683 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26684 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26688 /* ISA floating-point and Advanced SIMD extensions. */
26689 struct arm_option_fpu_value_table
26692 const arm_feature_set value
;
26695 /* This list should, at a minimum, contain all the fpu names
26696 recognized by GCC. */
26697 static const struct arm_option_fpu_value_table arm_fpus
[] =
26699 {"softfpa", FPU_NONE
},
26700 {"fpe", FPU_ARCH_FPE
},
26701 {"fpe2", FPU_ARCH_FPE
},
26702 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26703 {"fpa", FPU_ARCH_FPA
},
26704 {"fpa10", FPU_ARCH_FPA
},
26705 {"fpa11", FPU_ARCH_FPA
},
26706 {"arm7500fe", FPU_ARCH_FPA
},
26707 {"softvfp", FPU_ARCH_VFP
},
26708 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26709 {"vfp", FPU_ARCH_VFP_V2
},
26710 {"vfp9", FPU_ARCH_VFP_V2
},
26711 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26712 {"vfp10", FPU_ARCH_VFP_V2
},
26713 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26714 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26715 {"vfpv2", FPU_ARCH_VFP_V2
},
26716 {"vfpv3", FPU_ARCH_VFP_V3
},
26717 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26718 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26719 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26720 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26721 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26722 {"arm1020t", FPU_ARCH_VFP_V1
},
26723 {"arm1020e", FPU_ARCH_VFP_V2
},
26724 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26725 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26726 {"maverick", FPU_ARCH_MAVERICK
},
26727 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26728 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26729 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26730 {"vfpv4", FPU_ARCH_VFP_V4
},
26731 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26732 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26733 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26734 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26735 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26736 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26737 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26738 {"crypto-neon-fp-armv8",
26739 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26740 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26741 {"crypto-neon-fp-armv8.1",
26742 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26743 {NULL
, ARM_ARCH_NONE
}
26746 struct arm_option_value_table
26752 static const struct arm_option_value_table arm_float_abis
[] =
26754 {"hard", ARM_FLOAT_ABI_HARD
},
26755 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26756 {"soft", ARM_FLOAT_ABI_SOFT
},
26761 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26762 static const struct arm_option_value_table arm_eabis
[] =
26764 {"gnu", EF_ARM_EABI_UNKNOWN
},
26765 {"4", EF_ARM_EABI_VER4
},
26766 {"5", EF_ARM_EABI_VER5
},
26771 struct arm_long_option_table
26773 const char * option
; /* Substring to match. */
26774 const char * help
; /* Help information. */
26775 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26776 const char * deprecated
; /* If non-null, print this message. */
26780 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26781 arm_feature_set
*ext_set
,
26782 const struct arm_ext_table
*ext_table
)
26784 /* We insist on extensions being specified in alphabetical order, and with
26785 extensions being added before being removed. We achieve this by having
26786 the global ARM_EXTENSIONS table in alphabetical order, and using the
26787 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26788 or removing it (0) and only allowing it to change in the order
26790 const struct arm_option_extension_value_table
* opt
= NULL
;
26791 const arm_feature_set arm_any
= ARM_ANY
;
26792 int adding_value
= -1;
26794 while (str
!= NULL
&& *str
!= 0)
26801 as_bad (_("invalid architectural extension"));
26806 ext
= strchr (str
, '+');
26811 len
= strlen (str
);
26813 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26815 if (adding_value
!= 0)
26818 opt
= arm_extensions
;
26826 if (adding_value
== -1)
26829 opt
= arm_extensions
;
26831 else if (adding_value
!= 1)
26833 as_bad (_("must specify extensions to add before specifying "
26834 "those to remove"));
26841 as_bad (_("missing architectural extension"));
26845 gas_assert (adding_value
!= -1);
26846 gas_assert (opt
!= NULL
);
26848 if (ext_table
!= NULL
)
26850 const struct arm_ext_table
* ext_opt
= ext_table
;
26851 bfd_boolean found
= FALSE
;
26852 for (; ext_opt
->name
!= NULL
; ext_opt
++)
26853 if (ext_opt
->name_len
== len
26854 && strncmp (ext_opt
->name
, str
, len
) == 0)
26858 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
26859 /* TODO: Option not supported. When we remove the
26860 legacy table this case should error out. */
26863 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
26867 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
26868 /* TODO: Option not supported. When we remove the
26869 legacy table this case should error out. */
26871 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
26883 /* Scan over the options table trying to find an exact match. */
26884 for (; opt
->name
!= NULL
; opt
++)
26885 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26887 int i
, nb_allowed_archs
=
26888 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26889 /* Check we can apply the extension to this architecture. */
26890 for (i
= 0; i
< nb_allowed_archs
; i
++)
26893 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26895 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26898 if (i
== nb_allowed_archs
)
26900 as_bad (_("extension does not apply to the base architecture"));
26904 /* Add or remove the extension. */
26906 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
26908 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
26910 /* Allowing Thumb division instructions for ARMv7 in autodetection
26911 rely on this break so that duplicate extensions (extensions
26912 with the same name as a previous extension in the list) are not
26913 considered for command-line parsing. */
26917 if (opt
->name
== NULL
)
26919 /* Did we fail to find an extension because it wasn't specified in
26920 alphabetical order, or because it does not exist? */
26922 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26923 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26926 if (opt
->name
== NULL
)
26927 as_bad (_("unknown architectural extension `%s'"), str
);
26929 as_bad (_("architectural extensions must be specified in "
26930 "alphabetical order"));
26936 /* We should skip the extension we've just matched the next time
26948 arm_parse_cpu (const char *str
)
26950 const struct arm_cpu_option_table
*opt
;
26951 const char *ext
= strchr (str
, '+');
26957 len
= strlen (str
);
26961 as_bad (_("missing cpu name `%s'"), str
);
26965 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26966 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26968 mcpu_cpu_opt
= &opt
->value
;
26969 if (mcpu_ext_opt
== NULL
)
26970 mcpu_ext_opt
= XNEW (arm_feature_set
);
26971 *mcpu_ext_opt
= opt
->ext
;
26972 mcpu_fpu_opt
= &opt
->default_fpu
;
26973 if (opt
->canonical_name
)
26975 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26976 strcpy (selected_cpu_name
, opt
->canonical_name
);
26982 if (len
>= sizeof selected_cpu_name
)
26983 len
= (sizeof selected_cpu_name
) - 1;
26985 for (i
= 0; i
< len
; i
++)
26986 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26987 selected_cpu_name
[i
] = 0;
26991 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
26996 as_bad (_("unknown cpu `%s'"), str
);
27001 arm_parse_arch (const char *str
)
27003 const struct arm_arch_option_table
*opt
;
27004 const char *ext
= strchr (str
, '+');
27010 len
= strlen (str
);
27014 as_bad (_("missing architecture name `%s'"), str
);
27018 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
27019 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27021 march_cpu_opt
= &opt
->value
;
27022 if (march_ext_opt
== NULL
)
27023 march_ext_opt
= XNEW (arm_feature_set
);
27024 *march_ext_opt
= arm_arch_none
;
27025 march_fpu_opt
= &opt
->default_fpu
;
27026 strcpy (selected_cpu_name
, opt
->name
);
27029 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
27035 as_bad (_("unknown architecture `%s'\n"), str
);
27040 arm_parse_fpu (const char * str
)
27042 const struct arm_option_fpu_value_table
* opt
;
27044 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27045 if (streq (opt
->name
, str
))
27047 mfpu_opt
= &opt
->value
;
27051 as_bad (_("unknown floating point format `%s'\n"), str
);
27056 arm_parse_float_abi (const char * str
)
27058 const struct arm_option_value_table
* opt
;
27060 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
27061 if (streq (opt
->name
, str
))
27063 mfloat_abi_opt
= opt
->value
;
27067 as_bad (_("unknown floating point abi `%s'\n"), str
);
27073 arm_parse_eabi (const char * str
)
27075 const struct arm_option_value_table
*opt
;
27077 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
27078 if (streq (opt
->name
, str
))
27080 meabi_flags
= opt
->value
;
27083 as_bad (_("unknown EABI `%s'\n"), str
);
27089 arm_parse_it_mode (const char * str
)
27091 bfd_boolean ret
= TRUE
;
27093 if (streq ("arm", str
))
27094 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
27095 else if (streq ("thumb", str
))
27096 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
27097 else if (streq ("always", str
))
27098 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
27099 else if (streq ("never", str
))
27100 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
27103 as_bad (_("unknown implicit IT mode `%s', should be "\
27104 "arm, thumb, always, or never."), str
);
27112 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
27114 codecomposer_syntax
= TRUE
;
27115 arm_comment_chars
[0] = ';';
27116 arm_line_separator_chars
[0] = 0;
27120 struct arm_long_option_table arm_long_opts
[] =
27122 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
27123 arm_parse_cpu
, NULL
},
27124 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
27125 arm_parse_arch
, NULL
},
27126 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
27127 arm_parse_fpu
, NULL
},
27128 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
27129 arm_parse_float_abi
, NULL
},
27131 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
27132 arm_parse_eabi
, NULL
},
27134 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
27135 arm_parse_it_mode
, NULL
},
27136 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
27137 arm_ccs_mode
, NULL
},
27138 {NULL
, NULL
, 0, NULL
}
27142 md_parse_option (int c
, const char * arg
)
27144 struct arm_option_table
*opt
;
27145 const struct arm_legacy_option_table
*fopt
;
27146 struct arm_long_option_table
*lopt
;
27152 target_big_endian
= 1;
27158 target_big_endian
= 0;
27162 case OPTION_FIX_V4BX
:
27170 #endif /* OBJ_ELF */
27173 /* Listing option. Just ignore these, we don't support additional
27178 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27180 if (c
== opt
->option
[0]
27181 && ((arg
== NULL
&& opt
->option
[1] == 0)
27182 || streq (arg
, opt
->option
+ 1)))
27184 /* If the option is deprecated, tell the user. */
27185 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
27186 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27187 arg
? arg
: "", _(opt
->deprecated
));
27189 if (opt
->var
!= NULL
)
27190 *opt
->var
= opt
->value
;
27196 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
27198 if (c
== fopt
->option
[0]
27199 && ((arg
== NULL
&& fopt
->option
[1] == 0)
27200 || streq (arg
, fopt
->option
+ 1)))
27202 /* If the option is deprecated, tell the user. */
27203 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
27204 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27205 arg
? arg
: "", _(fopt
->deprecated
));
27207 if (fopt
->var
!= NULL
)
27208 *fopt
->var
= &fopt
->value
;
27214 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27216 /* These options are expected to have an argument. */
27217 if (c
== lopt
->option
[0]
27219 && strncmp (arg
, lopt
->option
+ 1,
27220 strlen (lopt
->option
+ 1)) == 0)
27222 /* If the option is deprecated, tell the user. */
27223 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
27224 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
27225 _(lopt
->deprecated
));
27227 /* Call the sup-option parser. */
27228 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
27239 md_show_usage (FILE * fp
)
27241 struct arm_option_table
*opt
;
27242 struct arm_long_option_table
*lopt
;
27244 fprintf (fp
, _(" ARM-specific assembler options:\n"));
27246 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27247 if (opt
->help
!= NULL
)
27248 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
27250 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27251 if (lopt
->help
!= NULL
)
27252 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
27256 -EB assemble code for a big-endian cpu\n"));
27261 -EL assemble code for a little-endian cpu\n"));
27265 --fix-v4bx Allow BX in ARMv4 code\n"));
27269 --fdpic generate an FDPIC object file\n"));
27270 #endif /* OBJ_ELF */
27278 arm_feature_set flags
;
27279 } cpu_arch_ver_table
;
27281 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27282 chronologically for architectures, with an exception for ARMv6-M and
27283 ARMv6S-M due to legacy reasons. No new architecture should have a
27284 special case. This allows for build attribute selection results to be
27285 stable when new architectures are added. */
27286 static const cpu_arch_ver_table cpu_arch_ver
[] =
27288 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27289 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27290 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27291 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27292 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27293 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27294 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27295 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27296 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27297 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27298 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27299 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27300 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27301 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27302 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27303 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27304 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27305 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27306 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27307 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27308 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27309 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27310 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27311 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27313 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27314 always selected build attributes to match those of ARMv6-M
27315 (resp. ARMv6S-M). However, due to these architectures being a strict
27316 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27317 would be selected when fully respecting chronology of architectures.
27318 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27319 move them before ARMv7 architectures. */
27320 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27321 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27323 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27324 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27325 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27326 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27327 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27328 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27329 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27330 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27331 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27332 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27333 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27334 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27335 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27336 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27337 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
27338 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
27339 {-1, ARM_ARCH_NONE
}
27342 /* Set an attribute if it has not already been set by the user. */
27345 aeabi_set_attribute_int (int tag
, int value
)
27348 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27349 || !attributes_set_explicitly
[tag
])
27350 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27354 aeabi_set_attribute_string (int tag
, const char *value
)
27357 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27358 || !attributes_set_explicitly
[tag
])
27359 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27362 /* Return whether features in the *NEEDED feature set are available via
27363 extensions for the architecture whose feature set is *ARCH_FSET. */
27366 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27367 const arm_feature_set
*needed
)
27369 int i
, nb_allowed_archs
;
27370 arm_feature_set ext_fset
;
27371 const struct arm_option_extension_value_table
*opt
;
27373 ext_fset
= arm_arch_none
;
27374 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27376 /* Extension does not provide any feature we need. */
27377 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27381 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27382 for (i
= 0; i
< nb_allowed_archs
; i
++)
27385 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27388 /* Extension is available, add it. */
27389 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27390 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27394 /* Can we enable all features in *needed? */
27395 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27398 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27399 a given architecture feature set *ARCH_EXT_FSET including extension feature
27400 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27401 - if true, check for an exact match of the architecture modulo extensions;
27402 - otherwise, select build attribute value of the first superset
27403 architecture released so that results remains stable when new architectures
27405 For -march/-mcpu=all the build attribute value of the most featureful
27406 architecture is returned. Tag_CPU_arch_profile result is returned in
27410 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27411 const arm_feature_set
*ext_fset
,
27412 char *profile
, int exact_match
)
27414 arm_feature_set arch_fset
;
27415 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27417 /* Select most featureful architecture with all its extensions if building
27418 for -march=all as the feature sets used to set build attributes. */
27419 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27421 /* Force revisiting of decision for each new architecture. */
27422 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27424 return TAG_CPU_ARCH_V8
;
27427 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27429 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27431 arm_feature_set known_arch_fset
;
27433 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27436 /* Base architecture match user-specified architecture and
27437 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27438 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27443 /* Base architecture match user-specified architecture only
27444 (eg. ARMv6-M in the same case as above). Record it in case we
27445 find a match with above condition. */
27446 else if (p_ver_ret
== NULL
27447 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27453 /* Architecture has all features wanted. */
27454 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27456 arm_feature_set added_fset
;
27458 /* Compute features added by this architecture over the one
27459 recorded in p_ver_ret. */
27460 if (p_ver_ret
!= NULL
)
27461 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27463 /* First architecture that match incl. with extensions, or the
27464 only difference in features over the recorded match is
27465 features that were optional and are now mandatory. */
27466 if (p_ver_ret
== NULL
27467 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27473 else if (p_ver_ret
== NULL
)
27475 arm_feature_set needed_ext_fset
;
27477 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27479 /* Architecture has all features needed when using some
27480 extensions. Record it and continue searching in case there
27481 exist an architecture providing all needed features without
27482 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27484 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27491 if (p_ver_ret
== NULL
)
27495 /* Tag_CPU_arch_profile. */
27496 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27497 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27498 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27499 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27501 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27503 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27507 return p_ver_ret
->val
;
27510 /* Set the public EABI object attributes. */
27513 aeabi_set_public_attributes (void)
27515 char profile
= '\0';
27518 int fp16_optional
= 0;
27519 int skip_exact_match
= 0;
27520 arm_feature_set flags
, flags_arch
, flags_ext
;
27522 /* Autodetection mode, choose the architecture based the instructions
27524 if (no_cpu_selected ())
27526 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27528 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27529 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27531 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27532 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27534 /* Code run during relaxation relies on selected_cpu being set. */
27535 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27536 flags_ext
= arm_arch_none
;
27537 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27538 selected_ext
= flags_ext
;
27539 selected_cpu
= flags
;
27541 /* Otherwise, choose the architecture based on the capabilities of the
27545 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27546 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27547 flags_ext
= selected_ext
;
27548 flags
= selected_cpu
;
27550 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27552 /* Allow the user to override the reported architecture. */
27553 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27555 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27556 flags_ext
= arm_arch_none
;
27559 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27561 /* When this function is run again after relaxation has happened there is no
27562 way to determine whether an architecture or CPU was specified by the user:
27563 - selected_cpu is set above for relaxation to work;
27564 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27565 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27566 Therefore, if not in -march=all case we first try an exact match and fall
27567 back to autodetection. */
27568 if (!skip_exact_match
)
27569 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27571 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27573 as_bad (_("no architecture contains all the instructions used\n"));
27575 /* Tag_CPU_name. */
27576 if (selected_cpu_name
[0])
27580 q
= selected_cpu_name
;
27581 if (strncmp (q
, "armv", 4) == 0)
27586 for (i
= 0; q
[i
]; i
++)
27587 q
[i
] = TOUPPER (q
[i
]);
27589 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27592 /* Tag_CPU_arch. */
27593 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27595 /* Tag_CPU_arch_profile. */
27596 if (profile
!= '\0')
27597 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27599 /* Tag_DSP_extension. */
27600 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27601 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27603 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27604 /* Tag_ARM_ISA_use. */
27605 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27606 || ARM_FEATURE_ZERO (flags_arch
))
27607 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27609 /* Tag_THUMB_ISA_use. */
27610 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27611 || ARM_FEATURE_ZERO (flags_arch
))
27615 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27616 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27618 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27622 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27625 /* Tag_VFP_arch. */
27626 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27627 aeabi_set_attribute_int (Tag_VFP_arch
,
27628 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27630 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27631 aeabi_set_attribute_int (Tag_VFP_arch
,
27632 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27634 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27637 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27639 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27641 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27644 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27645 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27646 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27647 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27648 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27650 /* Tag_ABI_HardFP_use. */
27651 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27652 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27653 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27655 /* Tag_WMMX_arch. */
27656 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27657 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27658 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27659 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27661 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27662 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27663 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27664 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27665 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27666 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27668 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27670 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27674 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27679 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27680 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27681 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27685 We set Tag_DIV_use to two when integer divide instructions have been used
27686 in ARM state, or when Thumb integer divide instructions have been used,
27687 but we have no architecture profile set, nor have we any ARM instructions.
27689 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27690 by the base architecture.
27692 For new architectures we will have to check these tests. */
27693 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27694 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27695 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27696 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27697 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27698 || (profile
== '\0'
27699 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27700 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27701 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27703 /* Tag_MP_extension_use. */
27704 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27705 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27707 /* Tag Virtualization_use. */
27708 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27710 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27713 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27716 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27717 finished and free extension feature bits which will not be used anymore. */
27720 arm_md_post_relax (void)
27722 aeabi_set_public_attributes ();
27723 XDELETE (mcpu_ext_opt
);
27724 mcpu_ext_opt
= NULL
;
27725 XDELETE (march_ext_opt
);
27726 march_ext_opt
= NULL
;
27729 /* Add the default contents for the .ARM.attributes section. */
27734 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27737 aeabi_set_public_attributes ();
27739 #endif /* OBJ_ELF */
27741 /* Parse a .cpu directive. */
27744 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27746 const struct arm_cpu_option_table
*opt
;
27750 name
= input_line_pointer
;
27751 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27752 input_line_pointer
++;
27753 saved_char
= *input_line_pointer
;
27754 *input_line_pointer
= 0;
27756 /* Skip the first "all" entry. */
27757 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27758 if (streq (opt
->name
, name
))
27760 selected_arch
= opt
->value
;
27761 selected_ext
= opt
->ext
;
27762 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27763 if (opt
->canonical_name
)
27764 strcpy (selected_cpu_name
, opt
->canonical_name
);
27768 for (i
= 0; opt
->name
[i
]; i
++)
27769 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27771 selected_cpu_name
[i
] = 0;
27773 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27775 *input_line_pointer
= saved_char
;
27776 demand_empty_rest_of_line ();
27779 as_bad (_("unknown cpu `%s'"), name
);
27780 *input_line_pointer
= saved_char
;
27781 ignore_rest_of_line ();
27784 /* Parse a .arch directive. */
27787 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27789 const struct arm_arch_option_table
*opt
;
27793 name
= input_line_pointer
;
27794 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27795 input_line_pointer
++;
27796 saved_char
= *input_line_pointer
;
27797 *input_line_pointer
= 0;
27799 /* Skip the first "all" entry. */
27800 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27801 if (streq (opt
->name
, name
))
27803 selected_arch
= opt
->value
;
27804 selected_ext
= arm_arch_none
;
27805 selected_cpu
= selected_arch
;
27806 strcpy (selected_cpu_name
, opt
->name
);
27807 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27808 *input_line_pointer
= saved_char
;
27809 demand_empty_rest_of_line ();
27813 as_bad (_("unknown architecture `%s'\n"), name
);
27814 *input_line_pointer
= saved_char
;
27815 ignore_rest_of_line ();
27818 /* Parse a .object_arch directive. */
27821 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27823 const struct arm_arch_option_table
*opt
;
27827 name
= input_line_pointer
;
27828 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27829 input_line_pointer
++;
27830 saved_char
= *input_line_pointer
;
27831 *input_line_pointer
= 0;
27833 /* Skip the first "all" entry. */
27834 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27835 if (streq (opt
->name
, name
))
27837 selected_object_arch
= opt
->value
;
27838 *input_line_pointer
= saved_char
;
27839 demand_empty_rest_of_line ();
27843 as_bad (_("unknown architecture `%s'\n"), name
);
27844 *input_line_pointer
= saved_char
;
27845 ignore_rest_of_line ();
27848 /* Parse a .arch_extension directive. */
27851 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27853 const struct arm_option_extension_value_table
*opt
;
27856 int adding_value
= 1;
27858 name
= input_line_pointer
;
27859 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27860 input_line_pointer
++;
27861 saved_char
= *input_line_pointer
;
27862 *input_line_pointer
= 0;
27864 if (strlen (name
) >= 2
27865 && strncmp (name
, "no", 2) == 0)
27871 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27872 if (streq (opt
->name
, name
))
27874 int i
, nb_allowed_archs
=
27875 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27876 for (i
= 0; i
< nb_allowed_archs
; i
++)
27879 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
27881 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
27885 if (i
== nb_allowed_archs
)
27887 as_bad (_("architectural extension `%s' is not allowed for the "
27888 "current base architecture"), name
);
27893 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
27896 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
27898 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27899 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27900 *input_line_pointer
= saved_char
;
27901 demand_empty_rest_of_line ();
27902 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27903 on this return so that duplicate extensions (extensions with the
27904 same name as a previous extension in the list) are not considered
27905 for command-line parsing. */
27909 if (opt
->name
== NULL
)
27910 as_bad (_("unknown architecture extension `%s'\n"), name
);
27912 *input_line_pointer
= saved_char
;
27913 ignore_rest_of_line ();
27916 /* Parse a .fpu directive. */
27919 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27921 const struct arm_option_fpu_value_table
*opt
;
27925 name
= input_line_pointer
;
27926 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27927 input_line_pointer
++;
27928 saved_char
= *input_line_pointer
;
27929 *input_line_pointer
= 0;
27931 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27932 if (streq (opt
->name
, name
))
27934 selected_fpu
= opt
->value
;
27935 #ifndef CPU_DEFAULT
27936 if (no_cpu_selected ())
27937 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
27940 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27941 *input_line_pointer
= saved_char
;
27942 demand_empty_rest_of_line ();
27946 as_bad (_("unknown floating point format `%s'\n"), name
);
27947 *input_line_pointer
= saved_char
;
27948 ignore_rest_of_line ();
27951 /* Copy symbol information. */
27954 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27956 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27960 /* Given a symbolic attribute NAME, return the proper integer value.
27961 Returns -1 if the attribute is not known. */
27964 arm_convert_symbolic_attribute (const char *name
)
27966 static const struct
27971 attribute_table
[] =
27973 /* When you modify this table you should
27974 also modify the list in doc/c-arm.texi. */
27975 #define T(tag) {#tag, tag}
27976 T (Tag_CPU_raw_name
),
27979 T (Tag_CPU_arch_profile
),
27980 T (Tag_ARM_ISA_use
),
27981 T (Tag_THUMB_ISA_use
),
27985 T (Tag_Advanced_SIMD_arch
),
27986 T (Tag_PCS_config
),
27987 T (Tag_ABI_PCS_R9_use
),
27988 T (Tag_ABI_PCS_RW_data
),
27989 T (Tag_ABI_PCS_RO_data
),
27990 T (Tag_ABI_PCS_GOT_use
),
27991 T (Tag_ABI_PCS_wchar_t
),
27992 T (Tag_ABI_FP_rounding
),
27993 T (Tag_ABI_FP_denormal
),
27994 T (Tag_ABI_FP_exceptions
),
27995 T (Tag_ABI_FP_user_exceptions
),
27996 T (Tag_ABI_FP_number_model
),
27997 T (Tag_ABI_align_needed
),
27998 T (Tag_ABI_align8_needed
),
27999 T (Tag_ABI_align_preserved
),
28000 T (Tag_ABI_align8_preserved
),
28001 T (Tag_ABI_enum_size
),
28002 T (Tag_ABI_HardFP_use
),
28003 T (Tag_ABI_VFP_args
),
28004 T (Tag_ABI_WMMX_args
),
28005 T (Tag_ABI_optimization_goals
),
28006 T (Tag_ABI_FP_optimization_goals
),
28007 T (Tag_compatibility
),
28008 T (Tag_CPU_unaligned_access
),
28009 T (Tag_FP_HP_extension
),
28010 T (Tag_VFP_HP_extension
),
28011 T (Tag_ABI_FP_16bit_format
),
28012 T (Tag_MPextension_use
),
28014 T (Tag_nodefaults
),
28015 T (Tag_also_compatible_with
),
28016 T (Tag_conformance
),
28018 T (Tag_Virtualization_use
),
28019 T (Tag_DSP_extension
),
28020 /* We deliberately do not include Tag_MPextension_use_legacy. */
28028 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
28029 if (streq (name
, attribute_table
[i
].name
))
28030 return attribute_table
[i
].tag
;
28035 /* Apply sym value for relocations only in the case that they are for
28036 local symbols in the same segment as the fixup and you have the
28037 respective architectural feature for blx and simple switches. */
28040 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
28043 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28044 /* PR 17444: If the local symbol is in a different section then a reloc
28045 will always be generated for it, so applying the symbol value now
28046 will result in a double offset being stored in the relocation. */
28047 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
28048 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
28050 switch (fixP
->fx_r_type
)
28052 case BFD_RELOC_ARM_PCREL_BLX
:
28053 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28054 if (ARM_IS_FUNC (fixP
->fx_addsy
))
28058 case BFD_RELOC_ARM_PCREL_CALL
:
28059 case BFD_RELOC_THUMB_PCREL_BLX
:
28060 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
28071 #endif /* OBJ_ELF */