1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_neon_ext_armv8
=
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
241 static const arm_feature_set fpu_crypto_ext_armv8
=
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
243 static const arm_feature_set crc_ext_armv8
=
244 ARM_FEATURE (0, CRC_EXT_ARMV8
);
246 static int mfloat_abi_opt
= -1;
247 /* Record user cpu selection for object attributes. */
248 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
249 /* Must be long enough to hold any of the names in arm_cpus. */
250 static char selected_cpu_name
[16];
252 /* Return if no cpu was selected on command-line. */
254 no_cpu_selected (void)
256 return selected_cpu
.core
== arm_arch_none
.core
257 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
262 static int meabi_flags
= EABI_DEFAULT
;
264 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
267 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
272 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
277 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
278 symbolS
* GOT_symbol
;
281 /* 0: assemble for ARM,
282 1: assemble for Thumb,
283 2: assemble for Thumb even though target CPU does not support thumb
285 static int thumb_mode
= 0;
286 /* A value distinct from the possible values for thumb_mode that we
287 can use to record whether thumb_mode has been copied into the
288 tc_frag_data field of a frag. */
289 #define MODE_RECORDED (1 << 4)
291 /* Specifies the intrinsic IT insn behavior mode. */
292 enum implicit_it_mode
294 IMPLICIT_IT_MODE_NEVER
= 0x00,
295 IMPLICIT_IT_MODE_ARM
= 0x01,
296 IMPLICIT_IT_MODE_THUMB
= 0x02,
297 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
299 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
301 /* If unified_syntax is true, we are processing the new unified
302 ARM/Thumb syntax. Important differences from the old ARM mode:
304 - Immediate operands do not require a # prefix.
305 - Conditional affixes always appear at the end of the
306 instruction. (For backward compatibility, those instructions
307 that formerly had them in the middle, continue to accept them
309 - The IT instruction may appear, and if it does is validated
310 against subsequent conditional affixes. It does not generate
313 Important differences from the old Thumb mode:
315 - Immediate operands do not require a # prefix.
316 - Most of the V6T2 instructions are only available in unified mode.
317 - The .N and .W suffixes are recognized and honored (it is an error
318 if they cannot be honored).
319 - All instructions set the flags if and only if they have an 's' affix.
320 - Conditional affixes may be used. They are validated against
321 preceding IT instructions. Unlike ARM mode, you cannot use a
322 conditional affix except in the scope of an IT instruction. */
324 static bfd_boolean unified_syntax
= FALSE
;
326 /* An immediate operand can start with #, and ld*, st*, pld operands
327 can contain [ and ]. We need to tell APP not to elide whitespace
328 before a [, which can appear as the first operand for pld.
329 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
330 const char arm_symbol_chars
[] = "#[]{}";
345 enum neon_el_type type
;
349 #define NEON_MAX_TYPE_ELS 4
353 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
357 enum it_instruction_type
362 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
363 if inside, should be the last one. */
364 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
365 i.e. BKPT and NOP. */
366 IT_INSN
/* The IT insn has been parsed. */
369 /* The maximum number of operands we need. */
370 #define ARM_IT_MAX_OPERANDS 6
375 unsigned long instruction
;
379 /* "uncond_value" is set to the value in place of the conditional field in
380 unconditional versions of the instruction, or -1 if nothing is
383 struct neon_type vectype
;
384 /* This does not indicate an actual NEON instruction, only that
385 the mnemonic accepts neon-style type suffixes. */
387 /* Set to the opcode if the instruction needs relaxation.
388 Zero if the instruction is not relaxed. */
392 bfd_reloc_code_real_type type
;
397 enum it_instruction_type it_insn_type
;
403 struct neon_type_el vectype
;
404 unsigned present
: 1; /* Operand present. */
405 unsigned isreg
: 1; /* Operand was a register. */
406 unsigned immisreg
: 1; /* .imm field is a second register. */
407 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
408 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
409 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
410 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
411 instructions. This allows us to disambiguate ARM <-> vector insns. */
412 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
413 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
414 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
415 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
416 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
417 unsigned writeback
: 1; /* Operand has trailing ! */
418 unsigned preind
: 1; /* Preindexed address. */
419 unsigned postind
: 1; /* Postindexed address. */
420 unsigned negative
: 1; /* Index register was negated. */
421 unsigned shifted
: 1; /* Shift applied to operation. */
422 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
423 } operands
[ARM_IT_MAX_OPERANDS
];
426 static struct arm_it inst
;
428 #define NUM_FLOAT_VALS 8
430 const char * fp_const
[] =
432 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
435 /* Number of littlenums required to hold an extended precision number. */
436 #define MAX_LITTLENUMS 6
438 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
448 #define CP_T_X 0x00008000
449 #define CP_T_Y 0x00400000
451 #define CONDS_BIT 0x00100000
452 #define LOAD_BIT 0x00100000
454 #define DOUBLE_LOAD_FLAG 0x00000001
458 const char * template_name
;
462 #define COND_ALWAYS 0xE
466 const char * template_name
;
470 struct asm_barrier_opt
472 const char * template_name
;
474 const arm_feature_set arch
;
477 /* The bit that distinguishes CPSR and SPSR. */
478 #define SPSR_BIT (1 << 22)
480 /* The individual PSR flag bits. */
481 #define PSR_c (1 << 16)
482 #define PSR_x (1 << 17)
483 #define PSR_s (1 << 18)
484 #define PSR_f (1 << 19)
489 bfd_reloc_code_real_type reloc
;
494 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
495 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
500 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
503 /* Bits for DEFINED field in neon_typed_alias. */
504 #define NTA_HASTYPE 1
505 #define NTA_HASINDEX 2
507 struct neon_typed_alias
509 unsigned char defined
;
511 struct neon_type_el eltype
;
514 /* ARM register categories. This includes coprocessor numbers and various
515 architecture extensions' registers. */
542 /* Structure for a hash table entry for a register.
543 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
544 information which states whether a vector type or index is specified (for a
545 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
551 unsigned char builtin
;
552 struct neon_typed_alias
* neon
;
555 /* Diagnostics used when we don't get a register of the expected type. */
556 const char * const reg_expected_msgs
[] =
558 N_("ARM register expected"),
559 N_("bad or missing co-processor number"),
560 N_("co-processor register expected"),
561 N_("FPA register expected"),
562 N_("VFP single precision register expected"),
563 N_("VFP/Neon double precision register expected"),
564 N_("Neon quad precision register expected"),
565 N_("VFP single or double precision register expected"),
566 N_("Neon double or quad precision register expected"),
567 N_("VFP single, double or Neon quad precision register expected"),
568 N_("VFP system register expected"),
569 N_("Maverick MVF register expected"),
570 N_("Maverick MVD register expected"),
571 N_("Maverick MVFX register expected"),
572 N_("Maverick MVDX register expected"),
573 N_("Maverick MVAX register expected"),
574 N_("Maverick DSPSC register expected"),
575 N_("iWMMXt data register expected"),
576 N_("iWMMXt control register expected"),
577 N_("iWMMXt scalar register expected"),
578 N_("XScale accumulator register expected"),
581 /* Some well known registers that we refer to directly elsewhere. */
587 /* ARM instructions take 4bytes in the object file, Thumb instructions
593 /* Basic string to match. */
594 const char * template_name
;
596 /* Parameters to instruction. */
597 unsigned int operands
[8];
599 /* Conditional tag - see opcode_lookup. */
600 unsigned int tag
: 4;
602 /* Basic instruction code. */
603 unsigned int avalue
: 28;
605 /* Thumb-format instruction code. */
608 /* Which architecture variant provides this instruction. */
609 const arm_feature_set
* avariant
;
610 const arm_feature_set
* tvariant
;
612 /* Function to call to encode instruction in ARM format. */
613 void (* aencode
) (void);
615 /* Function to call to encode instruction in Thumb format. */
616 void (* tencode
) (void);
619 /* Defines for various bits that we will want to toggle. */
620 #define INST_IMMEDIATE 0x02000000
621 #define OFFSET_REG 0x02000000
622 #define HWOFFSET_IMM 0x00400000
623 #define SHIFT_BY_REG 0x00000010
624 #define PRE_INDEX 0x01000000
625 #define INDEX_UP 0x00800000
626 #define WRITE_BACK 0x00200000
627 #define LDM_TYPE_2_OR_3 0x00400000
628 #define CPSI_MMOD 0x00020000
630 #define LITERAL_MASK 0xf000f000
631 #define OPCODE_MASK 0xfe1fffff
632 #define V4_STR_BIT 0x00000020
634 #define T2_SUBS_PC_LR 0xf3de8f00
636 #define DATA_OP_SHIFT 21
638 #define T2_OPCODE_MASK 0xfe1fffff
639 #define T2_DATA_OP_SHIFT 21
641 #define A_COND_MASK 0xf0000000
642 #define A_PUSH_POP_OP_MASK 0x0fff0000
644 /* Opcodes for pushing/poping registers to/from the stack. */
645 #define A1_OPCODE_PUSH 0x092d0000
646 #define A2_OPCODE_PUSH 0x052d0004
647 #define A2_OPCODE_POP 0x049d0004
649 /* Codes to distinguish the arithmetic instructions. */
660 #define OPCODE_CMP 10
661 #define OPCODE_CMN 11
662 #define OPCODE_ORR 12
663 #define OPCODE_MOV 13
664 #define OPCODE_BIC 14
665 #define OPCODE_MVN 15
667 #define T2_OPCODE_AND 0
668 #define T2_OPCODE_BIC 1
669 #define T2_OPCODE_ORR 2
670 #define T2_OPCODE_ORN 3
671 #define T2_OPCODE_EOR 4
672 #define T2_OPCODE_ADD 8
673 #define T2_OPCODE_ADC 10
674 #define T2_OPCODE_SBC 11
675 #define T2_OPCODE_SUB 13
676 #define T2_OPCODE_RSB 14
678 #define T_OPCODE_MUL 0x4340
679 #define T_OPCODE_TST 0x4200
680 #define T_OPCODE_CMN 0x42c0
681 #define T_OPCODE_NEG 0x4240
682 #define T_OPCODE_MVN 0x43c0
684 #define T_OPCODE_ADD_R3 0x1800
685 #define T_OPCODE_SUB_R3 0x1a00
686 #define T_OPCODE_ADD_HI 0x4400
687 #define T_OPCODE_ADD_ST 0xb000
688 #define T_OPCODE_SUB_ST 0xb080
689 #define T_OPCODE_ADD_SP 0xa800
690 #define T_OPCODE_ADD_PC 0xa000
691 #define T_OPCODE_ADD_I8 0x3000
692 #define T_OPCODE_SUB_I8 0x3800
693 #define T_OPCODE_ADD_I3 0x1c00
694 #define T_OPCODE_SUB_I3 0x1e00
696 #define T_OPCODE_ASR_R 0x4100
697 #define T_OPCODE_LSL_R 0x4080
698 #define T_OPCODE_LSR_R 0x40c0
699 #define T_OPCODE_ROR_R 0x41c0
700 #define T_OPCODE_ASR_I 0x1000
701 #define T_OPCODE_LSL_I 0x0000
702 #define T_OPCODE_LSR_I 0x0800
704 #define T_OPCODE_MOV_I8 0x2000
705 #define T_OPCODE_CMP_I8 0x2800
706 #define T_OPCODE_CMP_LR 0x4280
707 #define T_OPCODE_MOV_HR 0x4600
708 #define T_OPCODE_CMP_HR 0x4500
710 #define T_OPCODE_LDR_PC 0x4800
711 #define T_OPCODE_LDR_SP 0x9800
712 #define T_OPCODE_STR_SP 0x9000
713 #define T_OPCODE_LDR_IW 0x6800
714 #define T_OPCODE_STR_IW 0x6000
715 #define T_OPCODE_LDR_IH 0x8800
716 #define T_OPCODE_STR_IH 0x8000
717 #define T_OPCODE_LDR_IB 0x7800
718 #define T_OPCODE_STR_IB 0x7000
719 #define T_OPCODE_LDR_RW 0x5800
720 #define T_OPCODE_STR_RW 0x5000
721 #define T_OPCODE_LDR_RH 0x5a00
722 #define T_OPCODE_STR_RH 0x5200
723 #define T_OPCODE_LDR_RB 0x5c00
724 #define T_OPCODE_STR_RB 0x5400
726 #define T_OPCODE_PUSH 0xb400
727 #define T_OPCODE_POP 0xbc00
729 #define T_OPCODE_BRANCH 0xe000
731 #define THUMB_SIZE 2 /* Size of thumb instruction. */
732 #define THUMB_PP_PC_LR 0x0100
733 #define THUMB_LOAD_BIT 0x0800
734 #define THUMB2_LOAD_BIT 0x00100000
736 #define BAD_ARGS _("bad arguments to instruction")
737 #define BAD_SP _("r13 not allowed here")
738 #define BAD_PC _("r15 not allowed here")
739 #define BAD_COND _("instruction cannot be conditional")
740 #define BAD_OVERLAP _("registers may not be the same")
741 #define BAD_HIREG _("lo register required")
742 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
743 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
744 #define BAD_BRANCH _("branch must be last instruction in IT block")
745 #define BAD_NOT_IT _("instruction not allowed in IT block")
746 #define BAD_FPU _("selected FPU does not support instruction")
747 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
748 #define BAD_IT_COND _("incorrect condition in IT block")
749 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
750 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
751 #define BAD_PC_ADDRESSING \
752 _("cannot use register index with PC-relative addressing")
753 #define BAD_PC_WRITEBACK \
754 _("cannot use writeback with PC-relative addressing")
755 #define BAD_RANGE _("branch out of range")
756 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
758 static struct hash_control
* arm_ops_hsh
;
759 static struct hash_control
* arm_cond_hsh
;
760 static struct hash_control
* arm_shift_hsh
;
761 static struct hash_control
* arm_psr_hsh
;
762 static struct hash_control
* arm_v7m_psr_hsh
;
763 static struct hash_control
* arm_reg_hsh
;
764 static struct hash_control
* arm_reloc_hsh
;
765 static struct hash_control
* arm_barrier_opt_hsh
;
767 /* Stuff needed to resolve the label ambiguity
776 symbolS
* last_label_seen
;
777 static int label_is_thumb_function_name
= FALSE
;
779 /* Literal pool structure. Held on a per-section
780 and per-sub-section basis. */
782 #define MAX_LITERAL_POOL_SIZE 1024
783 typedef struct literal_pool
785 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
786 unsigned int next_free_entry
;
792 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
794 struct literal_pool
* next
;
797 /* Pointer to a linked list of literal pools. */
798 literal_pool
* list_of_pools
= NULL
;
800 typedef enum asmfunc_states
803 WAITING_ASMFUNC_NAME
,
807 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
810 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
812 static struct current_it now_it
;
816 now_it_compatible (int cond
)
818 return (cond
& ~1) == (now_it
.cc
& ~1);
822 conditional_insn (void)
824 return inst
.cond
!= COND_ALWAYS
;
827 static int in_it_block (void);
829 static int handle_it_state (void);
831 static void force_automatic_it_block_close (void);
833 static void it_fsm_post_encode (void);
835 #define set_it_insn_type(type) \
838 inst.it_insn_type = type; \
839 if (handle_it_state () == FAIL) \
844 #define set_it_insn_type_nonvoid(type, failret) \
847 inst.it_insn_type = type; \
848 if (handle_it_state () == FAIL) \
853 #define set_it_insn_type_last() \
856 if (inst.cond == COND_ALWAYS) \
857 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
859 set_it_insn_type (INSIDE_IT_LAST_INSN); \
865 /* This array holds the chars that always start a comment. If the
866 pre-processor is disabled, these aren't very useful. */
867 char arm_comment_chars
[] = "@";
869 /* This array holds the chars that only start a comment at the beginning of
870 a line. If the line seems to have the form '# 123 filename'
871 .line and .file directives will appear in the pre-processed output. */
872 /* Note that input_file.c hand checks for '#' at the beginning of the
873 first line of the input file. This is because the compiler outputs
874 #NO_APP at the beginning of its output. */
875 /* Also note that comments like this one will always work. */
876 const char line_comment_chars
[] = "#";
878 char arm_line_separator_chars
[] = ";";
880 /* Chars that can be used to separate mant
881 from exp in floating point numbers. */
882 const char EXP_CHARS
[] = "eE";
884 /* Chars that mean this number is a floating point constant. */
888 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
890 /* Prefix characters that indicate the start of an immediate
892 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
894 /* Separator character handling. */
896 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
899 skip_past_char (char ** str
, char c
)
901 /* PR gas/14987: Allow for whitespace before the expected character. */
902 skip_whitespace (*str
);
913 #define skip_past_comma(str) skip_past_char (str, ',')
915 /* Arithmetic expressions (possibly involving symbols). */
917 /* Return TRUE if anything in the expression is a bignum. */
920 walk_no_bignums (symbolS
* sp
)
922 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
925 if (symbol_get_value_expression (sp
)->X_add_symbol
)
927 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
928 || (symbol_get_value_expression (sp
)->X_op_symbol
929 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
935 static int in_my_get_expression
= 0;
937 /* Third argument to my_get_expression. */
938 #define GE_NO_PREFIX 0
939 #define GE_IMM_PREFIX 1
940 #define GE_OPT_PREFIX 2
941 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
942 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
943 #define GE_OPT_PREFIX_BIG 3
946 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
951 /* In unified syntax, all prefixes are optional. */
953 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
958 case GE_NO_PREFIX
: break;
960 if (!is_immediate_prefix (**str
))
962 inst
.error
= _("immediate expression requires a # prefix");
968 case GE_OPT_PREFIX_BIG
:
969 if (is_immediate_prefix (**str
))
975 memset (ep
, 0, sizeof (expressionS
));
977 save_in
= input_line_pointer
;
978 input_line_pointer
= *str
;
979 in_my_get_expression
= 1;
980 seg
= expression (ep
);
981 in_my_get_expression
= 0;
983 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
985 /* We found a bad or missing expression in md_operand(). */
986 *str
= input_line_pointer
;
987 input_line_pointer
= save_in
;
988 if (inst
.error
== NULL
)
989 inst
.error
= (ep
->X_op
== O_absent
990 ? _("missing expression") :_("bad expression"));
995 if (seg
!= absolute_section
996 && seg
!= text_section
997 && seg
!= data_section
998 && seg
!= bss_section
999 && seg
!= undefined_section
)
1001 inst
.error
= _("bad segment");
1002 *str
= input_line_pointer
;
1003 input_line_pointer
= save_in
;
1010 /* Get rid of any bignums now, so that we don't generate an error for which
1011 we can't establish a line number later on. Big numbers are never valid
1012 in instructions, which is where this routine is always called. */
1013 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1014 && (ep
->X_op
== O_big
1015 || (ep
->X_add_symbol
1016 && (walk_no_bignums (ep
->X_add_symbol
)
1018 && walk_no_bignums (ep
->X_op_symbol
))))))
1020 inst
.error
= _("invalid constant");
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1026 *str
= input_line_pointer
;
1027 input_line_pointer
= save_in
;
1031 /* Turn a string in input_line_pointer into a floating point constant
1032 of type TYPE, and store the appropriate bytes in *LITP. The number
1033 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1034 returned, or NULL on OK.
1036 Note that fp constants aren't represent in the normal way on the ARM.
1037 In big endian mode, things are as expected. However, in little endian
1038 mode fp constants are big-endian word-wise, and little-endian byte-wise
1039 within the words. For example, (double) 1.1 in big endian mode is
1040 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1041 the byte sequence 99 99 f1 3f 9a 99 99 99.
1043 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1046 md_atof (int type
, char * litP
, int * sizeP
)
1049 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1081 return _("Unrecognized or unsupported floating point constant");
1084 t
= atof_ieee (input_line_pointer
, type
, words
);
1086 input_line_pointer
= t
;
1087 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1089 if (target_big_endian
)
1091 for (i
= 0; i
< prec
; i
++)
1093 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1094 litP
+= sizeof (LITTLENUM_TYPE
);
1099 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1100 for (i
= prec
- 1; i
>= 0; i
--)
1102 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1103 litP
+= sizeof (LITTLENUM_TYPE
);
1106 /* For a 4 byte float the order of elements in `words' is 1 0.
1107 For an 8 byte float the order is 1 0 3 2. */
1108 for (i
= 0; i
< prec
; i
+= 2)
1110 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1111 sizeof (LITTLENUM_TYPE
));
1112 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1113 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1114 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1121 /* We handle all bad expressions here, so that we can report the faulty
1122 instruction in the error message. */
1124 md_operand (expressionS
* exp
)
1126 if (in_my_get_expression
)
1127 exp
->X_op
= O_illegal
;
1130 /* Immediate values. */
1132 /* Generic immediate-value read function for use in directives.
1133 Accepts anything that 'expression' can fold to a constant.
1134 *val receives the number. */
1137 immediate_for_directive (int *val
)
1140 exp
.X_op
= O_illegal
;
1142 if (is_immediate_prefix (*input_line_pointer
))
1144 input_line_pointer
++;
1148 if (exp
.X_op
!= O_constant
)
1150 as_bad (_("expected #constant"));
1151 ignore_rest_of_line ();
1154 *val
= exp
.X_add_number
;
1159 /* Register parsing. */
1161 /* Generic register parser. CCP points to what should be the
1162 beginning of a register name. If it is indeed a valid register
1163 name, advance CCP over it and return the reg_entry structure;
1164 otherwise return NULL. Does not issue diagnostics. */
1166 static struct reg_entry
*
1167 arm_reg_parse_multi (char **ccp
)
1171 struct reg_entry
*reg
;
1173 skip_whitespace (start
);
1175 #ifdef REGISTER_PREFIX
1176 if (*start
!= REGISTER_PREFIX
)
1180 #ifdef OPTIONAL_REGISTER_PREFIX
1181 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1186 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1191 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1193 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1203 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1204 enum arm_reg_type type
)
1206 /* Alternative syntaxes are accepted for a few register classes. */
1213 /* Generic coprocessor register names are allowed for these. */
1214 if (reg
&& reg
->type
== REG_TYPE_CN
)
1219 /* For backward compatibility, a bare number is valid here. */
1221 unsigned long processor
= strtoul (start
, ccp
, 10);
1222 if (*ccp
!= start
&& processor
<= 15)
1226 case REG_TYPE_MMXWC
:
1227 /* WC includes WCG. ??? I'm not sure this is true for all
1228 instructions that take WC registers. */
1229 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1240 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1241 return value is the register number or FAIL. */
1244 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1247 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1250 /* Do not allow a scalar (reg+index) to parse as a register. */
1251 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1254 if (reg
&& reg
->type
== type
)
1257 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1264 /* Parse a Neon type specifier. *STR should point at the leading '.'
1265 character. Does no verification at this stage that the type fits the opcode
1272 Can all be legally parsed by this function.
1274 Fills in neon_type struct pointer with parsed information, and updates STR
1275 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1276 type, FAIL if not. */
1279 parse_neon_type (struct neon_type
*type
, char **str
)
1286 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1288 enum neon_el_type thistype
= NT_untyped
;
1289 unsigned thissize
= -1u;
1296 /* Just a size without an explicit type. */
1300 switch (TOLOWER (*ptr
))
1302 case 'i': thistype
= NT_integer
; break;
1303 case 'f': thistype
= NT_float
; break;
1304 case 'p': thistype
= NT_poly
; break;
1305 case 's': thistype
= NT_signed
; break;
1306 case 'u': thistype
= NT_unsigned
; break;
1308 thistype
= NT_float
;
1313 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1319 /* .f is an abbreviation for .f32. */
1320 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1325 thissize
= strtoul (ptr
, &ptr
, 10);
1327 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1330 as_bad (_("bad size %d in type specifier"), thissize
);
1338 type
->el
[type
->elems
].type
= thistype
;
1339 type
->el
[type
->elems
].size
= thissize
;
1344 /* Empty/missing type is not a successful parse. */
1345 if (type
->elems
== 0)
1353 /* Errors may be set multiple times during parsing or bit encoding
1354 (particularly in the Neon bits), but usually the earliest error which is set
1355 will be the most meaningful. Avoid overwriting it with later (cascading)
1356 errors by calling this function. */
1359 first_error (const char *err
)
1365 /* Parse a single type, e.g. ".s32", leading period included. */
1367 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1370 struct neon_type optype
;
1374 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1376 if (optype
.elems
== 1)
1377 *vectype
= optype
.el
[0];
1380 first_error (_("only one type should be specified for operand"));
1386 first_error (_("vector type expected"));
1398 /* Special meanings for indices (which have a range of 0-7), which will fit into
1401 #define NEON_ALL_LANES 15
1402 #define NEON_INTERLEAVE_LANES 14
1404 /* Parse either a register or a scalar, with an optional type. Return the
1405 register number, and optionally fill in the actual type of the register
1406 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1407 type/index information in *TYPEINFO. */
1410 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1411 enum arm_reg_type
*rtype
,
1412 struct neon_typed_alias
*typeinfo
)
1415 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1416 struct neon_typed_alias atype
;
1417 struct neon_type_el parsetype
;
1421 atype
.eltype
.type
= NT_invtype
;
1422 atype
.eltype
.size
= -1;
1424 /* Try alternate syntax for some types of register. Note these are mutually
1425 exclusive with the Neon syntax extensions. */
1428 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1436 /* Undo polymorphism when a set of register types may be accepted. */
1437 if ((type
== REG_TYPE_NDQ
1438 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1439 || (type
== REG_TYPE_VFSD
1440 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1441 || (type
== REG_TYPE_NSDQ
1442 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1443 || reg
->type
== REG_TYPE_NQ
))
1444 || (type
== REG_TYPE_MMXWC
1445 && (reg
->type
== REG_TYPE_MMXWCG
)))
1446 type
= (enum arm_reg_type
) reg
->type
;
1448 if (type
!= reg
->type
)
1454 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1456 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1458 first_error (_("can't redefine type for operand"));
1461 atype
.defined
|= NTA_HASTYPE
;
1462 atype
.eltype
= parsetype
;
1465 if (skip_past_char (&str
, '[') == SUCCESS
)
1467 if (type
!= REG_TYPE_VFD
)
1469 first_error (_("only D registers may be indexed"));
1473 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1475 first_error (_("can't change index for operand"));
1479 atype
.defined
|= NTA_HASINDEX
;
1481 if (skip_past_char (&str
, ']') == SUCCESS
)
1482 atype
.index
= NEON_ALL_LANES
;
1487 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1489 if (exp
.X_op
!= O_constant
)
1491 first_error (_("constant expression required"));
1495 if (skip_past_char (&str
, ']') == FAIL
)
1498 atype
.index
= exp
.X_add_number
;
1513 /* Like arm_reg_parse, but allow allow the following extra features:
1514 - If RTYPE is non-zero, return the (possibly restricted) type of the
1515 register (e.g. Neon double or quad reg when either has been requested).
1516 - If this is a Neon vector type with additional type information, fill
1517 in the struct pointed to by VECTYPE (if non-NULL).
1518 This function will fault on encountering a scalar. */
1521 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1522 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1524 struct neon_typed_alias atype
;
1526 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1531 /* Do not allow regname(... to parse as a register. */
1535 /* Do not allow a scalar (reg+index) to parse as a register. */
1536 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1538 first_error (_("register operand expected, but got scalar"));
1543 *vectype
= atype
.eltype
;
1550 #define NEON_SCALAR_REG(X) ((X) >> 4)
1551 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1553 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1554 have enough information to be able to do a good job bounds-checking. So, we
1555 just do easy checks here, and do further checks later. */
1558 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1562 struct neon_typed_alias atype
;
1564 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1566 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1569 if (atype
.index
== NEON_ALL_LANES
)
1571 first_error (_("scalar must have an index"));
1574 else if (atype
.index
>= 64 / elsize
)
1576 first_error (_("scalar index out of range"));
1581 *type
= atype
.eltype
;
1585 return reg
* 16 + atype
.index
;
1588 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1591 parse_reg_list (char ** strp
)
1593 char * str
= * strp
;
1597 /* We come back here if we get ranges concatenated by '+' or '|'. */
1600 skip_whitespace (str
);
1614 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1616 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1626 first_error (_("bad range in register list"));
1630 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1632 if (range
& (1 << i
))
1634 (_("Warning: duplicated register (r%d) in register list"),
1642 if (range
& (1 << reg
))
1643 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1645 else if (reg
<= cur_reg
)
1646 as_tsktsk (_("Warning: register range not in ascending order"));
1651 while (skip_past_comma (&str
) != FAIL
1652 || (in_range
= 1, *str
++ == '-'));
1655 if (skip_past_char (&str
, '}') == FAIL
)
1657 first_error (_("missing `}'"));
1665 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1668 if (exp
.X_op
== O_constant
)
1670 if (exp
.X_add_number
1671 != (exp
.X_add_number
& 0x0000ffff))
1673 inst
.error
= _("invalid register mask");
1677 if ((range
& exp
.X_add_number
) != 0)
1679 int regno
= range
& exp
.X_add_number
;
1682 regno
= (1 << regno
) - 1;
1684 (_("Warning: duplicated register (r%d) in register list"),
1688 range
|= exp
.X_add_number
;
1692 if (inst
.reloc
.type
!= 0)
1694 inst
.error
= _("expression too complex");
1698 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1699 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1700 inst
.reloc
.pc_rel
= 0;
1704 if (*str
== '|' || *str
== '+')
1710 while (another_range
);
1716 /* Types of registers in a list. */
1725 /* Parse a VFP register list. If the string is invalid return FAIL.
1726 Otherwise return the number of registers, and set PBASE to the first
1727 register. Parses registers of type ETYPE.
1728 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1729 - Q registers can be used to specify pairs of D registers
1730 - { } can be omitted from around a singleton register list
1731 FIXME: This is not implemented, as it would require backtracking in
1734 This could be done (the meaning isn't really ambiguous), but doesn't
1735 fit in well with the current parsing framework.
1736 - 32 D registers may be used (also true for VFPv3).
1737 FIXME: Types are ignored in these register lists, which is probably a
1741 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1746 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1750 unsigned long mask
= 0;
1753 if (skip_past_char (&str
, '{') == FAIL
)
1755 inst
.error
= _("expecting {");
1762 regtype
= REG_TYPE_VFS
;
1767 regtype
= REG_TYPE_VFD
;
1770 case REGLIST_NEON_D
:
1771 regtype
= REG_TYPE_NDQ
;
1775 if (etype
!= REGLIST_VFP_S
)
1777 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1782 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1785 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1792 base_reg
= max_regs
;
1796 int setmask
= 1, addregs
= 1;
1798 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1800 if (new_base
== FAIL
)
1802 first_error (_(reg_expected_msgs
[regtype
]));
1806 if (new_base
>= max_regs
)
1808 first_error (_("register out of range in list"));
1812 /* Note: a value of 2 * n is returned for the register Q<n>. */
1813 if (regtype
== REG_TYPE_NQ
)
1819 if (new_base
< base_reg
)
1820 base_reg
= new_base
;
1822 if (mask
& (setmask
<< new_base
))
1824 first_error (_("invalid register list"));
1828 if ((mask
>> new_base
) != 0 && ! warned
)
1830 as_tsktsk (_("register list not in ascending order"));
1834 mask
|= setmask
<< new_base
;
1837 if (*str
== '-') /* We have the start of a range expression */
1843 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1846 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1850 if (high_range
>= max_regs
)
1852 first_error (_("register out of range in list"));
1856 if (regtype
== REG_TYPE_NQ
)
1857 high_range
= high_range
+ 1;
1859 if (high_range
<= new_base
)
1861 inst
.error
= _("register range not in ascending order");
1865 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1867 if (mask
& (setmask
<< new_base
))
1869 inst
.error
= _("invalid register list");
1873 mask
|= setmask
<< new_base
;
1878 while (skip_past_comma (&str
) != FAIL
);
1882 /* Sanity check -- should have raised a parse error above. */
1883 if (count
== 0 || count
> max_regs
)
1888 /* Final test -- the registers must be consecutive. */
1890 for (i
= 0; i
< count
; i
++)
1892 if ((mask
& (1u << i
)) == 0)
1894 inst
.error
= _("non-contiguous register range");
1904 /* True if two alias types are the same. */
1907 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1915 if (a
->defined
!= b
->defined
)
1918 if ((a
->defined
& NTA_HASTYPE
) != 0
1919 && (a
->eltype
.type
!= b
->eltype
.type
1920 || a
->eltype
.size
!= b
->eltype
.size
))
1923 if ((a
->defined
& NTA_HASINDEX
) != 0
1924 && (a
->index
!= b
->index
))
1930 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1931 The base register is put in *PBASE.
1932 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1934 The register stride (minus one) is put in bit 4 of the return value.
1935 Bits [6:5] encode the list length (minus one).
1936 The type of the list elements is put in *ELTYPE, if non-NULL. */
1938 #define NEON_LANE(X) ((X) & 0xf)
1939 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1940 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1943 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1944 struct neon_type_el
*eltype
)
1951 int leading_brace
= 0;
1952 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1953 const char *const incr_error
= _("register stride must be 1 or 2");
1954 const char *const type_error
= _("mismatched element/structure types in list");
1955 struct neon_typed_alias firsttype
;
1957 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1962 struct neon_typed_alias atype
;
1963 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1967 first_error (_(reg_expected_msgs
[rtype
]));
1974 if (rtype
== REG_TYPE_NQ
)
1980 else if (reg_incr
== -1)
1982 reg_incr
= getreg
- base_reg
;
1983 if (reg_incr
< 1 || reg_incr
> 2)
1985 first_error (_(incr_error
));
1989 else if (getreg
!= base_reg
+ reg_incr
* count
)
1991 first_error (_(incr_error
));
1995 if (! neon_alias_types_same (&atype
, &firsttype
))
1997 first_error (_(type_error
));
2001 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2005 struct neon_typed_alias htype
;
2006 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 else if (reg_incr
!= 1)
2018 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2022 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2025 first_error (_(reg_expected_msgs
[rtype
]));
2028 if (! neon_alias_types_same (&htype
, &firsttype
))
2030 first_error (_(type_error
));
2033 count
+= hireg
+ dregs
- getreg
;
2037 /* If we're using Q registers, we can't use [] or [n] syntax. */
2038 if (rtype
== REG_TYPE_NQ
)
2044 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2048 else if (lane
!= atype
.index
)
2050 first_error (_(type_error
));
2054 else if (lane
== -1)
2055 lane
= NEON_INTERLEAVE_LANES
;
2056 else if (lane
!= NEON_INTERLEAVE_LANES
)
2058 first_error (_(type_error
));
2063 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2065 /* No lane set by [x]. We must be interleaving structures. */
2067 lane
= NEON_INTERLEAVE_LANES
;
2070 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2071 || (count
> 1 && reg_incr
== -1))
2073 first_error (_("error parsing element/structure list"));
2077 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2079 first_error (_("expected }"));
2087 *eltype
= firsttype
.eltype
;
2092 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2095 /* Parse an explicit relocation suffix on an expression. This is
2096 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2097 arm_reloc_hsh contains no entries, so this function can only
2098 succeed if there is no () after the word. Returns -1 on error,
2099 BFD_RELOC_UNUSED if there wasn't any suffix. */
2102 parse_reloc (char **str
)
2104 struct reloc_entry
*r
;
2108 return BFD_RELOC_UNUSED
;
2113 while (*q
&& *q
!= ')' && *q
!= ',')
2118 if ((r
= (struct reloc_entry
*)
2119 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2126 /* Directives: register aliases. */
2128 static struct reg_entry
*
2129 insert_reg_alias (char *str
, unsigned number
, int type
)
2131 struct reg_entry
*new_reg
;
2134 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2136 if (new_reg
->builtin
)
2137 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2139 /* Only warn about a redefinition if it's not defined as the
2141 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2142 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2147 name
= xstrdup (str
);
2148 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2150 new_reg
->name
= name
;
2151 new_reg
->number
= number
;
2152 new_reg
->type
= type
;
2153 new_reg
->builtin
= FALSE
;
2154 new_reg
->neon
= NULL
;
2156 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2163 insert_neon_reg_alias (char *str
, int number
, int type
,
2164 struct neon_typed_alias
*atype
)
2166 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2170 first_error (_("attempt to redefine typed alias"));
2176 reg
->neon
= (struct neon_typed_alias
*)
2177 xmalloc (sizeof (struct neon_typed_alias
));
2178 *reg
->neon
= *atype
;
2182 /* Look for the .req directive. This is of the form:
2184 new_register_name .req existing_register_name
2186 If we find one, or if it looks sufficiently like one that we want to
2187 handle any error here, return TRUE. Otherwise return FALSE. */
2190 create_register_alias (char * newname
, char *p
)
2192 struct reg_entry
*old
;
2193 char *oldname
, *nbuf
;
2196 /* The input scrubber ensures that whitespace after the mnemonic is
2197 collapsed to single spaces. */
2199 if (strncmp (oldname
, " .req ", 6) != 0)
2203 if (*oldname
== '\0')
2206 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2209 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2213 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2214 the desired alias name, and p points to its end. If not, then
2215 the desired alias name is in the global original_case_string. */
2216 #ifdef TC_CASE_SENSITIVE
2219 newname
= original_case_string
;
2220 nlen
= strlen (newname
);
2223 nbuf
= (char *) alloca (nlen
+ 1);
2224 memcpy (nbuf
, newname
, nlen
);
2227 /* Create aliases under the new name as stated; an all-lowercase
2228 version of the new name; and an all-uppercase version of the new
2230 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2232 for (p
= nbuf
; *p
; p
++)
2235 if (strncmp (nbuf
, newname
, nlen
))
2237 /* If this attempt to create an additional alias fails, do not bother
2238 trying to create the all-lower case alias. We will fail and issue
2239 a second, duplicate error message. This situation arises when the
2240 programmer does something like:
2243 The second .req creates the "Foo" alias but then fails to create
2244 the artificial FOO alias because it has already been created by the
2246 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2250 for (p
= nbuf
; *p
; p
++)
2253 if (strncmp (nbuf
, newname
, nlen
))
2254 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2260 /* Create a Neon typed/indexed register alias using directives, e.g.:
2265 These typed registers can be used instead of the types specified after the
2266 Neon mnemonic, so long as all operands given have types. Types can also be
2267 specified directly, e.g.:
2268 vadd d0.s32, d1.s32, d2.s32 */
2271 create_neon_reg_alias (char *newname
, char *p
)
2273 enum arm_reg_type basetype
;
2274 struct reg_entry
*basereg
;
2275 struct reg_entry mybasereg
;
2276 struct neon_type ntype
;
2277 struct neon_typed_alias typeinfo
;
2278 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2281 typeinfo
.defined
= 0;
2282 typeinfo
.eltype
.type
= NT_invtype
;
2283 typeinfo
.eltype
.size
= -1;
2284 typeinfo
.index
= -1;
2288 if (strncmp (p
, " .dn ", 5) == 0)
2289 basetype
= REG_TYPE_VFD
;
2290 else if (strncmp (p
, " .qn ", 5) == 0)
2291 basetype
= REG_TYPE_NQ
;
2300 basereg
= arm_reg_parse_multi (&p
);
2302 if (basereg
&& basereg
->type
!= basetype
)
2304 as_bad (_("bad type for register"));
2308 if (basereg
== NULL
)
2311 /* Try parsing as an integer. */
2312 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2313 if (exp
.X_op
!= O_constant
)
2315 as_bad (_("expression must be constant"));
2318 basereg
= &mybasereg
;
2319 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2325 typeinfo
= *basereg
->neon
;
2327 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2329 /* We got a type. */
2330 if (typeinfo
.defined
& NTA_HASTYPE
)
2332 as_bad (_("can't redefine the type of a register alias"));
2336 typeinfo
.defined
|= NTA_HASTYPE
;
2337 if (ntype
.elems
!= 1)
2339 as_bad (_("you must specify a single type only"));
2342 typeinfo
.eltype
= ntype
.el
[0];
2345 if (skip_past_char (&p
, '[') == SUCCESS
)
2348 /* We got a scalar index. */
2350 if (typeinfo
.defined
& NTA_HASINDEX
)
2352 as_bad (_("can't redefine the index of a scalar alias"));
2356 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2358 if (exp
.X_op
!= O_constant
)
2360 as_bad (_("scalar index must be constant"));
2364 typeinfo
.defined
|= NTA_HASINDEX
;
2365 typeinfo
.index
= exp
.X_add_number
;
2367 if (skip_past_char (&p
, ']') == FAIL
)
2369 as_bad (_("expecting ]"));
2374 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2375 the desired alias name, and p points to its end. If not, then
2376 the desired alias name is in the global original_case_string. */
2377 #ifdef TC_CASE_SENSITIVE
2378 namelen
= nameend
- newname
;
2380 newname
= original_case_string
;
2381 namelen
= strlen (newname
);
2384 namebuf
= (char *) alloca (namelen
+ 1);
2385 strncpy (namebuf
, newname
, namelen
);
2386 namebuf
[namelen
] = '\0';
2388 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2389 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2391 /* Insert name in all uppercase. */
2392 for (p
= namebuf
; *p
; p
++)
2395 if (strncmp (namebuf
, newname
, namelen
))
2396 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2397 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2399 /* Insert name in all lowercase. */
2400 for (p
= namebuf
; *p
; p
++)
2403 if (strncmp (namebuf
, newname
, namelen
))
2404 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2405 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2410 /* Should never be called, as .req goes between the alias and the
2411 register name, not at the beginning of the line. */
2414 s_req (int a ATTRIBUTE_UNUSED
)
2416 as_bad (_("invalid syntax for .req directive"));
2420 s_dn (int a ATTRIBUTE_UNUSED
)
2422 as_bad (_("invalid syntax for .dn directive"));
2426 s_qn (int a ATTRIBUTE_UNUSED
)
2428 as_bad (_("invalid syntax for .qn directive"));
2431 /* The .unreq directive deletes an alias which was previously defined
2432 by .req. For example:
2438 s_unreq (int a ATTRIBUTE_UNUSED
)
2443 name
= input_line_pointer
;
2445 while (*input_line_pointer
!= 0
2446 && *input_line_pointer
!= ' '
2447 && *input_line_pointer
!= '\n')
2448 ++input_line_pointer
;
2450 saved_char
= *input_line_pointer
;
2451 *input_line_pointer
= 0;
2454 as_bad (_("invalid syntax for .unreq directive"));
2457 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2461 as_bad (_("unknown register alias '%s'"), name
);
2462 else if (reg
->builtin
)
2463 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2470 hash_delete (arm_reg_hsh
, name
, FALSE
);
2471 free ((char *) reg
->name
);
2476 /* Also locate the all upper case and all lower case versions.
2477 Do not complain if we cannot find one or the other as it
2478 was probably deleted above. */
2480 nbuf
= strdup (name
);
2481 for (p
= nbuf
; *p
; p
++)
2483 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2486 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2487 free ((char *) reg
->name
);
2493 for (p
= nbuf
; *p
; p
++)
2495 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2498 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2499 free ((char *) reg
->name
);
2509 *input_line_pointer
= saved_char
;
2510 demand_empty_rest_of_line ();
2513 /* Directives: Instruction set selection. */
2516 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2517 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2518 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2519 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2521 /* Create a new mapping symbol for the transition to STATE. */
2524 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2527 const char * symname
;
2534 type
= BSF_NO_FLAGS
;
2538 type
= BSF_NO_FLAGS
;
2542 type
= BSF_NO_FLAGS
;
2548 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2549 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2554 THUMB_SET_FUNC (symbolP
, 0);
2555 ARM_SET_THUMB (symbolP
, 0);
2556 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2570 /* Save the mapping symbols for future reference. Also check that
2571 we do not place two mapping symbols at the same offset within a
2572 frag. We'll handle overlap between frags in
2573 check_mapping_symbols.
2575 If .fill or other data filling directive generates zero sized data,
2576 the mapping symbol for the following code will have the same value
2577 as the one generated for the data filling directive. In this case,
2578 we replace the old symbol with the new one at the same address. */
2581 if (frag
->tc_frag_data
.first_map
!= NULL
)
2583 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2584 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2586 frag
->tc_frag_data
.first_map
= symbolP
;
2588 if (frag
->tc_frag_data
.last_map
!= NULL
)
2590 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2591 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2592 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2594 frag
->tc_frag_data
.last_map
= symbolP
;
2597 /* We must sometimes convert a region marked as code to data during
2598 code alignment, if an odd number of bytes have to be padded. The
2599 code mapping symbol is pushed to an aligned address. */
2602 insert_data_mapping_symbol (enum mstate state
,
2603 valueT value
, fragS
*frag
, offsetT bytes
)
2605 /* If there was already a mapping symbol, remove it. */
2606 if (frag
->tc_frag_data
.last_map
!= NULL
2607 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2609 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2613 know (frag
->tc_frag_data
.first_map
== symp
);
2614 frag
->tc_frag_data
.first_map
= NULL
;
2616 frag
->tc_frag_data
.last_map
= NULL
;
2617 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2620 make_mapping_symbol (MAP_DATA
, value
, frag
);
2621 make_mapping_symbol (state
, value
+ bytes
, frag
);
2624 static void mapping_state_2 (enum mstate state
, int max_chars
);
2626 /* Set the mapping state to STATE. Only call this when about to
2627 emit some STATE bytes to the file. */
2630 mapping_state (enum mstate state
)
2632 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2634 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2636 if (mapstate
== state
)
2637 /* The mapping symbol has already been emitted.
2638 There is nothing else to do. */
2641 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2643 All ARM instructions require 4-byte alignment.
2644 (Almost) all Thumb instructions require 2-byte alignment.
2646 When emitting instructions into any section, mark the section
2649 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2650 but themselves require 2-byte alignment; this applies to some
2651 PC- relative forms. However, these cases will invovle implicit
2652 literal pool generation or an explicit .align >=2, both of
2653 which will cause the section to me marked with sufficient
2654 alignment. Thus, we don't handle those cases here. */
2655 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2657 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2658 /* This case will be evaluated later in the next else. */
2660 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2661 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2663 /* Only add the symbol if the offset is > 0:
2664 if we're at the first frag, check it's size > 0;
2665 if we're not at the first frag, then for sure
2666 the offset is > 0. */
2667 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2668 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2671 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2674 mapping_state_2 (state
, 0);
2678 /* Same as mapping_state, but MAX_CHARS bytes have already been
2679 allocated. Put the mapping symbol that far back. */
2682 mapping_state_2 (enum mstate state
, int max_chars
)
2684 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2686 if (!SEG_NORMAL (now_seg
))
2689 if (mapstate
== state
)
2690 /* The mapping symbol has already been emitted.
2691 There is nothing else to do. */
2694 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2695 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2698 #define mapping_state(x) ((void)0)
2699 #define mapping_state_2(x, y) ((void)0)
2702 /* Find the real, Thumb encoded start of a Thumb function. */
2706 find_real_start (symbolS
* symbolP
)
2709 const char * name
= S_GET_NAME (symbolP
);
2710 symbolS
* new_target
;
2712 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2713 #define STUB_NAME ".real_start_of"
2718 /* The compiler may generate BL instructions to local labels because
2719 it needs to perform a branch to a far away location. These labels
2720 do not have a corresponding ".real_start_of" label. We check
2721 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2722 the ".real_start_of" convention for nonlocal branches. */
2723 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2726 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2727 new_target
= symbol_find (real_start
);
2729 if (new_target
== NULL
)
2731 as_warn (_("Failed to find real start of function: %s\n"), name
);
2732 new_target
= symbolP
;
2740 opcode_select (int width
)
2747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2748 as_bad (_("selected processor does not support THUMB opcodes"));
2751 /* No need to force the alignment, since we will have been
2752 coming from ARM mode, which is word-aligned. */
2753 record_alignment (now_seg
, 1);
2760 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2761 as_bad (_("selected processor does not support ARM opcodes"));
2766 frag_align (2, 0, 0);
2768 record_alignment (now_seg
, 1);
2773 as_bad (_("invalid instruction size selected (%d)"), width
);
2778 s_arm (int ignore ATTRIBUTE_UNUSED
)
2781 demand_empty_rest_of_line ();
2785 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2788 demand_empty_rest_of_line ();
2792 s_code (int unused ATTRIBUTE_UNUSED
)
2796 temp
= get_absolute_expression ();
2801 opcode_select (temp
);
2805 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2810 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2812 /* If we are not already in thumb mode go into it, EVEN if
2813 the target processor does not support thumb instructions.
2814 This is used by gcc/config/arm/lib1funcs.asm for example
2815 to compile interworking support functions even if the
2816 target processor should not support interworking. */
2820 record_alignment (now_seg
, 1);
2823 demand_empty_rest_of_line ();
2827 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2831 /* The following label is the name/address of the start of a Thumb function.
2832 We need to know this for the interworking support. */
2833 label_is_thumb_function_name
= TRUE
;
2836 /* Perform a .set directive, but also mark the alias as
2837 being a thumb function. */
2840 s_thumb_set (int equiv
)
2842 /* XXX the following is a duplicate of the code for s_set() in read.c
2843 We cannot just call that code as we need to get at the symbol that
2850 /* Especial apologies for the random logic:
2851 This just grew, and could be parsed much more simply!
2853 name
= input_line_pointer
;
2854 delim
= get_symbol_end ();
2855 end_name
= input_line_pointer
;
2858 if (*input_line_pointer
!= ',')
2861 as_bad (_("expected comma after name \"%s\""), name
);
2863 ignore_rest_of_line ();
2867 input_line_pointer
++;
2870 if (name
[0] == '.' && name
[1] == '\0')
2872 /* XXX - this should not happen to .thumb_set. */
2876 if ((symbolP
= symbol_find (name
)) == NULL
2877 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2880 /* When doing symbol listings, play games with dummy fragments living
2881 outside the normal fragment chain to record the file and line info
2883 if (listing
& LISTING_SYMBOLS
)
2885 extern struct list_info_struct
* listing_tail
;
2886 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2888 memset (dummy_frag
, 0, sizeof (fragS
));
2889 dummy_frag
->fr_type
= rs_fill
;
2890 dummy_frag
->line
= listing_tail
;
2891 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2892 dummy_frag
->fr_symbol
= symbolP
;
2896 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2899 /* "set" symbols are local unless otherwise specified. */
2900 SF_SET_LOCAL (symbolP
);
2901 #endif /* OBJ_COFF */
2902 } /* Make a new symbol. */
2904 symbol_table_insert (symbolP
);
2909 && S_IS_DEFINED (symbolP
)
2910 && S_GET_SEGMENT (symbolP
) != reg_section
)
2911 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2913 pseudo_set (symbolP
);
2915 demand_empty_rest_of_line ();
2917 /* XXX Now we come to the Thumb specific bit of code. */
2919 THUMB_SET_FUNC (symbolP
, 1);
2920 ARM_SET_THUMB (symbolP
, 1);
2921 #if defined OBJ_ELF || defined OBJ_COFF
2922 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2926 /* Directives: Mode selection. */
2928 /* .syntax [unified|divided] - choose the new unified syntax
2929 (same for Arm and Thumb encoding, modulo slight differences in what
2930 can be represented) or the old divergent syntax for each mode. */
2932 s_syntax (int unused ATTRIBUTE_UNUSED
)
2936 name
= input_line_pointer
;
2937 delim
= get_symbol_end ();
2939 if (!strcasecmp (name
, "unified"))
2940 unified_syntax
= TRUE
;
2941 else if (!strcasecmp (name
, "divided"))
2942 unified_syntax
= FALSE
;
2945 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2948 *input_line_pointer
= delim
;
2949 demand_empty_rest_of_line ();
2952 /* Directives: sectioning and alignment. */
2954 /* Same as s_align_ptwo but align 0 => align 2. */
2957 s_align (int unused ATTRIBUTE_UNUSED
)
2962 long max_alignment
= 15;
2964 temp
= get_absolute_expression ();
2965 if (temp
> max_alignment
)
2966 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2969 as_bad (_("alignment negative. 0 assumed."));
2973 if (*input_line_pointer
== ',')
2975 input_line_pointer
++;
2976 temp_fill
= get_absolute_expression ();
2988 /* Only make a frag if we HAVE to. */
2989 if (temp
&& !need_pass_2
)
2991 if (!fill_p
&& subseg_text_p (now_seg
))
2992 frag_align_code (temp
, 0);
2994 frag_align (temp
, (int) temp_fill
, 0);
2996 demand_empty_rest_of_line ();
2998 record_alignment (now_seg
, temp
);
3002 s_bss (int ignore ATTRIBUTE_UNUSED
)
3004 /* We don't support putting frags in the BSS segment, we fake it by
3005 marking in_bss, then looking at s_skip for clues. */
3006 subseg_set (bss_section
, 0);
3007 demand_empty_rest_of_line ();
3009 #ifdef md_elf_section_change_hook
3010 md_elf_section_change_hook ();
3015 s_even (int ignore ATTRIBUTE_UNUSED
)
3017 /* Never make frag if expect extra pass. */
3019 frag_align (1, 0, 0);
3021 record_alignment (now_seg
, 1);
3023 demand_empty_rest_of_line ();
3026 /* Directives: CodeComposer Studio. */
3028 /* .ref (for CodeComposer Studio syntax only). */
3030 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3032 if (codecomposer_syntax
)
3033 ignore_rest_of_line ();
3035 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3038 /* If name is not NULL, then it is used for marking the beginning of a
3039 function, wherease if it is NULL then it means the function end. */
3041 asmfunc_debug (const char * name
)
3043 static const char * last_name
= NULL
;
3047 gas_assert (last_name
== NULL
);
3050 if (debug_type
== DEBUG_STABS
)
3051 stabs_generate_asm_func (name
, name
);
3055 gas_assert (last_name
!= NULL
);
3057 if (debug_type
== DEBUG_STABS
)
3058 stabs_generate_asm_endfunc (last_name
, last_name
);
3065 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3067 if (codecomposer_syntax
)
3069 switch (asmfunc_state
)
3071 case OUTSIDE_ASMFUNC
:
3072 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3075 case WAITING_ASMFUNC_NAME
:
3076 as_bad (_(".asmfunc repeated."));
3079 case WAITING_ENDASMFUNC
:
3080 as_bad (_(".asmfunc without function."));
3083 demand_empty_rest_of_line ();
3086 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3090 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3092 if (codecomposer_syntax
)
3094 switch (asmfunc_state
)
3096 case OUTSIDE_ASMFUNC
:
3097 as_bad (_(".endasmfunc without a .asmfunc."));
3100 case WAITING_ASMFUNC_NAME
:
3101 as_bad (_(".endasmfunc without function."));
3104 case WAITING_ENDASMFUNC
:
3105 asmfunc_state
= OUTSIDE_ASMFUNC
;
3106 asmfunc_debug (NULL
);
3109 demand_empty_rest_of_line ();
3112 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3116 s_ccs_def (int name
)
3118 if (codecomposer_syntax
)
3121 as_bad (_(".def pseudo-op only available with -mccs flag."));
3124 /* Directives: Literal pools. */
3126 static literal_pool
*
3127 find_literal_pool (void)
3129 literal_pool
* pool
;
3131 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3133 if (pool
->section
== now_seg
3134 && pool
->sub_section
== now_subseg
)
3141 static literal_pool
*
3142 find_or_make_literal_pool (void)
3144 /* Next literal pool ID number. */
3145 static unsigned int latest_pool_num
= 1;
3146 literal_pool
* pool
;
3148 pool
= find_literal_pool ();
3152 /* Create a new pool. */
3153 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3157 pool
->next_free_entry
= 0;
3158 pool
->section
= now_seg
;
3159 pool
->sub_section
= now_subseg
;
3160 pool
->next
= list_of_pools
;
3161 pool
->symbol
= NULL
;
3163 /* Add it to the list. */
3164 list_of_pools
= pool
;
3167 /* New pools, and emptied pools, will have a NULL symbol. */
3168 if (pool
->symbol
== NULL
)
3170 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3171 (valueT
) 0, &zero_address_frag
);
3172 pool
->id
= latest_pool_num
++;
3179 /* Add the literal in the global 'inst'
3180 structure to the relevant literal pool. */
3183 add_to_lit_pool (void)
3185 literal_pool
* pool
;
3188 pool
= find_or_make_literal_pool ();
3190 /* Check if this literal value is already in the pool. */
3191 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3193 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3194 && (inst
.reloc
.exp
.X_op
== O_constant
)
3195 && (pool
->literals
[entry
].X_add_number
3196 == inst
.reloc
.exp
.X_add_number
)
3197 && (pool
->literals
[entry
].X_unsigned
3198 == inst
.reloc
.exp
.X_unsigned
))
3201 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3202 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3203 && (pool
->literals
[entry
].X_add_number
3204 == inst
.reloc
.exp
.X_add_number
)
3205 && (pool
->literals
[entry
].X_add_symbol
3206 == inst
.reloc
.exp
.X_add_symbol
)
3207 && (pool
->literals
[entry
].X_op_symbol
3208 == inst
.reloc
.exp
.X_op_symbol
))
3212 /* Do we need to create a new entry? */
3213 if (entry
== pool
->next_free_entry
)
3215 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3217 inst
.error
= _("literal pool overflow");
3221 pool
->literals
[entry
] = inst
.reloc
.exp
;
3223 /* PR ld/12974: Record the location of the first source line to reference
3224 this entry in the literal pool. If it turns out during linking that the
3225 symbol does not exist we will be able to give an accurate line number for
3226 the (first use of the) missing reference. */
3227 if (debug_type
== DEBUG_DWARF2
)
3228 dwarf2_where (pool
->locs
+ entry
);
3230 pool
->next_free_entry
+= 1;
3233 inst
.reloc
.exp
.X_op
= O_symbol
;
3234 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3235 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3241 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3243 bfd_boolean ret
= TRUE
;
3245 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3247 const char *label
= rest
;
3249 while (!is_end_of_line
[(int) label
[-1]])
3254 as_bad (_("Invalid label '%s'"), label
);
3258 asmfunc_debug (label
);
3260 asmfunc_state
= WAITING_ENDASMFUNC
;
3266 /* Can't use symbol_new here, so have to create a symbol and then at
3267 a later date assign it a value. Thats what these functions do. */
3270 symbol_locate (symbolS
* symbolP
,
3271 const char * name
, /* It is copied, the caller can modify. */
3272 segT segment
, /* Segment identifier (SEG_<something>). */
3273 valueT valu
, /* Symbol value. */
3274 fragS
* frag
) /* Associated fragment. */
3276 unsigned int name_length
;
3277 char * preserved_copy_of_name
;
3279 name_length
= strlen (name
) + 1; /* +1 for \0. */
3280 obstack_grow (¬es
, name
, name_length
);
3281 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3283 #ifdef tc_canonicalize_symbol_name
3284 preserved_copy_of_name
=
3285 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3288 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3290 S_SET_SEGMENT (symbolP
, segment
);
3291 S_SET_VALUE (symbolP
, valu
);
3292 symbol_clear_list_pointers (symbolP
);
3294 symbol_set_frag (symbolP
, frag
);
3296 /* Link to end of symbol chain. */
3298 extern int symbol_table_frozen
;
3300 if (symbol_table_frozen
)
3304 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3306 obj_symbol_new_hook (symbolP
);
3308 #ifdef tc_symbol_new_hook
3309 tc_symbol_new_hook (symbolP
);
3313 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3314 #endif /* DEBUG_SYMS */
3319 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3322 literal_pool
* pool
;
3325 pool
= find_literal_pool ();
3327 || pool
->symbol
== NULL
3328 || pool
->next_free_entry
== 0)
3331 /* Align pool as you have word accesses.
3332 Only make a frag if we have to. */
3334 frag_align (2, 0, 0);
3336 record_alignment (now_seg
, 2);
3339 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3340 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3342 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3344 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3345 (valueT
) frag_now_fix (), frag_now
);
3346 symbol_table_insert (pool
->symbol
);
3348 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3350 #if defined OBJ_COFF || defined OBJ_ELF
3351 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3354 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3357 if (debug_type
== DEBUG_DWARF2
)
3358 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3360 /* First output the expression in the instruction to the pool. */
3361 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3364 /* Mark the pool as empty. */
3365 pool
->next_free_entry
= 0;
3366 pool
->symbol
= NULL
;
3370 /* Forward declarations for functions below, in the MD interface
3372 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3373 static valueT
create_unwind_entry (int);
3374 static void start_unwind_section (const segT
, int);
3375 static void add_unwind_opcode (valueT
, int);
3376 static void flush_pending_unwind (void);
3378 /* Directives: Data. */
3381 s_arm_elf_cons (int nbytes
)
3385 #ifdef md_flush_pending_output
3386 md_flush_pending_output ();
3389 if (is_it_end_of_statement ())
3391 demand_empty_rest_of_line ();
3395 #ifdef md_cons_align
3396 md_cons_align (nbytes
);
3399 mapping_state (MAP_DATA
);
3403 char *base
= input_line_pointer
;
3407 if (exp
.X_op
!= O_symbol
)
3408 emit_expr (&exp
, (unsigned int) nbytes
);
3411 char *before_reloc
= input_line_pointer
;
3412 reloc
= parse_reloc (&input_line_pointer
);
3415 as_bad (_("unrecognized relocation suffix"));
3416 ignore_rest_of_line ();
3419 else if (reloc
== BFD_RELOC_UNUSED
)
3420 emit_expr (&exp
, (unsigned int) nbytes
);
3423 reloc_howto_type
*howto
= (reloc_howto_type
*)
3424 bfd_reloc_type_lookup (stdoutput
,
3425 (bfd_reloc_code_real_type
) reloc
);
3426 int size
= bfd_get_reloc_size (howto
);
3428 if (reloc
== BFD_RELOC_ARM_PLT32
)
3430 as_bad (_("(plt) is only valid on branch targets"));
3431 reloc
= BFD_RELOC_UNUSED
;
3436 as_bad (_("%s relocations do not fit in %d bytes"),
3437 howto
->name
, nbytes
);
3440 /* We've parsed an expression stopping at O_symbol.
3441 But there may be more expression left now that we
3442 have parsed the relocation marker. Parse it again.
3443 XXX Surely there is a cleaner way to do this. */
3444 char *p
= input_line_pointer
;
3446 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3447 memcpy (save_buf
, base
, input_line_pointer
- base
);
3448 memmove (base
+ (input_line_pointer
- before_reloc
),
3449 base
, before_reloc
- base
);
3451 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3453 memcpy (base
, save_buf
, p
- base
);
3455 offset
= nbytes
- size
;
3456 p
= frag_more ((int) nbytes
);
3457 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3458 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3463 while (*input_line_pointer
++ == ',');
3465 /* Put terminator back into stream. */
3466 input_line_pointer
--;
3467 demand_empty_rest_of_line ();
3470 /* Emit an expression containing a 32-bit thumb instruction.
3471 Implementation based on put_thumb32_insn. */
3474 emit_thumb32_expr (expressionS
* exp
)
3476 expressionS exp_high
= *exp
;
3478 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3479 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3480 exp
->X_add_number
&= 0xffff;
3481 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3484 /* Guess the instruction size based on the opcode. */
3487 thumb_insn_size (int opcode
)
3489 if ((unsigned int) opcode
< 0xe800u
)
3491 else if ((unsigned int) opcode
>= 0xe8000000u
)
3498 emit_insn (expressionS
*exp
, int nbytes
)
3502 if (exp
->X_op
== O_constant
)
3507 size
= thumb_insn_size (exp
->X_add_number
);
3511 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3513 as_bad (_(".inst.n operand too big. "\
3514 "Use .inst.w instead"));
3519 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3520 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3522 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3524 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3525 emit_thumb32_expr (exp
);
3527 emit_expr (exp
, (unsigned int) size
);
3529 it_fsm_post_encode ();
3533 as_bad (_("cannot determine Thumb instruction size. " \
3534 "Use .inst.n/.inst.w instead"));
3537 as_bad (_("constant expression required"));
3542 /* Like s_arm_elf_cons but do not use md_cons_align and
3543 set the mapping state to MAP_ARM/MAP_THUMB. */
3546 s_arm_elf_inst (int nbytes
)
3548 if (is_it_end_of_statement ())
3550 demand_empty_rest_of_line ();
3554 /* Calling mapping_state () here will not change ARM/THUMB,
3555 but will ensure not to be in DATA state. */
3558 mapping_state (MAP_THUMB
);
3563 as_bad (_("width suffixes are invalid in ARM mode"));
3564 ignore_rest_of_line ();
3570 mapping_state (MAP_ARM
);
3579 if (! emit_insn (& exp
, nbytes
))
3581 ignore_rest_of_line ();
3585 while (*input_line_pointer
++ == ',');
3587 /* Put terminator back into stream. */
3588 input_line_pointer
--;
3589 demand_empty_rest_of_line ();
3592 /* Parse a .rel31 directive. */
3595 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3602 if (*input_line_pointer
== '1')
3603 highbit
= 0x80000000;
3604 else if (*input_line_pointer
!= '0')
3605 as_bad (_("expected 0 or 1"));
3607 input_line_pointer
++;
3608 if (*input_line_pointer
!= ',')
3609 as_bad (_("missing comma"));
3610 input_line_pointer
++;
3612 #ifdef md_flush_pending_output
3613 md_flush_pending_output ();
3616 #ifdef md_cons_align
3620 mapping_state (MAP_DATA
);
3625 md_number_to_chars (p
, highbit
, 4);
3626 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3627 BFD_RELOC_ARM_PREL31
);
3629 demand_empty_rest_of_line ();
3632 /* Directives: AEABI stack-unwind tables. */
3634 /* Parse an unwind_fnstart directive. Simply records the current location. */
3637 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3639 demand_empty_rest_of_line ();
3640 if (unwind
.proc_start
)
3642 as_bad (_("duplicate .fnstart directive"));
3646 /* Mark the start of the function. */
3647 unwind
.proc_start
= expr_build_dot ();
3649 /* Reset the rest of the unwind info. */
3650 unwind
.opcode_count
= 0;
3651 unwind
.table_entry
= NULL
;
3652 unwind
.personality_routine
= NULL
;
3653 unwind
.personality_index
= -1;
3654 unwind
.frame_size
= 0;
3655 unwind
.fp_offset
= 0;
3656 unwind
.fp_reg
= REG_SP
;
3658 unwind
.sp_restored
= 0;
3662 /* Parse a handlerdata directive. Creates the exception handling table entry
3663 for the function. */
3666 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3668 demand_empty_rest_of_line ();
3669 if (!unwind
.proc_start
)
3670 as_bad (MISSING_FNSTART
);
3672 if (unwind
.table_entry
)
3673 as_bad (_("duplicate .handlerdata directive"));
3675 create_unwind_entry (1);
3678 /* Parse an unwind_fnend directive. Generates the index table entry. */
3681 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3686 unsigned int marked_pr_dependency
;
3688 demand_empty_rest_of_line ();
3690 if (!unwind
.proc_start
)
3692 as_bad (_(".fnend directive without .fnstart"));
3696 /* Add eh table entry. */
3697 if (unwind
.table_entry
== NULL
)
3698 val
= create_unwind_entry (0);
3702 /* Add index table entry. This is two words. */
3703 start_unwind_section (unwind
.saved_seg
, 1);
3704 frag_align (2, 0, 0);
3705 record_alignment (now_seg
, 2);
3707 ptr
= frag_more (8);
3709 where
= frag_now_fix () - 8;
3711 /* Self relative offset of the function start. */
3712 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3713 BFD_RELOC_ARM_PREL31
);
3715 /* Indicate dependency on EHABI-defined personality routines to the
3716 linker, if it hasn't been done already. */
3717 marked_pr_dependency
3718 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3719 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3720 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3722 static const char *const name
[] =
3724 "__aeabi_unwind_cpp_pr0",
3725 "__aeabi_unwind_cpp_pr1",
3726 "__aeabi_unwind_cpp_pr2"
3728 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3729 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3730 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3731 |= 1 << unwind
.personality_index
;
3735 /* Inline exception table entry. */
3736 md_number_to_chars (ptr
+ 4, val
, 4);
3738 /* Self relative offset of the table entry. */
3739 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3740 BFD_RELOC_ARM_PREL31
);
3742 /* Restore the original section. */
3743 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3745 unwind
.proc_start
= NULL
;
3749 /* Parse an unwind_cantunwind directive. */
3752 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3754 demand_empty_rest_of_line ();
3755 if (!unwind
.proc_start
)
3756 as_bad (MISSING_FNSTART
);
3758 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3759 as_bad (_("personality routine specified for cantunwind frame"));
3761 unwind
.personality_index
= -2;
3765 /* Parse a personalityindex directive. */
3768 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3772 if (!unwind
.proc_start
)
3773 as_bad (MISSING_FNSTART
);
3775 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3776 as_bad (_("duplicate .personalityindex directive"));
3780 if (exp
.X_op
!= O_constant
3781 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3783 as_bad (_("bad personality routine number"));
3784 ignore_rest_of_line ();
3788 unwind
.personality_index
= exp
.X_add_number
;
3790 demand_empty_rest_of_line ();
3794 /* Parse a personality directive. */
3797 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3801 if (!unwind
.proc_start
)
3802 as_bad (MISSING_FNSTART
);
3804 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3805 as_bad (_("duplicate .personality directive"));
3807 name
= input_line_pointer
;
3808 c
= get_symbol_end ();
3809 p
= input_line_pointer
;
3810 unwind
.personality_routine
= symbol_find_or_make (name
);
3812 demand_empty_rest_of_line ();
3816 /* Parse a directive saving core registers. */
3819 s_arm_unwind_save_core (void)
3825 range
= parse_reg_list (&input_line_pointer
);
3828 as_bad (_("expected register list"));
3829 ignore_rest_of_line ();
3833 demand_empty_rest_of_line ();
3835 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3836 into .unwind_save {..., sp...}. We aren't bothered about the value of
3837 ip because it is clobbered by calls. */
3838 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3839 && (range
& 0x3000) == 0x1000)
3841 unwind
.opcode_count
--;
3842 unwind
.sp_restored
= 0;
3843 range
= (range
| 0x2000) & ~0x1000;
3844 unwind
.pending_offset
= 0;
3850 /* See if we can use the short opcodes. These pop a block of up to 8
3851 registers starting with r4, plus maybe r14. */
3852 for (n
= 0; n
< 8; n
++)
3854 /* Break at the first non-saved register. */
3855 if ((range
& (1 << (n
+ 4))) == 0)
3858 /* See if there are any other bits set. */
3859 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3861 /* Use the long form. */
3862 op
= 0x8000 | ((range
>> 4) & 0xfff);
3863 add_unwind_opcode (op
, 2);
3867 /* Use the short form. */
3869 op
= 0xa8; /* Pop r14. */
3871 op
= 0xa0; /* Do not pop r14. */
3873 add_unwind_opcode (op
, 1);
3880 op
= 0xb100 | (range
& 0xf);
3881 add_unwind_opcode (op
, 2);
3884 /* Record the number of bytes pushed. */
3885 for (n
= 0; n
< 16; n
++)
3887 if (range
& (1 << n
))
3888 unwind
.frame_size
+= 4;
3893 /* Parse a directive saving FPA registers. */
3896 s_arm_unwind_save_fpa (int reg
)
3902 /* Get Number of registers to transfer. */
3903 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3906 exp
.X_op
= O_illegal
;
3908 if (exp
.X_op
!= O_constant
)
3910 as_bad (_("expected , <constant>"));
3911 ignore_rest_of_line ();
3915 num_regs
= exp
.X_add_number
;
3917 if (num_regs
< 1 || num_regs
> 4)
3919 as_bad (_("number of registers must be in the range [1:4]"));
3920 ignore_rest_of_line ();
3924 demand_empty_rest_of_line ();
3929 op
= 0xb4 | (num_regs
- 1);
3930 add_unwind_opcode (op
, 1);
3935 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3936 add_unwind_opcode (op
, 2);
3938 unwind
.frame_size
+= num_regs
* 12;
3942 /* Parse a directive saving VFP registers for ARMv6 and above. */
3945 s_arm_unwind_save_vfp_armv6 (void)
3950 int num_vfpv3_regs
= 0;
3951 int num_regs_below_16
;
3953 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3956 as_bad (_("expected register list"));
3957 ignore_rest_of_line ();
3961 demand_empty_rest_of_line ();
3963 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3964 than FSTMX/FLDMX-style ones). */
3966 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3968 num_vfpv3_regs
= count
;
3969 else if (start
+ count
> 16)
3970 num_vfpv3_regs
= start
+ count
- 16;
3972 if (num_vfpv3_regs
> 0)
3974 int start_offset
= start
> 16 ? start
- 16 : 0;
3975 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3976 add_unwind_opcode (op
, 2);
3979 /* Generate opcode for registers numbered in the range 0 .. 15. */
3980 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3981 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3982 if (num_regs_below_16
> 0)
3984 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3985 add_unwind_opcode (op
, 2);
3988 unwind
.frame_size
+= count
* 8;
3992 /* Parse a directive saving VFP registers for pre-ARMv6. */
3995 s_arm_unwind_save_vfp (void)
4001 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4004 as_bad (_("expected register list"));
4005 ignore_rest_of_line ();
4009 demand_empty_rest_of_line ();
4014 op
= 0xb8 | (count
- 1);
4015 add_unwind_opcode (op
, 1);
4020 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4021 add_unwind_opcode (op
, 2);
4023 unwind
.frame_size
+= count
* 8 + 4;
4027 /* Parse a directive saving iWMMXt data registers. */
4030 s_arm_unwind_save_mmxwr (void)
4038 if (*input_line_pointer
== '{')
4039 input_line_pointer
++;
4043 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4047 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4052 as_tsktsk (_("register list not in ascending order"));
4055 if (*input_line_pointer
== '-')
4057 input_line_pointer
++;
4058 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4061 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4064 else if (reg
>= hi_reg
)
4066 as_bad (_("bad register range"));
4069 for (; reg
< hi_reg
; reg
++)
4073 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4075 skip_past_char (&input_line_pointer
, '}');
4077 demand_empty_rest_of_line ();
4079 /* Generate any deferred opcodes because we're going to be looking at
4081 flush_pending_unwind ();
4083 for (i
= 0; i
< 16; i
++)
4085 if (mask
& (1 << i
))
4086 unwind
.frame_size
+= 8;
4089 /* Attempt to combine with a previous opcode. We do this because gcc
4090 likes to output separate unwind directives for a single block of
4092 if (unwind
.opcode_count
> 0)
4094 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4095 if ((i
& 0xf8) == 0xc0)
4098 /* Only merge if the blocks are contiguous. */
4101 if ((mask
& 0xfe00) == (1 << 9))
4103 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4104 unwind
.opcode_count
--;
4107 else if (i
== 6 && unwind
.opcode_count
>= 2)
4109 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4113 op
= 0xffff << (reg
- 1);
4115 && ((mask
& op
) == (1u << (reg
- 1))))
4117 op
= (1 << (reg
+ i
+ 1)) - 1;
4118 op
&= ~((1 << reg
) - 1);
4120 unwind
.opcode_count
-= 2;
4127 /* We want to generate opcodes in the order the registers have been
4128 saved, ie. descending order. */
4129 for (reg
= 15; reg
>= -1; reg
--)
4131 /* Save registers in blocks. */
4133 || !(mask
& (1 << reg
)))
4135 /* We found an unsaved reg. Generate opcodes to save the
4142 op
= 0xc0 | (hi_reg
- 10);
4143 add_unwind_opcode (op
, 1);
4148 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4149 add_unwind_opcode (op
, 2);
4158 ignore_rest_of_line ();
4162 s_arm_unwind_save_mmxwcg (void)
4169 if (*input_line_pointer
== '{')
4170 input_line_pointer
++;
4172 skip_whitespace (input_line_pointer
);
4176 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4180 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4186 as_tsktsk (_("register list not in ascending order"));
4189 if (*input_line_pointer
== '-')
4191 input_line_pointer
++;
4192 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4195 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4198 else if (reg
>= hi_reg
)
4200 as_bad (_("bad register range"));
4203 for (; reg
< hi_reg
; reg
++)
4207 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4209 skip_past_char (&input_line_pointer
, '}');
4211 demand_empty_rest_of_line ();
4213 /* Generate any deferred opcodes because we're going to be looking at
4215 flush_pending_unwind ();
4217 for (reg
= 0; reg
< 16; reg
++)
4219 if (mask
& (1 << reg
))
4220 unwind
.frame_size
+= 4;
4223 add_unwind_opcode (op
, 2);
4226 ignore_rest_of_line ();
4230 /* Parse an unwind_save directive.
4231 If the argument is non-zero, this is a .vsave directive. */
4234 s_arm_unwind_save (int arch_v6
)
4237 struct reg_entry
*reg
;
4238 bfd_boolean had_brace
= FALSE
;
4240 if (!unwind
.proc_start
)
4241 as_bad (MISSING_FNSTART
);
4243 /* Figure out what sort of save we have. */
4244 peek
= input_line_pointer
;
4252 reg
= arm_reg_parse_multi (&peek
);
4256 as_bad (_("register expected"));
4257 ignore_rest_of_line ();
4266 as_bad (_("FPA .unwind_save does not take a register list"));
4267 ignore_rest_of_line ();
4270 input_line_pointer
= peek
;
4271 s_arm_unwind_save_fpa (reg
->number
);
4275 s_arm_unwind_save_core ();
4280 s_arm_unwind_save_vfp_armv6 ();
4282 s_arm_unwind_save_vfp ();
4285 case REG_TYPE_MMXWR
:
4286 s_arm_unwind_save_mmxwr ();
4289 case REG_TYPE_MMXWCG
:
4290 s_arm_unwind_save_mmxwcg ();
4294 as_bad (_(".unwind_save does not support this kind of register"));
4295 ignore_rest_of_line ();
4300 /* Parse an unwind_movsp directive. */
4303 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4309 if (!unwind
.proc_start
)
4310 as_bad (MISSING_FNSTART
);
4312 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4315 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4316 ignore_rest_of_line ();
4320 /* Optional constant. */
4321 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4323 if (immediate_for_directive (&offset
) == FAIL
)
4329 demand_empty_rest_of_line ();
4331 if (reg
== REG_SP
|| reg
== REG_PC
)
4333 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4337 if (unwind
.fp_reg
!= REG_SP
)
4338 as_bad (_("unexpected .unwind_movsp directive"));
4340 /* Generate opcode to restore the value. */
4342 add_unwind_opcode (op
, 1);
4344 /* Record the information for later. */
4345 unwind
.fp_reg
= reg
;
4346 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4347 unwind
.sp_restored
= 1;
4350 /* Parse an unwind_pad directive. */
4353 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4357 if (!unwind
.proc_start
)
4358 as_bad (MISSING_FNSTART
);
4360 if (immediate_for_directive (&offset
) == FAIL
)
4365 as_bad (_("stack increment must be multiple of 4"));
4366 ignore_rest_of_line ();
4370 /* Don't generate any opcodes, just record the details for later. */
4371 unwind
.frame_size
+= offset
;
4372 unwind
.pending_offset
+= offset
;
4374 demand_empty_rest_of_line ();
4377 /* Parse an unwind_setfp directive. */
4380 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4386 if (!unwind
.proc_start
)
4387 as_bad (MISSING_FNSTART
);
4389 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4390 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4393 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4395 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4397 as_bad (_("expected <reg>, <reg>"));
4398 ignore_rest_of_line ();
4402 /* Optional constant. */
4403 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4405 if (immediate_for_directive (&offset
) == FAIL
)
4411 demand_empty_rest_of_line ();
4413 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4415 as_bad (_("register must be either sp or set by a previous"
4416 "unwind_movsp directive"));
4420 /* Don't generate any opcodes, just record the information for later. */
4421 unwind
.fp_reg
= fp_reg
;
4423 if (sp_reg
== REG_SP
)
4424 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4426 unwind
.fp_offset
-= offset
;
4429 /* Parse an unwind_raw directive. */
4432 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4435 /* This is an arbitrary limit. */
4436 unsigned char op
[16];
4439 if (!unwind
.proc_start
)
4440 as_bad (MISSING_FNSTART
);
4443 if (exp
.X_op
== O_constant
4444 && skip_past_comma (&input_line_pointer
) != FAIL
)
4446 unwind
.frame_size
+= exp
.X_add_number
;
4450 exp
.X_op
= O_illegal
;
4452 if (exp
.X_op
!= O_constant
)
4454 as_bad (_("expected <offset>, <opcode>"));
4455 ignore_rest_of_line ();
4461 /* Parse the opcode. */
4466 as_bad (_("unwind opcode too long"));
4467 ignore_rest_of_line ();
4469 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4471 as_bad (_("invalid unwind opcode"));
4472 ignore_rest_of_line ();
4475 op
[count
++] = exp
.X_add_number
;
4477 /* Parse the next byte. */
4478 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4484 /* Add the opcode bytes in reverse order. */
4486 add_unwind_opcode (op
[count
], 1);
4488 demand_empty_rest_of_line ();
4492 /* Parse a .eabi_attribute directive. */
4495 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4497 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4499 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4500 attributes_set_explicitly
[tag
] = 1;
4503 /* Emit a tls fix for the symbol. */
4506 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4510 #ifdef md_flush_pending_output
4511 md_flush_pending_output ();
4514 #ifdef md_cons_align
4518 /* Since we're just labelling the code, there's no need to define a
4521 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4522 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4523 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4524 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4526 #endif /* OBJ_ELF */
4528 static void s_arm_arch (int);
4529 static void s_arm_object_arch (int);
4530 static void s_arm_cpu (int);
4531 static void s_arm_fpu (int);
4532 static void s_arm_arch_extension (int);
4537 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4544 if (exp
.X_op
== O_symbol
)
4545 exp
.X_op
= O_secrel
;
4547 emit_expr (&exp
, 4);
4549 while (*input_line_pointer
++ == ',');
4551 input_line_pointer
--;
4552 demand_empty_rest_of_line ();
4556 /* This table describes all the machine specific pseudo-ops the assembler
4557 has to support. The fields are:
4558 pseudo-op name without dot
4559 function to call to execute this pseudo-op
4560 Integer arg to pass to the function. */
4562 const pseudo_typeS md_pseudo_table
[] =
4564 /* Never called because '.req' does not start a line. */
4565 { "req", s_req
, 0 },
4566 /* Following two are likewise never called. */
4569 { "unreq", s_unreq
, 0 },
4570 { "bss", s_bss
, 0 },
4571 { "align", s_align
, 0 },
4572 { "arm", s_arm
, 0 },
4573 { "thumb", s_thumb
, 0 },
4574 { "code", s_code
, 0 },
4575 { "force_thumb", s_force_thumb
, 0 },
4576 { "thumb_func", s_thumb_func
, 0 },
4577 { "thumb_set", s_thumb_set
, 0 },
4578 { "even", s_even
, 0 },
4579 { "ltorg", s_ltorg
, 0 },
4580 { "pool", s_ltorg
, 0 },
4581 { "syntax", s_syntax
, 0 },
4582 { "cpu", s_arm_cpu
, 0 },
4583 { "arch", s_arm_arch
, 0 },
4584 { "object_arch", s_arm_object_arch
, 0 },
4585 { "fpu", s_arm_fpu
, 0 },
4586 { "arch_extension", s_arm_arch_extension
, 0 },
4588 { "word", s_arm_elf_cons
, 4 },
4589 { "long", s_arm_elf_cons
, 4 },
4590 { "inst.n", s_arm_elf_inst
, 2 },
4591 { "inst.w", s_arm_elf_inst
, 4 },
4592 { "inst", s_arm_elf_inst
, 0 },
4593 { "rel31", s_arm_rel31
, 0 },
4594 { "fnstart", s_arm_unwind_fnstart
, 0 },
4595 { "fnend", s_arm_unwind_fnend
, 0 },
4596 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4597 { "personality", s_arm_unwind_personality
, 0 },
4598 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4599 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4600 { "save", s_arm_unwind_save
, 0 },
4601 { "vsave", s_arm_unwind_save
, 1 },
4602 { "movsp", s_arm_unwind_movsp
, 0 },
4603 { "pad", s_arm_unwind_pad
, 0 },
4604 { "setfp", s_arm_unwind_setfp
, 0 },
4605 { "unwind_raw", s_arm_unwind_raw
, 0 },
4606 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4607 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4611 /* These are used for dwarf. */
4615 /* These are used for dwarf2. */
4616 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4617 { "loc", dwarf2_directive_loc
, 0 },
4618 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4620 { "extend", float_cons
, 'x' },
4621 { "ldouble", float_cons
, 'x' },
4622 { "packed", float_cons
, 'p' },
4624 {"secrel32", pe_directive_secrel
, 0},
4627 /* These are for compatibility with CodeComposer Studio. */
4628 {"ref", s_ccs_ref
, 0},
4629 {"def", s_ccs_def
, 0},
4630 {"asmfunc", s_ccs_asmfunc
, 0},
4631 {"endasmfunc", s_ccs_endasmfunc
, 0},
4636 /* Parser functions used exclusively in instruction operands. */
4638 /* Generic immediate-value read function for use in insn parsing.
4639 STR points to the beginning of the immediate (the leading #);
4640 VAL receives the value; if the value is outside [MIN, MAX]
4641 issue an error. PREFIX_OPT is true if the immediate prefix is
4645 parse_immediate (char **str
, int *val
, int min
, int max
,
4646 bfd_boolean prefix_opt
)
4649 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4650 if (exp
.X_op
!= O_constant
)
4652 inst
.error
= _("constant expression required");
4656 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4658 inst
.error
= _("immediate value out of range");
4662 *val
= exp
.X_add_number
;
4666 /* Less-generic immediate-value read function with the possibility of loading a
4667 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4668 instructions. Puts the result directly in inst.operands[i]. */
4671 parse_big_immediate (char **str
, int i
)
4676 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4678 if (exp
.X_op
== O_constant
)
4680 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4681 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4682 O_constant. We have to be careful not to break compilation for
4683 32-bit X_add_number, though. */
4684 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4686 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4687 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4688 inst
.operands
[i
].regisimm
= 1;
4691 else if (exp
.X_op
== O_big
4692 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4694 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4696 /* Bignums have their least significant bits in
4697 generic_bignum[0]. Make sure we put 32 bits in imm and
4698 32 bits in reg, in a (hopefully) portable way. */
4699 gas_assert (parts
!= 0);
4701 /* Make sure that the number is not too big.
4702 PR 11972: Bignums can now be sign-extended to the
4703 size of a .octa so check that the out of range bits
4704 are all zero or all one. */
4705 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4707 LITTLENUM_TYPE m
= -1;
4709 if (generic_bignum
[parts
* 2] != 0
4710 && generic_bignum
[parts
* 2] != m
)
4713 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4714 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4718 inst
.operands
[i
].imm
= 0;
4719 for (j
= 0; j
< parts
; j
++, idx
++)
4720 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4721 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4722 inst
.operands
[i
].reg
= 0;
4723 for (j
= 0; j
< parts
; j
++, idx
++)
4724 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4725 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4726 inst
.operands
[i
].regisimm
= 1;
4736 /* Returns the pseudo-register number of an FPA immediate constant,
4737 or FAIL if there isn't a valid constant here. */
4740 parse_fpa_immediate (char ** str
)
4742 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4748 /* First try and match exact strings, this is to guarantee
4749 that some formats will work even for cross assembly. */
4751 for (i
= 0; fp_const
[i
]; i
++)
4753 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4757 *str
+= strlen (fp_const
[i
]);
4758 if (is_end_of_line
[(unsigned char) **str
])
4764 /* Just because we didn't get a match doesn't mean that the constant
4765 isn't valid, just that it is in a format that we don't
4766 automatically recognize. Try parsing it with the standard
4767 expression routines. */
4769 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4771 /* Look for a raw floating point number. */
4772 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4773 && is_end_of_line
[(unsigned char) *save_in
])
4775 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4777 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4779 if (words
[j
] != fp_values
[i
][j
])
4783 if (j
== MAX_LITTLENUMS
)
4791 /* Try and parse a more complex expression, this will probably fail
4792 unless the code uses a floating point prefix (eg "0f"). */
4793 save_in
= input_line_pointer
;
4794 input_line_pointer
= *str
;
4795 if (expression (&exp
) == absolute_section
4796 && exp
.X_op
== O_big
4797 && exp
.X_add_number
< 0)
4799 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4801 if (gen_to_words (words
, 5, (long) 15) == 0)
4803 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4805 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4807 if (words
[j
] != fp_values
[i
][j
])
4811 if (j
== MAX_LITTLENUMS
)
4813 *str
= input_line_pointer
;
4814 input_line_pointer
= save_in
;
4821 *str
= input_line_pointer
;
4822 input_line_pointer
= save_in
;
4823 inst
.error
= _("invalid FPA immediate expression");
4827 /* Returns 1 if a number has "quarter-precision" float format
4828 0baBbbbbbc defgh000 00000000 00000000. */
4831 is_quarter_float (unsigned imm
)
4833 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4834 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4837 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4838 0baBbbbbbc defgh000 00000000 00000000.
4839 The zero and minus-zero cases need special handling, since they can't be
4840 encoded in the "quarter-precision" float format, but can nonetheless be
4841 loaded as integer constants. */
4844 parse_qfloat_immediate (char **ccp
, int *immed
)
4848 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4849 int found_fpchar
= 0;
4851 skip_past_char (&str
, '#');
4853 /* We must not accidentally parse an integer as a floating-point number. Make
4854 sure that the value we parse is not an integer by checking for special
4855 characters '.' or 'e'.
4856 FIXME: This is a horrible hack, but doing better is tricky because type
4857 information isn't in a very usable state at parse time. */
4859 skip_whitespace (fpnum
);
4861 if (strncmp (fpnum
, "0x", 2) == 0)
4865 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4866 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4876 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4878 unsigned fpword
= 0;
4881 /* Our FP word must be 32 bits (single-precision FP). */
4882 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4884 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4888 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4901 /* Shift operands. */
4904 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4907 struct asm_shift_name
4910 enum shift_kind kind
;
4913 /* Third argument to parse_shift. */
4914 enum parse_shift_mode
4916 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4917 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4918 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4919 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4920 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4923 /* Parse a <shift> specifier on an ARM data processing instruction.
4924 This has three forms:
4926 (LSL|LSR|ASL|ASR|ROR) Rs
4927 (LSL|LSR|ASL|ASR|ROR) #imm
4930 Note that ASL is assimilated to LSL in the instruction encoding, and
4931 RRX to ROR #0 (which cannot be written as such). */
4934 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4936 const struct asm_shift_name
*shift_name
;
4937 enum shift_kind shift
;
4942 for (p
= *str
; ISALPHA (*p
); p
++)
4947 inst
.error
= _("shift expression expected");
4951 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4954 if (shift_name
== NULL
)
4956 inst
.error
= _("shift expression expected");
4960 shift
= shift_name
->kind
;
4964 case NO_SHIFT_RESTRICT
:
4965 case SHIFT_IMMEDIATE
: break;
4967 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4968 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4970 inst
.error
= _("'LSL' or 'ASR' required");
4975 case SHIFT_LSL_IMMEDIATE
:
4976 if (shift
!= SHIFT_LSL
)
4978 inst
.error
= _("'LSL' required");
4983 case SHIFT_ASR_IMMEDIATE
:
4984 if (shift
!= SHIFT_ASR
)
4986 inst
.error
= _("'ASR' required");
4994 if (shift
!= SHIFT_RRX
)
4996 /* Whitespace can appear here if the next thing is a bare digit. */
4997 skip_whitespace (p
);
4999 if (mode
== NO_SHIFT_RESTRICT
5000 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5002 inst
.operands
[i
].imm
= reg
;
5003 inst
.operands
[i
].immisreg
= 1;
5005 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5008 inst
.operands
[i
].shift_kind
= shift
;
5009 inst
.operands
[i
].shifted
= 1;
5014 /* Parse a <shifter_operand> for an ARM data processing instruction:
5017 #<immediate>, <rotate>
5021 where <shift> is defined by parse_shift above, and <rotate> is a
5022 multiple of 2 between 0 and 30. Validation of immediate operands
5023 is deferred to md_apply_fix. */
5026 parse_shifter_operand (char **str
, int i
)
5031 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5033 inst
.operands
[i
].reg
= value
;
5034 inst
.operands
[i
].isreg
= 1;
5036 /* parse_shift will override this if appropriate */
5037 inst
.reloc
.exp
.X_op
= O_constant
;
5038 inst
.reloc
.exp
.X_add_number
= 0;
5040 if (skip_past_comma (str
) == FAIL
)
5043 /* Shift operation on register. */
5044 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5047 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5050 if (skip_past_comma (str
) == SUCCESS
)
5052 /* #x, y -- ie explicit rotation by Y. */
5053 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5056 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5058 inst
.error
= _("constant expression expected");
5062 value
= exp
.X_add_number
;
5063 if (value
< 0 || value
> 30 || value
% 2 != 0)
5065 inst
.error
= _("invalid rotation");
5068 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5070 inst
.error
= _("invalid constant");
5074 /* Encode as specified. */
5075 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5079 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5080 inst
.reloc
.pc_rel
= 0;
5084 /* Group relocation information. Each entry in the table contains the
5085 textual name of the relocation as may appear in assembler source
5086 and must end with a colon.
5087 Along with this textual name are the relocation codes to be used if
5088 the corresponding instruction is an ALU instruction (ADD or SUB only),
5089 an LDR, an LDRS, or an LDC. */
5091 struct group_reloc_table_entry
5102 /* Varieties of non-ALU group relocation. */
5109 static struct group_reloc_table_entry group_reloc_table
[] =
5110 { /* Program counter relative: */
5112 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5117 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5118 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5119 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5120 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5122 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5127 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5128 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5129 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5130 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5132 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5133 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5134 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5135 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5136 /* Section base relative */
5138 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5143 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5144 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5145 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5146 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5148 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5153 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5154 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5155 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5156 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5158 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5159 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5160 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5161 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5163 /* Given the address of a pointer pointing to the textual name of a group
5164 relocation as may appear in assembler source, attempt to find its details
5165 in group_reloc_table. The pointer will be updated to the character after
5166 the trailing colon. On failure, FAIL will be returned; SUCCESS
5167 otherwise. On success, *entry will be updated to point at the relevant
5168 group_reloc_table entry. */
5171 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5174 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5176 int length
= strlen (group_reloc_table
[i
].name
);
5178 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5179 && (*str
)[length
] == ':')
5181 *out
= &group_reloc_table
[i
];
5182 *str
+= (length
+ 1);
5190 /* Parse a <shifter_operand> for an ARM data processing instruction
5191 (as for parse_shifter_operand) where group relocations are allowed:
5194 #<immediate>, <rotate>
5195 #:<group_reloc>:<expression>
5199 where <group_reloc> is one of the strings defined in group_reloc_table.
5200 The hashes are optional.
5202 Everything else is as for parse_shifter_operand. */
5204 static parse_operand_result
5205 parse_shifter_operand_group_reloc (char **str
, int i
)
5207 /* Determine if we have the sequence of characters #: or just :
5208 coming next. If we do, then we check for a group relocation.
5209 If we don't, punt the whole lot to parse_shifter_operand. */
5211 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5212 || (*str
)[0] == ':')
5214 struct group_reloc_table_entry
*entry
;
5216 if ((*str
)[0] == '#')
5221 /* Try to parse a group relocation. Anything else is an error. */
5222 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5224 inst
.error
= _("unknown group relocation");
5225 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5228 /* We now have the group relocation table entry corresponding to
5229 the name in the assembler source. Next, we parse the expression. */
5230 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5231 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5233 /* Record the relocation type (always the ALU variant here). */
5234 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5235 gas_assert (inst
.reloc
.type
!= 0);
5237 return PARSE_OPERAND_SUCCESS
;
5240 return parse_shifter_operand (str
, i
) == SUCCESS
5241 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5243 /* Never reached. */
5246 /* Parse a Neon alignment expression. Information is written to
5247 inst.operands[i]. We assume the initial ':' has been skipped.
5249 align .imm = align << 8, .immisalign=1, .preind=0 */
5250 static parse_operand_result
5251 parse_neon_alignment (char **str
, int i
)
5256 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5258 if (exp
.X_op
!= O_constant
)
5260 inst
.error
= _("alignment must be constant");
5261 return PARSE_OPERAND_FAIL
;
5264 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5265 inst
.operands
[i
].immisalign
= 1;
5266 /* Alignments are not pre-indexes. */
5267 inst
.operands
[i
].preind
= 0;
5270 return PARSE_OPERAND_SUCCESS
;
5273 /* Parse all forms of an ARM address expression. Information is written
5274 to inst.operands[i] and/or inst.reloc.
5276 Preindexed addressing (.preind=1):
5278 [Rn, #offset] .reg=Rn .reloc.exp=offset
5279 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5280 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5281 .shift_kind=shift .reloc.exp=shift_imm
5283 These three may have a trailing ! which causes .writeback to be set also.
5285 Postindexed addressing (.postind=1, .writeback=1):
5287 [Rn], #offset .reg=Rn .reloc.exp=offset
5288 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5289 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5290 .shift_kind=shift .reloc.exp=shift_imm
5292 Unindexed addressing (.preind=0, .postind=0):
5294 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5298 [Rn]{!} shorthand for [Rn,#0]{!}
5299 =immediate .isreg=0 .reloc.exp=immediate
5300 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5302 It is the caller's responsibility to check for addressing modes not
5303 supported by the instruction, and to set inst.reloc.type. */
5305 static parse_operand_result
5306 parse_address_main (char **str
, int i
, int group_relocations
,
5307 group_reloc_type group_type
)
5312 if (skip_past_char (&p
, '[') == FAIL
)
5314 if (skip_past_char (&p
, '=') == FAIL
)
5316 /* Bare address - translate to PC-relative offset. */
5317 inst
.reloc
.pc_rel
= 1;
5318 inst
.operands
[i
].reg
= REG_PC
;
5319 inst
.operands
[i
].isreg
= 1;
5320 inst
.operands
[i
].preind
= 1;
5322 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5324 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5325 return PARSE_OPERAND_FAIL
;
5328 return PARSE_OPERAND_SUCCESS
;
5331 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5332 skip_whitespace (p
);
5334 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5336 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5337 return PARSE_OPERAND_FAIL
;
5339 inst
.operands
[i
].reg
= reg
;
5340 inst
.operands
[i
].isreg
= 1;
5342 if (skip_past_comma (&p
) == SUCCESS
)
5344 inst
.operands
[i
].preind
= 1;
5347 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5349 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5351 inst
.operands
[i
].imm
= reg
;
5352 inst
.operands
[i
].immisreg
= 1;
5354 if (skip_past_comma (&p
) == SUCCESS
)
5355 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5356 return PARSE_OPERAND_FAIL
;
5358 else if (skip_past_char (&p
, ':') == SUCCESS
)
5360 /* FIXME: '@' should be used here, but it's filtered out by generic
5361 code before we get to see it here. This may be subject to
5363 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5365 if (result
!= PARSE_OPERAND_SUCCESS
)
5370 if (inst
.operands
[i
].negative
)
5372 inst
.operands
[i
].negative
= 0;
5376 if (group_relocations
5377 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5379 struct group_reloc_table_entry
*entry
;
5381 /* Skip over the #: or : sequence. */
5387 /* Try to parse a group relocation. Anything else is an
5389 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5391 inst
.error
= _("unknown group relocation");
5392 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5395 /* We now have the group relocation table entry corresponding to
5396 the name in the assembler source. Next, we parse the
5398 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5399 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5401 /* Record the relocation type. */
5405 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5409 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5413 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5420 if (inst
.reloc
.type
== 0)
5422 inst
.error
= _("this group relocation is not allowed on this instruction");
5423 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5429 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5430 return PARSE_OPERAND_FAIL
;
5431 /* If the offset is 0, find out if it's a +0 or -0. */
5432 if (inst
.reloc
.exp
.X_op
== O_constant
5433 && inst
.reloc
.exp
.X_add_number
== 0)
5435 skip_whitespace (q
);
5439 skip_whitespace (q
);
5442 inst
.operands
[i
].negative
= 1;
5447 else if (skip_past_char (&p
, ':') == SUCCESS
)
5449 /* FIXME: '@' should be used here, but it's filtered out by generic code
5450 before we get to see it here. This may be subject to change. */
5451 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5453 if (result
!= PARSE_OPERAND_SUCCESS
)
5457 if (skip_past_char (&p
, ']') == FAIL
)
5459 inst
.error
= _("']' expected");
5460 return PARSE_OPERAND_FAIL
;
5463 if (skip_past_char (&p
, '!') == SUCCESS
)
5464 inst
.operands
[i
].writeback
= 1;
5466 else if (skip_past_comma (&p
) == SUCCESS
)
5468 if (skip_past_char (&p
, '{') == SUCCESS
)
5470 /* [Rn], {expr} - unindexed, with option */
5471 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5472 0, 255, TRUE
) == FAIL
)
5473 return PARSE_OPERAND_FAIL
;
5475 if (skip_past_char (&p
, '}') == FAIL
)
5477 inst
.error
= _("'}' expected at end of 'option' field");
5478 return PARSE_OPERAND_FAIL
;
5480 if (inst
.operands
[i
].preind
)
5482 inst
.error
= _("cannot combine index with option");
5483 return PARSE_OPERAND_FAIL
;
5486 return PARSE_OPERAND_SUCCESS
;
5490 inst
.operands
[i
].postind
= 1;
5491 inst
.operands
[i
].writeback
= 1;
5493 if (inst
.operands
[i
].preind
)
5495 inst
.error
= _("cannot combine pre- and post-indexing");
5496 return PARSE_OPERAND_FAIL
;
5500 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5502 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5504 /* We might be using the immediate for alignment already. If we
5505 are, OR the register number into the low-order bits. */
5506 if (inst
.operands
[i
].immisalign
)
5507 inst
.operands
[i
].imm
|= reg
;
5509 inst
.operands
[i
].imm
= reg
;
5510 inst
.operands
[i
].immisreg
= 1;
5512 if (skip_past_comma (&p
) == SUCCESS
)
5513 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5514 return PARSE_OPERAND_FAIL
;
5519 if (inst
.operands
[i
].negative
)
5521 inst
.operands
[i
].negative
= 0;
5524 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5525 return PARSE_OPERAND_FAIL
;
5526 /* If the offset is 0, find out if it's a +0 or -0. */
5527 if (inst
.reloc
.exp
.X_op
== O_constant
5528 && inst
.reloc
.exp
.X_add_number
== 0)
5530 skip_whitespace (q
);
5534 skip_whitespace (q
);
5537 inst
.operands
[i
].negative
= 1;
5543 /* If at this point neither .preind nor .postind is set, we have a
5544 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5545 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5547 inst
.operands
[i
].preind
= 1;
5548 inst
.reloc
.exp
.X_op
= O_constant
;
5549 inst
.reloc
.exp
.X_add_number
= 0;
5552 return PARSE_OPERAND_SUCCESS
;
5556 parse_address (char **str
, int i
)
5558 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5562 static parse_operand_result
5563 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5565 return parse_address_main (str
, i
, 1, type
);
5568 /* Parse an operand for a MOVW or MOVT instruction. */
5570 parse_half (char **str
)
5575 skip_past_char (&p
, '#');
5576 if (strncasecmp (p
, ":lower16:", 9) == 0)
5577 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5578 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5579 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5581 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5584 skip_whitespace (p
);
5587 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5590 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5592 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5594 inst
.error
= _("constant expression expected");
5597 if (inst
.reloc
.exp
.X_add_number
< 0
5598 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5600 inst
.error
= _("immediate value out of range");
5608 /* Miscellaneous. */
5610 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5611 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5613 parse_psr (char **str
, bfd_boolean lhs
)
5616 unsigned long psr_field
;
5617 const struct asm_psr
*psr
;
5619 bfd_boolean is_apsr
= FALSE
;
5620 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5622 /* PR gas/12698: If the user has specified -march=all then m_profile will
5623 be TRUE, but we want to ignore it in this case as we are building for any
5624 CPU type, including non-m variants. */
5625 if (selected_cpu
.core
== arm_arch_any
.core
)
5628 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5629 feature for ease of use and backwards compatibility. */
5631 if (strncasecmp (p
, "SPSR", 4) == 0)
5634 goto unsupported_psr
;
5636 psr_field
= SPSR_BIT
;
5638 else if (strncasecmp (p
, "CPSR", 4) == 0)
5641 goto unsupported_psr
;
5645 else if (strncasecmp (p
, "APSR", 4) == 0)
5647 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5648 and ARMv7-R architecture CPUs. */
5657 while (ISALNUM (*p
) || *p
== '_');
5659 if (strncasecmp (start
, "iapsr", 5) == 0
5660 || strncasecmp (start
, "eapsr", 5) == 0
5661 || strncasecmp (start
, "xpsr", 4) == 0
5662 || strncasecmp (start
, "psr", 3) == 0)
5663 p
= start
+ strcspn (start
, "rR") + 1;
5665 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5671 /* If APSR is being written, a bitfield may be specified. Note that
5672 APSR itself is handled above. */
5673 if (psr
->field
<= 3)
5675 psr_field
= psr
->field
;
5681 /* M-profile MSR instructions have the mask field set to "10", except
5682 *PSR variants which modify APSR, which may use a different mask (and
5683 have been handled already). Do that by setting the PSR_f field
5685 return psr
->field
| (lhs
? PSR_f
: 0);
5688 goto unsupported_psr
;
5694 /* A suffix follows. */
5700 while (ISALNUM (*p
) || *p
== '_');
5704 /* APSR uses a notation for bits, rather than fields. */
5705 unsigned int nzcvq_bits
= 0;
5706 unsigned int g_bit
= 0;
5709 for (bit
= start
; bit
!= p
; bit
++)
5711 switch (TOLOWER (*bit
))
5714 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5718 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5722 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5726 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5730 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5734 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5738 inst
.error
= _("unexpected bit specified after APSR");
5743 if (nzcvq_bits
== 0x1f)
5748 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5750 inst
.error
= _("selected processor does not "
5751 "support DSP extension");
5758 if ((nzcvq_bits
& 0x20) != 0
5759 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5760 || (g_bit
& 0x2) != 0)
5762 inst
.error
= _("bad bitmask specified after APSR");
5768 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5773 psr_field
|= psr
->field
;
5779 goto error
; /* Garbage after "[CS]PSR". */
5781 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5782 is deprecated, but allow it anyway. */
5786 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5789 else if (!m_profile
)
5790 /* These bits are never right for M-profile devices: don't set them
5791 (only code paths which read/write APSR reach here). */
5792 psr_field
|= (PSR_c
| PSR_f
);
5798 inst
.error
= _("selected processor does not support requested special "
5799 "purpose register");
5803 inst
.error
= _("flag for {c}psr instruction expected");
5807 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5808 value suitable for splatting into the AIF field of the instruction. */
5811 parse_cps_flags (char **str
)
5820 case '\0': case ',':
5823 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5824 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5825 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5828 inst
.error
= _("unrecognized CPS flag");
5833 if (saw_a_flag
== 0)
5835 inst
.error
= _("missing CPS flags");
5843 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5844 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5847 parse_endian_specifier (char **str
)
5852 if (strncasecmp (s
, "BE", 2))
5854 else if (strncasecmp (s
, "LE", 2))
5858 inst
.error
= _("valid endian specifiers are be or le");
5862 if (ISALNUM (s
[2]) || s
[2] == '_')
5864 inst
.error
= _("valid endian specifiers are be or le");
5869 return little_endian
;
5872 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5873 value suitable for poking into the rotate field of an sxt or sxta
5874 instruction, or FAIL on error. */
5877 parse_ror (char **str
)
5882 if (strncasecmp (s
, "ROR", 3) == 0)
5886 inst
.error
= _("missing rotation field after comma");
5890 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5895 case 0: *str
= s
; return 0x0;
5896 case 8: *str
= s
; return 0x1;
5897 case 16: *str
= s
; return 0x2;
5898 case 24: *str
= s
; return 0x3;
5901 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5906 /* Parse a conditional code (from conds[] below). The value returned is in the
5907 range 0 .. 14, or FAIL. */
5909 parse_cond (char **str
)
5912 const struct asm_cond
*c
;
5914 /* Condition codes are always 2 characters, so matching up to
5915 3 characters is sufficient. */
5920 while (ISALPHA (*q
) && n
< 3)
5922 cond
[n
] = TOLOWER (*q
);
5927 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5930 inst
.error
= _("condition required");
5938 /* If the given feature available in the selected CPU, mark it as used.
5939 Returns TRUE iff feature is available. */
5941 mark_feature_used (const arm_feature_set
*feature
)
5943 /* Ensure the option is valid on the current architecture. */
5944 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
5947 /* Add the appropriate architecture feature for the barrier option used.
5950 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
5952 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
5957 /* Parse an option for a barrier instruction. Returns the encoding for the
5960 parse_barrier (char **str
)
5963 const struct asm_barrier_opt
*o
;
5966 while (ISALPHA (*q
))
5969 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5974 if (!mark_feature_used (&o
->arch
))
5981 /* Parse the operands of a table branch instruction. Similar to a memory
5984 parse_tb (char **str
)
5989 if (skip_past_char (&p
, '[') == FAIL
)
5991 inst
.error
= _("'[' expected");
5995 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5997 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6000 inst
.operands
[0].reg
= reg
;
6002 if (skip_past_comma (&p
) == FAIL
)
6004 inst
.error
= _("',' expected");
6008 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6010 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6013 inst
.operands
[0].imm
= reg
;
6015 if (skip_past_comma (&p
) == SUCCESS
)
6017 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6019 if (inst
.reloc
.exp
.X_add_number
!= 1)
6021 inst
.error
= _("invalid shift");
6024 inst
.operands
[0].shifted
= 1;
6027 if (skip_past_char (&p
, ']') == FAIL
)
6029 inst
.error
= _("']' expected");
6036 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6037 information on the types the operands can take and how they are encoded.
6038 Up to four operands may be read; this function handles setting the
6039 ".present" field for each read operand itself.
6040 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6041 else returns FAIL. */
6044 parse_neon_mov (char **str
, int *which_operand
)
6046 int i
= *which_operand
, val
;
6047 enum arm_reg_type rtype
;
6049 struct neon_type_el optype
;
6051 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6053 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6054 inst
.operands
[i
].reg
= val
;
6055 inst
.operands
[i
].isscalar
= 1;
6056 inst
.operands
[i
].vectype
= optype
;
6057 inst
.operands
[i
++].present
= 1;
6059 if (skip_past_comma (&ptr
) == FAIL
)
6062 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6065 inst
.operands
[i
].reg
= val
;
6066 inst
.operands
[i
].isreg
= 1;
6067 inst
.operands
[i
].present
= 1;
6069 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6072 /* Cases 0, 1, 2, 3, 5 (D only). */
6073 if (skip_past_comma (&ptr
) == FAIL
)
6076 inst
.operands
[i
].reg
= val
;
6077 inst
.operands
[i
].isreg
= 1;
6078 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6079 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6080 inst
.operands
[i
].isvec
= 1;
6081 inst
.operands
[i
].vectype
= optype
;
6082 inst
.operands
[i
++].present
= 1;
6084 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6086 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6087 Case 13: VMOV <Sd>, <Rm> */
6088 inst
.operands
[i
].reg
= val
;
6089 inst
.operands
[i
].isreg
= 1;
6090 inst
.operands
[i
].present
= 1;
6092 if (rtype
== REG_TYPE_NQ
)
6094 first_error (_("can't use Neon quad register here"));
6097 else if (rtype
!= REG_TYPE_VFS
)
6100 if (skip_past_comma (&ptr
) == FAIL
)
6102 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6104 inst
.operands
[i
].reg
= val
;
6105 inst
.operands
[i
].isreg
= 1;
6106 inst
.operands
[i
].present
= 1;
6109 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6112 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6113 Case 1: VMOV<c><q> <Dd>, <Dm>
6114 Case 8: VMOV.F32 <Sd>, <Sm>
6115 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6117 inst
.operands
[i
].reg
= val
;
6118 inst
.operands
[i
].isreg
= 1;
6119 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6120 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6121 inst
.operands
[i
].isvec
= 1;
6122 inst
.operands
[i
].vectype
= optype
;
6123 inst
.operands
[i
].present
= 1;
6125 if (skip_past_comma (&ptr
) == SUCCESS
)
6130 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6133 inst
.operands
[i
].reg
= val
;
6134 inst
.operands
[i
].isreg
= 1;
6135 inst
.operands
[i
++].present
= 1;
6137 if (skip_past_comma (&ptr
) == FAIL
)
6140 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6143 inst
.operands
[i
].reg
= val
;
6144 inst
.operands
[i
].isreg
= 1;
6145 inst
.operands
[i
].present
= 1;
6148 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6149 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6150 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6151 Case 10: VMOV.F32 <Sd>, #<imm>
6152 Case 11: VMOV.F64 <Dd>, #<imm> */
6153 inst
.operands
[i
].immisfloat
= 1;
6154 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
6155 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6156 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6160 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6164 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6167 inst
.operands
[i
].reg
= val
;
6168 inst
.operands
[i
].isreg
= 1;
6169 inst
.operands
[i
++].present
= 1;
6171 if (skip_past_comma (&ptr
) == FAIL
)
6174 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6176 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6177 inst
.operands
[i
].reg
= val
;
6178 inst
.operands
[i
].isscalar
= 1;
6179 inst
.operands
[i
].present
= 1;
6180 inst
.operands
[i
].vectype
= optype
;
6182 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6184 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6185 inst
.operands
[i
].reg
= val
;
6186 inst
.operands
[i
].isreg
= 1;
6187 inst
.operands
[i
++].present
= 1;
6189 if (skip_past_comma (&ptr
) == FAIL
)
6192 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6195 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6199 inst
.operands
[i
].reg
= val
;
6200 inst
.operands
[i
].isreg
= 1;
6201 inst
.operands
[i
].isvec
= 1;
6202 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6203 inst
.operands
[i
].vectype
= optype
;
6204 inst
.operands
[i
].present
= 1;
6206 if (rtype
== REG_TYPE_VFS
)
6210 if (skip_past_comma (&ptr
) == FAIL
)
6212 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6215 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6218 inst
.operands
[i
].reg
= val
;
6219 inst
.operands
[i
].isreg
= 1;
6220 inst
.operands
[i
].isvec
= 1;
6221 inst
.operands
[i
].issingle
= 1;
6222 inst
.operands
[i
].vectype
= optype
;
6223 inst
.operands
[i
].present
= 1;
6226 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6230 inst
.operands
[i
].reg
= val
;
6231 inst
.operands
[i
].isreg
= 1;
6232 inst
.operands
[i
].isvec
= 1;
6233 inst
.operands
[i
].issingle
= 1;
6234 inst
.operands
[i
].vectype
= optype
;
6235 inst
.operands
[i
].present
= 1;
6240 first_error (_("parse error"));
6244 /* Successfully parsed the operands. Update args. */
6250 first_error (_("expected comma"));
6254 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6258 /* Use this macro when the operand constraints are different
6259 for ARM and THUMB (e.g. ldrd). */
6260 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6261 ((arm_operand) | ((thumb_operand) << 16))
6263 /* Matcher codes for parse_operands. */
6264 enum operand_parse_code
6266 OP_stop
, /* end of line */
6268 OP_RR
, /* ARM register */
6269 OP_RRnpc
, /* ARM register, not r15 */
6270 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6271 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6272 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6273 optional trailing ! */
6274 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6275 OP_RCP
, /* Coprocessor number */
6276 OP_RCN
, /* Coprocessor register */
6277 OP_RF
, /* FPA register */
6278 OP_RVS
, /* VFP single precision register */
6279 OP_RVD
, /* VFP double precision register (0..15) */
6280 OP_RND
, /* Neon double precision register (0..31) */
6281 OP_RNQ
, /* Neon quad precision register */
6282 OP_RVSD
, /* VFP single or double precision register */
6283 OP_RNDQ
, /* Neon double or quad precision register */
6284 OP_RNSDQ
, /* Neon single, double or quad precision register */
6285 OP_RNSC
, /* Neon scalar D[X] */
6286 OP_RVC
, /* VFP control register */
6287 OP_RMF
, /* Maverick F register */
6288 OP_RMD
, /* Maverick D register */
6289 OP_RMFX
, /* Maverick FX register */
6290 OP_RMDX
, /* Maverick DX register */
6291 OP_RMAX
, /* Maverick AX register */
6292 OP_RMDS
, /* Maverick DSPSC register */
6293 OP_RIWR
, /* iWMMXt wR register */
6294 OP_RIWC
, /* iWMMXt wC register */
6295 OP_RIWG
, /* iWMMXt wCG register */
6296 OP_RXA
, /* XScale accumulator register */
6298 OP_REGLST
, /* ARM register list */
6299 OP_VRSLST
, /* VFP single-precision register list */
6300 OP_VRDLST
, /* VFP double-precision register list */
6301 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6302 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6303 OP_NSTRLST
, /* Neon element/structure list */
6305 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6306 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6307 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6308 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6309 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6310 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6311 OP_VMOV
, /* Neon VMOV operands. */
6312 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6313 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6314 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6316 OP_I0
, /* immediate zero */
6317 OP_I7
, /* immediate value 0 .. 7 */
6318 OP_I15
, /* 0 .. 15 */
6319 OP_I16
, /* 1 .. 16 */
6320 OP_I16z
, /* 0 .. 16 */
6321 OP_I31
, /* 0 .. 31 */
6322 OP_I31w
, /* 0 .. 31, optional trailing ! */
6323 OP_I32
, /* 1 .. 32 */
6324 OP_I32z
, /* 0 .. 32 */
6325 OP_I63
, /* 0 .. 63 */
6326 OP_I63s
, /* -64 .. 63 */
6327 OP_I64
, /* 1 .. 64 */
6328 OP_I64z
, /* 0 .. 64 */
6329 OP_I255
, /* 0 .. 255 */
6331 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6332 OP_I7b
, /* 0 .. 7 */
6333 OP_I15b
, /* 0 .. 15 */
6334 OP_I31b
, /* 0 .. 31 */
6336 OP_SH
, /* shifter operand */
6337 OP_SHG
, /* shifter operand with possible group relocation */
6338 OP_ADDR
, /* Memory address expression (any mode) */
6339 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6340 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6341 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6342 OP_EXP
, /* arbitrary expression */
6343 OP_EXPi
, /* same, with optional immediate prefix */
6344 OP_EXPr
, /* same, with optional relocation suffix */
6345 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6347 OP_CPSF
, /* CPS flags */
6348 OP_ENDI
, /* Endianness specifier */
6349 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6350 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6351 OP_COND
, /* conditional code */
6352 OP_TB
, /* Table branch. */
6354 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6356 OP_RRnpc_I0
, /* ARM register or literal 0 */
6357 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6358 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6359 OP_RF_IF
, /* FPA register or immediate */
6360 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6361 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6363 /* Optional operands. */
6364 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6365 OP_oI31b
, /* 0 .. 31 */
6366 OP_oI32b
, /* 1 .. 32 */
6367 OP_oI32z
, /* 0 .. 32 */
6368 OP_oIffffb
, /* 0 .. 65535 */
6369 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6371 OP_oRR
, /* ARM register */
6372 OP_oRRnpc
, /* ARM register, not the PC */
6373 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6374 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6375 OP_oRND
, /* Optional Neon double precision register */
6376 OP_oRNQ
, /* Optional Neon quad precision register */
6377 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6378 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6379 OP_oSHll
, /* LSL immediate */
6380 OP_oSHar
, /* ASR immediate */
6381 OP_oSHllar
, /* LSL or ASR immediate */
6382 OP_oROR
, /* ROR 0/8/16/24 */
6383 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6385 /* Some pre-defined mixed (ARM/THUMB) operands. */
6386 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6387 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6388 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6390 OP_FIRST_OPTIONAL
= OP_oI7b
6393 /* Generic instruction operand parser. This does no encoding and no
6394 semantic validation; it merely squirrels values away in the inst
6395 structure. Returns SUCCESS or FAIL depending on whether the
6396 specified grammar matched. */
6398 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6400 unsigned const int *upat
= pattern
;
6401 char *backtrack_pos
= 0;
6402 const char *backtrack_error
= 0;
6403 int i
, val
= 0, backtrack_index
= 0;
6404 enum arm_reg_type rtype
;
6405 parse_operand_result result
;
6406 unsigned int op_parse_code
;
6408 #define po_char_or_fail(chr) \
6411 if (skip_past_char (&str, chr) == FAIL) \
6416 #define po_reg_or_fail(regtype) \
6419 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6420 & inst.operands[i].vectype); \
6423 first_error (_(reg_expected_msgs[regtype])); \
6426 inst.operands[i].reg = val; \
6427 inst.operands[i].isreg = 1; \
6428 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6429 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6430 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6431 || rtype == REG_TYPE_VFD \
6432 || rtype == REG_TYPE_NQ); \
6436 #define po_reg_or_goto(regtype, label) \
6439 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6440 & inst.operands[i].vectype); \
6444 inst.operands[i].reg = val; \
6445 inst.operands[i].isreg = 1; \
6446 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6447 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6448 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6449 || rtype == REG_TYPE_VFD \
6450 || rtype == REG_TYPE_NQ); \
6454 #define po_imm_or_fail(min, max, popt) \
6457 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6459 inst.operands[i].imm = val; \
6463 #define po_scalar_or_goto(elsz, label) \
6466 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6469 inst.operands[i].reg = val; \
6470 inst.operands[i].isscalar = 1; \
6474 #define po_misc_or_fail(expr) \
6482 #define po_misc_or_fail_no_backtrack(expr) \
6486 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6487 backtrack_pos = 0; \
6488 if (result != PARSE_OPERAND_SUCCESS) \
6493 #define po_barrier_or_imm(str) \
6496 val = parse_barrier (&str); \
6497 if (val == FAIL && ! ISALPHA (*str)) \
6500 /* ISB can only take SY as an option. */ \
6501 || ((inst.instruction & 0xf0) == 0x60 \
6504 inst.error = _("invalid barrier type"); \
6505 backtrack_pos = 0; \
6511 skip_whitespace (str
);
6513 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6515 op_parse_code
= upat
[i
];
6516 if (op_parse_code
>= 1<<16)
6517 op_parse_code
= thumb
? (op_parse_code
>> 16)
6518 : (op_parse_code
& ((1<<16)-1));
6520 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6522 /* Remember where we are in case we need to backtrack. */
6523 gas_assert (!backtrack_pos
);
6524 backtrack_pos
= str
;
6525 backtrack_error
= inst
.error
;
6526 backtrack_index
= i
;
6529 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6530 po_char_or_fail (',');
6532 switch (op_parse_code
)
6540 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6541 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6542 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6543 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6544 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6545 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6547 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6549 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6551 /* Also accept generic coprocessor regs for unknown registers. */
6553 po_reg_or_fail (REG_TYPE_CN
);
6555 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6556 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6557 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6558 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6559 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6560 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6561 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6562 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6563 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6564 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6566 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6568 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6569 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6571 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6573 /* Neon scalar. Using an element size of 8 means that some invalid
6574 scalars are accepted here, so deal with those in later code. */
6575 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6579 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6582 po_imm_or_fail (0, 0, TRUE
);
6587 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6592 po_scalar_or_goto (8, try_rr
);
6595 po_reg_or_fail (REG_TYPE_RN
);
6601 po_scalar_or_goto (8, try_nsdq
);
6604 po_reg_or_fail (REG_TYPE_NSDQ
);
6610 po_scalar_or_goto (8, try_ndq
);
6613 po_reg_or_fail (REG_TYPE_NDQ
);
6619 po_scalar_or_goto (8, try_vfd
);
6622 po_reg_or_fail (REG_TYPE_VFD
);
6627 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6628 not careful then bad things might happen. */
6629 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6634 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6637 /* There's a possibility of getting a 64-bit immediate here, so
6638 we need special handling. */
6639 if (parse_big_immediate (&str
, i
) == FAIL
)
6641 inst
.error
= _("immediate value is out of range");
6649 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6652 po_imm_or_fail (0, 63, TRUE
);
6657 po_char_or_fail ('[');
6658 po_reg_or_fail (REG_TYPE_RN
);
6659 po_char_or_fail (']');
6665 po_reg_or_fail (REG_TYPE_RN
);
6666 if (skip_past_char (&str
, '!') == SUCCESS
)
6667 inst
.operands
[i
].writeback
= 1;
6671 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6672 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6673 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6674 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6675 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6676 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6677 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6678 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6679 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6680 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6681 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6682 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6684 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6686 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6687 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6689 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6690 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6691 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6692 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6694 /* Immediate variants */
6696 po_char_or_fail ('{');
6697 po_imm_or_fail (0, 255, TRUE
);
6698 po_char_or_fail ('}');
6702 /* The expression parser chokes on a trailing !, so we have
6703 to find it first and zap it. */
6706 while (*s
&& *s
!= ',')
6711 inst
.operands
[i
].writeback
= 1;
6713 po_imm_or_fail (0, 31, TRUE
);
6721 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6726 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6731 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6733 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6735 val
= parse_reloc (&str
);
6738 inst
.error
= _("unrecognized relocation suffix");
6741 else if (val
!= BFD_RELOC_UNUSED
)
6743 inst
.operands
[i
].imm
= val
;
6744 inst
.operands
[i
].hasreloc
= 1;
6749 /* Operand for MOVW or MOVT. */
6751 po_misc_or_fail (parse_half (&str
));
6754 /* Register or expression. */
6755 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6756 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6758 /* Register or immediate. */
6759 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6760 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6762 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6764 if (!is_immediate_prefix (*str
))
6767 val
= parse_fpa_immediate (&str
);
6770 /* FPA immediates are encoded as registers 8-15.
6771 parse_fpa_immediate has already applied the offset. */
6772 inst
.operands
[i
].reg
= val
;
6773 inst
.operands
[i
].isreg
= 1;
6776 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6777 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6779 /* Two kinds of register. */
6782 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6784 || (rege
->type
!= REG_TYPE_MMXWR
6785 && rege
->type
!= REG_TYPE_MMXWC
6786 && rege
->type
!= REG_TYPE_MMXWCG
))
6788 inst
.error
= _("iWMMXt data or control register expected");
6791 inst
.operands
[i
].reg
= rege
->number
;
6792 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6798 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6800 || (rege
->type
!= REG_TYPE_MMXWC
6801 && rege
->type
!= REG_TYPE_MMXWCG
))
6803 inst
.error
= _("iWMMXt control register expected");
6806 inst
.operands
[i
].reg
= rege
->number
;
6807 inst
.operands
[i
].isreg
= 1;
6812 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6813 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6814 case OP_oROR
: val
= parse_ror (&str
); break;
6815 case OP_COND
: val
= parse_cond (&str
); break;
6816 case OP_oBARRIER_I15
:
6817 po_barrier_or_imm (str
); break;
6819 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6825 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6826 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6828 inst
.error
= _("Banked registers are not available with this "
6834 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6838 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6841 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6843 if (strncasecmp (str
, "APSR_", 5) == 0)
6850 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6851 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6852 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6853 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6854 default: found
= 16;
6858 inst
.operands
[i
].isvec
= 1;
6859 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6860 inst
.operands
[i
].reg
= REG_PC
;
6867 po_misc_or_fail (parse_tb (&str
));
6870 /* Register lists. */
6872 val
= parse_reg_list (&str
);
6875 inst
.operands
[1].writeback
= 1;
6881 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6885 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6889 /* Allow Q registers too. */
6890 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6895 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6897 inst
.operands
[i
].issingle
= 1;
6902 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6907 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6908 &inst
.operands
[i
].vectype
);
6911 /* Addressing modes */
6913 po_misc_or_fail (parse_address (&str
, i
));
6917 po_misc_or_fail_no_backtrack (
6918 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6922 po_misc_or_fail_no_backtrack (
6923 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6927 po_misc_or_fail_no_backtrack (
6928 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6932 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6936 po_misc_or_fail_no_backtrack (
6937 parse_shifter_operand_group_reloc (&str
, i
));
6941 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6945 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6949 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6953 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6956 /* Various value-based sanity checks and shared operations. We
6957 do not signal immediate failures for the register constraints;
6958 this allows a syntax error to take precedence. */
6959 switch (op_parse_code
)
6967 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6968 inst
.error
= BAD_PC
;
6973 if (inst
.operands
[i
].isreg
)
6975 if (inst
.operands
[i
].reg
== REG_PC
)
6976 inst
.error
= BAD_PC
;
6977 else if (inst
.operands
[i
].reg
== REG_SP
)
6978 inst
.error
= BAD_SP
;
6983 if (inst
.operands
[i
].isreg
6984 && inst
.operands
[i
].reg
== REG_PC
6985 && (inst
.operands
[i
].writeback
|| thumb
))
6986 inst
.error
= BAD_PC
;
6995 case OP_oBARRIER_I15
:
7004 inst
.operands
[i
].imm
= val
;
7011 /* If we get here, this operand was successfully parsed. */
7012 inst
.operands
[i
].present
= 1;
7016 inst
.error
= BAD_ARGS
;
7021 /* The parse routine should already have set inst.error, but set a
7022 default here just in case. */
7024 inst
.error
= _("syntax error");
7028 /* Do not backtrack over a trailing optional argument that
7029 absorbed some text. We will only fail again, with the
7030 'garbage following instruction' error message, which is
7031 probably less helpful than the current one. */
7032 if (backtrack_index
== i
&& backtrack_pos
!= str
7033 && upat
[i
+1] == OP_stop
)
7036 inst
.error
= _("syntax error");
7040 /* Try again, skipping the optional argument at backtrack_pos. */
7041 str
= backtrack_pos
;
7042 inst
.error
= backtrack_error
;
7043 inst
.operands
[backtrack_index
].present
= 0;
7044 i
= backtrack_index
;
7048 /* Check that we have parsed all the arguments. */
7049 if (*str
!= '\0' && !inst
.error
)
7050 inst
.error
= _("garbage following instruction");
7052 return inst
.error
? FAIL
: SUCCESS
;
7055 #undef po_char_or_fail
7056 #undef po_reg_or_fail
7057 #undef po_reg_or_goto
7058 #undef po_imm_or_fail
7059 #undef po_scalar_or_fail
7060 #undef po_barrier_or_imm
7062 /* Shorthand macro for instruction encoding functions issuing errors. */
7063 #define constraint(expr, err) \
7074 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7075 instructions are unpredictable if these registers are used. This
7076 is the BadReg predicate in ARM's Thumb-2 documentation. */
7077 #define reject_bad_reg(reg) \
7079 if (reg == REG_SP || reg == REG_PC) \
7081 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7086 /* If REG is R13 (the stack pointer), warn that its use is
7088 #define warn_deprecated_sp(reg) \
7090 if (warn_on_deprecated && reg == REG_SP) \
7091 as_warn (_("use of r13 is deprecated")); \
7094 /* Functions for operand encoding. ARM, then Thumb. */
7096 #define rotate_left(v, n) (v << n | v >> (32 - n))
7098 /* If VAL can be encoded in the immediate field of an ARM instruction,
7099 return the encoded form. Otherwise, return FAIL. */
7102 encode_arm_immediate (unsigned int val
)
7106 for (i
= 0; i
< 32; i
+= 2)
7107 if ((a
= rotate_left (val
, i
)) <= 0xff)
7108 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7113 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7114 return the encoded form. Otherwise, return FAIL. */
7116 encode_thumb32_immediate (unsigned int val
)
7123 for (i
= 1; i
<= 24; i
++)
7126 if ((val
& ~(0xff << i
)) == 0)
7127 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7131 if (val
== ((a
<< 16) | a
))
7133 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7137 if (val
== ((a
<< 16) | a
))
7138 return 0x200 | (a
>> 8);
7142 /* Encode a VFP SP or DP register number into inst.instruction. */
7145 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7147 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7150 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7153 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7156 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7161 first_error (_("D register out of range for selected VFP version"));
7169 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7173 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7177 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7181 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7185 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7189 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7197 /* Encode a <shift> in an ARM-format instruction. The immediate,
7198 if any, is handled by md_apply_fix. */
7200 encode_arm_shift (int i
)
7202 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7203 inst
.instruction
|= SHIFT_ROR
<< 5;
7206 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7207 if (inst
.operands
[i
].immisreg
)
7209 inst
.instruction
|= SHIFT_BY_REG
;
7210 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7213 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7218 encode_arm_shifter_operand (int i
)
7220 if (inst
.operands
[i
].isreg
)
7222 inst
.instruction
|= inst
.operands
[i
].reg
;
7223 encode_arm_shift (i
);
7227 inst
.instruction
|= INST_IMMEDIATE
;
7228 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7229 inst
.instruction
|= inst
.operands
[i
].imm
;
7233 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7235 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7238 Generate an error if the operand is not a register. */
7239 constraint (!inst
.operands
[i
].isreg
,
7240 _("Instruction does not support =N addresses"));
7242 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7244 if (inst
.operands
[i
].preind
)
7248 inst
.error
= _("instruction does not accept preindexed addressing");
7251 inst
.instruction
|= PRE_INDEX
;
7252 if (inst
.operands
[i
].writeback
)
7253 inst
.instruction
|= WRITE_BACK
;
7256 else if (inst
.operands
[i
].postind
)
7258 gas_assert (inst
.operands
[i
].writeback
);
7260 inst
.instruction
|= WRITE_BACK
;
7262 else /* unindexed - only for coprocessor */
7264 inst
.error
= _("instruction does not accept unindexed addressing");
7268 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7269 && (((inst
.instruction
& 0x000f0000) >> 16)
7270 == ((inst
.instruction
& 0x0000f000) >> 12)))
7271 as_warn ((inst
.instruction
& LOAD_BIT
)
7272 ? _("destination register same as write-back base")
7273 : _("source register same as write-back base"));
7276 /* inst.operands[i] was set up by parse_address. Encode it into an
7277 ARM-format mode 2 load or store instruction. If is_t is true,
7278 reject forms that cannot be used with a T instruction (i.e. not
7281 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7283 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7285 encode_arm_addr_mode_common (i
, is_t
);
7287 if (inst
.operands
[i
].immisreg
)
7289 constraint ((inst
.operands
[i
].imm
== REG_PC
7290 || (is_pc
&& inst
.operands
[i
].writeback
)),
7292 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7293 inst
.instruction
|= inst
.operands
[i
].imm
;
7294 if (!inst
.operands
[i
].negative
)
7295 inst
.instruction
|= INDEX_UP
;
7296 if (inst
.operands
[i
].shifted
)
7298 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7299 inst
.instruction
|= SHIFT_ROR
<< 5;
7302 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7303 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7307 else /* immediate offset in inst.reloc */
7309 if (is_pc
&& !inst
.reloc
.pc_rel
)
7311 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7313 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7314 cannot use PC in addressing.
7315 PC cannot be used in writeback addressing, either. */
7316 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7319 /* Use of PC in str is deprecated for ARMv7. */
7320 if (warn_on_deprecated
7322 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7323 as_warn (_("use of PC in this instruction is deprecated"));
7326 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7328 /* Prefer + for zero encoded value. */
7329 if (!inst
.operands
[i
].negative
)
7330 inst
.instruction
|= INDEX_UP
;
7331 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7336 /* inst.operands[i] was set up by parse_address. Encode it into an
7337 ARM-format mode 3 load or store instruction. Reject forms that
7338 cannot be used with such instructions. If is_t is true, reject
7339 forms that cannot be used with a T instruction (i.e. not
7342 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7344 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7346 inst
.error
= _("instruction does not accept scaled register index");
7350 encode_arm_addr_mode_common (i
, is_t
);
7352 if (inst
.operands
[i
].immisreg
)
7354 constraint ((inst
.operands
[i
].imm
== REG_PC
7355 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7357 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7359 inst
.instruction
|= inst
.operands
[i
].imm
;
7360 if (!inst
.operands
[i
].negative
)
7361 inst
.instruction
|= INDEX_UP
;
7363 else /* immediate offset in inst.reloc */
7365 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7366 && inst
.operands
[i
].writeback
),
7368 inst
.instruction
|= HWOFFSET_IMM
;
7369 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7371 /* Prefer + for zero encoded value. */
7372 if (!inst
.operands
[i
].negative
)
7373 inst
.instruction
|= INDEX_UP
;
7375 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7380 /* inst.operands[i] was set up by parse_address. Encode it into an
7381 ARM-format instruction. Reject all forms which cannot be encoded
7382 into a coprocessor load/store instruction. If wb_ok is false,
7383 reject use of writeback; if unind_ok is false, reject use of
7384 unindexed addressing. If reloc_override is not 0, use it instead
7385 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7386 (in which case it is preserved). */
7389 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7391 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7393 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7395 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7397 gas_assert (!inst
.operands
[i
].writeback
);
7400 inst
.error
= _("instruction does not support unindexed addressing");
7403 inst
.instruction
|= inst
.operands
[i
].imm
;
7404 inst
.instruction
|= INDEX_UP
;
7408 if (inst
.operands
[i
].preind
)
7409 inst
.instruction
|= PRE_INDEX
;
7411 if (inst
.operands
[i
].writeback
)
7413 if (inst
.operands
[i
].reg
== REG_PC
)
7415 inst
.error
= _("pc may not be used with write-back");
7420 inst
.error
= _("instruction does not support writeback");
7423 inst
.instruction
|= WRITE_BACK
;
7427 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7428 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7429 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7430 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7433 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7435 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7438 /* Prefer + for zero encoded value. */
7439 if (!inst
.operands
[i
].negative
)
7440 inst
.instruction
|= INDEX_UP
;
7445 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7446 Determine whether it can be performed with a move instruction; if
7447 it can, convert inst.instruction to that move instruction and
7448 return TRUE; if it can't, convert inst.instruction to a literal-pool
7449 load and return FALSE. If this is not a valid thing to do in the
7450 current context, set inst.error and return TRUE.
7452 inst.operands[i] describes the destination register. */
7455 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7460 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7464 if ((inst
.instruction
& tbit
) == 0)
7466 inst
.error
= _("invalid pseudo operation");
7469 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7471 inst
.error
= _("constant expression expected");
7474 if (inst
.reloc
.exp
.X_op
== O_constant
)
7478 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7480 /* This can be done with a mov(1) instruction. */
7481 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7482 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7488 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7491 /* This can be done with a mov instruction. */
7492 inst
.instruction
&= LITERAL_MASK
;
7493 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7494 inst
.instruction
|= value
& 0xfff;
7498 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7501 /* This can be done with a mvn instruction. */
7502 inst
.instruction
&= LITERAL_MASK
;
7503 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7504 inst
.instruction
|= value
& 0xfff;
7510 if (add_to_lit_pool () == FAIL
)
7512 inst
.error
= _("literal pool insertion failed");
7515 inst
.operands
[1].reg
= REG_PC
;
7516 inst
.operands
[1].isreg
= 1;
7517 inst
.operands
[1].preind
= 1;
7518 inst
.reloc
.pc_rel
= 1;
7519 inst
.reloc
.type
= (thumb_p
7520 ? BFD_RELOC_ARM_THUMB_OFFSET
7522 ? BFD_RELOC_ARM_HWLITERAL
7523 : BFD_RELOC_ARM_LITERAL
));
7527 /* Functions for instruction encoding, sorted by sub-architecture.
7528 First some generics; their names are taken from the conventional
7529 bit positions for register arguments in ARM format instructions. */
7539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7546 inst
.instruction
|= inst
.operands
[1].reg
;
7552 inst
.instruction
|= inst
.operands
[0].reg
;
7553 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7560 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7566 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7567 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7571 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7573 if (ARM_CPU_IS_ANY (cpu_variant
))
7575 as_warn ("%s", msg
);
7578 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
7590 unsigned Rn
= inst
.operands
[2].reg
;
7591 /* Enforce restrictions on SWP instruction. */
7592 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7594 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7595 _("Rn must not overlap other operands"));
7597 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7599 if (!check_obsolete (&arm_ext_v8
,
7600 _("swp{b} use is obsoleted for ARMv8 and later"))
7601 && warn_on_deprecated
7602 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
7603 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7607 inst
.instruction
|= inst
.operands
[1].reg
;
7608 inst
.instruction
|= Rn
<< 16;
7614 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7615 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7616 inst
.instruction
|= inst
.operands
[2].reg
;
7622 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7623 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7624 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7625 || inst
.reloc
.exp
.X_add_number
!= 0),
7627 inst
.instruction
|= inst
.operands
[0].reg
;
7628 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7629 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7635 inst
.instruction
|= inst
.operands
[0].imm
;
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7642 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7645 /* ARM instructions, in alphabetical order by function name (except
7646 that wrapper functions appear immediately after the function they
7649 /* This is a pseudo-op of the form "adr rd, label" to be converted
7650 into a relative address of the form "add rd, pc, #label-.-8". */
7655 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7657 /* Frag hacking will turn this into a sub instruction if the offset turns
7658 out to be negative. */
7659 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7660 inst
.reloc
.pc_rel
= 1;
7661 inst
.reloc
.exp
.X_add_number
-= 8;
7664 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7665 into a relative address of the form:
7666 add rd, pc, #low(label-.-8)"
7667 add rd, rd, #high(label-.-8)" */
7672 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7674 /* Frag hacking will turn this into a sub instruction if the offset turns
7675 out to be negative. */
7676 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7677 inst
.reloc
.pc_rel
= 1;
7678 inst
.size
= INSN_SIZE
* 2;
7679 inst
.reloc
.exp
.X_add_number
-= 8;
7685 if (!inst
.operands
[1].present
)
7686 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7688 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7689 encode_arm_shifter_operand (2);
7695 if (inst
.operands
[0].present
)
7696 inst
.instruction
|= inst
.operands
[0].imm
;
7698 inst
.instruction
|= 0xf;
7704 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7705 constraint (msb
> 32, _("bit-field extends past end of register"));
7706 /* The instruction encoding stores the LSB and MSB,
7707 not the LSB and width. */
7708 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7709 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7710 inst
.instruction
|= (msb
- 1) << 16;
7718 /* #0 in second position is alternative syntax for bfc, which is
7719 the same instruction but with REG_PC in the Rm field. */
7720 if (!inst
.operands
[1].isreg
)
7721 inst
.operands
[1].reg
= REG_PC
;
7723 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7724 constraint (msb
> 32, _("bit-field extends past end of register"));
7725 /* The instruction encoding stores the LSB and MSB,
7726 not the LSB and width. */
7727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7728 inst
.instruction
|= inst
.operands
[1].reg
;
7729 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7730 inst
.instruction
|= (msb
- 1) << 16;
7736 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7737 _("bit-field extends past end of register"));
7738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7739 inst
.instruction
|= inst
.operands
[1].reg
;
7740 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7741 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7744 /* ARM V5 breakpoint instruction (argument parse)
7745 BKPT <16 bit unsigned immediate>
7746 Instruction is not conditional.
7747 The bit pattern given in insns[] has the COND_ALWAYS condition,
7748 and it is an error if the caller tried to override that. */
7753 /* Top 12 of 16 bits to bits 19:8. */
7754 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7756 /* Bottom 4 of 16 bits to bits 3:0. */
7757 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7761 encode_branch (int default_reloc
)
7763 if (inst
.operands
[0].hasreloc
)
7765 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7766 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7767 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7768 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7769 ? BFD_RELOC_ARM_PLT32
7770 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7773 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7774 inst
.reloc
.pc_rel
= 1;
7781 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7782 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7785 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7792 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7794 if (inst
.cond
== COND_ALWAYS
)
7795 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7797 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7801 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7804 /* ARM V5 branch-link-exchange instruction (argument parse)
7805 BLX <target_addr> ie BLX(1)
7806 BLX{<condition>} <Rm> ie BLX(2)
7807 Unfortunately, there are two different opcodes for this mnemonic.
7808 So, the insns[].value is not used, and the code here zaps values
7809 into inst.instruction.
7810 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7815 if (inst
.operands
[0].isreg
)
7817 /* Arg is a register; the opcode provided by insns[] is correct.
7818 It is not illegal to do "blx pc", just useless. */
7819 if (inst
.operands
[0].reg
== REG_PC
)
7820 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7822 inst
.instruction
|= inst
.operands
[0].reg
;
7826 /* Arg is an address; this instruction cannot be executed
7827 conditionally, and the opcode must be adjusted.
7828 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7829 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7830 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7831 inst
.instruction
= 0xfa000000;
7832 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7839 bfd_boolean want_reloc
;
7841 if (inst
.operands
[0].reg
== REG_PC
)
7842 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7844 inst
.instruction
|= inst
.operands
[0].reg
;
7845 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7846 it is for ARMv4t or earlier. */
7847 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7848 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7852 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7857 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7861 /* ARM v5TEJ. Jump to Jazelle code. */
7866 if (inst
.operands
[0].reg
== REG_PC
)
7867 as_tsktsk (_("use of r15 in bxj is not really useful"));
7869 inst
.instruction
|= inst
.operands
[0].reg
;
7872 /* Co-processor data operation:
7873 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7874 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7878 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7879 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7880 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7881 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7882 inst
.instruction
|= inst
.operands
[4].reg
;
7883 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7889 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7890 encode_arm_shifter_operand (1);
7893 /* Transfer between coprocessor and ARM registers.
7894 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7899 No special properties. */
7901 struct deprecated_coproc_regs_s
7908 arm_feature_set deprecated
;
7909 arm_feature_set obsoleted
;
7910 const char *dep_msg
;
7911 const char *obs_msg
;
7914 #define DEPR_ACCESS_V8 \
7915 N_("This coprocessor register access is deprecated in ARMv8")
7917 /* Table of all deprecated coprocessor registers. */
7918 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
7920 {15, 0, 7, 10, 5, /* CP15DMB. */
7921 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7922 DEPR_ACCESS_V8
, NULL
},
7923 {15, 0, 7, 10, 4, /* CP15DSB. */
7924 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7925 DEPR_ACCESS_V8
, NULL
},
7926 {15, 0, 7, 5, 4, /* CP15ISB. */
7927 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7928 DEPR_ACCESS_V8
, NULL
},
7929 {14, 6, 1, 0, 0, /* TEEHBR. */
7930 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7931 DEPR_ACCESS_V8
, NULL
},
7932 {14, 6, 0, 0, 0, /* TEECR. */
7933 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7934 DEPR_ACCESS_V8
, NULL
},
7937 #undef DEPR_ACCESS_V8
7939 static const size_t deprecated_coproc_reg_count
=
7940 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
7948 Rd
= inst
.operands
[2].reg
;
7951 if (inst
.instruction
== 0xee000010
7952 || inst
.instruction
== 0xfe000010)
7954 reject_bad_reg (Rd
);
7957 constraint (Rd
== REG_SP
, BAD_SP
);
7962 if (inst
.instruction
== 0xe000010)
7963 constraint (Rd
== REG_PC
, BAD_PC
);
7966 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
7968 const struct deprecated_coproc_regs_s
*r
=
7969 deprecated_coproc_regs
+ i
;
7971 if (inst
.operands
[0].reg
== r
->cp
7972 && inst
.operands
[1].imm
== r
->opc1
7973 && inst
.operands
[3].reg
== r
->crn
7974 && inst
.operands
[4].reg
== r
->crm
7975 && inst
.operands
[5].imm
== r
->opc2
)
7977 if (! ARM_CPU_IS_ANY (cpu_variant
)
7978 && warn_on_deprecated
7979 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
7980 as_warn ("%s", r
->dep_msg
);
7984 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7985 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7986 inst
.instruction
|= Rd
<< 12;
7987 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7988 inst
.instruction
|= inst
.operands
[4].reg
;
7989 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7992 /* Transfer between coprocessor register and pair of ARM registers.
7993 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7998 Two XScale instructions are special cases of these:
8000 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8001 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8003 Result unpredictable if Rd or Rn is R15. */
8010 Rd
= inst
.operands
[2].reg
;
8011 Rn
= inst
.operands
[3].reg
;
8015 reject_bad_reg (Rd
);
8016 reject_bad_reg (Rn
);
8020 constraint (Rd
== REG_PC
, BAD_PC
);
8021 constraint (Rn
== REG_PC
, BAD_PC
);
8024 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8025 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8026 inst
.instruction
|= Rd
<< 12;
8027 inst
.instruction
|= Rn
<< 16;
8028 inst
.instruction
|= inst
.operands
[4].reg
;
8034 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8035 if (inst
.operands
[1].present
)
8037 inst
.instruction
|= CPSI_MMOD
;
8038 inst
.instruction
|= inst
.operands
[1].imm
;
8045 inst
.instruction
|= inst
.operands
[0].imm
;
8051 unsigned Rd
, Rn
, Rm
;
8053 Rd
= inst
.operands
[0].reg
;
8054 Rn
= (inst
.operands
[1].present
8055 ? inst
.operands
[1].reg
: Rd
);
8056 Rm
= inst
.operands
[2].reg
;
8058 constraint ((Rd
== REG_PC
), BAD_PC
);
8059 constraint ((Rn
== REG_PC
), BAD_PC
);
8060 constraint ((Rm
== REG_PC
), BAD_PC
);
8062 inst
.instruction
|= Rd
<< 16;
8063 inst
.instruction
|= Rn
<< 0;
8064 inst
.instruction
|= Rm
<< 8;
8070 /* There is no IT instruction in ARM mode. We
8071 process it to do the validation as if in
8072 thumb mode, just in case the code gets
8073 assembled for thumb using the unified syntax. */
8078 set_it_insn_type (IT_INSN
);
8079 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8080 now_it
.cc
= inst
.operands
[0].imm
;
8084 /* If there is only one register in the register list,
8085 then return its register number. Otherwise return -1. */
8087 only_one_reg_in_list (int range
)
8089 int i
= ffs (range
) - 1;
8090 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8094 encode_ldmstm(int from_push_pop_mnem
)
8096 int base_reg
= inst
.operands
[0].reg
;
8097 int range
= inst
.operands
[1].imm
;
8100 inst
.instruction
|= base_reg
<< 16;
8101 inst
.instruction
|= range
;
8103 if (inst
.operands
[1].writeback
)
8104 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8106 if (inst
.operands
[0].writeback
)
8108 inst
.instruction
|= WRITE_BACK
;
8109 /* Check for unpredictable uses of writeback. */
8110 if (inst
.instruction
& LOAD_BIT
)
8112 /* Not allowed in LDM type 2. */
8113 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8114 && ((range
& (1 << REG_PC
)) == 0))
8115 as_warn (_("writeback of base register is UNPREDICTABLE"));
8116 /* Only allowed if base reg not in list for other types. */
8117 else if (range
& (1 << base_reg
))
8118 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8122 /* Not allowed for type 2. */
8123 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8124 as_warn (_("writeback of base register is UNPREDICTABLE"));
8125 /* Only allowed if base reg not in list, or first in list. */
8126 else if ((range
& (1 << base_reg
))
8127 && (range
& ((1 << base_reg
) - 1)))
8128 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8132 /* If PUSH/POP has only one register, then use the A2 encoding. */
8133 one_reg
= only_one_reg_in_list (range
);
8134 if (from_push_pop_mnem
&& one_reg
>= 0)
8136 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8138 inst
.instruction
&= A_COND_MASK
;
8139 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8140 inst
.instruction
|= one_reg
<< 12;
8147 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8150 /* ARMv5TE load-consecutive (argument parse)
8159 constraint (inst
.operands
[0].reg
% 2 != 0,
8160 _("first transfer register must be even"));
8161 constraint (inst
.operands
[1].present
8162 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8163 _("can only transfer two consecutive registers"));
8164 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8165 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8167 if (!inst
.operands
[1].present
)
8168 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8170 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8171 register and the first register written; we have to diagnose
8172 overlap between the base and the second register written here. */
8174 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8175 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8176 as_warn (_("base register written back, and overlaps "
8177 "second transfer register"));
8179 if (!(inst
.instruction
& V4_STR_BIT
))
8181 /* For an index-register load, the index register must not overlap the
8182 destination (even if not write-back). */
8183 if (inst
.operands
[2].immisreg
8184 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8185 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8186 as_warn (_("index register overlaps transfer register"));
8188 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8189 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8195 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8196 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8197 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8198 || inst
.operands
[1].negative
8199 /* This can arise if the programmer has written
8201 or if they have mistakenly used a register name as the last
8204 It is very difficult to distinguish between these two cases
8205 because "rX" might actually be a label. ie the register
8206 name has been occluded by a symbol of the same name. So we
8207 just generate a general 'bad addressing mode' type error
8208 message and leave it up to the programmer to discover the
8209 true cause and fix their mistake. */
8210 || (inst
.operands
[1].reg
== REG_PC
),
8213 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8214 || inst
.reloc
.exp
.X_add_number
!= 0,
8215 _("offset must be zero in ARM encoding"));
8217 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8220 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8221 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8227 constraint (inst
.operands
[0].reg
% 2 != 0,
8228 _("even register required"));
8229 constraint (inst
.operands
[1].present
8230 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8231 _("can only load two consecutive registers"));
8232 /* If op 1 were present and equal to PC, this function wouldn't
8233 have been called in the first place. */
8234 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8237 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8240 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8241 which is not a multiple of four is UNPREDICTABLE. */
8243 check_ldr_r15_aligned (void)
8245 constraint (!(inst
.operands
[1].immisreg
)
8246 && (inst
.operands
[0].reg
== REG_PC
8247 && inst
.operands
[1].reg
== REG_PC
8248 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8249 _("ldr to register 15 must be 4-byte alligned"));
8255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8256 if (!inst
.operands
[1].isreg
)
8257 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
8259 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8260 check_ldr_r15_aligned ();
8266 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8268 if (inst
.operands
[1].preind
)
8270 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8271 || inst
.reloc
.exp
.X_add_number
!= 0,
8272 _("this instruction requires a post-indexed address"));
8274 inst
.operands
[1].preind
= 0;
8275 inst
.operands
[1].postind
= 1;
8276 inst
.operands
[1].writeback
= 1;
8278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8279 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8282 /* Halfword and signed-byte load/store operations. */
8287 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8289 if (!inst
.operands
[1].isreg
)
8290 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
8292 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8298 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8300 if (inst
.operands
[1].preind
)
8302 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8303 || inst
.reloc
.exp
.X_add_number
!= 0,
8304 _("this instruction requires a post-indexed address"));
8306 inst
.operands
[1].preind
= 0;
8307 inst
.operands
[1].postind
= 1;
8308 inst
.operands
[1].writeback
= 1;
8310 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8311 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8314 /* Co-processor register load/store.
8315 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8319 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8320 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8321 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8327 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8328 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8329 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8330 && !(inst
.instruction
& 0x00400000))
8331 as_tsktsk (_("Rd and Rm should be different in mla"));
8333 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8334 inst
.instruction
|= inst
.operands
[1].reg
;
8335 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8336 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8343 encode_arm_shifter_operand (1);
8346 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8353 top
= (inst
.instruction
& 0x00400000) != 0;
8354 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8355 _(":lower16: not allowed this instruction"));
8356 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8357 _(":upper16: not allowed instruction"));
8358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8359 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8361 imm
= inst
.reloc
.exp
.X_add_number
;
8362 /* The value is in two pieces: 0:11, 16:19. */
8363 inst
.instruction
|= (imm
& 0x00000fff);
8364 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8368 static void do_vfp_nsyn_opcode (const char *);
8371 do_vfp_nsyn_mrs (void)
8373 if (inst
.operands
[0].isvec
)
8375 if (inst
.operands
[1].reg
!= 1)
8376 first_error (_("operand 1 must be FPSCR"));
8377 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8378 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8379 do_vfp_nsyn_opcode ("fmstat");
8381 else if (inst
.operands
[1].isvec
)
8382 do_vfp_nsyn_opcode ("fmrx");
8390 do_vfp_nsyn_msr (void)
8392 if (inst
.operands
[0].isvec
)
8393 do_vfp_nsyn_opcode ("fmxr");
8403 unsigned Rt
= inst
.operands
[0].reg
;
8405 if (thumb_mode
&& Rt
== REG_SP
)
8407 inst
.error
= BAD_SP
;
8411 /* APSR_ sets isvec. All other refs to PC are illegal. */
8412 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8414 inst
.error
= BAD_PC
;
8418 /* If we get through parsing the register name, we just insert the number
8419 generated into the instruction without further validation. */
8420 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8421 inst
.instruction
|= (Rt
<< 12);
8427 unsigned Rt
= inst
.operands
[1].reg
;
8430 reject_bad_reg (Rt
);
8431 else if (Rt
== REG_PC
)
8433 inst
.error
= BAD_PC
;
8437 /* If we get through parsing the register name, we just insert the number
8438 generated into the instruction without further validation. */
8439 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8440 inst
.instruction
|= (Rt
<< 12);
8448 if (do_vfp_nsyn_mrs () == SUCCESS
)
8451 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8454 if (inst
.operands
[1].isreg
)
8456 br
= inst
.operands
[1].reg
;
8457 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8458 as_bad (_("bad register for mrs"));
8462 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8463 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8465 _("'APSR', 'CPSR' or 'SPSR' expected"));
8466 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8469 inst
.instruction
|= br
;
8472 /* Two possible forms:
8473 "{C|S}PSR_<field>, Rm",
8474 "{C|S}PSR_f, #expression". */
8479 if (do_vfp_nsyn_msr () == SUCCESS
)
8482 inst
.instruction
|= inst
.operands
[0].imm
;
8483 if (inst
.operands
[1].isreg
)
8484 inst
.instruction
|= inst
.operands
[1].reg
;
8487 inst
.instruction
|= INST_IMMEDIATE
;
8488 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8489 inst
.reloc
.pc_rel
= 0;
8496 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8498 if (!inst
.operands
[2].present
)
8499 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8500 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8501 inst
.instruction
|= inst
.operands
[1].reg
;
8502 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8504 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8505 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8506 as_tsktsk (_("Rd and Rm should be different in mul"));
8509 /* Long Multiply Parser
8510 UMULL RdLo, RdHi, Rm, Rs
8511 SMULL RdLo, RdHi, Rm, Rs
8512 UMLAL RdLo, RdHi, Rm, Rs
8513 SMLAL RdLo, RdHi, Rm, Rs. */
8518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8519 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8520 inst
.instruction
|= inst
.operands
[2].reg
;
8521 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8523 /* rdhi and rdlo must be different. */
8524 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8525 as_tsktsk (_("rdhi and rdlo must be different"));
8527 /* rdhi, rdlo and rm must all be different before armv6. */
8528 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8529 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8530 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8531 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8537 if (inst
.operands
[0].present
8538 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8540 /* Architectural NOP hints are CPSR sets with no bits selected. */
8541 inst
.instruction
&= 0xf0000000;
8542 inst
.instruction
|= 0x0320f000;
8543 if (inst
.operands
[0].present
)
8544 inst
.instruction
|= inst
.operands
[0].imm
;
8548 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8549 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8550 Condition defaults to COND_ALWAYS.
8551 Error if Rd, Rn or Rm are R15. */
8556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8557 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8558 inst
.instruction
|= inst
.operands
[2].reg
;
8559 if (inst
.operands
[3].present
)
8560 encode_arm_shift (3);
8563 /* ARM V6 PKHTB (Argument Parse). */
8568 if (!inst
.operands
[3].present
)
8570 /* If the shift specifier is omitted, turn the instruction
8571 into pkhbt rd, rm, rn. */
8572 inst
.instruction
&= 0xfff00010;
8573 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8574 inst
.instruction
|= inst
.operands
[1].reg
;
8575 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8579 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8580 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8581 inst
.instruction
|= inst
.operands
[2].reg
;
8582 encode_arm_shift (3);
8586 /* ARMv5TE: Preload-Cache
8587 MP Extensions: Preload for write
8591 Syntactically, like LDR with B=1, W=0, L=1. */
8596 constraint (!inst
.operands
[0].isreg
,
8597 _("'[' expected after PLD mnemonic"));
8598 constraint (inst
.operands
[0].postind
,
8599 _("post-indexed expression used in preload instruction"));
8600 constraint (inst
.operands
[0].writeback
,
8601 _("writeback used in preload instruction"));
8602 constraint (!inst
.operands
[0].preind
,
8603 _("unindexed addressing used in preload instruction"));
8604 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8607 /* ARMv7: PLI <addr_mode> */
8611 constraint (!inst
.operands
[0].isreg
,
8612 _("'[' expected after PLI mnemonic"));
8613 constraint (inst
.operands
[0].postind
,
8614 _("post-indexed expression used in preload instruction"));
8615 constraint (inst
.operands
[0].writeback
,
8616 _("writeback used in preload instruction"));
8617 constraint (!inst
.operands
[0].preind
,
8618 _("unindexed addressing used in preload instruction"));
8619 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8620 inst
.instruction
&= ~PRE_INDEX
;
8626 inst
.operands
[1] = inst
.operands
[0];
8627 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8628 inst
.operands
[0].isreg
= 1;
8629 inst
.operands
[0].writeback
= 1;
8630 inst
.operands
[0].reg
= REG_SP
;
8631 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
8634 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8635 word at the specified address and the following word
8637 Unconditionally executed.
8638 Error if Rn is R15. */
8643 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8644 if (inst
.operands
[0].writeback
)
8645 inst
.instruction
|= WRITE_BACK
;
8648 /* ARM V6 ssat (argument parse). */
8653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8654 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8655 inst
.instruction
|= inst
.operands
[2].reg
;
8657 if (inst
.operands
[3].present
)
8658 encode_arm_shift (3);
8661 /* ARM V6 usat (argument parse). */
8666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8667 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8668 inst
.instruction
|= inst
.operands
[2].reg
;
8670 if (inst
.operands
[3].present
)
8671 encode_arm_shift (3);
8674 /* ARM V6 ssat16 (argument parse). */
8679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8680 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8681 inst
.instruction
|= inst
.operands
[2].reg
;
8687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8688 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8689 inst
.instruction
|= inst
.operands
[2].reg
;
8692 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8693 preserving the other bits.
8695 setend <endian_specifier>, where <endian_specifier> is either
8701 if (warn_on_deprecated
8702 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8703 as_warn (_("setend use is deprecated for ARMv8"));
8705 if (inst
.operands
[0].imm
)
8706 inst
.instruction
|= 0x200;
8712 unsigned int Rm
= (inst
.operands
[1].present
8713 ? inst
.operands
[1].reg
8714 : inst
.operands
[0].reg
);
8716 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8717 inst
.instruction
|= Rm
;
8718 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8720 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8721 inst
.instruction
|= SHIFT_BY_REG
;
8722 /* PR 12854: Error on extraneous shifts. */
8723 constraint (inst
.operands
[2].shifted
,
8724 _("extraneous shift as part of operand to shift insn"));
8727 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8733 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8734 inst
.reloc
.pc_rel
= 0;
8740 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8741 inst
.reloc
.pc_rel
= 0;
8747 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8748 inst
.reloc
.pc_rel
= 0;
8751 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8752 SMLAxy{cond} Rd,Rm,Rs,Rn
8753 SMLAWy{cond} Rd,Rm,Rs,Rn
8754 Error if any register is R15. */
8759 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8760 inst
.instruction
|= inst
.operands
[1].reg
;
8761 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8762 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8765 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8766 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8767 Error if any register is R15.
8768 Warning if Rdlo == Rdhi. */
8773 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8774 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8775 inst
.instruction
|= inst
.operands
[2].reg
;
8776 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8778 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8779 as_tsktsk (_("rdhi and rdlo must be different"));
8782 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8783 SMULxy{cond} Rd,Rm,Rs
8784 Error if any register is R15. */
8789 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8790 inst
.instruction
|= inst
.operands
[1].reg
;
8791 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8794 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8795 the same for both ARM and Thumb-2. */
8802 if (inst
.operands
[0].present
)
8804 reg
= inst
.operands
[0].reg
;
8805 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8810 inst
.instruction
|= reg
<< 16;
8811 inst
.instruction
|= inst
.operands
[1].imm
;
8812 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8813 inst
.instruction
|= WRITE_BACK
;
8816 /* ARM V6 strex (argument parse). */
8821 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8822 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8823 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8824 || inst
.operands
[2].negative
8825 /* See comment in do_ldrex(). */
8826 || (inst
.operands
[2].reg
== REG_PC
),
8829 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8830 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8832 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8833 || inst
.reloc
.exp
.X_add_number
!= 0,
8834 _("offset must be zero in ARM encoding"));
8836 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8837 inst
.instruction
|= inst
.operands
[1].reg
;
8838 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8839 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8845 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8846 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8847 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8848 || inst
.operands
[2].negative
,
8851 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8852 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8860 constraint (inst
.operands
[1].reg
% 2 != 0,
8861 _("even register required"));
8862 constraint (inst
.operands
[2].present
8863 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8864 _("can only store two consecutive registers"));
8865 /* If op 2 were present and equal to PC, this function wouldn't
8866 have been called in the first place. */
8867 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8869 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8870 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8871 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8875 inst
.instruction
|= inst
.operands
[1].reg
;
8876 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8883 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8884 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8892 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8893 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8898 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8899 extends it to 32-bits, and adds the result to a value in another
8900 register. You can specify a rotation by 0, 8, 16, or 24 bits
8901 before extracting the 16-bit value.
8902 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8903 Condition defaults to COND_ALWAYS.
8904 Error if any register uses R15. */
8909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8910 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8911 inst
.instruction
|= inst
.operands
[2].reg
;
8912 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8917 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8918 Condition defaults to COND_ALWAYS.
8919 Error if any register uses R15. */
8924 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8925 inst
.instruction
|= inst
.operands
[1].reg
;
8926 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8929 /* VFP instructions. In a logical order: SP variant first, monad
8930 before dyad, arithmetic then move then load/store. */
8933 do_vfp_sp_monadic (void)
8935 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8936 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8940 do_vfp_sp_dyadic (void)
8942 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8943 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8944 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8948 do_vfp_sp_compare_z (void)
8950 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8954 do_vfp_dp_sp_cvt (void)
8956 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8957 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8961 do_vfp_sp_dp_cvt (void)
8963 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8964 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8968 do_vfp_reg_from_sp (void)
8970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8971 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8975 do_vfp_reg2_from_sp2 (void)
8977 constraint (inst
.operands
[2].imm
!= 2,
8978 _("only two consecutive VFP SP registers allowed here"));
8979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8980 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8981 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8985 do_vfp_sp_from_reg (void)
8987 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8988 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8992 do_vfp_sp2_from_reg2 (void)
8994 constraint (inst
.operands
[0].imm
!= 2,
8995 _("only two consecutive VFP SP registers allowed here"));
8996 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8997 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8998 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9002 do_vfp_sp_ldst (void)
9004 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9005 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9009 do_vfp_dp_ldst (void)
9011 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9012 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9017 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9019 if (inst
.operands
[0].writeback
)
9020 inst
.instruction
|= WRITE_BACK
;
9022 constraint (ldstm_type
!= VFP_LDSTMIA
,
9023 _("this addressing mode requires base-register writeback"));
9024 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9025 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9026 inst
.instruction
|= inst
.operands
[1].imm
;
9030 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9034 if (inst
.operands
[0].writeback
)
9035 inst
.instruction
|= WRITE_BACK
;
9037 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9038 _("this addressing mode requires base-register writeback"));
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9041 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9043 count
= inst
.operands
[1].imm
<< 1;
9044 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9047 inst
.instruction
|= count
;
9051 do_vfp_sp_ldstmia (void)
9053 vfp_sp_ldstm (VFP_LDSTMIA
);
9057 do_vfp_sp_ldstmdb (void)
9059 vfp_sp_ldstm (VFP_LDSTMDB
);
9063 do_vfp_dp_ldstmia (void)
9065 vfp_dp_ldstm (VFP_LDSTMIA
);
9069 do_vfp_dp_ldstmdb (void)
9071 vfp_dp_ldstm (VFP_LDSTMDB
);
9075 do_vfp_xp_ldstmia (void)
9077 vfp_dp_ldstm (VFP_LDSTMIAX
);
9081 do_vfp_xp_ldstmdb (void)
9083 vfp_dp_ldstm (VFP_LDSTMDBX
);
9087 do_vfp_dp_rd_rm (void)
9089 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9090 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9094 do_vfp_dp_rn_rd (void)
9096 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9097 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9101 do_vfp_dp_rd_rn (void)
9103 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9104 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9108 do_vfp_dp_rd_rn_rm (void)
9110 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9111 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9112 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9118 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9122 do_vfp_dp_rm_rd_rn (void)
9124 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9125 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9126 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9129 /* VFPv3 instructions. */
9131 do_vfp_sp_const (void)
9133 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9134 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9135 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9139 do_vfp_dp_const (void)
9141 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9142 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9143 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9147 vfp_conv (int srcsize
)
9149 int immbits
= srcsize
- inst
.operands
[1].imm
;
9151 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9153 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9154 i.e. immbits must be in range 0 - 16. */
9155 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9158 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9160 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9161 i.e. immbits must be in range 0 - 31. */
9162 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9166 inst
.instruction
|= (immbits
& 1) << 5;
9167 inst
.instruction
|= (immbits
>> 1);
9171 do_vfp_sp_conv_16 (void)
9173 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9178 do_vfp_dp_conv_16 (void)
9180 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9185 do_vfp_sp_conv_32 (void)
9187 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9192 do_vfp_dp_conv_32 (void)
9194 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9198 /* FPA instructions. Also in a logical order. */
9203 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9204 inst
.instruction
|= inst
.operands
[1].reg
;
9208 do_fpa_ldmstm (void)
9210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9211 switch (inst
.operands
[1].imm
)
9213 case 1: inst
.instruction
|= CP_T_X
; break;
9214 case 2: inst
.instruction
|= CP_T_Y
; break;
9215 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9220 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9222 /* The instruction specified "ea" or "fd", so we can only accept
9223 [Rn]{!}. The instruction does not really support stacking or
9224 unstacking, so we have to emulate these by setting appropriate
9225 bits and offsets. */
9226 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9227 || inst
.reloc
.exp
.X_add_number
!= 0,
9228 _("this instruction does not support indexing"));
9230 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9231 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9233 if (!(inst
.instruction
& INDEX_UP
))
9234 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9236 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9238 inst
.operands
[2].preind
= 0;
9239 inst
.operands
[2].postind
= 1;
9243 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9246 /* iWMMXt instructions: strictly in alphabetical order. */
9249 do_iwmmxt_tandorc (void)
9251 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9255 do_iwmmxt_textrc (void)
9257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9258 inst
.instruction
|= inst
.operands
[1].imm
;
9262 do_iwmmxt_textrm (void)
9264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9265 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9266 inst
.instruction
|= inst
.operands
[2].imm
;
9270 do_iwmmxt_tinsr (void)
9272 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9273 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9274 inst
.instruction
|= inst
.operands
[2].imm
;
9278 do_iwmmxt_tmia (void)
9280 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9281 inst
.instruction
|= inst
.operands
[1].reg
;
9282 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9286 do_iwmmxt_waligni (void)
9288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9289 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9290 inst
.instruction
|= inst
.operands
[2].reg
;
9291 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9295 do_iwmmxt_wmerge (void)
9297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9298 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9299 inst
.instruction
|= inst
.operands
[2].reg
;
9300 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9304 do_iwmmxt_wmov (void)
9306 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9308 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9309 inst
.instruction
|= inst
.operands
[1].reg
;
9313 do_iwmmxt_wldstbh (void)
9316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9318 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9320 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9321 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9325 do_iwmmxt_wldstw (void)
9327 /* RIWR_RIWC clears .isreg for a control register. */
9328 if (!inst
.operands
[0].isreg
)
9330 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9331 inst
.instruction
|= 0xf0000000;
9334 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9335 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9339 do_iwmmxt_wldstd (void)
9341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9342 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9343 && inst
.operands
[1].immisreg
)
9345 inst
.instruction
&= ~0x1a000ff;
9346 inst
.instruction
|= (0xf << 28);
9347 if (inst
.operands
[1].preind
)
9348 inst
.instruction
|= PRE_INDEX
;
9349 if (!inst
.operands
[1].negative
)
9350 inst
.instruction
|= INDEX_UP
;
9351 if (inst
.operands
[1].writeback
)
9352 inst
.instruction
|= WRITE_BACK
;
9353 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9354 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9355 inst
.instruction
|= inst
.operands
[1].imm
;
9358 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9362 do_iwmmxt_wshufh (void)
9364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9365 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9366 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9367 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9371 do_iwmmxt_wzero (void)
9373 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9374 inst
.instruction
|= inst
.operands
[0].reg
;
9375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9376 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9380 do_iwmmxt_wrwrwr_or_imm5 (void)
9382 if (inst
.operands
[2].isreg
)
9385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9386 _("immediate operand requires iWMMXt2"));
9388 if (inst
.operands
[2].imm
== 0)
9390 switch ((inst
.instruction
>> 20) & 0xf)
9396 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9397 inst
.operands
[2].imm
= 16;
9398 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9404 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9405 inst
.operands
[2].imm
= 32;
9406 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9413 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9415 wrn
= (inst
.instruction
>> 16) & 0xf;
9416 inst
.instruction
&= 0xff0fff0f;
9417 inst
.instruction
|= wrn
;
9418 /* Bail out here; the instruction is now assembled. */
9423 /* Map 32 -> 0, etc. */
9424 inst
.operands
[2].imm
&= 0x1f;
9425 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9429 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9430 operations first, then control, shift, and load/store. */
9432 /* Insns like "foo X,Y,Z". */
9435 do_mav_triple (void)
9437 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9438 inst
.instruction
|= inst
.operands
[1].reg
;
9439 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9442 /* Insns like "foo W,X,Y,Z".
9443 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9448 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9449 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9450 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9451 inst
.instruction
|= inst
.operands
[3].reg
;
9454 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9458 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9461 /* Maverick shift immediate instructions.
9462 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9463 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9468 int imm
= inst
.operands
[2].imm
;
9470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9471 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9473 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9474 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9475 Bit 4 should be 0. */
9476 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9478 inst
.instruction
|= imm
;
9481 /* XScale instructions. Also sorted arithmetic before move. */
9483 /* Xscale multiply-accumulate (argument parse)
9486 MIAxycc acc0,Rm,Rs. */
9491 inst
.instruction
|= inst
.operands
[1].reg
;
9492 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9495 /* Xscale move-accumulator-register (argument parse)
9497 MARcc acc0,RdLo,RdHi. */
9502 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9503 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9506 /* Xscale move-register-accumulator (argument parse)
9508 MRAcc RdLo,RdHi,acc0. */
9513 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9515 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9518 /* Encoding functions relevant only to Thumb. */
9520 /* inst.operands[i] is a shifted-register operand; encode
9521 it into inst.instruction in the format used by Thumb32. */
9524 encode_thumb32_shifted_operand (int i
)
9526 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9527 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9529 constraint (inst
.operands
[i
].immisreg
,
9530 _("shift by register not allowed in thumb mode"));
9531 inst
.instruction
|= inst
.operands
[i
].reg
;
9532 if (shift
== SHIFT_RRX
)
9533 inst
.instruction
|= SHIFT_ROR
<< 4;
9536 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9537 _("expression too complex"));
9539 constraint (value
> 32
9540 || (value
== 32 && (shift
== SHIFT_LSL
9541 || shift
== SHIFT_ROR
)),
9542 _("shift expression is too large"));
9546 else if (value
== 32)
9549 inst
.instruction
|= shift
<< 4;
9550 inst
.instruction
|= (value
& 0x1c) << 10;
9551 inst
.instruction
|= (value
& 0x03) << 6;
9556 /* inst.operands[i] was set up by parse_address. Encode it into a
9557 Thumb32 format load or store instruction. Reject forms that cannot
9558 be used with such instructions. If is_t is true, reject forms that
9559 cannot be used with a T instruction; if is_d is true, reject forms
9560 that cannot be used with a D instruction. If it is a store insn,
9564 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9566 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9568 constraint (!inst
.operands
[i
].isreg
,
9569 _("Instruction does not support =N addresses"));
9571 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9572 if (inst
.operands
[i
].immisreg
)
9574 constraint (is_pc
, BAD_PC_ADDRESSING
);
9575 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9576 constraint (inst
.operands
[i
].negative
,
9577 _("Thumb does not support negative register indexing"));
9578 constraint (inst
.operands
[i
].postind
,
9579 _("Thumb does not support register post-indexing"));
9580 constraint (inst
.operands
[i
].writeback
,
9581 _("Thumb does not support register indexing with writeback"));
9582 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9583 _("Thumb supports only LSL in shifted register indexing"));
9585 inst
.instruction
|= inst
.operands
[i
].imm
;
9586 if (inst
.operands
[i
].shifted
)
9588 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9589 _("expression too complex"));
9590 constraint (inst
.reloc
.exp
.X_add_number
< 0
9591 || inst
.reloc
.exp
.X_add_number
> 3,
9592 _("shift out of range"));
9593 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9595 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9597 else if (inst
.operands
[i
].preind
)
9599 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9600 constraint (is_t
&& inst
.operands
[i
].writeback
,
9601 _("cannot use writeback with this instruction"));
9602 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
9607 inst
.instruction
|= 0x01000000;
9608 if (inst
.operands
[i
].writeback
)
9609 inst
.instruction
|= 0x00200000;
9613 inst
.instruction
|= 0x00000c00;
9614 if (inst
.operands
[i
].writeback
)
9615 inst
.instruction
|= 0x00000100;
9617 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9619 else if (inst
.operands
[i
].postind
)
9621 gas_assert (inst
.operands
[i
].writeback
);
9622 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9623 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9626 inst
.instruction
|= 0x00200000;
9628 inst
.instruction
|= 0x00000900;
9629 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9631 else /* unindexed - only for coprocessor */
9632 inst
.error
= _("instruction does not accept unindexed addressing");
9635 /* Table of Thumb instructions which exist in both 16- and 32-bit
9636 encodings (the latter only in post-V6T2 cores). The index is the
9637 value used in the insns table below. When there is more than one
9638 possible 16-bit encoding for the instruction, this table always
9640 Also contains several pseudo-instructions used during relaxation. */
9641 #define T16_32_TAB \
9642 X(_adc, 4140, eb400000), \
9643 X(_adcs, 4140, eb500000), \
9644 X(_add, 1c00, eb000000), \
9645 X(_adds, 1c00, eb100000), \
9646 X(_addi, 0000, f1000000), \
9647 X(_addis, 0000, f1100000), \
9648 X(_add_pc,000f, f20f0000), \
9649 X(_add_sp,000d, f10d0000), \
9650 X(_adr, 000f, f20f0000), \
9651 X(_and, 4000, ea000000), \
9652 X(_ands, 4000, ea100000), \
9653 X(_asr, 1000, fa40f000), \
9654 X(_asrs, 1000, fa50f000), \
9655 X(_b, e000, f000b000), \
9656 X(_bcond, d000, f0008000), \
9657 X(_bic, 4380, ea200000), \
9658 X(_bics, 4380, ea300000), \
9659 X(_cmn, 42c0, eb100f00), \
9660 X(_cmp, 2800, ebb00f00), \
9661 X(_cpsie, b660, f3af8400), \
9662 X(_cpsid, b670, f3af8600), \
9663 X(_cpy, 4600, ea4f0000), \
9664 X(_dec_sp,80dd, f1ad0d00), \
9665 X(_eor, 4040, ea800000), \
9666 X(_eors, 4040, ea900000), \
9667 X(_inc_sp,00dd, f10d0d00), \
9668 X(_ldmia, c800, e8900000), \
9669 X(_ldr, 6800, f8500000), \
9670 X(_ldrb, 7800, f8100000), \
9671 X(_ldrh, 8800, f8300000), \
9672 X(_ldrsb, 5600, f9100000), \
9673 X(_ldrsh, 5e00, f9300000), \
9674 X(_ldr_pc,4800, f85f0000), \
9675 X(_ldr_pc2,4800, f85f0000), \
9676 X(_ldr_sp,9800, f85d0000), \
9677 X(_lsl, 0000, fa00f000), \
9678 X(_lsls, 0000, fa10f000), \
9679 X(_lsr, 0800, fa20f000), \
9680 X(_lsrs, 0800, fa30f000), \
9681 X(_mov, 2000, ea4f0000), \
9682 X(_movs, 2000, ea5f0000), \
9683 X(_mul, 4340, fb00f000), \
9684 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9685 X(_mvn, 43c0, ea6f0000), \
9686 X(_mvns, 43c0, ea7f0000), \
9687 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9688 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9689 X(_orr, 4300, ea400000), \
9690 X(_orrs, 4300, ea500000), \
9691 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9692 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9693 X(_rev, ba00, fa90f080), \
9694 X(_rev16, ba40, fa90f090), \
9695 X(_revsh, bac0, fa90f0b0), \
9696 X(_ror, 41c0, fa60f000), \
9697 X(_rors, 41c0, fa70f000), \
9698 X(_sbc, 4180, eb600000), \
9699 X(_sbcs, 4180, eb700000), \
9700 X(_stmia, c000, e8800000), \
9701 X(_str, 6000, f8400000), \
9702 X(_strb, 7000, f8000000), \
9703 X(_strh, 8000, f8200000), \
9704 X(_str_sp,9000, f84d0000), \
9705 X(_sub, 1e00, eba00000), \
9706 X(_subs, 1e00, ebb00000), \
9707 X(_subi, 8000, f1a00000), \
9708 X(_subis, 8000, f1b00000), \
9709 X(_sxtb, b240, fa4ff080), \
9710 X(_sxth, b200, fa0ff080), \
9711 X(_tst, 4200, ea100f00), \
9712 X(_uxtb, b2c0, fa5ff080), \
9713 X(_uxth, b280, fa1ff080), \
9714 X(_nop, bf00, f3af8000), \
9715 X(_yield, bf10, f3af8001), \
9716 X(_wfe, bf20, f3af8002), \
9717 X(_wfi, bf30, f3af8003), \
9718 X(_sev, bf40, f3af8004), \
9719 X(_sevl, bf50, f3af8005), \
9720 X(_udf, de00, f7f0a000)
9722 /* To catch errors in encoding functions, the codes are all offset by
9723 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9724 as 16-bit instructions. */
9725 #define X(a,b,c) T_MNEM##a
9726 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9729 #define X(a,b,c) 0x##b
9730 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9731 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9734 #define X(a,b,c) 0x##c
9735 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9736 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9737 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9741 /* Thumb instruction encoders, in alphabetical order. */
9746 do_t_add_sub_w (void)
9750 Rd
= inst
.operands
[0].reg
;
9751 Rn
= inst
.operands
[1].reg
;
9753 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9754 is the SP-{plus,minus}-immediate form of the instruction. */
9756 constraint (Rd
== REG_PC
, BAD_PC
);
9758 reject_bad_reg (Rd
);
9760 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9761 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9764 /* Parse an add or subtract instruction. We get here with inst.instruction
9765 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9772 Rd
= inst
.operands
[0].reg
;
9773 Rs
= (inst
.operands
[1].present
9774 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9775 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9778 set_it_insn_type_last ();
9786 flags
= (inst
.instruction
== T_MNEM_adds
9787 || inst
.instruction
== T_MNEM_subs
);
9789 narrow
= !in_it_block ();
9791 narrow
= in_it_block ();
9792 if (!inst
.operands
[2].isreg
)
9796 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9798 add
= (inst
.instruction
== T_MNEM_add
9799 || inst
.instruction
== T_MNEM_adds
);
9801 if (inst
.size_req
!= 4)
9803 /* Attempt to use a narrow opcode, with relaxation if
9805 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9806 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9807 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9808 opcode
= T_MNEM_add_sp
;
9809 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9810 opcode
= T_MNEM_add_pc
;
9811 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9814 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9816 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9820 inst
.instruction
= THUMB_OP16(opcode
);
9821 inst
.instruction
|= (Rd
<< 4) | Rs
;
9822 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9823 if (inst
.size_req
!= 2)
9824 inst
.relax
= opcode
;
9827 constraint (inst
.size_req
== 2, BAD_HIREG
);
9829 if (inst
.size_req
== 4
9830 || (inst
.size_req
!= 2 && !opcode
))
9834 constraint (add
, BAD_PC
);
9835 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9836 _("only SUBS PC, LR, #const allowed"));
9837 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9838 _("expression too complex"));
9839 constraint (inst
.reloc
.exp
.X_add_number
< 0
9840 || inst
.reloc
.exp
.X_add_number
> 0xff,
9841 _("immediate value out of range"));
9842 inst
.instruction
= T2_SUBS_PC_LR
9843 | inst
.reloc
.exp
.X_add_number
;
9844 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9847 else if (Rs
== REG_PC
)
9849 /* Always use addw/subw. */
9850 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9851 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9855 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9856 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9859 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9861 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9863 inst
.instruction
|= Rd
<< 8;
9864 inst
.instruction
|= Rs
<< 16;
9869 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9870 unsigned int shift
= inst
.operands
[2].shift_kind
;
9872 Rn
= inst
.operands
[2].reg
;
9873 /* See if we can do this with a 16-bit instruction. */
9874 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9876 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9881 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9882 || inst
.instruction
== T_MNEM_add
)
9885 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9889 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9891 /* Thumb-1 cores (except v6-M) require at least one high
9892 register in a narrow non flag setting add. */
9893 if (Rd
> 7 || Rn
> 7
9894 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9895 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9902 inst
.instruction
= T_OPCODE_ADD_HI
;
9903 inst
.instruction
|= (Rd
& 8) << 4;
9904 inst
.instruction
|= (Rd
& 7);
9905 inst
.instruction
|= Rn
<< 3;
9911 constraint (Rd
== REG_PC
, BAD_PC
);
9912 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9913 constraint (Rs
== REG_PC
, BAD_PC
);
9914 reject_bad_reg (Rn
);
9916 /* If we get here, it can't be done in 16 bits. */
9917 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9918 _("shift must be constant"));
9919 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9920 inst
.instruction
|= Rd
<< 8;
9921 inst
.instruction
|= Rs
<< 16;
9922 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9923 _("shift value over 3 not allowed in thumb mode"));
9924 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9925 _("only LSL shift allowed in thumb mode"));
9926 encode_thumb32_shifted_operand (2);
9931 constraint (inst
.instruction
== T_MNEM_adds
9932 || inst
.instruction
== T_MNEM_subs
,
9935 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9937 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9938 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9941 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9943 inst
.instruction
|= (Rd
<< 4) | Rs
;
9944 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9948 Rn
= inst
.operands
[2].reg
;
9949 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9951 /* We now have Rd, Rs, and Rn set to registers. */
9952 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9954 /* Can't do this for SUB. */
9955 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9956 inst
.instruction
= T_OPCODE_ADD_HI
;
9957 inst
.instruction
|= (Rd
& 8) << 4;
9958 inst
.instruction
|= (Rd
& 7);
9960 inst
.instruction
|= Rn
<< 3;
9962 inst
.instruction
|= Rs
<< 3;
9964 constraint (1, _("dest must overlap one source register"));
9968 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9969 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9970 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9980 Rd
= inst
.operands
[0].reg
;
9981 reject_bad_reg (Rd
);
9983 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9985 /* Defer to section relaxation. */
9986 inst
.relax
= inst
.instruction
;
9987 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9988 inst
.instruction
|= Rd
<< 4;
9990 else if (unified_syntax
&& inst
.size_req
!= 2)
9992 /* Generate a 32-bit opcode. */
9993 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9994 inst
.instruction
|= Rd
<< 8;
9995 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9996 inst
.reloc
.pc_rel
= 1;
10000 /* Generate a 16-bit opcode. */
10001 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10002 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10003 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10004 inst
.reloc
.pc_rel
= 1;
10006 inst
.instruction
|= Rd
<< 4;
10010 /* Arithmetic instructions for which there is just one 16-bit
10011 instruction encoding, and it allows only two low registers.
10012 For maximal compatibility with ARM syntax, we allow three register
10013 operands even when Thumb-32 instructions are not available, as long
10014 as the first two are identical. For instance, both "sbc r0,r1" and
10015 "sbc r0,r0,r1" are allowed. */
10021 Rd
= inst
.operands
[0].reg
;
10022 Rs
= (inst
.operands
[1].present
10023 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10024 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10025 Rn
= inst
.operands
[2].reg
;
10027 reject_bad_reg (Rd
);
10028 reject_bad_reg (Rs
);
10029 if (inst
.operands
[2].isreg
)
10030 reject_bad_reg (Rn
);
10032 if (unified_syntax
)
10034 if (!inst
.operands
[2].isreg
)
10036 /* For an immediate, we always generate a 32-bit opcode;
10037 section relaxation will shrink it later if possible. */
10038 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10039 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10040 inst
.instruction
|= Rd
<< 8;
10041 inst
.instruction
|= Rs
<< 16;
10042 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10046 bfd_boolean narrow
;
10048 /* See if we can do this with a 16-bit instruction. */
10049 if (THUMB_SETS_FLAGS (inst
.instruction
))
10050 narrow
= !in_it_block ();
10052 narrow
= in_it_block ();
10054 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10056 if (inst
.operands
[2].shifted
)
10058 if (inst
.size_req
== 4)
10064 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10065 inst
.instruction
|= Rd
;
10066 inst
.instruction
|= Rn
<< 3;
10070 /* If we get here, it can't be done in 16 bits. */
10071 constraint (inst
.operands
[2].shifted
10072 && inst
.operands
[2].immisreg
,
10073 _("shift must be constant"));
10074 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10075 inst
.instruction
|= Rd
<< 8;
10076 inst
.instruction
|= Rs
<< 16;
10077 encode_thumb32_shifted_operand (2);
10082 /* On its face this is a lie - the instruction does set the
10083 flags. However, the only supported mnemonic in this mode
10084 says it doesn't. */
10085 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10087 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10088 _("unshifted register required"));
10089 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10090 constraint (Rd
!= Rs
,
10091 _("dest and source1 must be the same register"));
10093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10094 inst
.instruction
|= Rd
;
10095 inst
.instruction
|= Rn
<< 3;
10099 /* Similarly, but for instructions where the arithmetic operation is
10100 commutative, so we can allow either of them to be different from
10101 the destination operand in a 16-bit instruction. For instance, all
10102 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10109 Rd
= inst
.operands
[0].reg
;
10110 Rs
= (inst
.operands
[1].present
10111 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10112 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10113 Rn
= inst
.operands
[2].reg
;
10115 reject_bad_reg (Rd
);
10116 reject_bad_reg (Rs
);
10117 if (inst
.operands
[2].isreg
)
10118 reject_bad_reg (Rn
);
10120 if (unified_syntax
)
10122 if (!inst
.operands
[2].isreg
)
10124 /* For an immediate, we always generate a 32-bit opcode;
10125 section relaxation will shrink it later if possible. */
10126 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10127 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10128 inst
.instruction
|= Rd
<< 8;
10129 inst
.instruction
|= Rs
<< 16;
10130 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10134 bfd_boolean narrow
;
10136 /* See if we can do this with a 16-bit instruction. */
10137 if (THUMB_SETS_FLAGS (inst
.instruction
))
10138 narrow
= !in_it_block ();
10140 narrow
= in_it_block ();
10142 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10144 if (inst
.operands
[2].shifted
)
10146 if (inst
.size_req
== 4)
10153 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10154 inst
.instruction
|= Rd
;
10155 inst
.instruction
|= Rn
<< 3;
10160 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10161 inst
.instruction
|= Rd
;
10162 inst
.instruction
|= Rs
<< 3;
10167 /* If we get here, it can't be done in 16 bits. */
10168 constraint (inst
.operands
[2].shifted
10169 && inst
.operands
[2].immisreg
,
10170 _("shift must be constant"));
10171 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10172 inst
.instruction
|= Rd
<< 8;
10173 inst
.instruction
|= Rs
<< 16;
10174 encode_thumb32_shifted_operand (2);
10179 /* On its face this is a lie - the instruction does set the
10180 flags. However, the only supported mnemonic in this mode
10181 says it doesn't. */
10182 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10184 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10185 _("unshifted register required"));
10186 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10188 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10189 inst
.instruction
|= Rd
;
10192 inst
.instruction
|= Rn
<< 3;
10194 inst
.instruction
|= Rs
<< 3;
10196 constraint (1, _("dest must overlap one source register"));
10204 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10205 constraint (msb
> 32, _("bit-field extends past end of register"));
10206 /* The instruction encoding stores the LSB and MSB,
10207 not the LSB and width. */
10208 Rd
= inst
.operands
[0].reg
;
10209 reject_bad_reg (Rd
);
10210 inst
.instruction
|= Rd
<< 8;
10211 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10212 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10213 inst
.instruction
|= msb
- 1;
10222 Rd
= inst
.operands
[0].reg
;
10223 reject_bad_reg (Rd
);
10225 /* #0 in second position is alternative syntax for bfc, which is
10226 the same instruction but with REG_PC in the Rm field. */
10227 if (!inst
.operands
[1].isreg
)
10231 Rn
= inst
.operands
[1].reg
;
10232 reject_bad_reg (Rn
);
10235 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10236 constraint (msb
> 32, _("bit-field extends past end of register"));
10237 /* The instruction encoding stores the LSB and MSB,
10238 not the LSB and width. */
10239 inst
.instruction
|= Rd
<< 8;
10240 inst
.instruction
|= Rn
<< 16;
10241 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10242 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10243 inst
.instruction
|= msb
- 1;
10251 Rd
= inst
.operands
[0].reg
;
10252 Rn
= inst
.operands
[1].reg
;
10254 reject_bad_reg (Rd
);
10255 reject_bad_reg (Rn
);
10257 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10258 _("bit-field extends past end of register"));
10259 inst
.instruction
|= Rd
<< 8;
10260 inst
.instruction
|= Rn
<< 16;
10261 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10262 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10263 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10266 /* ARM V5 Thumb BLX (argument parse)
10267 BLX <target_addr> which is BLX(1)
10268 BLX <Rm> which is BLX(2)
10269 Unfortunately, there are two different opcodes for this mnemonic.
10270 So, the insns[].value is not used, and the code here zaps values
10271 into inst.instruction.
10273 ??? How to take advantage of the additional two bits of displacement
10274 available in Thumb32 mode? Need new relocation? */
10279 set_it_insn_type_last ();
10281 if (inst
.operands
[0].isreg
)
10283 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10284 /* We have a register, so this is BLX(2). */
10285 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10289 /* No register. This must be BLX(1). */
10290 inst
.instruction
= 0xf000e800;
10291 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10303 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10305 if (in_it_block ())
10307 /* Conditional branches inside IT blocks are encoded as unconditional
10309 cond
= COND_ALWAYS
;
10314 if (cond
!= COND_ALWAYS
)
10315 opcode
= T_MNEM_bcond
;
10317 opcode
= inst
.instruction
;
10320 && (inst
.size_req
== 4
10321 || (inst
.size_req
!= 2
10322 && (inst
.operands
[0].hasreloc
10323 || inst
.reloc
.exp
.X_op
== O_constant
))))
10325 inst
.instruction
= THUMB_OP32(opcode
);
10326 if (cond
== COND_ALWAYS
)
10327 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10330 gas_assert (cond
!= 0xF);
10331 inst
.instruction
|= cond
<< 22;
10332 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10337 inst
.instruction
= THUMB_OP16(opcode
);
10338 if (cond
== COND_ALWAYS
)
10339 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10342 inst
.instruction
|= cond
<< 8;
10343 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10345 /* Allow section relaxation. */
10346 if (unified_syntax
&& inst
.size_req
!= 2)
10347 inst
.relax
= opcode
;
10349 inst
.reloc
.type
= reloc
;
10350 inst
.reloc
.pc_rel
= 1;
10353 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10354 between the two is the maximum immediate allowed - which is passed in
10357 do_t_bkpt_hlt1 (int range
)
10359 constraint (inst
.cond
!= COND_ALWAYS
,
10360 _("instruction is always unconditional"));
10361 if (inst
.operands
[0].present
)
10363 constraint (inst
.operands
[0].imm
> range
,
10364 _("immediate value out of range"));
10365 inst
.instruction
|= inst
.operands
[0].imm
;
10368 set_it_insn_type (NEUTRAL_IT_INSN
);
10374 do_t_bkpt_hlt1 (63);
10380 do_t_bkpt_hlt1 (255);
10384 do_t_branch23 (void)
10386 set_it_insn_type_last ();
10387 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10389 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10390 this file. We used to simply ignore the PLT reloc type here --
10391 the branch encoding is now needed to deal with TLSCALL relocs.
10392 So if we see a PLT reloc now, put it back to how it used to be to
10393 keep the preexisting behaviour. */
10394 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10395 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10397 #if defined(OBJ_COFF)
10398 /* If the destination of the branch is a defined symbol which does not have
10399 the THUMB_FUNC attribute, then we must be calling a function which has
10400 the (interfacearm) attribute. We look for the Thumb entry point to that
10401 function and change the branch to refer to that function instead. */
10402 if ( inst
.reloc
.exp
.X_op
== O_symbol
10403 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10404 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10405 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10406 inst
.reloc
.exp
.X_add_symbol
=
10407 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10414 set_it_insn_type_last ();
10415 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10416 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10417 should cause the alignment to be checked once it is known. This is
10418 because BX PC only works if the instruction is word aligned. */
10426 set_it_insn_type_last ();
10427 Rm
= inst
.operands
[0].reg
;
10428 reject_bad_reg (Rm
);
10429 inst
.instruction
|= Rm
<< 16;
10438 Rd
= inst
.operands
[0].reg
;
10439 Rm
= inst
.operands
[1].reg
;
10441 reject_bad_reg (Rd
);
10442 reject_bad_reg (Rm
);
10444 inst
.instruction
|= Rd
<< 8;
10445 inst
.instruction
|= Rm
<< 16;
10446 inst
.instruction
|= Rm
;
10452 set_it_insn_type (OUTSIDE_IT_INSN
);
10453 inst
.instruction
|= inst
.operands
[0].imm
;
10459 set_it_insn_type (OUTSIDE_IT_INSN
);
10461 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10462 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10464 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10465 inst
.instruction
= 0xf3af8000;
10466 inst
.instruction
|= imod
<< 9;
10467 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10468 if (inst
.operands
[1].present
)
10469 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10474 && (inst
.operands
[0].imm
& 4),
10475 _("selected processor does not support 'A' form "
10476 "of this instruction"));
10477 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10478 _("Thumb does not support the 2-argument "
10479 "form of this instruction"));
10480 inst
.instruction
|= inst
.operands
[0].imm
;
10484 /* THUMB CPY instruction (argument parse). */
10489 if (inst
.size_req
== 4)
10491 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10492 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10493 inst
.instruction
|= inst
.operands
[1].reg
;
10497 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10498 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10499 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10506 set_it_insn_type (OUTSIDE_IT_INSN
);
10507 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10508 inst
.instruction
|= inst
.operands
[0].reg
;
10509 inst
.reloc
.pc_rel
= 1;
10510 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10516 inst
.instruction
|= inst
.operands
[0].imm
;
10522 unsigned Rd
, Rn
, Rm
;
10524 Rd
= inst
.operands
[0].reg
;
10525 Rn
= (inst
.operands
[1].present
10526 ? inst
.operands
[1].reg
: Rd
);
10527 Rm
= inst
.operands
[2].reg
;
10529 reject_bad_reg (Rd
);
10530 reject_bad_reg (Rn
);
10531 reject_bad_reg (Rm
);
10533 inst
.instruction
|= Rd
<< 8;
10534 inst
.instruction
|= Rn
<< 16;
10535 inst
.instruction
|= Rm
;
10541 if (unified_syntax
&& inst
.size_req
== 4)
10542 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10544 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10550 unsigned int cond
= inst
.operands
[0].imm
;
10552 set_it_insn_type (IT_INSN
);
10553 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10555 now_it
.warn_deprecated
= FALSE
;
10557 /* If the condition is a negative condition, invert the mask. */
10558 if ((cond
& 0x1) == 0x0)
10560 unsigned int mask
= inst
.instruction
& 0x000f;
10562 if ((mask
& 0x7) == 0)
10564 /* No conversion needed. */
10565 now_it
.block_length
= 1;
10567 else if ((mask
& 0x3) == 0)
10570 now_it
.block_length
= 2;
10572 else if ((mask
& 0x1) == 0)
10575 now_it
.block_length
= 3;
10580 now_it
.block_length
= 4;
10583 inst
.instruction
&= 0xfff0;
10584 inst
.instruction
|= mask
;
10587 inst
.instruction
|= cond
<< 4;
10590 /* Helper function used for both push/pop and ldm/stm. */
10592 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10596 load
= (inst
.instruction
& (1 << 20)) != 0;
10598 if (mask
& (1 << 13))
10599 inst
.error
= _("SP not allowed in register list");
10601 if ((mask
& (1 << base
)) != 0
10603 inst
.error
= _("having the base register in the register list when "
10604 "using write back is UNPREDICTABLE");
10608 if (mask
& (1 << 15))
10610 if (mask
& (1 << 14))
10611 inst
.error
= _("LR and PC should not both be in register list");
10613 set_it_insn_type_last ();
10618 if (mask
& (1 << 15))
10619 inst
.error
= _("PC not allowed in register list");
10622 if ((mask
& (mask
- 1)) == 0)
10624 /* Single register transfers implemented as str/ldr. */
10627 if (inst
.instruction
& (1 << 23))
10628 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10630 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10634 if (inst
.instruction
& (1 << 23))
10635 inst
.instruction
= 0x00800000; /* ia -> [base] */
10637 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10640 inst
.instruction
|= 0xf8400000;
10642 inst
.instruction
|= 0x00100000;
10644 mask
= ffs (mask
) - 1;
10647 else if (writeback
)
10648 inst
.instruction
|= WRITE_BACK
;
10650 inst
.instruction
|= mask
;
10651 inst
.instruction
|= base
<< 16;
10657 /* This really doesn't seem worth it. */
10658 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10659 _("expression too complex"));
10660 constraint (inst
.operands
[1].writeback
,
10661 _("Thumb load/store multiple does not support {reglist}^"));
10663 if (unified_syntax
)
10665 bfd_boolean narrow
;
10669 /* See if we can use a 16-bit instruction. */
10670 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10671 && inst
.size_req
!= 4
10672 && !(inst
.operands
[1].imm
& ~0xff))
10674 mask
= 1 << inst
.operands
[0].reg
;
10676 if (inst
.operands
[0].reg
<= 7)
10678 if (inst
.instruction
== T_MNEM_stmia
10679 ? inst
.operands
[0].writeback
10680 : (inst
.operands
[0].writeback
10681 == !(inst
.operands
[1].imm
& mask
)))
10683 if (inst
.instruction
== T_MNEM_stmia
10684 && (inst
.operands
[1].imm
& mask
)
10685 && (inst
.operands
[1].imm
& (mask
- 1)))
10686 as_warn (_("value stored for r%d is UNKNOWN"),
10687 inst
.operands
[0].reg
);
10689 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10690 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10691 inst
.instruction
|= inst
.operands
[1].imm
;
10694 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10696 /* This means 1 register in reg list one of 3 situations:
10697 1. Instruction is stmia, but without writeback.
10698 2. lmdia without writeback, but with Rn not in
10700 3. ldmia with writeback, but with Rn in reglist.
10701 Case 3 is UNPREDICTABLE behaviour, so we handle
10702 case 1 and 2 which can be converted into a 16-bit
10703 str or ldr. The SP cases are handled below. */
10704 unsigned long opcode
;
10705 /* First, record an error for Case 3. */
10706 if (inst
.operands
[1].imm
& mask
10707 && inst
.operands
[0].writeback
)
10709 _("having the base register in the register list when "
10710 "using write back is UNPREDICTABLE");
10712 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10714 inst
.instruction
= THUMB_OP16 (opcode
);
10715 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10716 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10720 else if (inst
.operands
[0] .reg
== REG_SP
)
10722 if (inst
.operands
[0].writeback
)
10725 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10726 ? T_MNEM_push
: T_MNEM_pop
);
10727 inst
.instruction
|= inst
.operands
[1].imm
;
10730 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10733 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10734 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10735 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10743 if (inst
.instruction
< 0xffff)
10744 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10746 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10747 inst
.operands
[0].writeback
);
10752 constraint (inst
.operands
[0].reg
> 7
10753 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10754 constraint (inst
.instruction
!= T_MNEM_ldmia
10755 && inst
.instruction
!= T_MNEM_stmia
,
10756 _("Thumb-2 instruction only valid in unified syntax"));
10757 if (inst
.instruction
== T_MNEM_stmia
)
10759 if (!inst
.operands
[0].writeback
)
10760 as_warn (_("this instruction will write back the base register"));
10761 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10762 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10763 as_warn (_("value stored for r%d is UNKNOWN"),
10764 inst
.operands
[0].reg
);
10768 if (!inst
.operands
[0].writeback
10769 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10770 as_warn (_("this instruction will write back the base register"));
10771 else if (inst
.operands
[0].writeback
10772 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10773 as_warn (_("this instruction will not write back the base register"));
10776 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10777 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10778 inst
.instruction
|= inst
.operands
[1].imm
;
10785 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10786 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10787 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10788 || inst
.operands
[1].negative
,
10791 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10794 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10795 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10801 if (!inst
.operands
[1].present
)
10803 constraint (inst
.operands
[0].reg
== REG_LR
,
10804 _("r14 not allowed as first register "
10805 "when second register is omitted"));
10806 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10808 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10811 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10812 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10813 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10819 unsigned long opcode
;
10822 if (inst
.operands
[0].isreg
10823 && !inst
.operands
[0].preind
10824 && inst
.operands
[0].reg
== REG_PC
)
10825 set_it_insn_type_last ();
10827 opcode
= inst
.instruction
;
10828 if (unified_syntax
)
10830 if (!inst
.operands
[1].isreg
)
10832 if (opcode
<= 0xffff)
10833 inst
.instruction
= THUMB_OP32 (opcode
);
10834 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10837 if (inst
.operands
[1].isreg
10838 && !inst
.operands
[1].writeback
10839 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10840 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10841 && opcode
<= 0xffff
10842 && inst
.size_req
!= 4)
10844 /* Insn may have a 16-bit form. */
10845 Rn
= inst
.operands
[1].reg
;
10846 if (inst
.operands
[1].immisreg
)
10848 inst
.instruction
= THUMB_OP16 (opcode
);
10850 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10852 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10853 reject_bad_reg (inst
.operands
[1].imm
);
10855 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10856 && opcode
!= T_MNEM_ldrsb
)
10857 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10858 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10865 if (inst
.reloc
.pc_rel
)
10866 opcode
= T_MNEM_ldr_pc2
;
10868 opcode
= T_MNEM_ldr_pc
;
10872 if (opcode
== T_MNEM_ldr
)
10873 opcode
= T_MNEM_ldr_sp
;
10875 opcode
= T_MNEM_str_sp
;
10877 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10881 inst
.instruction
= inst
.operands
[0].reg
;
10882 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10884 inst
.instruction
|= THUMB_OP16 (opcode
);
10885 if (inst
.size_req
== 2)
10886 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10888 inst
.relax
= opcode
;
10892 /* Definitely a 32-bit variant. */
10894 /* Warning for Erratum 752419. */
10895 if (opcode
== T_MNEM_ldr
10896 && inst
.operands
[0].reg
== REG_SP
10897 && inst
.operands
[1].writeback
== 1
10898 && !inst
.operands
[1].immisreg
)
10900 if (no_cpu_selected ()
10901 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10902 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10903 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10904 as_warn (_("This instruction may be unpredictable "
10905 "if executed on M-profile cores "
10906 "with interrupts enabled."));
10909 /* Do some validations regarding addressing modes. */
10910 if (inst
.operands
[1].immisreg
)
10911 reject_bad_reg (inst
.operands
[1].imm
);
10913 constraint (inst
.operands
[1].writeback
== 1
10914 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10917 inst
.instruction
= THUMB_OP32 (opcode
);
10918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10919 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10920 check_ldr_r15_aligned ();
10924 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10926 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10928 /* Only [Rn,Rm] is acceptable. */
10929 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10930 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10931 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10932 || inst
.operands
[1].negative
,
10933 _("Thumb does not support this addressing mode"));
10934 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10938 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10939 if (!inst
.operands
[1].isreg
)
10940 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10943 constraint (!inst
.operands
[1].preind
10944 || inst
.operands
[1].shifted
10945 || inst
.operands
[1].writeback
,
10946 _("Thumb does not support this addressing mode"));
10947 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10949 constraint (inst
.instruction
& 0x0600,
10950 _("byte or halfword not valid for base register"));
10951 constraint (inst
.operands
[1].reg
== REG_PC
10952 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10953 _("r15 based store not allowed"));
10954 constraint (inst
.operands
[1].immisreg
,
10955 _("invalid base register for register offset"));
10957 if (inst
.operands
[1].reg
== REG_PC
)
10958 inst
.instruction
= T_OPCODE_LDR_PC
;
10959 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10960 inst
.instruction
= T_OPCODE_LDR_SP
;
10962 inst
.instruction
= T_OPCODE_STR_SP
;
10964 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10965 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10969 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10970 if (!inst
.operands
[1].immisreg
)
10972 /* Immediate offset. */
10973 inst
.instruction
|= inst
.operands
[0].reg
;
10974 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10975 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10979 /* Register offset. */
10980 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10981 constraint (inst
.operands
[1].negative
,
10982 _("Thumb does not support this addressing mode"));
10985 switch (inst
.instruction
)
10987 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10988 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10989 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10990 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10991 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10992 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10993 case 0x5600 /* ldrsb */:
10994 case 0x5e00 /* ldrsh */: break;
10998 inst
.instruction
|= inst
.operands
[0].reg
;
10999 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11000 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11006 if (!inst
.operands
[1].present
)
11008 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11009 constraint (inst
.operands
[0].reg
== REG_LR
,
11010 _("r14 not allowed here"));
11011 constraint (inst
.operands
[0].reg
== REG_R12
,
11012 _("r12 not allowed here"));
11015 if (inst
.operands
[2].writeback
11016 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11017 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11018 as_warn (_("base register written back, and overlaps "
11019 "one of transfer registers"));
11021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11022 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11023 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11030 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11036 unsigned Rd
, Rn
, Rm
, Ra
;
11038 Rd
= inst
.operands
[0].reg
;
11039 Rn
= inst
.operands
[1].reg
;
11040 Rm
= inst
.operands
[2].reg
;
11041 Ra
= inst
.operands
[3].reg
;
11043 reject_bad_reg (Rd
);
11044 reject_bad_reg (Rn
);
11045 reject_bad_reg (Rm
);
11046 reject_bad_reg (Ra
);
11048 inst
.instruction
|= Rd
<< 8;
11049 inst
.instruction
|= Rn
<< 16;
11050 inst
.instruction
|= Rm
;
11051 inst
.instruction
|= Ra
<< 12;
11057 unsigned RdLo
, RdHi
, Rn
, Rm
;
11059 RdLo
= inst
.operands
[0].reg
;
11060 RdHi
= inst
.operands
[1].reg
;
11061 Rn
= inst
.operands
[2].reg
;
11062 Rm
= inst
.operands
[3].reg
;
11064 reject_bad_reg (RdLo
);
11065 reject_bad_reg (RdHi
);
11066 reject_bad_reg (Rn
);
11067 reject_bad_reg (Rm
);
11069 inst
.instruction
|= RdLo
<< 12;
11070 inst
.instruction
|= RdHi
<< 8;
11071 inst
.instruction
|= Rn
<< 16;
11072 inst
.instruction
|= Rm
;
11076 do_t_mov_cmp (void)
11080 Rn
= inst
.operands
[0].reg
;
11081 Rm
= inst
.operands
[1].reg
;
11084 set_it_insn_type_last ();
11086 if (unified_syntax
)
11088 int r0off
= (inst
.instruction
== T_MNEM_mov
11089 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11090 unsigned long opcode
;
11091 bfd_boolean narrow
;
11092 bfd_boolean low_regs
;
11094 low_regs
= (Rn
<= 7 && Rm
<= 7);
11095 opcode
= inst
.instruction
;
11096 if (in_it_block ())
11097 narrow
= opcode
!= T_MNEM_movs
;
11099 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11100 if (inst
.size_req
== 4
11101 || inst
.operands
[1].shifted
)
11104 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11105 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11106 && !inst
.operands
[1].shifted
11110 inst
.instruction
= T2_SUBS_PC_LR
;
11114 if (opcode
== T_MNEM_cmp
)
11116 constraint (Rn
== REG_PC
, BAD_PC
);
11119 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11121 warn_deprecated_sp (Rm
);
11122 /* R15 was documented as a valid choice for Rm in ARMv6,
11123 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11124 tools reject R15, so we do too. */
11125 constraint (Rm
== REG_PC
, BAD_PC
);
11128 reject_bad_reg (Rm
);
11130 else if (opcode
== T_MNEM_mov
11131 || opcode
== T_MNEM_movs
)
11133 if (inst
.operands
[1].isreg
)
11135 if (opcode
== T_MNEM_movs
)
11137 reject_bad_reg (Rn
);
11138 reject_bad_reg (Rm
);
11142 /* This is mov.n. */
11143 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11144 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11146 as_warn (_("Use of r%u as a source register is "
11147 "deprecated when r%u is the destination "
11148 "register."), Rm
, Rn
);
11153 /* This is mov.w. */
11154 constraint (Rn
== REG_PC
, BAD_PC
);
11155 constraint (Rm
== REG_PC
, BAD_PC
);
11156 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11160 reject_bad_reg (Rn
);
11163 if (!inst
.operands
[1].isreg
)
11165 /* Immediate operand. */
11166 if (!in_it_block () && opcode
== T_MNEM_mov
)
11168 if (low_regs
&& narrow
)
11170 inst
.instruction
= THUMB_OP16 (opcode
);
11171 inst
.instruction
|= Rn
<< 8;
11172 if (inst
.size_req
== 2)
11173 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11175 inst
.relax
= opcode
;
11179 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11180 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11181 inst
.instruction
|= Rn
<< r0off
;
11182 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11185 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11186 && (inst
.instruction
== T_MNEM_mov
11187 || inst
.instruction
== T_MNEM_movs
))
11189 /* Register shifts are encoded as separate shift instructions. */
11190 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11192 if (in_it_block ())
11197 if (inst
.size_req
== 4)
11200 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11206 switch (inst
.operands
[1].shift_kind
)
11209 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11212 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11215 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11218 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11224 inst
.instruction
= opcode
;
11227 inst
.instruction
|= Rn
;
11228 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11233 inst
.instruction
|= CONDS_BIT
;
11235 inst
.instruction
|= Rn
<< 8;
11236 inst
.instruction
|= Rm
<< 16;
11237 inst
.instruction
|= inst
.operands
[1].imm
;
11242 /* Some mov with immediate shift have narrow variants.
11243 Register shifts are handled above. */
11244 if (low_regs
&& inst
.operands
[1].shifted
11245 && (inst
.instruction
== T_MNEM_mov
11246 || inst
.instruction
== T_MNEM_movs
))
11248 if (in_it_block ())
11249 narrow
= (inst
.instruction
== T_MNEM_mov
);
11251 narrow
= (inst
.instruction
== T_MNEM_movs
);
11256 switch (inst
.operands
[1].shift_kind
)
11258 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11259 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11260 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11261 default: narrow
= FALSE
; break;
11267 inst
.instruction
|= Rn
;
11268 inst
.instruction
|= Rm
<< 3;
11269 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11273 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11274 inst
.instruction
|= Rn
<< r0off
;
11275 encode_thumb32_shifted_operand (1);
11279 switch (inst
.instruction
)
11282 /* In v4t or v5t a move of two lowregs produces unpredictable
11283 results. Don't allow this. */
11286 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11287 "MOV Rd, Rs with two low registers is not "
11288 "permitted on this architecture");
11289 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11293 inst
.instruction
= T_OPCODE_MOV_HR
;
11294 inst
.instruction
|= (Rn
& 0x8) << 4;
11295 inst
.instruction
|= (Rn
& 0x7);
11296 inst
.instruction
|= Rm
<< 3;
11300 /* We know we have low registers at this point.
11301 Generate LSLS Rd, Rs, #0. */
11302 inst
.instruction
= T_OPCODE_LSL_I
;
11303 inst
.instruction
|= Rn
;
11304 inst
.instruction
|= Rm
<< 3;
11310 inst
.instruction
= T_OPCODE_CMP_LR
;
11311 inst
.instruction
|= Rn
;
11312 inst
.instruction
|= Rm
<< 3;
11316 inst
.instruction
= T_OPCODE_CMP_HR
;
11317 inst
.instruction
|= (Rn
& 0x8) << 4;
11318 inst
.instruction
|= (Rn
& 0x7);
11319 inst
.instruction
|= Rm
<< 3;
11326 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11328 /* PR 10443: Do not silently ignore shifted operands. */
11329 constraint (inst
.operands
[1].shifted
,
11330 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11332 if (inst
.operands
[1].isreg
)
11334 if (Rn
< 8 && Rm
< 8)
11336 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11337 since a MOV instruction produces unpredictable results. */
11338 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11339 inst
.instruction
= T_OPCODE_ADD_I3
;
11341 inst
.instruction
= T_OPCODE_CMP_LR
;
11343 inst
.instruction
|= Rn
;
11344 inst
.instruction
|= Rm
<< 3;
11348 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11349 inst
.instruction
= T_OPCODE_MOV_HR
;
11351 inst
.instruction
= T_OPCODE_CMP_HR
;
11357 constraint (Rn
> 7,
11358 _("only lo regs allowed with immediate"));
11359 inst
.instruction
|= Rn
<< 8;
11360 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11371 top
= (inst
.instruction
& 0x00800000) != 0;
11372 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11374 constraint (top
, _(":lower16: not allowed this instruction"));
11375 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11377 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11379 constraint (!top
, _(":upper16: not allowed this instruction"));
11380 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11383 Rd
= inst
.operands
[0].reg
;
11384 reject_bad_reg (Rd
);
11386 inst
.instruction
|= Rd
<< 8;
11387 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11389 imm
= inst
.reloc
.exp
.X_add_number
;
11390 inst
.instruction
|= (imm
& 0xf000) << 4;
11391 inst
.instruction
|= (imm
& 0x0800) << 15;
11392 inst
.instruction
|= (imm
& 0x0700) << 4;
11393 inst
.instruction
|= (imm
& 0x00ff);
11398 do_t_mvn_tst (void)
11402 Rn
= inst
.operands
[0].reg
;
11403 Rm
= inst
.operands
[1].reg
;
11405 if (inst
.instruction
== T_MNEM_cmp
11406 || inst
.instruction
== T_MNEM_cmn
)
11407 constraint (Rn
== REG_PC
, BAD_PC
);
11409 reject_bad_reg (Rn
);
11410 reject_bad_reg (Rm
);
11412 if (unified_syntax
)
11414 int r0off
= (inst
.instruction
== T_MNEM_mvn
11415 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11416 bfd_boolean narrow
;
11418 if (inst
.size_req
== 4
11419 || inst
.instruction
> 0xffff
11420 || inst
.operands
[1].shifted
11421 || Rn
> 7 || Rm
> 7)
11423 else if (inst
.instruction
== T_MNEM_cmn
11424 || inst
.instruction
== T_MNEM_tst
)
11426 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11427 narrow
= !in_it_block ();
11429 narrow
= in_it_block ();
11431 if (!inst
.operands
[1].isreg
)
11433 /* For an immediate, we always generate a 32-bit opcode;
11434 section relaxation will shrink it later if possible. */
11435 if (inst
.instruction
< 0xffff)
11436 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11437 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11438 inst
.instruction
|= Rn
<< r0off
;
11439 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11443 /* See if we can do this with a 16-bit instruction. */
11446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11447 inst
.instruction
|= Rn
;
11448 inst
.instruction
|= Rm
<< 3;
11452 constraint (inst
.operands
[1].shifted
11453 && inst
.operands
[1].immisreg
,
11454 _("shift must be constant"));
11455 if (inst
.instruction
< 0xffff)
11456 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11457 inst
.instruction
|= Rn
<< r0off
;
11458 encode_thumb32_shifted_operand (1);
11464 constraint (inst
.instruction
> 0xffff
11465 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11466 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11467 _("unshifted register required"));
11468 constraint (Rn
> 7 || Rm
> 7,
11471 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11472 inst
.instruction
|= Rn
;
11473 inst
.instruction
|= Rm
<< 3;
11482 if (do_vfp_nsyn_mrs () == SUCCESS
)
11485 Rd
= inst
.operands
[0].reg
;
11486 reject_bad_reg (Rd
);
11487 inst
.instruction
|= Rd
<< 8;
11489 if (inst
.operands
[1].isreg
)
11491 unsigned br
= inst
.operands
[1].reg
;
11492 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11493 as_bad (_("bad register for mrs"));
11495 inst
.instruction
|= br
& (0xf << 16);
11496 inst
.instruction
|= (br
& 0x300) >> 4;
11497 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11501 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11503 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11505 /* PR gas/12698: The constraint is only applied for m_profile.
11506 If the user has specified -march=all, we want to ignore it as
11507 we are building for any CPU type, including non-m variants. */
11508 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11509 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11510 "not support requested special purpose register"));
11513 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11515 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11516 _("'APSR', 'CPSR' or 'SPSR' expected"));
11518 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11519 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11520 inst
.instruction
|= 0xf0000;
11530 if (do_vfp_nsyn_msr () == SUCCESS
)
11533 constraint (!inst
.operands
[1].isreg
,
11534 _("Thumb encoding does not support an immediate here"));
11536 if (inst
.operands
[0].isreg
)
11537 flags
= (int)(inst
.operands
[0].reg
);
11539 flags
= inst
.operands
[0].imm
;
11541 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11543 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11545 /* PR gas/12698: The constraint is only applied for m_profile.
11546 If the user has specified -march=all, we want to ignore it as
11547 we are building for any CPU type, including non-m variants. */
11548 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11549 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11550 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11551 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11552 && bits
!= PSR_f
)) && m_profile
,
11553 _("selected processor does not support requested special "
11554 "purpose register"));
11557 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11558 "requested special purpose register"));
11560 Rn
= inst
.operands
[1].reg
;
11561 reject_bad_reg (Rn
);
11563 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11564 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11565 inst
.instruction
|= (flags
& 0x300) >> 4;
11566 inst
.instruction
|= (flags
& 0xff);
11567 inst
.instruction
|= Rn
<< 16;
11573 bfd_boolean narrow
;
11574 unsigned Rd
, Rn
, Rm
;
11576 if (!inst
.operands
[2].present
)
11577 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11579 Rd
= inst
.operands
[0].reg
;
11580 Rn
= inst
.operands
[1].reg
;
11581 Rm
= inst
.operands
[2].reg
;
11583 if (unified_syntax
)
11585 if (inst
.size_req
== 4
11591 else if (inst
.instruction
== T_MNEM_muls
)
11592 narrow
= !in_it_block ();
11594 narrow
= in_it_block ();
11598 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11599 constraint (Rn
> 7 || Rm
> 7,
11606 /* 16-bit MULS/Conditional MUL. */
11607 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11608 inst
.instruction
|= Rd
;
11611 inst
.instruction
|= Rm
<< 3;
11613 inst
.instruction
|= Rn
<< 3;
11615 constraint (1, _("dest must overlap one source register"));
11619 constraint (inst
.instruction
!= T_MNEM_mul
,
11620 _("Thumb-2 MUL must not set flags"));
11622 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11623 inst
.instruction
|= Rd
<< 8;
11624 inst
.instruction
|= Rn
<< 16;
11625 inst
.instruction
|= Rm
<< 0;
11627 reject_bad_reg (Rd
);
11628 reject_bad_reg (Rn
);
11629 reject_bad_reg (Rm
);
11636 unsigned RdLo
, RdHi
, Rn
, Rm
;
11638 RdLo
= inst
.operands
[0].reg
;
11639 RdHi
= inst
.operands
[1].reg
;
11640 Rn
= inst
.operands
[2].reg
;
11641 Rm
= inst
.operands
[3].reg
;
11643 reject_bad_reg (RdLo
);
11644 reject_bad_reg (RdHi
);
11645 reject_bad_reg (Rn
);
11646 reject_bad_reg (Rm
);
11648 inst
.instruction
|= RdLo
<< 12;
11649 inst
.instruction
|= RdHi
<< 8;
11650 inst
.instruction
|= Rn
<< 16;
11651 inst
.instruction
|= Rm
;
11654 as_tsktsk (_("rdhi and rdlo must be different"));
11660 set_it_insn_type (NEUTRAL_IT_INSN
);
11662 if (unified_syntax
)
11664 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11666 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11667 inst
.instruction
|= inst
.operands
[0].imm
;
11671 /* PR9722: Check for Thumb2 availability before
11672 generating a thumb2 nop instruction. */
11673 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11675 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11676 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11679 inst
.instruction
= 0x46c0;
11684 constraint (inst
.operands
[0].present
,
11685 _("Thumb does not support NOP with hints"));
11686 inst
.instruction
= 0x46c0;
11693 if (unified_syntax
)
11695 bfd_boolean narrow
;
11697 if (THUMB_SETS_FLAGS (inst
.instruction
))
11698 narrow
= !in_it_block ();
11700 narrow
= in_it_block ();
11701 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11703 if (inst
.size_req
== 4)
11708 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11709 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11710 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11714 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11715 inst
.instruction
|= inst
.operands
[0].reg
;
11716 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11721 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11723 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11725 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11726 inst
.instruction
|= inst
.operands
[0].reg
;
11727 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11736 Rd
= inst
.operands
[0].reg
;
11737 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11739 reject_bad_reg (Rd
);
11740 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11741 reject_bad_reg (Rn
);
11743 inst
.instruction
|= Rd
<< 8;
11744 inst
.instruction
|= Rn
<< 16;
11746 if (!inst
.operands
[2].isreg
)
11748 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11749 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11755 Rm
= inst
.operands
[2].reg
;
11756 reject_bad_reg (Rm
);
11758 constraint (inst
.operands
[2].shifted
11759 && inst
.operands
[2].immisreg
,
11760 _("shift must be constant"));
11761 encode_thumb32_shifted_operand (2);
11768 unsigned Rd
, Rn
, Rm
;
11770 Rd
= inst
.operands
[0].reg
;
11771 Rn
= inst
.operands
[1].reg
;
11772 Rm
= inst
.operands
[2].reg
;
11774 reject_bad_reg (Rd
);
11775 reject_bad_reg (Rn
);
11776 reject_bad_reg (Rm
);
11778 inst
.instruction
|= Rd
<< 8;
11779 inst
.instruction
|= Rn
<< 16;
11780 inst
.instruction
|= Rm
;
11781 if (inst
.operands
[3].present
)
11783 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11784 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11785 _("expression too complex"));
11786 inst
.instruction
|= (val
& 0x1c) << 10;
11787 inst
.instruction
|= (val
& 0x03) << 6;
11794 if (!inst
.operands
[3].present
)
11798 inst
.instruction
&= ~0x00000020;
11800 /* PR 10168. Swap the Rm and Rn registers. */
11801 Rtmp
= inst
.operands
[1].reg
;
11802 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11803 inst
.operands
[2].reg
= Rtmp
;
11811 if (inst
.operands
[0].immisreg
)
11812 reject_bad_reg (inst
.operands
[0].imm
);
11814 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11818 do_t_push_pop (void)
11822 constraint (inst
.operands
[0].writeback
,
11823 _("push/pop do not support {reglist}^"));
11824 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11825 _("expression too complex"));
11827 mask
= inst
.operands
[0].imm
;
11828 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
11829 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11830 else if (inst
.size_req
!= 4
11831 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
11832 ? REG_LR
: REG_PC
)))
11834 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11835 inst
.instruction
|= THUMB_PP_PC_LR
;
11836 inst
.instruction
|= mask
& 0xff;
11838 else if (unified_syntax
)
11840 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11841 encode_thumb2_ldmstm (13, mask
, TRUE
);
11845 inst
.error
= _("invalid register list to push/pop instruction");
11855 Rd
= inst
.operands
[0].reg
;
11856 Rm
= inst
.operands
[1].reg
;
11858 reject_bad_reg (Rd
);
11859 reject_bad_reg (Rm
);
11861 inst
.instruction
|= Rd
<< 8;
11862 inst
.instruction
|= Rm
<< 16;
11863 inst
.instruction
|= Rm
;
11871 Rd
= inst
.operands
[0].reg
;
11872 Rm
= inst
.operands
[1].reg
;
11874 reject_bad_reg (Rd
);
11875 reject_bad_reg (Rm
);
11877 if (Rd
<= 7 && Rm
<= 7
11878 && inst
.size_req
!= 4)
11880 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11881 inst
.instruction
|= Rd
;
11882 inst
.instruction
|= Rm
<< 3;
11884 else if (unified_syntax
)
11886 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11887 inst
.instruction
|= Rd
<< 8;
11888 inst
.instruction
|= Rm
<< 16;
11889 inst
.instruction
|= Rm
;
11892 inst
.error
= BAD_HIREG
;
11900 Rd
= inst
.operands
[0].reg
;
11901 Rm
= inst
.operands
[1].reg
;
11903 reject_bad_reg (Rd
);
11904 reject_bad_reg (Rm
);
11906 inst
.instruction
|= Rd
<< 8;
11907 inst
.instruction
|= Rm
;
11915 Rd
= inst
.operands
[0].reg
;
11916 Rs
= (inst
.operands
[1].present
11917 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11918 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11920 reject_bad_reg (Rd
);
11921 reject_bad_reg (Rs
);
11922 if (inst
.operands
[2].isreg
)
11923 reject_bad_reg (inst
.operands
[2].reg
);
11925 inst
.instruction
|= Rd
<< 8;
11926 inst
.instruction
|= Rs
<< 16;
11927 if (!inst
.operands
[2].isreg
)
11929 bfd_boolean narrow
;
11931 if ((inst
.instruction
& 0x00100000) != 0)
11932 narrow
= !in_it_block ();
11934 narrow
= in_it_block ();
11936 if (Rd
> 7 || Rs
> 7)
11939 if (inst
.size_req
== 4 || !unified_syntax
)
11942 if (inst
.reloc
.exp
.X_op
!= O_constant
11943 || inst
.reloc
.exp
.X_add_number
!= 0)
11946 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11947 relaxation, but it doesn't seem worth the hassle. */
11950 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11951 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11952 inst
.instruction
|= Rs
<< 3;
11953 inst
.instruction
|= Rd
;
11957 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11958 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11962 encode_thumb32_shifted_operand (2);
11968 if (warn_on_deprecated
11969 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11970 as_warn (_("setend use is deprecated for ARMv8"));
11972 set_it_insn_type (OUTSIDE_IT_INSN
);
11973 if (inst
.operands
[0].imm
)
11974 inst
.instruction
|= 0x8;
11980 if (!inst
.operands
[1].present
)
11981 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11983 if (unified_syntax
)
11985 bfd_boolean narrow
;
11988 switch (inst
.instruction
)
11991 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11993 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11995 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11997 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12001 if (THUMB_SETS_FLAGS (inst
.instruction
))
12002 narrow
= !in_it_block ();
12004 narrow
= in_it_block ();
12005 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12007 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12009 if (inst
.operands
[2].isreg
12010 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12011 || inst
.operands
[2].reg
> 7))
12013 if (inst
.size_req
== 4)
12016 reject_bad_reg (inst
.operands
[0].reg
);
12017 reject_bad_reg (inst
.operands
[1].reg
);
12021 if (inst
.operands
[2].isreg
)
12023 reject_bad_reg (inst
.operands
[2].reg
);
12024 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12025 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12026 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12027 inst
.instruction
|= inst
.operands
[2].reg
;
12029 /* PR 12854: Error on extraneous shifts. */
12030 constraint (inst
.operands
[2].shifted
,
12031 _("extraneous shift as part of operand to shift insn"));
12035 inst
.operands
[1].shifted
= 1;
12036 inst
.operands
[1].shift_kind
= shift_kind
;
12037 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12038 ? T_MNEM_movs
: T_MNEM_mov
);
12039 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12040 encode_thumb32_shifted_operand (1);
12041 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12042 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12047 if (inst
.operands
[2].isreg
)
12049 switch (shift_kind
)
12051 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12052 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12053 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12054 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12058 inst
.instruction
|= inst
.operands
[0].reg
;
12059 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12061 /* PR 12854: Error on extraneous shifts. */
12062 constraint (inst
.operands
[2].shifted
,
12063 _("extraneous shift as part of operand to shift insn"));
12067 switch (shift_kind
)
12069 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12070 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12071 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12074 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12075 inst
.instruction
|= inst
.operands
[0].reg
;
12076 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12082 constraint (inst
.operands
[0].reg
> 7
12083 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12084 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12086 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12088 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12089 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12090 _("source1 and dest must be same register"));
12092 switch (inst
.instruction
)
12094 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12095 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12096 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12097 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12101 inst
.instruction
|= inst
.operands
[0].reg
;
12102 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12104 /* PR 12854: Error on extraneous shifts. */
12105 constraint (inst
.operands
[2].shifted
,
12106 _("extraneous shift as part of operand to shift insn"));
12110 switch (inst
.instruction
)
12112 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12113 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12114 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12115 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12118 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12119 inst
.instruction
|= inst
.operands
[0].reg
;
12120 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12128 unsigned Rd
, Rn
, Rm
;
12130 Rd
= inst
.operands
[0].reg
;
12131 Rn
= inst
.operands
[1].reg
;
12132 Rm
= inst
.operands
[2].reg
;
12134 reject_bad_reg (Rd
);
12135 reject_bad_reg (Rn
);
12136 reject_bad_reg (Rm
);
12138 inst
.instruction
|= Rd
<< 8;
12139 inst
.instruction
|= Rn
<< 16;
12140 inst
.instruction
|= Rm
;
12146 unsigned Rd
, Rn
, Rm
;
12148 Rd
= inst
.operands
[0].reg
;
12149 Rm
= inst
.operands
[1].reg
;
12150 Rn
= inst
.operands
[2].reg
;
12152 reject_bad_reg (Rd
);
12153 reject_bad_reg (Rn
);
12154 reject_bad_reg (Rm
);
12156 inst
.instruction
|= Rd
<< 8;
12157 inst
.instruction
|= Rn
<< 16;
12158 inst
.instruction
|= Rm
;
12164 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12165 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12166 _("SMC is not permitted on this architecture"));
12167 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12168 _("expression too complex"));
12169 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12170 inst
.instruction
|= (value
& 0xf000) >> 12;
12171 inst
.instruction
|= (value
& 0x0ff0);
12172 inst
.instruction
|= (value
& 0x000f) << 16;
12173 /* PR gas/15623: SMC instructions must be last in an IT block. */
12174 set_it_insn_type_last ();
12180 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12182 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12183 inst
.instruction
|= (value
& 0x0fff);
12184 inst
.instruction
|= (value
& 0xf000) << 4;
12188 do_t_ssat_usat (int bias
)
12192 Rd
= inst
.operands
[0].reg
;
12193 Rn
= inst
.operands
[2].reg
;
12195 reject_bad_reg (Rd
);
12196 reject_bad_reg (Rn
);
12198 inst
.instruction
|= Rd
<< 8;
12199 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12200 inst
.instruction
|= Rn
<< 16;
12202 if (inst
.operands
[3].present
)
12204 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12206 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12208 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12209 _("expression too complex"));
12211 if (shift_amount
!= 0)
12213 constraint (shift_amount
> 31,
12214 _("shift expression is too large"));
12216 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12217 inst
.instruction
|= 0x00200000; /* sh bit. */
12219 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12220 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12228 do_t_ssat_usat (1);
12236 Rd
= inst
.operands
[0].reg
;
12237 Rn
= inst
.operands
[2].reg
;
12239 reject_bad_reg (Rd
);
12240 reject_bad_reg (Rn
);
12242 inst
.instruction
|= Rd
<< 8;
12243 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12244 inst
.instruction
|= Rn
<< 16;
12250 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12251 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12252 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12253 || inst
.operands
[2].negative
,
12256 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12258 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12259 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12260 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12261 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12267 if (!inst
.operands
[2].present
)
12268 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12270 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12271 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12272 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12275 inst
.instruction
|= inst
.operands
[0].reg
;
12276 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12277 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12278 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12284 unsigned Rd
, Rn
, Rm
;
12286 Rd
= inst
.operands
[0].reg
;
12287 Rn
= inst
.operands
[1].reg
;
12288 Rm
= inst
.operands
[2].reg
;
12290 reject_bad_reg (Rd
);
12291 reject_bad_reg (Rn
);
12292 reject_bad_reg (Rm
);
12294 inst
.instruction
|= Rd
<< 8;
12295 inst
.instruction
|= Rn
<< 16;
12296 inst
.instruction
|= Rm
;
12297 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12305 Rd
= inst
.operands
[0].reg
;
12306 Rm
= inst
.operands
[1].reg
;
12308 reject_bad_reg (Rd
);
12309 reject_bad_reg (Rm
);
12311 if (inst
.instruction
<= 0xffff
12312 && inst
.size_req
!= 4
12313 && Rd
<= 7 && Rm
<= 7
12314 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12316 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12317 inst
.instruction
|= Rd
;
12318 inst
.instruction
|= Rm
<< 3;
12320 else if (unified_syntax
)
12322 if (inst
.instruction
<= 0xffff)
12323 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12324 inst
.instruction
|= Rd
<< 8;
12325 inst
.instruction
|= Rm
;
12326 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12330 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12331 _("Thumb encoding does not support rotation"));
12332 constraint (1, BAD_HIREG
);
12339 /* We have to do the following check manually as ARM_EXT_OS only applies
12341 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12343 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12344 /* This only applies to the v6m howver, not later architectures. */
12345 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12346 as_bad (_("SVC is not permitted on this architecture"));
12347 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12350 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12359 half
= (inst
.instruction
& 0x10) != 0;
12360 set_it_insn_type_last ();
12361 constraint (inst
.operands
[0].immisreg
,
12362 _("instruction requires register index"));
12364 Rn
= inst
.operands
[0].reg
;
12365 Rm
= inst
.operands
[0].imm
;
12367 constraint (Rn
== REG_SP
, BAD_SP
);
12368 reject_bad_reg (Rm
);
12370 constraint (!half
&& inst
.operands
[0].shifted
,
12371 _("instruction does not allow shifted index"));
12372 inst
.instruction
|= (Rn
<< 16) | Rm
;
12378 if (!inst
.operands
[0].present
)
12379 inst
.operands
[0].imm
= 0;
12381 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12383 constraint (inst
.size_req
== 2,
12384 _("immediate value out of range"));
12385 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12386 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12387 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12391 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12392 inst
.instruction
|= inst
.operands
[0].imm
;
12395 set_it_insn_type (NEUTRAL_IT_INSN
);
12402 do_t_ssat_usat (0);
12410 Rd
= inst
.operands
[0].reg
;
12411 Rn
= inst
.operands
[2].reg
;
12413 reject_bad_reg (Rd
);
12414 reject_bad_reg (Rn
);
12416 inst
.instruction
|= Rd
<< 8;
12417 inst
.instruction
|= inst
.operands
[1].imm
;
12418 inst
.instruction
|= Rn
<< 16;
12421 /* Neon instruction encoder helpers. */
12423 /* Encodings for the different types for various Neon opcodes. */
12425 /* An "invalid" code for the following tables. */
12428 struct neon_tab_entry
12431 unsigned float_or_poly
;
12432 unsigned scalar_or_imm
;
12435 /* Map overloaded Neon opcodes to their respective encodings. */
12436 #define NEON_ENC_TAB \
12437 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12438 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12439 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12440 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12441 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12442 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12443 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12444 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12445 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12446 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12447 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12448 /* Register variants of the following two instructions are encoded as
12449 vcge / vcgt with the operands reversed. */ \
12450 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12451 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12452 X(vfma, N_INV, 0x0000c10, N_INV), \
12453 X(vfms, N_INV, 0x0200c10, N_INV), \
12454 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12455 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12456 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12457 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12458 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12459 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12460 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12461 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12462 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12463 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12464 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12465 X(vshl, 0x0000400, N_INV, 0x0800510), \
12466 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12467 X(vand, 0x0000110, N_INV, 0x0800030), \
12468 X(vbic, 0x0100110, N_INV, 0x0800030), \
12469 X(veor, 0x1000110, N_INV, N_INV), \
12470 X(vorn, 0x0300110, N_INV, 0x0800010), \
12471 X(vorr, 0x0200110, N_INV, 0x0800010), \
12472 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12473 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12474 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12475 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12476 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12477 X(vst1, 0x0000000, 0x0800000, N_INV), \
12478 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12479 X(vst2, 0x0000100, 0x0800100, N_INV), \
12480 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12481 X(vst3, 0x0000200, 0x0800200, N_INV), \
12482 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12483 X(vst4, 0x0000300, 0x0800300, N_INV), \
12484 X(vmovn, 0x1b20200, N_INV, N_INV), \
12485 X(vtrn, 0x1b20080, N_INV, N_INV), \
12486 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12487 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12488 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12489 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12490 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12491 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12492 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12493 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12494 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12495 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12496 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12497 X(vseleq, 0xe000a00, N_INV, N_INV), \
12498 X(vselvs, 0xe100a00, N_INV, N_INV), \
12499 X(vselge, 0xe200a00, N_INV, N_INV), \
12500 X(vselgt, 0xe300a00, N_INV, N_INV), \
12501 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12502 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12503 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12504 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12505 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12506 X(aes, 0x3b00300, N_INV, N_INV), \
12507 X(sha3op, 0x2000c00, N_INV, N_INV), \
12508 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12509 X(sha2op, 0x3ba0380, N_INV, N_INV)
12513 #define X(OPC,I,F,S) N_MNEM_##OPC
12518 static const struct neon_tab_entry neon_enc_tab
[] =
12520 #define X(OPC,I,F,S) { (I), (F), (S) }
12525 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12526 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12527 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12528 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12529 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12530 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12531 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12532 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12533 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12534 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12535 #define NEON_ENC_SINGLE_(X) \
12536 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12537 #define NEON_ENC_DOUBLE_(X) \
12538 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12539 #define NEON_ENC_FPV8_(X) \
12540 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12542 #define NEON_ENCODE(type, inst) \
12545 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12546 inst.is_neon = 1; \
12550 #define check_neon_suffixes \
12553 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12555 as_bad (_("invalid neon suffix for non neon instruction")); \
12561 /* Define shapes for instruction operands. The following mnemonic characters
12562 are used in this table:
12564 F - VFP S<n> register
12565 D - Neon D<n> register
12566 Q - Neon Q<n> register
12570 L - D<n> register list
12572 This table is used to generate various data:
12573 - enumerations of the form NS_DDR to be used as arguments to
12575 - a table classifying shapes into single, double, quad, mixed.
12576 - a table used to drive neon_select_shape. */
12578 #define NEON_SHAPE_DEF \
12579 X(3, (D, D, D), DOUBLE), \
12580 X(3, (Q, Q, Q), QUAD), \
12581 X(3, (D, D, I), DOUBLE), \
12582 X(3, (Q, Q, I), QUAD), \
12583 X(3, (D, D, S), DOUBLE), \
12584 X(3, (Q, Q, S), QUAD), \
12585 X(2, (D, D), DOUBLE), \
12586 X(2, (Q, Q), QUAD), \
12587 X(2, (D, S), DOUBLE), \
12588 X(2, (Q, S), QUAD), \
12589 X(2, (D, R), DOUBLE), \
12590 X(2, (Q, R), QUAD), \
12591 X(2, (D, I), DOUBLE), \
12592 X(2, (Q, I), QUAD), \
12593 X(3, (D, L, D), DOUBLE), \
12594 X(2, (D, Q), MIXED), \
12595 X(2, (Q, D), MIXED), \
12596 X(3, (D, Q, I), MIXED), \
12597 X(3, (Q, D, I), MIXED), \
12598 X(3, (Q, D, D), MIXED), \
12599 X(3, (D, Q, Q), MIXED), \
12600 X(3, (Q, Q, D), MIXED), \
12601 X(3, (Q, D, S), MIXED), \
12602 X(3, (D, Q, S), MIXED), \
12603 X(4, (D, D, D, I), DOUBLE), \
12604 X(4, (Q, Q, Q, I), QUAD), \
12605 X(2, (F, F), SINGLE), \
12606 X(3, (F, F, F), SINGLE), \
12607 X(2, (F, I), SINGLE), \
12608 X(2, (F, D), MIXED), \
12609 X(2, (D, F), MIXED), \
12610 X(3, (F, F, I), MIXED), \
12611 X(4, (R, R, F, F), SINGLE), \
12612 X(4, (F, F, R, R), SINGLE), \
12613 X(3, (D, R, R), DOUBLE), \
12614 X(3, (R, R, D), DOUBLE), \
12615 X(2, (S, R), SINGLE), \
12616 X(2, (R, S), SINGLE), \
12617 X(2, (F, R), SINGLE), \
12618 X(2, (R, F), SINGLE)
12620 #define S2(A,B) NS_##A##B
12621 #define S3(A,B,C) NS_##A##B##C
12622 #define S4(A,B,C,D) NS_##A##B##C##D
12624 #define X(N, L, C) S##N L
12637 enum neon_shape_class
12645 #define X(N, L, C) SC_##C
12647 static enum neon_shape_class neon_shape_class
[] =
12665 /* Register widths of above. */
12666 static unsigned neon_shape_el_size
[] =
12677 struct neon_shape_info
12680 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12683 #define S2(A,B) { SE_##A, SE_##B }
12684 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12685 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12687 #define X(N, L, C) { N, S##N L }
12689 static struct neon_shape_info neon_shape_tab
[] =
12699 /* Bit masks used in type checking given instructions.
12700 'N_EQK' means the type must be the same as (or based on in some way) the key
12701 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12702 set, various other bits can be set as well in order to modify the meaning of
12703 the type constraint. */
12705 enum neon_type_mask
12729 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12730 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12731 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12732 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
12733 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12734 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12735 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12736 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12737 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12738 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12739 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12741 N_MAX_NONSPECIAL
= N_P64
12744 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12746 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12747 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12748 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12749 #define N_SUF_32 (N_SU_32 | N_F32)
12750 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12751 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12753 /* Pass this as the first type argument to neon_check_type to ignore types
12755 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12757 /* Select a "shape" for the current instruction (describing register types or
12758 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12759 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12760 function of operand parsing, so this function doesn't need to be called.
12761 Shapes should be listed in order of decreasing length. */
12763 static enum neon_shape
12764 neon_select_shape (enum neon_shape shape
, ...)
12767 enum neon_shape first_shape
= shape
;
12769 /* Fix missing optional operands. FIXME: we don't know at this point how
12770 many arguments we should have, so this makes the assumption that we have
12771 > 1. This is true of all current Neon opcodes, I think, but may not be
12772 true in the future. */
12773 if (!inst
.operands
[1].present
)
12774 inst
.operands
[1] = inst
.operands
[0];
12776 va_start (ap
, shape
);
12778 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12783 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12785 if (!inst
.operands
[j
].present
)
12791 switch (neon_shape_tab
[shape
].el
[j
])
12794 if (!(inst
.operands
[j
].isreg
12795 && inst
.operands
[j
].isvec
12796 && inst
.operands
[j
].issingle
12797 && !inst
.operands
[j
].isquad
))
12802 if (!(inst
.operands
[j
].isreg
12803 && inst
.operands
[j
].isvec
12804 && !inst
.operands
[j
].isquad
12805 && !inst
.operands
[j
].issingle
))
12810 if (!(inst
.operands
[j
].isreg
12811 && !inst
.operands
[j
].isvec
))
12816 if (!(inst
.operands
[j
].isreg
12817 && inst
.operands
[j
].isvec
12818 && inst
.operands
[j
].isquad
12819 && !inst
.operands
[j
].issingle
))
12824 if (!(!inst
.operands
[j
].isreg
12825 && !inst
.operands
[j
].isscalar
))
12830 if (!(!inst
.operands
[j
].isreg
12831 && inst
.operands
[j
].isscalar
))
12841 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
12842 /* We've matched all the entries in the shape table, and we don't
12843 have any left over operands which have not been matched. */
12849 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12850 first_error (_("invalid instruction shape"));
12855 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12856 means the Q bit should be set). */
12859 neon_quad (enum neon_shape shape
)
12861 return neon_shape_class
[shape
] == SC_QUAD
;
12865 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12868 /* Allow modification to be made to types which are constrained to be
12869 based on the key element, based on bits set alongside N_EQK. */
12870 if ((typebits
& N_EQK
) != 0)
12872 if ((typebits
& N_HLF
) != 0)
12874 else if ((typebits
& N_DBL
) != 0)
12876 if ((typebits
& N_SGN
) != 0)
12877 *g_type
= NT_signed
;
12878 else if ((typebits
& N_UNS
) != 0)
12879 *g_type
= NT_unsigned
;
12880 else if ((typebits
& N_INT
) != 0)
12881 *g_type
= NT_integer
;
12882 else if ((typebits
& N_FLT
) != 0)
12883 *g_type
= NT_float
;
12884 else if ((typebits
& N_SIZ
) != 0)
12885 *g_type
= NT_untyped
;
12889 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12890 operand type, i.e. the single type specified in a Neon instruction when it
12891 is the only one given. */
12893 static struct neon_type_el
12894 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12896 struct neon_type_el dest
= *key
;
12898 gas_assert ((thisarg
& N_EQK
) != 0);
12900 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12905 /* Convert Neon type and size into compact bitmask representation. */
12907 static enum neon_type_mask
12908 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12915 case 8: return N_8
;
12916 case 16: return N_16
;
12917 case 32: return N_32
;
12918 case 64: return N_64
;
12926 case 8: return N_I8
;
12927 case 16: return N_I16
;
12928 case 32: return N_I32
;
12929 case 64: return N_I64
;
12937 case 16: return N_F16
;
12938 case 32: return N_F32
;
12939 case 64: return N_F64
;
12947 case 8: return N_P8
;
12948 case 16: return N_P16
;
12949 case 64: return N_P64
;
12957 case 8: return N_S8
;
12958 case 16: return N_S16
;
12959 case 32: return N_S32
;
12960 case 64: return N_S64
;
12968 case 8: return N_U8
;
12969 case 16: return N_U16
;
12970 case 32: return N_U32
;
12971 case 64: return N_U64
;
12982 /* Convert compact Neon bitmask type representation to a type and size. Only
12983 handles the case where a single bit is set in the mask. */
12986 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12987 enum neon_type_mask mask
)
12989 if ((mask
& N_EQK
) != 0)
12992 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12994 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
12996 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12998 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13003 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13005 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13006 *type
= NT_unsigned
;
13007 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13008 *type
= NT_integer
;
13009 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13010 *type
= NT_untyped
;
13011 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13013 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13021 /* Modify a bitmask of allowed types. This is only needed for type
13025 modify_types_allowed (unsigned allowed
, unsigned mods
)
13028 enum neon_el_type type
;
13034 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13036 if (el_type_of_type_chk (&type
, &size
,
13037 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13039 neon_modify_type_size (mods
, &type
, &size
);
13040 destmask
|= type_chk_of_el_type (type
, size
);
13047 /* Check type and return type classification.
13048 The manual states (paraphrase): If one datatype is given, it indicates the
13050 - the second operand, if there is one
13051 - the operand, if there is no second operand
13052 - the result, if there are no operands.
13053 This isn't quite good enough though, so we use a concept of a "key" datatype
13054 which is set on a per-instruction basis, which is the one which matters when
13055 only one data type is written.
13056 Note: this function has side-effects (e.g. filling in missing operands). All
13057 Neon instructions should call it before performing bit encoding. */
13059 static struct neon_type_el
13060 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13063 unsigned i
, pass
, key_el
= 0;
13064 unsigned types
[NEON_MAX_TYPE_ELS
];
13065 enum neon_el_type k_type
= NT_invtype
;
13066 unsigned k_size
= -1u;
13067 struct neon_type_el badtype
= {NT_invtype
, -1};
13068 unsigned key_allowed
= 0;
13070 /* Optional registers in Neon instructions are always (not) in operand 1.
13071 Fill in the missing operand here, if it was omitted. */
13072 if (els
> 1 && !inst
.operands
[1].present
)
13073 inst
.operands
[1] = inst
.operands
[0];
13075 /* Suck up all the varargs. */
13077 for (i
= 0; i
< els
; i
++)
13079 unsigned thisarg
= va_arg (ap
, unsigned);
13080 if (thisarg
== N_IGNORE_TYPE
)
13085 types
[i
] = thisarg
;
13086 if ((thisarg
& N_KEY
) != 0)
13091 if (inst
.vectype
.elems
> 0)
13092 for (i
= 0; i
< els
; i
++)
13093 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13095 first_error (_("types specified in both the mnemonic and operands"));
13099 /* Duplicate inst.vectype elements here as necessary.
13100 FIXME: No idea if this is exactly the same as the ARM assembler,
13101 particularly when an insn takes one register and one non-register
13103 if (inst
.vectype
.elems
== 1 && els
> 1)
13106 inst
.vectype
.elems
= els
;
13107 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13108 for (j
= 0; j
< els
; j
++)
13110 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13113 else if (inst
.vectype
.elems
== 0 && els
> 0)
13116 /* No types were given after the mnemonic, so look for types specified
13117 after each operand. We allow some flexibility here; as long as the
13118 "key" operand has a type, we can infer the others. */
13119 for (j
= 0; j
< els
; j
++)
13120 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13121 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13123 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13125 for (j
= 0; j
< els
; j
++)
13126 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13127 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13132 first_error (_("operand types can't be inferred"));
13136 else if (inst
.vectype
.elems
!= els
)
13138 first_error (_("type specifier has the wrong number of parts"));
13142 for (pass
= 0; pass
< 2; pass
++)
13144 for (i
= 0; i
< els
; i
++)
13146 unsigned thisarg
= types
[i
];
13147 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13148 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13149 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13150 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13152 /* Decay more-specific signed & unsigned types to sign-insensitive
13153 integer types if sign-specific variants are unavailable. */
13154 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13155 && (types_allowed
& N_SU_ALL
) == 0)
13156 g_type
= NT_integer
;
13158 /* If only untyped args are allowed, decay any more specific types to
13159 them. Some instructions only care about signs for some element
13160 sizes, so handle that properly. */
13161 if (((types_allowed
& N_UNT
) == 0)
13162 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13163 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13164 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13165 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13166 g_type
= NT_untyped
;
13170 if ((thisarg
& N_KEY
) != 0)
13174 key_allowed
= thisarg
& ~N_KEY
;
13179 if ((thisarg
& N_VFP
) != 0)
13181 enum neon_shape_el regshape
;
13182 unsigned regwidth
, match
;
13184 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13187 first_error (_("invalid instruction shape"));
13190 regshape
= neon_shape_tab
[ns
].el
[i
];
13191 regwidth
= neon_shape_el_size
[regshape
];
13193 /* In VFP mode, operands must match register widths. If we
13194 have a key operand, use its width, else use the width of
13195 the current operand. */
13201 if (regwidth
!= match
)
13203 first_error (_("operand size must match register width"));
13208 if ((thisarg
& N_EQK
) == 0)
13210 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13212 if ((given_type
& types_allowed
) == 0)
13214 first_error (_("bad type in Neon instruction"));
13220 enum neon_el_type mod_k_type
= k_type
;
13221 unsigned mod_k_size
= k_size
;
13222 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13223 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13225 first_error (_("inconsistent types in Neon instruction"));
13233 return inst
.vectype
.el
[key_el
];
13236 /* Neon-style VFP instruction forwarding. */
13238 /* Thumb VFP instructions have 0xE in the condition field. */
13241 do_vfp_cond_or_thumb (void)
13246 inst
.instruction
|= 0xe0000000;
13248 inst
.instruction
|= inst
.cond
<< 28;
13251 /* Look up and encode a simple mnemonic, for use as a helper function for the
13252 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13253 etc. It is assumed that operand parsing has already been done, and that the
13254 operands are in the form expected by the given opcode (this isn't necessarily
13255 the same as the form in which they were parsed, hence some massaging must
13256 take place before this function is called).
13257 Checks current arch version against that in the looked-up opcode. */
13260 do_vfp_nsyn_opcode (const char *opname
)
13262 const struct asm_opcode
*opcode
;
13264 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13269 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13270 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13277 inst
.instruction
= opcode
->tvalue
;
13278 opcode
->tencode ();
13282 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13283 opcode
->aencode ();
13288 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13290 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13295 do_vfp_nsyn_opcode ("fadds");
13297 do_vfp_nsyn_opcode ("fsubs");
13302 do_vfp_nsyn_opcode ("faddd");
13304 do_vfp_nsyn_opcode ("fsubd");
13308 /* Check operand types to see if this is a VFP instruction, and if so call
13312 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13314 enum neon_shape rs
;
13315 struct neon_type_el et
;
13320 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13321 et
= neon_check_type (2, rs
,
13322 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13326 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13327 et
= neon_check_type (3, rs
,
13328 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13335 if (et
.type
!= NT_invtype
)
13346 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13348 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13353 do_vfp_nsyn_opcode ("fmacs");
13355 do_vfp_nsyn_opcode ("fnmacs");
13360 do_vfp_nsyn_opcode ("fmacd");
13362 do_vfp_nsyn_opcode ("fnmacd");
13367 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13369 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13374 do_vfp_nsyn_opcode ("ffmas");
13376 do_vfp_nsyn_opcode ("ffnmas");
13381 do_vfp_nsyn_opcode ("ffmad");
13383 do_vfp_nsyn_opcode ("ffnmad");
13388 do_vfp_nsyn_mul (enum neon_shape rs
)
13391 do_vfp_nsyn_opcode ("fmuls");
13393 do_vfp_nsyn_opcode ("fmuld");
13397 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13399 int is_neg
= (inst
.instruction
& 0x80) != 0;
13400 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13405 do_vfp_nsyn_opcode ("fnegs");
13407 do_vfp_nsyn_opcode ("fabss");
13412 do_vfp_nsyn_opcode ("fnegd");
13414 do_vfp_nsyn_opcode ("fabsd");
13418 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13419 insns belong to Neon, and are handled elsewhere. */
13422 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13424 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13428 do_vfp_nsyn_opcode ("fldmdbs");
13430 do_vfp_nsyn_opcode ("fldmias");
13435 do_vfp_nsyn_opcode ("fstmdbs");
13437 do_vfp_nsyn_opcode ("fstmias");
13442 do_vfp_nsyn_sqrt (void)
13444 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13445 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13448 do_vfp_nsyn_opcode ("fsqrts");
13450 do_vfp_nsyn_opcode ("fsqrtd");
13454 do_vfp_nsyn_div (void)
13456 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13457 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13458 N_F32
| N_F64
| N_KEY
| N_VFP
);
13461 do_vfp_nsyn_opcode ("fdivs");
13463 do_vfp_nsyn_opcode ("fdivd");
13467 do_vfp_nsyn_nmul (void)
13469 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13470 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13471 N_F32
| N_F64
| N_KEY
| N_VFP
);
13475 NEON_ENCODE (SINGLE
, inst
);
13476 do_vfp_sp_dyadic ();
13480 NEON_ENCODE (DOUBLE
, inst
);
13481 do_vfp_dp_rd_rn_rm ();
13483 do_vfp_cond_or_thumb ();
13487 do_vfp_nsyn_cmp (void)
13489 if (inst
.operands
[1].isreg
)
13491 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13492 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13496 NEON_ENCODE (SINGLE
, inst
);
13497 do_vfp_sp_monadic ();
13501 NEON_ENCODE (DOUBLE
, inst
);
13502 do_vfp_dp_rd_rm ();
13507 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13508 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13510 switch (inst
.instruction
& 0x0fffffff)
13513 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13516 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13524 NEON_ENCODE (SINGLE
, inst
);
13525 do_vfp_sp_compare_z ();
13529 NEON_ENCODE (DOUBLE
, inst
);
13533 do_vfp_cond_or_thumb ();
13537 nsyn_insert_sp (void)
13539 inst
.operands
[1] = inst
.operands
[0];
13540 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13541 inst
.operands
[0].reg
= REG_SP
;
13542 inst
.operands
[0].isreg
= 1;
13543 inst
.operands
[0].writeback
= 1;
13544 inst
.operands
[0].present
= 1;
13548 do_vfp_nsyn_push (void)
13551 if (inst
.operands
[1].issingle
)
13552 do_vfp_nsyn_opcode ("fstmdbs");
13554 do_vfp_nsyn_opcode ("fstmdbd");
13558 do_vfp_nsyn_pop (void)
13561 if (inst
.operands
[1].issingle
)
13562 do_vfp_nsyn_opcode ("fldmias");
13564 do_vfp_nsyn_opcode ("fldmiad");
13567 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13568 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13571 neon_dp_fixup (struct arm_it
* insn
)
13573 unsigned int i
= insn
->instruction
;
13578 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13589 insn
->instruction
= i
;
13592 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13596 neon_logbits (unsigned x
)
13598 return ffs (x
) - 4;
13601 #define LOW4(R) ((R) & 0xf)
13602 #define HI1(R) (((R) >> 4) & 1)
13604 /* Encode insns with bit pattern:
13606 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13607 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13609 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13610 different meaning for some instruction. */
13613 neon_three_same (int isquad
, int ubit
, int size
)
13615 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13616 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13617 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13618 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13619 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13620 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13621 inst
.instruction
|= (isquad
!= 0) << 6;
13622 inst
.instruction
|= (ubit
!= 0) << 24;
13624 inst
.instruction
|= neon_logbits (size
) << 20;
13626 neon_dp_fixup (&inst
);
13629 /* Encode instructions of the form:
13631 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13632 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13634 Don't write size if SIZE == -1. */
13637 neon_two_same (int qbit
, int ubit
, int size
)
13639 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13640 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13641 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13642 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13643 inst
.instruction
|= (qbit
!= 0) << 6;
13644 inst
.instruction
|= (ubit
!= 0) << 24;
13647 inst
.instruction
|= neon_logbits (size
) << 18;
13649 neon_dp_fixup (&inst
);
13652 /* Neon instruction encoders, in approximate order of appearance. */
13655 do_neon_dyadic_i_su (void)
13657 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13658 struct neon_type_el et
= neon_check_type (3, rs
,
13659 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13660 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13664 do_neon_dyadic_i64_su (void)
13666 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13667 struct neon_type_el et
= neon_check_type (3, rs
,
13668 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13669 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13673 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13676 unsigned size
= et
.size
>> 3;
13677 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13678 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13679 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13680 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13681 inst
.instruction
|= (isquad
!= 0) << 6;
13682 inst
.instruction
|= immbits
<< 16;
13683 inst
.instruction
|= (size
>> 3) << 7;
13684 inst
.instruction
|= (size
& 0x7) << 19;
13686 inst
.instruction
|= (uval
!= 0) << 24;
13688 neon_dp_fixup (&inst
);
13692 do_neon_shl_imm (void)
13694 if (!inst
.operands
[2].isreg
)
13696 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13697 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13698 NEON_ENCODE (IMMED
, inst
);
13699 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13703 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13704 struct neon_type_el et
= neon_check_type (3, rs
,
13705 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13708 /* VSHL/VQSHL 3-register variants have syntax such as:
13710 whereas other 3-register operations encoded by neon_three_same have
13713 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13715 tmp
= inst
.operands
[2].reg
;
13716 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13717 inst
.operands
[1].reg
= tmp
;
13718 NEON_ENCODE (INTEGER
, inst
);
13719 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13724 do_neon_qshl_imm (void)
13726 if (!inst
.operands
[2].isreg
)
13728 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13729 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13731 NEON_ENCODE (IMMED
, inst
);
13732 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13733 inst
.operands
[2].imm
);
13737 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13738 struct neon_type_el et
= neon_check_type (3, rs
,
13739 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13742 /* See note in do_neon_shl_imm. */
13743 tmp
= inst
.operands
[2].reg
;
13744 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13745 inst
.operands
[1].reg
= tmp
;
13746 NEON_ENCODE (INTEGER
, inst
);
13747 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13752 do_neon_rshl (void)
13754 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13755 struct neon_type_el et
= neon_check_type (3, rs
,
13756 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13759 tmp
= inst
.operands
[2].reg
;
13760 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13761 inst
.operands
[1].reg
= tmp
;
13762 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13766 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13768 /* Handle .I8 pseudo-instructions. */
13771 /* Unfortunately, this will make everything apart from zero out-of-range.
13772 FIXME is this the intended semantics? There doesn't seem much point in
13773 accepting .I8 if so. */
13774 immediate
|= immediate
<< 8;
13780 if (immediate
== (immediate
& 0x000000ff))
13782 *immbits
= immediate
;
13785 else if (immediate
== (immediate
& 0x0000ff00))
13787 *immbits
= immediate
>> 8;
13790 else if (immediate
== (immediate
& 0x00ff0000))
13792 *immbits
= immediate
>> 16;
13795 else if (immediate
== (immediate
& 0xff000000))
13797 *immbits
= immediate
>> 24;
13800 if ((immediate
& 0xffff) != (immediate
>> 16))
13801 goto bad_immediate
;
13802 immediate
&= 0xffff;
13805 if (immediate
== (immediate
& 0x000000ff))
13807 *immbits
= immediate
;
13810 else if (immediate
== (immediate
& 0x0000ff00))
13812 *immbits
= immediate
>> 8;
13817 first_error (_("immediate value out of range"));
13821 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13825 neon_bits_same_in_bytes (unsigned imm
)
13827 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13828 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13829 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13830 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13833 /* For immediate of above form, return 0bABCD. */
13836 neon_squash_bits (unsigned imm
)
13838 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13839 | ((imm
& 0x01000000) >> 21);
13842 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13845 neon_qfloat_bits (unsigned imm
)
13847 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13850 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13851 the instruction. *OP is passed as the initial value of the op field, and
13852 may be set to a different value depending on the constant (i.e.
13853 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13854 MVN). If the immediate looks like a repeated pattern then also
13855 try smaller element sizes. */
13858 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13859 unsigned *immbits
, int *op
, int size
,
13860 enum neon_el_type type
)
13862 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13864 if (type
== NT_float
&& !float_p
)
13867 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13869 if (size
!= 32 || *op
== 1)
13871 *immbits
= neon_qfloat_bits (immlo
);
13877 if (neon_bits_same_in_bytes (immhi
)
13878 && neon_bits_same_in_bytes (immlo
))
13882 *immbits
= (neon_squash_bits (immhi
) << 4)
13883 | neon_squash_bits (immlo
);
13888 if (immhi
!= immlo
)
13894 if (immlo
== (immlo
& 0x000000ff))
13899 else if (immlo
== (immlo
& 0x0000ff00))
13901 *immbits
= immlo
>> 8;
13904 else if (immlo
== (immlo
& 0x00ff0000))
13906 *immbits
= immlo
>> 16;
13909 else if (immlo
== (immlo
& 0xff000000))
13911 *immbits
= immlo
>> 24;
13914 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13916 *immbits
= (immlo
>> 8) & 0xff;
13919 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13921 *immbits
= (immlo
>> 16) & 0xff;
13925 if ((immlo
& 0xffff) != (immlo
>> 16))
13932 if (immlo
== (immlo
& 0x000000ff))
13937 else if (immlo
== (immlo
& 0x0000ff00))
13939 *immbits
= immlo
>> 8;
13943 if ((immlo
& 0xff) != (immlo
>> 8))
13948 if (immlo
== (immlo
& 0x000000ff))
13950 /* Don't allow MVN with 8-bit immediate. */
13960 /* Write immediate bits [7:0] to the following locations:
13962 |28/24|23 19|18 16|15 4|3 0|
13963 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13965 This function is used by VMOV/VMVN/VORR/VBIC. */
13968 neon_write_immbits (unsigned immbits
)
13970 inst
.instruction
|= immbits
& 0xf;
13971 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13972 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13975 /* Invert low-order SIZE bits of XHI:XLO. */
13978 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13980 unsigned immlo
= xlo
? *xlo
: 0;
13981 unsigned immhi
= xhi
? *xhi
: 0;
13986 immlo
= (~immlo
) & 0xff;
13990 immlo
= (~immlo
) & 0xffff;
13994 immhi
= (~immhi
) & 0xffffffff;
13995 /* fall through. */
13998 immlo
= (~immlo
) & 0xffffffff;
14013 do_neon_logic (void)
14015 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14017 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14018 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14019 /* U bit and size field were set as part of the bitmask. */
14020 NEON_ENCODE (INTEGER
, inst
);
14021 neon_three_same (neon_quad (rs
), 0, -1);
14025 const int three_ops_form
= (inst
.operands
[2].present
14026 && !inst
.operands
[2].isreg
);
14027 const int immoperand
= (three_ops_form
? 2 : 1);
14028 enum neon_shape rs
= (three_ops_form
14029 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14030 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14031 struct neon_type_el et
= neon_check_type (2, rs
,
14032 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14033 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14037 if (et
.type
== NT_invtype
)
14040 if (three_ops_form
)
14041 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14042 _("first and second operands shall be the same register"));
14044 NEON_ENCODE (IMMED
, inst
);
14046 immbits
= inst
.operands
[immoperand
].imm
;
14049 /* .i64 is a pseudo-op, so the immediate must be a repeating
14051 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14052 inst
.operands
[immoperand
].reg
: 0))
14054 /* Set immbits to an invalid constant. */
14055 immbits
= 0xdeadbeef;
14062 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14066 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14070 /* Pseudo-instruction for VBIC. */
14071 neon_invert_size (&immbits
, 0, et
.size
);
14072 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14076 /* Pseudo-instruction for VORR. */
14077 neon_invert_size (&immbits
, 0, et
.size
);
14078 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14088 inst
.instruction
|= neon_quad (rs
) << 6;
14089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14091 inst
.instruction
|= cmode
<< 8;
14092 neon_write_immbits (immbits
);
14094 neon_dp_fixup (&inst
);
14099 do_neon_bitfield (void)
14101 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14102 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14103 neon_three_same (neon_quad (rs
), 0, -1);
14107 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14110 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14111 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14113 if (et
.type
== NT_float
)
14115 NEON_ENCODE (FLOAT
, inst
);
14116 neon_three_same (neon_quad (rs
), 0, -1);
14120 NEON_ENCODE (INTEGER
, inst
);
14121 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14126 do_neon_dyadic_if_su (void)
14128 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14132 do_neon_dyadic_if_su_d (void)
14134 /* This version only allow D registers, but that constraint is enforced during
14135 operand parsing so we don't need to do anything extra here. */
14136 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14140 do_neon_dyadic_if_i_d (void)
14142 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14143 affected if we specify unsigned args. */
14144 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14147 enum vfp_or_neon_is_neon_bits
14150 NEON_CHECK_ARCH
= 2,
14151 NEON_CHECK_ARCH8
= 4
14154 /* Call this function if an instruction which may have belonged to the VFP or
14155 Neon instruction sets, but turned out to be a Neon instruction (due to the
14156 operand types involved, etc.). We have to check and/or fix-up a couple of
14159 - Make sure the user hasn't attempted to make a Neon instruction
14161 - Alter the value in the condition code field if necessary.
14162 - Make sure that the arch supports Neon instructions.
14164 Which of these operations take place depends on bits from enum
14165 vfp_or_neon_is_neon_bits.
14167 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14168 current instruction's condition is COND_ALWAYS, the condition field is
14169 changed to inst.uncond_value. This is necessary because instructions shared
14170 between VFP and Neon may be conditional for the VFP variants only, and the
14171 unconditional Neon version must have, e.g., 0xF in the condition field. */
14174 vfp_or_neon_is_neon (unsigned check
)
14176 /* Conditions are always legal in Thumb mode (IT blocks). */
14177 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14179 if (inst
.cond
!= COND_ALWAYS
)
14181 first_error (_(BAD_COND
));
14184 if (inst
.uncond_value
!= -1)
14185 inst
.instruction
|= inst
.uncond_value
<< 28;
14188 if ((check
& NEON_CHECK_ARCH
)
14189 && !mark_feature_used (&fpu_neon_ext_v1
))
14191 first_error (_(BAD_FPU
));
14195 if ((check
& NEON_CHECK_ARCH8
)
14196 && !mark_feature_used (&fpu_neon_ext_armv8
))
14198 first_error (_(BAD_FPU
));
14206 do_neon_addsub_if_i (void)
14208 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14211 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14214 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14215 affected if we specify unsigned args. */
14216 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14219 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14221 V<op> A,B (A is operand 0, B is operand 2)
14226 so handle that case specially. */
14229 neon_exchange_operands (void)
14231 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14232 if (inst
.operands
[1].present
)
14234 /* Swap operands[1] and operands[2]. */
14235 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14236 inst
.operands
[1] = inst
.operands
[2];
14237 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14241 inst
.operands
[1] = inst
.operands
[2];
14242 inst
.operands
[2] = inst
.operands
[0];
14247 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14249 if (inst
.operands
[2].isreg
)
14252 neon_exchange_operands ();
14253 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14257 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14258 struct neon_type_el et
= neon_check_type (2, rs
,
14259 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14261 NEON_ENCODE (IMMED
, inst
);
14262 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14263 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14264 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14265 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14266 inst
.instruction
|= neon_quad (rs
) << 6;
14267 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14268 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14270 neon_dp_fixup (&inst
);
14277 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14281 do_neon_cmp_inv (void)
14283 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14289 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14292 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14293 scalars, which are encoded in 5 bits, M : Rm.
14294 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14295 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14299 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14301 unsigned regno
= NEON_SCALAR_REG (scalar
);
14302 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14307 if (regno
> 7 || elno
> 3)
14309 return regno
| (elno
<< 3);
14312 if (regno
> 15 || elno
> 1)
14314 return regno
| (elno
<< 4);
14318 first_error (_("scalar out of range for multiply instruction"));
14324 /* Encode multiply / multiply-accumulate scalar instructions. */
14327 neon_mul_mac (struct neon_type_el et
, int ubit
)
14331 /* Give a more helpful error message if we have an invalid type. */
14332 if (et
.type
== NT_invtype
)
14335 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14336 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14337 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14338 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14339 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14340 inst
.instruction
|= LOW4 (scalar
);
14341 inst
.instruction
|= HI1 (scalar
) << 5;
14342 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14343 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14344 inst
.instruction
|= (ubit
!= 0) << 24;
14346 neon_dp_fixup (&inst
);
14350 do_neon_mac_maybe_scalar (void)
14352 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14355 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14358 if (inst
.operands
[2].isscalar
)
14360 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14361 struct neon_type_el et
= neon_check_type (3, rs
,
14362 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14363 NEON_ENCODE (SCALAR
, inst
);
14364 neon_mul_mac (et
, neon_quad (rs
));
14368 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14369 affected if we specify unsigned args. */
14370 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14375 do_neon_fmac (void)
14377 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14380 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14383 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14389 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14390 struct neon_type_el et
= neon_check_type (3, rs
,
14391 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14392 neon_three_same (neon_quad (rs
), 0, et
.size
);
14395 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14396 same types as the MAC equivalents. The polynomial type for this instruction
14397 is encoded the same as the integer type. */
14402 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14405 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14408 if (inst
.operands
[2].isscalar
)
14409 do_neon_mac_maybe_scalar ();
14411 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14415 do_neon_qdmulh (void)
14417 if (inst
.operands
[2].isscalar
)
14419 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14420 struct neon_type_el et
= neon_check_type (3, rs
,
14421 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14422 NEON_ENCODE (SCALAR
, inst
);
14423 neon_mul_mac (et
, neon_quad (rs
));
14427 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14428 struct neon_type_el et
= neon_check_type (3, rs
,
14429 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14430 NEON_ENCODE (INTEGER
, inst
);
14431 /* The U bit (rounding) comes from bit mask. */
14432 neon_three_same (neon_quad (rs
), 0, et
.size
);
14437 do_neon_fcmp_absolute (void)
14439 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14440 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14441 /* Size field comes from bit mask. */
14442 neon_three_same (neon_quad (rs
), 1, -1);
14446 do_neon_fcmp_absolute_inv (void)
14448 neon_exchange_operands ();
14449 do_neon_fcmp_absolute ();
14453 do_neon_step (void)
14455 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14456 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14457 neon_three_same (neon_quad (rs
), 0, -1);
14461 do_neon_abs_neg (void)
14463 enum neon_shape rs
;
14464 struct neon_type_el et
;
14466 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14469 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14472 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14473 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14479 inst
.instruction
|= neon_quad (rs
) << 6;
14480 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14481 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14483 neon_dp_fixup (&inst
);
14489 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14490 struct neon_type_el et
= neon_check_type (2, rs
,
14491 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14492 int imm
= inst
.operands
[2].imm
;
14493 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14494 _("immediate out of range for insert"));
14495 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14501 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14502 struct neon_type_el et
= neon_check_type (2, rs
,
14503 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14504 int imm
= inst
.operands
[2].imm
;
14505 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14506 _("immediate out of range for insert"));
14507 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14511 do_neon_qshlu_imm (void)
14513 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14514 struct neon_type_el et
= neon_check_type (2, rs
,
14515 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14516 int imm
= inst
.operands
[2].imm
;
14517 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14518 _("immediate out of range for shift"));
14519 /* Only encodes the 'U present' variant of the instruction.
14520 In this case, signed types have OP (bit 8) set to 0.
14521 Unsigned types have OP set to 1. */
14522 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14523 /* The rest of the bits are the same as other immediate shifts. */
14524 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14528 do_neon_qmovn (void)
14530 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14531 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14532 /* Saturating move where operands can be signed or unsigned, and the
14533 destination has the same signedness. */
14534 NEON_ENCODE (INTEGER
, inst
);
14535 if (et
.type
== NT_unsigned
)
14536 inst
.instruction
|= 0xc0;
14538 inst
.instruction
|= 0x80;
14539 neon_two_same (0, 1, et
.size
/ 2);
14543 do_neon_qmovun (void)
14545 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14546 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14547 /* Saturating move with unsigned results. Operands must be signed. */
14548 NEON_ENCODE (INTEGER
, inst
);
14549 neon_two_same (0, 1, et
.size
/ 2);
14553 do_neon_rshift_sat_narrow (void)
14555 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14556 or unsigned. If operands are unsigned, results must also be unsigned. */
14557 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14558 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14559 int imm
= inst
.operands
[2].imm
;
14560 /* This gets the bounds check, size encoding and immediate bits calculation
14564 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14565 VQMOVN.I<size> <Dd>, <Qm>. */
14568 inst
.operands
[2].present
= 0;
14569 inst
.instruction
= N_MNEM_vqmovn
;
14574 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14575 _("immediate out of range"));
14576 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14580 do_neon_rshift_sat_narrow_u (void)
14582 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14583 or unsigned. If operands are unsigned, results must also be unsigned. */
14584 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14585 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14586 int imm
= inst
.operands
[2].imm
;
14587 /* This gets the bounds check, size encoding and immediate bits calculation
14591 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14592 VQMOVUN.I<size> <Dd>, <Qm>. */
14595 inst
.operands
[2].present
= 0;
14596 inst
.instruction
= N_MNEM_vqmovun
;
14601 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14602 _("immediate out of range"));
14603 /* FIXME: The manual is kind of unclear about what value U should have in
14604 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14606 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14610 do_neon_movn (void)
14612 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14613 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14614 NEON_ENCODE (INTEGER
, inst
);
14615 neon_two_same (0, 1, et
.size
/ 2);
14619 do_neon_rshift_narrow (void)
14621 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14622 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14623 int imm
= inst
.operands
[2].imm
;
14624 /* This gets the bounds check, size encoding and immediate bits calculation
14628 /* If immediate is zero then we are a pseudo-instruction for
14629 VMOVN.I<size> <Dd>, <Qm> */
14632 inst
.operands
[2].present
= 0;
14633 inst
.instruction
= N_MNEM_vmovn
;
14638 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14639 _("immediate out of range for narrowing operation"));
14640 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14644 do_neon_shll (void)
14646 /* FIXME: Type checking when lengthening. */
14647 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14648 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14649 unsigned imm
= inst
.operands
[2].imm
;
14651 if (imm
== et
.size
)
14653 /* Maximum shift variant. */
14654 NEON_ENCODE (INTEGER
, inst
);
14655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14659 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14661 neon_dp_fixup (&inst
);
14665 /* A more-specific type check for non-max versions. */
14666 et
= neon_check_type (2, NS_QDI
,
14667 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14668 NEON_ENCODE (IMMED
, inst
);
14669 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14673 /* Check the various types for the VCVT instruction, and return which version
14674 the current instruction is. */
14676 #define CVT_FLAVOUR_VAR \
14677 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14678 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14679 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14680 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14681 /* Half-precision conversions. */ \
14682 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14683 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14684 /* VFP instructions. */ \
14685 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14686 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14687 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14688 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14689 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14690 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14691 /* VFP instructions with bitshift. */ \
14692 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14693 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14694 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14695 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14696 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14697 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14698 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14699 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14701 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14702 neon_cvt_flavour_##C,
14704 /* The different types of conversions we can do. */
14705 enum neon_cvt_flavour
14708 neon_cvt_flavour_invalid
,
14709 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14714 static enum neon_cvt_flavour
14715 get_neon_cvt_flavour (enum neon_shape rs
)
14717 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14718 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14719 if (et.type != NT_invtype) \
14721 inst.error = NULL; \
14722 return (neon_cvt_flavour_##C); \
14725 struct neon_type_el et
;
14726 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14727 || rs
== NS_FF
) ? N_VFP
: 0;
14728 /* The instruction versions which take an immediate take one register
14729 argument, which is extended to the width of the full register. Thus the
14730 "source" and "destination" registers must have the same width. Hack that
14731 here by making the size equal to the key (wider, in this case) operand. */
14732 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14736 return neon_cvt_flavour_invalid
;
14751 /* Neon-syntax VFP conversions. */
14754 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
14756 const char *opname
= 0;
14758 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14760 /* Conversions with immediate bitshift. */
14761 const char *enc
[] =
14763 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14769 if (flavour
< (int) ARRAY_SIZE (enc
))
14771 opname
= enc
[flavour
];
14772 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14773 _("operands 0 and 1 must be the same register"));
14774 inst
.operands
[1] = inst
.operands
[2];
14775 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14780 /* Conversions without bitshift. */
14781 const char *enc
[] =
14783 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14789 if (flavour
< (int) ARRAY_SIZE (enc
))
14790 opname
= enc
[flavour
];
14794 do_vfp_nsyn_opcode (opname
);
14798 do_vfp_nsyn_cvtz (void)
14800 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14801 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14802 const char *enc
[] =
14804 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14810 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14811 do_vfp_nsyn_opcode (enc
[flavour
]);
14815 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
14816 enum neon_cvt_mode mode
)
14821 set_it_insn_type (OUTSIDE_IT_INSN
);
14825 case neon_cvt_flavour_s32_f64
:
14829 case neon_cvt_flavour_s32_f32
:
14833 case neon_cvt_flavour_u32_f64
:
14837 case neon_cvt_flavour_u32_f32
:
14842 first_error (_("invalid instruction shape"));
14848 case neon_cvt_mode_a
: rm
= 0; break;
14849 case neon_cvt_mode_n
: rm
= 1; break;
14850 case neon_cvt_mode_p
: rm
= 2; break;
14851 case neon_cvt_mode_m
: rm
= 3; break;
14852 default: first_error (_("invalid rounding mode")); return;
14855 NEON_ENCODE (FPV8
, inst
);
14856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14857 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
14858 inst
.instruction
|= sz
<< 8;
14859 inst
.instruction
|= op
<< 7;
14860 inst
.instruction
|= rm
<< 16;
14861 inst
.instruction
|= 0xf0000000;
14862 inst
.is_neon
= TRUE
;
14866 do_neon_cvt_1 (enum neon_cvt_mode mode
)
14868 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14869 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14870 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14872 /* PR11109: Handle round-to-zero for VCVT conversions. */
14873 if (mode
== neon_cvt_mode_z
14874 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14875 && (flavour
== neon_cvt_flavour_s32_f32
14876 || flavour
== neon_cvt_flavour_u32_f32
14877 || flavour
== neon_cvt_flavour_s32_f64
14878 || flavour
== neon_cvt_flavour_u32_f64
)
14879 && (rs
== NS_FD
|| rs
== NS_FF
))
14881 do_vfp_nsyn_cvtz ();
14885 /* VFP rather than Neon conversions. */
14886 if (flavour
>= neon_cvt_flavour_first_fp
)
14888 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
14889 do_vfp_nsyn_cvt (rs
, flavour
);
14891 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
14902 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14904 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14907 /* Fixed-point conversion with #0 immediate is encoded as an
14908 integer conversion. */
14909 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14911 immbits
= 32 - inst
.operands
[2].imm
;
14912 NEON_ENCODE (IMMED
, inst
);
14913 if (flavour
!= neon_cvt_flavour_invalid
)
14914 inst
.instruction
|= enctab
[flavour
];
14915 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14916 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14917 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14918 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14919 inst
.instruction
|= neon_quad (rs
) << 6;
14920 inst
.instruction
|= 1 << 21;
14921 inst
.instruction
|= immbits
<< 16;
14923 neon_dp_fixup (&inst
);
14929 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
14931 NEON_ENCODE (FLOAT
, inst
);
14932 set_it_insn_type (OUTSIDE_IT_INSN
);
14934 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
14937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14939 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14940 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14941 inst
.instruction
|= neon_quad (rs
) << 6;
14942 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
14943 inst
.instruction
|= mode
<< 8;
14945 inst
.instruction
|= 0xfc000000;
14947 inst
.instruction
|= 0xf0000000;
14953 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14955 NEON_ENCODE (INTEGER
, inst
);
14957 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14960 if (flavour
!= neon_cvt_flavour_invalid
)
14961 inst
.instruction
|= enctab
[flavour
];
14963 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14964 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14965 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14966 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14967 inst
.instruction
|= neon_quad (rs
) << 6;
14968 inst
.instruction
|= 2 << 18;
14970 neon_dp_fixup (&inst
);
14975 /* Half-precision conversions for Advanced SIMD -- neon. */
14980 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14982 as_bad (_("operand size must match register width"));
14987 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14989 as_bad (_("operand size must match register width"));
14994 inst
.instruction
= 0x3b60600;
14996 inst
.instruction
= 0x3b60700;
14998 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14999 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15000 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15001 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15002 neon_dp_fixup (&inst
);
15006 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15007 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15008 do_vfp_nsyn_cvt (rs
, flavour
);
15010 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15015 do_neon_cvtr (void)
15017 do_neon_cvt_1 (neon_cvt_mode_x
);
15023 do_neon_cvt_1 (neon_cvt_mode_z
);
15027 do_neon_cvta (void)
15029 do_neon_cvt_1 (neon_cvt_mode_a
);
15033 do_neon_cvtn (void)
15035 do_neon_cvt_1 (neon_cvt_mode_n
);
15039 do_neon_cvtp (void)
15041 do_neon_cvt_1 (neon_cvt_mode_p
);
15045 do_neon_cvtm (void)
15047 do_neon_cvt_1 (neon_cvt_mode_m
);
15051 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15054 mark_feature_used (&fpu_vfp_ext_armv8
);
15056 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15057 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15058 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15059 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15060 inst
.instruction
|= to
? 0x10000 : 0;
15061 inst
.instruction
|= t
? 0x80 : 0;
15062 inst
.instruction
|= is_double
? 0x100 : 0;
15063 do_vfp_cond_or_thumb ();
15067 do_neon_cvttb_1 (bfd_boolean t
)
15069 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15073 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15076 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15078 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15081 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15083 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15086 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15088 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15091 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15098 do_neon_cvtb (void)
15100 do_neon_cvttb_1 (FALSE
);
15105 do_neon_cvtt (void)
15107 do_neon_cvttb_1 (TRUE
);
15111 neon_move_immediate (void)
15113 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15114 struct neon_type_el et
= neon_check_type (2, rs
,
15115 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15116 unsigned immlo
, immhi
= 0, immbits
;
15117 int op
, cmode
, float_p
;
15119 constraint (et
.type
== NT_invtype
,
15120 _("operand size must be specified for immediate VMOV"));
15122 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15123 op
= (inst
.instruction
& (1 << 5)) != 0;
15125 immlo
= inst
.operands
[1].imm
;
15126 if (inst
.operands
[1].regisimm
)
15127 immhi
= inst
.operands
[1].reg
;
15129 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15130 _("immediate has bits set outside the operand size"));
15132 float_p
= inst
.operands
[1].immisfloat
;
15134 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15135 et
.size
, et
.type
)) == FAIL
)
15137 /* Invert relevant bits only. */
15138 neon_invert_size (&immlo
, &immhi
, et
.size
);
15139 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15140 with one or the other; those cases are caught by
15141 neon_cmode_for_move_imm. */
15143 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15144 &op
, et
.size
, et
.type
)) == FAIL
)
15146 first_error (_("immediate out of range"));
15151 inst
.instruction
&= ~(1 << 5);
15152 inst
.instruction
|= op
<< 5;
15154 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15155 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15156 inst
.instruction
|= neon_quad (rs
) << 6;
15157 inst
.instruction
|= cmode
<< 8;
15159 neon_write_immbits (immbits
);
15165 if (inst
.operands
[1].isreg
)
15167 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15169 NEON_ENCODE (INTEGER
, inst
);
15170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15172 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15173 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15174 inst
.instruction
|= neon_quad (rs
) << 6;
15178 NEON_ENCODE (IMMED
, inst
);
15179 neon_move_immediate ();
15182 neon_dp_fixup (&inst
);
15185 /* Encode instructions of form:
15187 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15188 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15191 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15193 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15194 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15195 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15196 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15197 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15198 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15199 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15200 inst
.instruction
|= neon_logbits (size
) << 20;
15202 neon_dp_fixup (&inst
);
15206 do_neon_dyadic_long (void)
15208 /* FIXME: Type checking for lengthening op. */
15209 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15210 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15211 neon_mixed_length (et
, et
.size
);
15215 do_neon_abal (void)
15217 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15218 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15219 neon_mixed_length (et
, et
.size
);
15223 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15225 if (inst
.operands
[2].isscalar
)
15227 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15228 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15229 NEON_ENCODE (SCALAR
, inst
);
15230 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15234 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15235 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15236 NEON_ENCODE (INTEGER
, inst
);
15237 neon_mixed_length (et
, et
.size
);
15242 do_neon_mac_maybe_scalar_long (void)
15244 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15248 do_neon_dyadic_wide (void)
15250 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15251 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15252 neon_mixed_length (et
, et
.size
);
15256 do_neon_dyadic_narrow (void)
15258 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15259 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15260 /* Operand sign is unimportant, and the U bit is part of the opcode,
15261 so force the operand type to integer. */
15262 et
.type
= NT_integer
;
15263 neon_mixed_length (et
, et
.size
/ 2);
15267 do_neon_mul_sat_scalar_long (void)
15269 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15273 do_neon_vmull (void)
15275 if (inst
.operands
[2].isscalar
)
15276 do_neon_mac_maybe_scalar_long ();
15279 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15280 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15282 if (et
.type
== NT_poly
)
15283 NEON_ENCODE (POLY
, inst
);
15285 NEON_ENCODE (INTEGER
, inst
);
15287 /* For polynomial encoding the U bit must be zero, and the size must
15288 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15289 obviously, as 0b10). */
15292 /* Check we're on the correct architecture. */
15293 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15295 _("Instruction form not available on this architecture.");
15300 neon_mixed_length (et
, et
.size
);
15307 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15308 struct neon_type_el et
= neon_check_type (3, rs
,
15309 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15310 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15312 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15313 _("shift out of range"));
15314 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15315 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15316 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15317 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15318 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15319 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15320 inst
.instruction
|= neon_quad (rs
) << 6;
15321 inst
.instruction
|= imm
<< 8;
15323 neon_dp_fixup (&inst
);
15329 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15330 struct neon_type_el et
= neon_check_type (2, rs
,
15331 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15332 unsigned op
= (inst
.instruction
>> 7) & 3;
15333 /* N (width of reversed regions) is encoded as part of the bitmask. We
15334 extract it here to check the elements to be reversed are smaller.
15335 Otherwise we'd get a reserved instruction. */
15336 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15337 gas_assert (elsize
!= 0);
15338 constraint (et
.size
>= elsize
,
15339 _("elements must be smaller than reversal region"));
15340 neon_two_same (neon_quad (rs
), 1, et
.size
);
15346 if (inst
.operands
[1].isscalar
)
15348 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15349 struct neon_type_el et
= neon_check_type (2, rs
,
15350 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15351 unsigned sizebits
= et
.size
>> 3;
15352 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15353 int logsize
= neon_logbits (et
.size
);
15354 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15356 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15359 NEON_ENCODE (SCALAR
, inst
);
15360 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15361 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15362 inst
.instruction
|= LOW4 (dm
);
15363 inst
.instruction
|= HI1 (dm
) << 5;
15364 inst
.instruction
|= neon_quad (rs
) << 6;
15365 inst
.instruction
|= x
<< 17;
15366 inst
.instruction
|= sizebits
<< 16;
15368 neon_dp_fixup (&inst
);
15372 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15373 struct neon_type_el et
= neon_check_type (2, rs
,
15374 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15375 /* Duplicate ARM register to lanes of vector. */
15376 NEON_ENCODE (ARMREG
, inst
);
15379 case 8: inst
.instruction
|= 0x400000; break;
15380 case 16: inst
.instruction
|= 0x000020; break;
15381 case 32: inst
.instruction
|= 0x000000; break;
15384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15385 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15386 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15387 inst
.instruction
|= neon_quad (rs
) << 21;
15388 /* The encoding for this instruction is identical for the ARM and Thumb
15389 variants, except for the condition field. */
15390 do_vfp_cond_or_thumb ();
15394 /* VMOV has particularly many variations. It can be one of:
15395 0. VMOV<c><q> <Qd>, <Qm>
15396 1. VMOV<c><q> <Dd>, <Dm>
15397 (Register operations, which are VORR with Rm = Rn.)
15398 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15399 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15401 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15402 (ARM register to scalar.)
15403 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15404 (Two ARM registers to vector.)
15405 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15406 (Scalar to ARM register.)
15407 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15408 (Vector to two ARM registers.)
15409 8. VMOV.F32 <Sd>, <Sm>
15410 9. VMOV.F64 <Dd>, <Dm>
15411 (VFP register moves.)
15412 10. VMOV.F32 <Sd>, #imm
15413 11. VMOV.F64 <Dd>, #imm
15414 (VFP float immediate load.)
15415 12. VMOV <Rd>, <Sm>
15416 (VFP single to ARM reg.)
15417 13. VMOV <Sd>, <Rm>
15418 (ARM reg to VFP single.)
15419 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15420 (Two ARM regs to two VFP singles.)
15421 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15422 (Two VFP singles to two ARM regs.)
15424 These cases can be disambiguated using neon_select_shape, except cases 1/9
15425 and 3/11 which depend on the operand type too.
15427 All the encoded bits are hardcoded by this function.
15429 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15430 Cases 5, 7 may be used with VFPv2 and above.
15432 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15433 can specify a type where it doesn't make sense to, and is ignored). */
15438 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15439 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15441 struct neon_type_el et
;
15442 const char *ldconst
= 0;
15446 case NS_DD
: /* case 1/9. */
15447 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15448 /* It is not an error here if no type is given. */
15450 if (et
.type
== NT_float
&& et
.size
== 64)
15452 do_vfp_nsyn_opcode ("fcpyd");
15455 /* fall through. */
15457 case NS_QQ
: /* case 0/1. */
15459 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15461 /* The architecture manual I have doesn't explicitly state which
15462 value the U bit should have for register->register moves, but
15463 the equivalent VORR instruction has U = 0, so do that. */
15464 inst
.instruction
= 0x0200110;
15465 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15466 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15467 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15468 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15469 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15470 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15471 inst
.instruction
|= neon_quad (rs
) << 6;
15473 neon_dp_fixup (&inst
);
15477 case NS_DI
: /* case 3/11. */
15478 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15480 if (et
.type
== NT_float
&& et
.size
== 64)
15482 /* case 11 (fconstd). */
15483 ldconst
= "fconstd";
15484 goto encode_fconstd
;
15486 /* fall through. */
15488 case NS_QI
: /* case 2/3. */
15489 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15491 inst
.instruction
= 0x0800010;
15492 neon_move_immediate ();
15493 neon_dp_fixup (&inst
);
15496 case NS_SR
: /* case 4. */
15498 unsigned bcdebits
= 0;
15500 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15501 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15503 /* .<size> is optional here, defaulting to .32. */
15504 if (inst
.vectype
.elems
== 0
15505 && inst
.operands
[0].vectype
.type
== NT_invtype
15506 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15508 inst
.vectype
.el
[0].type
= NT_untyped
;
15509 inst
.vectype
.el
[0].size
= 32;
15510 inst
.vectype
.elems
= 1;
15513 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15514 logsize
= neon_logbits (et
.size
);
15516 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15518 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15519 && et
.size
!= 32, _(BAD_FPU
));
15520 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15521 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15525 case 8: bcdebits
= 0x8; break;
15526 case 16: bcdebits
= 0x1; break;
15527 case 32: bcdebits
= 0x0; break;
15531 bcdebits
|= x
<< logsize
;
15533 inst
.instruction
= 0xe000b10;
15534 do_vfp_cond_or_thumb ();
15535 inst
.instruction
|= LOW4 (dn
) << 16;
15536 inst
.instruction
|= HI1 (dn
) << 7;
15537 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15538 inst
.instruction
|= (bcdebits
& 3) << 5;
15539 inst
.instruction
|= (bcdebits
>> 2) << 21;
15543 case NS_DRR
: /* case 5 (fmdrr). */
15544 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15547 inst
.instruction
= 0xc400b10;
15548 do_vfp_cond_or_thumb ();
15549 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15550 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15551 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15552 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15555 case NS_RS
: /* case 6. */
15558 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15559 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15560 unsigned abcdebits
= 0;
15562 /* .<dt> is optional here, defaulting to .32. */
15563 if (inst
.vectype
.elems
== 0
15564 && inst
.operands
[0].vectype
.type
== NT_invtype
15565 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15567 inst
.vectype
.el
[0].type
= NT_untyped
;
15568 inst
.vectype
.el
[0].size
= 32;
15569 inst
.vectype
.elems
= 1;
15572 et
= neon_check_type (2, NS_NULL
,
15573 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15574 logsize
= neon_logbits (et
.size
);
15576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15578 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15579 && et
.size
!= 32, _(BAD_FPU
));
15580 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15581 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15585 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15586 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15587 case 32: abcdebits
= 0x00; break;
15591 abcdebits
|= x
<< logsize
;
15592 inst
.instruction
= 0xe100b10;
15593 do_vfp_cond_or_thumb ();
15594 inst
.instruction
|= LOW4 (dn
) << 16;
15595 inst
.instruction
|= HI1 (dn
) << 7;
15596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15597 inst
.instruction
|= (abcdebits
& 3) << 5;
15598 inst
.instruction
|= (abcdebits
>> 2) << 21;
15602 case NS_RRD
: /* case 7 (fmrrd). */
15603 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15606 inst
.instruction
= 0xc500b10;
15607 do_vfp_cond_or_thumb ();
15608 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15609 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15610 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15611 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15614 case NS_FF
: /* case 8 (fcpys). */
15615 do_vfp_nsyn_opcode ("fcpys");
15618 case NS_FI
: /* case 10 (fconsts). */
15619 ldconst
= "fconsts";
15621 if (is_quarter_float (inst
.operands
[1].imm
))
15623 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15624 do_vfp_nsyn_opcode (ldconst
);
15627 first_error (_("immediate out of range"));
15630 case NS_RF
: /* case 12 (fmrs). */
15631 do_vfp_nsyn_opcode ("fmrs");
15634 case NS_FR
: /* case 13 (fmsr). */
15635 do_vfp_nsyn_opcode ("fmsr");
15638 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15639 (one of which is a list), but we have parsed four. Do some fiddling to
15640 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15642 case NS_RRFF
: /* case 14 (fmrrs). */
15643 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15644 _("VFP registers must be adjacent"));
15645 inst
.operands
[2].imm
= 2;
15646 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15647 do_vfp_nsyn_opcode ("fmrrs");
15650 case NS_FFRR
: /* case 15 (fmsrr). */
15651 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15652 _("VFP registers must be adjacent"));
15653 inst
.operands
[1] = inst
.operands
[2];
15654 inst
.operands
[2] = inst
.operands
[3];
15655 inst
.operands
[0].imm
= 2;
15656 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15657 do_vfp_nsyn_opcode ("fmsrr");
15661 /* neon_select_shape has determined that the instruction
15662 shape is wrong and has already set the error message. */
15671 do_neon_rshift_round_imm (void)
15673 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15674 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15675 int imm
= inst
.operands
[2].imm
;
15677 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15680 inst
.operands
[2].present
= 0;
15685 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15686 _("immediate out of range for shift"));
15687 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15692 do_neon_movl (void)
15694 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15695 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15696 unsigned sizebits
= et
.size
>> 3;
15697 inst
.instruction
|= sizebits
<< 19;
15698 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15704 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15705 struct neon_type_el et
= neon_check_type (2, rs
,
15706 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15707 NEON_ENCODE (INTEGER
, inst
);
15708 neon_two_same (neon_quad (rs
), 1, et
.size
);
15712 do_neon_zip_uzp (void)
15714 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15715 struct neon_type_el et
= neon_check_type (2, rs
,
15716 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15717 if (rs
== NS_DD
&& et
.size
== 32)
15719 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15720 inst
.instruction
= N_MNEM_vtrn
;
15724 neon_two_same (neon_quad (rs
), 1, et
.size
);
15728 do_neon_sat_abs_neg (void)
15730 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15731 struct neon_type_el et
= neon_check_type (2, rs
,
15732 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15733 neon_two_same (neon_quad (rs
), 1, et
.size
);
15737 do_neon_pair_long (void)
15739 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15740 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15741 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15742 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15743 neon_two_same (neon_quad (rs
), 1, et
.size
);
15747 do_neon_recip_est (void)
15749 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15750 struct neon_type_el et
= neon_check_type (2, rs
,
15751 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15752 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15753 neon_two_same (neon_quad (rs
), 1, et
.size
);
15759 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15760 struct neon_type_el et
= neon_check_type (2, rs
,
15761 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15762 neon_two_same (neon_quad (rs
), 1, et
.size
);
15768 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15769 struct neon_type_el et
= neon_check_type (2, rs
,
15770 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15771 neon_two_same (neon_quad (rs
), 1, et
.size
);
15777 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15778 struct neon_type_el et
= neon_check_type (2, rs
,
15779 N_EQK
| N_INT
, N_8
| N_KEY
);
15780 neon_two_same (neon_quad (rs
), 1, et
.size
);
15786 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15787 neon_two_same (neon_quad (rs
), 1, -1);
15791 do_neon_tbl_tbx (void)
15793 unsigned listlenbits
;
15794 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15796 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15798 first_error (_("bad list length for table lookup"));
15802 listlenbits
= inst
.operands
[1].imm
- 1;
15803 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15804 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15805 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15806 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15807 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15808 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15809 inst
.instruction
|= listlenbits
<< 8;
15811 neon_dp_fixup (&inst
);
15815 do_neon_ldm_stm (void)
15817 /* P, U and L bits are part of bitmask. */
15818 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15819 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15821 if (inst
.operands
[1].issingle
)
15823 do_vfp_nsyn_ldm_stm (is_dbmode
);
15827 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15828 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15830 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15831 _("register list must contain at least 1 and at most 16 "
15834 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15835 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15836 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15837 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15839 inst
.instruction
|= offsetbits
;
15841 do_vfp_cond_or_thumb ();
15845 do_neon_ldr_str (void)
15847 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15849 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15850 And is UNPREDICTABLE in thumb mode. */
15852 && inst
.operands
[1].reg
== REG_PC
15853 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
15856 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15857 else if (warn_on_deprecated
)
15858 as_warn (_("Use of PC here is deprecated"));
15861 if (inst
.operands
[0].issingle
)
15864 do_vfp_nsyn_opcode ("flds");
15866 do_vfp_nsyn_opcode ("fsts");
15871 do_vfp_nsyn_opcode ("fldd");
15873 do_vfp_nsyn_opcode ("fstd");
15877 /* "interleave" version also handles non-interleaving register VLD1/VST1
15881 do_neon_ld_st_interleave (void)
15883 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15884 N_8
| N_16
| N_32
| N_64
);
15885 unsigned alignbits
= 0;
15887 /* The bits in this table go:
15888 0: register stride of one (0) or two (1)
15889 1,2: register list length, minus one (1, 2, 3, 4).
15890 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15891 We use -1 for invalid entries. */
15892 const int typetable
[] =
15894 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15895 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15896 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15897 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15901 if (et
.type
== NT_invtype
)
15904 if (inst
.operands
[1].immisalign
)
15905 switch (inst
.operands
[1].imm
>> 8)
15907 case 64: alignbits
= 1; break;
15909 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15910 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15911 goto bad_alignment
;
15915 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15916 goto bad_alignment
;
15921 first_error (_("bad alignment"));
15925 inst
.instruction
|= alignbits
<< 4;
15926 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15928 /* Bits [4:6] of the immediate in a list specifier encode register stride
15929 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15930 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15931 up the right value for "type" in a table based on this value and the given
15932 list style, then stick it back. */
15933 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15934 | (((inst
.instruction
>> 8) & 3) << 3);
15936 typebits
= typetable
[idx
];
15938 constraint (typebits
== -1, _("bad list type for instruction"));
15939 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
15940 _("bad element type for instruction"));
15942 inst
.instruction
&= ~0xf00;
15943 inst
.instruction
|= typebits
<< 8;
15946 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15947 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15948 otherwise. The variable arguments are a list of pairs of legal (size, align)
15949 values, terminated with -1. */
15952 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15955 int result
= FAIL
, thissize
, thisalign
;
15957 if (!inst
.operands
[1].immisalign
)
15963 va_start (ap
, do_align
);
15967 thissize
= va_arg (ap
, int);
15968 if (thissize
== -1)
15970 thisalign
= va_arg (ap
, int);
15972 if (size
== thissize
&& align
== thisalign
)
15975 while (result
!= SUCCESS
);
15979 if (result
== SUCCESS
)
15982 first_error (_("unsupported alignment for instruction"));
15988 do_neon_ld_st_lane (void)
15990 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15991 int align_good
, do_align
= 0;
15992 int logsize
= neon_logbits (et
.size
);
15993 int align
= inst
.operands
[1].imm
>> 8;
15994 int n
= (inst
.instruction
>> 8) & 3;
15995 int max_el
= 64 / et
.size
;
15997 if (et
.type
== NT_invtype
)
16000 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16001 _("bad list length"));
16002 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16003 _("scalar index out of range"));
16004 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16006 _("stride of 2 unavailable when element size is 8"));
16010 case 0: /* VLD1 / VST1. */
16011 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16013 if (align_good
== FAIL
)
16017 unsigned alignbits
= 0;
16020 case 16: alignbits
= 0x1; break;
16021 case 32: alignbits
= 0x3; break;
16024 inst
.instruction
|= alignbits
<< 4;
16028 case 1: /* VLD2 / VST2. */
16029 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16031 if (align_good
== FAIL
)
16034 inst
.instruction
|= 1 << 4;
16037 case 2: /* VLD3 / VST3. */
16038 constraint (inst
.operands
[1].immisalign
,
16039 _("can't use alignment with this instruction"));
16042 case 3: /* VLD4 / VST4. */
16043 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16044 16, 64, 32, 64, 32, 128, -1);
16045 if (align_good
== FAIL
)
16049 unsigned alignbits
= 0;
16052 case 8: alignbits
= 0x1; break;
16053 case 16: alignbits
= 0x1; break;
16054 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16057 inst
.instruction
|= alignbits
<< 4;
16064 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16065 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16066 inst
.instruction
|= 1 << (4 + logsize
);
16068 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16069 inst
.instruction
|= logsize
<< 10;
16072 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16075 do_neon_ld_dup (void)
16077 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16078 int align_good
, do_align
= 0;
16080 if (et
.type
== NT_invtype
)
16083 switch ((inst
.instruction
>> 8) & 3)
16085 case 0: /* VLD1. */
16086 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16087 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16088 &do_align
, 16, 16, 32, 32, -1);
16089 if (align_good
== FAIL
)
16091 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16094 case 2: inst
.instruction
|= 1 << 5; break;
16095 default: first_error (_("bad list length")); return;
16097 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16100 case 1: /* VLD2. */
16101 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16102 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16103 if (align_good
== FAIL
)
16105 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16106 _("bad list length"));
16107 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16108 inst
.instruction
|= 1 << 5;
16109 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16112 case 2: /* VLD3. */
16113 constraint (inst
.operands
[1].immisalign
,
16114 _("can't use alignment with this instruction"));
16115 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16116 _("bad list length"));
16117 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16118 inst
.instruction
|= 1 << 5;
16119 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16122 case 3: /* VLD4. */
16124 int align
= inst
.operands
[1].imm
>> 8;
16125 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16126 16, 64, 32, 64, 32, 128, -1);
16127 if (align_good
== FAIL
)
16129 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16130 _("bad list length"));
16131 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16132 inst
.instruction
|= 1 << 5;
16133 if (et
.size
== 32 && align
== 128)
16134 inst
.instruction
|= 0x3 << 6;
16136 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16143 inst
.instruction
|= do_align
<< 4;
16146 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16147 apart from bits [11:4]. */
16150 do_neon_ldx_stx (void)
16152 if (inst
.operands
[1].isreg
)
16153 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16155 switch (NEON_LANE (inst
.operands
[0].imm
))
16157 case NEON_INTERLEAVE_LANES
:
16158 NEON_ENCODE (INTERLV
, inst
);
16159 do_neon_ld_st_interleave ();
16162 case NEON_ALL_LANES
:
16163 NEON_ENCODE (DUP
, inst
);
16164 if (inst
.instruction
== N_INV
)
16166 first_error ("only loads support such operands");
16173 NEON_ENCODE (LANE
, inst
);
16174 do_neon_ld_st_lane ();
16177 /* L bit comes from bit mask. */
16178 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16179 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16182 if (inst
.operands
[1].postind
)
16184 int postreg
= inst
.operands
[1].imm
& 0xf;
16185 constraint (!inst
.operands
[1].immisreg
,
16186 _("post-index must be a register"));
16187 constraint (postreg
== 0xd || postreg
== 0xf,
16188 _("bad register for post-index"));
16189 inst
.instruction
|= postreg
;
16193 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16194 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16195 || inst
.reloc
.exp
.X_add_number
!= 0,
16198 if (inst
.operands
[1].writeback
)
16200 inst
.instruction
|= 0xd;
16203 inst
.instruction
|= 0xf;
16207 inst
.instruction
|= 0xf9000000;
16209 inst
.instruction
|= 0xf4000000;
16214 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16216 NEON_ENCODE (FPV8
, inst
);
16219 do_vfp_sp_dyadic ();
16221 do_vfp_dp_rd_rn_rm ();
16224 inst
.instruction
|= 0x100;
16226 inst
.instruction
|= 0xf0000000;
16232 set_it_insn_type (OUTSIDE_IT_INSN
);
16234 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16235 first_error (_("invalid instruction shape"));
16241 set_it_insn_type (OUTSIDE_IT_INSN
);
16243 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16246 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16249 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16253 do_vrint_1 (enum neon_cvt_mode mode
)
16255 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16256 struct neon_type_el et
;
16261 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16262 if (et
.type
!= NT_invtype
)
16264 /* VFP encodings. */
16265 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16266 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16267 set_it_insn_type (OUTSIDE_IT_INSN
);
16269 NEON_ENCODE (FPV8
, inst
);
16271 do_vfp_sp_monadic ();
16273 do_vfp_dp_rd_rm ();
16277 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16278 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16279 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16280 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16281 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16282 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16283 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16287 inst
.instruction
|= (rs
== NS_DD
) << 8;
16288 do_vfp_cond_or_thumb ();
16292 /* Neon encodings (or something broken...). */
16294 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16296 if (et
.type
== NT_invtype
)
16299 set_it_insn_type (OUTSIDE_IT_INSN
);
16300 NEON_ENCODE (FLOAT
, inst
);
16302 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16305 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16307 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16308 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16309 inst
.instruction
|= neon_quad (rs
) << 6;
16312 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16313 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16314 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16315 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16316 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16317 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16318 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16323 inst
.instruction
|= 0xfc000000;
16325 inst
.instruction
|= 0xf0000000;
16332 do_vrint_1 (neon_cvt_mode_x
);
16338 do_vrint_1 (neon_cvt_mode_z
);
16344 do_vrint_1 (neon_cvt_mode_r
);
16350 do_vrint_1 (neon_cvt_mode_a
);
16356 do_vrint_1 (neon_cvt_mode_n
);
16362 do_vrint_1 (neon_cvt_mode_p
);
16368 do_vrint_1 (neon_cvt_mode_m
);
16371 /* Crypto v1 instructions. */
16373 do_crypto_2op_1 (unsigned elttype
, int op
)
16375 set_it_insn_type (OUTSIDE_IT_INSN
);
16377 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16383 NEON_ENCODE (INTEGER
, inst
);
16384 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16385 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16386 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16387 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16389 inst
.instruction
|= op
<< 6;
16392 inst
.instruction
|= 0xfc000000;
16394 inst
.instruction
|= 0xf0000000;
16398 do_crypto_3op_1 (int u
, int op
)
16400 set_it_insn_type (OUTSIDE_IT_INSN
);
16402 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16403 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16408 NEON_ENCODE (INTEGER
, inst
);
16409 neon_three_same (1, u
, 8 << op
);
16415 do_crypto_2op_1 (N_8
, 0);
16421 do_crypto_2op_1 (N_8
, 1);
16427 do_crypto_2op_1 (N_8
, 2);
16433 do_crypto_2op_1 (N_8
, 3);
16439 do_crypto_3op_1 (0, 0);
16445 do_crypto_3op_1 (0, 1);
16451 do_crypto_3op_1 (0, 2);
16457 do_crypto_3op_1 (0, 3);
16463 do_crypto_3op_1 (1, 0);
16469 do_crypto_3op_1 (1, 1);
16473 do_sha256su1 (void)
16475 do_crypto_3op_1 (1, 2);
16481 do_crypto_2op_1 (N_32
, -1);
16487 do_crypto_2op_1 (N_32
, 0);
16491 do_sha256su0 (void)
16493 do_crypto_2op_1 (N_32
, 1);
16497 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16499 unsigned int Rd
= inst
.operands
[0].reg
;
16500 unsigned int Rn
= inst
.operands
[1].reg
;
16501 unsigned int Rm
= inst
.operands
[2].reg
;
16503 set_it_insn_type (OUTSIDE_IT_INSN
);
16504 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16505 inst
.instruction
|= LOW4 (Rn
) << 16;
16506 inst
.instruction
|= LOW4 (Rm
);
16507 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16508 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16510 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16511 as_warn (UNPRED_REG ("r15"));
16512 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16513 as_warn (UNPRED_REG ("r13"));
16553 /* Overall per-instruction processing. */
16555 /* We need to be able to fix up arbitrary expressions in some statements.
16556 This is so that we can handle symbols that are an arbitrary distance from
16557 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16558 which returns part of an address in a form which will be valid for
16559 a data instruction. We do this by pushing the expression into a symbol
16560 in the expr_section, and creating a fix for that. */
16563 fix_new_arm (fragS
* frag
,
16577 /* Create an absolute valued symbol, so we have something to
16578 refer to in the object file. Unfortunately for us, gas's
16579 generic expression parsing will already have folded out
16580 any use of .set foo/.type foo %function that may have
16581 been used to set type information of the target location,
16582 that's being specified symbolically. We have to presume
16583 the user knows what they are doing. */
16587 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16589 symbol
= symbol_find_or_make (name
);
16590 S_SET_SEGMENT (symbol
, absolute_section
);
16591 symbol_set_frag (symbol
, &zero_address_frag
);
16592 S_SET_VALUE (symbol
, exp
->X_add_number
);
16593 exp
->X_op
= O_symbol
;
16594 exp
->X_add_symbol
= symbol
;
16595 exp
->X_add_number
= 0;
16601 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16602 (enum bfd_reloc_code_real
) reloc
);
16606 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16607 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16611 /* Mark whether the fix is to a THUMB instruction, or an ARM
16613 new_fix
->tc_fix_data
= thumb_mode
;
16616 /* Create a frg for an instruction requiring relaxation. */
16618 output_relax_insn (void)
16624 /* The size of the instruction is unknown, so tie the debug info to the
16625 start of the instruction. */
16626 dwarf2_emit_insn (0);
16628 switch (inst
.reloc
.exp
.X_op
)
16631 sym
= inst
.reloc
.exp
.X_add_symbol
;
16632 offset
= inst
.reloc
.exp
.X_add_number
;
16636 offset
= inst
.reloc
.exp
.X_add_number
;
16639 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16643 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16644 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16645 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16648 /* Write a 32-bit thumb instruction to buf. */
16650 put_thumb32_insn (char * buf
, unsigned long insn
)
16652 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16653 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16657 output_inst (const char * str
)
16663 as_bad ("%s -- `%s'", inst
.error
, str
);
16668 output_relax_insn ();
16671 if (inst
.size
== 0)
16674 to
= frag_more (inst
.size
);
16675 /* PR 9814: Record the thumb mode into the current frag so that we know
16676 what type of NOP padding to use, if necessary. We override any previous
16677 setting so that if the mode has changed then the NOPS that we use will
16678 match the encoding of the last instruction in the frag. */
16679 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16681 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16683 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16684 put_thumb32_insn (to
, inst
.instruction
);
16686 else if (inst
.size
> INSN_SIZE
)
16688 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16689 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16690 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16693 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16695 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16696 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16697 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16700 dwarf2_emit_insn (inst
.size
);
16704 output_it_inst (int cond
, int mask
, char * to
)
16706 unsigned long instruction
= 0xbf00;
16709 instruction
|= mask
;
16710 instruction
|= cond
<< 4;
16714 to
= frag_more (2);
16716 dwarf2_emit_insn (2);
16720 md_number_to_chars (to
, instruction
, 2);
16725 /* Tag values used in struct asm_opcode's tag field. */
16728 OT_unconditional
, /* Instruction cannot be conditionalized.
16729 The ARM condition field is still 0xE. */
16730 OT_unconditionalF
, /* Instruction cannot be conditionalized
16731 and carries 0xF in its ARM condition field. */
16732 OT_csuffix
, /* Instruction takes a conditional suffix. */
16733 OT_csuffixF
, /* Some forms of the instruction take a conditional
16734 suffix, others place 0xF where the condition field
16736 OT_cinfix3
, /* Instruction takes a conditional infix,
16737 beginning at character index 3. (In
16738 unified mode, it becomes a suffix.) */
16739 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
16740 tsts, cmps, cmns, and teqs. */
16741 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
16742 character index 3, even in unified mode. Used for
16743 legacy instructions where suffix and infix forms
16744 may be ambiguous. */
16745 OT_csuf_or_in3
, /* Instruction takes either a conditional
16746 suffix or an infix at character index 3. */
16747 OT_odd_infix_unc
, /* This is the unconditional variant of an
16748 instruction that takes a conditional infix
16749 at an unusual position. In unified mode,
16750 this variant will accept a suffix. */
16751 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
16752 are the conditional variants of instructions that
16753 take conditional infixes in unusual positions.
16754 The infix appears at character index
16755 (tag - OT_odd_infix_0). These are not accepted
16756 in unified mode. */
16759 /* Subroutine of md_assemble, responsible for looking up the primary
16760 opcode from the mnemonic the user wrote. STR points to the
16761 beginning of the mnemonic.
16763 This is not simply a hash table lookup, because of conditional
16764 variants. Most instructions have conditional variants, which are
16765 expressed with a _conditional affix_ to the mnemonic. If we were
16766 to encode each conditional variant as a literal string in the opcode
16767 table, it would have approximately 20,000 entries.
16769 Most mnemonics take this affix as a suffix, and in unified syntax,
16770 'most' is upgraded to 'all'. However, in the divided syntax, some
16771 instructions take the affix as an infix, notably the s-variants of
16772 the arithmetic instructions. Of those instructions, all but six
16773 have the infix appear after the third character of the mnemonic.
16775 Accordingly, the algorithm for looking up primary opcodes given
16778 1. Look up the identifier in the opcode table.
16779 If we find a match, go to step U.
16781 2. Look up the last two characters of the identifier in the
16782 conditions table. If we find a match, look up the first N-2
16783 characters of the identifier in the opcode table. If we
16784 find a match, go to step CE.
16786 3. Look up the fourth and fifth characters of the identifier in
16787 the conditions table. If we find a match, extract those
16788 characters from the identifier, and look up the remaining
16789 characters in the opcode table. If we find a match, go
16794 U. Examine the tag field of the opcode structure, in case this is
16795 one of the six instructions with its conditional infix in an
16796 unusual place. If it is, the tag tells us where to find the
16797 infix; look it up in the conditions table and set inst.cond
16798 accordingly. Otherwise, this is an unconditional instruction.
16799 Again set inst.cond accordingly. Return the opcode structure.
16801 CE. Examine the tag field to make sure this is an instruction that
16802 should receive a conditional suffix. If it is not, fail.
16803 Otherwise, set inst.cond from the suffix we already looked up,
16804 and return the opcode structure.
16806 CM. Examine the tag field to make sure this is an instruction that
16807 should receive a conditional infix after the third character.
16808 If it is not, fail. Otherwise, undo the edits to the current
16809 line of input and proceed as for case CE. */
16811 static const struct asm_opcode
*
16812 opcode_lookup (char **str
)
16816 const struct asm_opcode
*opcode
;
16817 const struct asm_cond
*cond
;
16820 /* Scan up to the end of the mnemonic, which must end in white space,
16821 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16822 for (base
= end
= *str
; *end
!= '\0'; end
++)
16823 if (*end
== ' ' || *end
== '.')
16829 /* Handle a possible width suffix and/or Neon type suffix. */
16834 /* The .w and .n suffixes are only valid if the unified syntax is in
16836 if (unified_syntax
&& end
[1] == 'w')
16838 else if (unified_syntax
&& end
[1] == 'n')
16843 inst
.vectype
.elems
= 0;
16845 *str
= end
+ offset
;
16847 if (end
[offset
] == '.')
16849 /* See if we have a Neon type suffix (possible in either unified or
16850 non-unified ARM syntax mode). */
16851 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
16854 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
16860 /* Look for unaffixed or special-case affixed mnemonic. */
16861 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16866 if (opcode
->tag
< OT_odd_infix_0
)
16868 inst
.cond
= COND_ALWAYS
;
16872 if (warn_on_deprecated
&& unified_syntax
)
16873 as_warn (_("conditional infixes are deprecated in unified syntax"));
16874 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
16875 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16878 inst
.cond
= cond
->value
;
16882 /* Cannot have a conditional suffix on a mnemonic of less than two
16884 if (end
- base
< 3)
16887 /* Look for suffixed mnemonic. */
16889 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16890 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16892 if (opcode
&& cond
)
16895 switch (opcode
->tag
)
16897 case OT_cinfix3_legacy
:
16898 /* Ignore conditional suffixes matched on infix only mnemonics. */
16902 case OT_cinfix3_deprecated
:
16903 case OT_odd_infix_unc
:
16904 if (!unified_syntax
)
16906 /* else fall through */
16910 case OT_csuf_or_in3
:
16911 inst
.cond
= cond
->value
;
16914 case OT_unconditional
:
16915 case OT_unconditionalF
:
16917 inst
.cond
= cond
->value
;
16920 /* Delayed diagnostic. */
16921 inst
.error
= BAD_COND
;
16922 inst
.cond
= COND_ALWAYS
;
16931 /* Cannot have a usual-position infix on a mnemonic of less than
16932 six characters (five would be a suffix). */
16933 if (end
- base
< 6)
16936 /* Look for infixed mnemonic in the usual position. */
16938 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16942 memcpy (save
, affix
, 2);
16943 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
16944 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16946 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
16947 memcpy (affix
, save
, 2);
16950 && (opcode
->tag
== OT_cinfix3
16951 || opcode
->tag
== OT_cinfix3_deprecated
16952 || opcode
->tag
== OT_csuf_or_in3
16953 || opcode
->tag
== OT_cinfix3_legacy
))
16956 if (warn_on_deprecated
&& unified_syntax
16957 && (opcode
->tag
== OT_cinfix3
16958 || opcode
->tag
== OT_cinfix3_deprecated
))
16959 as_warn (_("conditional infixes are deprecated in unified syntax"));
16961 inst
.cond
= cond
->value
;
16968 /* This function generates an initial IT instruction, leaving its block
16969 virtually open for the new instructions. Eventually,
16970 the mask will be updated by now_it_add_mask () each time
16971 a new instruction needs to be included in the IT block.
16972 Finally, the block is closed with close_automatic_it_block ().
16973 The block closure can be requested either from md_assemble (),
16974 a tencode (), or due to a label hook. */
16977 new_automatic_it_block (int cond
)
16979 now_it
.state
= AUTOMATIC_IT_BLOCK
;
16980 now_it
.mask
= 0x18;
16982 now_it
.block_length
= 1;
16983 mapping_state (MAP_THUMB
);
16984 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
16985 now_it
.warn_deprecated
= FALSE
;
16986 now_it
.insn_cond
= TRUE
;
16989 /* Close an automatic IT block.
16990 See comments in new_automatic_it_block (). */
16993 close_automatic_it_block (void)
16995 now_it
.mask
= 0x10;
16996 now_it
.block_length
= 0;
16999 /* Update the mask of the current automatically-generated IT
17000 instruction. See comments in new_automatic_it_block (). */
17003 now_it_add_mask (int cond
)
17005 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17006 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17007 | ((bitvalue) << (nbit)))
17008 const int resulting_bit
= (cond
& 1);
17010 now_it
.mask
&= 0xf;
17011 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17013 (5 - now_it
.block_length
));
17014 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17016 ((5 - now_it
.block_length
) - 1) );
17017 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17020 #undef SET_BIT_VALUE
17023 /* The IT blocks handling machinery is accessed through the these functions:
17024 it_fsm_pre_encode () from md_assemble ()
17025 set_it_insn_type () optional, from the tencode functions
17026 set_it_insn_type_last () ditto
17027 in_it_block () ditto
17028 it_fsm_post_encode () from md_assemble ()
17029 force_automatic_it_block_close () from label habdling functions
17032 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17033 initializing the IT insn type with a generic initial value depending
17034 on the inst.condition.
17035 2) During the tencode function, two things may happen:
17036 a) The tencode function overrides the IT insn type by
17037 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17038 b) The tencode function queries the IT block state by
17039 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17041 Both set_it_insn_type and in_it_block run the internal FSM state
17042 handling function (handle_it_state), because: a) setting the IT insn
17043 type may incur in an invalid state (exiting the function),
17044 and b) querying the state requires the FSM to be updated.
17045 Specifically we want to avoid creating an IT block for conditional
17046 branches, so it_fsm_pre_encode is actually a guess and we can't
17047 determine whether an IT block is required until the tencode () routine
17048 has decided what type of instruction this actually it.
17049 Because of this, if set_it_insn_type and in_it_block have to be used,
17050 set_it_insn_type has to be called first.
17052 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17053 determines the insn IT type depending on the inst.cond code.
17054 When a tencode () routine encodes an instruction that can be
17055 either outside an IT block, or, in the case of being inside, has to be
17056 the last one, set_it_insn_type_last () will determine the proper
17057 IT instruction type based on the inst.cond code. Otherwise,
17058 set_it_insn_type can be called for overriding that logic or
17059 for covering other cases.
17061 Calling handle_it_state () may not transition the IT block state to
17062 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17063 still queried. Instead, if the FSM determines that the state should
17064 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17065 after the tencode () function: that's what it_fsm_post_encode () does.
17067 Since in_it_block () calls the state handling function to get an
17068 updated state, an error may occur (due to invalid insns combination).
17069 In that case, inst.error is set.
17070 Therefore, inst.error has to be checked after the execution of
17071 the tencode () routine.
17073 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17074 any pending state change (if any) that didn't take place in
17075 handle_it_state () as explained above. */
17078 it_fsm_pre_encode (void)
17080 if (inst
.cond
!= COND_ALWAYS
)
17081 inst
.it_insn_type
= INSIDE_IT_INSN
;
17083 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17085 now_it
.state_handled
= 0;
17088 /* IT state FSM handling function. */
17091 handle_it_state (void)
17093 now_it
.state_handled
= 1;
17094 now_it
.insn_cond
= FALSE
;
17096 switch (now_it
.state
)
17098 case OUTSIDE_IT_BLOCK
:
17099 switch (inst
.it_insn_type
)
17101 case OUTSIDE_IT_INSN
:
17104 case INSIDE_IT_INSN
:
17105 case INSIDE_IT_LAST_INSN
:
17106 if (thumb_mode
== 0)
17109 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17110 as_tsktsk (_("Warning: conditional outside an IT block"\
17115 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17116 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17118 /* Automatically generate the IT instruction. */
17119 new_automatic_it_block (inst
.cond
);
17120 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17121 close_automatic_it_block ();
17125 inst
.error
= BAD_OUT_IT
;
17131 case IF_INSIDE_IT_LAST_INSN
:
17132 case NEUTRAL_IT_INSN
:
17136 now_it
.state
= MANUAL_IT_BLOCK
;
17137 now_it
.block_length
= 0;
17142 case AUTOMATIC_IT_BLOCK
:
17143 /* Three things may happen now:
17144 a) We should increment current it block size;
17145 b) We should close current it block (closing insn or 4 insns);
17146 c) We should close current it block and start a new one (due
17147 to incompatible conditions or
17148 4 insns-length block reached). */
17150 switch (inst
.it_insn_type
)
17152 case OUTSIDE_IT_INSN
:
17153 /* The closure of the block shall happen immediatelly,
17154 so any in_it_block () call reports the block as closed. */
17155 force_automatic_it_block_close ();
17158 case INSIDE_IT_INSN
:
17159 case INSIDE_IT_LAST_INSN
:
17160 case IF_INSIDE_IT_LAST_INSN
:
17161 now_it
.block_length
++;
17163 if (now_it
.block_length
> 4
17164 || !now_it_compatible (inst
.cond
))
17166 force_automatic_it_block_close ();
17167 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17168 new_automatic_it_block (inst
.cond
);
17172 now_it
.insn_cond
= TRUE
;
17173 now_it_add_mask (inst
.cond
);
17176 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17177 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17178 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17179 close_automatic_it_block ();
17182 case NEUTRAL_IT_INSN
:
17183 now_it
.block_length
++;
17184 now_it
.insn_cond
= TRUE
;
17186 if (now_it
.block_length
> 4)
17187 force_automatic_it_block_close ();
17189 now_it_add_mask (now_it
.cc
& 1);
17193 close_automatic_it_block ();
17194 now_it
.state
= MANUAL_IT_BLOCK
;
17199 case MANUAL_IT_BLOCK
:
17201 /* Check conditional suffixes. */
17202 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17205 now_it
.mask
&= 0x1f;
17206 is_last
= (now_it
.mask
== 0x10);
17207 now_it
.insn_cond
= TRUE
;
17209 switch (inst
.it_insn_type
)
17211 case OUTSIDE_IT_INSN
:
17212 inst
.error
= BAD_NOT_IT
;
17215 case INSIDE_IT_INSN
:
17216 if (cond
!= inst
.cond
)
17218 inst
.error
= BAD_IT_COND
;
17223 case INSIDE_IT_LAST_INSN
:
17224 case IF_INSIDE_IT_LAST_INSN
:
17225 if (cond
!= inst
.cond
)
17227 inst
.error
= BAD_IT_COND
;
17232 inst
.error
= BAD_BRANCH
;
17237 case NEUTRAL_IT_INSN
:
17238 /* The BKPT instruction is unconditional even in an IT block. */
17242 inst
.error
= BAD_IT_IT
;
17252 struct depr_insn_mask
17254 unsigned long pattern
;
17255 unsigned long mask
;
17256 const char* description
;
17259 /* List of 16-bit instruction patterns deprecated in an IT block in
17261 static const struct depr_insn_mask depr_it_insns
[] = {
17262 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17263 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17264 { 0xa000, 0xb800, N_("ADR") },
17265 { 0x4800, 0xf800, N_("Literal loads") },
17266 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17267 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17272 it_fsm_post_encode (void)
17276 if (!now_it
.state_handled
)
17277 handle_it_state ();
17279 if (now_it
.insn_cond
17280 && !now_it
.warn_deprecated
17281 && warn_on_deprecated
17282 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17284 if (inst
.instruction
>= 0x10000)
17286 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17287 "deprecated in ARMv8"));
17288 now_it
.warn_deprecated
= TRUE
;
17292 const struct depr_insn_mask
*p
= depr_it_insns
;
17294 while (p
->mask
!= 0)
17296 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17298 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17299 "of the following class are deprecated in ARMv8: "
17300 "%s"), p
->description
);
17301 now_it
.warn_deprecated
= TRUE
;
17309 if (now_it
.block_length
> 1)
17311 as_warn (_("IT blocks containing more than one conditional "
17312 "instruction are deprecated in ARMv8"));
17313 now_it
.warn_deprecated
= TRUE
;
17317 is_last
= (now_it
.mask
== 0x10);
17320 now_it
.state
= OUTSIDE_IT_BLOCK
;
17326 force_automatic_it_block_close (void)
17328 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17330 close_automatic_it_block ();
17331 now_it
.state
= OUTSIDE_IT_BLOCK
;
17339 if (!now_it
.state_handled
)
17340 handle_it_state ();
17342 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17346 md_assemble (char *str
)
17349 const struct asm_opcode
* opcode
;
17351 /* Align the previous label if needed. */
17352 if (last_label_seen
!= NULL
)
17354 symbol_set_frag (last_label_seen
, frag_now
);
17355 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17356 S_SET_SEGMENT (last_label_seen
, now_seg
);
17359 memset (&inst
, '\0', sizeof (inst
));
17360 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17362 opcode
= opcode_lookup (&p
);
17365 /* It wasn't an instruction, but it might be a register alias of
17366 the form alias .req reg, or a Neon .dn/.qn directive. */
17367 if (! create_register_alias (str
, p
)
17368 && ! create_neon_reg_alias (str
, p
))
17369 as_bad (_("bad instruction `%s'"), str
);
17374 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17375 as_warn (_("s suffix on comparison instruction is deprecated"));
17377 /* The value which unconditional instructions should have in place of the
17378 condition field. */
17379 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17383 arm_feature_set variant
;
17385 variant
= cpu_variant
;
17386 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17387 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17388 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17389 /* Check that this instruction is supported for this CPU. */
17390 if (!opcode
->tvariant
17391 || (thumb_mode
== 1
17392 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17394 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17397 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17398 && opcode
->tencode
!= do_t_branch
)
17400 as_bad (_("Thumb does not support conditional execution"));
17404 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17406 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17407 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17408 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17410 /* Two things are addressed here.
17411 1) Implicit require narrow instructions on Thumb-1.
17412 This avoids relaxation accidentally introducing Thumb-2
17414 2) Reject wide instructions in non Thumb-2 cores. */
17415 if (inst
.size_req
== 0)
17417 else if (inst
.size_req
== 4)
17419 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17425 inst
.instruction
= opcode
->tvalue
;
17427 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17429 /* Prepare the it_insn_type for those encodings that don't set
17431 it_fsm_pre_encode ();
17433 opcode
->tencode ();
17435 it_fsm_post_encode ();
17438 if (!(inst
.error
|| inst
.relax
))
17440 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17441 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17442 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17444 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17449 /* Something has gone badly wrong if we try to relax a fixed size
17451 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17453 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17454 *opcode
->tvariant
);
17455 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17456 set those bits when Thumb-2 32-bit instructions are seen. ie.
17457 anything other than bl/blx and v6-M instructions.
17458 This is overly pessimistic for relaxable instructions. */
17459 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17461 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17462 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17463 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17466 check_neon_suffixes
;
17470 mapping_state (MAP_THUMB
);
17473 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17477 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17478 is_bx
= (opcode
->aencode
== do_bx
);
17480 /* Check that this instruction is supported for this CPU. */
17481 if (!(is_bx
&& fix_v4bx
)
17482 && !(opcode
->avariant
&&
17483 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17485 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17490 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17494 inst
.instruction
= opcode
->avalue
;
17495 if (opcode
->tag
== OT_unconditionalF
)
17496 inst
.instruction
|= 0xF << 28;
17498 inst
.instruction
|= inst
.cond
<< 28;
17499 inst
.size
= INSN_SIZE
;
17500 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17502 it_fsm_pre_encode ();
17503 opcode
->aencode ();
17504 it_fsm_post_encode ();
17506 /* Arm mode bx is marked as both v4T and v5 because it's still required
17507 on a hypothetical non-thumb v5 core. */
17509 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17511 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17512 *opcode
->avariant
);
17514 check_neon_suffixes
;
17518 mapping_state (MAP_ARM
);
17523 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17531 check_it_blocks_finished (void)
17536 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17537 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17538 == MANUAL_IT_BLOCK
)
17540 as_warn (_("section '%s' finished with an open IT block."),
17544 if (now_it
.state
== MANUAL_IT_BLOCK
)
17545 as_warn (_("file finished with an open IT block."));
17549 /* Various frobbings of labels and their addresses. */
17552 arm_start_line_hook (void)
17554 last_label_seen
= NULL
;
17558 arm_frob_label (symbolS
* sym
)
17560 last_label_seen
= sym
;
17562 ARM_SET_THUMB (sym
, thumb_mode
);
17564 #if defined OBJ_COFF || defined OBJ_ELF
17565 ARM_SET_INTERWORK (sym
, support_interwork
);
17568 force_automatic_it_block_close ();
17570 /* Note - do not allow local symbols (.Lxxx) to be labelled
17571 as Thumb functions. This is because these labels, whilst
17572 they exist inside Thumb code, are not the entry points for
17573 possible ARM->Thumb calls. Also, these labels can be used
17574 as part of a computed goto or switch statement. eg gcc
17575 can generate code that looks like this:
17577 ldr r2, [pc, .Laaa]
17587 The first instruction loads the address of the jump table.
17588 The second instruction converts a table index into a byte offset.
17589 The third instruction gets the jump address out of the table.
17590 The fourth instruction performs the jump.
17592 If the address stored at .Laaa is that of a symbol which has the
17593 Thumb_Func bit set, then the linker will arrange for this address
17594 to have the bottom bit set, which in turn would mean that the
17595 address computation performed by the third instruction would end
17596 up with the bottom bit set. Since the ARM is capable of unaligned
17597 word loads, the instruction would then load the incorrect address
17598 out of the jump table, and chaos would ensue. */
17599 if (label_is_thumb_function_name
17600 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17601 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17603 /* When the address of a Thumb function is taken the bottom
17604 bit of that address should be set. This will allow
17605 interworking between Arm and Thumb functions to work
17608 THUMB_SET_FUNC (sym
, 1);
17610 label_is_thumb_function_name
= FALSE
;
17613 dwarf2_emit_label (sym
);
17617 arm_data_in_code (void)
17619 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17621 *input_line_pointer
= '/';
17622 input_line_pointer
+= 5;
17623 *input_line_pointer
= 0;
17631 arm_canonicalize_symbol_name (char * name
)
17635 if (thumb_mode
&& (len
= strlen (name
)) > 5
17636 && streq (name
+ len
- 5, "/data"))
17637 *(name
+ len
- 5) = 0;
17642 /* Table of all register names defined by default. The user can
17643 define additional names with .req. Note that all register names
17644 should appear in both upper and lowercase variants. Some registers
17645 also have mixed-case names. */
17647 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17648 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17649 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17650 #define REGSET(p,t) \
17651 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17652 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17653 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17654 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17655 #define REGSETH(p,t) \
17656 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17657 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17658 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17659 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17660 #define REGSET2(p,t) \
17661 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17662 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17663 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17664 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17665 #define SPLRBANK(base,bank,t) \
17666 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17667 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17668 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17669 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17670 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17671 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17673 static const struct reg_entry reg_names
[] =
17675 /* ARM integer registers. */
17676 REGSET(r
, RN
), REGSET(R
, RN
),
17678 /* ATPCS synonyms. */
17679 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17680 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17681 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17683 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17684 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17685 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17687 /* Well-known aliases. */
17688 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17689 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17691 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17692 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17694 /* Coprocessor numbers. */
17695 REGSET(p
, CP
), REGSET(P
, CP
),
17697 /* Coprocessor register numbers. The "cr" variants are for backward
17699 REGSET(c
, CN
), REGSET(C
, CN
),
17700 REGSET(cr
, CN
), REGSET(CR
, CN
),
17702 /* ARM banked registers. */
17703 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
17704 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
17705 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
17706 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
17707 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
17708 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
17709 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
17711 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
17712 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
17713 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
17714 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
17715 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
17716 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
17717 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
17718 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
17720 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
17721 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
17722 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
17723 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
17724 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
17725 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
17726 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
17727 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17728 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17730 /* FPA registers. */
17731 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
17732 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
17734 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
17735 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
17737 /* VFP SP registers. */
17738 REGSET(s
,VFS
), REGSET(S
,VFS
),
17739 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
17741 /* VFP DP Registers. */
17742 REGSET(d
,VFD
), REGSET(D
,VFD
),
17743 /* Extra Neon DP registers. */
17744 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
17746 /* Neon QP registers. */
17747 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
17749 /* VFP control registers. */
17750 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
17751 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
17752 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
17753 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
17754 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
17755 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
17757 /* Maverick DSP coprocessor registers. */
17758 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
17759 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
17761 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
17762 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
17763 REGDEF(dspsc
,0,DSPSC
),
17765 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
17766 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
17767 REGDEF(DSPSC
,0,DSPSC
),
17769 /* iWMMXt data registers - p0, c0-15. */
17770 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
17772 /* iWMMXt control registers - p1, c0-3. */
17773 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
17774 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
17775 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
17776 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
17778 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17779 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
17780 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
17781 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
17782 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
17784 /* XScale accumulator registers. */
17785 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
17791 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17792 within psr_required_here. */
17793 static const struct asm_psr psrs
[] =
17795 /* Backward compatibility notation. Note that "all" is no longer
17796 truly all possible PSR bits. */
17797 {"all", PSR_c
| PSR_f
},
17801 /* Individual flags. */
17807 /* Combinations of flags. */
17808 {"fs", PSR_f
| PSR_s
},
17809 {"fx", PSR_f
| PSR_x
},
17810 {"fc", PSR_f
| PSR_c
},
17811 {"sf", PSR_s
| PSR_f
},
17812 {"sx", PSR_s
| PSR_x
},
17813 {"sc", PSR_s
| PSR_c
},
17814 {"xf", PSR_x
| PSR_f
},
17815 {"xs", PSR_x
| PSR_s
},
17816 {"xc", PSR_x
| PSR_c
},
17817 {"cf", PSR_c
| PSR_f
},
17818 {"cs", PSR_c
| PSR_s
},
17819 {"cx", PSR_c
| PSR_x
},
17820 {"fsx", PSR_f
| PSR_s
| PSR_x
},
17821 {"fsc", PSR_f
| PSR_s
| PSR_c
},
17822 {"fxs", PSR_f
| PSR_x
| PSR_s
},
17823 {"fxc", PSR_f
| PSR_x
| PSR_c
},
17824 {"fcs", PSR_f
| PSR_c
| PSR_s
},
17825 {"fcx", PSR_f
| PSR_c
| PSR_x
},
17826 {"sfx", PSR_s
| PSR_f
| PSR_x
},
17827 {"sfc", PSR_s
| PSR_f
| PSR_c
},
17828 {"sxf", PSR_s
| PSR_x
| PSR_f
},
17829 {"sxc", PSR_s
| PSR_x
| PSR_c
},
17830 {"scf", PSR_s
| PSR_c
| PSR_f
},
17831 {"scx", PSR_s
| PSR_c
| PSR_x
},
17832 {"xfs", PSR_x
| PSR_f
| PSR_s
},
17833 {"xfc", PSR_x
| PSR_f
| PSR_c
},
17834 {"xsf", PSR_x
| PSR_s
| PSR_f
},
17835 {"xsc", PSR_x
| PSR_s
| PSR_c
},
17836 {"xcf", PSR_x
| PSR_c
| PSR_f
},
17837 {"xcs", PSR_x
| PSR_c
| PSR_s
},
17838 {"cfs", PSR_c
| PSR_f
| PSR_s
},
17839 {"cfx", PSR_c
| PSR_f
| PSR_x
},
17840 {"csf", PSR_c
| PSR_s
| PSR_f
},
17841 {"csx", PSR_c
| PSR_s
| PSR_x
},
17842 {"cxf", PSR_c
| PSR_x
| PSR_f
},
17843 {"cxs", PSR_c
| PSR_x
| PSR_s
},
17844 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
17845 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
17846 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
17847 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
17848 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
17849 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
17850 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
17851 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
17852 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
17853 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
17854 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
17855 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
17856 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
17857 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
17858 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
17859 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
17860 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
17861 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
17862 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
17863 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
17864 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
17865 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
17866 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
17867 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
17870 /* Table of V7M psr names. */
17871 static const struct asm_psr v7m_psrs
[] =
17873 {"apsr", 0 }, {"APSR", 0 },
17874 {"iapsr", 1 }, {"IAPSR", 1 },
17875 {"eapsr", 2 }, {"EAPSR", 2 },
17876 {"psr", 3 }, {"PSR", 3 },
17877 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17878 {"ipsr", 5 }, {"IPSR", 5 },
17879 {"epsr", 6 }, {"EPSR", 6 },
17880 {"iepsr", 7 }, {"IEPSR", 7 },
17881 {"msp", 8 }, {"MSP", 8 },
17882 {"psp", 9 }, {"PSP", 9 },
17883 {"primask", 16}, {"PRIMASK", 16},
17884 {"basepri", 17}, {"BASEPRI", 17},
17885 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17886 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17887 {"faultmask", 19}, {"FAULTMASK", 19},
17888 {"control", 20}, {"CONTROL", 20}
17891 /* Table of all shift-in-operand names. */
17892 static const struct asm_shift_name shift_names
[] =
17894 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
17895 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
17896 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
17897 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
17898 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
17899 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
17902 /* Table of all explicit relocation names. */
17904 static struct reloc_entry reloc_names
[] =
17906 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
17907 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
17908 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
17909 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
17910 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
17911 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
17912 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
17913 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
17914 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
17915 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
17916 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
17917 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
17918 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
17919 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
17920 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
17921 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
17922 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
17923 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
17927 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17928 static const struct asm_cond conds
[] =
17932 {"cs", 0x2}, {"hs", 0x2},
17933 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17947 #define UL_BARRIER(L,U,CODE,FEAT) \
17948 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17949 { U, CODE, ARM_FEATURE (FEAT, 0) }
17951 static struct asm_barrier_opt barrier_opt_names
[] =
17953 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
17954 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
17955 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
17956 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
17957 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
17958 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
17959 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
17960 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
17961 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
17962 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
17963 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
17964 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
17965 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
17966 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
17967 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
17968 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
17973 /* Table of ARM-format instructions. */
17975 /* Macros for gluing together operand strings. N.B. In all cases
17976 other than OPS0, the trailing OP_stop comes from default
17977 zero-initialization of the unspecified elements of the array. */
17978 #define OPS0() { OP_stop, }
17979 #define OPS1(a) { OP_##a, }
17980 #define OPS2(a,b) { OP_##a,OP_##b, }
17981 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17982 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17983 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17984 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17986 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17987 This is useful when mixing operands for ARM and THUMB, i.e. using the
17988 MIX_ARM_THUMB_OPERANDS macro.
17989 In order to use these macros, prefix the number of operands with _
17991 #define OPS_1(a) { a, }
17992 #define OPS_2(a,b) { a,b, }
17993 #define OPS_3(a,b,c) { a,b,c, }
17994 #define OPS_4(a,b,c,d) { a,b,c,d, }
17995 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17996 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17998 /* These macros abstract out the exact format of the mnemonic table and
17999 save some repeated characters. */
18001 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18002 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18003 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18004 THUMB_VARIANT, do_##ae, do_##te }
18006 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18007 a T_MNEM_xyz enumerator. */
18008 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18009 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18010 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18011 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18013 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18014 infix after the third character. */
18015 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18016 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18017 THUMB_VARIANT, do_##ae, do_##te }
18018 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18019 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18020 THUMB_VARIANT, do_##ae, do_##te }
18021 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18022 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18023 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18024 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18025 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18026 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18027 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18028 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18030 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18031 field is still 0xE. Many of the Thumb variants can be executed
18032 conditionally, so this is checked separately. */
18033 #define TUE(mnem, op, top, nops, ops, ae, te) \
18034 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18035 THUMB_VARIANT, do_##ae, do_##te }
18037 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18038 Used by mnemonics that have very minimal differences in the encoding for
18039 ARM and Thumb variants and can be handled in a common function. */
18040 #define TUEc(mnem, op, top, nops, ops, en) \
18041 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18042 THUMB_VARIANT, do_##en, do_##en }
18044 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18045 condition code field. */
18046 #define TUF(mnem, op, top, nops, ops, ae, te) \
18047 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18048 THUMB_VARIANT, do_##ae, do_##te }
18050 /* ARM-only variants of all the above. */
18051 #define CE(mnem, op, nops, ops, ae) \
18052 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18054 #define C3(mnem, op, nops, ops, ae) \
18055 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18057 /* Legacy mnemonics that always have conditional infix after the third
18059 #define CL(mnem, op, nops, ops, ae) \
18060 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18061 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18063 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18064 #define cCE(mnem, op, nops, ops, ae) \
18065 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18067 /* Legacy coprocessor instructions where conditional infix and conditional
18068 suffix are ambiguous. For consistency this includes all FPA instructions,
18069 not just the potentially ambiguous ones. */
18070 #define cCL(mnem, op, nops, ops, ae) \
18071 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18072 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18074 /* Coprocessor, takes either a suffix or a position-3 infix
18075 (for an FPA corner case). */
18076 #define C3E(mnem, op, nops, ops, ae) \
18077 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18078 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18080 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18081 { m1 #m2 m3, OPS##nops ops, \
18082 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18083 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18085 #define CM(m1, m2, op, nops, ops, ae) \
18086 xCM_ (m1, , m2, op, nops, ops, ae), \
18087 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18088 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18089 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18090 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18091 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18092 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18093 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18094 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18095 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18096 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18097 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18098 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18099 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18100 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18101 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18102 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18103 xCM_ (m1, le, m2, op, nops, ops, ae), \
18104 xCM_ (m1, al, m2, op, nops, ops, ae)
18106 #define UE(mnem, op, nops, ops, ae) \
18107 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18109 #define UF(mnem, op, nops, ops, ae) \
18110 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18112 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18113 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18114 use the same encoding function for each. */
18115 #define NUF(mnem, op, nops, ops, enc) \
18116 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18117 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18119 /* Neon data processing, version which indirects through neon_enc_tab for
18120 the various overloaded versions of opcodes. */
18121 #define nUF(mnem, op, nops, ops, enc) \
18122 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18123 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18125 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18127 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18128 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18129 THUMB_VARIANT, do_##enc, do_##enc }
18131 #define NCE(mnem, op, nops, ops, enc) \
18132 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18134 #define NCEF(mnem, op, nops, ops, enc) \
18135 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18137 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18138 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18139 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18140 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18142 #define nCE(mnem, op, nops, ops, enc) \
18143 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18145 #define nCEF(mnem, op, nops, ops, enc) \
18146 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18150 static const struct asm_opcode insns
[] =
18152 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18153 #define THUMB_VARIANT & arm_ext_v4t
18154 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18155 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18156 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18157 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18158 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18159 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18160 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18161 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18162 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18163 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18164 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18165 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18166 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18167 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18168 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18169 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18171 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18172 for setting PSR flag bits. They are obsolete in V6 and do not
18173 have Thumb equivalents. */
18174 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18175 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18176 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18177 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18178 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18179 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18180 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18181 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18182 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18184 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18185 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18186 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18187 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18189 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18190 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18191 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18193 OP_ADDRGLDR
),ldst
, t_ldst
),
18194 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18196 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18197 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18198 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18199 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18200 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18201 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18203 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18204 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18205 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18206 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18209 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18210 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18211 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18212 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18214 /* Thumb-compatibility pseudo ops. */
18215 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18216 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18217 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18218 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18219 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18220 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18221 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18222 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18223 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18224 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18225 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18226 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18228 /* These may simplify to neg. */
18229 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18230 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18232 #undef THUMB_VARIANT
18233 #define THUMB_VARIANT & arm_ext_v6
18235 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18237 /* V1 instructions with no Thumb analogue prior to V6T2. */
18238 #undef THUMB_VARIANT
18239 #define THUMB_VARIANT & arm_ext_v6t2
18241 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18242 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18243 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18245 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18246 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18247 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18248 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18250 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18251 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18253 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18254 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18256 /* V1 instructions with no Thumb analogue at all. */
18257 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18258 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18260 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18261 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18262 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18263 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18264 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18265 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18266 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18267 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18270 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18271 #undef THUMB_VARIANT
18272 #define THUMB_VARIANT & arm_ext_v4t
18274 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18275 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18277 #undef THUMB_VARIANT
18278 #define THUMB_VARIANT & arm_ext_v6t2
18280 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18281 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18283 /* Generic coprocessor instructions. */
18284 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18285 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18286 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18287 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18288 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18289 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18290 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18293 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18295 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18296 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18299 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18300 #undef THUMB_VARIANT
18301 #define THUMB_VARIANT & arm_ext_msr
18303 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18304 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18307 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18308 #undef THUMB_VARIANT
18309 #define THUMB_VARIANT & arm_ext_v6t2
18311 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18312 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18313 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18314 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18315 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18316 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18317 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18318 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18321 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18322 #undef THUMB_VARIANT
18323 #define THUMB_VARIANT & arm_ext_v4t
18325 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18326 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18327 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18328 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18329 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18330 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18333 #define ARM_VARIANT & arm_ext_v4t_5
18335 /* ARM Architecture 4T. */
18336 /* Note: bx (and blx) are required on V5, even if the processor does
18337 not support Thumb. */
18338 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18341 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18342 #undef THUMB_VARIANT
18343 #define THUMB_VARIANT & arm_ext_v5t
18345 /* Note: blx has 2 variants; the .value coded here is for
18346 BLX(2). Only this variant has conditional execution. */
18347 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18348 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18350 #undef THUMB_VARIANT
18351 #define THUMB_VARIANT & arm_ext_v6t2
18353 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18354 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18355 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18356 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18357 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18358 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18359 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18360 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18363 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18364 #undef THUMB_VARIANT
18365 #define THUMB_VARIANT & arm_ext_v5exp
18367 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18368 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18369 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18370 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18372 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18373 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18375 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18376 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18377 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18378 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18380 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18381 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18382 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18383 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18385 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18386 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18388 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18389 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18390 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18391 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18394 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18395 #undef THUMB_VARIANT
18396 #define THUMB_VARIANT & arm_ext_v6t2
18398 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18399 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18401 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18402 ADDRGLDRS
), ldrd
, t_ldstd
),
18404 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18405 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18408 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18410 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18413 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18414 #undef THUMB_VARIANT
18415 #define THUMB_VARIANT & arm_ext_v6
18417 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18418 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18419 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18420 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18421 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18422 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18423 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18424 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18425 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18426 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18428 #undef THUMB_VARIANT
18429 #define THUMB_VARIANT & arm_ext_v6t2
18431 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18432 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18434 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18435 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18437 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18438 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18440 /* ARM V6 not included in V7M. */
18441 #undef THUMB_VARIANT
18442 #define THUMB_VARIANT & arm_ext_v6_notm
18443 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18444 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18445 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18446 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18447 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18448 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18449 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18450 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18451 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18452 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18453 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18454 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18455 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18456 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18457 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18458 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18459 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18460 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18462 /* ARM V6 not included in V7M (eg. integer SIMD). */
18463 #undef THUMB_VARIANT
18464 #define THUMB_VARIANT & arm_ext_v6_dsp
18465 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18466 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18467 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18468 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18469 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18470 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18471 /* Old name for QASX. */
18472 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18473 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18474 /* Old name for QSAX. */
18475 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18476 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18477 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18478 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18479 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18480 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18481 /* Old name for SASX. */
18482 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18483 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18484 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18485 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18486 /* Old name for SHASX. */
18487 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18488 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18489 /* Old name for SHSAX. */
18490 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18491 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18492 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18493 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18494 /* Old name for SSAX. */
18495 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18496 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18497 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18498 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18499 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18500 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18501 /* Old name for UASX. */
18502 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18503 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18504 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18505 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18506 /* Old name for UHASX. */
18507 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18508 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18509 /* Old name for UHSAX. */
18510 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18511 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18512 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18513 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18514 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18515 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18516 /* Old name for UQASX. */
18517 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18518 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18519 /* Old name for UQSAX. */
18520 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18521 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18522 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18523 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18524 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18525 /* Old name for USAX. */
18526 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18527 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18528 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18529 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18530 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18531 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18532 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18533 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18534 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18535 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18536 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18537 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18538 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18539 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18540 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18541 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18542 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18543 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18544 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18545 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18546 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18547 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18548 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18549 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18550 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18551 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18552 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18553 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18554 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18555 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18556 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18557 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18558 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18559 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18562 #define ARM_VARIANT & arm_ext_v6k
18563 #undef THUMB_VARIANT
18564 #define THUMB_VARIANT & arm_ext_v6k
18566 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18567 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18568 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18569 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18571 #undef THUMB_VARIANT
18572 #define THUMB_VARIANT & arm_ext_v6_notm
18573 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18575 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18576 RRnpcb
), strexd
, t_strexd
),
18578 #undef THUMB_VARIANT
18579 #define THUMB_VARIANT & arm_ext_v6t2
18580 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18582 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18584 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18586 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18588 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18591 #define ARM_VARIANT & arm_ext_sec
18592 #undef THUMB_VARIANT
18593 #define THUMB_VARIANT & arm_ext_sec
18595 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18598 #define ARM_VARIANT & arm_ext_virt
18599 #undef THUMB_VARIANT
18600 #define THUMB_VARIANT & arm_ext_virt
18602 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18603 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18606 #define ARM_VARIANT & arm_ext_v6t2
18607 #undef THUMB_VARIANT
18608 #define THUMB_VARIANT & arm_ext_v6t2
18610 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18611 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18612 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18613 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18615 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18616 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18617 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18618 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18620 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18621 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18622 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18623 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18625 /* Thumb-only instructions. */
18627 #define ARM_VARIANT NULL
18628 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18629 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18631 /* ARM does not really have an IT instruction, so always allow it.
18632 The opcode is copied from Thumb in order to allow warnings in
18633 -mimplicit-it=[never | arm] modes. */
18635 #define ARM_VARIANT & arm_ext_v1
18637 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18638 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18639 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18640 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18641 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18642 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18643 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18644 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18645 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18646 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18647 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18648 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18649 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18650 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18651 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18652 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18653 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18654 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18656 /* Thumb2 only instructions. */
18658 #define ARM_VARIANT NULL
18660 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18661 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18662 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18663 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18664 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18665 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18667 /* Hardware division instructions. */
18669 #define ARM_VARIANT & arm_ext_adiv
18670 #undef THUMB_VARIANT
18671 #define THUMB_VARIANT & arm_ext_div
18673 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18674 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18676 /* ARM V6M/V7 instructions. */
18678 #define ARM_VARIANT & arm_ext_barrier
18679 #undef THUMB_VARIANT
18680 #define THUMB_VARIANT & arm_ext_barrier
18682 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
18683 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
18684 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
18686 /* ARM V7 instructions. */
18688 #define ARM_VARIANT & arm_ext_v7
18689 #undef THUMB_VARIANT
18690 #define THUMB_VARIANT & arm_ext_v7
18692 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
18693 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
18696 #define ARM_VARIANT & arm_ext_mp
18697 #undef THUMB_VARIANT
18698 #define THUMB_VARIANT & arm_ext_mp
18700 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
18702 /* AArchv8 instructions. */
18704 #define ARM_VARIANT & arm_ext_v8
18705 #undef THUMB_VARIANT
18706 #define THUMB_VARIANT & arm_ext_v8
18708 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
18709 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
18710 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18711 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
18713 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
18714 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18715 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18717 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
18719 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18721 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18723 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18724 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18725 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18726 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18727 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18728 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18730 /* ARMv8 T32 only. */
18732 #define ARM_VARIANT NULL
18733 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
18734 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
18735 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
18737 /* FP for ARMv8. */
18739 #define ARM_VARIANT & fpu_vfp_ext_armv8
18740 #undef THUMB_VARIANT
18741 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18743 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18744 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18745 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18746 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18747 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18748 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18749 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
18750 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
18751 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
18752 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
18753 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
18754 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
18755 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
18756 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
18757 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
18758 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
18759 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
18761 /* Crypto v1 extensions. */
18763 #define ARM_VARIANT & fpu_crypto_ext_armv8
18764 #undef THUMB_VARIANT
18765 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18767 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
18768 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
18769 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
18770 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
18771 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
18772 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
18773 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
18774 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
18775 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
18776 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
18777 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
18778 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
18779 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
18780 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
18783 #define ARM_VARIANT & crc_ext_armv8
18784 #undef THUMB_VARIANT
18785 #define THUMB_VARIANT & crc_ext_armv8
18786 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
18787 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
18788 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
18789 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
18790 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
18791 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
18794 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18795 #undef THUMB_VARIANT
18796 #define THUMB_VARIANT NULL
18798 cCE("wfs", e200110
, 1, (RR
), rd
),
18799 cCE("rfs", e300110
, 1, (RR
), rd
),
18800 cCE("wfc", e400110
, 1, (RR
), rd
),
18801 cCE("rfc", e500110
, 1, (RR
), rd
),
18803 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18804 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18805 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18806 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18808 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18809 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18810 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18811 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18813 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
18814 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
18815 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
18816 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
18817 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
18818 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
18819 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
18820 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
18821 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
18822 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
18823 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
18824 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
18826 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
18827 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
18828 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
18829 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
18830 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
18831 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
18832 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
18833 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
18834 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
18835 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
18836 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
18837 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
18839 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
18840 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
18841 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
18842 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
18843 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
18844 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
18845 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
18846 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
18847 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
18848 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
18849 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
18850 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
18852 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
18853 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
18854 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
18855 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
18856 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
18857 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
18858 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
18859 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
18860 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
18861 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
18862 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
18863 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
18865 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
18866 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
18867 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
18868 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
18869 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
18870 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
18871 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
18872 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
18873 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
18874 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
18875 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
18876 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
18878 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
18879 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
18880 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
18881 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
18882 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
18883 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
18884 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
18885 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
18886 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
18887 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
18888 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
18889 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
18891 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
18892 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
18893 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
18894 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
18895 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
18896 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
18897 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
18898 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
18899 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
18900 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
18901 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
18902 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
18904 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
18905 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
18906 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
18907 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
18908 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
18909 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
18910 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
18911 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
18912 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
18913 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
18914 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
18915 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
18917 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
18918 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
18919 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
18920 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
18921 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
18922 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
18923 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
18924 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
18925 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
18926 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
18927 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
18928 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
18930 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
18931 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
18932 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
18933 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
18934 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
18935 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
18936 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
18937 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
18938 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
18939 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
18940 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
18941 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
18943 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
18944 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
18945 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
18946 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
18947 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
18948 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
18949 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
18950 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
18951 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
18952 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
18953 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
18954 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
18956 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
18957 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
18958 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
18959 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
18960 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
18961 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
18962 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
18963 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
18964 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
18965 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
18966 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
18967 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
18969 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
18970 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
18971 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
18972 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
18973 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
18974 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
18975 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
18976 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
18977 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
18978 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
18979 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
18980 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
18982 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
18983 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
18984 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
18985 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
18986 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
18987 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
18988 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
18989 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
18990 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
18991 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
18992 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
18993 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
18995 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
18996 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
18997 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
18998 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
18999 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19000 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19001 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19002 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19003 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19004 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19005 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19006 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19008 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19009 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19010 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19011 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19012 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19013 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19014 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19015 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19016 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19017 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19018 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19019 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19021 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19022 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19023 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19024 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19025 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19026 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19027 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19028 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19029 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19030 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19031 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19032 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19034 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19035 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19036 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19037 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19038 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19039 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19040 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19041 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19042 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19043 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19044 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19045 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19047 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19048 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19049 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19050 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19051 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19052 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19053 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19054 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19055 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19056 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19057 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19058 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19060 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19061 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19062 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19063 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19064 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19065 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19066 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19067 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19068 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19069 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19070 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19071 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19073 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19074 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19075 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19076 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19077 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19078 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19079 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19080 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19081 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19082 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19083 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19084 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19086 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19087 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19088 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19089 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19090 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19091 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19092 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19093 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19094 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19095 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19096 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19097 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19099 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19100 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19101 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19102 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19103 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19104 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19105 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19106 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19107 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19108 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19109 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19110 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19112 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19113 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19114 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19115 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19116 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19117 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19118 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19119 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19120 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19121 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19122 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19123 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19125 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19126 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19127 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19128 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19129 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19130 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19131 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19132 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19133 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19134 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19135 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19136 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19138 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19139 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19140 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19141 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19142 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19143 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19144 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19145 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19146 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19147 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19148 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19149 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19151 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19152 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19153 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19154 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19155 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19156 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19157 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19158 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19159 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19160 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19161 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19162 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19164 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19165 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19166 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19167 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19168 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19169 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19170 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19171 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19172 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19173 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19174 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19175 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19177 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19178 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19179 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19180 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19181 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19182 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19183 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19184 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19185 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19186 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19187 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19188 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19190 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19191 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19192 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19193 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19195 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19196 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19197 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19198 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19199 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19200 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19201 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19202 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19203 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19204 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19205 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19206 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19208 /* The implementation of the FIX instruction is broken on some
19209 assemblers, in that it accepts a precision specifier as well as a
19210 rounding specifier, despite the fact that this is meaningless.
19211 To be more compatible, we accept it as well, though of course it
19212 does not set any bits. */
19213 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19214 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19215 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19216 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19217 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19218 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19219 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19220 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19221 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19222 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19223 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19224 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19225 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19227 /* Instructions that were new with the real FPA, call them V2. */
19229 #define ARM_VARIANT & fpu_fpa_ext_v2
19231 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19232 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19233 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19234 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19235 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19236 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19239 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19241 /* Moves and type conversions. */
19242 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19243 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19244 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19245 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19246 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19247 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19248 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19249 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19250 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19251 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19252 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19253 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19254 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19255 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19257 /* Memory operations. */
19258 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19259 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19260 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19261 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19262 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19263 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19264 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19265 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19266 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19267 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19268 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19269 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19270 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19271 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19272 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19273 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19274 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19275 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19277 /* Monadic operations. */
19278 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19279 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19280 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19282 /* Dyadic operations. */
19283 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19284 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19285 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19286 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19287 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19288 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19289 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19290 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19291 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19294 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19295 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19296 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19297 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19299 /* Double precision load/store are still present on single precision
19300 implementations. */
19301 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19302 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19303 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19304 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19305 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19306 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19307 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19308 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19309 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19310 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19313 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19315 /* Moves and type conversions. */
19316 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19317 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19318 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19319 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19320 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19321 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19322 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19323 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19324 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19325 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19326 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19327 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19328 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19330 /* Monadic operations. */
19331 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19332 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19333 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19335 /* Dyadic operations. */
19336 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19337 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19338 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19339 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19340 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19341 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19342 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19343 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19344 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19347 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19348 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19349 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19350 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19353 #define ARM_VARIANT & fpu_vfp_ext_v2
19355 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19356 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19357 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19358 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19360 /* Instructions which may belong to either the Neon or VFP instruction sets.
19361 Individual encoder functions perform additional architecture checks. */
19363 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19364 #undef THUMB_VARIANT
19365 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19367 /* These mnemonics are unique to VFP. */
19368 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19369 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19370 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19371 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19372 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19373 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19374 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19375 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19376 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19377 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19379 /* Mnemonics shared by Neon and VFP. */
19380 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19381 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19382 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19384 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19385 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19387 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19388 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19390 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19391 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19392 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19393 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19394 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19395 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19396 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19397 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19399 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19400 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19401 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19402 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19405 /* NOTE: All VMOV encoding is special-cased! */
19406 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19407 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19409 #undef THUMB_VARIANT
19410 #define THUMB_VARIANT & fpu_neon_ext_v1
19412 #define ARM_VARIANT & fpu_neon_ext_v1
19414 /* Data processing with three registers of the same length. */
19415 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19416 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19417 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19418 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19419 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19420 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19421 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19422 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19423 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19424 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19425 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19426 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19427 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19428 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19429 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19430 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19431 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19432 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19433 /* If not immediate, fall back to neon_dyadic_i64_su.
19434 shl_imm should accept I8 I16 I32 I64,
19435 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19436 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19437 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19438 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19439 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19440 /* Logic ops, types optional & ignored. */
19441 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19442 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19443 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19444 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19445 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19446 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19447 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19448 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19449 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19450 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19451 /* Bitfield ops, untyped. */
19452 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19453 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19454 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19455 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19456 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19457 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19458 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19459 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19460 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19461 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19462 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19463 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19464 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19465 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19466 back to neon_dyadic_if_su. */
19467 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19468 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19469 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19470 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19471 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19472 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19473 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19474 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19475 /* Comparison. Type I8 I16 I32 F32. */
19476 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19477 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19478 /* As above, D registers only. */
19479 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19480 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19481 /* Int and float variants, signedness unimportant. */
19482 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19483 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19484 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19485 /* Add/sub take types I8 I16 I32 I64 F32. */
19486 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19487 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19488 /* vtst takes sizes 8, 16, 32. */
19489 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19490 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19491 /* VMUL takes I8 I16 I32 F32 P8. */
19492 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19493 /* VQD{R}MULH takes S16 S32. */
19494 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19495 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19496 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19497 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19498 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19499 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19500 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19501 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19502 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19503 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19504 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19505 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19506 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19507 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19508 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19509 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19511 /* Two address, int/float. Types S8 S16 S32 F32. */
19512 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19513 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19515 /* Data processing with two registers and a shift amount. */
19516 /* Right shifts, and variants with rounding.
19517 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19518 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19519 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19520 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19521 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19522 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19523 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19524 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19525 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19526 /* Shift and insert. Sizes accepted 8 16 32 64. */
19527 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19528 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19529 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19530 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19531 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19532 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19533 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19534 /* Right shift immediate, saturating & narrowing, with rounding variants.
19535 Types accepted S16 S32 S64 U16 U32 U64. */
19536 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19537 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19538 /* As above, unsigned. Types accepted S16 S32 S64. */
19539 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19540 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19541 /* Right shift narrowing. Types accepted I16 I32 I64. */
19542 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19543 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19544 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19545 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19546 /* CVT with optional immediate for fixed-point variant. */
19547 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19549 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19550 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19552 /* Data processing, three registers of different lengths. */
19553 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19554 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19555 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19556 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19557 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19558 /* If not scalar, fall back to neon_dyadic_long.
19559 Vector types as above, scalar types S16 S32 U16 U32. */
19560 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19561 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19562 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19563 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19564 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19565 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19566 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19567 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19568 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19569 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19570 /* Saturating doubling multiplies. Types S16 S32. */
19571 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19572 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19573 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19574 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19575 S16 S32 U16 U32. */
19576 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19578 /* Extract. Size 8. */
19579 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19580 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19582 /* Two registers, miscellaneous. */
19583 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19584 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19585 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19586 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19587 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19588 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19589 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19590 /* Vector replicate. Sizes 8 16 32. */
19591 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19592 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19593 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19594 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19595 /* VMOVN. Types I16 I32 I64. */
19596 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19597 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19598 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19599 /* VQMOVUN. Types S16 S32 S64. */
19600 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19601 /* VZIP / VUZP. Sizes 8 16 32. */
19602 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19603 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19604 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19605 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19606 /* VQABS / VQNEG. Types S8 S16 S32. */
19607 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19608 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19609 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19610 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19611 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19612 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19613 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19614 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19615 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19616 /* Reciprocal estimates. Types U32 F32. */
19617 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19618 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19619 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19620 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19621 /* VCLS. Types S8 S16 S32. */
19622 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19623 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19624 /* VCLZ. Types I8 I16 I32. */
19625 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19626 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19627 /* VCNT. Size 8. */
19628 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19629 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19630 /* Two address, untyped. */
19631 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19632 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19633 /* VTRN. Sizes 8 16 32. */
19634 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19635 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19637 /* Table lookup. Size 8. */
19638 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19639 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19641 #undef THUMB_VARIANT
19642 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19644 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19646 /* Neon element/structure load/store. */
19647 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19648 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19649 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19650 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19651 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19652 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19653 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19654 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19656 #undef THUMB_VARIANT
19657 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19659 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19660 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19661 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19662 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19663 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19664 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19665 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19666 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19667 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19668 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19670 #undef THUMB_VARIANT
19671 #define THUMB_VARIANT & fpu_vfp_ext_v3
19673 #define ARM_VARIANT & fpu_vfp_ext_v3
19675 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19676 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19677 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19678 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19679 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19680 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19681 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19682 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19683 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19686 #define ARM_VARIANT & fpu_vfp_ext_fma
19687 #undef THUMB_VARIANT
19688 #define THUMB_VARIANT & fpu_vfp_ext_fma
19689 /* Mnemonics shared by Neon and VFP. These are included in the
19690 VFP FMA variant; NEON and VFP FMA always includes the NEON
19691 FMA instructions. */
19692 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19693 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19694 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19695 the v form should always be used. */
19696 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19697 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19698 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19699 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19700 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19701 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19703 #undef THUMB_VARIANT
19705 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19707 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19708 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19709 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19710 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19711 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19712 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19713 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
19714 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
19717 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19719 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
19720 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
19721 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
19722 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
19723 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
19724 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
19725 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
19726 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
19727 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
19728 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19729 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19730 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19731 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19732 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19733 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19734 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19735 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19736 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19737 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
19738 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
19739 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19740 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19741 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19742 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19743 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19744 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19745 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
19746 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
19747 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
19748 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
19749 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
19750 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
19751 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
19752 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
19753 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19754 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19755 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19756 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19757 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19758 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19759 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19760 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19761 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19762 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19763 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19764 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19765 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
19766 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19767 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19768 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19769 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19770 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19771 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19772 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19773 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19774 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19775 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19776 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19777 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19778 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19779 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19780 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19781 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19782 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19783 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19784 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19785 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19786 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19787 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19788 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19789 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19790 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19791 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19792 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19793 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19794 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19795 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19796 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19797 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19798 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19799 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19800 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19801 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19802 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19803 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19804 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19805 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19806 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19807 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
19808 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19809 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19810 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19811 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19812 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19813 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19814 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19815 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19816 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19817 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19818 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19819 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19820 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19821 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19822 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19823 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19824 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19825 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19826 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19827 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19828 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19829 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
19830 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19831 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19832 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19833 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19834 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19835 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19836 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19837 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19838 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19839 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19840 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19841 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19842 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19843 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19844 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19845 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19846 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19847 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19848 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19849 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19850 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19851 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19852 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19853 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19854 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19855 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19856 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19857 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19858 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19859 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19860 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19861 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19862 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19863 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19864 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19865 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19866 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19867 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19868 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19869 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19870 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19871 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19872 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19873 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19874 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19875 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19876 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19877 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19878 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19879 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19880 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
19883 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19885 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
19886 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
19887 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
19888 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19889 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19890 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19891 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19892 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19893 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19894 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19895 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19896 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19897 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19898 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19899 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19900 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19901 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19902 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19903 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19904 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19905 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
19906 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19907 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19908 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19909 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19910 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19911 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19912 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19913 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19914 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19915 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19916 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19917 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19918 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19919 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19920 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19921 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19922 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19923 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19924 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19925 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19926 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19927 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19928 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19929 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19930 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19931 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19932 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19933 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19934 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19935 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19936 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19937 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19938 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19939 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19940 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19941 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19944 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19946 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19947 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19948 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19949 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19950 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19951 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19952 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19953 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19954 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
19955 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
19956 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
19957 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
19958 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
19959 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
19960 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
19961 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
19962 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
19963 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
19964 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
19965 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
19966 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
19967 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
19968 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
19969 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
19970 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
19971 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
19972 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
19973 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
19974 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
19975 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
19976 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
19977 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
19978 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
19979 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
19980 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
19981 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
19982 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
19983 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
19984 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
19985 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
19986 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
19987 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
19988 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
19989 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
19990 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
19991 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
19992 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
19993 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
19994 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
19995 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
19996 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
19997 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
19998 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
19999 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20000 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20001 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20002 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20003 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20004 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20005 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20006 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20007 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20008 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20009 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20010 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20011 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20012 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20013 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20014 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20015 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20016 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20017 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20018 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20019 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20020 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20021 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20024 #undef THUMB_VARIANT
20050 /* MD interface: bits in the object file. */
20052 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20053 for use in the a.out file, and stores them in the array pointed to by buf.
20054 This knows about the endian-ness of the target machine and does
20055 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20056 2 (short) and 4 (long) Floating numbers are put out as a series of
20057 LITTLENUMS (shorts, here at least). */
20060 md_number_to_chars (char * buf
, valueT val
, int n
)
20062 if (target_big_endian
)
20063 number_to_chars_bigendian (buf
, val
, n
);
20065 number_to_chars_littleendian (buf
, val
, n
);
20069 md_chars_to_number (char * buf
, int n
)
20072 unsigned char * where
= (unsigned char *) buf
;
20074 if (target_big_endian
)
20079 result
|= (*where
++ & 255);
20087 result
|= (where
[n
] & 255);
20094 /* MD interface: Sections. */
20096 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20097 that an rs_machine_dependent frag may reach. */
20100 arm_frag_max_var (fragS
*fragp
)
20102 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20103 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20105 Note that we generate relaxable instructions even for cases that don't
20106 really need it, like an immediate that's a trivial constant. So we're
20107 overestimating the instruction size for some of those cases. Rather
20108 than putting more intelligence here, it would probably be better to
20109 avoid generating a relaxation frag in the first place when it can be
20110 determined up front that a short instruction will suffice. */
20112 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20116 /* Estimate the size of a frag before relaxing. Assume everything fits in
20120 md_estimate_size_before_relax (fragS
* fragp
,
20121 segT segtype ATTRIBUTE_UNUSED
)
20127 /* Convert a machine dependent frag. */
20130 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20132 unsigned long insn
;
20133 unsigned long old_op
;
20141 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20143 old_op
= bfd_get_16(abfd
, buf
);
20144 if (fragp
->fr_symbol
)
20146 exp
.X_op
= O_symbol
;
20147 exp
.X_add_symbol
= fragp
->fr_symbol
;
20151 exp
.X_op
= O_constant
;
20153 exp
.X_add_number
= fragp
->fr_offset
;
20154 opcode
= fragp
->fr_subtype
;
20157 case T_MNEM_ldr_pc
:
20158 case T_MNEM_ldr_pc2
:
20159 case T_MNEM_ldr_sp
:
20160 case T_MNEM_str_sp
:
20167 if (fragp
->fr_var
== 4)
20169 insn
= THUMB_OP32 (opcode
);
20170 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20172 insn
|= (old_op
& 0x700) << 4;
20176 insn
|= (old_op
& 7) << 12;
20177 insn
|= (old_op
& 0x38) << 13;
20179 insn
|= 0x00000c00;
20180 put_thumb32_insn (buf
, insn
);
20181 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20185 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20187 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20190 if (fragp
->fr_var
== 4)
20192 insn
= THUMB_OP32 (opcode
);
20193 insn
|= (old_op
& 0xf0) << 4;
20194 put_thumb32_insn (buf
, insn
);
20195 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20199 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20200 exp
.X_add_number
-= 4;
20208 if (fragp
->fr_var
== 4)
20210 int r0off
= (opcode
== T_MNEM_mov
20211 || opcode
== T_MNEM_movs
) ? 0 : 8;
20212 insn
= THUMB_OP32 (opcode
);
20213 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20214 insn
|= (old_op
& 0x700) << r0off
;
20215 put_thumb32_insn (buf
, insn
);
20216 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20220 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20225 if (fragp
->fr_var
== 4)
20227 insn
= THUMB_OP32(opcode
);
20228 put_thumb32_insn (buf
, insn
);
20229 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20232 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20236 if (fragp
->fr_var
== 4)
20238 insn
= THUMB_OP32(opcode
);
20239 insn
|= (old_op
& 0xf00) << 14;
20240 put_thumb32_insn (buf
, insn
);
20241 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20244 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20247 case T_MNEM_add_sp
:
20248 case T_MNEM_add_pc
:
20249 case T_MNEM_inc_sp
:
20250 case T_MNEM_dec_sp
:
20251 if (fragp
->fr_var
== 4)
20253 /* ??? Choose between add and addw. */
20254 insn
= THUMB_OP32 (opcode
);
20255 insn
|= (old_op
& 0xf0) << 4;
20256 put_thumb32_insn (buf
, insn
);
20257 if (opcode
== T_MNEM_add_pc
)
20258 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20260 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20263 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20271 if (fragp
->fr_var
== 4)
20273 insn
= THUMB_OP32 (opcode
);
20274 insn
|= (old_op
& 0xf0) << 4;
20275 insn
|= (old_op
& 0xf) << 16;
20276 put_thumb32_insn (buf
, insn
);
20277 if (insn
& (1 << 20))
20278 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20280 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20283 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20289 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20290 (enum bfd_reloc_code_real
) reloc_type
);
20291 fixp
->fx_file
= fragp
->fr_file
;
20292 fixp
->fx_line
= fragp
->fr_line
;
20293 fragp
->fr_fix
+= fragp
->fr_var
;
20296 /* Return the size of a relaxable immediate operand instruction.
20297 SHIFT and SIZE specify the form of the allowable immediate. */
20299 relax_immediate (fragS
*fragp
, int size
, int shift
)
20305 /* ??? Should be able to do better than this. */
20306 if (fragp
->fr_symbol
)
20309 low
= (1 << shift
) - 1;
20310 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20311 offset
= fragp
->fr_offset
;
20312 /* Force misaligned offsets to 32-bit variant. */
20315 if (offset
& ~mask
)
20320 /* Get the address of a symbol during relaxation. */
20322 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20328 sym
= fragp
->fr_symbol
;
20329 sym_frag
= symbol_get_frag (sym
);
20330 know (S_GET_SEGMENT (sym
) != absolute_section
20331 || sym_frag
== &zero_address_frag
);
20332 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20334 /* If frag has yet to be reached on this pass, assume it will
20335 move by STRETCH just as we did. If this is not so, it will
20336 be because some frag between grows, and that will force
20340 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20344 /* Adjust stretch for any alignment frag. Note that if have
20345 been expanding the earlier code, the symbol may be
20346 defined in what appears to be an earlier frag. FIXME:
20347 This doesn't handle the fr_subtype field, which specifies
20348 a maximum number of bytes to skip when doing an
20350 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20352 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20355 stretch
= - ((- stretch
)
20356 & ~ ((1 << (int) f
->fr_offset
) - 1));
20358 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20370 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20373 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20378 /* Assume worst case for symbols not known to be in the same section. */
20379 if (fragp
->fr_symbol
== NULL
20380 || !S_IS_DEFINED (fragp
->fr_symbol
)
20381 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20382 || S_IS_WEAK (fragp
->fr_symbol
))
20385 val
= relaxed_symbol_addr (fragp
, stretch
);
20386 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20387 addr
= (addr
+ 4) & ~3;
20388 /* Force misaligned targets to 32-bit variant. */
20392 if (val
< 0 || val
> 1020)
20397 /* Return the size of a relaxable add/sub immediate instruction. */
20399 relax_addsub (fragS
*fragp
, asection
*sec
)
20404 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20405 op
= bfd_get_16(sec
->owner
, buf
);
20406 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20407 return relax_immediate (fragp
, 8, 0);
20409 return relax_immediate (fragp
, 3, 0);
20412 /* Return TRUE iff the definition of symbol S could be pre-empted
20413 (overridden) at link or load time. */
20415 symbol_preemptible (symbolS
*s
)
20417 /* Weak symbols can always be pre-empted. */
20421 /* Non-global symbols cannot be pre-empted. */
20422 if (! S_IS_EXTERNAL (s
))
20426 /* In ELF, a global symbol can be marked protected, or private. In that
20427 case it can't be pre-empted (other definitions in the same link unit
20428 would violate the ODR). */
20429 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20433 /* Other global symbols might be pre-empted. */
20437 /* Return the size of a relaxable branch instruction. BITS is the
20438 size of the offset field in the narrow instruction. */
20441 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20447 /* Assume worst case for symbols not known to be in the same section. */
20448 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20449 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20450 || S_IS_WEAK (fragp
->fr_symbol
))
20454 /* A branch to a function in ARM state will require interworking. */
20455 if (S_IS_DEFINED (fragp
->fr_symbol
)
20456 && ARM_IS_FUNC (fragp
->fr_symbol
))
20460 if (symbol_preemptible (fragp
->fr_symbol
))
20463 val
= relaxed_symbol_addr (fragp
, stretch
);
20464 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20467 /* Offset is a signed value *2 */
20469 if (val
>= limit
|| val
< -limit
)
20475 /* Relax a machine dependent frag. This returns the amount by which
20476 the current size of the frag should change. */
20479 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20484 oldsize
= fragp
->fr_var
;
20485 switch (fragp
->fr_subtype
)
20487 case T_MNEM_ldr_pc2
:
20488 newsize
= relax_adr (fragp
, sec
, stretch
);
20490 case T_MNEM_ldr_pc
:
20491 case T_MNEM_ldr_sp
:
20492 case T_MNEM_str_sp
:
20493 newsize
= relax_immediate (fragp
, 8, 2);
20497 newsize
= relax_immediate (fragp
, 5, 2);
20501 newsize
= relax_immediate (fragp
, 5, 1);
20505 newsize
= relax_immediate (fragp
, 5, 0);
20508 newsize
= relax_adr (fragp
, sec
, stretch
);
20514 newsize
= relax_immediate (fragp
, 8, 0);
20517 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20520 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20522 case T_MNEM_add_sp
:
20523 case T_MNEM_add_pc
:
20524 newsize
= relax_immediate (fragp
, 8, 2);
20526 case T_MNEM_inc_sp
:
20527 case T_MNEM_dec_sp
:
20528 newsize
= relax_immediate (fragp
, 7, 2);
20534 newsize
= relax_addsub (fragp
, sec
);
20540 fragp
->fr_var
= newsize
;
20541 /* Freeze wide instructions that are at or before the same location as
20542 in the previous pass. This avoids infinite loops.
20543 Don't freeze them unconditionally because targets may be artificially
20544 misaligned by the expansion of preceding frags. */
20545 if (stretch
<= 0 && newsize
> 2)
20547 md_convert_frag (sec
->owner
, sec
, fragp
);
20551 return newsize
- oldsize
;
20554 /* Round up a section size to the appropriate boundary. */
20557 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20560 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20561 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20563 /* For a.out, force the section size to be aligned. If we don't do
20564 this, BFD will align it for us, but it will not write out the
20565 final bytes of the section. This may be a bug in BFD, but it is
20566 easier to fix it here since that is how the other a.out targets
20570 align
= bfd_get_section_alignment (stdoutput
, segment
);
20571 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20578 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20579 of an rs_align_code fragment. */
20582 arm_handle_align (fragS
* fragP
)
20584 static char const arm_noop
[2][2][4] =
20587 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20588 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20591 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20592 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20595 static char const thumb_noop
[2][2][2] =
20598 {0xc0, 0x46}, /* LE */
20599 {0x46, 0xc0}, /* BE */
20602 {0x00, 0xbf}, /* LE */
20603 {0xbf, 0x00} /* BE */
20606 static char const wide_thumb_noop
[2][4] =
20607 { /* Wide Thumb-2 */
20608 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20609 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20612 unsigned bytes
, fix
, noop_size
;
20615 const char *narrow_noop
= NULL
;
20620 if (fragP
->fr_type
!= rs_align_code
)
20623 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20624 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20627 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20628 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20630 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20632 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20634 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
20636 narrow_noop
= thumb_noop
[1][target_big_endian
];
20637 noop
= wide_thumb_noop
[target_big_endian
];
20640 noop
= thumb_noop
[0][target_big_endian
];
20648 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
20649 [target_big_endian
];
20656 fragP
->fr_var
= noop_size
;
20658 if (bytes
& (noop_size
- 1))
20660 fix
= bytes
& (noop_size
- 1);
20662 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20664 memset (p
, 0, fix
);
20671 if (bytes
& noop_size
)
20673 /* Insert a narrow noop. */
20674 memcpy (p
, narrow_noop
, noop_size
);
20676 bytes
-= noop_size
;
20680 /* Use wide noops for the remainder */
20684 while (bytes
>= noop_size
)
20686 memcpy (p
, noop
, noop_size
);
20688 bytes
-= noop_size
;
20692 fragP
->fr_fix
+= fix
;
20695 /* Called from md_do_align. Used to create an alignment
20696 frag in a code section. */
20699 arm_frag_align_code (int n
, int max
)
20703 /* We assume that there will never be a requirement
20704 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20705 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20710 _("alignments greater than %d bytes not supported in .text sections."),
20711 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
20712 as_fatal ("%s", err_msg
);
20715 p
= frag_var (rs_align_code
,
20716 MAX_MEM_FOR_RS_ALIGN_CODE
,
20718 (relax_substateT
) max
,
20725 /* Perform target specific initialisation of a frag.
20726 Note - despite the name this initialisation is not done when the frag
20727 is created, but only when its type is assigned. A frag can be created
20728 and used a long time before its type is set, so beware of assuming that
20729 this initialisationis performed first. */
20733 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
20735 /* Record whether this frag is in an ARM or a THUMB area. */
20736 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20739 #else /* OBJ_ELF is defined. */
20741 arm_init_frag (fragS
* fragP
, int max_chars
)
20743 /* If the current ARM vs THUMB mode has not already
20744 been recorded into this frag then do so now. */
20745 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
20747 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20749 /* Record a mapping symbol for alignment frags. We will delete this
20750 later if the alignment ends up empty. */
20751 switch (fragP
->fr_type
)
20754 case rs_align_test
:
20756 mapping_state_2 (MAP_DATA
, max_chars
);
20758 case rs_align_code
:
20759 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
20767 /* When we change sections we need to issue a new mapping symbol. */
20770 arm_elf_change_section (void)
20772 /* Link an unlinked unwind index table section to the .text section. */
20773 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
20774 && elf_linked_to_section (now_seg
) == NULL
)
20775 elf_linked_to_section (now_seg
) = text_section
;
20779 arm_elf_section_type (const char * str
, size_t len
)
20781 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
20782 return SHT_ARM_EXIDX
;
20787 /* Code to deal with unwinding tables. */
20789 static void add_unwind_adjustsp (offsetT
);
20791 /* Generate any deferred unwind frame offset. */
20794 flush_pending_unwind (void)
20798 offset
= unwind
.pending_offset
;
20799 unwind
.pending_offset
= 0;
20801 add_unwind_adjustsp (offset
);
20804 /* Add an opcode to this list for this function. Two-byte opcodes should
20805 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20809 add_unwind_opcode (valueT op
, int length
)
20811 /* Add any deferred stack adjustment. */
20812 if (unwind
.pending_offset
)
20813 flush_pending_unwind ();
20815 unwind
.sp_restored
= 0;
20817 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
20819 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
20820 if (unwind
.opcodes
)
20821 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
20822 unwind
.opcode_alloc
);
20824 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
20829 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
20831 unwind
.opcode_count
++;
20835 /* Add unwind opcodes to adjust the stack pointer. */
20838 add_unwind_adjustsp (offsetT offset
)
20842 if (offset
> 0x200)
20844 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20849 /* Long form: 0xb2, uleb128. */
20850 /* This might not fit in a word so add the individual bytes,
20851 remembering the list is built in reverse order. */
20852 o
= (valueT
) ((offset
- 0x204) >> 2);
20854 add_unwind_opcode (0, 1);
20856 /* Calculate the uleb128 encoding of the offset. */
20860 bytes
[n
] = o
& 0x7f;
20866 /* Add the insn. */
20868 add_unwind_opcode (bytes
[n
- 1], 1);
20869 add_unwind_opcode (0xb2, 1);
20871 else if (offset
> 0x100)
20873 /* Two short opcodes. */
20874 add_unwind_opcode (0x3f, 1);
20875 op
= (offset
- 0x104) >> 2;
20876 add_unwind_opcode (op
, 1);
20878 else if (offset
> 0)
20880 /* Short opcode. */
20881 op
= (offset
- 4) >> 2;
20882 add_unwind_opcode (op
, 1);
20884 else if (offset
< 0)
20887 while (offset
> 0x100)
20889 add_unwind_opcode (0x7f, 1);
20892 op
= ((offset
- 4) >> 2) | 0x40;
20893 add_unwind_opcode (op
, 1);
20897 /* Finish the list of unwind opcodes for this function. */
20899 finish_unwind_opcodes (void)
20903 if (unwind
.fp_used
)
20905 /* Adjust sp as necessary. */
20906 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
20907 flush_pending_unwind ();
20909 /* After restoring sp from the frame pointer. */
20910 op
= 0x90 | unwind
.fp_reg
;
20911 add_unwind_opcode (op
, 1);
20914 flush_pending_unwind ();
20918 /* Start an exception table entry. If idx is nonzero this is an index table
20922 start_unwind_section (const segT text_seg
, int idx
)
20924 const char * text_name
;
20925 const char * prefix
;
20926 const char * prefix_once
;
20927 const char * group_name
;
20931 size_t sec_name_len
;
20938 prefix
= ELF_STRING_ARM_unwind
;
20939 prefix_once
= ELF_STRING_ARM_unwind_once
;
20940 type
= SHT_ARM_EXIDX
;
20944 prefix
= ELF_STRING_ARM_unwind_info
;
20945 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
20946 type
= SHT_PROGBITS
;
20949 text_name
= segment_name (text_seg
);
20950 if (streq (text_name
, ".text"))
20953 if (strncmp (text_name
, ".gnu.linkonce.t.",
20954 strlen (".gnu.linkonce.t.")) == 0)
20956 prefix
= prefix_once
;
20957 text_name
+= strlen (".gnu.linkonce.t.");
20960 prefix_len
= strlen (prefix
);
20961 text_len
= strlen (text_name
);
20962 sec_name_len
= prefix_len
+ text_len
;
20963 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
20964 memcpy (sec_name
, prefix
, prefix_len
);
20965 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
20966 sec_name
[prefix_len
+ text_len
] = '\0';
20972 /* Handle COMDAT group. */
20973 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
20975 group_name
= elf_group_name (text_seg
);
20976 if (group_name
== NULL
)
20978 as_bad (_("Group section `%s' has no group signature"),
20979 segment_name (text_seg
));
20980 ignore_rest_of_line ();
20983 flags
|= SHF_GROUP
;
20987 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
20989 /* Set the section link for index tables. */
20991 elf_linked_to_section (now_seg
) = text_seg
;
20995 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20996 personality routine data. Returns zero, or the index table value for
20997 an inline entry. */
21000 create_unwind_entry (int have_data
)
21005 /* The current word of data. */
21007 /* The number of bytes left in this word. */
21010 finish_unwind_opcodes ();
21012 /* Remember the current text section. */
21013 unwind
.saved_seg
= now_seg
;
21014 unwind
.saved_subseg
= now_subseg
;
21016 start_unwind_section (now_seg
, 0);
21018 if (unwind
.personality_routine
== NULL
)
21020 if (unwind
.personality_index
== -2)
21023 as_bad (_("handlerdata in cantunwind frame"));
21024 return 1; /* EXIDX_CANTUNWIND. */
21027 /* Use a default personality routine if none is specified. */
21028 if (unwind
.personality_index
== -1)
21030 if (unwind
.opcode_count
> 3)
21031 unwind
.personality_index
= 1;
21033 unwind
.personality_index
= 0;
21036 /* Space for the personality routine entry. */
21037 if (unwind
.personality_index
== 0)
21039 if (unwind
.opcode_count
> 3)
21040 as_bad (_("too many unwind opcodes for personality routine 0"));
21044 /* All the data is inline in the index table. */
21047 while (unwind
.opcode_count
> 0)
21049 unwind
.opcode_count
--;
21050 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21054 /* Pad with "finish" opcodes. */
21056 data
= (data
<< 8) | 0xb0;
21063 /* We get two opcodes "free" in the first word. */
21064 size
= unwind
.opcode_count
- 2;
21068 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21069 if (unwind
.personality_index
!= -1)
21071 as_bad (_("attempt to recreate an unwind entry"));
21075 /* An extra byte is required for the opcode count. */
21076 size
= unwind
.opcode_count
+ 1;
21079 size
= (size
+ 3) >> 2;
21081 as_bad (_("too many unwind opcodes"));
21083 frag_align (2, 0, 0);
21084 record_alignment (now_seg
, 2);
21085 unwind
.table_entry
= expr_build_dot ();
21087 /* Allocate the table entry. */
21088 ptr
= frag_more ((size
<< 2) + 4);
21089 /* PR 13449: Zero the table entries in case some of them are not used. */
21090 memset (ptr
, 0, (size
<< 2) + 4);
21091 where
= frag_now_fix () - ((size
<< 2) + 4);
21093 switch (unwind
.personality_index
)
21096 /* ??? Should this be a PLT generating relocation? */
21097 /* Custom personality routine. */
21098 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21099 BFD_RELOC_ARM_PREL31
);
21104 /* Set the first byte to the number of additional words. */
21105 data
= size
> 0 ? size
- 1 : 0;
21109 /* ABI defined personality routines. */
21111 /* Three opcodes bytes are packed into the first word. */
21118 /* The size and first two opcode bytes go in the first word. */
21119 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21124 /* Should never happen. */
21128 /* Pack the opcodes into words (MSB first), reversing the list at the same
21130 while (unwind
.opcode_count
> 0)
21134 md_number_to_chars (ptr
, data
, 4);
21139 unwind
.opcode_count
--;
21141 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21144 /* Finish off the last word. */
21147 /* Pad with "finish" opcodes. */
21149 data
= (data
<< 8) | 0xb0;
21151 md_number_to_chars (ptr
, data
, 4);
21156 /* Add an empty descriptor if there is no user-specified data. */
21157 ptr
= frag_more (4);
21158 md_number_to_chars (ptr
, 0, 4);
21165 /* Initialize the DWARF-2 unwind information for this procedure. */
21168 tc_arm_frame_initial_instructions (void)
21170 cfi_add_CFA_def_cfa (REG_SP
, 0);
21172 #endif /* OBJ_ELF */
21174 /* Convert REGNAME to a DWARF-2 register number. */
21177 tc_arm_regname_to_dw2regnum (char *regname
)
21179 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21183 /* PR 16694: Allow VFP registers as well. */
21184 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21188 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21197 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21201 exp
.X_op
= O_secrel
;
21202 exp
.X_add_symbol
= symbol
;
21203 exp
.X_add_number
= 0;
21204 emit_expr (&exp
, size
);
21208 /* MD interface: Symbol and relocation handling. */
21210 /* Return the address within the segment that a PC-relative fixup is
21211 relative to. For ARM, PC-relative fixups applied to instructions
21212 are generally relative to the location of the fixup plus 8 bytes.
21213 Thumb branches are offset by 4, and Thumb loads relative to PC
21214 require special handling. */
21217 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21219 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21221 /* If this is pc-relative and we are going to emit a relocation
21222 then we just want to put out any pipeline compensation that the linker
21223 will need. Otherwise we want to use the calculated base.
21224 For WinCE we skip the bias for externals as well, since this
21225 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21227 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21228 || (arm_force_relocation (fixP
)
21230 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21236 switch (fixP
->fx_r_type
)
21238 /* PC relative addressing on the Thumb is slightly odd as the
21239 bottom two bits of the PC are forced to zero for the
21240 calculation. This happens *after* application of the
21241 pipeline offset. However, Thumb adrl already adjusts for
21242 this, so we need not do it again. */
21243 case BFD_RELOC_ARM_THUMB_ADD
:
21246 case BFD_RELOC_ARM_THUMB_OFFSET
:
21247 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21248 case BFD_RELOC_ARM_T32_ADD_PC12
:
21249 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21250 return (base
+ 4) & ~3;
21252 /* Thumb branches are simply offset by +4. */
21253 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21254 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21255 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21256 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21257 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21260 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21262 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21263 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21264 && ARM_IS_FUNC (fixP
->fx_addsy
)
21265 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21266 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21269 /* BLX is like branches above, but forces the low two bits of PC to
21271 case BFD_RELOC_THUMB_PCREL_BLX
:
21273 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21274 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21275 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21276 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21277 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21278 return (base
+ 4) & ~3;
21280 /* ARM mode branches are offset by +8. However, the Windows CE
21281 loader expects the relocation not to take this into account. */
21282 case BFD_RELOC_ARM_PCREL_BLX
:
21284 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21285 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21286 && ARM_IS_FUNC (fixP
->fx_addsy
)
21287 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21288 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21291 case BFD_RELOC_ARM_PCREL_CALL
:
21293 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21294 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21295 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21296 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21297 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21300 case BFD_RELOC_ARM_PCREL_BRANCH
:
21301 case BFD_RELOC_ARM_PCREL_JUMP
:
21302 case BFD_RELOC_ARM_PLT32
:
21304 /* When handling fixups immediately, because we have already
21305 discovered the value of a symbol, or the address of the frag involved
21306 we must account for the offset by +8, as the OS loader will never see the reloc.
21307 see fixup_segment() in write.c
21308 The S_IS_EXTERNAL test handles the case of global symbols.
21309 Those need the calculated base, not just the pipe compensation the linker will need. */
21311 && fixP
->fx_addsy
!= NULL
21312 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21313 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21321 /* ARM mode loads relative to PC are also offset by +8. Unlike
21322 branches, the Windows CE loader *does* expect the relocation
21323 to take this into account. */
21324 case BFD_RELOC_ARM_OFFSET_IMM
:
21325 case BFD_RELOC_ARM_OFFSET_IMM8
:
21326 case BFD_RELOC_ARM_HWLITERAL
:
21327 case BFD_RELOC_ARM_LITERAL
:
21328 case BFD_RELOC_ARM_CP_OFF_IMM
:
21332 /* Other PC-relative relocations are un-offset. */
21338 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21339 Otherwise we have no need to default values of symbols. */
21342 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21345 if (name
[0] == '_' && name
[1] == 'G'
21346 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21350 if (symbol_find (name
))
21351 as_bad (_("GOT already in the symbol table"));
21353 GOT_symbol
= symbol_new (name
, undefined_section
,
21354 (valueT
) 0, & zero_address_frag
);
21364 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21365 computed as two separate immediate values, added together. We
21366 already know that this value cannot be computed by just one ARM
21369 static unsigned int
21370 validate_immediate_twopart (unsigned int val
,
21371 unsigned int * highpart
)
21376 for (i
= 0; i
< 32; i
+= 2)
21377 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21383 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21385 else if (a
& 0xff0000)
21387 if (a
& 0xff000000)
21389 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21393 gas_assert (a
& 0xff000000);
21394 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21397 return (a
& 0xff) | (i
<< 7);
21404 validate_offset_imm (unsigned int val
, int hwse
)
21406 if ((hwse
&& val
> 255) || val
> 4095)
21411 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21412 negative immediate constant by altering the instruction. A bit of
21417 by inverting the second operand, and
21420 by negating the second operand. */
21423 negate_data_op (unsigned long * instruction
,
21424 unsigned long value
)
21427 unsigned long negated
, inverted
;
21429 negated
= encode_arm_immediate (-value
);
21430 inverted
= encode_arm_immediate (~value
);
21432 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21435 /* First negates. */
21436 case OPCODE_SUB
: /* ADD <-> SUB */
21437 new_inst
= OPCODE_ADD
;
21442 new_inst
= OPCODE_SUB
;
21446 case OPCODE_CMP
: /* CMP <-> CMN */
21447 new_inst
= OPCODE_CMN
;
21452 new_inst
= OPCODE_CMP
;
21456 /* Now Inverted ops. */
21457 case OPCODE_MOV
: /* MOV <-> MVN */
21458 new_inst
= OPCODE_MVN
;
21463 new_inst
= OPCODE_MOV
;
21467 case OPCODE_AND
: /* AND <-> BIC */
21468 new_inst
= OPCODE_BIC
;
21473 new_inst
= OPCODE_AND
;
21477 case OPCODE_ADC
: /* ADC <-> SBC */
21478 new_inst
= OPCODE_SBC
;
21483 new_inst
= OPCODE_ADC
;
21487 /* We cannot do anything. */
21492 if (value
== (unsigned) FAIL
)
21495 *instruction
&= OPCODE_MASK
;
21496 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21500 /* Like negate_data_op, but for Thumb-2. */
21502 static unsigned int
21503 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21507 unsigned int negated
, inverted
;
21509 negated
= encode_thumb32_immediate (-value
);
21510 inverted
= encode_thumb32_immediate (~value
);
21512 rd
= (*instruction
>> 8) & 0xf;
21513 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21516 /* ADD <-> SUB. Includes CMP <-> CMN. */
21517 case T2_OPCODE_SUB
:
21518 new_inst
= T2_OPCODE_ADD
;
21522 case T2_OPCODE_ADD
:
21523 new_inst
= T2_OPCODE_SUB
;
21527 /* ORR <-> ORN. Includes MOV <-> MVN. */
21528 case T2_OPCODE_ORR
:
21529 new_inst
= T2_OPCODE_ORN
;
21533 case T2_OPCODE_ORN
:
21534 new_inst
= T2_OPCODE_ORR
;
21538 /* AND <-> BIC. TST has no inverted equivalent. */
21539 case T2_OPCODE_AND
:
21540 new_inst
= T2_OPCODE_BIC
;
21547 case T2_OPCODE_BIC
:
21548 new_inst
= T2_OPCODE_AND
;
21553 case T2_OPCODE_ADC
:
21554 new_inst
= T2_OPCODE_SBC
;
21558 case T2_OPCODE_SBC
:
21559 new_inst
= T2_OPCODE_ADC
;
21563 /* We cannot do anything. */
21568 if (value
== (unsigned int)FAIL
)
21571 *instruction
&= T2_OPCODE_MASK
;
21572 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21576 /* Read a 32-bit thumb instruction from buf. */
21577 static unsigned long
21578 get_thumb32_insn (char * buf
)
21580 unsigned long insn
;
21581 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21582 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21588 /* We usually want to set the low bit on the address of thumb function
21589 symbols. In particular .word foo - . should have the low bit set.
21590 Generic code tries to fold the difference of two symbols to
21591 a constant. Prevent this and force a relocation when the first symbols
21592 is a thumb function. */
21595 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21597 if (op
== O_subtract
21598 && l
->X_op
== O_symbol
21599 && r
->X_op
== O_symbol
21600 && THUMB_IS_FUNC (l
->X_add_symbol
))
21602 l
->X_op
= O_subtract
;
21603 l
->X_op_symbol
= r
->X_add_symbol
;
21604 l
->X_add_number
-= r
->X_add_number
;
21608 /* Process as normal. */
21612 /* Encode Thumb2 unconditional branches and calls. The encoding
21613 for the 2 are identical for the immediate values. */
21616 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21618 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21621 addressT S
, I1
, I2
, lo
, hi
;
21623 S
= (value
>> 24) & 0x01;
21624 I1
= (value
>> 23) & 0x01;
21625 I2
= (value
>> 22) & 0x01;
21626 hi
= (value
>> 12) & 0x3ff;
21627 lo
= (value
>> 1) & 0x7ff;
21628 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21629 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21630 newval
|= (S
<< 10) | hi
;
21631 newval2
&= ~T2I1I2MASK
;
21632 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21633 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21634 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21638 md_apply_fix (fixS
* fixP
,
21642 offsetT value
= * valP
;
21644 unsigned int newimm
;
21645 unsigned long temp
;
21647 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
21649 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
21651 /* Note whether this will delete the relocation. */
21653 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
21656 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21657 consistency with the behaviour on 32-bit hosts. Remember value
21659 value
&= 0xffffffff;
21660 value
^= 0x80000000;
21661 value
-= 0x80000000;
21664 fixP
->fx_addnumber
= value
;
21666 /* Same treatment for fixP->fx_offset. */
21667 fixP
->fx_offset
&= 0xffffffff;
21668 fixP
->fx_offset
^= 0x80000000;
21669 fixP
->fx_offset
-= 0x80000000;
21671 switch (fixP
->fx_r_type
)
21673 case BFD_RELOC_NONE
:
21674 /* This will need to go in the object file. */
21678 case BFD_RELOC_ARM_IMMEDIATE
:
21679 /* We claim that this fixup has been processed here,
21680 even if in fact we generate an error because we do
21681 not have a reloc for it, so tc_gen_reloc will reject it. */
21684 if (fixP
->fx_addsy
)
21686 const char *msg
= 0;
21688 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21689 msg
= _("undefined symbol %s used as an immediate value");
21690 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21691 msg
= _("symbol %s is in a different section");
21692 else if (S_IS_WEAK (fixP
->fx_addsy
))
21693 msg
= _("symbol %s is weak and may be overridden later");
21697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21698 msg
, S_GET_NAME (fixP
->fx_addsy
));
21703 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21705 /* If the offset is negative, we should use encoding A2 for ADR. */
21706 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
21707 newimm
= negate_data_op (&temp
, value
);
21710 newimm
= encode_arm_immediate (value
);
21712 /* If the instruction will fail, see if we can fix things up by
21713 changing the opcode. */
21714 if (newimm
== (unsigned int) FAIL
)
21715 newimm
= negate_data_op (&temp
, value
);
21718 if (newimm
== (unsigned int) FAIL
)
21720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21721 _("invalid constant (%lx) after fixup"),
21722 (unsigned long) value
);
21726 newimm
|= (temp
& 0xfffff000);
21727 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21730 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21732 unsigned int highpart
= 0;
21733 unsigned int newinsn
= 0xe1a00000; /* nop. */
21735 if (fixP
->fx_addsy
)
21737 const char *msg
= 0;
21739 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21740 msg
= _("undefined symbol %s used as an immediate value");
21741 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21742 msg
= _("symbol %s is in a different section");
21743 else if (S_IS_WEAK (fixP
->fx_addsy
))
21744 msg
= _("symbol %s is weak and may be overridden later");
21748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21749 msg
, S_GET_NAME (fixP
->fx_addsy
));
21754 newimm
= encode_arm_immediate (value
);
21755 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21757 /* If the instruction will fail, see if we can fix things up by
21758 changing the opcode. */
21759 if (newimm
== (unsigned int) FAIL
21760 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
21762 /* No ? OK - try using two ADD instructions to generate
21764 newimm
= validate_immediate_twopart (value
, & highpart
);
21766 /* Yes - then make sure that the second instruction is
21768 if (newimm
!= (unsigned int) FAIL
)
21770 /* Still No ? Try using a negated value. */
21771 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
21772 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
21773 /* Otherwise - give up. */
21776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21777 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21782 /* Replace the first operand in the 2nd instruction (which
21783 is the PC) with the destination register. We have
21784 already added in the PC in the first instruction and we
21785 do not want to do it again. */
21786 newinsn
&= ~ 0xf0000;
21787 newinsn
|= ((newinsn
& 0x0f000) << 4);
21790 newimm
|= (temp
& 0xfffff000);
21791 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21793 highpart
|= (newinsn
& 0xfffff000);
21794 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
21798 case BFD_RELOC_ARM_OFFSET_IMM
:
21799 if (!fixP
->fx_done
&& seg
->use_rela_p
)
21802 case BFD_RELOC_ARM_LITERAL
:
21808 if (validate_offset_imm (value
, 0) == FAIL
)
21810 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
21811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21812 _("invalid literal constant: pool needs to be closer"));
21814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21815 _("bad immediate value for offset (%ld)"),
21820 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21822 newval
&= 0xfffff000;
21825 newval
&= 0xff7ff000;
21826 newval
|= value
| (sign
? INDEX_UP
: 0);
21828 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21831 case BFD_RELOC_ARM_OFFSET_IMM8
:
21832 case BFD_RELOC_ARM_HWLITERAL
:
21838 if (validate_offset_imm (value
, 1) == FAIL
)
21840 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
21841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21842 _("invalid literal constant: pool needs to be closer"));
21844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21845 _("bad immediate value for 8-bit offset (%ld)"),
21850 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21852 newval
&= 0xfffff0f0;
21855 newval
&= 0xff7ff0f0;
21856 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
21858 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21861 case BFD_RELOC_ARM_T32_OFFSET_U8
:
21862 if (value
< 0 || value
> 1020 || value
% 4 != 0)
21863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21864 _("bad immediate value for offset (%ld)"), (long) value
);
21867 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
21869 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
21872 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21873 /* This is a complicated relocation used for all varieties of Thumb32
21874 load/store instruction with immediate offset:
21876 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21877 *4, optional writeback(W)
21878 (doubleword load/store)
21880 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21881 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21882 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21883 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21884 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21886 Uppercase letters indicate bits that are already encoded at
21887 this point. Lowercase letters are our problem. For the
21888 second block of instructions, the secondary opcode nybble
21889 (bits 8..11) is present, and bit 23 is zero, even if this is
21890 a PC-relative operation. */
21891 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21893 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
21895 if ((newval
& 0xf0000000) == 0xe0000000)
21897 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21899 newval
|= (1 << 23);
21902 if (value
% 4 != 0)
21904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21905 _("offset not a multiple of 4"));
21911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21912 _("offset out of range"));
21917 else if ((newval
& 0x000f0000) == 0x000f0000)
21919 /* PC-relative, 12-bit offset. */
21921 newval
|= (1 << 23);
21926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21927 _("offset out of range"));
21932 else if ((newval
& 0x00000100) == 0x00000100)
21934 /* Writeback: 8-bit, +/- offset. */
21936 newval
|= (1 << 9);
21941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21942 _("offset out of range"));
21947 else if ((newval
& 0x00000f00) == 0x00000e00)
21949 /* T-instruction: positive 8-bit offset. */
21950 if (value
< 0 || value
> 0xff)
21952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21953 _("offset out of range"));
21961 /* Positive 12-bit or negative 8-bit offset. */
21965 newval
|= (1 << 23);
21975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21976 _("offset out of range"));
21983 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
21984 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
21987 case BFD_RELOC_ARM_SHIFT_IMM
:
21988 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21989 if (((unsigned long) value
) > 32
21991 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
21993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21994 _("shift expression is too large"));
21999 /* Shifts of zero must be done as lsl. */
22001 else if (value
== 32)
22003 newval
&= 0xfffff07f;
22004 newval
|= (value
& 0x1f) << 7;
22005 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22008 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22009 case BFD_RELOC_ARM_T32_ADD_IMM
:
22010 case BFD_RELOC_ARM_T32_IMM12
:
22011 case BFD_RELOC_ARM_T32_ADD_PC12
:
22012 /* We claim that this fixup has been processed here,
22013 even if in fact we generate an error because we do
22014 not have a reloc for it, so tc_gen_reloc will reject it. */
22018 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22021 _("undefined symbol %s used as an immediate value"),
22022 S_GET_NAME (fixP
->fx_addsy
));
22026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22028 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22031 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22032 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22034 newimm
= encode_thumb32_immediate (value
);
22035 if (newimm
== (unsigned int) FAIL
)
22036 newimm
= thumb32_negate_data_op (&newval
, value
);
22038 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22039 && newimm
== (unsigned int) FAIL
)
22041 /* Turn add/sum into addw/subw. */
22042 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22043 newval
= (newval
& 0xfeffffff) | 0x02000000;
22044 /* No flat 12-bit imm encoding for addsw/subsw. */
22045 if ((newval
& 0x00100000) == 0)
22047 /* 12 bit immediate for addw/subw. */
22051 newval
^= 0x00a00000;
22054 newimm
= (unsigned int) FAIL
;
22060 if (newimm
== (unsigned int)FAIL
)
22062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22063 _("invalid constant (%lx) after fixup"),
22064 (unsigned long) value
);
22068 newval
|= (newimm
& 0x800) << 15;
22069 newval
|= (newimm
& 0x700) << 4;
22070 newval
|= (newimm
& 0x0ff);
22072 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22073 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22076 case BFD_RELOC_ARM_SMC
:
22077 if (((unsigned long) value
) > 0xffff)
22078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22079 _("invalid smc expression"));
22080 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22081 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22082 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22085 case BFD_RELOC_ARM_HVC
:
22086 if (((unsigned long) value
) > 0xffff)
22087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22088 _("invalid hvc expression"));
22089 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22090 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22091 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22094 case BFD_RELOC_ARM_SWI
:
22095 if (fixP
->tc_fix_data
!= 0)
22097 if (((unsigned long) value
) > 0xff)
22098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22099 _("invalid swi expression"));
22100 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22102 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22106 if (((unsigned long) value
) > 0x00ffffff)
22107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22108 _("invalid swi expression"));
22109 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22111 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22115 case BFD_RELOC_ARM_MULTI
:
22116 if (((unsigned long) value
) > 0xffff)
22117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22118 _("invalid expression in load/store multiple"));
22119 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22120 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22124 case BFD_RELOC_ARM_PCREL_CALL
:
22126 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22128 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22129 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22130 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22131 /* Flip the bl to blx. This is a simple flip
22132 bit here because we generate PCREL_CALL for
22133 unconditional bls. */
22135 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22136 newval
= newval
| 0x10000000;
22137 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22143 goto arm_branch_common
;
22145 case BFD_RELOC_ARM_PCREL_JUMP
:
22146 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22148 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22149 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22150 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22152 /* This would map to a bl<cond>, b<cond>,
22153 b<always> to a Thumb function. We
22154 need to force a relocation for this particular
22156 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22160 case BFD_RELOC_ARM_PLT32
:
22162 case BFD_RELOC_ARM_PCREL_BRANCH
:
22164 goto arm_branch_common
;
22166 case BFD_RELOC_ARM_PCREL_BLX
:
22169 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22171 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22172 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22173 && ARM_IS_FUNC (fixP
->fx_addsy
))
22175 /* Flip the blx to a bl and warn. */
22176 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22177 newval
= 0xeb000000;
22178 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22179 _("blx to '%s' an ARM ISA state function changed to bl"),
22181 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22187 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22188 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22192 /* We are going to store value (shifted right by two) in the
22193 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22194 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22195 also be be clear. */
22197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22198 _("misaligned branch destination"));
22199 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22200 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22203 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22205 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22206 newval
|= (value
>> 2) & 0x00ffffff;
22207 /* Set the H bit on BLX instructions. */
22211 newval
|= 0x01000000;
22213 newval
&= ~0x01000000;
22215 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22219 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22220 /* CBZ can only branch forward. */
22222 /* Attempts to use CBZ to branch to the next instruction
22223 (which, strictly speaking, are prohibited) will be turned into
22226 FIXME: It may be better to remove the instruction completely and
22227 perform relaxation. */
22230 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22231 newval
= 0xbf00; /* NOP encoding T1 */
22232 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22239 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22241 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22242 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22243 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22248 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22249 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22252 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22254 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22255 newval
|= (value
& 0x1ff) >> 1;
22256 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22260 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22261 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22264 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22266 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22267 newval
|= (value
& 0xfff) >> 1;
22268 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22272 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22274 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22275 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22276 && ARM_IS_FUNC (fixP
->fx_addsy
)
22277 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22279 /* Force a relocation for a branch 20 bits wide. */
22282 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22284 _("conditional branch out of range"));
22286 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22289 addressT S
, J1
, J2
, lo
, hi
;
22291 S
= (value
& 0x00100000) >> 20;
22292 J2
= (value
& 0x00080000) >> 19;
22293 J1
= (value
& 0x00040000) >> 18;
22294 hi
= (value
& 0x0003f000) >> 12;
22295 lo
= (value
& 0x00000ffe) >> 1;
22297 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22298 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22299 newval
|= (S
<< 10) | hi
;
22300 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22301 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22302 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22306 case BFD_RELOC_THUMB_PCREL_BLX
:
22307 /* If there is a blx from a thumb state function to
22308 another thumb function flip this to a bl and warn
22312 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22313 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22314 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22316 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22317 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22318 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22320 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22321 newval
= newval
| 0x1000;
22322 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22323 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22328 goto thumb_bl_common
;
22330 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22331 /* A bl from Thumb state ISA to an internal ARM state function
22332 is converted to a blx. */
22334 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22335 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22336 && ARM_IS_FUNC (fixP
->fx_addsy
)
22337 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22339 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22340 newval
= newval
& ~0x1000;
22341 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22342 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22348 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22349 /* For a BLX instruction, make sure that the relocation is rounded up
22350 to a word boundary. This follows the semantics of the instruction
22351 which specifies that bit 1 of the target address will come from bit
22352 1 of the base address. */
22353 value
= (value
+ 3) & ~ 3;
22356 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22357 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22358 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22361 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22363 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22365 else if ((value
& ~0x1ffffff)
22366 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22368 _("Thumb2 branch out of range"));
22371 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22372 encode_thumb2_b_bl_offset (buf
, value
);
22376 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22377 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22380 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22381 encode_thumb2_b_bl_offset (buf
, value
);
22386 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22387 md_number_to_chars (buf
, value
, 1);
22391 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22392 md_number_to_chars (buf
, value
, 2);
22396 case BFD_RELOC_ARM_TLS_CALL
:
22397 case BFD_RELOC_ARM_THM_TLS_CALL
:
22398 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22399 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22400 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22403 case BFD_RELOC_ARM_TLS_GOTDESC
:
22404 case BFD_RELOC_ARM_TLS_GD32
:
22405 case BFD_RELOC_ARM_TLS_LE32
:
22406 case BFD_RELOC_ARM_TLS_IE32
:
22407 case BFD_RELOC_ARM_TLS_LDM32
:
22408 case BFD_RELOC_ARM_TLS_LDO32
:
22409 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22412 case BFD_RELOC_ARM_GOT32
:
22413 case BFD_RELOC_ARM_GOTOFF
:
22414 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22415 md_number_to_chars (buf
, 0, 4);
22418 case BFD_RELOC_ARM_GOT_PREL
:
22419 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22420 md_number_to_chars (buf
, value
, 4);
22423 case BFD_RELOC_ARM_TARGET2
:
22424 /* TARGET2 is not partial-inplace, so we need to write the
22425 addend here for REL targets, because it won't be written out
22426 during reloc processing later. */
22427 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22428 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22432 case BFD_RELOC_RVA
:
22434 case BFD_RELOC_ARM_TARGET1
:
22435 case BFD_RELOC_ARM_ROSEGREL32
:
22436 case BFD_RELOC_ARM_SBREL32
:
22437 case BFD_RELOC_32_PCREL
:
22439 case BFD_RELOC_32_SECREL
:
22441 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22443 /* For WinCE we only do this for pcrel fixups. */
22444 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22446 md_number_to_chars (buf
, value
, 4);
22450 case BFD_RELOC_ARM_PREL31
:
22451 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22453 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22454 if ((value
^ (value
>> 1)) & 0x40000000)
22456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22457 _("rel31 relocation overflow"));
22459 newval
|= value
& 0x7fffffff;
22460 md_number_to_chars (buf
, newval
, 4);
22465 case BFD_RELOC_ARM_CP_OFF_IMM
:
22466 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22467 if (value
< -1023 || value
> 1023 || (value
& 3))
22468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22469 _("co-processor offset out of range"));
22474 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22475 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22476 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22478 newval
= get_thumb32_insn (buf
);
22480 newval
&= 0xffffff00;
22483 newval
&= 0xff7fff00;
22484 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22486 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22487 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22488 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22490 put_thumb32_insn (buf
, newval
);
22493 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22494 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22495 if (value
< -255 || value
> 255)
22496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22497 _("co-processor offset out of range"));
22499 goto cp_off_common
;
22501 case BFD_RELOC_ARM_THUMB_OFFSET
:
22502 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22503 /* Exactly what ranges, and where the offset is inserted depends
22504 on the type of instruction, we can establish this from the
22506 switch (newval
>> 12)
22508 case 4: /* PC load. */
22509 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22510 forced to zero for these loads; md_pcrel_from has already
22511 compensated for this. */
22513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22514 _("invalid offset, target not word aligned (0x%08lX)"),
22515 (((unsigned long) fixP
->fx_frag
->fr_address
22516 + (unsigned long) fixP
->fx_where
) & ~3)
22517 + (unsigned long) value
);
22519 if (value
& ~0x3fc)
22520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22521 _("invalid offset, value too big (0x%08lX)"),
22524 newval
|= value
>> 2;
22527 case 9: /* SP load/store. */
22528 if (value
& ~0x3fc)
22529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22530 _("invalid offset, value too big (0x%08lX)"),
22532 newval
|= value
>> 2;
22535 case 6: /* Word load/store. */
22537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22538 _("invalid offset, value too big (0x%08lX)"),
22540 newval
|= value
<< 4; /* 6 - 2. */
22543 case 7: /* Byte load/store. */
22545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22546 _("invalid offset, value too big (0x%08lX)"),
22548 newval
|= value
<< 6;
22551 case 8: /* Halfword load/store. */
22553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22554 _("invalid offset, value too big (0x%08lX)"),
22556 newval
|= value
<< 5; /* 6 - 1. */
22560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22561 "Unable to process relocation for thumb opcode: %lx",
22562 (unsigned long) newval
);
22565 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22568 case BFD_RELOC_ARM_THUMB_ADD
:
22569 /* This is a complicated relocation, since we use it for all of
22570 the following immediate relocations:
22574 9bit ADD/SUB SP word-aligned
22575 10bit ADD PC/SP word-aligned
22577 The type of instruction being processed is encoded in the
22584 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22586 int rd
= (newval
>> 4) & 0xf;
22587 int rs
= newval
& 0xf;
22588 int subtract
= !!(newval
& 0x8000);
22590 /* Check for HI regs, only very restricted cases allowed:
22591 Adjusting SP, and using PC or SP to get an address. */
22592 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22593 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22595 _("invalid Hi register with immediate"));
22597 /* If value is negative, choose the opposite instruction. */
22601 subtract
= !subtract
;
22603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22604 _("immediate value out of range"));
22609 if (value
& ~0x1fc)
22610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22611 _("invalid immediate for stack address calculation"));
22612 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22613 newval
|= value
>> 2;
22615 else if (rs
== REG_PC
|| rs
== REG_SP
)
22617 if (subtract
|| value
& ~0x3fc)
22618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22619 _("invalid immediate for address calculation (value = 0x%08lX)"),
22620 (unsigned long) value
);
22621 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22623 newval
|= value
>> 2;
22628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22629 _("immediate value out of range"));
22630 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22631 newval
|= (rd
<< 8) | value
;
22636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22637 _("immediate value out of range"));
22638 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22639 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22642 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22645 case BFD_RELOC_ARM_THUMB_IMM
:
22646 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22647 if (value
< 0 || value
> 255)
22648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22649 _("invalid immediate: %ld is out of range"),
22652 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22655 case BFD_RELOC_ARM_THUMB_SHIFT
:
22656 /* 5bit shift value (0..32). LSL cannot take 32. */
22657 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
22658 temp
= newval
& 0xf800;
22659 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
22660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22661 _("invalid shift value: %ld"), (long) value
);
22662 /* Shifts of zero must be encoded as LSL. */
22664 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
22665 /* Shifts of 32 are encoded as zero. */
22666 else if (value
== 32)
22668 newval
|= value
<< 6;
22669 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22672 case BFD_RELOC_VTABLE_INHERIT
:
22673 case BFD_RELOC_VTABLE_ENTRY
:
22677 case BFD_RELOC_ARM_MOVW
:
22678 case BFD_RELOC_ARM_MOVT
:
22679 case BFD_RELOC_ARM_THUMB_MOVW
:
22680 case BFD_RELOC_ARM_THUMB_MOVT
:
22681 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22683 /* REL format relocations are limited to a 16-bit addend. */
22684 if (!fixP
->fx_done
)
22686 if (value
< -0x8000 || value
> 0x7fff)
22687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22688 _("offset out of range"));
22690 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22691 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22696 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22697 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22699 newval
= get_thumb32_insn (buf
);
22700 newval
&= 0xfbf08f00;
22701 newval
|= (value
& 0xf000) << 4;
22702 newval
|= (value
& 0x0800) << 15;
22703 newval
|= (value
& 0x0700) << 4;
22704 newval
|= (value
& 0x00ff);
22705 put_thumb32_insn (buf
, newval
);
22709 newval
= md_chars_to_number (buf
, 4);
22710 newval
&= 0xfff0f000;
22711 newval
|= value
& 0x0fff;
22712 newval
|= (value
& 0xf000) << 4;
22713 md_number_to_chars (buf
, newval
, 4);
22718 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22719 case BFD_RELOC_ARM_ALU_PC_G0
:
22720 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22721 case BFD_RELOC_ARM_ALU_PC_G1
:
22722 case BFD_RELOC_ARM_ALU_PC_G2
:
22723 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22724 case BFD_RELOC_ARM_ALU_SB_G0
:
22725 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22726 case BFD_RELOC_ARM_ALU_SB_G1
:
22727 case BFD_RELOC_ARM_ALU_SB_G2
:
22728 gas_assert (!fixP
->fx_done
);
22729 if (!seg
->use_rela_p
)
22732 bfd_vma encoded_addend
;
22733 bfd_vma addend_abs
= abs (value
);
22735 /* Check that the absolute value of the addend can be
22736 expressed as an 8-bit constant plus a rotation. */
22737 encoded_addend
= encode_arm_immediate (addend_abs
);
22738 if (encoded_addend
== (unsigned int) FAIL
)
22739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22740 _("the offset 0x%08lX is not representable"),
22741 (unsigned long) addend_abs
);
22743 /* Extract the instruction. */
22744 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22746 /* If the addend is positive, use an ADD instruction.
22747 Otherwise use a SUB. Take care not to destroy the S bit. */
22748 insn
&= 0xff1fffff;
22754 /* Place the encoded addend into the first 12 bits of the
22756 insn
&= 0xfffff000;
22757 insn
|= encoded_addend
;
22759 /* Update the instruction. */
22760 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22764 case BFD_RELOC_ARM_LDR_PC_G0
:
22765 case BFD_RELOC_ARM_LDR_PC_G1
:
22766 case BFD_RELOC_ARM_LDR_PC_G2
:
22767 case BFD_RELOC_ARM_LDR_SB_G0
:
22768 case BFD_RELOC_ARM_LDR_SB_G1
:
22769 case BFD_RELOC_ARM_LDR_SB_G2
:
22770 gas_assert (!fixP
->fx_done
);
22771 if (!seg
->use_rela_p
)
22774 bfd_vma addend_abs
= abs (value
);
22776 /* Check that the absolute value of the addend can be
22777 encoded in 12 bits. */
22778 if (addend_abs
>= 0x1000)
22779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22780 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22781 (unsigned long) addend_abs
);
22783 /* Extract the instruction. */
22784 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22786 /* If the addend is negative, clear bit 23 of the instruction.
22787 Otherwise set it. */
22789 insn
&= ~(1 << 23);
22793 /* Place the absolute value of the addend into the first 12 bits
22794 of the instruction. */
22795 insn
&= 0xfffff000;
22796 insn
|= addend_abs
;
22798 /* Update the instruction. */
22799 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22803 case BFD_RELOC_ARM_LDRS_PC_G0
:
22804 case BFD_RELOC_ARM_LDRS_PC_G1
:
22805 case BFD_RELOC_ARM_LDRS_PC_G2
:
22806 case BFD_RELOC_ARM_LDRS_SB_G0
:
22807 case BFD_RELOC_ARM_LDRS_SB_G1
:
22808 case BFD_RELOC_ARM_LDRS_SB_G2
:
22809 gas_assert (!fixP
->fx_done
);
22810 if (!seg
->use_rela_p
)
22813 bfd_vma addend_abs
= abs (value
);
22815 /* Check that the absolute value of the addend can be
22816 encoded in 8 bits. */
22817 if (addend_abs
>= 0x100)
22818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22819 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22820 (unsigned long) addend_abs
);
22822 /* Extract the instruction. */
22823 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22825 /* If the addend is negative, clear bit 23 of the instruction.
22826 Otherwise set it. */
22828 insn
&= ~(1 << 23);
22832 /* Place the first four bits of the absolute value of the addend
22833 into the first 4 bits of the instruction, and the remaining
22834 four into bits 8 .. 11. */
22835 insn
&= 0xfffff0f0;
22836 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
22838 /* Update the instruction. */
22839 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22843 case BFD_RELOC_ARM_LDC_PC_G0
:
22844 case BFD_RELOC_ARM_LDC_PC_G1
:
22845 case BFD_RELOC_ARM_LDC_PC_G2
:
22846 case BFD_RELOC_ARM_LDC_SB_G0
:
22847 case BFD_RELOC_ARM_LDC_SB_G1
:
22848 case BFD_RELOC_ARM_LDC_SB_G2
:
22849 gas_assert (!fixP
->fx_done
);
22850 if (!seg
->use_rela_p
)
22853 bfd_vma addend_abs
= abs (value
);
22855 /* Check that the absolute value of the addend is a multiple of
22856 four and, when divided by four, fits in 8 bits. */
22857 if (addend_abs
& 0x3)
22858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22859 _("bad offset 0x%08lX (must be word-aligned)"),
22860 (unsigned long) addend_abs
);
22862 if ((addend_abs
>> 2) > 0xff)
22863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22864 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22865 (unsigned long) addend_abs
);
22867 /* Extract the instruction. */
22868 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22870 /* If the addend is negative, clear bit 23 of the instruction.
22871 Otherwise set it. */
22873 insn
&= ~(1 << 23);
22877 /* Place the addend (divided by four) into the first eight
22878 bits of the instruction. */
22879 insn
&= 0xfffffff0;
22880 insn
|= addend_abs
>> 2;
22882 /* Update the instruction. */
22883 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22887 case BFD_RELOC_ARM_V4BX
:
22888 /* This will need to go in the object file. */
22892 case BFD_RELOC_UNUSED
:
22894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22895 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
22899 /* Translate internal representation of relocation info to BFD target
22903 tc_gen_reloc (asection
*section
, fixS
*fixp
)
22906 bfd_reloc_code_real_type code
;
22908 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
22910 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
22911 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
22912 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
22914 if (fixp
->fx_pcrel
)
22916 if (section
->use_rela_p
)
22917 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
22919 fixp
->fx_offset
= reloc
->address
;
22921 reloc
->addend
= fixp
->fx_offset
;
22923 switch (fixp
->fx_r_type
)
22926 if (fixp
->fx_pcrel
)
22928 code
= BFD_RELOC_8_PCREL
;
22933 if (fixp
->fx_pcrel
)
22935 code
= BFD_RELOC_16_PCREL
;
22940 if (fixp
->fx_pcrel
)
22942 code
= BFD_RELOC_32_PCREL
;
22946 case BFD_RELOC_ARM_MOVW
:
22947 if (fixp
->fx_pcrel
)
22949 code
= BFD_RELOC_ARM_MOVW_PCREL
;
22953 case BFD_RELOC_ARM_MOVT
:
22954 if (fixp
->fx_pcrel
)
22956 code
= BFD_RELOC_ARM_MOVT_PCREL
;
22960 case BFD_RELOC_ARM_THUMB_MOVW
:
22961 if (fixp
->fx_pcrel
)
22963 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
22967 case BFD_RELOC_ARM_THUMB_MOVT
:
22968 if (fixp
->fx_pcrel
)
22970 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
22974 case BFD_RELOC_NONE
:
22975 case BFD_RELOC_ARM_PCREL_BRANCH
:
22976 case BFD_RELOC_ARM_PCREL_BLX
:
22977 case BFD_RELOC_RVA
:
22978 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22979 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22980 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22981 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22982 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22983 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22984 case BFD_RELOC_VTABLE_ENTRY
:
22985 case BFD_RELOC_VTABLE_INHERIT
:
22987 case BFD_RELOC_32_SECREL
:
22989 code
= fixp
->fx_r_type
;
22992 case BFD_RELOC_THUMB_PCREL_BLX
:
22994 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22995 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22998 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23001 case BFD_RELOC_ARM_LITERAL
:
23002 case BFD_RELOC_ARM_HWLITERAL
:
23003 /* If this is called then the a literal has
23004 been referenced across a section boundary. */
23005 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23006 _("literal referenced across section boundary"));
23010 case BFD_RELOC_ARM_TLS_CALL
:
23011 case BFD_RELOC_ARM_THM_TLS_CALL
:
23012 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23013 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23014 case BFD_RELOC_ARM_GOT32
:
23015 case BFD_RELOC_ARM_GOTOFF
:
23016 case BFD_RELOC_ARM_GOT_PREL
:
23017 case BFD_RELOC_ARM_PLT32
:
23018 case BFD_RELOC_ARM_TARGET1
:
23019 case BFD_RELOC_ARM_ROSEGREL32
:
23020 case BFD_RELOC_ARM_SBREL32
:
23021 case BFD_RELOC_ARM_PREL31
:
23022 case BFD_RELOC_ARM_TARGET2
:
23023 case BFD_RELOC_ARM_TLS_LE32
:
23024 case BFD_RELOC_ARM_TLS_LDO32
:
23025 case BFD_RELOC_ARM_PCREL_CALL
:
23026 case BFD_RELOC_ARM_PCREL_JUMP
:
23027 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23028 case BFD_RELOC_ARM_ALU_PC_G0
:
23029 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23030 case BFD_RELOC_ARM_ALU_PC_G1
:
23031 case BFD_RELOC_ARM_ALU_PC_G2
:
23032 case BFD_RELOC_ARM_LDR_PC_G0
:
23033 case BFD_RELOC_ARM_LDR_PC_G1
:
23034 case BFD_RELOC_ARM_LDR_PC_G2
:
23035 case BFD_RELOC_ARM_LDRS_PC_G0
:
23036 case BFD_RELOC_ARM_LDRS_PC_G1
:
23037 case BFD_RELOC_ARM_LDRS_PC_G2
:
23038 case BFD_RELOC_ARM_LDC_PC_G0
:
23039 case BFD_RELOC_ARM_LDC_PC_G1
:
23040 case BFD_RELOC_ARM_LDC_PC_G2
:
23041 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23042 case BFD_RELOC_ARM_ALU_SB_G0
:
23043 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23044 case BFD_RELOC_ARM_ALU_SB_G1
:
23045 case BFD_RELOC_ARM_ALU_SB_G2
:
23046 case BFD_RELOC_ARM_LDR_SB_G0
:
23047 case BFD_RELOC_ARM_LDR_SB_G1
:
23048 case BFD_RELOC_ARM_LDR_SB_G2
:
23049 case BFD_RELOC_ARM_LDRS_SB_G0
:
23050 case BFD_RELOC_ARM_LDRS_SB_G1
:
23051 case BFD_RELOC_ARM_LDRS_SB_G2
:
23052 case BFD_RELOC_ARM_LDC_SB_G0
:
23053 case BFD_RELOC_ARM_LDC_SB_G1
:
23054 case BFD_RELOC_ARM_LDC_SB_G2
:
23055 case BFD_RELOC_ARM_V4BX
:
23056 code
= fixp
->fx_r_type
;
23059 case BFD_RELOC_ARM_TLS_GOTDESC
:
23060 case BFD_RELOC_ARM_TLS_GD32
:
23061 case BFD_RELOC_ARM_TLS_IE32
:
23062 case BFD_RELOC_ARM_TLS_LDM32
:
23063 /* BFD will include the symbol's address in the addend.
23064 But we don't want that, so subtract it out again here. */
23065 if (!S_IS_COMMON (fixp
->fx_addsy
))
23066 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23067 code
= fixp
->fx_r_type
;
23071 case BFD_RELOC_ARM_IMMEDIATE
:
23072 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23073 _("internal relocation (type: IMMEDIATE) not fixed up"));
23076 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23077 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23078 _("ADRL used for a symbol not defined in the same file"));
23081 case BFD_RELOC_ARM_OFFSET_IMM
:
23082 if (section
->use_rela_p
)
23084 code
= fixp
->fx_r_type
;
23088 if (fixp
->fx_addsy
!= NULL
23089 && !S_IS_DEFINED (fixp
->fx_addsy
)
23090 && S_IS_LOCAL (fixp
->fx_addsy
))
23092 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23093 _("undefined local label `%s'"),
23094 S_GET_NAME (fixp
->fx_addsy
));
23098 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23099 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23106 switch (fixp
->fx_r_type
)
23108 case BFD_RELOC_NONE
: type
= "NONE"; break;
23109 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23110 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23111 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23112 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23113 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23114 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23115 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23116 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23117 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23118 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23119 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23120 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23121 default: type
= _("<unknown>"); break;
23123 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23124 _("cannot represent %s relocation in this object file format"),
23131 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23133 && fixp
->fx_addsy
== GOT_symbol
)
23135 code
= BFD_RELOC_ARM_GOTPC
;
23136 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23140 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23142 if (reloc
->howto
== NULL
)
23144 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23145 _("cannot represent %s relocation in this object file format"),
23146 bfd_get_reloc_code_name (code
));
23150 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23151 vtable entry to be used in the relocation's section offset. */
23152 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23153 reloc
->address
= fixp
->fx_offset
;
23158 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23161 cons_fix_new_arm (fragS
* frag
,
23165 bfd_reloc_code_real_type reloc
)
23170 FIXME: @@ Should look at CPU word size. */
23174 reloc
= BFD_RELOC_8
;
23177 reloc
= BFD_RELOC_16
;
23181 reloc
= BFD_RELOC_32
;
23184 reloc
= BFD_RELOC_64
;
23189 if (exp
->X_op
== O_secrel
)
23191 exp
->X_op
= O_symbol
;
23192 reloc
= BFD_RELOC_32_SECREL
;
23196 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23199 #if defined (OBJ_COFF)
23201 arm_validate_fix (fixS
* fixP
)
23203 /* If the destination of the branch is a defined symbol which does not have
23204 the THUMB_FUNC attribute, then we must be calling a function which has
23205 the (interfacearm) attribute. We look for the Thumb entry point to that
23206 function and change the branch to refer to that function instead. */
23207 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23208 && fixP
->fx_addsy
!= NULL
23209 && S_IS_DEFINED (fixP
->fx_addsy
)
23210 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23212 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23219 arm_force_relocation (struct fix
* fixp
)
23221 #if defined (OBJ_COFF) && defined (TE_PE)
23222 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23226 /* In case we have a call or a branch to a function in ARM ISA mode from
23227 a thumb function or vice-versa force the relocation. These relocations
23228 are cleared off for some cores that might have blx and simple transformations
23232 switch (fixp
->fx_r_type
)
23234 case BFD_RELOC_ARM_PCREL_JUMP
:
23235 case BFD_RELOC_ARM_PCREL_CALL
:
23236 case BFD_RELOC_THUMB_PCREL_BLX
:
23237 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23241 case BFD_RELOC_ARM_PCREL_BLX
:
23242 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23243 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23244 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23245 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23254 /* Resolve these relocations even if the symbol is extern or weak.
23255 Technically this is probably wrong due to symbol preemption.
23256 In practice these relocations do not have enough range to be useful
23257 at dynamic link time, and some code (e.g. in the Linux kernel)
23258 expects these references to be resolved. */
23259 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23260 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23261 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23262 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23263 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23264 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23265 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23266 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23267 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23268 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23269 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23270 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23271 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23272 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23275 /* Always leave these relocations for the linker. */
23276 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23277 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23278 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23281 /* Always generate relocations against function symbols. */
23282 if (fixp
->fx_r_type
== BFD_RELOC_32
23284 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23287 return generic_force_reloc (fixp
);
23290 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23291 /* Relocations against function names must be left unadjusted,
23292 so that the linker can use this information to generate interworking
23293 stubs. The MIPS version of this function
23294 also prevents relocations that are mips-16 specific, but I do not
23295 know why it does this.
23298 There is one other problem that ought to be addressed here, but
23299 which currently is not: Taking the address of a label (rather
23300 than a function) and then later jumping to that address. Such
23301 addresses also ought to have their bottom bit set (assuming that
23302 they reside in Thumb code), but at the moment they will not. */
23305 arm_fix_adjustable (fixS
* fixP
)
23307 if (fixP
->fx_addsy
== NULL
)
23310 /* Preserve relocations against symbols with function type. */
23311 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23314 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23315 && fixP
->fx_subsy
== NULL
)
23318 /* We need the symbol name for the VTABLE entries. */
23319 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23320 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23323 /* Don't allow symbols to be discarded on GOT related relocs. */
23324 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23325 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23326 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23327 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23328 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23329 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23330 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23331 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23332 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23333 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23334 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23335 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23336 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23337 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23340 /* Similarly for group relocations. */
23341 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23342 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23343 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23346 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23347 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23348 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23349 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23350 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23351 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23352 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23353 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23354 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23359 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23364 elf32_arm_target_format (void)
23367 return (target_big_endian
23368 ? "elf32-bigarm-symbian"
23369 : "elf32-littlearm-symbian");
23370 #elif defined (TE_VXWORKS)
23371 return (target_big_endian
23372 ? "elf32-bigarm-vxworks"
23373 : "elf32-littlearm-vxworks");
23374 #elif defined (TE_NACL)
23375 return (target_big_endian
23376 ? "elf32-bigarm-nacl"
23377 : "elf32-littlearm-nacl");
23379 if (target_big_endian
)
23380 return "elf32-bigarm";
23382 return "elf32-littlearm";
23387 armelf_frob_symbol (symbolS
* symp
,
23390 elf_frob_symbol (symp
, puntp
);
23394 /* MD interface: Finalization. */
23399 literal_pool
* pool
;
23401 /* Ensure that all the IT blocks are properly closed. */
23402 check_it_blocks_finished ();
23404 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23406 /* Put it at the end of the relevant section. */
23407 subseg_set (pool
->section
, pool
->sub_section
);
23409 arm_elf_change_section ();
23416 /* Remove any excess mapping symbols generated for alignment frags in
23417 SEC. We may have created a mapping symbol before a zero byte
23418 alignment; remove it if there's a mapping symbol after the
23421 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23422 void *dummy ATTRIBUTE_UNUSED
)
23424 segment_info_type
*seginfo
= seg_info (sec
);
23427 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23430 for (fragp
= seginfo
->frchainP
->frch_root
;
23432 fragp
= fragp
->fr_next
)
23434 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23435 fragS
*next
= fragp
->fr_next
;
23437 /* Variable-sized frags have been converted to fixed size by
23438 this point. But if this was variable-sized to start with,
23439 there will be a fixed-size frag after it. So don't handle
23441 if (sym
== NULL
|| next
== NULL
)
23444 if (S_GET_VALUE (sym
) < next
->fr_address
)
23445 /* Not at the end of this frag. */
23447 know (S_GET_VALUE (sym
) == next
->fr_address
);
23451 if (next
->tc_frag_data
.first_map
!= NULL
)
23453 /* Next frag starts with a mapping symbol. Discard this
23455 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23459 if (next
->fr_next
== NULL
)
23461 /* This mapping symbol is at the end of the section. Discard
23463 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23464 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23468 /* As long as we have empty frags without any mapping symbols,
23470 /* If the next frag is non-empty and does not start with a
23471 mapping symbol, then this mapping symbol is required. */
23472 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23475 next
= next
->fr_next
;
23477 while (next
!= NULL
);
23482 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23486 arm_adjust_symtab (void)
23491 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23493 if (ARM_IS_THUMB (sym
))
23495 if (THUMB_IS_FUNC (sym
))
23497 /* Mark the symbol as a Thumb function. */
23498 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23499 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23500 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23502 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23503 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23505 as_bad (_("%s: unexpected function type: %d"),
23506 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23508 else switch (S_GET_STORAGE_CLASS (sym
))
23511 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23514 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23517 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23525 if (ARM_IS_INTERWORK (sym
))
23526 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23533 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23535 if (ARM_IS_THUMB (sym
))
23537 elf_symbol_type
* elf_sym
;
23539 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23540 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23542 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23543 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23545 /* If it's a .thumb_func, declare it as so,
23546 otherwise tag label as .code 16. */
23547 if (THUMB_IS_FUNC (sym
))
23548 elf_sym
->internal_elf_sym
.st_target_internal
23549 = ST_BRANCH_TO_THUMB
;
23550 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23551 elf_sym
->internal_elf_sym
.st_info
=
23552 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23557 /* Remove any overlapping mapping symbols generated by alignment frags. */
23558 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23559 /* Now do generic ELF adjustments. */
23560 elf_adjust_symtab ();
23564 /* MD interface: Initialization. */
23567 set_constant_flonums (void)
23571 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23572 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23576 /* Auto-select Thumb mode if it's the only available instruction set for the
23577 given architecture. */
23580 autoselect_thumb_from_cpu_variant (void)
23582 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23583 opcode_select (16);
23592 if ( (arm_ops_hsh
= hash_new ()) == NULL
23593 || (arm_cond_hsh
= hash_new ()) == NULL
23594 || (arm_shift_hsh
= hash_new ()) == NULL
23595 || (arm_psr_hsh
= hash_new ()) == NULL
23596 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23597 || (arm_reg_hsh
= hash_new ()) == NULL
23598 || (arm_reloc_hsh
= hash_new ()) == NULL
23599 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23600 as_fatal (_("virtual memory exhausted"));
23602 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23603 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23604 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23605 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23606 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23607 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23608 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23609 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23610 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23611 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23612 (void *) (v7m_psrs
+ i
));
23613 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23614 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23616 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23618 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23619 (void *) (barrier_opt_names
+ i
));
23621 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23623 struct reloc_entry
* entry
= reloc_names
+ i
;
23625 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23626 /* This makes encode_branch() use the EABI versions of this relocation. */
23627 entry
->reloc
= BFD_RELOC_UNUSED
;
23629 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23633 set_constant_flonums ();
23635 /* Set the cpu variant based on the command-line options. We prefer
23636 -mcpu= over -march= if both are set (as for GCC); and we prefer
23637 -mfpu= over any other way of setting the floating point unit.
23638 Use of legacy options with new options are faulted. */
23641 if (mcpu_cpu_opt
|| march_cpu_opt
)
23642 as_bad (_("use of old and new-style options to set CPU type"));
23644 mcpu_cpu_opt
= legacy_cpu
;
23646 else if (!mcpu_cpu_opt
)
23647 mcpu_cpu_opt
= march_cpu_opt
;
23652 as_bad (_("use of old and new-style options to set FPU type"));
23654 mfpu_opt
= legacy_fpu
;
23656 else if (!mfpu_opt
)
23658 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23659 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23660 /* Some environments specify a default FPU. If they don't, infer it
23661 from the processor. */
23663 mfpu_opt
= mcpu_fpu_opt
;
23665 mfpu_opt
= march_fpu_opt
;
23667 mfpu_opt
= &fpu_default
;
23673 if (mcpu_cpu_opt
!= NULL
)
23674 mfpu_opt
= &fpu_default
;
23675 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
23676 mfpu_opt
= &fpu_arch_vfp_v2
;
23678 mfpu_opt
= &fpu_arch_fpa
;
23684 mcpu_cpu_opt
= &cpu_default
;
23685 selected_cpu
= cpu_default
;
23689 selected_cpu
= *mcpu_cpu_opt
;
23691 mcpu_cpu_opt
= &arm_arch_any
;
23694 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23696 autoselect_thumb_from_cpu_variant ();
23698 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
23700 #if defined OBJ_COFF || defined OBJ_ELF
23702 unsigned int flags
= 0;
23704 #if defined OBJ_ELF
23705 flags
= meabi_flags
;
23707 switch (meabi_flags
)
23709 case EF_ARM_EABI_UNKNOWN
:
23711 /* Set the flags in the private structure. */
23712 if (uses_apcs_26
) flags
|= F_APCS26
;
23713 if (support_interwork
) flags
|= F_INTERWORK
;
23714 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
23715 if (pic_code
) flags
|= F_PIC
;
23716 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
23717 flags
|= F_SOFT_FLOAT
;
23719 switch (mfloat_abi_opt
)
23721 case ARM_FLOAT_ABI_SOFT
:
23722 case ARM_FLOAT_ABI_SOFTFP
:
23723 flags
|= F_SOFT_FLOAT
;
23726 case ARM_FLOAT_ABI_HARD
:
23727 if (flags
& F_SOFT_FLOAT
)
23728 as_bad (_("hard-float conflicts with specified fpu"));
23732 /* Using pure-endian doubles (even if soft-float). */
23733 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
23734 flags
|= F_VFP_FLOAT
;
23736 #if defined OBJ_ELF
23737 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
23738 flags
|= EF_ARM_MAVERICK_FLOAT
;
23741 case EF_ARM_EABI_VER4
:
23742 case EF_ARM_EABI_VER5
:
23743 /* No additional flags to set. */
23750 bfd_set_private_flags (stdoutput
, flags
);
23752 /* We have run out flags in the COFF header to encode the
23753 status of ATPCS support, so instead we create a dummy,
23754 empty, debug section called .arm.atpcs. */
23759 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
23763 bfd_set_section_flags
23764 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
23765 bfd_set_section_size (stdoutput
, sec
, 0);
23766 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
23772 /* Record the CPU type as well. */
23773 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
23774 mach
= bfd_mach_arm_iWMMXt2
;
23775 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
23776 mach
= bfd_mach_arm_iWMMXt
;
23777 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
23778 mach
= bfd_mach_arm_XScale
;
23779 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
23780 mach
= bfd_mach_arm_ep9312
;
23781 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
23782 mach
= bfd_mach_arm_5TE
;
23783 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
23785 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23786 mach
= bfd_mach_arm_5T
;
23788 mach
= bfd_mach_arm_5
;
23790 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
23792 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23793 mach
= bfd_mach_arm_4T
;
23795 mach
= bfd_mach_arm_4
;
23797 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
23798 mach
= bfd_mach_arm_3M
;
23799 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
23800 mach
= bfd_mach_arm_3
;
23801 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
23802 mach
= bfd_mach_arm_2a
;
23803 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
23804 mach
= bfd_mach_arm_2
;
23806 mach
= bfd_mach_arm_unknown
;
23808 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
23811 /* Command line processing. */
23814 Invocation line includes a switch not recognized by the base assembler.
23815 See if it's a processor-specific option.
23817 This routine is somewhat complicated by the need for backwards
23818 compatibility (since older releases of gcc can't be changed).
23819 The new options try to make the interface as compatible as
23822 New options (supported) are:
23824 -mcpu=<cpu name> Assemble for selected processor
23825 -march=<architecture name> Assemble for selected architecture
23826 -mfpu=<fpu architecture> Assemble for selected FPU.
23827 -EB/-mbig-endian Big-endian
23828 -EL/-mlittle-endian Little-endian
23829 -k Generate PIC code
23830 -mthumb Start in Thumb mode
23831 -mthumb-interwork Code supports ARM/Thumb interworking
23833 -m[no-]warn-deprecated Warn about deprecated features
23835 For now we will also provide support for:
23837 -mapcs-32 32-bit Program counter
23838 -mapcs-26 26-bit Program counter
23839 -macps-float Floats passed in FP registers
23840 -mapcs-reentrant Reentrant code
23842 (sometime these will probably be replaced with -mapcs=<list of options>
23843 and -matpcs=<list of options>)
23845 The remaining options are only supported for back-wards compatibility.
23846 Cpu variants, the arm part is optional:
23847 -m[arm]1 Currently not supported.
23848 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23849 -m[arm]3 Arm 3 processor
23850 -m[arm]6[xx], Arm 6 processors
23851 -m[arm]7[xx][t][[d]m] Arm 7 processors
23852 -m[arm]8[10] Arm 8 processors
23853 -m[arm]9[20][tdmi] Arm 9 processors
23854 -mstrongarm[110[0]] StrongARM processors
23855 -mxscale XScale processors
23856 -m[arm]v[2345[t[e]]] Arm architectures
23857 -mall All (except the ARM1)
23859 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23860 -mfpe-old (No float load/store multiples)
23861 -mvfpxd VFP Single precision
23863 -mno-fpu Disable all floating point instructions
23865 The following CPU names are recognized:
23866 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23867 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23868 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23869 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23870 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23871 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23872 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23876 const char * md_shortopts
= "m:k";
23878 #ifdef ARM_BI_ENDIAN
23879 #define OPTION_EB (OPTION_MD_BASE + 0)
23880 #define OPTION_EL (OPTION_MD_BASE + 1)
23882 #if TARGET_BYTES_BIG_ENDIAN
23883 #define OPTION_EB (OPTION_MD_BASE + 0)
23885 #define OPTION_EL (OPTION_MD_BASE + 1)
23888 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23890 struct option md_longopts
[] =
23893 {"EB", no_argument
, NULL
, OPTION_EB
},
23896 {"EL", no_argument
, NULL
, OPTION_EL
},
23898 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
23899 {NULL
, no_argument
, NULL
, 0}
23902 size_t md_longopts_size
= sizeof (md_longopts
);
23904 struct arm_option_table
23906 char *option
; /* Option name to match. */
23907 char *help
; /* Help information. */
23908 int *var
; /* Variable to change. */
23909 int value
; /* What to change it to. */
23910 char *deprecated
; /* If non-null, print this message. */
23913 struct arm_option_table arm_opts
[] =
23915 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
23916 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
23917 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23918 &support_interwork
, 1, NULL
},
23919 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
23920 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
23921 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
23923 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
23924 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
23925 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
23926 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
23929 /* These are recognized by the assembler, but have no affect on code. */
23930 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
23931 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
23933 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
23934 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23935 &warn_on_deprecated
, 0, NULL
},
23936 {NULL
, NULL
, NULL
, 0, NULL
}
23939 struct arm_legacy_option_table
23941 char *option
; /* Option name to match. */
23942 const arm_feature_set
**var
; /* Variable to change. */
23943 const arm_feature_set value
; /* What to change it to. */
23944 char *deprecated
; /* If non-null, print this message. */
23947 const struct arm_legacy_option_table arm_legacy_opts
[] =
23949 /* DON'T add any new processors to this list -- we want the whole list
23950 to go away... Add them to the processors table instead. */
23951 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23952 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23953 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23954 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23955 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23956 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23957 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23958 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23959 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23960 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23961 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23962 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23963 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23964 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23965 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23966 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23967 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23968 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23969 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23970 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23971 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23972 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23973 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23974 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23975 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23976 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23977 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23978 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23979 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23980 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23981 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23982 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23983 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23984 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23985 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23986 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23987 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23988 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23989 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23990 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23991 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23992 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23993 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23994 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23995 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23996 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23997 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23998 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23999 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24000 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24001 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24002 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24003 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24004 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24005 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24006 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24007 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24008 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24009 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24010 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24011 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24012 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24013 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24014 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24015 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24016 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24017 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24018 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24019 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24020 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24021 N_("use -mcpu=strongarm110")},
24022 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24023 N_("use -mcpu=strongarm1100")},
24024 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24025 N_("use -mcpu=strongarm1110")},
24026 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24027 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24028 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24030 /* Architecture variants -- don't add any more to this list either. */
24031 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24032 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24033 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24034 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24035 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24036 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24037 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24038 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24039 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24040 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24041 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24042 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24043 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24044 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24045 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24046 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24047 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24048 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24050 /* Floating point variants -- don't add any more to this list either. */
24051 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24052 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24053 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24054 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24055 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24057 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24060 struct arm_cpu_option_table
24064 const arm_feature_set value
;
24065 /* For some CPUs we assume an FPU unless the user explicitly sets
24067 const arm_feature_set default_fpu
;
24068 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24070 const char *canonical_name
;
24073 /* This list should, at a minimum, contain all the cpu names
24074 recognized by GCC. */
24075 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24076 static const struct arm_cpu_option_table arm_cpus
[] =
24078 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24079 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24080 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24081 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24082 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24083 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24084 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24085 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24086 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24087 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24088 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24089 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24090 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24091 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24092 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24093 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24094 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24095 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24096 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24097 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24098 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24099 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24100 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24101 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24102 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24103 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24104 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24105 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24106 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24107 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24108 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24109 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24110 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24111 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24112 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24113 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24114 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24115 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24116 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24117 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24118 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24119 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24120 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24121 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24122 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24123 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24124 /* For V5 or later processors we default to using VFP; but the user
24125 should really set the FPU type explicitly. */
24126 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24127 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24128 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24129 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24130 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24131 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24132 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24133 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24134 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24135 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24136 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24137 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24138 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24139 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24140 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24141 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24142 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24143 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24144 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24145 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24147 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24148 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24149 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24150 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24151 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24152 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24153 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24154 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24155 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24157 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24158 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24159 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24160 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24161 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24162 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24163 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24164 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24165 FPU_NONE
, "Cortex-A5"),
24166 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24168 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24169 ARM_FEATURE (0, FPU_VFP_V3
24170 | FPU_NEON_EXT_V1
),
24172 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24173 ARM_FEATURE (0, FPU_VFP_V3
24174 | FPU_NEON_EXT_V1
),
24176 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24178 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24180 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24182 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24184 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24185 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24187 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24188 FPU_NONE
, "Cortex-R5"),
24189 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24190 FPU_ARCH_VFP_V3D16
,
24192 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24193 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24194 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24195 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24196 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24197 /* ??? XSCALE is really an architecture. */
24198 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24199 /* ??? iwmmxt is not a processor. */
24200 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24201 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24202 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24204 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24205 FPU_ARCH_MAVERICK
, "ARM920T"),
24206 /* Marvell processors. */
24207 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
| ARM_EXT_SEC
, 0),
24208 FPU_ARCH_VFP_V3D16
, NULL
),
24210 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24214 struct arm_arch_option_table
24218 const arm_feature_set value
;
24219 const arm_feature_set default_fpu
;
24222 /* This list should, at a minimum, contain all the architecture names
24223 recognized by GCC. */
24224 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24225 static const struct arm_arch_option_table arm_archs
[] =
24227 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24228 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24229 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24230 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24231 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24232 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24233 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24234 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24235 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24236 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24237 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24238 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24239 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24240 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24241 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24242 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24243 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24244 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24245 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24246 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24247 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24248 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24249 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24250 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24251 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24252 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24253 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24254 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24255 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24256 /* The official spelling of the ARMv7 profile variants is the dashed form.
24257 Accept the non-dashed form for compatibility with old toolchains. */
24258 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24259 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24260 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24261 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24262 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24263 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24264 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24265 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24266 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24267 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24268 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24269 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24270 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24272 #undef ARM_ARCH_OPT
24274 /* ISA extensions in the co-processor and main instruction set space. */
24275 struct arm_option_extension_value_table
24279 const arm_feature_set value
;
24280 const arm_feature_set allowed_archs
;
24283 /* The following table must be in alphabetical order with a NULL last entry.
24285 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24286 static const struct arm_option_extension_value_table arm_extensions
[] =
24288 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE (ARM_EXT_V8
, 0)),
24289 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24290 ARM_FEATURE (ARM_EXT_V8
, 0)),
24291 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
,
24292 ARM_FEATURE (ARM_EXT_V8
, 0)),
24293 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24294 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24295 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
24296 ARM_EXT_OPT ("iwmmxt2",
24297 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
24298 ARM_EXT_OPT ("maverick",
24299 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
24300 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
24301 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24302 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24303 ARM_FEATURE (ARM_EXT_V8
, 0)),
24304 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
24305 ARM_FEATURE (ARM_EXT_V6M
, 0)),
24306 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
24307 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
24308 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
24310 ARM_FEATURE (ARM_EXT_V7A
, 0)),
24311 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
24312 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24316 /* ISA floating-point and Advanced SIMD extensions. */
24317 struct arm_option_fpu_value_table
24320 const arm_feature_set value
;
24323 /* This list should, at a minimum, contain all the fpu names
24324 recognized by GCC. */
24325 static const struct arm_option_fpu_value_table arm_fpus
[] =
24327 {"softfpa", FPU_NONE
},
24328 {"fpe", FPU_ARCH_FPE
},
24329 {"fpe2", FPU_ARCH_FPE
},
24330 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24331 {"fpa", FPU_ARCH_FPA
},
24332 {"fpa10", FPU_ARCH_FPA
},
24333 {"fpa11", FPU_ARCH_FPA
},
24334 {"arm7500fe", FPU_ARCH_FPA
},
24335 {"softvfp", FPU_ARCH_VFP
},
24336 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24337 {"vfp", FPU_ARCH_VFP_V2
},
24338 {"vfp9", FPU_ARCH_VFP_V2
},
24339 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24340 {"vfp10", FPU_ARCH_VFP_V2
},
24341 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24342 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24343 {"vfpv2", FPU_ARCH_VFP_V2
},
24344 {"vfpv3", FPU_ARCH_VFP_V3
},
24345 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24346 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24347 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24348 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24349 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24350 {"arm1020t", FPU_ARCH_VFP_V1
},
24351 {"arm1020e", FPU_ARCH_VFP_V2
},
24352 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24353 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24354 {"maverick", FPU_ARCH_MAVERICK
},
24355 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24356 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24357 {"vfpv4", FPU_ARCH_VFP_V4
},
24358 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24359 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24360 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24361 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24362 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24363 {"crypto-neon-fp-armv8",
24364 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24365 {NULL
, ARM_ARCH_NONE
}
24368 struct arm_option_value_table
24374 static const struct arm_option_value_table arm_float_abis
[] =
24376 {"hard", ARM_FLOAT_ABI_HARD
},
24377 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24378 {"soft", ARM_FLOAT_ABI_SOFT
},
24383 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24384 static const struct arm_option_value_table arm_eabis
[] =
24386 {"gnu", EF_ARM_EABI_UNKNOWN
},
24387 {"4", EF_ARM_EABI_VER4
},
24388 {"5", EF_ARM_EABI_VER5
},
24393 struct arm_long_option_table
24395 char * option
; /* Substring to match. */
24396 char * help
; /* Help information. */
24397 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24398 char * deprecated
; /* If non-null, print this message. */
24402 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24404 arm_feature_set
*ext_set
= (arm_feature_set
*)
24405 xmalloc (sizeof (arm_feature_set
));
24407 /* We insist on extensions being specified in alphabetical order, and with
24408 extensions being added before being removed. We achieve this by having
24409 the global ARM_EXTENSIONS table in alphabetical order, and using the
24410 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24411 or removing it (0) and only allowing it to change in the order
24413 const struct arm_option_extension_value_table
* opt
= NULL
;
24414 int adding_value
= -1;
24416 /* Copy the feature set, so that we can modify it. */
24417 *ext_set
= **opt_p
;
24420 while (str
!= NULL
&& *str
!= 0)
24427 as_bad (_("invalid architectural extension"));
24432 ext
= strchr (str
, '+');
24437 len
= strlen (str
);
24439 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24441 if (adding_value
!= 0)
24444 opt
= arm_extensions
;
24452 if (adding_value
== -1)
24455 opt
= arm_extensions
;
24457 else if (adding_value
!= 1)
24459 as_bad (_("must specify extensions to add before specifying "
24460 "those to remove"));
24467 as_bad (_("missing architectural extension"));
24471 gas_assert (adding_value
!= -1);
24472 gas_assert (opt
!= NULL
);
24474 /* Scan over the options table trying to find an exact match. */
24475 for (; opt
->name
!= NULL
; opt
++)
24476 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24478 /* Check we can apply the extension to this architecture. */
24479 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24481 as_bad (_("extension does not apply to the base architecture"));
24485 /* Add or remove the extension. */
24487 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
24489 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
24494 if (opt
->name
== NULL
)
24496 /* Did we fail to find an extension because it wasn't specified in
24497 alphabetical order, or because it does not exist? */
24499 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24500 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24503 if (opt
->name
== NULL
)
24504 as_bad (_("unknown architectural extension `%s'"), str
);
24506 as_bad (_("architectural extensions must be specified in "
24507 "alphabetical order"));
24513 /* We should skip the extension we've just matched the next time
24525 arm_parse_cpu (char *str
)
24527 const struct arm_cpu_option_table
*opt
;
24528 char *ext
= strchr (str
, '+');
24534 len
= strlen (str
);
24538 as_bad (_("missing cpu name `%s'"), str
);
24542 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24543 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24545 mcpu_cpu_opt
= &opt
->value
;
24546 mcpu_fpu_opt
= &opt
->default_fpu
;
24547 if (opt
->canonical_name
)
24548 strcpy (selected_cpu_name
, opt
->canonical_name
);
24553 for (i
= 0; i
< len
; i
++)
24554 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24555 selected_cpu_name
[i
] = 0;
24559 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24564 as_bad (_("unknown cpu `%s'"), str
);
24569 arm_parse_arch (char *str
)
24571 const struct arm_arch_option_table
*opt
;
24572 char *ext
= strchr (str
, '+');
24578 len
= strlen (str
);
24582 as_bad (_("missing architecture name `%s'"), str
);
24586 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24587 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24589 march_cpu_opt
= &opt
->value
;
24590 march_fpu_opt
= &opt
->default_fpu
;
24591 strcpy (selected_cpu_name
, opt
->name
);
24594 return arm_parse_extension (ext
, &march_cpu_opt
);
24599 as_bad (_("unknown architecture `%s'\n"), str
);
24604 arm_parse_fpu (char * str
)
24606 const struct arm_option_fpu_value_table
* opt
;
24608 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24609 if (streq (opt
->name
, str
))
24611 mfpu_opt
= &opt
->value
;
24615 as_bad (_("unknown floating point format `%s'\n"), str
);
24620 arm_parse_float_abi (char * str
)
24622 const struct arm_option_value_table
* opt
;
24624 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
24625 if (streq (opt
->name
, str
))
24627 mfloat_abi_opt
= opt
->value
;
24631 as_bad (_("unknown floating point abi `%s'\n"), str
);
24637 arm_parse_eabi (char * str
)
24639 const struct arm_option_value_table
*opt
;
24641 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
24642 if (streq (opt
->name
, str
))
24644 meabi_flags
= opt
->value
;
24647 as_bad (_("unknown EABI `%s'\n"), str
);
24653 arm_parse_it_mode (char * str
)
24655 bfd_boolean ret
= TRUE
;
24657 if (streq ("arm", str
))
24658 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
24659 else if (streq ("thumb", str
))
24660 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
24661 else if (streq ("always", str
))
24662 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
24663 else if (streq ("never", str
))
24664 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
24667 as_bad (_("unknown implicit IT mode `%s', should be "\
24668 "arm, thumb, always, or never."), str
);
24676 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
24678 codecomposer_syntax
= TRUE
;
24679 arm_comment_chars
[0] = ';';
24680 arm_line_separator_chars
[0] = 0;
24684 struct arm_long_option_table arm_long_opts
[] =
24686 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24687 arm_parse_cpu
, NULL
},
24688 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24689 arm_parse_arch
, NULL
},
24690 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24691 arm_parse_fpu
, NULL
},
24692 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24693 arm_parse_float_abi
, NULL
},
24695 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24696 arm_parse_eabi
, NULL
},
24698 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24699 arm_parse_it_mode
, NULL
},
24700 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24701 arm_ccs_mode
, NULL
},
24702 {NULL
, NULL
, 0, NULL
}
24706 md_parse_option (int c
, char * arg
)
24708 struct arm_option_table
*opt
;
24709 const struct arm_legacy_option_table
*fopt
;
24710 struct arm_long_option_table
*lopt
;
24716 target_big_endian
= 1;
24722 target_big_endian
= 0;
24726 case OPTION_FIX_V4BX
:
24731 /* Listing option. Just ignore these, we don't support additional
24736 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24738 if (c
== opt
->option
[0]
24739 && ((arg
== NULL
&& opt
->option
[1] == 0)
24740 || streq (arg
, opt
->option
+ 1)))
24742 /* If the option is deprecated, tell the user. */
24743 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
24744 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24745 arg
? arg
: "", _(opt
->deprecated
));
24747 if (opt
->var
!= NULL
)
24748 *opt
->var
= opt
->value
;
24754 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
24756 if (c
== fopt
->option
[0]
24757 && ((arg
== NULL
&& fopt
->option
[1] == 0)
24758 || streq (arg
, fopt
->option
+ 1)))
24760 /* If the option is deprecated, tell the user. */
24761 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
24762 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24763 arg
? arg
: "", _(fopt
->deprecated
));
24765 if (fopt
->var
!= NULL
)
24766 *fopt
->var
= &fopt
->value
;
24772 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24774 /* These options are expected to have an argument. */
24775 if (c
== lopt
->option
[0]
24777 && strncmp (arg
, lopt
->option
+ 1,
24778 strlen (lopt
->option
+ 1)) == 0)
24780 /* If the option is deprecated, tell the user. */
24781 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
24782 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
24783 _(lopt
->deprecated
));
24785 /* Call the sup-option parser. */
24786 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
24797 md_show_usage (FILE * fp
)
24799 struct arm_option_table
*opt
;
24800 struct arm_long_option_table
*lopt
;
24802 fprintf (fp
, _(" ARM-specific assembler options:\n"));
24804 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24805 if (opt
->help
!= NULL
)
24806 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
24808 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24809 if (lopt
->help
!= NULL
)
24810 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
24814 -EB assemble code for a big-endian cpu\n"));
24819 -EL assemble code for a little-endian cpu\n"));
24823 --fix-v4bx Allow BX in ARMv4 code\n"));
24831 arm_feature_set flags
;
24832 } cpu_arch_ver_table
;
24834 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24835 least features first. */
24836 static const cpu_arch_ver_table cpu_arch_ver
[] =
24842 {4, ARM_ARCH_V5TE
},
24843 {5, ARM_ARCH_V5TEJ
},
24847 {11, ARM_ARCH_V6M
},
24848 {12, ARM_ARCH_V6SM
},
24849 {8, ARM_ARCH_V6T2
},
24850 {10, ARM_ARCH_V7VE
},
24851 {10, ARM_ARCH_V7R
},
24852 {10, ARM_ARCH_V7M
},
24853 {14, ARM_ARCH_V8A
},
24857 /* Set an attribute if it has not already been set by the user. */
24859 aeabi_set_attribute_int (int tag
, int value
)
24862 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24863 || !attributes_set_explicitly
[tag
])
24864 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
24868 aeabi_set_attribute_string (int tag
, const char *value
)
24871 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24872 || !attributes_set_explicitly
[tag
])
24873 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
24876 /* Set the public EABI object attributes. */
24878 aeabi_set_public_attributes (void)
24883 int fp16_optional
= 0;
24884 arm_feature_set flags
;
24885 arm_feature_set tmp
;
24886 const cpu_arch_ver_table
*p
;
24888 /* Choose the architecture based on the capabilities of the requested cpu
24889 (if any) and/or the instructions actually used. */
24890 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
24891 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
24892 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
24894 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
24895 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
24897 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
24898 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
24900 /* Allow the user to override the reported architecture. */
24903 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
24904 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
24907 /* We need to make sure that the attributes do not identify us as v6S-M
24908 when the only v6S-M feature in use is the Operating System Extensions. */
24909 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
24910 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
24911 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
24915 for (p
= cpu_arch_ver
; p
->val
; p
++)
24917 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
24920 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
24924 /* The table lookup above finds the last architecture to contribute
24925 a new feature. Unfortunately, Tag13 is a subset of the union of
24926 v6T2 and v7-M, so it is never seen as contributing a new feature.
24927 We can not search for the last entry which is entirely used,
24928 because if no CPU is specified we build up only those flags
24929 actually used. Perhaps we should separate out the specified
24930 and implicit cases. Avoid taking this path for -march=all by
24931 checking for contradictory v7-A / v7-M features. */
24933 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
24934 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
24935 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
24938 /* Tag_CPU_name. */
24939 if (selected_cpu_name
[0])
24943 q
= selected_cpu_name
;
24944 if (strncmp (q
, "armv", 4) == 0)
24949 for (i
= 0; q
[i
]; i
++)
24950 q
[i
] = TOUPPER (q
[i
]);
24952 aeabi_set_attribute_string (Tag_CPU_name
, q
);
24955 /* Tag_CPU_arch. */
24956 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
24958 /* Tag_CPU_arch_profile. */
24959 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
24961 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
24963 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
24968 if (profile
!= '\0')
24969 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
24971 /* Tag_ARM_ISA_use. */
24972 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
24974 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
24976 /* Tag_THUMB_ISA_use. */
24977 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
24979 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
24980 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
24982 /* Tag_VFP_arch. */
24983 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8
))
24984 aeabi_set_attribute_int (Tag_VFP_arch
, 7);
24985 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
24986 aeabi_set_attribute_int (Tag_VFP_arch
,
24987 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
24989 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
24992 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
24994 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
24996 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
24999 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25000 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25001 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25002 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25003 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25005 /* Tag_ABI_HardFP_use. */
25006 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25007 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25008 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25010 /* Tag_WMMX_arch. */
25011 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25012 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25013 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25014 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25016 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25017 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25018 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25019 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25021 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25023 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25027 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25032 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25033 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25034 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25038 We set Tag_DIV_use to two when integer divide instructions have been used
25039 in ARM state, or when Thumb integer divide instructions have been used,
25040 but we have no architecture profile set, nor have we any ARM instructions.
25042 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25045 For new architectures we will have to check these tests. */
25046 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25047 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25048 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25049 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25050 || (profile
== '\0'
25051 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25052 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25053 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25055 /* Tag_MP_extension_use. */
25056 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25057 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25059 /* Tag Virtualization_use. */
25060 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25062 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25065 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25068 /* Add the default contents for the .ARM.attributes section. */
25072 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25075 aeabi_set_public_attributes ();
25077 #endif /* OBJ_ELF */
25080 /* Parse a .cpu directive. */
25083 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25085 const struct arm_cpu_option_table
*opt
;
25089 name
= input_line_pointer
;
25090 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25091 input_line_pointer
++;
25092 saved_char
= *input_line_pointer
;
25093 *input_line_pointer
= 0;
25095 /* Skip the first "all" entry. */
25096 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25097 if (streq (opt
->name
, name
))
25099 mcpu_cpu_opt
= &opt
->value
;
25100 selected_cpu
= opt
->value
;
25101 if (opt
->canonical_name
)
25102 strcpy (selected_cpu_name
, opt
->canonical_name
);
25106 for (i
= 0; opt
->name
[i
]; i
++)
25107 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25109 selected_cpu_name
[i
] = 0;
25111 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25112 *input_line_pointer
= saved_char
;
25113 demand_empty_rest_of_line ();
25116 as_bad (_("unknown cpu `%s'"), name
);
25117 *input_line_pointer
= saved_char
;
25118 ignore_rest_of_line ();
25122 /* Parse a .arch directive. */
25125 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25127 const struct arm_arch_option_table
*opt
;
25131 name
= input_line_pointer
;
25132 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25133 input_line_pointer
++;
25134 saved_char
= *input_line_pointer
;
25135 *input_line_pointer
= 0;
25137 /* Skip the first "all" entry. */
25138 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25139 if (streq (opt
->name
, name
))
25141 mcpu_cpu_opt
= &opt
->value
;
25142 selected_cpu
= opt
->value
;
25143 strcpy (selected_cpu_name
, opt
->name
);
25144 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25145 *input_line_pointer
= saved_char
;
25146 demand_empty_rest_of_line ();
25150 as_bad (_("unknown architecture `%s'\n"), name
);
25151 *input_line_pointer
= saved_char
;
25152 ignore_rest_of_line ();
25156 /* Parse a .object_arch directive. */
25159 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25161 const struct arm_arch_option_table
*opt
;
25165 name
= input_line_pointer
;
25166 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25167 input_line_pointer
++;
25168 saved_char
= *input_line_pointer
;
25169 *input_line_pointer
= 0;
25171 /* Skip the first "all" entry. */
25172 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25173 if (streq (opt
->name
, name
))
25175 object_arch
= &opt
->value
;
25176 *input_line_pointer
= saved_char
;
25177 demand_empty_rest_of_line ();
25181 as_bad (_("unknown architecture `%s'\n"), name
);
25182 *input_line_pointer
= saved_char
;
25183 ignore_rest_of_line ();
25186 /* Parse a .arch_extension directive. */
25189 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25191 const struct arm_option_extension_value_table
*opt
;
25194 int adding_value
= 1;
25196 name
= input_line_pointer
;
25197 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25198 input_line_pointer
++;
25199 saved_char
= *input_line_pointer
;
25200 *input_line_pointer
= 0;
25202 if (strlen (name
) >= 2
25203 && strncmp (name
, "no", 2) == 0)
25209 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25210 if (streq (opt
->name
, name
))
25212 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25214 as_bad (_("architectural extension `%s' is not allowed for the "
25215 "current base architecture"), name
);
25220 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
25222 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
25224 mcpu_cpu_opt
= &selected_cpu
;
25225 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25226 *input_line_pointer
= saved_char
;
25227 demand_empty_rest_of_line ();
25231 if (opt
->name
== NULL
)
25232 as_bad (_("unknown architecture extension `%s'\n"), name
);
25234 *input_line_pointer
= saved_char
;
25235 ignore_rest_of_line ();
25238 /* Parse a .fpu directive. */
25241 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25243 const struct arm_option_fpu_value_table
*opt
;
25247 name
= input_line_pointer
;
25248 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25249 input_line_pointer
++;
25250 saved_char
= *input_line_pointer
;
25251 *input_line_pointer
= 0;
25253 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25254 if (streq (opt
->name
, name
))
25256 mfpu_opt
= &opt
->value
;
25257 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25258 *input_line_pointer
= saved_char
;
25259 demand_empty_rest_of_line ();
25263 as_bad (_("unknown floating point format `%s'\n"), name
);
25264 *input_line_pointer
= saved_char
;
25265 ignore_rest_of_line ();
25268 /* Copy symbol information. */
25271 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25273 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25277 /* Given a symbolic attribute NAME, return the proper integer value.
25278 Returns -1 if the attribute is not known. */
25281 arm_convert_symbolic_attribute (const char *name
)
25283 static const struct
25288 attribute_table
[] =
25290 /* When you modify this table you should
25291 also modify the list in doc/c-arm.texi. */
25292 #define T(tag) {#tag, tag}
25293 T (Tag_CPU_raw_name
),
25296 T (Tag_CPU_arch_profile
),
25297 T (Tag_ARM_ISA_use
),
25298 T (Tag_THUMB_ISA_use
),
25302 T (Tag_Advanced_SIMD_arch
),
25303 T (Tag_PCS_config
),
25304 T (Tag_ABI_PCS_R9_use
),
25305 T (Tag_ABI_PCS_RW_data
),
25306 T (Tag_ABI_PCS_RO_data
),
25307 T (Tag_ABI_PCS_GOT_use
),
25308 T (Tag_ABI_PCS_wchar_t
),
25309 T (Tag_ABI_FP_rounding
),
25310 T (Tag_ABI_FP_denormal
),
25311 T (Tag_ABI_FP_exceptions
),
25312 T (Tag_ABI_FP_user_exceptions
),
25313 T (Tag_ABI_FP_number_model
),
25314 T (Tag_ABI_align_needed
),
25315 T (Tag_ABI_align8_needed
),
25316 T (Tag_ABI_align_preserved
),
25317 T (Tag_ABI_align8_preserved
),
25318 T (Tag_ABI_enum_size
),
25319 T (Tag_ABI_HardFP_use
),
25320 T (Tag_ABI_VFP_args
),
25321 T (Tag_ABI_WMMX_args
),
25322 T (Tag_ABI_optimization_goals
),
25323 T (Tag_ABI_FP_optimization_goals
),
25324 T (Tag_compatibility
),
25325 T (Tag_CPU_unaligned_access
),
25326 T (Tag_FP_HP_extension
),
25327 T (Tag_VFP_HP_extension
),
25328 T (Tag_ABI_FP_16bit_format
),
25329 T (Tag_MPextension_use
),
25331 T (Tag_nodefaults
),
25332 T (Tag_also_compatible_with
),
25333 T (Tag_conformance
),
25335 T (Tag_Virtualization_use
),
25336 /* We deliberately do not include Tag_MPextension_use_legacy. */
25344 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25345 if (streq (name
, attribute_table
[i
].name
))
25346 return attribute_table
[i
].tag
;
25352 /* Apply sym value for relocations only in the case that
25353 they are for local symbols and you have the respective
25354 architectural feature for blx and simple switches. */
25356 arm_apply_sym_value (struct fix
* fixP
)
25359 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25360 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25362 switch (fixP
->fx_r_type
)
25364 case BFD_RELOC_ARM_PCREL_BLX
:
25365 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25366 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25370 case BFD_RELOC_ARM_PCREL_CALL
:
25371 case BFD_RELOC_THUMB_PCREL_BLX
:
25372 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25383 #endif /* OBJ_ELF */