1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, ARM_EXT2_V8M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
211 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
212 static const arm_feature_set arm_ext_v6t2_v8m
=
213 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
214 /* Instructions shared between ARMv8-A and ARMv8-M. */
215 static const arm_feature_set arm_ext_atomics
=
216 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
217 static const arm_feature_set arm_ext_v8_2
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
219 /* FP16 instructions. */
220 static const arm_feature_set arm_ext_fp16
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
223 static const arm_feature_set arm_arch_any
= ARM_ANY
;
224 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
225 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
226 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
227 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
229 static const arm_feature_set arm_cext_iwmmxt2
=
230 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
231 static const arm_feature_set arm_cext_iwmmxt
=
232 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
233 static const arm_feature_set arm_cext_xscale
=
234 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
235 static const arm_feature_set arm_cext_maverick
=
236 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
237 static const arm_feature_set fpu_fpa_ext_v1
=
238 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
239 static const arm_feature_set fpu_fpa_ext_v2
=
240 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
241 static const arm_feature_set fpu_vfp_ext_v1xd
=
242 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
243 static const arm_feature_set fpu_vfp_ext_v1
=
244 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
245 static const arm_feature_set fpu_vfp_ext_v2
=
246 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
247 static const arm_feature_set fpu_vfp_ext_v3xd
=
248 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
249 static const arm_feature_set fpu_vfp_ext_v3
=
250 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
251 static const arm_feature_set fpu_vfp_ext_d32
=
252 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
253 static const arm_feature_set fpu_neon_ext_v1
=
254 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
255 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
256 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
257 static const arm_feature_set fpu_vfp_fp16
=
258 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
259 static const arm_feature_set fpu_neon_ext_fma
=
260 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
261 static const arm_feature_set fpu_vfp_ext_fma
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
263 static const arm_feature_set fpu_vfp_ext_armv8
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
265 static const arm_feature_set fpu_vfp_ext_armv8xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
267 static const arm_feature_set fpu_neon_ext_armv8
=
268 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
269 static const arm_feature_set fpu_crypto_ext_armv8
=
270 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
271 static const arm_feature_set crc_ext_armv8
=
272 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
273 static const arm_feature_set fpu_neon_ext_v8_1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
276 static int mfloat_abi_opt
= -1;
277 /* Record user cpu selection for object attributes. */
278 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
279 /* Must be long enough to hold any of the names in arm_cpus. */
280 static char selected_cpu_name
[20];
282 extern FLONUM_TYPE generic_floating_point_number
;
284 /* Return if no cpu was selected on command-line. */
286 no_cpu_selected (void)
288 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
293 static int meabi_flags
= EABI_DEFAULT
;
295 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
298 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
303 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
309 symbolS
* GOT_symbol
;
312 /* 0: assemble for ARM,
313 1: assemble for Thumb,
314 2: assemble for Thumb even though target CPU does not support thumb
316 static int thumb_mode
= 0;
317 /* A value distinct from the possible values for thumb_mode that we
318 can use to record whether thumb_mode has been copied into the
319 tc_frag_data field of a frag. */
320 #define MODE_RECORDED (1 << 4)
322 /* Specifies the intrinsic IT insn behavior mode. */
323 enum implicit_it_mode
325 IMPLICIT_IT_MODE_NEVER
= 0x00,
326 IMPLICIT_IT_MODE_ARM
= 0x01,
327 IMPLICIT_IT_MODE_THUMB
= 0x02,
328 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
330 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
332 /* If unified_syntax is true, we are processing the new unified
333 ARM/Thumb syntax. Important differences from the old ARM mode:
335 - Immediate operands do not require a # prefix.
336 - Conditional affixes always appear at the end of the
337 instruction. (For backward compatibility, those instructions
338 that formerly had them in the middle, continue to accept them
340 - The IT instruction may appear, and if it does is validated
341 against subsequent conditional affixes. It does not generate
344 Important differences from the old Thumb mode:
346 - Immediate operands do not require a # prefix.
347 - Most of the V6T2 instructions are only available in unified mode.
348 - The .N and .W suffixes are recognized and honored (it is an error
349 if they cannot be honored).
350 - All instructions set the flags if and only if they have an 's' affix.
351 - Conditional affixes may be used. They are validated against
352 preceding IT instructions. Unlike ARM mode, you cannot use a
353 conditional affix except in the scope of an IT instruction. */
355 static bfd_boolean unified_syntax
= FALSE
;
357 /* An immediate operand can start with #, and ld*, st*, pld operands
358 can contain [ and ]. We need to tell APP not to elide whitespace
359 before a [, which can appear as the first operand for pld.
360 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
361 const char arm_symbol_chars
[] = "#[]{}";
376 enum neon_el_type type
;
380 #define NEON_MAX_TYPE_ELS 4
384 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
388 enum it_instruction_type
393 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
394 if inside, should be the last one. */
395 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
396 i.e. BKPT and NOP. */
397 IT_INSN
/* The IT insn has been parsed. */
400 /* The maximum number of operands we need. */
401 #define ARM_IT_MAX_OPERANDS 6
406 unsigned long instruction
;
410 /* "uncond_value" is set to the value in place of the conditional field in
411 unconditional versions of the instruction, or -1 if nothing is
414 struct neon_type vectype
;
415 /* This does not indicate an actual NEON instruction, only that
416 the mnemonic accepts neon-style type suffixes. */
418 /* Set to the opcode if the instruction needs relaxation.
419 Zero if the instruction is not relaxed. */
423 bfd_reloc_code_real_type type
;
428 enum it_instruction_type it_insn_type
;
434 struct neon_type_el vectype
;
435 unsigned present
: 1; /* Operand present. */
436 unsigned isreg
: 1; /* Operand was a register. */
437 unsigned immisreg
: 1; /* .imm field is a second register. */
438 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
439 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
440 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
441 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
442 instructions. This allows us to disambiguate ARM <-> vector insns. */
443 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
444 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
445 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
446 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
447 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
448 unsigned writeback
: 1; /* Operand has trailing ! */
449 unsigned preind
: 1; /* Preindexed address. */
450 unsigned postind
: 1; /* Postindexed address. */
451 unsigned negative
: 1; /* Index register was negated. */
452 unsigned shifted
: 1; /* Shift applied to operation. */
453 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
454 } operands
[ARM_IT_MAX_OPERANDS
];
457 static struct arm_it inst
;
459 #define NUM_FLOAT_VALS 8
461 const char * fp_const
[] =
463 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
466 /* Number of littlenums required to hold an extended precision number. */
467 #define MAX_LITTLENUMS 6
469 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
479 #define CP_T_X 0x00008000
480 #define CP_T_Y 0x00400000
482 #define CONDS_BIT 0x00100000
483 #define LOAD_BIT 0x00100000
485 #define DOUBLE_LOAD_FLAG 0x00000001
489 const char * template_name
;
493 #define COND_ALWAYS 0xE
497 const char * template_name
;
501 struct asm_barrier_opt
503 const char * template_name
;
505 const arm_feature_set arch
;
508 /* The bit that distinguishes CPSR and SPSR. */
509 #define SPSR_BIT (1 << 22)
511 /* The individual PSR flag bits. */
512 #define PSR_c (1 << 16)
513 #define PSR_x (1 << 17)
514 #define PSR_s (1 << 18)
515 #define PSR_f (1 << 19)
520 bfd_reloc_code_real_type reloc
;
525 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
526 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
531 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
534 /* Bits for DEFINED field in neon_typed_alias. */
535 #define NTA_HASTYPE 1
536 #define NTA_HASINDEX 2
538 struct neon_typed_alias
540 unsigned char defined
;
542 struct neon_type_el eltype
;
545 /* ARM register categories. This includes coprocessor numbers and various
546 architecture extensions' registers. */
573 /* Structure for a hash table entry for a register.
574 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
575 information which states whether a vector type or index is specified (for a
576 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
582 unsigned char builtin
;
583 struct neon_typed_alias
* neon
;
586 /* Diagnostics used when we don't get a register of the expected type. */
587 const char * const reg_expected_msgs
[] =
589 N_("ARM register expected"),
590 N_("bad or missing co-processor number"),
591 N_("co-processor register expected"),
592 N_("FPA register expected"),
593 N_("VFP single precision register expected"),
594 N_("VFP/Neon double precision register expected"),
595 N_("Neon quad precision register expected"),
596 N_("VFP single or double precision register expected"),
597 N_("Neon double or quad precision register expected"),
598 N_("VFP single, double or Neon quad precision register expected"),
599 N_("VFP system register expected"),
600 N_("Maverick MVF register expected"),
601 N_("Maverick MVD register expected"),
602 N_("Maverick MVFX register expected"),
603 N_("Maverick MVDX register expected"),
604 N_("Maverick MVAX register expected"),
605 N_("Maverick DSPSC register expected"),
606 N_("iWMMXt data register expected"),
607 N_("iWMMXt control register expected"),
608 N_("iWMMXt scalar register expected"),
609 N_("XScale accumulator register expected"),
612 /* Some well known registers that we refer to directly elsewhere. */
618 /* ARM instructions take 4bytes in the object file, Thumb instructions
624 /* Basic string to match. */
625 const char * template_name
;
627 /* Parameters to instruction. */
628 unsigned int operands
[8];
630 /* Conditional tag - see opcode_lookup. */
631 unsigned int tag
: 4;
633 /* Basic instruction code. */
634 unsigned int avalue
: 28;
636 /* Thumb-format instruction code. */
639 /* Which architecture variant provides this instruction. */
640 const arm_feature_set
* avariant
;
641 const arm_feature_set
* tvariant
;
643 /* Function to call to encode instruction in ARM format. */
644 void (* aencode
) (void);
646 /* Function to call to encode instruction in Thumb format. */
647 void (* tencode
) (void);
650 /* Defines for various bits that we will want to toggle. */
651 #define INST_IMMEDIATE 0x02000000
652 #define OFFSET_REG 0x02000000
653 #define HWOFFSET_IMM 0x00400000
654 #define SHIFT_BY_REG 0x00000010
655 #define PRE_INDEX 0x01000000
656 #define INDEX_UP 0x00800000
657 #define WRITE_BACK 0x00200000
658 #define LDM_TYPE_2_OR_3 0x00400000
659 #define CPSI_MMOD 0x00020000
661 #define LITERAL_MASK 0xf000f000
662 #define OPCODE_MASK 0xfe1fffff
663 #define V4_STR_BIT 0x00000020
664 #define VLDR_VMOV_SAME 0x0040f000
666 #define T2_SUBS_PC_LR 0xf3de8f00
668 #define DATA_OP_SHIFT 21
670 #define T2_OPCODE_MASK 0xfe1fffff
671 #define T2_DATA_OP_SHIFT 21
673 #define A_COND_MASK 0xf0000000
674 #define A_PUSH_POP_OP_MASK 0x0fff0000
676 /* Opcodes for pushing/poping registers to/from the stack. */
677 #define A1_OPCODE_PUSH 0x092d0000
678 #define A2_OPCODE_PUSH 0x052d0004
679 #define A2_OPCODE_POP 0x049d0004
681 /* Codes to distinguish the arithmetic instructions. */
692 #define OPCODE_CMP 10
693 #define OPCODE_CMN 11
694 #define OPCODE_ORR 12
695 #define OPCODE_MOV 13
696 #define OPCODE_BIC 14
697 #define OPCODE_MVN 15
699 #define T2_OPCODE_AND 0
700 #define T2_OPCODE_BIC 1
701 #define T2_OPCODE_ORR 2
702 #define T2_OPCODE_ORN 3
703 #define T2_OPCODE_EOR 4
704 #define T2_OPCODE_ADD 8
705 #define T2_OPCODE_ADC 10
706 #define T2_OPCODE_SBC 11
707 #define T2_OPCODE_SUB 13
708 #define T2_OPCODE_RSB 14
710 #define T_OPCODE_MUL 0x4340
711 #define T_OPCODE_TST 0x4200
712 #define T_OPCODE_CMN 0x42c0
713 #define T_OPCODE_NEG 0x4240
714 #define T_OPCODE_MVN 0x43c0
716 #define T_OPCODE_ADD_R3 0x1800
717 #define T_OPCODE_SUB_R3 0x1a00
718 #define T_OPCODE_ADD_HI 0x4400
719 #define T_OPCODE_ADD_ST 0xb000
720 #define T_OPCODE_SUB_ST 0xb080
721 #define T_OPCODE_ADD_SP 0xa800
722 #define T_OPCODE_ADD_PC 0xa000
723 #define T_OPCODE_ADD_I8 0x3000
724 #define T_OPCODE_SUB_I8 0x3800
725 #define T_OPCODE_ADD_I3 0x1c00
726 #define T_OPCODE_SUB_I3 0x1e00
728 #define T_OPCODE_ASR_R 0x4100
729 #define T_OPCODE_LSL_R 0x4080
730 #define T_OPCODE_LSR_R 0x40c0
731 #define T_OPCODE_ROR_R 0x41c0
732 #define T_OPCODE_ASR_I 0x1000
733 #define T_OPCODE_LSL_I 0x0000
734 #define T_OPCODE_LSR_I 0x0800
736 #define T_OPCODE_MOV_I8 0x2000
737 #define T_OPCODE_CMP_I8 0x2800
738 #define T_OPCODE_CMP_LR 0x4280
739 #define T_OPCODE_MOV_HR 0x4600
740 #define T_OPCODE_CMP_HR 0x4500
742 #define T_OPCODE_LDR_PC 0x4800
743 #define T_OPCODE_LDR_SP 0x9800
744 #define T_OPCODE_STR_SP 0x9000
745 #define T_OPCODE_LDR_IW 0x6800
746 #define T_OPCODE_STR_IW 0x6000
747 #define T_OPCODE_LDR_IH 0x8800
748 #define T_OPCODE_STR_IH 0x8000
749 #define T_OPCODE_LDR_IB 0x7800
750 #define T_OPCODE_STR_IB 0x7000
751 #define T_OPCODE_LDR_RW 0x5800
752 #define T_OPCODE_STR_RW 0x5000
753 #define T_OPCODE_LDR_RH 0x5a00
754 #define T_OPCODE_STR_RH 0x5200
755 #define T_OPCODE_LDR_RB 0x5c00
756 #define T_OPCODE_STR_RB 0x5400
758 #define T_OPCODE_PUSH 0xb400
759 #define T_OPCODE_POP 0xbc00
761 #define T_OPCODE_BRANCH 0xe000
763 #define THUMB_SIZE 2 /* Size of thumb instruction. */
764 #define THUMB_PP_PC_LR 0x0100
765 #define THUMB_LOAD_BIT 0x0800
766 #define THUMB2_LOAD_BIT 0x00100000
768 #define BAD_ARGS _("bad arguments to instruction")
769 #define BAD_SP _("r13 not allowed here")
770 #define BAD_PC _("r15 not allowed here")
771 #define BAD_COND _("instruction cannot be conditional")
772 #define BAD_OVERLAP _("registers may not be the same")
773 #define BAD_HIREG _("lo register required")
774 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
775 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
776 #define BAD_BRANCH _("branch must be last instruction in IT block")
777 #define BAD_NOT_IT _("instruction not allowed in IT block")
778 #define BAD_FPU _("selected FPU does not support instruction")
779 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
780 #define BAD_IT_COND _("incorrect condition in IT block")
781 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
782 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
783 #define BAD_PC_ADDRESSING \
784 _("cannot use register index with PC-relative addressing")
785 #define BAD_PC_WRITEBACK \
786 _("cannot use writeback with PC-relative addressing")
787 #define BAD_RANGE _("branch out of range")
788 #define BAD_FP16 _("selected processor does not support fp16 instruction")
789 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
790 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
792 static struct hash_control
* arm_ops_hsh
;
793 static struct hash_control
* arm_cond_hsh
;
794 static struct hash_control
* arm_shift_hsh
;
795 static struct hash_control
* arm_psr_hsh
;
796 static struct hash_control
* arm_v7m_psr_hsh
;
797 static struct hash_control
* arm_reg_hsh
;
798 static struct hash_control
* arm_reloc_hsh
;
799 static struct hash_control
* arm_barrier_opt_hsh
;
801 /* Stuff needed to resolve the label ambiguity
810 symbolS
* last_label_seen
;
811 static int label_is_thumb_function_name
= FALSE
;
813 /* Literal pool structure. Held on a per-section
814 and per-sub-section basis. */
816 #define MAX_LITERAL_POOL_SIZE 1024
817 typedef struct literal_pool
819 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
820 unsigned int next_free_entry
;
826 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
828 struct literal_pool
* next
;
829 unsigned int alignment
;
832 /* Pointer to a linked list of literal pools. */
833 literal_pool
* list_of_pools
= NULL
;
835 typedef enum asmfunc_states
838 WAITING_ASMFUNC_NAME
,
842 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
845 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
847 static struct current_it now_it
;
851 now_it_compatible (int cond
)
853 return (cond
& ~1) == (now_it
.cc
& ~1);
857 conditional_insn (void)
859 return inst
.cond
!= COND_ALWAYS
;
862 static int in_it_block (void);
864 static int handle_it_state (void);
866 static void force_automatic_it_block_close (void);
868 static void it_fsm_post_encode (void);
870 #define set_it_insn_type(type) \
873 inst.it_insn_type = type; \
874 if (handle_it_state () == FAIL) \
879 #define set_it_insn_type_nonvoid(type, failret) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_last() \
891 if (inst.cond == COND_ALWAYS) \
892 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
894 set_it_insn_type (INSIDE_IT_LAST_INSN); \
900 /* This array holds the chars that always start a comment. If the
901 pre-processor is disabled, these aren't very useful. */
902 char arm_comment_chars
[] = "@";
904 /* This array holds the chars that only start a comment at the beginning of
905 a line. If the line seems to have the form '# 123 filename'
906 .line and .file directives will appear in the pre-processed output. */
907 /* Note that input_file.c hand checks for '#' at the beginning of the
908 first line of the input file. This is because the compiler outputs
909 #NO_APP at the beginning of its output. */
910 /* Also note that comments like this one will always work. */
911 const char line_comment_chars
[] = "#";
913 char arm_line_separator_chars
[] = ";";
915 /* Chars that can be used to separate mant
916 from exp in floating point numbers. */
917 const char EXP_CHARS
[] = "eE";
919 /* Chars that mean this number is a floating point constant. */
923 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
925 /* Prefix characters that indicate the start of an immediate
927 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
929 /* Separator character handling. */
931 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
934 skip_past_char (char ** str
, char c
)
936 /* PR gas/14987: Allow for whitespace before the expected character. */
937 skip_whitespace (*str
);
948 #define skip_past_comma(str) skip_past_char (str, ',')
950 /* Arithmetic expressions (possibly involving symbols). */
952 /* Return TRUE if anything in the expression is a bignum. */
955 walk_no_bignums (symbolS
* sp
)
957 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
960 if (symbol_get_value_expression (sp
)->X_add_symbol
)
962 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
963 || (symbol_get_value_expression (sp
)->X_op_symbol
964 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
970 static int in_my_get_expression
= 0;
972 /* Third argument to my_get_expression. */
973 #define GE_NO_PREFIX 0
974 #define GE_IMM_PREFIX 1
975 #define GE_OPT_PREFIX 2
976 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
977 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
978 #define GE_OPT_PREFIX_BIG 3
981 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
986 /* In unified syntax, all prefixes are optional. */
988 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
993 case GE_NO_PREFIX
: break;
995 if (!is_immediate_prefix (**str
))
997 inst
.error
= _("immediate expression requires a # prefix");
1003 case GE_OPT_PREFIX_BIG
:
1004 if (is_immediate_prefix (**str
))
1010 memset (ep
, 0, sizeof (expressionS
));
1012 save_in
= input_line_pointer
;
1013 input_line_pointer
= *str
;
1014 in_my_get_expression
= 1;
1015 seg
= expression (ep
);
1016 in_my_get_expression
= 0;
1018 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1020 /* We found a bad or missing expression in md_operand(). */
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1023 if (inst
.error
== NULL
)
1024 inst
.error
= (ep
->X_op
== O_absent
1025 ? _("missing expression") :_("bad expression"));
1030 if (seg
!= absolute_section
1031 && seg
!= text_section
1032 && seg
!= data_section
1033 && seg
!= bss_section
1034 && seg
!= undefined_section
)
1036 inst
.error
= _("bad segment");
1037 *str
= input_line_pointer
;
1038 input_line_pointer
= save_in
;
1045 /* Get rid of any bignums now, so that we don't generate an error for which
1046 we can't establish a line number later on. Big numbers are never valid
1047 in instructions, which is where this routine is always called. */
1048 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1049 && (ep
->X_op
== O_big
1050 || (ep
->X_add_symbol
1051 && (walk_no_bignums (ep
->X_add_symbol
)
1053 && walk_no_bignums (ep
->X_op_symbol
))))))
1055 inst
.error
= _("invalid constant");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1061 *str
= input_line_pointer
;
1062 input_line_pointer
= save_in
;
1066 /* Turn a string in input_line_pointer into a floating point constant
1067 of type TYPE, and store the appropriate bytes in *LITP. The number
1068 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1069 returned, or NULL on OK.
1071 Note that fp constants aren't represent in the normal way on the ARM.
1072 In big endian mode, things are as expected. However, in little endian
1073 mode fp constants are big-endian word-wise, and little-endian byte-wise
1074 within the words. For example, (double) 1.1 in big endian mode is
1075 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1076 the byte sequence 99 99 f1 3f 9a 99 99 99.
1078 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1081 md_atof (int type
, char * litP
, int * sizeP
)
1084 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1116 return _("Unrecognized or unsupported floating point constant");
1119 t
= atof_ieee (input_line_pointer
, type
, words
);
1121 input_line_pointer
= t
;
1122 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1124 if (target_big_endian
)
1126 for (i
= 0; i
< prec
; i
++)
1128 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1129 litP
+= sizeof (LITTLENUM_TYPE
);
1134 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1135 for (i
= prec
- 1; i
>= 0; i
--)
1137 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1138 litP
+= sizeof (LITTLENUM_TYPE
);
1141 /* For a 4 byte float the order of elements in `words' is 1 0.
1142 For an 8 byte float the order is 1 0 3 2. */
1143 for (i
= 0; i
< prec
; i
+= 2)
1145 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1146 sizeof (LITTLENUM_TYPE
));
1147 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1148 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1149 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1156 /* We handle all bad expressions here, so that we can report the faulty
1157 instruction in the error message. */
1159 md_operand (expressionS
* exp
)
1161 if (in_my_get_expression
)
1162 exp
->X_op
= O_illegal
;
1165 /* Immediate values. */
1167 /* Generic immediate-value read function for use in directives.
1168 Accepts anything that 'expression' can fold to a constant.
1169 *val receives the number. */
1172 immediate_for_directive (int *val
)
1175 exp
.X_op
= O_illegal
;
1177 if (is_immediate_prefix (*input_line_pointer
))
1179 input_line_pointer
++;
1183 if (exp
.X_op
!= O_constant
)
1185 as_bad (_("expected #constant"));
1186 ignore_rest_of_line ();
1189 *val
= exp
.X_add_number
;
1194 /* Register parsing. */
1196 /* Generic register parser. CCP points to what should be the
1197 beginning of a register name. If it is indeed a valid register
1198 name, advance CCP over it and return the reg_entry structure;
1199 otherwise return NULL. Does not issue diagnostics. */
1201 static struct reg_entry
*
1202 arm_reg_parse_multi (char **ccp
)
1206 struct reg_entry
*reg
;
1208 skip_whitespace (start
);
1210 #ifdef REGISTER_PREFIX
1211 if (*start
!= REGISTER_PREFIX
)
1215 #ifdef OPTIONAL_REGISTER_PREFIX
1216 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1221 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1226 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1228 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1238 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1239 enum arm_reg_type type
)
1241 /* Alternative syntaxes are accepted for a few register classes. */
1248 /* Generic coprocessor register names are allowed for these. */
1249 if (reg
&& reg
->type
== REG_TYPE_CN
)
1254 /* For backward compatibility, a bare number is valid here. */
1256 unsigned long processor
= strtoul (start
, ccp
, 10);
1257 if (*ccp
!= start
&& processor
<= 15)
1261 case REG_TYPE_MMXWC
:
1262 /* WC includes WCG. ??? I'm not sure this is true for all
1263 instructions that take WC registers. */
1264 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1275 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1276 return value is the register number or FAIL. */
1279 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1282 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1285 /* Do not allow a scalar (reg+index) to parse as a register. */
1286 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1289 if (reg
&& reg
->type
== type
)
1292 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1299 /* Parse a Neon type specifier. *STR should point at the leading '.'
1300 character. Does no verification at this stage that the type fits the opcode
1307 Can all be legally parsed by this function.
1309 Fills in neon_type struct pointer with parsed information, and updates STR
1310 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1311 type, FAIL if not. */
1314 parse_neon_type (struct neon_type
*type
, char **str
)
1321 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1323 enum neon_el_type thistype
= NT_untyped
;
1324 unsigned thissize
= -1u;
1331 /* Just a size without an explicit type. */
1335 switch (TOLOWER (*ptr
))
1337 case 'i': thistype
= NT_integer
; break;
1338 case 'f': thistype
= NT_float
; break;
1339 case 'p': thistype
= NT_poly
; break;
1340 case 's': thistype
= NT_signed
; break;
1341 case 'u': thistype
= NT_unsigned
; break;
1343 thistype
= NT_float
;
1348 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1354 /* .f is an abbreviation for .f32. */
1355 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1360 thissize
= strtoul (ptr
, &ptr
, 10);
1362 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1365 as_bad (_("bad size %d in type specifier"), thissize
);
1373 type
->el
[type
->elems
].type
= thistype
;
1374 type
->el
[type
->elems
].size
= thissize
;
1379 /* Empty/missing type is not a successful parse. */
1380 if (type
->elems
== 0)
1388 /* Errors may be set multiple times during parsing or bit encoding
1389 (particularly in the Neon bits), but usually the earliest error which is set
1390 will be the most meaningful. Avoid overwriting it with later (cascading)
1391 errors by calling this function. */
1394 first_error (const char *err
)
1400 /* Parse a single type, e.g. ".s32", leading period included. */
1402 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1405 struct neon_type optype
;
1409 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1411 if (optype
.elems
== 1)
1412 *vectype
= optype
.el
[0];
1415 first_error (_("only one type should be specified for operand"));
1421 first_error (_("vector type expected"));
1433 /* Special meanings for indices (which have a range of 0-7), which will fit into
1436 #define NEON_ALL_LANES 15
1437 #define NEON_INTERLEAVE_LANES 14
1439 /* Parse either a register or a scalar, with an optional type. Return the
1440 register number, and optionally fill in the actual type of the register
1441 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1442 type/index information in *TYPEINFO. */
1445 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1446 enum arm_reg_type
*rtype
,
1447 struct neon_typed_alias
*typeinfo
)
1450 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1451 struct neon_typed_alias atype
;
1452 struct neon_type_el parsetype
;
1456 atype
.eltype
.type
= NT_invtype
;
1457 atype
.eltype
.size
= -1;
1459 /* Try alternate syntax for some types of register. Note these are mutually
1460 exclusive with the Neon syntax extensions. */
1463 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1471 /* Undo polymorphism when a set of register types may be accepted. */
1472 if ((type
== REG_TYPE_NDQ
1473 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1474 || (type
== REG_TYPE_VFSD
1475 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1476 || (type
== REG_TYPE_NSDQ
1477 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1478 || reg
->type
== REG_TYPE_NQ
))
1479 || (type
== REG_TYPE_MMXWC
1480 && (reg
->type
== REG_TYPE_MMXWCG
)))
1481 type
= (enum arm_reg_type
) reg
->type
;
1483 if (type
!= reg
->type
)
1489 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1491 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1493 first_error (_("can't redefine type for operand"));
1496 atype
.defined
|= NTA_HASTYPE
;
1497 atype
.eltype
= parsetype
;
1500 if (skip_past_char (&str
, '[') == SUCCESS
)
1502 if (type
!= REG_TYPE_VFD
)
1504 first_error (_("only D registers may be indexed"));
1508 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1510 first_error (_("can't change index for operand"));
1514 atype
.defined
|= NTA_HASINDEX
;
1516 if (skip_past_char (&str
, ']') == SUCCESS
)
1517 atype
.index
= NEON_ALL_LANES
;
1522 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1524 if (exp
.X_op
!= O_constant
)
1526 first_error (_("constant expression required"));
1530 if (skip_past_char (&str
, ']') == FAIL
)
1533 atype
.index
= exp
.X_add_number
;
1548 /* Like arm_reg_parse, but allow allow the following extra features:
1549 - If RTYPE is non-zero, return the (possibly restricted) type of the
1550 register (e.g. Neon double or quad reg when either has been requested).
1551 - If this is a Neon vector type with additional type information, fill
1552 in the struct pointed to by VECTYPE (if non-NULL).
1553 This function will fault on encountering a scalar. */
1556 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1557 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1559 struct neon_typed_alias atype
;
1561 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1566 /* Do not allow regname(... to parse as a register. */
1570 /* Do not allow a scalar (reg+index) to parse as a register. */
1571 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1573 first_error (_("register operand expected, but got scalar"));
1578 *vectype
= atype
.eltype
;
1585 #define NEON_SCALAR_REG(X) ((X) >> 4)
1586 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1588 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1589 have enough information to be able to do a good job bounds-checking. So, we
1590 just do easy checks here, and do further checks later. */
1593 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1597 struct neon_typed_alias atype
;
1599 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1601 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1604 if (atype
.index
== NEON_ALL_LANES
)
1606 first_error (_("scalar must have an index"));
1609 else if (atype
.index
>= 64 / elsize
)
1611 first_error (_("scalar index out of range"));
1616 *type
= atype
.eltype
;
1620 return reg
* 16 + atype
.index
;
1623 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1626 parse_reg_list (char ** strp
)
1628 char * str
= * strp
;
1632 /* We come back here if we get ranges concatenated by '+' or '|'. */
1635 skip_whitespace (str
);
1649 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1651 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1661 first_error (_("bad range in register list"));
1665 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1667 if (range
& (1 << i
))
1669 (_("Warning: duplicated register (r%d) in register list"),
1677 if (range
& (1 << reg
))
1678 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1680 else if (reg
<= cur_reg
)
1681 as_tsktsk (_("Warning: register range not in ascending order"));
1686 while (skip_past_comma (&str
) != FAIL
1687 || (in_range
= 1, *str
++ == '-'));
1690 if (skip_past_char (&str
, '}') == FAIL
)
1692 first_error (_("missing `}'"));
1700 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1703 if (exp
.X_op
== O_constant
)
1705 if (exp
.X_add_number
1706 != (exp
.X_add_number
& 0x0000ffff))
1708 inst
.error
= _("invalid register mask");
1712 if ((range
& exp
.X_add_number
) != 0)
1714 int regno
= range
& exp
.X_add_number
;
1717 regno
= (1 << regno
) - 1;
1719 (_("Warning: duplicated register (r%d) in register list"),
1723 range
|= exp
.X_add_number
;
1727 if (inst
.reloc
.type
!= 0)
1729 inst
.error
= _("expression too complex");
1733 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1734 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1735 inst
.reloc
.pc_rel
= 0;
1739 if (*str
== '|' || *str
== '+')
1745 while (another_range
);
1751 /* Types of registers in a list. */
1760 /* Parse a VFP register list. If the string is invalid return FAIL.
1761 Otherwise return the number of registers, and set PBASE to the first
1762 register. Parses registers of type ETYPE.
1763 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1764 - Q registers can be used to specify pairs of D registers
1765 - { } can be omitted from around a singleton register list
1766 FIXME: This is not implemented, as it would require backtracking in
1769 This could be done (the meaning isn't really ambiguous), but doesn't
1770 fit in well with the current parsing framework.
1771 - 32 D registers may be used (also true for VFPv3).
1772 FIXME: Types are ignored in these register lists, which is probably a
1776 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1781 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1785 unsigned long mask
= 0;
1788 if (skip_past_char (&str
, '{') == FAIL
)
1790 inst
.error
= _("expecting {");
1797 regtype
= REG_TYPE_VFS
;
1802 regtype
= REG_TYPE_VFD
;
1805 case REGLIST_NEON_D
:
1806 regtype
= REG_TYPE_NDQ
;
1810 if (etype
!= REGLIST_VFP_S
)
1812 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1813 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1817 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1820 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1827 base_reg
= max_regs
;
1831 int setmask
= 1, addregs
= 1;
1833 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1835 if (new_base
== FAIL
)
1837 first_error (_(reg_expected_msgs
[regtype
]));
1841 if (new_base
>= max_regs
)
1843 first_error (_("register out of range in list"));
1847 /* Note: a value of 2 * n is returned for the register Q<n>. */
1848 if (regtype
== REG_TYPE_NQ
)
1854 if (new_base
< base_reg
)
1855 base_reg
= new_base
;
1857 if (mask
& (setmask
<< new_base
))
1859 first_error (_("invalid register list"));
1863 if ((mask
>> new_base
) != 0 && ! warned
)
1865 as_tsktsk (_("register list not in ascending order"));
1869 mask
|= setmask
<< new_base
;
1872 if (*str
== '-') /* We have the start of a range expression */
1878 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1881 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1885 if (high_range
>= max_regs
)
1887 first_error (_("register out of range in list"));
1891 if (regtype
== REG_TYPE_NQ
)
1892 high_range
= high_range
+ 1;
1894 if (high_range
<= new_base
)
1896 inst
.error
= _("register range not in ascending order");
1900 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1902 if (mask
& (setmask
<< new_base
))
1904 inst
.error
= _("invalid register list");
1908 mask
|= setmask
<< new_base
;
1913 while (skip_past_comma (&str
) != FAIL
);
1917 /* Sanity check -- should have raised a parse error above. */
1918 if (count
== 0 || count
> max_regs
)
1923 /* Final test -- the registers must be consecutive. */
1925 for (i
= 0; i
< count
; i
++)
1927 if ((mask
& (1u << i
)) == 0)
1929 inst
.error
= _("non-contiguous register range");
1939 /* True if two alias types are the same. */
1942 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1950 if (a
->defined
!= b
->defined
)
1953 if ((a
->defined
& NTA_HASTYPE
) != 0
1954 && (a
->eltype
.type
!= b
->eltype
.type
1955 || a
->eltype
.size
!= b
->eltype
.size
))
1958 if ((a
->defined
& NTA_HASINDEX
) != 0
1959 && (a
->index
!= b
->index
))
1965 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1966 The base register is put in *PBASE.
1967 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1969 The register stride (minus one) is put in bit 4 of the return value.
1970 Bits [6:5] encode the list length (minus one).
1971 The type of the list elements is put in *ELTYPE, if non-NULL. */
1973 #define NEON_LANE(X) ((X) & 0xf)
1974 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1975 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1978 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1979 struct neon_type_el
*eltype
)
1986 int leading_brace
= 0;
1987 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1988 const char *const incr_error
= _("register stride must be 1 or 2");
1989 const char *const type_error
= _("mismatched element/structure types in list");
1990 struct neon_typed_alias firsttype
;
1992 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1997 struct neon_typed_alias atype
;
1998 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2002 first_error (_(reg_expected_msgs
[rtype
]));
2009 if (rtype
== REG_TYPE_NQ
)
2015 else if (reg_incr
== -1)
2017 reg_incr
= getreg
- base_reg
;
2018 if (reg_incr
< 1 || reg_incr
> 2)
2020 first_error (_(incr_error
));
2024 else if (getreg
!= base_reg
+ reg_incr
* count
)
2026 first_error (_(incr_error
));
2030 if (! neon_alias_types_same (&atype
, &firsttype
))
2032 first_error (_(type_error
));
2036 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2040 struct neon_typed_alias htype
;
2041 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2043 lane
= NEON_INTERLEAVE_LANES
;
2044 else if (lane
!= NEON_INTERLEAVE_LANES
)
2046 first_error (_(type_error
));
2051 else if (reg_incr
!= 1)
2053 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2057 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2060 first_error (_(reg_expected_msgs
[rtype
]));
2063 if (! neon_alias_types_same (&htype
, &firsttype
))
2065 first_error (_(type_error
));
2068 count
+= hireg
+ dregs
- getreg
;
2072 /* If we're using Q registers, we can't use [] or [n] syntax. */
2073 if (rtype
== REG_TYPE_NQ
)
2079 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2083 else if (lane
!= atype
.index
)
2085 first_error (_(type_error
));
2089 else if (lane
== -1)
2090 lane
= NEON_INTERLEAVE_LANES
;
2091 else if (lane
!= NEON_INTERLEAVE_LANES
)
2093 first_error (_(type_error
));
2098 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2100 /* No lane set by [x]. We must be interleaving structures. */
2102 lane
= NEON_INTERLEAVE_LANES
;
2105 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2106 || (count
> 1 && reg_incr
== -1))
2108 first_error (_("error parsing element/structure list"));
2112 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2114 first_error (_("expected }"));
2122 *eltype
= firsttype
.eltype
;
2127 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2130 /* Parse an explicit relocation suffix on an expression. This is
2131 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2132 arm_reloc_hsh contains no entries, so this function can only
2133 succeed if there is no () after the word. Returns -1 on error,
2134 BFD_RELOC_UNUSED if there wasn't any suffix. */
2137 parse_reloc (char **str
)
2139 struct reloc_entry
*r
;
2143 return BFD_RELOC_UNUSED
;
2148 while (*q
&& *q
!= ')' && *q
!= ',')
2153 if ((r
= (struct reloc_entry
*)
2154 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2161 /* Directives: register aliases. */
2163 static struct reg_entry
*
2164 insert_reg_alias (char *str
, unsigned number
, int type
)
2166 struct reg_entry
*new_reg
;
2169 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2171 if (new_reg
->builtin
)
2172 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2174 /* Only warn about a redefinition if it's not defined as the
2176 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2177 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2182 name
= xstrdup (str
);
2183 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2185 new_reg
->name
= name
;
2186 new_reg
->number
= number
;
2187 new_reg
->type
= type
;
2188 new_reg
->builtin
= FALSE
;
2189 new_reg
->neon
= NULL
;
2191 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2198 insert_neon_reg_alias (char *str
, int number
, int type
,
2199 struct neon_typed_alias
*atype
)
2201 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2205 first_error (_("attempt to redefine typed alias"));
2211 reg
->neon
= (struct neon_typed_alias
*)
2212 xmalloc (sizeof (struct neon_typed_alias
));
2213 *reg
->neon
= *atype
;
2217 /* Look for the .req directive. This is of the form:
2219 new_register_name .req existing_register_name
2221 If we find one, or if it looks sufficiently like one that we want to
2222 handle any error here, return TRUE. Otherwise return FALSE. */
2225 create_register_alias (char * newname
, char *p
)
2227 struct reg_entry
*old
;
2228 char *oldname
, *nbuf
;
2231 /* The input scrubber ensures that whitespace after the mnemonic is
2232 collapsed to single spaces. */
2234 if (strncmp (oldname
, " .req ", 6) != 0)
2238 if (*oldname
== '\0')
2241 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2244 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2248 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2249 the desired alias name, and p points to its end. If not, then
2250 the desired alias name is in the global original_case_string. */
2251 #ifdef TC_CASE_SENSITIVE
2254 newname
= original_case_string
;
2255 nlen
= strlen (newname
);
2258 nbuf
= (char *) alloca (nlen
+ 1);
2259 memcpy (nbuf
, newname
, nlen
);
2262 /* Create aliases under the new name as stated; an all-lowercase
2263 version of the new name; and an all-uppercase version of the new
2265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2267 for (p
= nbuf
; *p
; p
++)
2270 if (strncmp (nbuf
, newname
, nlen
))
2272 /* If this attempt to create an additional alias fails, do not bother
2273 trying to create the all-lower case alias. We will fail and issue
2274 a second, duplicate error message. This situation arises when the
2275 programmer does something like:
2278 The second .req creates the "Foo" alias but then fails to create
2279 the artificial FOO alias because it has already been created by the
2281 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2285 for (p
= nbuf
; *p
; p
++)
2288 if (strncmp (nbuf
, newname
, nlen
))
2289 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2295 /* Create a Neon typed/indexed register alias using directives, e.g.:
2300 These typed registers can be used instead of the types specified after the
2301 Neon mnemonic, so long as all operands given have types. Types can also be
2302 specified directly, e.g.:
2303 vadd d0.s32, d1.s32, d2.s32 */
2306 create_neon_reg_alias (char *newname
, char *p
)
2308 enum arm_reg_type basetype
;
2309 struct reg_entry
*basereg
;
2310 struct reg_entry mybasereg
;
2311 struct neon_type ntype
;
2312 struct neon_typed_alias typeinfo
;
2313 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2316 typeinfo
.defined
= 0;
2317 typeinfo
.eltype
.type
= NT_invtype
;
2318 typeinfo
.eltype
.size
= -1;
2319 typeinfo
.index
= -1;
2323 if (strncmp (p
, " .dn ", 5) == 0)
2324 basetype
= REG_TYPE_VFD
;
2325 else if (strncmp (p
, " .qn ", 5) == 0)
2326 basetype
= REG_TYPE_NQ
;
2335 basereg
= arm_reg_parse_multi (&p
);
2337 if (basereg
&& basereg
->type
!= basetype
)
2339 as_bad (_("bad type for register"));
2343 if (basereg
== NULL
)
2346 /* Try parsing as an integer. */
2347 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2348 if (exp
.X_op
!= O_constant
)
2350 as_bad (_("expression must be constant"));
2353 basereg
= &mybasereg
;
2354 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2360 typeinfo
= *basereg
->neon
;
2362 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2364 /* We got a type. */
2365 if (typeinfo
.defined
& NTA_HASTYPE
)
2367 as_bad (_("can't redefine the type of a register alias"));
2371 typeinfo
.defined
|= NTA_HASTYPE
;
2372 if (ntype
.elems
!= 1)
2374 as_bad (_("you must specify a single type only"));
2377 typeinfo
.eltype
= ntype
.el
[0];
2380 if (skip_past_char (&p
, '[') == SUCCESS
)
2383 /* We got a scalar index. */
2385 if (typeinfo
.defined
& NTA_HASINDEX
)
2387 as_bad (_("can't redefine the index of a scalar alias"));
2391 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2393 if (exp
.X_op
!= O_constant
)
2395 as_bad (_("scalar index must be constant"));
2399 typeinfo
.defined
|= NTA_HASINDEX
;
2400 typeinfo
.index
= exp
.X_add_number
;
2402 if (skip_past_char (&p
, ']') == FAIL
)
2404 as_bad (_("expecting ]"));
2409 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2410 the desired alias name, and p points to its end. If not, then
2411 the desired alias name is in the global original_case_string. */
2412 #ifdef TC_CASE_SENSITIVE
2413 namelen
= nameend
- newname
;
2415 newname
= original_case_string
;
2416 namelen
= strlen (newname
);
2419 namebuf
= (char *) alloca (namelen
+ 1);
2420 strncpy (namebuf
, newname
, namelen
);
2421 namebuf
[namelen
] = '\0';
2423 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2424 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2426 /* Insert name in all uppercase. */
2427 for (p
= namebuf
; *p
; p
++)
2430 if (strncmp (namebuf
, newname
, namelen
))
2431 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2432 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2434 /* Insert name in all lowercase. */
2435 for (p
= namebuf
; *p
; p
++)
2438 if (strncmp (namebuf
, newname
, namelen
))
2439 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2440 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2445 /* Should never be called, as .req goes between the alias and the
2446 register name, not at the beginning of the line. */
2449 s_req (int a ATTRIBUTE_UNUSED
)
2451 as_bad (_("invalid syntax for .req directive"));
2455 s_dn (int a ATTRIBUTE_UNUSED
)
2457 as_bad (_("invalid syntax for .dn directive"));
2461 s_qn (int a ATTRIBUTE_UNUSED
)
2463 as_bad (_("invalid syntax for .qn directive"));
2466 /* The .unreq directive deletes an alias which was previously defined
2467 by .req. For example:
2473 s_unreq (int a ATTRIBUTE_UNUSED
)
2478 name
= input_line_pointer
;
2480 while (*input_line_pointer
!= 0
2481 && *input_line_pointer
!= ' '
2482 && *input_line_pointer
!= '\n')
2483 ++input_line_pointer
;
2485 saved_char
= *input_line_pointer
;
2486 *input_line_pointer
= 0;
2489 as_bad (_("invalid syntax for .unreq directive"));
2492 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2496 as_bad (_("unknown register alias '%s'"), name
);
2497 else if (reg
->builtin
)
2498 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2505 hash_delete (arm_reg_hsh
, name
, FALSE
);
2506 free ((char *) reg
->name
);
2511 /* Also locate the all upper case and all lower case versions.
2512 Do not complain if we cannot find one or the other as it
2513 was probably deleted above. */
2515 nbuf
= strdup (name
);
2516 for (p
= nbuf
; *p
; p
++)
2518 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2521 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2522 free ((char *) reg
->name
);
2528 for (p
= nbuf
; *p
; p
++)
2530 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2533 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2534 free ((char *) reg
->name
);
2544 *input_line_pointer
= saved_char
;
2545 demand_empty_rest_of_line ();
2548 /* Directives: Instruction set selection. */
2551 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2552 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2553 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2554 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2556 /* Create a new mapping symbol for the transition to STATE. */
2559 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2562 const char * symname
;
2569 type
= BSF_NO_FLAGS
;
2573 type
= BSF_NO_FLAGS
;
2577 type
= BSF_NO_FLAGS
;
2583 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2584 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2589 THUMB_SET_FUNC (symbolP
, 0);
2590 ARM_SET_THUMB (symbolP
, 0);
2591 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2595 THUMB_SET_FUNC (symbolP
, 1);
2596 ARM_SET_THUMB (symbolP
, 1);
2597 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2605 /* Save the mapping symbols for future reference. Also check that
2606 we do not place two mapping symbols at the same offset within a
2607 frag. We'll handle overlap between frags in
2608 check_mapping_symbols.
2610 If .fill or other data filling directive generates zero sized data,
2611 the mapping symbol for the following code will have the same value
2612 as the one generated for the data filling directive. In this case,
2613 we replace the old symbol with the new one at the same address. */
2616 if (frag
->tc_frag_data
.first_map
!= NULL
)
2618 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2619 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2621 frag
->tc_frag_data
.first_map
= symbolP
;
2623 if (frag
->tc_frag_data
.last_map
!= NULL
)
2625 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2626 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2627 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2629 frag
->tc_frag_data
.last_map
= symbolP
;
2632 /* We must sometimes convert a region marked as code to data during
2633 code alignment, if an odd number of bytes have to be padded. The
2634 code mapping symbol is pushed to an aligned address. */
2637 insert_data_mapping_symbol (enum mstate state
,
2638 valueT value
, fragS
*frag
, offsetT bytes
)
2640 /* If there was already a mapping symbol, remove it. */
2641 if (frag
->tc_frag_data
.last_map
!= NULL
2642 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2644 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2648 know (frag
->tc_frag_data
.first_map
== symp
);
2649 frag
->tc_frag_data
.first_map
= NULL
;
2651 frag
->tc_frag_data
.last_map
= NULL
;
2652 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2655 make_mapping_symbol (MAP_DATA
, value
, frag
);
2656 make_mapping_symbol (state
, value
+ bytes
, frag
);
2659 static void mapping_state_2 (enum mstate state
, int max_chars
);
2661 /* Set the mapping state to STATE. Only call this when about to
2662 emit some STATE bytes to the file. */
2664 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2666 mapping_state (enum mstate state
)
2668 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2670 if (mapstate
== state
)
2671 /* The mapping symbol has already been emitted.
2672 There is nothing else to do. */
2675 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2677 All ARM instructions require 4-byte alignment.
2678 (Almost) all Thumb instructions require 2-byte alignment.
2680 When emitting instructions into any section, mark the section
2683 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2684 but themselves require 2-byte alignment; this applies to some
2685 PC- relative forms. However, these cases will invovle implicit
2686 literal pool generation or an explicit .align >=2, both of
2687 which will cause the section to me marked with sufficient
2688 alignment. Thus, we don't handle those cases here. */
2689 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2691 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2692 /* This case will be evaluated later. */
2695 mapping_state_2 (state
, 0);
2698 /* Same as mapping_state, but MAX_CHARS bytes have already been
2699 allocated. Put the mapping symbol that far back. */
2702 mapping_state_2 (enum mstate state
, int max_chars
)
2704 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2706 if (!SEG_NORMAL (now_seg
))
2709 if (mapstate
== state
)
2710 /* The mapping symbol has already been emitted.
2711 There is nothing else to do. */
2714 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2715 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2717 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2718 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2721 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2724 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2725 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2729 #define mapping_state(x) ((void)0)
2730 #define mapping_state_2(x, y) ((void)0)
2733 /* Find the real, Thumb encoded start of a Thumb function. */
2737 find_real_start (symbolS
* symbolP
)
2740 const char * name
= S_GET_NAME (symbolP
);
2741 symbolS
* new_target
;
2743 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2744 #define STUB_NAME ".real_start_of"
2749 /* The compiler may generate BL instructions to local labels because
2750 it needs to perform a branch to a far away location. These labels
2751 do not have a corresponding ".real_start_of" label. We check
2752 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2753 the ".real_start_of" convention for nonlocal branches. */
2754 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2757 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2758 new_target
= symbol_find (real_start
);
2760 if (new_target
== NULL
)
2762 as_warn (_("Failed to find real start of function: %s\n"), name
);
2763 new_target
= symbolP
;
2771 opcode_select (int width
)
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2779 as_bad (_("selected processor does not support THUMB opcodes"));
2782 /* No need to force the alignment, since we will have been
2783 coming from ARM mode, which is word-aligned. */
2784 record_alignment (now_seg
, 1);
2791 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2792 as_bad (_("selected processor does not support ARM opcodes"));
2797 frag_align (2, 0, 0);
2799 record_alignment (now_seg
, 1);
2804 as_bad (_("invalid instruction size selected (%d)"), width
);
2809 s_arm (int ignore ATTRIBUTE_UNUSED
)
2812 demand_empty_rest_of_line ();
2816 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2819 demand_empty_rest_of_line ();
2823 s_code (int unused ATTRIBUTE_UNUSED
)
2827 temp
= get_absolute_expression ();
2832 opcode_select (temp
);
2836 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2841 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2843 /* If we are not already in thumb mode go into it, EVEN if
2844 the target processor does not support thumb instructions.
2845 This is used by gcc/config/arm/lib1funcs.asm for example
2846 to compile interworking support functions even if the
2847 target processor should not support interworking. */
2851 record_alignment (now_seg
, 1);
2854 demand_empty_rest_of_line ();
2858 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2862 /* The following label is the name/address of the start of a Thumb function.
2863 We need to know this for the interworking support. */
2864 label_is_thumb_function_name
= TRUE
;
2867 /* Perform a .set directive, but also mark the alias as
2868 being a thumb function. */
2871 s_thumb_set (int equiv
)
2873 /* XXX the following is a duplicate of the code for s_set() in read.c
2874 We cannot just call that code as we need to get at the symbol that
2881 /* Especial apologies for the random logic:
2882 This just grew, and could be parsed much more simply!
2884 delim
= get_symbol_name (& name
);
2885 end_name
= input_line_pointer
;
2886 (void) restore_line_pointer (delim
);
2888 if (*input_line_pointer
!= ',')
2891 as_bad (_("expected comma after name \"%s\""), name
);
2893 ignore_rest_of_line ();
2897 input_line_pointer
++;
2900 if (name
[0] == '.' && name
[1] == '\0')
2902 /* XXX - this should not happen to .thumb_set. */
2906 if ((symbolP
= symbol_find (name
)) == NULL
2907 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2910 /* When doing symbol listings, play games with dummy fragments living
2911 outside the normal fragment chain to record the file and line info
2913 if (listing
& LISTING_SYMBOLS
)
2915 extern struct list_info_struct
* listing_tail
;
2916 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2918 memset (dummy_frag
, 0, sizeof (fragS
));
2919 dummy_frag
->fr_type
= rs_fill
;
2920 dummy_frag
->line
= listing_tail
;
2921 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2922 dummy_frag
->fr_symbol
= symbolP
;
2926 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2929 /* "set" symbols are local unless otherwise specified. */
2930 SF_SET_LOCAL (symbolP
);
2931 #endif /* OBJ_COFF */
2932 } /* Make a new symbol. */
2934 symbol_table_insert (symbolP
);
2939 && S_IS_DEFINED (symbolP
)
2940 && S_GET_SEGMENT (symbolP
) != reg_section
)
2941 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2943 pseudo_set (symbolP
);
2945 demand_empty_rest_of_line ();
2947 /* XXX Now we come to the Thumb specific bit of code. */
2949 THUMB_SET_FUNC (symbolP
, 1);
2950 ARM_SET_THUMB (symbolP
, 1);
2951 #if defined OBJ_ELF || defined OBJ_COFF
2952 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2956 /* Directives: Mode selection. */
2958 /* .syntax [unified|divided] - choose the new unified syntax
2959 (same for Arm and Thumb encoding, modulo slight differences in what
2960 can be represented) or the old divergent syntax for each mode. */
2962 s_syntax (int unused ATTRIBUTE_UNUSED
)
2966 delim
= get_symbol_name (& name
);
2968 if (!strcasecmp (name
, "unified"))
2969 unified_syntax
= TRUE
;
2970 else if (!strcasecmp (name
, "divided"))
2971 unified_syntax
= FALSE
;
2974 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2977 (void) restore_line_pointer (delim
);
2978 demand_empty_rest_of_line ();
2981 /* Directives: sectioning and alignment. */
2984 s_bss (int ignore ATTRIBUTE_UNUSED
)
2986 /* We don't support putting frags in the BSS segment, we fake it by
2987 marking in_bss, then looking at s_skip for clues. */
2988 subseg_set (bss_section
, 0);
2989 demand_empty_rest_of_line ();
2991 #ifdef md_elf_section_change_hook
2992 md_elf_section_change_hook ();
2997 s_even (int ignore ATTRIBUTE_UNUSED
)
2999 /* Never make frag if expect extra pass. */
3001 frag_align (1, 0, 0);
3003 record_alignment (now_seg
, 1);
3005 demand_empty_rest_of_line ();
3008 /* Directives: CodeComposer Studio. */
3010 /* .ref (for CodeComposer Studio syntax only). */
3012 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3014 if (codecomposer_syntax
)
3015 ignore_rest_of_line ();
3017 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3020 /* If name is not NULL, then it is used for marking the beginning of a
3021 function, wherease if it is NULL then it means the function end. */
3023 asmfunc_debug (const char * name
)
3025 static const char * last_name
= NULL
;
3029 gas_assert (last_name
== NULL
);
3032 if (debug_type
== DEBUG_STABS
)
3033 stabs_generate_asm_func (name
, name
);
3037 gas_assert (last_name
!= NULL
);
3039 if (debug_type
== DEBUG_STABS
)
3040 stabs_generate_asm_endfunc (last_name
, last_name
);
3047 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3049 if (codecomposer_syntax
)
3051 switch (asmfunc_state
)
3053 case OUTSIDE_ASMFUNC
:
3054 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3057 case WAITING_ASMFUNC_NAME
:
3058 as_bad (_(".asmfunc repeated."));
3061 case WAITING_ENDASMFUNC
:
3062 as_bad (_(".asmfunc without function."));
3065 demand_empty_rest_of_line ();
3068 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3072 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3074 if (codecomposer_syntax
)
3076 switch (asmfunc_state
)
3078 case OUTSIDE_ASMFUNC
:
3079 as_bad (_(".endasmfunc without a .asmfunc."));
3082 case WAITING_ASMFUNC_NAME
:
3083 as_bad (_(".endasmfunc without function."));
3086 case WAITING_ENDASMFUNC
:
3087 asmfunc_state
= OUTSIDE_ASMFUNC
;
3088 asmfunc_debug (NULL
);
3091 demand_empty_rest_of_line ();
3094 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3098 s_ccs_def (int name
)
3100 if (codecomposer_syntax
)
3103 as_bad (_(".def pseudo-op only available with -mccs flag."));
3106 /* Directives: Literal pools. */
3108 static literal_pool
*
3109 find_literal_pool (void)
3111 literal_pool
* pool
;
3113 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3115 if (pool
->section
== now_seg
3116 && pool
->sub_section
== now_subseg
)
3123 static literal_pool
*
3124 find_or_make_literal_pool (void)
3126 /* Next literal pool ID number. */
3127 static unsigned int latest_pool_num
= 1;
3128 literal_pool
* pool
;
3130 pool
= find_literal_pool ();
3134 /* Create a new pool. */
3135 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3139 pool
->next_free_entry
= 0;
3140 pool
->section
= now_seg
;
3141 pool
->sub_section
= now_subseg
;
3142 pool
->next
= list_of_pools
;
3143 pool
->symbol
= NULL
;
3144 pool
->alignment
= 2;
3146 /* Add it to the list. */
3147 list_of_pools
= pool
;
3150 /* New pools, and emptied pools, will have a NULL symbol. */
3151 if (pool
->symbol
== NULL
)
3153 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3154 (valueT
) 0, &zero_address_frag
);
3155 pool
->id
= latest_pool_num
++;
3162 /* Add the literal in the global 'inst'
3163 structure to the relevant literal pool. */
3166 add_to_lit_pool (unsigned int nbytes
)
3168 #define PADDING_SLOT 0x1
3169 #define LIT_ENTRY_SIZE_MASK 0xFF
3170 literal_pool
* pool
;
3171 unsigned int entry
, pool_size
= 0;
3172 bfd_boolean padding_slot_p
= FALSE
;
3178 imm1
= inst
.operands
[1].imm
;
3179 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3180 : inst
.reloc
.exp
.X_unsigned
? 0
3181 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3182 if (target_big_endian
)
3185 imm2
= inst
.operands
[1].imm
;
3189 pool
= find_or_make_literal_pool ();
3191 /* Check if this literal value is already in the pool. */
3192 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3196 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3197 && (inst
.reloc
.exp
.X_op
== O_constant
)
3198 && (pool
->literals
[entry
].X_add_number
3199 == inst
.reloc
.exp
.X_add_number
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
)
3201 && (pool
->literals
[entry
].X_unsigned
3202 == inst
.reloc
.exp
.X_unsigned
))
3205 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3206 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3207 && (pool
->literals
[entry
].X_add_number
3208 == inst
.reloc
.exp
.X_add_number
)
3209 && (pool
->literals
[entry
].X_add_symbol
3210 == inst
.reloc
.exp
.X_add_symbol
)
3211 && (pool
->literals
[entry
].X_op_symbol
3212 == inst
.reloc
.exp
.X_op_symbol
)
3213 && (pool
->literals
[entry
].X_md
== nbytes
))
3216 else if ((nbytes
== 8)
3217 && !(pool_size
& 0x7)
3218 && ((entry
+ 1) != pool
->next_free_entry
)
3219 && (pool
->literals
[entry
].X_op
== O_constant
)
3220 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3221 && (pool
->literals
[entry
].X_unsigned
3222 == inst
.reloc
.exp
.X_unsigned
)
3223 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3224 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3225 && (pool
->literals
[entry
+ 1].X_unsigned
3226 == inst
.reloc
.exp
.X_unsigned
))
3229 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3230 if (padding_slot_p
&& (nbytes
== 4))
3236 /* Do we need to create a new entry? */
3237 if (entry
== pool
->next_free_entry
)
3239 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3241 inst
.error
= _("literal pool overflow");
3247 /* For 8-byte entries, we align to an 8-byte boundary,
3248 and split it into two 4-byte entries, because on 32-bit
3249 host, 8-byte constants are treated as big num, thus
3250 saved in "generic_bignum" which will be overwritten
3251 by later assignments.
3253 We also need to make sure there is enough space for
3256 We also check to make sure the literal operand is a
3258 if (!(inst
.reloc
.exp
.X_op
== O_constant
3259 || inst
.reloc
.exp
.X_op
== O_big
))
3261 inst
.error
= _("invalid type for literal pool");
3264 else if (pool_size
& 0x7)
3266 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3268 inst
.error
= _("literal pool overflow");
3272 pool
->literals
[entry
] = inst
.reloc
.exp
;
3273 pool
->literals
[entry
].X_add_number
= 0;
3274 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3275 pool
->next_free_entry
+= 1;
3278 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3280 inst
.error
= _("literal pool overflow");
3284 pool
->literals
[entry
] = inst
.reloc
.exp
;
3285 pool
->literals
[entry
].X_op
= O_constant
;
3286 pool
->literals
[entry
].X_add_number
= imm1
;
3287 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3288 pool
->literals
[entry
++].X_md
= 4;
3289 pool
->literals
[entry
] = inst
.reloc
.exp
;
3290 pool
->literals
[entry
].X_op
= O_constant
;
3291 pool
->literals
[entry
].X_add_number
= imm2
;
3292 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3293 pool
->literals
[entry
].X_md
= 4;
3294 pool
->alignment
= 3;
3295 pool
->next_free_entry
+= 1;
3299 pool
->literals
[entry
] = inst
.reloc
.exp
;
3300 pool
->literals
[entry
].X_md
= 4;
3304 /* PR ld/12974: Record the location of the first source line to reference
3305 this entry in the literal pool. If it turns out during linking that the
3306 symbol does not exist we will be able to give an accurate line number for
3307 the (first use of the) missing reference. */
3308 if (debug_type
== DEBUG_DWARF2
)
3309 dwarf2_where (pool
->locs
+ entry
);
3311 pool
->next_free_entry
+= 1;
3313 else if (padding_slot_p
)
3315 pool
->literals
[entry
] = inst
.reloc
.exp
;
3316 pool
->literals
[entry
].X_md
= nbytes
;
3319 inst
.reloc
.exp
.X_op
= O_symbol
;
3320 inst
.reloc
.exp
.X_add_number
= pool_size
;
3321 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3327 tc_start_label_without_colon (void)
3329 bfd_boolean ret
= TRUE
;
3331 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3333 const char *label
= input_line_pointer
;
3335 while (!is_end_of_line
[(int) label
[-1]])
3340 as_bad (_("Invalid label '%s'"), label
);
3344 asmfunc_debug (label
);
3346 asmfunc_state
= WAITING_ENDASMFUNC
;
3352 /* Can't use symbol_new here, so have to create a symbol and then at
3353 a later date assign it a value. Thats what these functions do. */
3356 symbol_locate (symbolS
* symbolP
,
3357 const char * name
, /* It is copied, the caller can modify. */
3358 segT segment
, /* Segment identifier (SEG_<something>). */
3359 valueT valu
, /* Symbol value. */
3360 fragS
* frag
) /* Associated fragment. */
3363 char * preserved_copy_of_name
;
3365 name_length
= strlen (name
) + 1; /* +1 for \0. */
3366 obstack_grow (¬es
, name
, name_length
);
3367 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3369 #ifdef tc_canonicalize_symbol_name
3370 preserved_copy_of_name
=
3371 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3374 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3376 S_SET_SEGMENT (symbolP
, segment
);
3377 S_SET_VALUE (symbolP
, valu
);
3378 symbol_clear_list_pointers (symbolP
);
3380 symbol_set_frag (symbolP
, frag
);
3382 /* Link to end of symbol chain. */
3384 extern int symbol_table_frozen
;
3386 if (symbol_table_frozen
)
3390 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3392 obj_symbol_new_hook (symbolP
);
3394 #ifdef tc_symbol_new_hook
3395 tc_symbol_new_hook (symbolP
);
3399 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3400 #endif /* DEBUG_SYMS */
3404 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3407 literal_pool
* pool
;
3410 pool
= find_literal_pool ();
3412 || pool
->symbol
== NULL
3413 || pool
->next_free_entry
== 0)
3416 /* Align pool as you have word accesses.
3417 Only make a frag if we have to. */
3419 frag_align (pool
->alignment
, 0, 0);
3421 record_alignment (now_seg
, 2);
3424 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3425 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3427 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3429 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3430 (valueT
) frag_now_fix (), frag_now
);
3431 symbol_table_insert (pool
->symbol
);
3433 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3435 #if defined OBJ_COFF || defined OBJ_ELF
3436 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3439 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3442 if (debug_type
== DEBUG_DWARF2
)
3443 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3445 /* First output the expression in the instruction to the pool. */
3446 emit_expr (&(pool
->literals
[entry
]),
3447 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3450 /* Mark the pool as empty. */
3451 pool
->next_free_entry
= 0;
3452 pool
->symbol
= NULL
;
3456 /* Forward declarations for functions below, in the MD interface
3458 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3459 static valueT
create_unwind_entry (int);
3460 static void start_unwind_section (const segT
, int);
3461 static void add_unwind_opcode (valueT
, int);
3462 static void flush_pending_unwind (void);
3464 /* Directives: Data. */
3467 s_arm_elf_cons (int nbytes
)
3471 #ifdef md_flush_pending_output
3472 md_flush_pending_output ();
3475 if (is_it_end_of_statement ())
3477 demand_empty_rest_of_line ();
3481 #ifdef md_cons_align
3482 md_cons_align (nbytes
);
3485 mapping_state (MAP_DATA
);
3489 char *base
= input_line_pointer
;
3493 if (exp
.X_op
!= O_symbol
)
3494 emit_expr (&exp
, (unsigned int) nbytes
);
3497 char *before_reloc
= input_line_pointer
;
3498 reloc
= parse_reloc (&input_line_pointer
);
3501 as_bad (_("unrecognized relocation suffix"));
3502 ignore_rest_of_line ();
3505 else if (reloc
== BFD_RELOC_UNUSED
)
3506 emit_expr (&exp
, (unsigned int) nbytes
);
3509 reloc_howto_type
*howto
= (reloc_howto_type
*)
3510 bfd_reloc_type_lookup (stdoutput
,
3511 (bfd_reloc_code_real_type
) reloc
);
3512 int size
= bfd_get_reloc_size (howto
);
3514 if (reloc
== BFD_RELOC_ARM_PLT32
)
3516 as_bad (_("(plt) is only valid on branch targets"));
3517 reloc
= BFD_RELOC_UNUSED
;
3522 as_bad (_("%s relocations do not fit in %d bytes"),
3523 howto
->name
, nbytes
);
3526 /* We've parsed an expression stopping at O_symbol.
3527 But there may be more expression left now that we
3528 have parsed the relocation marker. Parse it again.
3529 XXX Surely there is a cleaner way to do this. */
3530 char *p
= input_line_pointer
;
3532 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3533 memcpy (save_buf
, base
, input_line_pointer
- base
);
3534 memmove (base
+ (input_line_pointer
- before_reloc
),
3535 base
, before_reloc
- base
);
3537 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3539 memcpy (base
, save_buf
, p
- base
);
3541 offset
= nbytes
- size
;
3542 p
= frag_more (nbytes
);
3543 memset (p
, 0, nbytes
);
3544 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3545 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3550 while (*input_line_pointer
++ == ',');
3552 /* Put terminator back into stream. */
3553 input_line_pointer
--;
3554 demand_empty_rest_of_line ();
3557 /* Emit an expression containing a 32-bit thumb instruction.
3558 Implementation based on put_thumb32_insn. */
3561 emit_thumb32_expr (expressionS
* exp
)
3563 expressionS exp_high
= *exp
;
3565 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3566 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3567 exp
->X_add_number
&= 0xffff;
3568 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3571 /* Guess the instruction size based on the opcode. */
3574 thumb_insn_size (int opcode
)
3576 if ((unsigned int) opcode
< 0xe800u
)
3578 else if ((unsigned int) opcode
>= 0xe8000000u
)
3585 emit_insn (expressionS
*exp
, int nbytes
)
3589 if (exp
->X_op
== O_constant
)
3594 size
= thumb_insn_size (exp
->X_add_number
);
3598 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3600 as_bad (_(".inst.n operand too big. "\
3601 "Use .inst.w instead"));
3606 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3607 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3609 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3611 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3612 emit_thumb32_expr (exp
);
3614 emit_expr (exp
, (unsigned int) size
);
3616 it_fsm_post_encode ();
3620 as_bad (_("cannot determine Thumb instruction size. " \
3621 "Use .inst.n/.inst.w instead"));
3624 as_bad (_("constant expression required"));
3629 /* Like s_arm_elf_cons but do not use md_cons_align and
3630 set the mapping state to MAP_ARM/MAP_THUMB. */
3633 s_arm_elf_inst (int nbytes
)
3635 if (is_it_end_of_statement ())
3637 demand_empty_rest_of_line ();
3641 /* Calling mapping_state () here will not change ARM/THUMB,
3642 but will ensure not to be in DATA state. */
3645 mapping_state (MAP_THUMB
);
3650 as_bad (_("width suffixes are invalid in ARM mode"));
3651 ignore_rest_of_line ();
3657 mapping_state (MAP_ARM
);
3666 if (! emit_insn (& exp
, nbytes
))
3668 ignore_rest_of_line ();
3672 while (*input_line_pointer
++ == ',');
3674 /* Put terminator back into stream. */
3675 input_line_pointer
--;
3676 demand_empty_rest_of_line ();
3679 /* Parse a .rel31 directive. */
3682 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3689 if (*input_line_pointer
== '1')
3690 highbit
= 0x80000000;
3691 else if (*input_line_pointer
!= '0')
3692 as_bad (_("expected 0 or 1"));
3694 input_line_pointer
++;
3695 if (*input_line_pointer
!= ',')
3696 as_bad (_("missing comma"));
3697 input_line_pointer
++;
3699 #ifdef md_flush_pending_output
3700 md_flush_pending_output ();
3703 #ifdef md_cons_align
3707 mapping_state (MAP_DATA
);
3712 md_number_to_chars (p
, highbit
, 4);
3713 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3714 BFD_RELOC_ARM_PREL31
);
3716 demand_empty_rest_of_line ();
3719 /* Directives: AEABI stack-unwind tables. */
3721 /* Parse an unwind_fnstart directive. Simply records the current location. */
3724 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3726 demand_empty_rest_of_line ();
3727 if (unwind
.proc_start
)
3729 as_bad (_("duplicate .fnstart directive"));
3733 /* Mark the start of the function. */
3734 unwind
.proc_start
= expr_build_dot ();
3736 /* Reset the rest of the unwind info. */
3737 unwind
.opcode_count
= 0;
3738 unwind
.table_entry
= NULL
;
3739 unwind
.personality_routine
= NULL
;
3740 unwind
.personality_index
= -1;
3741 unwind
.frame_size
= 0;
3742 unwind
.fp_offset
= 0;
3743 unwind
.fp_reg
= REG_SP
;
3745 unwind
.sp_restored
= 0;
3749 /* Parse a handlerdata directive. Creates the exception handling table entry
3750 for the function. */
3753 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3755 demand_empty_rest_of_line ();
3756 if (!unwind
.proc_start
)
3757 as_bad (MISSING_FNSTART
);
3759 if (unwind
.table_entry
)
3760 as_bad (_("duplicate .handlerdata directive"));
3762 create_unwind_entry (1);
3765 /* Parse an unwind_fnend directive. Generates the index table entry. */
3768 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3773 unsigned int marked_pr_dependency
;
3775 demand_empty_rest_of_line ();
3777 if (!unwind
.proc_start
)
3779 as_bad (_(".fnend directive without .fnstart"));
3783 /* Add eh table entry. */
3784 if (unwind
.table_entry
== NULL
)
3785 val
= create_unwind_entry (0);
3789 /* Add index table entry. This is two words. */
3790 start_unwind_section (unwind
.saved_seg
, 1);
3791 frag_align (2, 0, 0);
3792 record_alignment (now_seg
, 2);
3794 ptr
= frag_more (8);
3796 where
= frag_now_fix () - 8;
3798 /* Self relative offset of the function start. */
3799 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3800 BFD_RELOC_ARM_PREL31
);
3802 /* Indicate dependency on EHABI-defined personality routines to the
3803 linker, if it hasn't been done already. */
3804 marked_pr_dependency
3805 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3806 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3807 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3809 static const char *const name
[] =
3811 "__aeabi_unwind_cpp_pr0",
3812 "__aeabi_unwind_cpp_pr1",
3813 "__aeabi_unwind_cpp_pr2"
3815 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3816 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3817 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3818 |= 1 << unwind
.personality_index
;
3822 /* Inline exception table entry. */
3823 md_number_to_chars (ptr
+ 4, val
, 4);
3825 /* Self relative offset of the table entry. */
3826 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3827 BFD_RELOC_ARM_PREL31
);
3829 /* Restore the original section. */
3830 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3832 unwind
.proc_start
= NULL
;
3836 /* Parse an unwind_cantunwind directive. */
3839 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3841 demand_empty_rest_of_line ();
3842 if (!unwind
.proc_start
)
3843 as_bad (MISSING_FNSTART
);
3845 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3846 as_bad (_("personality routine specified for cantunwind frame"));
3848 unwind
.personality_index
= -2;
3852 /* Parse a personalityindex directive. */
3855 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3859 if (!unwind
.proc_start
)
3860 as_bad (MISSING_FNSTART
);
3862 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3863 as_bad (_("duplicate .personalityindex directive"));
3867 if (exp
.X_op
!= O_constant
3868 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3870 as_bad (_("bad personality routine number"));
3871 ignore_rest_of_line ();
3875 unwind
.personality_index
= exp
.X_add_number
;
3877 demand_empty_rest_of_line ();
3881 /* Parse a personality directive. */
3884 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3888 if (!unwind
.proc_start
)
3889 as_bad (MISSING_FNSTART
);
3891 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3892 as_bad (_("duplicate .personality directive"));
3894 c
= get_symbol_name (& name
);
3895 p
= input_line_pointer
;
3897 ++ input_line_pointer
;
3898 unwind
.personality_routine
= symbol_find_or_make (name
);
3900 demand_empty_rest_of_line ();
3904 /* Parse a directive saving core registers. */
3907 s_arm_unwind_save_core (void)
3913 range
= parse_reg_list (&input_line_pointer
);
3916 as_bad (_("expected register list"));
3917 ignore_rest_of_line ();
3921 demand_empty_rest_of_line ();
3923 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3924 into .unwind_save {..., sp...}. We aren't bothered about the value of
3925 ip because it is clobbered by calls. */
3926 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3927 && (range
& 0x3000) == 0x1000)
3929 unwind
.opcode_count
--;
3930 unwind
.sp_restored
= 0;
3931 range
= (range
| 0x2000) & ~0x1000;
3932 unwind
.pending_offset
= 0;
3938 /* See if we can use the short opcodes. These pop a block of up to 8
3939 registers starting with r4, plus maybe r14. */
3940 for (n
= 0; n
< 8; n
++)
3942 /* Break at the first non-saved register. */
3943 if ((range
& (1 << (n
+ 4))) == 0)
3946 /* See if there are any other bits set. */
3947 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3949 /* Use the long form. */
3950 op
= 0x8000 | ((range
>> 4) & 0xfff);
3951 add_unwind_opcode (op
, 2);
3955 /* Use the short form. */
3957 op
= 0xa8; /* Pop r14. */
3959 op
= 0xa0; /* Do not pop r14. */
3961 add_unwind_opcode (op
, 1);
3968 op
= 0xb100 | (range
& 0xf);
3969 add_unwind_opcode (op
, 2);
3972 /* Record the number of bytes pushed. */
3973 for (n
= 0; n
< 16; n
++)
3975 if (range
& (1 << n
))
3976 unwind
.frame_size
+= 4;
3981 /* Parse a directive saving FPA registers. */
3984 s_arm_unwind_save_fpa (int reg
)
3990 /* Get Number of registers to transfer. */
3991 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3994 exp
.X_op
= O_illegal
;
3996 if (exp
.X_op
!= O_constant
)
3998 as_bad (_("expected , <constant>"));
3999 ignore_rest_of_line ();
4003 num_regs
= exp
.X_add_number
;
4005 if (num_regs
< 1 || num_regs
> 4)
4007 as_bad (_("number of registers must be in the range [1:4]"));
4008 ignore_rest_of_line ();
4012 demand_empty_rest_of_line ();
4017 op
= 0xb4 | (num_regs
- 1);
4018 add_unwind_opcode (op
, 1);
4023 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4024 add_unwind_opcode (op
, 2);
4026 unwind
.frame_size
+= num_regs
* 12;
4030 /* Parse a directive saving VFP registers for ARMv6 and above. */
4033 s_arm_unwind_save_vfp_armv6 (void)
4038 int num_vfpv3_regs
= 0;
4039 int num_regs_below_16
;
4041 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4044 as_bad (_("expected register list"));
4045 ignore_rest_of_line ();
4049 demand_empty_rest_of_line ();
4051 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4052 than FSTMX/FLDMX-style ones). */
4054 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4056 num_vfpv3_regs
= count
;
4057 else if (start
+ count
> 16)
4058 num_vfpv3_regs
= start
+ count
- 16;
4060 if (num_vfpv3_regs
> 0)
4062 int start_offset
= start
> 16 ? start
- 16 : 0;
4063 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4064 add_unwind_opcode (op
, 2);
4067 /* Generate opcode for registers numbered in the range 0 .. 15. */
4068 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4069 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4070 if (num_regs_below_16
> 0)
4072 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4073 add_unwind_opcode (op
, 2);
4076 unwind
.frame_size
+= count
* 8;
4080 /* Parse a directive saving VFP registers for pre-ARMv6. */
4083 s_arm_unwind_save_vfp (void)
4089 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4092 as_bad (_("expected register list"));
4093 ignore_rest_of_line ();
4097 demand_empty_rest_of_line ();
4102 op
= 0xb8 | (count
- 1);
4103 add_unwind_opcode (op
, 1);
4108 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4109 add_unwind_opcode (op
, 2);
4111 unwind
.frame_size
+= count
* 8 + 4;
4115 /* Parse a directive saving iWMMXt data registers. */
4118 s_arm_unwind_save_mmxwr (void)
4126 if (*input_line_pointer
== '{')
4127 input_line_pointer
++;
4131 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4135 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4140 as_tsktsk (_("register list not in ascending order"));
4143 if (*input_line_pointer
== '-')
4145 input_line_pointer
++;
4146 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4149 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4152 else if (reg
>= hi_reg
)
4154 as_bad (_("bad register range"));
4157 for (; reg
< hi_reg
; reg
++)
4161 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4163 skip_past_char (&input_line_pointer
, '}');
4165 demand_empty_rest_of_line ();
4167 /* Generate any deferred opcodes because we're going to be looking at
4169 flush_pending_unwind ();
4171 for (i
= 0; i
< 16; i
++)
4173 if (mask
& (1 << i
))
4174 unwind
.frame_size
+= 8;
4177 /* Attempt to combine with a previous opcode. We do this because gcc
4178 likes to output separate unwind directives for a single block of
4180 if (unwind
.opcode_count
> 0)
4182 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4183 if ((i
& 0xf8) == 0xc0)
4186 /* Only merge if the blocks are contiguous. */
4189 if ((mask
& 0xfe00) == (1 << 9))
4191 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4192 unwind
.opcode_count
--;
4195 else if (i
== 6 && unwind
.opcode_count
>= 2)
4197 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4201 op
= 0xffff << (reg
- 1);
4203 && ((mask
& op
) == (1u << (reg
- 1))))
4205 op
= (1 << (reg
+ i
+ 1)) - 1;
4206 op
&= ~((1 << reg
) - 1);
4208 unwind
.opcode_count
-= 2;
4215 /* We want to generate opcodes in the order the registers have been
4216 saved, ie. descending order. */
4217 for (reg
= 15; reg
>= -1; reg
--)
4219 /* Save registers in blocks. */
4221 || !(mask
& (1 << reg
)))
4223 /* We found an unsaved reg. Generate opcodes to save the
4230 op
= 0xc0 | (hi_reg
- 10);
4231 add_unwind_opcode (op
, 1);
4236 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4237 add_unwind_opcode (op
, 2);
4246 ignore_rest_of_line ();
4250 s_arm_unwind_save_mmxwcg (void)
4257 if (*input_line_pointer
== '{')
4258 input_line_pointer
++;
4260 skip_whitespace (input_line_pointer
);
4264 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4268 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4274 as_tsktsk (_("register list not in ascending order"));
4277 if (*input_line_pointer
== '-')
4279 input_line_pointer
++;
4280 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4283 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4286 else if (reg
>= hi_reg
)
4288 as_bad (_("bad register range"));
4291 for (; reg
< hi_reg
; reg
++)
4295 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4297 skip_past_char (&input_line_pointer
, '}');
4299 demand_empty_rest_of_line ();
4301 /* Generate any deferred opcodes because we're going to be looking at
4303 flush_pending_unwind ();
4305 for (reg
= 0; reg
< 16; reg
++)
4307 if (mask
& (1 << reg
))
4308 unwind
.frame_size
+= 4;
4311 add_unwind_opcode (op
, 2);
4314 ignore_rest_of_line ();
4318 /* Parse an unwind_save directive.
4319 If the argument is non-zero, this is a .vsave directive. */
4322 s_arm_unwind_save (int arch_v6
)
4325 struct reg_entry
*reg
;
4326 bfd_boolean had_brace
= FALSE
;
4328 if (!unwind
.proc_start
)
4329 as_bad (MISSING_FNSTART
);
4331 /* Figure out what sort of save we have. */
4332 peek
= input_line_pointer
;
4340 reg
= arm_reg_parse_multi (&peek
);
4344 as_bad (_("register expected"));
4345 ignore_rest_of_line ();
4354 as_bad (_("FPA .unwind_save does not take a register list"));
4355 ignore_rest_of_line ();
4358 input_line_pointer
= peek
;
4359 s_arm_unwind_save_fpa (reg
->number
);
4363 s_arm_unwind_save_core ();
4368 s_arm_unwind_save_vfp_armv6 ();
4370 s_arm_unwind_save_vfp ();
4373 case REG_TYPE_MMXWR
:
4374 s_arm_unwind_save_mmxwr ();
4377 case REG_TYPE_MMXWCG
:
4378 s_arm_unwind_save_mmxwcg ();
4382 as_bad (_(".unwind_save does not support this kind of register"));
4383 ignore_rest_of_line ();
4388 /* Parse an unwind_movsp directive. */
4391 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4397 if (!unwind
.proc_start
)
4398 as_bad (MISSING_FNSTART
);
4400 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4403 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4404 ignore_rest_of_line ();
4408 /* Optional constant. */
4409 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4411 if (immediate_for_directive (&offset
) == FAIL
)
4417 demand_empty_rest_of_line ();
4419 if (reg
== REG_SP
|| reg
== REG_PC
)
4421 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4425 if (unwind
.fp_reg
!= REG_SP
)
4426 as_bad (_("unexpected .unwind_movsp directive"));
4428 /* Generate opcode to restore the value. */
4430 add_unwind_opcode (op
, 1);
4432 /* Record the information for later. */
4433 unwind
.fp_reg
= reg
;
4434 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4435 unwind
.sp_restored
= 1;
4438 /* Parse an unwind_pad directive. */
4441 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4445 if (!unwind
.proc_start
)
4446 as_bad (MISSING_FNSTART
);
4448 if (immediate_for_directive (&offset
) == FAIL
)
4453 as_bad (_("stack increment must be multiple of 4"));
4454 ignore_rest_of_line ();
4458 /* Don't generate any opcodes, just record the details for later. */
4459 unwind
.frame_size
+= offset
;
4460 unwind
.pending_offset
+= offset
;
4462 demand_empty_rest_of_line ();
4465 /* Parse an unwind_setfp directive. */
4468 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4474 if (!unwind
.proc_start
)
4475 as_bad (MISSING_FNSTART
);
4477 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4478 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4481 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4483 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4485 as_bad (_("expected <reg>, <reg>"));
4486 ignore_rest_of_line ();
4490 /* Optional constant. */
4491 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4493 if (immediate_for_directive (&offset
) == FAIL
)
4499 demand_empty_rest_of_line ();
4501 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4503 as_bad (_("register must be either sp or set by a previous"
4504 "unwind_movsp directive"));
4508 /* Don't generate any opcodes, just record the information for later. */
4509 unwind
.fp_reg
= fp_reg
;
4511 if (sp_reg
== REG_SP
)
4512 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4514 unwind
.fp_offset
-= offset
;
4517 /* Parse an unwind_raw directive. */
4520 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4523 /* This is an arbitrary limit. */
4524 unsigned char op
[16];
4527 if (!unwind
.proc_start
)
4528 as_bad (MISSING_FNSTART
);
4531 if (exp
.X_op
== O_constant
4532 && skip_past_comma (&input_line_pointer
) != FAIL
)
4534 unwind
.frame_size
+= exp
.X_add_number
;
4538 exp
.X_op
= O_illegal
;
4540 if (exp
.X_op
!= O_constant
)
4542 as_bad (_("expected <offset>, <opcode>"));
4543 ignore_rest_of_line ();
4549 /* Parse the opcode. */
4554 as_bad (_("unwind opcode too long"));
4555 ignore_rest_of_line ();
4557 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4559 as_bad (_("invalid unwind opcode"));
4560 ignore_rest_of_line ();
4563 op
[count
++] = exp
.X_add_number
;
4565 /* Parse the next byte. */
4566 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4572 /* Add the opcode bytes in reverse order. */
4574 add_unwind_opcode (op
[count
], 1);
4576 demand_empty_rest_of_line ();
4580 /* Parse a .eabi_attribute directive. */
4583 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4585 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4587 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4588 attributes_set_explicitly
[tag
] = 1;
4591 /* Emit a tls fix for the symbol. */
4594 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4598 #ifdef md_flush_pending_output
4599 md_flush_pending_output ();
4602 #ifdef md_cons_align
4606 /* Since we're just labelling the code, there's no need to define a
4609 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4610 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4611 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4612 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4614 #endif /* OBJ_ELF */
4616 static void s_arm_arch (int);
4617 static void s_arm_object_arch (int);
4618 static void s_arm_cpu (int);
4619 static void s_arm_fpu (int);
4620 static void s_arm_arch_extension (int);
4625 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4632 if (exp
.X_op
== O_symbol
)
4633 exp
.X_op
= O_secrel
;
4635 emit_expr (&exp
, 4);
4637 while (*input_line_pointer
++ == ',');
4639 input_line_pointer
--;
4640 demand_empty_rest_of_line ();
4644 /* This table describes all the machine specific pseudo-ops the assembler
4645 has to support. The fields are:
4646 pseudo-op name without dot
4647 function to call to execute this pseudo-op
4648 Integer arg to pass to the function. */
4650 const pseudo_typeS md_pseudo_table
[] =
4652 /* Never called because '.req' does not start a line. */
4653 { "req", s_req
, 0 },
4654 /* Following two are likewise never called. */
4657 { "unreq", s_unreq
, 0 },
4658 { "bss", s_bss
, 0 },
4659 { "align", s_align_ptwo
, 2 },
4660 { "arm", s_arm
, 0 },
4661 { "thumb", s_thumb
, 0 },
4662 { "code", s_code
, 0 },
4663 { "force_thumb", s_force_thumb
, 0 },
4664 { "thumb_func", s_thumb_func
, 0 },
4665 { "thumb_set", s_thumb_set
, 0 },
4666 { "even", s_even
, 0 },
4667 { "ltorg", s_ltorg
, 0 },
4668 { "pool", s_ltorg
, 0 },
4669 { "syntax", s_syntax
, 0 },
4670 { "cpu", s_arm_cpu
, 0 },
4671 { "arch", s_arm_arch
, 0 },
4672 { "object_arch", s_arm_object_arch
, 0 },
4673 { "fpu", s_arm_fpu
, 0 },
4674 { "arch_extension", s_arm_arch_extension
, 0 },
4676 { "word", s_arm_elf_cons
, 4 },
4677 { "long", s_arm_elf_cons
, 4 },
4678 { "inst.n", s_arm_elf_inst
, 2 },
4679 { "inst.w", s_arm_elf_inst
, 4 },
4680 { "inst", s_arm_elf_inst
, 0 },
4681 { "rel31", s_arm_rel31
, 0 },
4682 { "fnstart", s_arm_unwind_fnstart
, 0 },
4683 { "fnend", s_arm_unwind_fnend
, 0 },
4684 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4685 { "personality", s_arm_unwind_personality
, 0 },
4686 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4687 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4688 { "save", s_arm_unwind_save
, 0 },
4689 { "vsave", s_arm_unwind_save
, 1 },
4690 { "movsp", s_arm_unwind_movsp
, 0 },
4691 { "pad", s_arm_unwind_pad
, 0 },
4692 { "setfp", s_arm_unwind_setfp
, 0 },
4693 { "unwind_raw", s_arm_unwind_raw
, 0 },
4694 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4695 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4699 /* These are used for dwarf. */
4703 /* These are used for dwarf2. */
4704 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4705 { "loc", dwarf2_directive_loc
, 0 },
4706 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4708 { "extend", float_cons
, 'x' },
4709 { "ldouble", float_cons
, 'x' },
4710 { "packed", float_cons
, 'p' },
4712 {"secrel32", pe_directive_secrel
, 0},
4715 /* These are for compatibility with CodeComposer Studio. */
4716 {"ref", s_ccs_ref
, 0},
4717 {"def", s_ccs_def
, 0},
4718 {"asmfunc", s_ccs_asmfunc
, 0},
4719 {"endasmfunc", s_ccs_endasmfunc
, 0},
4724 /* Parser functions used exclusively in instruction operands. */
4726 /* Generic immediate-value read function for use in insn parsing.
4727 STR points to the beginning of the immediate (the leading #);
4728 VAL receives the value; if the value is outside [MIN, MAX]
4729 issue an error. PREFIX_OPT is true if the immediate prefix is
4733 parse_immediate (char **str
, int *val
, int min
, int max
,
4734 bfd_boolean prefix_opt
)
4737 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4738 if (exp
.X_op
!= O_constant
)
4740 inst
.error
= _("constant expression required");
4744 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4746 inst
.error
= _("immediate value out of range");
4750 *val
= exp
.X_add_number
;
4754 /* Less-generic immediate-value read function with the possibility of loading a
4755 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4756 instructions. Puts the result directly in inst.operands[i]. */
4759 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4760 bfd_boolean allow_symbol_p
)
4763 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4766 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4768 if (exp_p
->X_op
== O_constant
)
4770 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4771 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4772 O_constant. We have to be careful not to break compilation for
4773 32-bit X_add_number, though. */
4774 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4776 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4777 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4779 inst
.operands
[i
].regisimm
= 1;
4782 else if (exp_p
->X_op
== O_big
4783 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4785 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4787 /* Bignums have their least significant bits in
4788 generic_bignum[0]. Make sure we put 32 bits in imm and
4789 32 bits in reg, in a (hopefully) portable way. */
4790 gas_assert (parts
!= 0);
4792 /* Make sure that the number is not too big.
4793 PR 11972: Bignums can now be sign-extended to the
4794 size of a .octa so check that the out of range bits
4795 are all zero or all one. */
4796 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4798 LITTLENUM_TYPE m
= -1;
4800 if (generic_bignum
[parts
* 2] != 0
4801 && generic_bignum
[parts
* 2] != m
)
4804 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4805 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4809 inst
.operands
[i
].imm
= 0;
4810 for (j
= 0; j
< parts
; j
++, idx
++)
4811 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4812 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4813 inst
.operands
[i
].reg
= 0;
4814 for (j
= 0; j
< parts
; j
++, idx
++)
4815 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4816 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4817 inst
.operands
[i
].regisimm
= 1;
4819 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4827 /* Returns the pseudo-register number of an FPA immediate constant,
4828 or FAIL if there isn't a valid constant here. */
4831 parse_fpa_immediate (char ** str
)
4833 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4839 /* First try and match exact strings, this is to guarantee
4840 that some formats will work even for cross assembly. */
4842 for (i
= 0; fp_const
[i
]; i
++)
4844 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4848 *str
+= strlen (fp_const
[i
]);
4849 if (is_end_of_line
[(unsigned char) **str
])
4855 /* Just because we didn't get a match doesn't mean that the constant
4856 isn't valid, just that it is in a format that we don't
4857 automatically recognize. Try parsing it with the standard
4858 expression routines. */
4860 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4862 /* Look for a raw floating point number. */
4863 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4864 && is_end_of_line
[(unsigned char) *save_in
])
4866 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4868 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4870 if (words
[j
] != fp_values
[i
][j
])
4874 if (j
== MAX_LITTLENUMS
)
4882 /* Try and parse a more complex expression, this will probably fail
4883 unless the code uses a floating point prefix (eg "0f"). */
4884 save_in
= input_line_pointer
;
4885 input_line_pointer
= *str
;
4886 if (expression (&exp
) == absolute_section
4887 && exp
.X_op
== O_big
4888 && exp
.X_add_number
< 0)
4890 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4892 #define X_PRECISION 5
4893 #define E_PRECISION 15L
4894 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4896 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4898 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4900 if (words
[j
] != fp_values
[i
][j
])
4904 if (j
== MAX_LITTLENUMS
)
4906 *str
= input_line_pointer
;
4907 input_line_pointer
= save_in
;
4914 *str
= input_line_pointer
;
4915 input_line_pointer
= save_in
;
4916 inst
.error
= _("invalid FPA immediate expression");
4920 /* Returns 1 if a number has "quarter-precision" float format
4921 0baBbbbbbc defgh000 00000000 00000000. */
4924 is_quarter_float (unsigned imm
)
4926 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4927 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4931 /* Detect the presence of a floating point or integer zero constant,
4935 parse_ifimm_zero (char **in
)
4939 if (!is_immediate_prefix (**in
))
4944 /* Accept #0x0 as a synonym for #0. */
4945 if (strncmp (*in
, "0x", 2) == 0)
4948 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4953 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4954 &generic_floating_point_number
);
4957 && generic_floating_point_number
.sign
== '+'
4958 && (generic_floating_point_number
.low
4959 > generic_floating_point_number
.leader
))
4965 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4966 0baBbbbbbc defgh000 00000000 00000000.
4967 The zero and minus-zero cases need special handling, since they can't be
4968 encoded in the "quarter-precision" float format, but can nonetheless be
4969 loaded as integer constants. */
4972 parse_qfloat_immediate (char **ccp
, int *immed
)
4976 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4977 int found_fpchar
= 0;
4979 skip_past_char (&str
, '#');
4981 /* We must not accidentally parse an integer as a floating-point number. Make
4982 sure that the value we parse is not an integer by checking for special
4983 characters '.' or 'e'.
4984 FIXME: This is a horrible hack, but doing better is tricky because type
4985 information isn't in a very usable state at parse time. */
4987 skip_whitespace (fpnum
);
4989 if (strncmp (fpnum
, "0x", 2) == 0)
4993 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4994 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5004 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5006 unsigned fpword
= 0;
5009 /* Our FP word must be 32 bits (single-precision FP). */
5010 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5012 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5016 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5029 /* Shift operands. */
5032 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5035 struct asm_shift_name
5038 enum shift_kind kind
;
5041 /* Third argument to parse_shift. */
5042 enum parse_shift_mode
5044 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5045 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5046 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5047 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5048 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5051 /* Parse a <shift> specifier on an ARM data processing instruction.
5052 This has three forms:
5054 (LSL|LSR|ASL|ASR|ROR) Rs
5055 (LSL|LSR|ASL|ASR|ROR) #imm
5058 Note that ASL is assimilated to LSL in the instruction encoding, and
5059 RRX to ROR #0 (which cannot be written as such). */
5062 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5064 const struct asm_shift_name
*shift_name
;
5065 enum shift_kind shift
;
5070 for (p
= *str
; ISALPHA (*p
); p
++)
5075 inst
.error
= _("shift expression expected");
5079 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5082 if (shift_name
== NULL
)
5084 inst
.error
= _("shift expression expected");
5088 shift
= shift_name
->kind
;
5092 case NO_SHIFT_RESTRICT
:
5093 case SHIFT_IMMEDIATE
: break;
5095 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5096 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5098 inst
.error
= _("'LSL' or 'ASR' required");
5103 case SHIFT_LSL_IMMEDIATE
:
5104 if (shift
!= SHIFT_LSL
)
5106 inst
.error
= _("'LSL' required");
5111 case SHIFT_ASR_IMMEDIATE
:
5112 if (shift
!= SHIFT_ASR
)
5114 inst
.error
= _("'ASR' required");
5122 if (shift
!= SHIFT_RRX
)
5124 /* Whitespace can appear here if the next thing is a bare digit. */
5125 skip_whitespace (p
);
5127 if (mode
== NO_SHIFT_RESTRICT
5128 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5130 inst
.operands
[i
].imm
= reg
;
5131 inst
.operands
[i
].immisreg
= 1;
5133 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5136 inst
.operands
[i
].shift_kind
= shift
;
5137 inst
.operands
[i
].shifted
= 1;
5142 /* Parse a <shifter_operand> for an ARM data processing instruction:
5145 #<immediate>, <rotate>
5149 where <shift> is defined by parse_shift above, and <rotate> is a
5150 multiple of 2 between 0 and 30. Validation of immediate operands
5151 is deferred to md_apply_fix. */
5154 parse_shifter_operand (char **str
, int i
)
5159 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5161 inst
.operands
[i
].reg
= value
;
5162 inst
.operands
[i
].isreg
= 1;
5164 /* parse_shift will override this if appropriate */
5165 inst
.reloc
.exp
.X_op
= O_constant
;
5166 inst
.reloc
.exp
.X_add_number
= 0;
5168 if (skip_past_comma (str
) == FAIL
)
5171 /* Shift operation on register. */
5172 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5175 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5178 if (skip_past_comma (str
) == SUCCESS
)
5180 /* #x, y -- ie explicit rotation by Y. */
5181 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5184 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5186 inst
.error
= _("constant expression expected");
5190 value
= exp
.X_add_number
;
5191 if (value
< 0 || value
> 30 || value
% 2 != 0)
5193 inst
.error
= _("invalid rotation");
5196 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5198 inst
.error
= _("invalid constant");
5202 /* Encode as specified. */
5203 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5207 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5208 inst
.reloc
.pc_rel
= 0;
5212 /* Group relocation information. Each entry in the table contains the
5213 textual name of the relocation as may appear in assembler source
5214 and must end with a colon.
5215 Along with this textual name are the relocation codes to be used if
5216 the corresponding instruction is an ALU instruction (ADD or SUB only),
5217 an LDR, an LDRS, or an LDC. */
5219 struct group_reloc_table_entry
5230 /* Varieties of non-ALU group relocation. */
5237 static struct group_reloc_table_entry group_reloc_table
[] =
5238 { /* Program counter relative: */
5240 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5245 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5246 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5247 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5248 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5250 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5255 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5256 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5257 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5258 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5260 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5261 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5262 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5263 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5264 /* Section base relative */
5266 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5271 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5272 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5273 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5274 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5276 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5281 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5282 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5283 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5284 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5286 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5287 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5288 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5289 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5290 /* Absolute thumb alu relocations. */
5292 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5297 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5302 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5307 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5312 /* Given the address of a pointer pointing to the textual name of a group
5313 relocation as may appear in assembler source, attempt to find its details
5314 in group_reloc_table. The pointer will be updated to the character after
5315 the trailing colon. On failure, FAIL will be returned; SUCCESS
5316 otherwise. On success, *entry will be updated to point at the relevant
5317 group_reloc_table entry. */
5320 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5323 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5325 int length
= strlen (group_reloc_table
[i
].name
);
5327 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5328 && (*str
)[length
] == ':')
5330 *out
= &group_reloc_table
[i
];
5331 *str
+= (length
+ 1);
5339 /* Parse a <shifter_operand> for an ARM data processing instruction
5340 (as for parse_shifter_operand) where group relocations are allowed:
5343 #<immediate>, <rotate>
5344 #:<group_reloc>:<expression>
5348 where <group_reloc> is one of the strings defined in group_reloc_table.
5349 The hashes are optional.
5351 Everything else is as for parse_shifter_operand. */
5353 static parse_operand_result
5354 parse_shifter_operand_group_reloc (char **str
, int i
)
5356 /* Determine if we have the sequence of characters #: or just :
5357 coming next. If we do, then we check for a group relocation.
5358 If we don't, punt the whole lot to parse_shifter_operand. */
5360 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5361 || (*str
)[0] == ':')
5363 struct group_reloc_table_entry
*entry
;
5365 if ((*str
)[0] == '#')
5370 /* Try to parse a group relocation. Anything else is an error. */
5371 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5373 inst
.error
= _("unknown group relocation");
5374 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5377 /* We now have the group relocation table entry corresponding to
5378 the name in the assembler source. Next, we parse the expression. */
5379 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5380 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5382 /* Record the relocation type (always the ALU variant here). */
5383 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5384 gas_assert (inst
.reloc
.type
!= 0);
5386 return PARSE_OPERAND_SUCCESS
;
5389 return parse_shifter_operand (str
, i
) == SUCCESS
5390 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5392 /* Never reached. */
5395 /* Parse a Neon alignment expression. Information is written to
5396 inst.operands[i]. We assume the initial ':' has been skipped.
5398 align .imm = align << 8, .immisalign=1, .preind=0 */
5399 static parse_operand_result
5400 parse_neon_alignment (char **str
, int i
)
5405 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5407 if (exp
.X_op
!= O_constant
)
5409 inst
.error
= _("alignment must be constant");
5410 return PARSE_OPERAND_FAIL
;
5413 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5414 inst
.operands
[i
].immisalign
= 1;
5415 /* Alignments are not pre-indexes. */
5416 inst
.operands
[i
].preind
= 0;
5419 return PARSE_OPERAND_SUCCESS
;
5422 /* Parse all forms of an ARM address expression. Information is written
5423 to inst.operands[i] and/or inst.reloc.
5425 Preindexed addressing (.preind=1):
5427 [Rn, #offset] .reg=Rn .reloc.exp=offset
5428 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5429 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5430 .shift_kind=shift .reloc.exp=shift_imm
5432 These three may have a trailing ! which causes .writeback to be set also.
5434 Postindexed addressing (.postind=1, .writeback=1):
5436 [Rn], #offset .reg=Rn .reloc.exp=offset
5437 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5438 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5439 .shift_kind=shift .reloc.exp=shift_imm
5441 Unindexed addressing (.preind=0, .postind=0):
5443 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5447 [Rn]{!} shorthand for [Rn,#0]{!}
5448 =immediate .isreg=0 .reloc.exp=immediate
5449 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5451 It is the caller's responsibility to check for addressing modes not
5452 supported by the instruction, and to set inst.reloc.type. */
5454 static parse_operand_result
5455 parse_address_main (char **str
, int i
, int group_relocations
,
5456 group_reloc_type group_type
)
5461 if (skip_past_char (&p
, '[') == FAIL
)
5463 if (skip_past_char (&p
, '=') == FAIL
)
5465 /* Bare address - translate to PC-relative offset. */
5466 inst
.reloc
.pc_rel
= 1;
5467 inst
.operands
[i
].reg
= REG_PC
;
5468 inst
.operands
[i
].isreg
= 1;
5469 inst
.operands
[i
].preind
= 1;
5471 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5472 return PARSE_OPERAND_FAIL
;
5474 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5475 /*allow_symbol_p=*/TRUE
))
5476 return PARSE_OPERAND_FAIL
;
5479 return PARSE_OPERAND_SUCCESS
;
5482 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5483 skip_whitespace (p
);
5485 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5487 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5488 return PARSE_OPERAND_FAIL
;
5490 inst
.operands
[i
].reg
= reg
;
5491 inst
.operands
[i
].isreg
= 1;
5493 if (skip_past_comma (&p
) == SUCCESS
)
5495 inst
.operands
[i
].preind
= 1;
5498 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5500 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5502 inst
.operands
[i
].imm
= reg
;
5503 inst
.operands
[i
].immisreg
= 1;
5505 if (skip_past_comma (&p
) == SUCCESS
)
5506 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5507 return PARSE_OPERAND_FAIL
;
5509 else if (skip_past_char (&p
, ':') == SUCCESS
)
5511 /* FIXME: '@' should be used here, but it's filtered out by generic
5512 code before we get to see it here. This may be subject to
5514 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5516 if (result
!= PARSE_OPERAND_SUCCESS
)
5521 if (inst
.operands
[i
].negative
)
5523 inst
.operands
[i
].negative
= 0;
5527 if (group_relocations
5528 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5530 struct group_reloc_table_entry
*entry
;
5532 /* Skip over the #: or : sequence. */
5538 /* Try to parse a group relocation. Anything else is an
5540 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5542 inst
.error
= _("unknown group relocation");
5543 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5546 /* We now have the group relocation table entry corresponding to
5547 the name in the assembler source. Next, we parse the
5549 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5550 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5552 /* Record the relocation type. */
5556 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5560 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5564 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5571 if (inst
.reloc
.type
== 0)
5573 inst
.error
= _("this group relocation is not allowed on this instruction");
5574 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5580 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5581 return PARSE_OPERAND_FAIL
;
5582 /* If the offset is 0, find out if it's a +0 or -0. */
5583 if (inst
.reloc
.exp
.X_op
== O_constant
5584 && inst
.reloc
.exp
.X_add_number
== 0)
5586 skip_whitespace (q
);
5590 skip_whitespace (q
);
5593 inst
.operands
[i
].negative
= 1;
5598 else if (skip_past_char (&p
, ':') == SUCCESS
)
5600 /* FIXME: '@' should be used here, but it's filtered out by generic code
5601 before we get to see it here. This may be subject to change. */
5602 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5604 if (result
!= PARSE_OPERAND_SUCCESS
)
5608 if (skip_past_char (&p
, ']') == FAIL
)
5610 inst
.error
= _("']' expected");
5611 return PARSE_OPERAND_FAIL
;
5614 if (skip_past_char (&p
, '!') == SUCCESS
)
5615 inst
.operands
[i
].writeback
= 1;
5617 else if (skip_past_comma (&p
) == SUCCESS
)
5619 if (skip_past_char (&p
, '{') == SUCCESS
)
5621 /* [Rn], {expr} - unindexed, with option */
5622 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5623 0, 255, TRUE
) == FAIL
)
5624 return PARSE_OPERAND_FAIL
;
5626 if (skip_past_char (&p
, '}') == FAIL
)
5628 inst
.error
= _("'}' expected at end of 'option' field");
5629 return PARSE_OPERAND_FAIL
;
5631 if (inst
.operands
[i
].preind
)
5633 inst
.error
= _("cannot combine index with option");
5634 return PARSE_OPERAND_FAIL
;
5637 return PARSE_OPERAND_SUCCESS
;
5641 inst
.operands
[i
].postind
= 1;
5642 inst
.operands
[i
].writeback
= 1;
5644 if (inst
.operands
[i
].preind
)
5646 inst
.error
= _("cannot combine pre- and post-indexing");
5647 return PARSE_OPERAND_FAIL
;
5651 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5653 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5655 /* We might be using the immediate for alignment already. If we
5656 are, OR the register number into the low-order bits. */
5657 if (inst
.operands
[i
].immisalign
)
5658 inst
.operands
[i
].imm
|= reg
;
5660 inst
.operands
[i
].imm
= reg
;
5661 inst
.operands
[i
].immisreg
= 1;
5663 if (skip_past_comma (&p
) == SUCCESS
)
5664 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5665 return PARSE_OPERAND_FAIL
;
5670 if (inst
.operands
[i
].negative
)
5672 inst
.operands
[i
].negative
= 0;
5675 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5676 return PARSE_OPERAND_FAIL
;
5677 /* If the offset is 0, find out if it's a +0 or -0. */
5678 if (inst
.reloc
.exp
.X_op
== O_constant
5679 && inst
.reloc
.exp
.X_add_number
== 0)
5681 skip_whitespace (q
);
5685 skip_whitespace (q
);
5688 inst
.operands
[i
].negative
= 1;
5694 /* If at this point neither .preind nor .postind is set, we have a
5695 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5696 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5698 inst
.operands
[i
].preind
= 1;
5699 inst
.reloc
.exp
.X_op
= O_constant
;
5700 inst
.reloc
.exp
.X_add_number
= 0;
5703 return PARSE_OPERAND_SUCCESS
;
5707 parse_address (char **str
, int i
)
5709 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5713 static parse_operand_result
5714 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5716 return parse_address_main (str
, i
, 1, type
);
5719 /* Parse an operand for a MOVW or MOVT instruction. */
5721 parse_half (char **str
)
5726 skip_past_char (&p
, '#');
5727 if (strncasecmp (p
, ":lower16:", 9) == 0)
5728 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5729 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5730 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5732 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5735 skip_whitespace (p
);
5738 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5741 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5743 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5745 inst
.error
= _("constant expression expected");
5748 if (inst
.reloc
.exp
.X_add_number
< 0
5749 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5751 inst
.error
= _("immediate value out of range");
5759 /* Miscellaneous. */
5761 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5762 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5764 parse_psr (char **str
, bfd_boolean lhs
)
5767 unsigned long psr_field
;
5768 const struct asm_psr
*psr
;
5770 bfd_boolean is_apsr
= FALSE
;
5771 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5773 /* PR gas/12698: If the user has specified -march=all then m_profile will
5774 be TRUE, but we want to ignore it in this case as we are building for any
5775 CPU type, including non-m variants. */
5776 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5779 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5780 feature for ease of use and backwards compatibility. */
5782 if (strncasecmp (p
, "SPSR", 4) == 0)
5785 goto unsupported_psr
;
5787 psr_field
= SPSR_BIT
;
5789 else if (strncasecmp (p
, "CPSR", 4) == 0)
5792 goto unsupported_psr
;
5796 else if (strncasecmp (p
, "APSR", 4) == 0)
5798 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5799 and ARMv7-R architecture CPUs. */
5808 while (ISALNUM (*p
) || *p
== '_');
5810 if (strncasecmp (start
, "iapsr", 5) == 0
5811 || strncasecmp (start
, "eapsr", 5) == 0
5812 || strncasecmp (start
, "xpsr", 4) == 0
5813 || strncasecmp (start
, "psr", 3) == 0)
5814 p
= start
+ strcspn (start
, "rR") + 1;
5816 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5822 /* If APSR is being written, a bitfield may be specified. Note that
5823 APSR itself is handled above. */
5824 if (psr
->field
<= 3)
5826 psr_field
= psr
->field
;
5832 /* M-profile MSR instructions have the mask field set to "10", except
5833 *PSR variants which modify APSR, which may use a different mask (and
5834 have been handled already). Do that by setting the PSR_f field
5836 return psr
->field
| (lhs
? PSR_f
: 0);
5839 goto unsupported_psr
;
5845 /* A suffix follows. */
5851 while (ISALNUM (*p
) || *p
== '_');
5855 /* APSR uses a notation for bits, rather than fields. */
5856 unsigned int nzcvq_bits
= 0;
5857 unsigned int g_bit
= 0;
5860 for (bit
= start
; bit
!= p
; bit
++)
5862 switch (TOLOWER (*bit
))
5865 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5869 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5873 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5877 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5881 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5885 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5889 inst
.error
= _("unexpected bit specified after APSR");
5894 if (nzcvq_bits
== 0x1f)
5899 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5901 inst
.error
= _("selected processor does not "
5902 "support DSP extension");
5909 if ((nzcvq_bits
& 0x20) != 0
5910 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5911 || (g_bit
& 0x2) != 0)
5913 inst
.error
= _("bad bitmask specified after APSR");
5919 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5924 psr_field
|= psr
->field
;
5930 goto error
; /* Garbage after "[CS]PSR". */
5932 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5933 is deprecated, but allow it anyway. */
5937 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5940 else if (!m_profile
)
5941 /* These bits are never right for M-profile devices: don't set them
5942 (only code paths which read/write APSR reach here). */
5943 psr_field
|= (PSR_c
| PSR_f
);
5949 inst
.error
= _("selected processor does not support requested special "
5950 "purpose register");
5954 inst
.error
= _("flag for {c}psr instruction expected");
5958 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5959 value suitable for splatting into the AIF field of the instruction. */
5962 parse_cps_flags (char **str
)
5971 case '\0': case ',':
5974 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5975 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5976 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5979 inst
.error
= _("unrecognized CPS flag");
5984 if (saw_a_flag
== 0)
5986 inst
.error
= _("missing CPS flags");
5994 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5995 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5998 parse_endian_specifier (char **str
)
6003 if (strncasecmp (s
, "BE", 2))
6005 else if (strncasecmp (s
, "LE", 2))
6009 inst
.error
= _("valid endian specifiers are be or le");
6013 if (ISALNUM (s
[2]) || s
[2] == '_')
6015 inst
.error
= _("valid endian specifiers are be or le");
6020 return little_endian
;
6023 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6024 value suitable for poking into the rotate field of an sxt or sxta
6025 instruction, or FAIL on error. */
6028 parse_ror (char **str
)
6033 if (strncasecmp (s
, "ROR", 3) == 0)
6037 inst
.error
= _("missing rotation field after comma");
6041 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6046 case 0: *str
= s
; return 0x0;
6047 case 8: *str
= s
; return 0x1;
6048 case 16: *str
= s
; return 0x2;
6049 case 24: *str
= s
; return 0x3;
6052 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6057 /* Parse a conditional code (from conds[] below). The value returned is in the
6058 range 0 .. 14, or FAIL. */
6060 parse_cond (char **str
)
6063 const struct asm_cond
*c
;
6065 /* Condition codes are always 2 characters, so matching up to
6066 3 characters is sufficient. */
6071 while (ISALPHA (*q
) && n
< 3)
6073 cond
[n
] = TOLOWER (*q
);
6078 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6081 inst
.error
= _("condition required");
6089 /* Record a use of the given feature. */
6091 record_feature_use (const arm_feature_set
*feature
)
6094 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6096 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6099 /* If the given feature available in the selected CPU, mark it as used.
6100 Returns TRUE iff feature is available. */
6102 mark_feature_used (const arm_feature_set
*feature
)
6104 /* Ensure the option is valid on the current architecture. */
6105 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6108 /* Add the appropriate architecture feature for the barrier option used.
6110 record_feature_use (feature
);
6115 /* Parse an option for a barrier instruction. Returns the encoding for the
6118 parse_barrier (char **str
)
6121 const struct asm_barrier_opt
*o
;
6124 while (ISALPHA (*q
))
6127 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6132 if (!mark_feature_used (&o
->arch
))
6139 /* Parse the operands of a table branch instruction. Similar to a memory
6142 parse_tb (char **str
)
6147 if (skip_past_char (&p
, '[') == FAIL
)
6149 inst
.error
= _("'[' expected");
6153 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6155 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6158 inst
.operands
[0].reg
= reg
;
6160 if (skip_past_comma (&p
) == FAIL
)
6162 inst
.error
= _("',' expected");
6166 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6168 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6171 inst
.operands
[0].imm
= reg
;
6173 if (skip_past_comma (&p
) == SUCCESS
)
6175 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6177 if (inst
.reloc
.exp
.X_add_number
!= 1)
6179 inst
.error
= _("invalid shift");
6182 inst
.operands
[0].shifted
= 1;
6185 if (skip_past_char (&p
, ']') == FAIL
)
6187 inst
.error
= _("']' expected");
6194 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6195 information on the types the operands can take and how they are encoded.
6196 Up to four operands may be read; this function handles setting the
6197 ".present" field for each read operand itself.
6198 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6199 else returns FAIL. */
6202 parse_neon_mov (char **str
, int *which_operand
)
6204 int i
= *which_operand
, val
;
6205 enum arm_reg_type rtype
;
6207 struct neon_type_el optype
;
6209 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6211 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6212 inst
.operands
[i
].reg
= val
;
6213 inst
.operands
[i
].isscalar
= 1;
6214 inst
.operands
[i
].vectype
= optype
;
6215 inst
.operands
[i
++].present
= 1;
6217 if (skip_past_comma (&ptr
) == FAIL
)
6220 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6223 inst
.operands
[i
].reg
= val
;
6224 inst
.operands
[i
].isreg
= 1;
6225 inst
.operands
[i
].present
= 1;
6227 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6230 /* Cases 0, 1, 2, 3, 5 (D only). */
6231 if (skip_past_comma (&ptr
) == FAIL
)
6234 inst
.operands
[i
].reg
= val
;
6235 inst
.operands
[i
].isreg
= 1;
6236 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6237 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6238 inst
.operands
[i
].isvec
= 1;
6239 inst
.operands
[i
].vectype
= optype
;
6240 inst
.operands
[i
++].present
= 1;
6242 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6244 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6245 Case 13: VMOV <Sd>, <Rm> */
6246 inst
.operands
[i
].reg
= val
;
6247 inst
.operands
[i
].isreg
= 1;
6248 inst
.operands
[i
].present
= 1;
6250 if (rtype
== REG_TYPE_NQ
)
6252 first_error (_("can't use Neon quad register here"));
6255 else if (rtype
!= REG_TYPE_VFS
)
6258 if (skip_past_comma (&ptr
) == FAIL
)
6260 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6262 inst
.operands
[i
].reg
= val
;
6263 inst
.operands
[i
].isreg
= 1;
6264 inst
.operands
[i
].present
= 1;
6267 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6270 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6271 Case 1: VMOV<c><q> <Dd>, <Dm>
6272 Case 8: VMOV.F32 <Sd>, <Sm>
6273 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6275 inst
.operands
[i
].reg
= val
;
6276 inst
.operands
[i
].isreg
= 1;
6277 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6278 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6279 inst
.operands
[i
].isvec
= 1;
6280 inst
.operands
[i
].vectype
= optype
;
6281 inst
.operands
[i
].present
= 1;
6283 if (skip_past_comma (&ptr
) == SUCCESS
)
6288 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6291 inst
.operands
[i
].reg
= val
;
6292 inst
.operands
[i
].isreg
= 1;
6293 inst
.operands
[i
++].present
= 1;
6295 if (skip_past_comma (&ptr
) == FAIL
)
6298 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6301 inst
.operands
[i
].reg
= val
;
6302 inst
.operands
[i
].isreg
= 1;
6303 inst
.operands
[i
].present
= 1;
6306 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6307 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6308 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6309 Case 10: VMOV.F32 <Sd>, #<imm>
6310 Case 11: VMOV.F64 <Dd>, #<imm> */
6311 inst
.operands
[i
].immisfloat
= 1;
6312 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6314 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6315 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6319 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6323 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6328 inst
.operands
[i
++].present
= 1;
6330 if (skip_past_comma (&ptr
) == FAIL
)
6333 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6335 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6336 inst
.operands
[i
].reg
= val
;
6337 inst
.operands
[i
].isscalar
= 1;
6338 inst
.operands
[i
].present
= 1;
6339 inst
.operands
[i
].vectype
= optype
;
6341 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6343 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6344 inst
.operands
[i
].reg
= val
;
6345 inst
.operands
[i
].isreg
= 1;
6346 inst
.operands
[i
++].present
= 1;
6348 if (skip_past_comma (&ptr
) == FAIL
)
6351 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6354 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6358 inst
.operands
[i
].reg
= val
;
6359 inst
.operands
[i
].isreg
= 1;
6360 inst
.operands
[i
].isvec
= 1;
6361 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6362 inst
.operands
[i
].vectype
= optype
;
6363 inst
.operands
[i
].present
= 1;
6365 if (rtype
== REG_TYPE_VFS
)
6369 if (skip_past_comma (&ptr
) == FAIL
)
6371 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6374 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6377 inst
.operands
[i
].reg
= val
;
6378 inst
.operands
[i
].isreg
= 1;
6379 inst
.operands
[i
].isvec
= 1;
6380 inst
.operands
[i
].issingle
= 1;
6381 inst
.operands
[i
].vectype
= optype
;
6382 inst
.operands
[i
].present
= 1;
6385 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6389 inst
.operands
[i
].reg
= val
;
6390 inst
.operands
[i
].isreg
= 1;
6391 inst
.operands
[i
].isvec
= 1;
6392 inst
.operands
[i
].issingle
= 1;
6393 inst
.operands
[i
].vectype
= optype
;
6394 inst
.operands
[i
].present
= 1;
6399 first_error (_("parse error"));
6403 /* Successfully parsed the operands. Update args. */
6409 first_error (_("expected comma"));
6413 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6417 /* Use this macro when the operand constraints are different
6418 for ARM and THUMB (e.g. ldrd). */
6419 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6420 ((arm_operand) | ((thumb_operand) << 16))
6422 /* Matcher codes for parse_operands. */
6423 enum operand_parse_code
6425 OP_stop
, /* end of line */
6427 OP_RR
, /* ARM register */
6428 OP_RRnpc
, /* ARM register, not r15 */
6429 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6430 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6431 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6432 optional trailing ! */
6433 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6434 OP_RCP
, /* Coprocessor number */
6435 OP_RCN
, /* Coprocessor register */
6436 OP_RF
, /* FPA register */
6437 OP_RVS
, /* VFP single precision register */
6438 OP_RVD
, /* VFP double precision register (0..15) */
6439 OP_RND
, /* Neon double precision register (0..31) */
6440 OP_RNQ
, /* Neon quad precision register */
6441 OP_RVSD
, /* VFP single or double precision register */
6442 OP_RNDQ
, /* Neon double or quad precision register */
6443 OP_RNSDQ
, /* Neon single, double or quad precision register */
6444 OP_RNSC
, /* Neon scalar D[X] */
6445 OP_RVC
, /* VFP control register */
6446 OP_RMF
, /* Maverick F register */
6447 OP_RMD
, /* Maverick D register */
6448 OP_RMFX
, /* Maverick FX register */
6449 OP_RMDX
, /* Maverick DX register */
6450 OP_RMAX
, /* Maverick AX register */
6451 OP_RMDS
, /* Maverick DSPSC register */
6452 OP_RIWR
, /* iWMMXt wR register */
6453 OP_RIWC
, /* iWMMXt wC register */
6454 OP_RIWG
, /* iWMMXt wCG register */
6455 OP_RXA
, /* XScale accumulator register */
6457 OP_REGLST
, /* ARM register list */
6458 OP_VRSLST
, /* VFP single-precision register list */
6459 OP_VRDLST
, /* VFP double-precision register list */
6460 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6461 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6462 OP_NSTRLST
, /* Neon element/structure list */
6464 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6465 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6466 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6467 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6468 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6469 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6470 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6471 OP_VMOV
, /* Neon VMOV operands. */
6472 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6473 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6474 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6476 OP_I0
, /* immediate zero */
6477 OP_I7
, /* immediate value 0 .. 7 */
6478 OP_I15
, /* 0 .. 15 */
6479 OP_I16
, /* 1 .. 16 */
6480 OP_I16z
, /* 0 .. 16 */
6481 OP_I31
, /* 0 .. 31 */
6482 OP_I31w
, /* 0 .. 31, optional trailing ! */
6483 OP_I32
, /* 1 .. 32 */
6484 OP_I32z
, /* 0 .. 32 */
6485 OP_I63
, /* 0 .. 63 */
6486 OP_I63s
, /* -64 .. 63 */
6487 OP_I64
, /* 1 .. 64 */
6488 OP_I64z
, /* 0 .. 64 */
6489 OP_I255
, /* 0 .. 255 */
6491 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6492 OP_I7b
, /* 0 .. 7 */
6493 OP_I15b
, /* 0 .. 15 */
6494 OP_I31b
, /* 0 .. 31 */
6496 OP_SH
, /* shifter operand */
6497 OP_SHG
, /* shifter operand with possible group relocation */
6498 OP_ADDR
, /* Memory address expression (any mode) */
6499 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6500 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6501 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6502 OP_EXP
, /* arbitrary expression */
6503 OP_EXPi
, /* same, with optional immediate prefix */
6504 OP_EXPr
, /* same, with optional relocation suffix */
6505 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6507 OP_CPSF
, /* CPS flags */
6508 OP_ENDI
, /* Endianness specifier */
6509 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6510 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6511 OP_COND
, /* conditional code */
6512 OP_TB
, /* Table branch. */
6514 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6516 OP_RRnpc_I0
, /* ARM register or literal 0 */
6517 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6518 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6519 OP_RF_IF
, /* FPA register or immediate */
6520 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6521 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6523 /* Optional operands. */
6524 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6525 OP_oI31b
, /* 0 .. 31 */
6526 OP_oI32b
, /* 1 .. 32 */
6527 OP_oI32z
, /* 0 .. 32 */
6528 OP_oIffffb
, /* 0 .. 65535 */
6529 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6531 OP_oRR
, /* ARM register */
6532 OP_oRRnpc
, /* ARM register, not the PC */
6533 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6534 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6535 OP_oRND
, /* Optional Neon double precision register */
6536 OP_oRNQ
, /* Optional Neon quad precision register */
6537 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6538 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6539 OP_oSHll
, /* LSL immediate */
6540 OP_oSHar
, /* ASR immediate */
6541 OP_oSHllar
, /* LSL or ASR immediate */
6542 OP_oROR
, /* ROR 0/8/16/24 */
6543 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6545 /* Some pre-defined mixed (ARM/THUMB) operands. */
6546 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6547 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6548 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6550 OP_FIRST_OPTIONAL
= OP_oI7b
6553 /* Generic instruction operand parser. This does no encoding and no
6554 semantic validation; it merely squirrels values away in the inst
6555 structure. Returns SUCCESS or FAIL depending on whether the
6556 specified grammar matched. */
6558 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6560 unsigned const int *upat
= pattern
;
6561 char *backtrack_pos
= 0;
6562 const char *backtrack_error
= 0;
6563 int i
, val
= 0, backtrack_index
= 0;
6564 enum arm_reg_type rtype
;
6565 parse_operand_result result
;
6566 unsigned int op_parse_code
;
6568 #define po_char_or_fail(chr) \
6571 if (skip_past_char (&str, chr) == FAIL) \
6576 #define po_reg_or_fail(regtype) \
6579 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6580 & inst.operands[i].vectype); \
6583 first_error (_(reg_expected_msgs[regtype])); \
6586 inst.operands[i].reg = val; \
6587 inst.operands[i].isreg = 1; \
6588 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6589 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6590 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6591 || rtype == REG_TYPE_VFD \
6592 || rtype == REG_TYPE_NQ); \
6596 #define po_reg_or_goto(regtype, label) \
6599 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6600 & inst.operands[i].vectype); \
6604 inst.operands[i].reg = val; \
6605 inst.operands[i].isreg = 1; \
6606 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6607 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6608 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6609 || rtype == REG_TYPE_VFD \
6610 || rtype == REG_TYPE_NQ); \
6614 #define po_imm_or_fail(min, max, popt) \
6617 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6619 inst.operands[i].imm = val; \
6623 #define po_scalar_or_goto(elsz, label) \
6626 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6629 inst.operands[i].reg = val; \
6630 inst.operands[i].isscalar = 1; \
6634 #define po_misc_or_fail(expr) \
6642 #define po_misc_or_fail_no_backtrack(expr) \
6646 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6647 backtrack_pos = 0; \
6648 if (result != PARSE_OPERAND_SUCCESS) \
6653 #define po_barrier_or_imm(str) \
6656 val = parse_barrier (&str); \
6657 if (val == FAIL && ! ISALPHA (*str)) \
6660 /* ISB can only take SY as an option. */ \
6661 || ((inst.instruction & 0xf0) == 0x60 \
6664 inst.error = _("invalid barrier type"); \
6665 backtrack_pos = 0; \
6671 skip_whitespace (str
);
6673 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6675 op_parse_code
= upat
[i
];
6676 if (op_parse_code
>= 1<<16)
6677 op_parse_code
= thumb
? (op_parse_code
>> 16)
6678 : (op_parse_code
& ((1<<16)-1));
6680 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6682 /* Remember where we are in case we need to backtrack. */
6683 gas_assert (!backtrack_pos
);
6684 backtrack_pos
= str
;
6685 backtrack_error
= inst
.error
;
6686 backtrack_index
= i
;
6689 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6690 po_char_or_fail (',');
6692 switch (op_parse_code
)
6700 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6701 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6702 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6703 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6704 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6705 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6707 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6709 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6711 /* Also accept generic coprocessor regs for unknown registers. */
6713 po_reg_or_fail (REG_TYPE_CN
);
6715 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6716 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6717 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6718 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6719 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6720 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6721 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6722 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6723 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6724 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6726 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6728 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6729 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6731 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6733 /* Neon scalar. Using an element size of 8 means that some invalid
6734 scalars are accepted here, so deal with those in later code. */
6735 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6739 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6742 po_imm_or_fail (0, 0, TRUE
);
6747 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6752 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6755 if (parse_ifimm_zero (&str
))
6756 inst
.operands
[i
].imm
= 0;
6760 = _("only floating point zero is allowed as immediate value");
6768 po_scalar_or_goto (8, try_rr
);
6771 po_reg_or_fail (REG_TYPE_RN
);
6777 po_scalar_or_goto (8, try_nsdq
);
6780 po_reg_or_fail (REG_TYPE_NSDQ
);
6786 po_scalar_or_goto (8, try_ndq
);
6789 po_reg_or_fail (REG_TYPE_NDQ
);
6795 po_scalar_or_goto (8, try_vfd
);
6798 po_reg_or_fail (REG_TYPE_VFD
);
6803 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6804 not careful then bad things might happen. */
6805 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6810 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6813 /* There's a possibility of getting a 64-bit immediate here, so
6814 we need special handling. */
6815 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6818 inst
.error
= _("immediate value is out of range");
6826 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6829 po_imm_or_fail (0, 63, TRUE
);
6834 po_char_or_fail ('[');
6835 po_reg_or_fail (REG_TYPE_RN
);
6836 po_char_or_fail (']');
6842 po_reg_or_fail (REG_TYPE_RN
);
6843 if (skip_past_char (&str
, '!') == SUCCESS
)
6844 inst
.operands
[i
].writeback
= 1;
6848 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6849 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6850 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6851 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6852 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6853 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6854 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6855 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6856 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6857 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6858 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6859 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6861 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6863 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6864 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6866 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6867 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6868 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6869 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6871 /* Immediate variants */
6873 po_char_or_fail ('{');
6874 po_imm_or_fail (0, 255, TRUE
);
6875 po_char_or_fail ('}');
6879 /* The expression parser chokes on a trailing !, so we have
6880 to find it first and zap it. */
6883 while (*s
&& *s
!= ',')
6888 inst
.operands
[i
].writeback
= 1;
6890 po_imm_or_fail (0, 31, TRUE
);
6898 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6903 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6908 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6910 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6912 val
= parse_reloc (&str
);
6915 inst
.error
= _("unrecognized relocation suffix");
6918 else if (val
!= BFD_RELOC_UNUSED
)
6920 inst
.operands
[i
].imm
= val
;
6921 inst
.operands
[i
].hasreloc
= 1;
6926 /* Operand for MOVW or MOVT. */
6928 po_misc_or_fail (parse_half (&str
));
6931 /* Register or expression. */
6932 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6933 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6935 /* Register or immediate. */
6936 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6937 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6939 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6941 if (!is_immediate_prefix (*str
))
6944 val
= parse_fpa_immediate (&str
);
6947 /* FPA immediates are encoded as registers 8-15.
6948 parse_fpa_immediate has already applied the offset. */
6949 inst
.operands
[i
].reg
= val
;
6950 inst
.operands
[i
].isreg
= 1;
6953 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6954 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6956 /* Two kinds of register. */
6959 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6961 || (rege
->type
!= REG_TYPE_MMXWR
6962 && rege
->type
!= REG_TYPE_MMXWC
6963 && rege
->type
!= REG_TYPE_MMXWCG
))
6965 inst
.error
= _("iWMMXt data or control register expected");
6968 inst
.operands
[i
].reg
= rege
->number
;
6969 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6975 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6977 || (rege
->type
!= REG_TYPE_MMXWC
6978 && rege
->type
!= REG_TYPE_MMXWCG
))
6980 inst
.error
= _("iWMMXt control register expected");
6983 inst
.operands
[i
].reg
= rege
->number
;
6984 inst
.operands
[i
].isreg
= 1;
6989 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6990 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6991 case OP_oROR
: val
= parse_ror (&str
); break;
6992 case OP_COND
: val
= parse_cond (&str
); break;
6993 case OP_oBARRIER_I15
:
6994 po_barrier_or_imm (str
); break;
6996 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7002 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7003 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7005 inst
.error
= _("Banked registers are not available with this "
7011 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7015 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7018 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7020 if (strncasecmp (str
, "APSR_", 5) == 0)
7027 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7028 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7029 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7030 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7031 default: found
= 16;
7035 inst
.operands
[i
].isvec
= 1;
7036 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7037 inst
.operands
[i
].reg
= REG_PC
;
7044 po_misc_or_fail (parse_tb (&str
));
7047 /* Register lists. */
7049 val
= parse_reg_list (&str
);
7052 inst
.operands
[i
].writeback
= 1;
7058 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7062 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7066 /* Allow Q registers too. */
7067 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7072 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7074 inst
.operands
[i
].issingle
= 1;
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7084 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7085 &inst
.operands
[i
].vectype
);
7088 /* Addressing modes */
7090 po_misc_or_fail (parse_address (&str
, i
));
7094 po_misc_or_fail_no_backtrack (
7095 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7099 po_misc_or_fail_no_backtrack (
7100 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7104 po_misc_or_fail_no_backtrack (
7105 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7109 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7113 po_misc_or_fail_no_backtrack (
7114 parse_shifter_operand_group_reloc (&str
, i
));
7118 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7122 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7126 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7130 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7133 /* Various value-based sanity checks and shared operations. We
7134 do not signal immediate failures for the register constraints;
7135 this allows a syntax error to take precedence. */
7136 switch (op_parse_code
)
7144 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7145 inst
.error
= BAD_PC
;
7150 if (inst
.operands
[i
].isreg
)
7152 if (inst
.operands
[i
].reg
== REG_PC
)
7153 inst
.error
= BAD_PC
;
7154 else if (inst
.operands
[i
].reg
== REG_SP
)
7155 inst
.error
= BAD_SP
;
7160 if (inst
.operands
[i
].isreg
7161 && inst
.operands
[i
].reg
== REG_PC
7162 && (inst
.operands
[i
].writeback
|| thumb
))
7163 inst
.error
= BAD_PC
;
7172 case OP_oBARRIER_I15
:
7181 inst
.operands
[i
].imm
= val
;
7188 /* If we get here, this operand was successfully parsed. */
7189 inst
.operands
[i
].present
= 1;
7193 inst
.error
= BAD_ARGS
;
7198 /* The parse routine should already have set inst.error, but set a
7199 default here just in case. */
7201 inst
.error
= _("syntax error");
7205 /* Do not backtrack over a trailing optional argument that
7206 absorbed some text. We will only fail again, with the
7207 'garbage following instruction' error message, which is
7208 probably less helpful than the current one. */
7209 if (backtrack_index
== i
&& backtrack_pos
!= str
7210 && upat
[i
+1] == OP_stop
)
7213 inst
.error
= _("syntax error");
7217 /* Try again, skipping the optional argument at backtrack_pos. */
7218 str
= backtrack_pos
;
7219 inst
.error
= backtrack_error
;
7220 inst
.operands
[backtrack_index
].present
= 0;
7221 i
= backtrack_index
;
7225 /* Check that we have parsed all the arguments. */
7226 if (*str
!= '\0' && !inst
.error
)
7227 inst
.error
= _("garbage following instruction");
7229 return inst
.error
? FAIL
: SUCCESS
;
7232 #undef po_char_or_fail
7233 #undef po_reg_or_fail
7234 #undef po_reg_or_goto
7235 #undef po_imm_or_fail
7236 #undef po_scalar_or_fail
7237 #undef po_barrier_or_imm
7239 /* Shorthand macro for instruction encoding functions issuing errors. */
7240 #define constraint(expr, err) \
7251 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7252 instructions are unpredictable if these registers are used. This
7253 is the BadReg predicate in ARM's Thumb-2 documentation. */
7254 #define reject_bad_reg(reg) \
7256 if (reg == REG_SP || reg == REG_PC) \
7258 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7263 /* If REG is R13 (the stack pointer), warn that its use is
7265 #define warn_deprecated_sp(reg) \
7267 if (warn_on_deprecated && reg == REG_SP) \
7268 as_tsktsk (_("use of r13 is deprecated")); \
7271 /* Functions for operand encoding. ARM, then Thumb. */
7273 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7275 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7277 The only binary encoding difference is the Coprocessor number. Coprocessor
7278 9 is used for half-precision calculations or conversions. The format of the
7279 instruction is the same as the equivalent Coprocessor 10 instuction that
7280 exists for Single-Precision operation. */
7283 do_scalar_fp16_v82_encode (void)
7285 if (inst
.cond
!= COND_ALWAYS
)
7286 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7287 " the behaviour is UNPREDICTABLE"));
7288 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7291 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7292 mark_feature_used (&arm_ext_fp16
);
7295 /* If VAL can be encoded in the immediate field of an ARM instruction,
7296 return the encoded form. Otherwise, return FAIL. */
7299 encode_arm_immediate (unsigned int val
)
7306 for (i
= 2; i
< 32; i
+= 2)
7307 if ((a
= rotate_left (val
, i
)) <= 0xff)
7308 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7313 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7314 return the encoded form. Otherwise, return FAIL. */
7316 encode_thumb32_immediate (unsigned int val
)
7323 for (i
= 1; i
<= 24; i
++)
7326 if ((val
& ~(0xff << i
)) == 0)
7327 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7331 if (val
== ((a
<< 16) | a
))
7333 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7337 if (val
== ((a
<< 16) | a
))
7338 return 0x200 | (a
>> 8);
7342 /* Encode a VFP SP or DP register number into inst.instruction. */
7345 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7347 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7350 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7353 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7356 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7361 first_error (_("D register out of range for selected VFP version"));
7369 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7373 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7377 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7381 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7385 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7389 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7397 /* Encode a <shift> in an ARM-format instruction. The immediate,
7398 if any, is handled by md_apply_fix. */
7400 encode_arm_shift (int i
)
7402 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7403 inst
.instruction
|= SHIFT_ROR
<< 5;
7406 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7407 if (inst
.operands
[i
].immisreg
)
7409 inst
.instruction
|= SHIFT_BY_REG
;
7410 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7413 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7418 encode_arm_shifter_operand (int i
)
7420 if (inst
.operands
[i
].isreg
)
7422 inst
.instruction
|= inst
.operands
[i
].reg
;
7423 encode_arm_shift (i
);
7427 inst
.instruction
|= INST_IMMEDIATE
;
7428 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7429 inst
.instruction
|= inst
.operands
[i
].imm
;
7433 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7435 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7438 Generate an error if the operand is not a register. */
7439 constraint (!inst
.operands
[i
].isreg
,
7440 _("Instruction does not support =N addresses"));
7442 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7444 if (inst
.operands
[i
].preind
)
7448 inst
.error
= _("instruction does not accept preindexed addressing");
7451 inst
.instruction
|= PRE_INDEX
;
7452 if (inst
.operands
[i
].writeback
)
7453 inst
.instruction
|= WRITE_BACK
;
7456 else if (inst
.operands
[i
].postind
)
7458 gas_assert (inst
.operands
[i
].writeback
);
7460 inst
.instruction
|= WRITE_BACK
;
7462 else /* unindexed - only for coprocessor */
7464 inst
.error
= _("instruction does not accept unindexed addressing");
7468 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7469 && (((inst
.instruction
& 0x000f0000) >> 16)
7470 == ((inst
.instruction
& 0x0000f000) >> 12)))
7471 as_warn ((inst
.instruction
& LOAD_BIT
)
7472 ? _("destination register same as write-back base")
7473 : _("source register same as write-back base"));
7476 /* inst.operands[i] was set up by parse_address. Encode it into an
7477 ARM-format mode 2 load or store instruction. If is_t is true,
7478 reject forms that cannot be used with a T instruction (i.e. not
7481 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7483 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7485 encode_arm_addr_mode_common (i
, is_t
);
7487 if (inst
.operands
[i
].immisreg
)
7489 constraint ((inst
.operands
[i
].imm
== REG_PC
7490 || (is_pc
&& inst
.operands
[i
].writeback
)),
7492 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7493 inst
.instruction
|= inst
.operands
[i
].imm
;
7494 if (!inst
.operands
[i
].negative
)
7495 inst
.instruction
|= INDEX_UP
;
7496 if (inst
.operands
[i
].shifted
)
7498 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7499 inst
.instruction
|= SHIFT_ROR
<< 5;
7502 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7503 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7507 else /* immediate offset in inst.reloc */
7509 if (is_pc
&& !inst
.reloc
.pc_rel
)
7511 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7513 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7514 cannot use PC in addressing.
7515 PC cannot be used in writeback addressing, either. */
7516 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7519 /* Use of PC in str is deprecated for ARMv7. */
7520 if (warn_on_deprecated
7522 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7523 as_tsktsk (_("use of PC in this instruction is deprecated"));
7526 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7528 /* Prefer + for zero encoded value. */
7529 if (!inst
.operands
[i
].negative
)
7530 inst
.instruction
|= INDEX_UP
;
7531 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7536 /* inst.operands[i] was set up by parse_address. Encode it into an
7537 ARM-format mode 3 load or store instruction. Reject forms that
7538 cannot be used with such instructions. If is_t is true, reject
7539 forms that cannot be used with a T instruction (i.e. not
7542 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7544 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7546 inst
.error
= _("instruction does not accept scaled register index");
7550 encode_arm_addr_mode_common (i
, is_t
);
7552 if (inst
.operands
[i
].immisreg
)
7554 constraint ((inst
.operands
[i
].imm
== REG_PC
7555 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7557 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7559 inst
.instruction
|= inst
.operands
[i
].imm
;
7560 if (!inst
.operands
[i
].negative
)
7561 inst
.instruction
|= INDEX_UP
;
7563 else /* immediate offset in inst.reloc */
7565 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7566 && inst
.operands
[i
].writeback
),
7568 inst
.instruction
|= HWOFFSET_IMM
;
7569 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7571 /* Prefer + for zero encoded value. */
7572 if (!inst
.operands
[i
].negative
)
7573 inst
.instruction
|= INDEX_UP
;
7575 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7580 /* Write immediate bits [7:0] to the following locations:
7582 |28/24|23 19|18 16|15 4|3 0|
7583 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7585 This function is used by VMOV/VMVN/VORR/VBIC. */
7588 neon_write_immbits (unsigned immbits
)
7590 inst
.instruction
|= immbits
& 0xf;
7591 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7592 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7595 /* Invert low-order SIZE bits of XHI:XLO. */
7598 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7600 unsigned immlo
= xlo
? *xlo
: 0;
7601 unsigned immhi
= xhi
? *xhi
: 0;
7606 immlo
= (~immlo
) & 0xff;
7610 immlo
= (~immlo
) & 0xffff;
7614 immhi
= (~immhi
) & 0xffffffff;
7618 immlo
= (~immlo
) & 0xffffffff;
7632 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7636 neon_bits_same_in_bytes (unsigned imm
)
7638 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7639 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7640 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7641 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7644 /* For immediate of above form, return 0bABCD. */
7647 neon_squash_bits (unsigned imm
)
7649 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7650 | ((imm
& 0x01000000) >> 21);
7653 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7656 neon_qfloat_bits (unsigned imm
)
7658 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7661 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7662 the instruction. *OP is passed as the initial value of the op field, and
7663 may be set to a different value depending on the constant (i.e.
7664 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7665 MVN). If the immediate looks like a repeated pattern then also
7666 try smaller element sizes. */
7669 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7670 unsigned *immbits
, int *op
, int size
,
7671 enum neon_el_type type
)
7673 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7675 if (type
== NT_float
&& !float_p
)
7678 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7680 if (size
!= 32 || *op
== 1)
7682 *immbits
= neon_qfloat_bits (immlo
);
7688 if (neon_bits_same_in_bytes (immhi
)
7689 && neon_bits_same_in_bytes (immlo
))
7693 *immbits
= (neon_squash_bits (immhi
) << 4)
7694 | neon_squash_bits (immlo
);
7705 if (immlo
== (immlo
& 0x000000ff))
7710 else if (immlo
== (immlo
& 0x0000ff00))
7712 *immbits
= immlo
>> 8;
7715 else if (immlo
== (immlo
& 0x00ff0000))
7717 *immbits
= immlo
>> 16;
7720 else if (immlo
== (immlo
& 0xff000000))
7722 *immbits
= immlo
>> 24;
7725 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7727 *immbits
= (immlo
>> 8) & 0xff;
7730 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7732 *immbits
= (immlo
>> 16) & 0xff;
7736 if ((immlo
& 0xffff) != (immlo
>> 16))
7743 if (immlo
== (immlo
& 0x000000ff))
7748 else if (immlo
== (immlo
& 0x0000ff00))
7750 *immbits
= immlo
>> 8;
7754 if ((immlo
& 0xff) != (immlo
>> 8))
7759 if (immlo
== (immlo
& 0x000000ff))
7761 /* Don't allow MVN with 8-bit immediate. */
7771 #if defined BFD_HOST_64_BIT
7772 /* Returns TRUE if double precision value V may be cast
7773 to single precision without loss of accuracy. */
7776 is_double_a_single (bfd_int64_t v
)
7778 int exp
= (int)((v
>> 52) & 0x7FF);
7779 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7781 return (exp
== 0 || exp
== 0x7FF
7782 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7783 && (mantissa
& 0x1FFFFFFFl
) == 0;
7786 /* Returns a double precision value casted to single precision
7787 (ignoring the least significant bits in exponent and mantissa). */
7790 double_to_single (bfd_int64_t v
)
7792 int sign
= (int) ((v
>> 63) & 1l);
7793 int exp
= (int) ((v
>> 52) & 0x7FF);
7794 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7800 exp
= exp
- 1023 + 127;
7809 /* No denormalized numbers. */
7815 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7817 #endif /* BFD_HOST_64_BIT */
7826 static void do_vfp_nsyn_opcode (const char *);
7828 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7829 Determine whether it can be performed with a move instruction; if
7830 it can, convert inst.instruction to that move instruction and
7831 return TRUE; if it can't, convert inst.instruction to a literal-pool
7832 load and return FALSE. If this is not a valid thing to do in the
7833 current context, set inst.error and return TRUE.
7835 inst.operands[i] describes the destination register. */
7838 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7841 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7842 bfd_boolean arm_p
= (t
== CONST_ARM
);
7845 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7849 if ((inst
.instruction
& tbit
) == 0)
7851 inst
.error
= _("invalid pseudo operation");
7855 if (inst
.reloc
.exp
.X_op
!= O_constant
7856 && inst
.reloc
.exp
.X_op
!= O_symbol
7857 && inst
.reloc
.exp
.X_op
!= O_big
)
7859 inst
.error
= _("constant expression expected");
7863 if (inst
.reloc
.exp
.X_op
== O_constant
7864 || inst
.reloc
.exp
.X_op
== O_big
)
7866 #if defined BFD_HOST_64_BIT
7871 if (inst
.reloc
.exp
.X_op
== O_big
)
7873 LITTLENUM_TYPE w
[X_PRECISION
];
7876 if (inst
.reloc
.exp
.X_add_number
== -1)
7878 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7880 /* FIXME: Should we check words w[2..5] ? */
7885 #if defined BFD_HOST_64_BIT
7887 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7888 << LITTLENUM_NUMBER_OF_BITS
)
7889 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7890 << LITTLENUM_NUMBER_OF_BITS
)
7891 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7892 << LITTLENUM_NUMBER_OF_BITS
)
7893 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7895 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7896 | (l
[0] & LITTLENUM_MASK
);
7900 v
= inst
.reloc
.exp
.X_add_number
;
7902 if (!inst
.operands
[i
].issingle
)
7906 /* This can be encoded only for a low register. */
7907 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7909 /* This can be done with a mov(1) instruction. */
7910 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7911 inst
.instruction
|= v
;
7915 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7916 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7918 /* Check if on thumb2 it can be done with a mov.w, mvn or
7919 movw instruction. */
7920 unsigned int newimm
;
7921 bfd_boolean isNegated
;
7923 newimm
= encode_thumb32_immediate (v
);
7924 if (newimm
!= (unsigned int) FAIL
)
7928 newimm
= encode_thumb32_immediate (~v
);
7929 if (newimm
!= (unsigned int) FAIL
)
7933 /* The number can be loaded with a mov.w or mvn
7935 if (newimm
!= (unsigned int) FAIL
7936 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7938 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7939 | (inst
.operands
[i
].reg
<< 8));
7940 /* Change to MOVN. */
7941 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7942 inst
.instruction
|= (newimm
& 0x800) << 15;
7943 inst
.instruction
|= (newimm
& 0x700) << 4;
7944 inst
.instruction
|= (newimm
& 0x0ff);
7947 /* The number can be loaded with a movw instruction. */
7948 else if ((v
& ~0xFFFF) == 0
7949 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7951 int imm
= v
& 0xFFFF;
7953 inst
.instruction
= 0xf2400000; /* MOVW. */
7954 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7955 inst
.instruction
|= (imm
& 0xf000) << 4;
7956 inst
.instruction
|= (imm
& 0x0800) << 15;
7957 inst
.instruction
|= (imm
& 0x0700) << 4;
7958 inst
.instruction
|= (imm
& 0x00ff);
7965 int value
= encode_arm_immediate (v
);
7969 /* This can be done with a mov instruction. */
7970 inst
.instruction
&= LITERAL_MASK
;
7971 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7972 inst
.instruction
|= value
& 0xfff;
7976 value
= encode_arm_immediate (~ v
);
7979 /* This can be done with a mvn instruction. */
7980 inst
.instruction
&= LITERAL_MASK
;
7981 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7982 inst
.instruction
|= value
& 0xfff;
7986 else if (t
== CONST_VEC
)
7989 unsigned immbits
= 0;
7990 unsigned immlo
= inst
.operands
[1].imm
;
7991 unsigned immhi
= inst
.operands
[1].regisimm
7992 ? inst
.operands
[1].reg
7993 : inst
.reloc
.exp
.X_unsigned
7995 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7996 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7997 &op
, 64, NT_invtype
);
8001 neon_invert_size (&immlo
, &immhi
, 64);
8003 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8004 &op
, 64, NT_invtype
);
8009 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8015 /* Fill other bits in vmov encoding for both thumb and arm. */
8017 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8019 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8020 neon_write_immbits (immbits
);
8028 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8029 if (inst
.operands
[i
].issingle
8030 && is_quarter_float (inst
.operands
[1].imm
)
8031 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8033 inst
.operands
[1].imm
=
8034 neon_qfloat_bits (v
);
8035 do_vfp_nsyn_opcode ("fconsts");
8039 /* If our host does not support a 64-bit type then we cannot perform
8040 the following optimization. This mean that there will be a
8041 discrepancy between the output produced by an assembler built for
8042 a 32-bit-only host and the output produced from a 64-bit host, but
8043 this cannot be helped. */
8044 #if defined BFD_HOST_64_BIT
8045 else if (!inst
.operands
[1].issingle
8046 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8048 if (is_double_a_single (v
)
8049 && is_quarter_float (double_to_single (v
)))
8051 inst
.operands
[1].imm
=
8052 neon_qfloat_bits (double_to_single (v
));
8053 do_vfp_nsyn_opcode ("fconstd");
8061 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8062 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8065 inst
.operands
[1].reg
= REG_PC
;
8066 inst
.operands
[1].isreg
= 1;
8067 inst
.operands
[1].preind
= 1;
8068 inst
.reloc
.pc_rel
= 1;
8069 inst
.reloc
.type
= (thumb_p
8070 ? BFD_RELOC_ARM_THUMB_OFFSET
8072 ? BFD_RELOC_ARM_HWLITERAL
8073 : BFD_RELOC_ARM_LITERAL
));
8077 /* inst.operands[i] was set up by parse_address. Encode it into an
8078 ARM-format instruction. Reject all forms which cannot be encoded
8079 into a coprocessor load/store instruction. If wb_ok is false,
8080 reject use of writeback; if unind_ok is false, reject use of
8081 unindexed addressing. If reloc_override is not 0, use it instead
8082 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8083 (in which case it is preserved). */
8086 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8088 if (!inst
.operands
[i
].isreg
)
8091 if (! inst
.operands
[0].isvec
)
8093 inst
.error
= _("invalid co-processor operand");
8096 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8100 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8102 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8104 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8106 gas_assert (!inst
.operands
[i
].writeback
);
8109 inst
.error
= _("instruction does not support unindexed addressing");
8112 inst
.instruction
|= inst
.operands
[i
].imm
;
8113 inst
.instruction
|= INDEX_UP
;
8117 if (inst
.operands
[i
].preind
)
8118 inst
.instruction
|= PRE_INDEX
;
8120 if (inst
.operands
[i
].writeback
)
8122 if (inst
.operands
[i
].reg
== REG_PC
)
8124 inst
.error
= _("pc may not be used with write-back");
8129 inst
.error
= _("instruction does not support writeback");
8132 inst
.instruction
|= WRITE_BACK
;
8136 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8137 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8138 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8139 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8142 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8144 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8147 /* Prefer + for zero encoded value. */
8148 if (!inst
.operands
[i
].negative
)
8149 inst
.instruction
|= INDEX_UP
;
8154 /* Functions for instruction encoding, sorted by sub-architecture.
8155 First some generics; their names are taken from the conventional
8156 bit positions for register arguments in ARM format instructions. */
8166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8173 inst
.instruction
|= inst
.operands
[1].reg
;
8179 inst
.instruction
|= inst
.operands
[0].reg
;
8180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8194 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8200 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8205 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8207 if (ARM_CPU_IS_ANY (cpu_variant
))
8209 as_tsktsk ("%s", msg
);
8212 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8224 unsigned Rn
= inst
.operands
[2].reg
;
8225 /* Enforce restrictions on SWP instruction. */
8226 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8228 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8229 _("Rn must not overlap other operands"));
8231 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8233 if (!check_obsolete (&arm_ext_v8
,
8234 _("swp{b} use is obsoleted for ARMv8 and later"))
8235 && warn_on_deprecated
8236 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8237 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8241 inst
.instruction
|= inst
.operands
[1].reg
;
8242 inst
.instruction
|= Rn
<< 16;
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8250 inst
.instruction
|= inst
.operands
[2].reg
;
8256 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8257 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8258 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8259 || inst
.reloc
.exp
.X_add_number
!= 0),
8261 inst
.instruction
|= inst
.operands
[0].reg
;
8262 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8263 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8269 inst
.instruction
|= inst
.operands
[0].imm
;
8275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8276 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8279 /* ARM instructions, in alphabetical order by function name (except
8280 that wrapper functions appear immediately after the function they
8283 /* This is a pseudo-op of the form "adr rd, label" to be converted
8284 into a relative address of the form "add rd, pc, #label-.-8". */
8289 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8291 /* Frag hacking will turn this into a sub instruction if the offset turns
8292 out to be negative. */
8293 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8294 inst
.reloc
.pc_rel
= 1;
8295 inst
.reloc
.exp
.X_add_number
-= 8;
8298 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8299 into a relative address of the form:
8300 add rd, pc, #low(label-.-8)"
8301 add rd, rd, #high(label-.-8)" */
8306 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8308 /* Frag hacking will turn this into a sub instruction if the offset turns
8309 out to be negative. */
8310 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8311 inst
.reloc
.pc_rel
= 1;
8312 inst
.size
= INSN_SIZE
* 2;
8313 inst
.reloc
.exp
.X_add_number
-= 8;
8319 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8320 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8322 if (!inst
.operands
[1].present
)
8323 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8325 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8326 encode_arm_shifter_operand (2);
8332 if (inst
.operands
[0].present
)
8333 inst
.instruction
|= inst
.operands
[0].imm
;
8335 inst
.instruction
|= 0xf;
8341 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8342 constraint (msb
> 32, _("bit-field extends past end of register"));
8343 /* The instruction encoding stores the LSB and MSB,
8344 not the LSB and width. */
8345 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8346 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8347 inst
.instruction
|= (msb
- 1) << 16;
8355 /* #0 in second position is alternative syntax for bfc, which is
8356 the same instruction but with REG_PC in the Rm field. */
8357 if (!inst
.operands
[1].isreg
)
8358 inst
.operands
[1].reg
= REG_PC
;
8360 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8361 constraint (msb
> 32, _("bit-field extends past end of register"));
8362 /* The instruction encoding stores the LSB and MSB,
8363 not the LSB and width. */
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8365 inst
.instruction
|= inst
.operands
[1].reg
;
8366 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8367 inst
.instruction
|= (msb
- 1) << 16;
8373 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8374 _("bit-field extends past end of register"));
8375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8376 inst
.instruction
|= inst
.operands
[1].reg
;
8377 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8378 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8381 /* ARM V5 breakpoint instruction (argument parse)
8382 BKPT <16 bit unsigned immediate>
8383 Instruction is not conditional.
8384 The bit pattern given in insns[] has the COND_ALWAYS condition,
8385 and it is an error if the caller tried to override that. */
8390 /* Top 12 of 16 bits to bits 19:8. */
8391 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8393 /* Bottom 4 of 16 bits to bits 3:0. */
8394 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8398 encode_branch (int default_reloc
)
8400 if (inst
.operands
[0].hasreloc
)
8402 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8403 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8404 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8405 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8406 ? BFD_RELOC_ARM_PLT32
8407 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8410 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8411 inst
.reloc
.pc_rel
= 1;
8418 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8419 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8422 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8429 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8431 if (inst
.cond
== COND_ALWAYS
)
8432 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8434 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8438 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8441 /* ARM V5 branch-link-exchange instruction (argument parse)
8442 BLX <target_addr> ie BLX(1)
8443 BLX{<condition>} <Rm> ie BLX(2)
8444 Unfortunately, there are two different opcodes for this mnemonic.
8445 So, the insns[].value is not used, and the code here zaps values
8446 into inst.instruction.
8447 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8452 if (inst
.operands
[0].isreg
)
8454 /* Arg is a register; the opcode provided by insns[] is correct.
8455 It is not illegal to do "blx pc", just useless. */
8456 if (inst
.operands
[0].reg
== REG_PC
)
8457 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8459 inst
.instruction
|= inst
.operands
[0].reg
;
8463 /* Arg is an address; this instruction cannot be executed
8464 conditionally, and the opcode must be adjusted.
8465 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8466 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8467 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8468 inst
.instruction
= 0xfa000000;
8469 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8476 bfd_boolean want_reloc
;
8478 if (inst
.operands
[0].reg
== REG_PC
)
8479 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8481 inst
.instruction
|= inst
.operands
[0].reg
;
8482 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8483 it is for ARMv4t or earlier. */
8484 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8485 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8489 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8494 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8498 /* ARM v5TEJ. Jump to Jazelle code. */
8503 if (inst
.operands
[0].reg
== REG_PC
)
8504 as_tsktsk (_("use of r15 in bxj is not really useful"));
8506 inst
.instruction
|= inst
.operands
[0].reg
;
8509 /* Co-processor data operation:
8510 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8511 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8515 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8516 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8517 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8518 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8519 inst
.instruction
|= inst
.operands
[4].reg
;
8520 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8526 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8527 encode_arm_shifter_operand (1);
8530 /* Transfer between coprocessor and ARM registers.
8531 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8536 No special properties. */
8538 struct deprecated_coproc_regs_s
8545 arm_feature_set deprecated
;
8546 arm_feature_set obsoleted
;
8547 const char *dep_msg
;
8548 const char *obs_msg
;
8551 #define DEPR_ACCESS_V8 \
8552 N_("This coprocessor register access is deprecated in ARMv8")
8554 /* Table of all deprecated coprocessor registers. */
8555 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8557 {15, 0, 7, 10, 5, /* CP15DMB. */
8558 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8559 DEPR_ACCESS_V8
, NULL
},
8560 {15, 0, 7, 10, 4, /* CP15DSB. */
8561 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8562 DEPR_ACCESS_V8
, NULL
},
8563 {15, 0, 7, 5, 4, /* CP15ISB. */
8564 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8565 DEPR_ACCESS_V8
, NULL
},
8566 {14, 6, 1, 0, 0, /* TEEHBR. */
8567 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8568 DEPR_ACCESS_V8
, NULL
},
8569 {14, 6, 0, 0, 0, /* TEECR. */
8570 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8571 DEPR_ACCESS_V8
, NULL
},
8574 #undef DEPR_ACCESS_V8
8576 static const size_t deprecated_coproc_reg_count
=
8577 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8585 Rd
= inst
.operands
[2].reg
;
8588 if (inst
.instruction
== 0xee000010
8589 || inst
.instruction
== 0xfe000010)
8591 reject_bad_reg (Rd
);
8594 constraint (Rd
== REG_SP
, BAD_SP
);
8599 if (inst
.instruction
== 0xe000010)
8600 constraint (Rd
== REG_PC
, BAD_PC
);
8603 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8605 const struct deprecated_coproc_regs_s
*r
=
8606 deprecated_coproc_regs
+ i
;
8608 if (inst
.operands
[0].reg
== r
->cp
8609 && inst
.operands
[1].imm
== r
->opc1
8610 && inst
.operands
[3].reg
== r
->crn
8611 && inst
.operands
[4].reg
== r
->crm
8612 && inst
.operands
[5].imm
== r
->opc2
)
8614 if (! ARM_CPU_IS_ANY (cpu_variant
)
8615 && warn_on_deprecated
8616 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8617 as_tsktsk ("%s", r
->dep_msg
);
8621 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8622 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8623 inst
.instruction
|= Rd
<< 12;
8624 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8625 inst
.instruction
|= inst
.operands
[4].reg
;
8626 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8629 /* Transfer between coprocessor register and pair of ARM registers.
8630 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8635 Two XScale instructions are special cases of these:
8637 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8638 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8640 Result unpredictable if Rd or Rn is R15. */
8647 Rd
= inst
.operands
[2].reg
;
8648 Rn
= inst
.operands
[3].reg
;
8652 reject_bad_reg (Rd
);
8653 reject_bad_reg (Rn
);
8657 constraint (Rd
== REG_PC
, BAD_PC
);
8658 constraint (Rn
== REG_PC
, BAD_PC
);
8661 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8662 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8663 inst
.instruction
|= Rd
<< 12;
8664 inst
.instruction
|= Rn
<< 16;
8665 inst
.instruction
|= inst
.operands
[4].reg
;
8671 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8672 if (inst
.operands
[1].present
)
8674 inst
.instruction
|= CPSI_MMOD
;
8675 inst
.instruction
|= inst
.operands
[1].imm
;
8682 inst
.instruction
|= inst
.operands
[0].imm
;
8688 unsigned Rd
, Rn
, Rm
;
8690 Rd
= inst
.operands
[0].reg
;
8691 Rn
= (inst
.operands
[1].present
8692 ? inst
.operands
[1].reg
: Rd
);
8693 Rm
= inst
.operands
[2].reg
;
8695 constraint ((Rd
== REG_PC
), BAD_PC
);
8696 constraint ((Rn
== REG_PC
), BAD_PC
);
8697 constraint ((Rm
== REG_PC
), BAD_PC
);
8699 inst
.instruction
|= Rd
<< 16;
8700 inst
.instruction
|= Rn
<< 0;
8701 inst
.instruction
|= Rm
<< 8;
8707 /* There is no IT instruction in ARM mode. We
8708 process it to do the validation as if in
8709 thumb mode, just in case the code gets
8710 assembled for thumb using the unified syntax. */
8715 set_it_insn_type (IT_INSN
);
8716 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8717 now_it
.cc
= inst
.operands
[0].imm
;
8721 /* If there is only one register in the register list,
8722 then return its register number. Otherwise return -1. */
8724 only_one_reg_in_list (int range
)
8726 int i
= ffs (range
) - 1;
8727 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8731 encode_ldmstm(int from_push_pop_mnem
)
8733 int base_reg
= inst
.operands
[0].reg
;
8734 int range
= inst
.operands
[1].imm
;
8737 inst
.instruction
|= base_reg
<< 16;
8738 inst
.instruction
|= range
;
8740 if (inst
.operands
[1].writeback
)
8741 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8743 if (inst
.operands
[0].writeback
)
8745 inst
.instruction
|= WRITE_BACK
;
8746 /* Check for unpredictable uses of writeback. */
8747 if (inst
.instruction
& LOAD_BIT
)
8749 /* Not allowed in LDM type 2. */
8750 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8751 && ((range
& (1 << REG_PC
)) == 0))
8752 as_warn (_("writeback of base register is UNPREDICTABLE"));
8753 /* Only allowed if base reg not in list for other types. */
8754 else if (range
& (1 << base_reg
))
8755 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8759 /* Not allowed for type 2. */
8760 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8761 as_warn (_("writeback of base register is UNPREDICTABLE"));
8762 /* Only allowed if base reg not in list, or first in list. */
8763 else if ((range
& (1 << base_reg
))
8764 && (range
& ((1 << base_reg
) - 1)))
8765 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8769 /* If PUSH/POP has only one register, then use the A2 encoding. */
8770 one_reg
= only_one_reg_in_list (range
);
8771 if (from_push_pop_mnem
&& one_reg
>= 0)
8773 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8775 inst
.instruction
&= A_COND_MASK
;
8776 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8777 inst
.instruction
|= one_reg
<< 12;
8784 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8787 /* ARMv5TE load-consecutive (argument parse)
8796 constraint (inst
.operands
[0].reg
% 2 != 0,
8797 _("first transfer register must be even"));
8798 constraint (inst
.operands
[1].present
8799 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8800 _("can only transfer two consecutive registers"));
8801 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8802 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8804 if (!inst
.operands
[1].present
)
8805 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8807 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8808 register and the first register written; we have to diagnose
8809 overlap between the base and the second register written here. */
8811 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8812 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8813 as_warn (_("base register written back, and overlaps "
8814 "second transfer register"));
8816 if (!(inst
.instruction
& V4_STR_BIT
))
8818 /* For an index-register load, the index register must not overlap the
8819 destination (even if not write-back). */
8820 if (inst
.operands
[2].immisreg
8821 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8822 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8823 as_warn (_("index register overlaps transfer register"));
8825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8826 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8832 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8833 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8834 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8835 || inst
.operands
[1].negative
8836 /* This can arise if the programmer has written
8838 or if they have mistakenly used a register name as the last
8841 It is very difficult to distinguish between these two cases
8842 because "rX" might actually be a label. ie the register
8843 name has been occluded by a symbol of the same name. So we
8844 just generate a general 'bad addressing mode' type error
8845 message and leave it up to the programmer to discover the
8846 true cause and fix their mistake. */
8847 || (inst
.operands
[1].reg
== REG_PC
),
8850 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8851 || inst
.reloc
.exp
.X_add_number
!= 0,
8852 _("offset must be zero in ARM encoding"));
8854 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8857 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8858 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8864 constraint (inst
.operands
[0].reg
% 2 != 0,
8865 _("even register required"));
8866 constraint (inst
.operands
[1].present
8867 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8868 _("can only load two consecutive registers"));
8869 /* If op 1 were present and equal to PC, this function wouldn't
8870 have been called in the first place. */
8871 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8874 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8877 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8878 which is not a multiple of four is UNPREDICTABLE. */
8880 check_ldr_r15_aligned (void)
8882 constraint (!(inst
.operands
[1].immisreg
)
8883 && (inst
.operands
[0].reg
== REG_PC
8884 && inst
.operands
[1].reg
== REG_PC
8885 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8886 _("ldr to register 15 must be 4-byte alligned"));
8892 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8893 if (!inst
.operands
[1].isreg
)
8894 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8896 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8897 check_ldr_r15_aligned ();
8903 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8905 if (inst
.operands
[1].preind
)
8907 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8908 || inst
.reloc
.exp
.X_add_number
!= 0,
8909 _("this instruction requires a post-indexed address"));
8911 inst
.operands
[1].preind
= 0;
8912 inst
.operands
[1].postind
= 1;
8913 inst
.operands
[1].writeback
= 1;
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8916 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8919 /* Halfword and signed-byte load/store operations. */
8924 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8926 if (!inst
.operands
[1].isreg
)
8927 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8929 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8935 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8937 if (inst
.operands
[1].preind
)
8939 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8940 || inst
.reloc
.exp
.X_add_number
!= 0,
8941 _("this instruction requires a post-indexed address"));
8943 inst
.operands
[1].preind
= 0;
8944 inst
.operands
[1].postind
= 1;
8945 inst
.operands
[1].writeback
= 1;
8947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8948 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8951 /* Co-processor register load/store.
8952 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8956 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8957 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8958 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8964 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8965 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8966 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8967 && !(inst
.instruction
& 0x00400000))
8968 as_tsktsk (_("Rd and Rm should be different in mla"));
8970 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8971 inst
.instruction
|= inst
.operands
[1].reg
;
8972 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8973 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8979 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8980 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8983 encode_arm_shifter_operand (1);
8986 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8993 top
= (inst
.instruction
& 0x00400000) != 0;
8994 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8995 _(":lower16: not allowed this instruction"));
8996 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8997 _(":upper16: not allowed instruction"));
8998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8999 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9001 imm
= inst
.reloc
.exp
.X_add_number
;
9002 /* The value is in two pieces: 0:11, 16:19. */
9003 inst
.instruction
|= (imm
& 0x00000fff);
9004 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9009 do_vfp_nsyn_mrs (void)
9011 if (inst
.operands
[0].isvec
)
9013 if (inst
.operands
[1].reg
!= 1)
9014 first_error (_("operand 1 must be FPSCR"));
9015 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9016 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9017 do_vfp_nsyn_opcode ("fmstat");
9019 else if (inst
.operands
[1].isvec
)
9020 do_vfp_nsyn_opcode ("fmrx");
9028 do_vfp_nsyn_msr (void)
9030 if (inst
.operands
[0].isvec
)
9031 do_vfp_nsyn_opcode ("fmxr");
9041 unsigned Rt
= inst
.operands
[0].reg
;
9043 if (thumb_mode
&& Rt
== REG_SP
)
9045 inst
.error
= BAD_SP
;
9049 /* APSR_ sets isvec. All other refs to PC are illegal. */
9050 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9052 inst
.error
= BAD_PC
;
9056 /* If we get through parsing the register name, we just insert the number
9057 generated into the instruction without further validation. */
9058 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9059 inst
.instruction
|= (Rt
<< 12);
9065 unsigned Rt
= inst
.operands
[1].reg
;
9068 reject_bad_reg (Rt
);
9069 else if (Rt
== REG_PC
)
9071 inst
.error
= BAD_PC
;
9075 /* If we get through parsing the register name, we just insert the number
9076 generated into the instruction without further validation. */
9077 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9078 inst
.instruction
|= (Rt
<< 12);
9086 if (do_vfp_nsyn_mrs () == SUCCESS
)
9089 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9092 if (inst
.operands
[1].isreg
)
9094 br
= inst
.operands
[1].reg
;
9095 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9096 as_bad (_("bad register for mrs"));
9100 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9101 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9103 _("'APSR', 'CPSR' or 'SPSR' expected"));
9104 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9107 inst
.instruction
|= br
;
9110 /* Two possible forms:
9111 "{C|S}PSR_<field>, Rm",
9112 "{C|S}PSR_f, #expression". */
9117 if (do_vfp_nsyn_msr () == SUCCESS
)
9120 inst
.instruction
|= inst
.operands
[0].imm
;
9121 if (inst
.operands
[1].isreg
)
9122 inst
.instruction
|= inst
.operands
[1].reg
;
9125 inst
.instruction
|= INST_IMMEDIATE
;
9126 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9127 inst
.reloc
.pc_rel
= 0;
9134 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9136 if (!inst
.operands
[2].present
)
9137 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9138 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9139 inst
.instruction
|= inst
.operands
[1].reg
;
9140 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9142 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9143 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9144 as_tsktsk (_("Rd and Rm should be different in mul"));
9147 /* Long Multiply Parser
9148 UMULL RdLo, RdHi, Rm, Rs
9149 SMULL RdLo, RdHi, Rm, Rs
9150 UMLAL RdLo, RdHi, Rm, Rs
9151 SMLAL RdLo, RdHi, Rm, Rs. */
9156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9157 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9158 inst
.instruction
|= inst
.operands
[2].reg
;
9159 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9161 /* rdhi and rdlo must be different. */
9162 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9163 as_tsktsk (_("rdhi and rdlo must be different"));
9165 /* rdhi, rdlo and rm must all be different before armv6. */
9166 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9167 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9168 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9169 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9175 if (inst
.operands
[0].present
9176 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9178 /* Architectural NOP hints are CPSR sets with no bits selected. */
9179 inst
.instruction
&= 0xf0000000;
9180 inst
.instruction
|= 0x0320f000;
9181 if (inst
.operands
[0].present
)
9182 inst
.instruction
|= inst
.operands
[0].imm
;
9186 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9187 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9188 Condition defaults to COND_ALWAYS.
9189 Error if Rd, Rn or Rm are R15. */
9194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9195 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9196 inst
.instruction
|= inst
.operands
[2].reg
;
9197 if (inst
.operands
[3].present
)
9198 encode_arm_shift (3);
9201 /* ARM V6 PKHTB (Argument Parse). */
9206 if (!inst
.operands
[3].present
)
9208 /* If the shift specifier is omitted, turn the instruction
9209 into pkhbt rd, rm, rn. */
9210 inst
.instruction
&= 0xfff00010;
9211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9212 inst
.instruction
|= inst
.operands
[1].reg
;
9213 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9218 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9219 inst
.instruction
|= inst
.operands
[2].reg
;
9220 encode_arm_shift (3);
9224 /* ARMv5TE: Preload-Cache
9225 MP Extensions: Preload for write
9229 Syntactically, like LDR with B=1, W=0, L=1. */
9234 constraint (!inst
.operands
[0].isreg
,
9235 _("'[' expected after PLD mnemonic"));
9236 constraint (inst
.operands
[0].postind
,
9237 _("post-indexed expression used in preload instruction"));
9238 constraint (inst
.operands
[0].writeback
,
9239 _("writeback used in preload instruction"));
9240 constraint (!inst
.operands
[0].preind
,
9241 _("unindexed addressing used in preload instruction"));
9242 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9245 /* ARMv7: PLI <addr_mode> */
9249 constraint (!inst
.operands
[0].isreg
,
9250 _("'[' expected after PLI mnemonic"));
9251 constraint (inst
.operands
[0].postind
,
9252 _("post-indexed expression used in preload instruction"));
9253 constraint (inst
.operands
[0].writeback
,
9254 _("writeback used in preload instruction"));
9255 constraint (!inst
.operands
[0].preind
,
9256 _("unindexed addressing used in preload instruction"));
9257 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9258 inst
.instruction
&= ~PRE_INDEX
;
9264 constraint (inst
.operands
[0].writeback
,
9265 _("push/pop do not support {reglist}^"));
9266 inst
.operands
[1] = inst
.operands
[0];
9267 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9268 inst
.operands
[0].isreg
= 1;
9269 inst
.operands
[0].writeback
= 1;
9270 inst
.operands
[0].reg
= REG_SP
;
9271 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9274 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9275 word at the specified address and the following word
9277 Unconditionally executed.
9278 Error if Rn is R15. */
9283 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9284 if (inst
.operands
[0].writeback
)
9285 inst
.instruction
|= WRITE_BACK
;
9288 /* ARM V6 ssat (argument parse). */
9293 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9294 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9295 inst
.instruction
|= inst
.operands
[2].reg
;
9297 if (inst
.operands
[3].present
)
9298 encode_arm_shift (3);
9301 /* ARM V6 usat (argument parse). */
9306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9307 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9308 inst
.instruction
|= inst
.operands
[2].reg
;
9310 if (inst
.operands
[3].present
)
9311 encode_arm_shift (3);
9314 /* ARM V6 ssat16 (argument parse). */
9319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9320 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9321 inst
.instruction
|= inst
.operands
[2].reg
;
9327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9328 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9329 inst
.instruction
|= inst
.operands
[2].reg
;
9332 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9333 preserving the other bits.
9335 setend <endian_specifier>, where <endian_specifier> is either
9341 if (warn_on_deprecated
9342 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9343 as_tsktsk (_("setend use is deprecated for ARMv8"));
9345 if (inst
.operands
[0].imm
)
9346 inst
.instruction
|= 0x200;
9352 unsigned int Rm
= (inst
.operands
[1].present
9353 ? inst
.operands
[1].reg
9354 : inst
.operands
[0].reg
);
9356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9357 inst
.instruction
|= Rm
;
9358 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9360 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9361 inst
.instruction
|= SHIFT_BY_REG
;
9362 /* PR 12854: Error on extraneous shifts. */
9363 constraint (inst
.operands
[2].shifted
,
9364 _("extraneous shift as part of operand to shift insn"));
9367 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9373 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9374 inst
.reloc
.pc_rel
= 0;
9380 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9381 inst
.reloc
.pc_rel
= 0;
9387 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9388 inst
.reloc
.pc_rel
= 0;
9394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9395 _("selected processor does not support SETPAN instruction"));
9397 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9404 _("selected processor does not support SETPAN instruction"));
9406 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9409 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9410 SMLAxy{cond} Rd,Rm,Rs,Rn
9411 SMLAWy{cond} Rd,Rm,Rs,Rn
9412 Error if any register is R15. */
9417 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9418 inst
.instruction
|= inst
.operands
[1].reg
;
9419 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9420 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9423 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9424 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9425 Error if any register is R15.
9426 Warning if Rdlo == Rdhi. */
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9432 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9433 inst
.instruction
|= inst
.operands
[2].reg
;
9434 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9436 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9437 as_tsktsk (_("rdhi and rdlo must be different"));
9440 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9441 SMULxy{cond} Rd,Rm,Rs
9442 Error if any register is R15. */
9447 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9448 inst
.instruction
|= inst
.operands
[1].reg
;
9449 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9452 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9453 the same for both ARM and Thumb-2. */
9460 if (inst
.operands
[0].present
)
9462 reg
= inst
.operands
[0].reg
;
9463 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9468 inst
.instruction
|= reg
<< 16;
9469 inst
.instruction
|= inst
.operands
[1].imm
;
9470 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9471 inst
.instruction
|= WRITE_BACK
;
9474 /* ARM V6 strex (argument parse). */
9479 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9480 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9481 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9482 || inst
.operands
[2].negative
9483 /* See comment in do_ldrex(). */
9484 || (inst
.operands
[2].reg
== REG_PC
),
9487 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9488 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9490 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9491 || inst
.reloc
.exp
.X_add_number
!= 0,
9492 _("offset must be zero in ARM encoding"));
9494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9495 inst
.instruction
|= inst
.operands
[1].reg
;
9496 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9497 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9503 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9504 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9505 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9506 || inst
.operands
[2].negative
,
9509 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9510 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9518 constraint (inst
.operands
[1].reg
% 2 != 0,
9519 _("even register required"));
9520 constraint (inst
.operands
[2].present
9521 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9522 _("can only store two consecutive registers"));
9523 /* If op 2 were present and equal to PC, this function wouldn't
9524 have been called in the first place. */
9525 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9527 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9528 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9529 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9533 inst
.instruction
|= inst
.operands
[1].reg
;
9534 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9541 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9542 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9550 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9551 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9556 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9557 extends it to 32-bits, and adds the result to a value in another
9558 register. You can specify a rotation by 0, 8, 16, or 24 bits
9559 before extracting the 16-bit value.
9560 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9561 Condition defaults to COND_ALWAYS.
9562 Error if any register uses R15. */
9567 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9568 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9569 inst
.instruction
|= inst
.operands
[2].reg
;
9570 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9575 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9576 Condition defaults to COND_ALWAYS.
9577 Error if any register uses R15. */
9582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9583 inst
.instruction
|= inst
.operands
[1].reg
;
9584 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9587 /* VFP instructions. In a logical order: SP variant first, monad
9588 before dyad, arithmetic then move then load/store. */
9591 do_vfp_sp_monadic (void)
9593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9594 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9598 do_vfp_sp_dyadic (void)
9600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9601 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9602 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9606 do_vfp_sp_compare_z (void)
9608 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9612 do_vfp_dp_sp_cvt (void)
9614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9615 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9619 do_vfp_sp_dp_cvt (void)
9621 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9622 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9626 do_vfp_reg_from_sp (void)
9628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9629 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9633 do_vfp_reg2_from_sp2 (void)
9635 constraint (inst
.operands
[2].imm
!= 2,
9636 _("only two consecutive VFP SP registers allowed here"));
9637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9639 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9643 do_vfp_sp_from_reg (void)
9645 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9646 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9650 do_vfp_sp2_from_reg2 (void)
9652 constraint (inst
.operands
[0].imm
!= 2,
9653 _("only two consecutive VFP SP registers allowed here"));
9654 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9655 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9656 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9660 do_vfp_sp_ldst (void)
9662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9663 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9667 do_vfp_dp_ldst (void)
9669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9670 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9675 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9677 if (inst
.operands
[0].writeback
)
9678 inst
.instruction
|= WRITE_BACK
;
9680 constraint (ldstm_type
!= VFP_LDSTMIA
,
9681 _("this addressing mode requires base-register writeback"));
9682 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9683 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9684 inst
.instruction
|= inst
.operands
[1].imm
;
9688 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9692 if (inst
.operands
[0].writeback
)
9693 inst
.instruction
|= WRITE_BACK
;
9695 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9696 _("this addressing mode requires base-register writeback"));
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9701 count
= inst
.operands
[1].imm
<< 1;
9702 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9705 inst
.instruction
|= count
;
9709 do_vfp_sp_ldstmia (void)
9711 vfp_sp_ldstm (VFP_LDSTMIA
);
9715 do_vfp_sp_ldstmdb (void)
9717 vfp_sp_ldstm (VFP_LDSTMDB
);
9721 do_vfp_dp_ldstmia (void)
9723 vfp_dp_ldstm (VFP_LDSTMIA
);
9727 do_vfp_dp_ldstmdb (void)
9729 vfp_dp_ldstm (VFP_LDSTMDB
);
9733 do_vfp_xp_ldstmia (void)
9735 vfp_dp_ldstm (VFP_LDSTMIAX
);
9739 do_vfp_xp_ldstmdb (void)
9741 vfp_dp_ldstm (VFP_LDSTMDBX
);
9745 do_vfp_dp_rd_rm (void)
9747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9748 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9752 do_vfp_dp_rn_rd (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9759 do_vfp_dp_rd_rn (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9762 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9766 do_vfp_dp_rd_rn_rm (void)
9768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9769 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9770 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9776 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9780 do_vfp_dp_rm_rd_rn (void)
9782 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9783 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9784 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9787 /* VFPv3 instructions. */
9789 do_vfp_sp_const (void)
9791 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9792 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9793 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9797 do_vfp_dp_const (void)
9799 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9800 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9801 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9805 vfp_conv (int srcsize
)
9807 int immbits
= srcsize
- inst
.operands
[1].imm
;
9809 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9811 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9812 i.e. immbits must be in range 0 - 16. */
9813 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9816 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9818 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9819 i.e. immbits must be in range 0 - 31. */
9820 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9824 inst
.instruction
|= (immbits
& 1) << 5;
9825 inst
.instruction
|= (immbits
>> 1);
9829 do_vfp_sp_conv_16 (void)
9831 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9836 do_vfp_dp_conv_16 (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9843 do_vfp_sp_conv_32 (void)
9845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9850 do_vfp_dp_conv_32 (void)
9852 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9856 /* FPA instructions. Also in a logical order. */
9861 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9862 inst
.instruction
|= inst
.operands
[1].reg
;
9866 do_fpa_ldmstm (void)
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9869 switch (inst
.operands
[1].imm
)
9871 case 1: inst
.instruction
|= CP_T_X
; break;
9872 case 2: inst
.instruction
|= CP_T_Y
; break;
9873 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9878 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9880 /* The instruction specified "ea" or "fd", so we can only accept
9881 [Rn]{!}. The instruction does not really support stacking or
9882 unstacking, so we have to emulate these by setting appropriate
9883 bits and offsets. */
9884 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9885 || inst
.reloc
.exp
.X_add_number
!= 0,
9886 _("this instruction does not support indexing"));
9888 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9889 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9891 if (!(inst
.instruction
& INDEX_UP
))
9892 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9894 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9896 inst
.operands
[2].preind
= 0;
9897 inst
.operands
[2].postind
= 1;
9901 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9904 /* iWMMXt instructions: strictly in alphabetical order. */
9907 do_iwmmxt_tandorc (void)
9909 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9913 do_iwmmxt_textrc (void)
9915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9916 inst
.instruction
|= inst
.operands
[1].imm
;
9920 do_iwmmxt_textrm (void)
9922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9924 inst
.instruction
|= inst
.operands
[2].imm
;
9928 do_iwmmxt_tinsr (void)
9930 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9931 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9932 inst
.instruction
|= inst
.operands
[2].imm
;
9936 do_iwmmxt_tmia (void)
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9939 inst
.instruction
|= inst
.operands
[1].reg
;
9940 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9944 do_iwmmxt_waligni (void)
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9947 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9948 inst
.instruction
|= inst
.operands
[2].reg
;
9949 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9953 do_iwmmxt_wmerge (void)
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].reg
;
9958 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9962 do_iwmmxt_wmov (void)
9964 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9966 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9967 inst
.instruction
|= inst
.operands
[1].reg
;
9971 do_iwmmxt_wldstbh (void)
9974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9976 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9978 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9979 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9983 do_iwmmxt_wldstw (void)
9985 /* RIWR_RIWC clears .isreg for a control register. */
9986 if (!inst
.operands
[0].isreg
)
9988 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9989 inst
.instruction
|= 0xf0000000;
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9993 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9997 do_iwmmxt_wldstd (void)
9999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10000 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10001 && inst
.operands
[1].immisreg
)
10003 inst
.instruction
&= ~0x1a000ff;
10004 inst
.instruction
|= (0xfU
<< 28);
10005 if (inst
.operands
[1].preind
)
10006 inst
.instruction
|= PRE_INDEX
;
10007 if (!inst
.operands
[1].negative
)
10008 inst
.instruction
|= INDEX_UP
;
10009 if (inst
.operands
[1].writeback
)
10010 inst
.instruction
|= WRITE_BACK
;
10011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10012 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10013 inst
.instruction
|= inst
.operands
[1].imm
;
10016 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10020 do_iwmmxt_wshufh (void)
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10023 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10024 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10025 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10029 do_iwmmxt_wzero (void)
10031 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10032 inst
.instruction
|= inst
.operands
[0].reg
;
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10034 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10038 do_iwmmxt_wrwrwr_or_imm5 (void)
10040 if (inst
.operands
[2].isreg
)
10043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10044 _("immediate operand requires iWMMXt2"));
10046 if (inst
.operands
[2].imm
== 0)
10048 switch ((inst
.instruction
>> 20) & 0xf)
10054 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10055 inst
.operands
[2].imm
= 16;
10056 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10062 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10063 inst
.operands
[2].imm
= 32;
10064 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10071 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10073 wrn
= (inst
.instruction
>> 16) & 0xf;
10074 inst
.instruction
&= 0xff0fff0f;
10075 inst
.instruction
|= wrn
;
10076 /* Bail out here; the instruction is now assembled. */
10081 /* Map 32 -> 0, etc. */
10082 inst
.operands
[2].imm
&= 0x1f;
10083 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10087 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10088 operations first, then control, shift, and load/store. */
10090 /* Insns like "foo X,Y,Z". */
10093 do_mav_triple (void)
10095 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10096 inst
.instruction
|= inst
.operands
[1].reg
;
10097 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10100 /* Insns like "foo W,X,Y,Z".
10101 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10107 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10108 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10109 inst
.instruction
|= inst
.operands
[3].reg
;
10112 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10114 do_mav_dspsc (void)
10116 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10119 /* Maverick shift immediate instructions.
10120 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10121 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10124 do_mav_shift (void)
10126 int imm
= inst
.operands
[2].imm
;
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10131 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10132 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10133 Bit 4 should be 0. */
10134 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10136 inst
.instruction
|= imm
;
10139 /* XScale instructions. Also sorted arithmetic before move. */
10141 /* Xscale multiply-accumulate (argument parse)
10144 MIAxycc acc0,Rm,Rs. */
10149 inst
.instruction
|= inst
.operands
[1].reg
;
10150 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10153 /* Xscale move-accumulator-register (argument parse)
10155 MARcc acc0,RdLo,RdHi. */
10160 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10161 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10164 /* Xscale move-register-accumulator (argument parse)
10166 MRAcc RdLo,RdHi,acc0. */
10171 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10176 /* Encoding functions relevant only to Thumb. */
10178 /* inst.operands[i] is a shifted-register operand; encode
10179 it into inst.instruction in the format used by Thumb32. */
10182 encode_thumb32_shifted_operand (int i
)
10184 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10185 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10187 constraint (inst
.operands
[i
].immisreg
,
10188 _("shift by register not allowed in thumb mode"));
10189 inst
.instruction
|= inst
.operands
[i
].reg
;
10190 if (shift
== SHIFT_RRX
)
10191 inst
.instruction
|= SHIFT_ROR
<< 4;
10194 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10195 _("expression too complex"));
10197 constraint (value
> 32
10198 || (value
== 32 && (shift
== SHIFT_LSL
10199 || shift
== SHIFT_ROR
)),
10200 _("shift expression is too large"));
10204 else if (value
== 32)
10207 inst
.instruction
|= shift
<< 4;
10208 inst
.instruction
|= (value
& 0x1c) << 10;
10209 inst
.instruction
|= (value
& 0x03) << 6;
10214 /* inst.operands[i] was set up by parse_address. Encode it into a
10215 Thumb32 format load or store instruction. Reject forms that cannot
10216 be used with such instructions. If is_t is true, reject forms that
10217 cannot be used with a T instruction; if is_d is true, reject forms
10218 that cannot be used with a D instruction. If it is a store insn,
10219 reject PC in Rn. */
10222 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10224 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10226 constraint (!inst
.operands
[i
].isreg
,
10227 _("Instruction does not support =N addresses"));
10229 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10230 if (inst
.operands
[i
].immisreg
)
10232 constraint (is_pc
, BAD_PC_ADDRESSING
);
10233 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10234 constraint (inst
.operands
[i
].negative
,
10235 _("Thumb does not support negative register indexing"));
10236 constraint (inst
.operands
[i
].postind
,
10237 _("Thumb does not support register post-indexing"));
10238 constraint (inst
.operands
[i
].writeback
,
10239 _("Thumb does not support register indexing with writeback"));
10240 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10241 _("Thumb supports only LSL in shifted register indexing"));
10243 inst
.instruction
|= inst
.operands
[i
].imm
;
10244 if (inst
.operands
[i
].shifted
)
10246 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10247 _("expression too complex"));
10248 constraint (inst
.reloc
.exp
.X_add_number
< 0
10249 || inst
.reloc
.exp
.X_add_number
> 3,
10250 _("shift out of range"));
10251 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10253 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10255 else if (inst
.operands
[i
].preind
)
10257 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10258 constraint (is_t
&& inst
.operands
[i
].writeback
,
10259 _("cannot use writeback with this instruction"));
10260 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10261 BAD_PC_ADDRESSING
);
10265 inst
.instruction
|= 0x01000000;
10266 if (inst
.operands
[i
].writeback
)
10267 inst
.instruction
|= 0x00200000;
10271 inst
.instruction
|= 0x00000c00;
10272 if (inst
.operands
[i
].writeback
)
10273 inst
.instruction
|= 0x00000100;
10275 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10277 else if (inst
.operands
[i
].postind
)
10279 gas_assert (inst
.operands
[i
].writeback
);
10280 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10281 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10284 inst
.instruction
|= 0x00200000;
10286 inst
.instruction
|= 0x00000900;
10287 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10289 else /* unindexed - only for coprocessor */
10290 inst
.error
= _("instruction does not accept unindexed addressing");
10293 /* Table of Thumb instructions which exist in both 16- and 32-bit
10294 encodings (the latter only in post-V6T2 cores). The index is the
10295 value used in the insns table below. When there is more than one
10296 possible 16-bit encoding for the instruction, this table always
10298 Also contains several pseudo-instructions used during relaxation. */
10299 #define T16_32_TAB \
10300 X(_adc, 4140, eb400000), \
10301 X(_adcs, 4140, eb500000), \
10302 X(_add, 1c00, eb000000), \
10303 X(_adds, 1c00, eb100000), \
10304 X(_addi, 0000, f1000000), \
10305 X(_addis, 0000, f1100000), \
10306 X(_add_pc,000f, f20f0000), \
10307 X(_add_sp,000d, f10d0000), \
10308 X(_adr, 000f, f20f0000), \
10309 X(_and, 4000, ea000000), \
10310 X(_ands, 4000, ea100000), \
10311 X(_asr, 1000, fa40f000), \
10312 X(_asrs, 1000, fa50f000), \
10313 X(_b, e000, f000b000), \
10314 X(_bcond, d000, f0008000), \
10315 X(_bic, 4380, ea200000), \
10316 X(_bics, 4380, ea300000), \
10317 X(_cmn, 42c0, eb100f00), \
10318 X(_cmp, 2800, ebb00f00), \
10319 X(_cpsie, b660, f3af8400), \
10320 X(_cpsid, b670, f3af8600), \
10321 X(_cpy, 4600, ea4f0000), \
10322 X(_dec_sp,80dd, f1ad0d00), \
10323 X(_eor, 4040, ea800000), \
10324 X(_eors, 4040, ea900000), \
10325 X(_inc_sp,00dd, f10d0d00), \
10326 X(_ldmia, c800, e8900000), \
10327 X(_ldr, 6800, f8500000), \
10328 X(_ldrb, 7800, f8100000), \
10329 X(_ldrh, 8800, f8300000), \
10330 X(_ldrsb, 5600, f9100000), \
10331 X(_ldrsh, 5e00, f9300000), \
10332 X(_ldr_pc,4800, f85f0000), \
10333 X(_ldr_pc2,4800, f85f0000), \
10334 X(_ldr_sp,9800, f85d0000), \
10335 X(_lsl, 0000, fa00f000), \
10336 X(_lsls, 0000, fa10f000), \
10337 X(_lsr, 0800, fa20f000), \
10338 X(_lsrs, 0800, fa30f000), \
10339 X(_mov, 2000, ea4f0000), \
10340 X(_movs, 2000, ea5f0000), \
10341 X(_mul, 4340, fb00f000), \
10342 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10343 X(_mvn, 43c0, ea6f0000), \
10344 X(_mvns, 43c0, ea7f0000), \
10345 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10346 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10347 X(_orr, 4300, ea400000), \
10348 X(_orrs, 4300, ea500000), \
10349 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10350 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10351 X(_rev, ba00, fa90f080), \
10352 X(_rev16, ba40, fa90f090), \
10353 X(_revsh, bac0, fa90f0b0), \
10354 X(_ror, 41c0, fa60f000), \
10355 X(_rors, 41c0, fa70f000), \
10356 X(_sbc, 4180, eb600000), \
10357 X(_sbcs, 4180, eb700000), \
10358 X(_stmia, c000, e8800000), \
10359 X(_str, 6000, f8400000), \
10360 X(_strb, 7000, f8000000), \
10361 X(_strh, 8000, f8200000), \
10362 X(_str_sp,9000, f84d0000), \
10363 X(_sub, 1e00, eba00000), \
10364 X(_subs, 1e00, ebb00000), \
10365 X(_subi, 8000, f1a00000), \
10366 X(_subis, 8000, f1b00000), \
10367 X(_sxtb, b240, fa4ff080), \
10368 X(_sxth, b200, fa0ff080), \
10369 X(_tst, 4200, ea100f00), \
10370 X(_uxtb, b2c0, fa5ff080), \
10371 X(_uxth, b280, fa1ff080), \
10372 X(_nop, bf00, f3af8000), \
10373 X(_yield, bf10, f3af8001), \
10374 X(_wfe, bf20, f3af8002), \
10375 X(_wfi, bf30, f3af8003), \
10376 X(_sev, bf40, f3af8004), \
10377 X(_sevl, bf50, f3af8005), \
10378 X(_udf, de00, f7f0a000)
10380 /* To catch errors in encoding functions, the codes are all offset by
10381 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10382 as 16-bit instructions. */
10383 #define X(a,b,c) T_MNEM##a
10384 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10387 #define X(a,b,c) 0x##b
10388 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10389 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10392 #define X(a,b,c) 0x##c
10393 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10394 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10395 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10399 /* Thumb instruction encoders, in alphabetical order. */
10401 /* ADDW or SUBW. */
10404 do_t_add_sub_w (void)
10408 Rd
= inst
.operands
[0].reg
;
10409 Rn
= inst
.operands
[1].reg
;
10411 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10412 is the SP-{plus,minus}-immediate form of the instruction. */
10414 constraint (Rd
== REG_PC
, BAD_PC
);
10416 reject_bad_reg (Rd
);
10418 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10419 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10422 /* Parse an add or subtract instruction. We get here with inst.instruction
10423 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10426 do_t_add_sub (void)
10430 Rd
= inst
.operands
[0].reg
;
10431 Rs
= (inst
.operands
[1].present
10432 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10433 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10436 set_it_insn_type_last ();
10438 if (unified_syntax
)
10441 bfd_boolean narrow
;
10444 flags
= (inst
.instruction
== T_MNEM_adds
10445 || inst
.instruction
== T_MNEM_subs
);
10447 narrow
= !in_it_block ();
10449 narrow
= in_it_block ();
10450 if (!inst
.operands
[2].isreg
)
10454 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10456 add
= (inst
.instruction
== T_MNEM_add
10457 || inst
.instruction
== T_MNEM_adds
);
10459 if (inst
.size_req
!= 4)
10461 /* Attempt to use a narrow opcode, with relaxation if
10463 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10464 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10465 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10466 opcode
= T_MNEM_add_sp
;
10467 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10468 opcode
= T_MNEM_add_pc
;
10469 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10472 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10474 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10478 inst
.instruction
= THUMB_OP16(opcode
);
10479 inst
.instruction
|= (Rd
<< 4) | Rs
;
10480 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10481 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10483 if (inst
.size_req
== 2)
10484 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10486 inst
.relax
= opcode
;
10490 constraint (inst
.size_req
== 2, BAD_HIREG
);
10492 if (inst
.size_req
== 4
10493 || (inst
.size_req
!= 2 && !opcode
))
10495 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10496 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10497 THUMB1_RELOC_ONLY
);
10500 constraint (add
, BAD_PC
);
10501 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10502 _("only SUBS PC, LR, #const allowed"));
10503 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10504 _("expression too complex"));
10505 constraint (inst
.reloc
.exp
.X_add_number
< 0
10506 || inst
.reloc
.exp
.X_add_number
> 0xff,
10507 _("immediate value out of range"));
10508 inst
.instruction
= T2_SUBS_PC_LR
10509 | inst
.reloc
.exp
.X_add_number
;
10510 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10513 else if (Rs
== REG_PC
)
10515 /* Always use addw/subw. */
10516 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10517 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10522 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10525 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10527 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10529 inst
.instruction
|= Rd
<< 8;
10530 inst
.instruction
|= Rs
<< 16;
10535 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10536 unsigned int shift
= inst
.operands
[2].shift_kind
;
10538 Rn
= inst
.operands
[2].reg
;
10539 /* See if we can do this with a 16-bit instruction. */
10540 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10542 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10547 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10548 || inst
.instruction
== T_MNEM_add
)
10550 : T_OPCODE_SUB_R3
);
10551 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10555 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10557 /* Thumb-1 cores (except v6-M) require at least one high
10558 register in a narrow non flag setting add. */
10559 if (Rd
> 7 || Rn
> 7
10560 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10561 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10568 inst
.instruction
= T_OPCODE_ADD_HI
;
10569 inst
.instruction
|= (Rd
& 8) << 4;
10570 inst
.instruction
|= (Rd
& 7);
10571 inst
.instruction
|= Rn
<< 3;
10577 constraint (Rd
== REG_PC
, BAD_PC
);
10578 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10579 constraint (Rs
== REG_PC
, BAD_PC
);
10580 reject_bad_reg (Rn
);
10582 /* If we get here, it can't be done in 16 bits. */
10583 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10584 _("shift must be constant"));
10585 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10586 inst
.instruction
|= Rd
<< 8;
10587 inst
.instruction
|= Rs
<< 16;
10588 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10589 _("shift value over 3 not allowed in thumb mode"));
10590 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10591 _("only LSL shift allowed in thumb mode"));
10592 encode_thumb32_shifted_operand (2);
10597 constraint (inst
.instruction
== T_MNEM_adds
10598 || inst
.instruction
== T_MNEM_subs
,
10601 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10603 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10604 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10607 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10608 ? 0x0000 : 0x8000);
10609 inst
.instruction
|= (Rd
<< 4) | Rs
;
10610 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10614 Rn
= inst
.operands
[2].reg
;
10615 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10617 /* We now have Rd, Rs, and Rn set to registers. */
10618 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10620 /* Can't do this for SUB. */
10621 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10622 inst
.instruction
= T_OPCODE_ADD_HI
;
10623 inst
.instruction
|= (Rd
& 8) << 4;
10624 inst
.instruction
|= (Rd
& 7);
10626 inst
.instruction
|= Rn
<< 3;
10628 inst
.instruction
|= Rs
<< 3;
10630 constraint (1, _("dest must overlap one source register"));
10634 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10635 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10636 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10646 Rd
= inst
.operands
[0].reg
;
10647 reject_bad_reg (Rd
);
10649 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10651 /* Defer to section relaxation. */
10652 inst
.relax
= inst
.instruction
;
10653 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10654 inst
.instruction
|= Rd
<< 4;
10656 else if (unified_syntax
&& inst
.size_req
!= 2)
10658 /* Generate a 32-bit opcode. */
10659 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10660 inst
.instruction
|= Rd
<< 8;
10661 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10662 inst
.reloc
.pc_rel
= 1;
10666 /* Generate a 16-bit opcode. */
10667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10668 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10669 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10670 inst
.reloc
.pc_rel
= 1;
10672 inst
.instruction
|= Rd
<< 4;
10676 /* Arithmetic instructions for which there is just one 16-bit
10677 instruction encoding, and it allows only two low registers.
10678 For maximal compatibility with ARM syntax, we allow three register
10679 operands even when Thumb-32 instructions are not available, as long
10680 as the first two are identical. For instance, both "sbc r0,r1" and
10681 "sbc r0,r0,r1" are allowed. */
10687 Rd
= inst
.operands
[0].reg
;
10688 Rs
= (inst
.operands
[1].present
10689 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10690 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10691 Rn
= inst
.operands
[2].reg
;
10693 reject_bad_reg (Rd
);
10694 reject_bad_reg (Rs
);
10695 if (inst
.operands
[2].isreg
)
10696 reject_bad_reg (Rn
);
10698 if (unified_syntax
)
10700 if (!inst
.operands
[2].isreg
)
10702 /* For an immediate, we always generate a 32-bit opcode;
10703 section relaxation will shrink it later if possible. */
10704 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10705 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10706 inst
.instruction
|= Rd
<< 8;
10707 inst
.instruction
|= Rs
<< 16;
10708 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10712 bfd_boolean narrow
;
10714 /* See if we can do this with a 16-bit instruction. */
10715 if (THUMB_SETS_FLAGS (inst
.instruction
))
10716 narrow
= !in_it_block ();
10718 narrow
= in_it_block ();
10720 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10722 if (inst
.operands
[2].shifted
)
10724 if (inst
.size_req
== 4)
10730 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10731 inst
.instruction
|= Rd
;
10732 inst
.instruction
|= Rn
<< 3;
10736 /* If we get here, it can't be done in 16 bits. */
10737 constraint (inst
.operands
[2].shifted
10738 && inst
.operands
[2].immisreg
,
10739 _("shift must be constant"));
10740 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10741 inst
.instruction
|= Rd
<< 8;
10742 inst
.instruction
|= Rs
<< 16;
10743 encode_thumb32_shifted_operand (2);
10748 /* On its face this is a lie - the instruction does set the
10749 flags. However, the only supported mnemonic in this mode
10750 says it doesn't. */
10751 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10753 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10754 _("unshifted register required"));
10755 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10756 constraint (Rd
!= Rs
,
10757 _("dest and source1 must be the same register"));
10759 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10760 inst
.instruction
|= Rd
;
10761 inst
.instruction
|= Rn
<< 3;
10765 /* Similarly, but for instructions where the arithmetic operation is
10766 commutative, so we can allow either of them to be different from
10767 the destination operand in a 16-bit instruction. For instance, all
10768 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10775 Rd
= inst
.operands
[0].reg
;
10776 Rs
= (inst
.operands
[1].present
10777 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10778 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10779 Rn
= inst
.operands
[2].reg
;
10781 reject_bad_reg (Rd
);
10782 reject_bad_reg (Rs
);
10783 if (inst
.operands
[2].isreg
)
10784 reject_bad_reg (Rn
);
10786 if (unified_syntax
)
10788 if (!inst
.operands
[2].isreg
)
10790 /* For an immediate, we always generate a 32-bit opcode;
10791 section relaxation will shrink it later if possible. */
10792 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10793 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10794 inst
.instruction
|= Rd
<< 8;
10795 inst
.instruction
|= Rs
<< 16;
10796 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10800 bfd_boolean narrow
;
10802 /* See if we can do this with a 16-bit instruction. */
10803 if (THUMB_SETS_FLAGS (inst
.instruction
))
10804 narrow
= !in_it_block ();
10806 narrow
= in_it_block ();
10808 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10810 if (inst
.operands
[2].shifted
)
10812 if (inst
.size_req
== 4)
10819 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10820 inst
.instruction
|= Rd
;
10821 inst
.instruction
|= Rn
<< 3;
10826 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10827 inst
.instruction
|= Rd
;
10828 inst
.instruction
|= Rs
<< 3;
10833 /* If we get here, it can't be done in 16 bits. */
10834 constraint (inst
.operands
[2].shifted
10835 && inst
.operands
[2].immisreg
,
10836 _("shift must be constant"));
10837 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10838 inst
.instruction
|= Rd
<< 8;
10839 inst
.instruction
|= Rs
<< 16;
10840 encode_thumb32_shifted_operand (2);
10845 /* On its face this is a lie - the instruction does set the
10846 flags. However, the only supported mnemonic in this mode
10847 says it doesn't. */
10848 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10850 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10851 _("unshifted register required"));
10852 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10854 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10855 inst
.instruction
|= Rd
;
10858 inst
.instruction
|= Rn
<< 3;
10860 inst
.instruction
|= Rs
<< 3;
10862 constraint (1, _("dest must overlap one source register"));
10870 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10871 constraint (msb
> 32, _("bit-field extends past end of register"));
10872 /* The instruction encoding stores the LSB and MSB,
10873 not the LSB and width. */
10874 Rd
= inst
.operands
[0].reg
;
10875 reject_bad_reg (Rd
);
10876 inst
.instruction
|= Rd
<< 8;
10877 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10878 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10879 inst
.instruction
|= msb
- 1;
10888 Rd
= inst
.operands
[0].reg
;
10889 reject_bad_reg (Rd
);
10891 /* #0 in second position is alternative syntax for bfc, which is
10892 the same instruction but with REG_PC in the Rm field. */
10893 if (!inst
.operands
[1].isreg
)
10897 Rn
= inst
.operands
[1].reg
;
10898 reject_bad_reg (Rn
);
10901 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10902 constraint (msb
> 32, _("bit-field extends past end of register"));
10903 /* The instruction encoding stores the LSB and MSB,
10904 not the LSB and width. */
10905 inst
.instruction
|= Rd
<< 8;
10906 inst
.instruction
|= Rn
<< 16;
10907 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10908 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10909 inst
.instruction
|= msb
- 1;
10917 Rd
= inst
.operands
[0].reg
;
10918 Rn
= inst
.operands
[1].reg
;
10920 reject_bad_reg (Rd
);
10921 reject_bad_reg (Rn
);
10923 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10924 _("bit-field extends past end of register"));
10925 inst
.instruction
|= Rd
<< 8;
10926 inst
.instruction
|= Rn
<< 16;
10927 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10928 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10929 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10932 /* ARM V5 Thumb BLX (argument parse)
10933 BLX <target_addr> which is BLX(1)
10934 BLX <Rm> which is BLX(2)
10935 Unfortunately, there are two different opcodes for this mnemonic.
10936 So, the insns[].value is not used, and the code here zaps values
10937 into inst.instruction.
10939 ??? How to take advantage of the additional two bits of displacement
10940 available in Thumb32 mode? Need new relocation? */
10945 set_it_insn_type_last ();
10947 if (inst
.operands
[0].isreg
)
10949 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10950 /* We have a register, so this is BLX(2). */
10951 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10955 /* No register. This must be BLX(1). */
10956 inst
.instruction
= 0xf000e800;
10957 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10969 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10971 if (in_it_block ())
10973 /* Conditional branches inside IT blocks are encoded as unconditional
10975 cond
= COND_ALWAYS
;
10980 if (cond
!= COND_ALWAYS
)
10981 opcode
= T_MNEM_bcond
;
10983 opcode
= inst
.instruction
;
10986 && (inst
.size_req
== 4
10987 || (inst
.size_req
!= 2
10988 && (inst
.operands
[0].hasreloc
10989 || inst
.reloc
.exp
.X_op
== O_constant
))))
10991 inst
.instruction
= THUMB_OP32(opcode
);
10992 if (cond
== COND_ALWAYS
)
10993 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
10997 _("selected architecture does not support "
10998 "wide conditional branch instruction"));
11000 gas_assert (cond
!= 0xF);
11001 inst
.instruction
|= cond
<< 22;
11002 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11007 inst
.instruction
= THUMB_OP16(opcode
);
11008 if (cond
== COND_ALWAYS
)
11009 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11012 inst
.instruction
|= cond
<< 8;
11013 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11015 /* Allow section relaxation. */
11016 if (unified_syntax
&& inst
.size_req
!= 2)
11017 inst
.relax
= opcode
;
11019 inst
.reloc
.type
= reloc
;
11020 inst
.reloc
.pc_rel
= 1;
11023 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11024 between the two is the maximum immediate allowed - which is passed in
11027 do_t_bkpt_hlt1 (int range
)
11029 constraint (inst
.cond
!= COND_ALWAYS
,
11030 _("instruction is always unconditional"));
11031 if (inst
.operands
[0].present
)
11033 constraint (inst
.operands
[0].imm
> range
,
11034 _("immediate value out of range"));
11035 inst
.instruction
|= inst
.operands
[0].imm
;
11038 set_it_insn_type (NEUTRAL_IT_INSN
);
11044 do_t_bkpt_hlt1 (63);
11050 do_t_bkpt_hlt1 (255);
11054 do_t_branch23 (void)
11056 set_it_insn_type_last ();
11057 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11059 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11060 this file. We used to simply ignore the PLT reloc type here --
11061 the branch encoding is now needed to deal with TLSCALL relocs.
11062 So if we see a PLT reloc now, put it back to how it used to be to
11063 keep the preexisting behaviour. */
11064 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11065 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11067 #if defined(OBJ_COFF)
11068 /* If the destination of the branch is a defined symbol which does not have
11069 the THUMB_FUNC attribute, then we must be calling a function which has
11070 the (interfacearm) attribute. We look for the Thumb entry point to that
11071 function and change the branch to refer to that function instead. */
11072 if ( inst
.reloc
.exp
.X_op
== O_symbol
11073 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11074 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11075 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11076 inst
.reloc
.exp
.X_add_symbol
=
11077 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11084 set_it_insn_type_last ();
11085 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11086 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11087 should cause the alignment to be checked once it is known. This is
11088 because BX PC only works if the instruction is word aligned. */
11096 set_it_insn_type_last ();
11097 Rm
= inst
.operands
[0].reg
;
11098 reject_bad_reg (Rm
);
11099 inst
.instruction
|= Rm
<< 16;
11108 Rd
= inst
.operands
[0].reg
;
11109 Rm
= inst
.operands
[1].reg
;
11111 reject_bad_reg (Rd
);
11112 reject_bad_reg (Rm
);
11114 inst
.instruction
|= Rd
<< 8;
11115 inst
.instruction
|= Rm
<< 16;
11116 inst
.instruction
|= Rm
;
11122 set_it_insn_type (OUTSIDE_IT_INSN
);
11123 inst
.instruction
|= inst
.operands
[0].imm
;
11129 set_it_insn_type (OUTSIDE_IT_INSN
);
11131 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11132 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11134 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11135 inst
.instruction
= 0xf3af8000;
11136 inst
.instruction
|= imod
<< 9;
11137 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11138 if (inst
.operands
[1].present
)
11139 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11144 && (inst
.operands
[0].imm
& 4),
11145 _("selected processor does not support 'A' form "
11146 "of this instruction"));
11147 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11148 _("Thumb does not support the 2-argument "
11149 "form of this instruction"));
11150 inst
.instruction
|= inst
.operands
[0].imm
;
11154 /* THUMB CPY instruction (argument parse). */
11159 if (inst
.size_req
== 4)
11161 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11162 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11163 inst
.instruction
|= inst
.operands
[1].reg
;
11167 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11168 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11169 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11176 set_it_insn_type (OUTSIDE_IT_INSN
);
11177 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11178 inst
.instruction
|= inst
.operands
[0].reg
;
11179 inst
.reloc
.pc_rel
= 1;
11180 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11186 inst
.instruction
|= inst
.operands
[0].imm
;
11192 unsigned Rd
, Rn
, Rm
;
11194 Rd
= inst
.operands
[0].reg
;
11195 Rn
= (inst
.operands
[1].present
11196 ? inst
.operands
[1].reg
: Rd
);
11197 Rm
= inst
.operands
[2].reg
;
11199 reject_bad_reg (Rd
);
11200 reject_bad_reg (Rn
);
11201 reject_bad_reg (Rm
);
11203 inst
.instruction
|= Rd
<< 8;
11204 inst
.instruction
|= Rn
<< 16;
11205 inst
.instruction
|= Rm
;
11211 if (unified_syntax
&& inst
.size_req
== 4)
11212 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11214 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11220 unsigned int cond
= inst
.operands
[0].imm
;
11222 set_it_insn_type (IT_INSN
);
11223 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11225 now_it
.warn_deprecated
= FALSE
;
11227 /* If the condition is a negative condition, invert the mask. */
11228 if ((cond
& 0x1) == 0x0)
11230 unsigned int mask
= inst
.instruction
& 0x000f;
11232 if ((mask
& 0x7) == 0)
11234 /* No conversion needed. */
11235 now_it
.block_length
= 1;
11237 else if ((mask
& 0x3) == 0)
11240 now_it
.block_length
= 2;
11242 else if ((mask
& 0x1) == 0)
11245 now_it
.block_length
= 3;
11250 now_it
.block_length
= 4;
11253 inst
.instruction
&= 0xfff0;
11254 inst
.instruction
|= mask
;
11257 inst
.instruction
|= cond
<< 4;
11260 /* Helper function used for both push/pop and ldm/stm. */
11262 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11266 load
= (inst
.instruction
& (1 << 20)) != 0;
11268 if (mask
& (1 << 13))
11269 inst
.error
= _("SP not allowed in register list");
11271 if ((mask
& (1 << base
)) != 0
11273 inst
.error
= _("having the base register in the register list when "
11274 "using write back is UNPREDICTABLE");
11278 if (mask
& (1 << 15))
11280 if (mask
& (1 << 14))
11281 inst
.error
= _("LR and PC should not both be in register list");
11283 set_it_insn_type_last ();
11288 if (mask
& (1 << 15))
11289 inst
.error
= _("PC not allowed in register list");
11292 if ((mask
& (mask
- 1)) == 0)
11294 /* Single register transfers implemented as str/ldr. */
11297 if (inst
.instruction
& (1 << 23))
11298 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11300 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11304 if (inst
.instruction
& (1 << 23))
11305 inst
.instruction
= 0x00800000; /* ia -> [base] */
11307 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11310 inst
.instruction
|= 0xf8400000;
11312 inst
.instruction
|= 0x00100000;
11314 mask
= ffs (mask
) - 1;
11317 else if (writeback
)
11318 inst
.instruction
|= WRITE_BACK
;
11320 inst
.instruction
|= mask
;
11321 inst
.instruction
|= base
<< 16;
11327 /* This really doesn't seem worth it. */
11328 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11329 _("expression too complex"));
11330 constraint (inst
.operands
[1].writeback
,
11331 _("Thumb load/store multiple does not support {reglist}^"));
11333 if (unified_syntax
)
11335 bfd_boolean narrow
;
11339 /* See if we can use a 16-bit instruction. */
11340 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11341 && inst
.size_req
!= 4
11342 && !(inst
.operands
[1].imm
& ~0xff))
11344 mask
= 1 << inst
.operands
[0].reg
;
11346 if (inst
.operands
[0].reg
<= 7)
11348 if (inst
.instruction
== T_MNEM_stmia
11349 ? inst
.operands
[0].writeback
11350 : (inst
.operands
[0].writeback
11351 == !(inst
.operands
[1].imm
& mask
)))
11353 if (inst
.instruction
== T_MNEM_stmia
11354 && (inst
.operands
[1].imm
& mask
)
11355 && (inst
.operands
[1].imm
& (mask
- 1)))
11356 as_warn (_("value stored for r%d is UNKNOWN"),
11357 inst
.operands
[0].reg
);
11359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11360 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11361 inst
.instruction
|= inst
.operands
[1].imm
;
11364 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11366 /* This means 1 register in reg list one of 3 situations:
11367 1. Instruction is stmia, but without writeback.
11368 2. lmdia without writeback, but with Rn not in
11370 3. ldmia with writeback, but with Rn in reglist.
11371 Case 3 is UNPREDICTABLE behaviour, so we handle
11372 case 1 and 2 which can be converted into a 16-bit
11373 str or ldr. The SP cases are handled below. */
11374 unsigned long opcode
;
11375 /* First, record an error for Case 3. */
11376 if (inst
.operands
[1].imm
& mask
11377 && inst
.operands
[0].writeback
)
11379 _("having the base register in the register list when "
11380 "using write back is UNPREDICTABLE");
11382 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11384 inst
.instruction
= THUMB_OP16 (opcode
);
11385 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11386 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11390 else if (inst
.operands
[0] .reg
== REG_SP
)
11392 if (inst
.operands
[0].writeback
)
11395 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11396 ? T_MNEM_push
: T_MNEM_pop
);
11397 inst
.instruction
|= inst
.operands
[1].imm
;
11400 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11403 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11404 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11405 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11413 if (inst
.instruction
< 0xffff)
11414 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11416 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11417 inst
.operands
[0].writeback
);
11422 constraint (inst
.operands
[0].reg
> 7
11423 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11424 constraint (inst
.instruction
!= T_MNEM_ldmia
11425 && inst
.instruction
!= T_MNEM_stmia
,
11426 _("Thumb-2 instruction only valid in unified syntax"));
11427 if (inst
.instruction
== T_MNEM_stmia
)
11429 if (!inst
.operands
[0].writeback
)
11430 as_warn (_("this instruction will write back the base register"));
11431 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11432 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11433 as_warn (_("value stored for r%d is UNKNOWN"),
11434 inst
.operands
[0].reg
);
11438 if (!inst
.operands
[0].writeback
11439 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11440 as_warn (_("this instruction will write back the base register"));
11441 else if (inst
.operands
[0].writeback
11442 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11443 as_warn (_("this instruction will not write back the base register"));
11446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11447 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11448 inst
.instruction
|= inst
.operands
[1].imm
;
11455 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11456 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11457 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11458 || inst
.operands
[1].negative
,
11461 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11464 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11465 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11471 if (!inst
.operands
[1].present
)
11473 constraint (inst
.operands
[0].reg
== REG_LR
,
11474 _("r14 not allowed as first register "
11475 "when second register is omitted"));
11476 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11478 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11481 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11482 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11483 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11489 unsigned long opcode
;
11492 if (inst
.operands
[0].isreg
11493 && !inst
.operands
[0].preind
11494 && inst
.operands
[0].reg
== REG_PC
)
11495 set_it_insn_type_last ();
11497 opcode
= inst
.instruction
;
11498 if (unified_syntax
)
11500 if (!inst
.operands
[1].isreg
)
11502 if (opcode
<= 0xffff)
11503 inst
.instruction
= THUMB_OP32 (opcode
);
11504 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11507 if (inst
.operands
[1].isreg
11508 && !inst
.operands
[1].writeback
11509 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11510 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11511 && opcode
<= 0xffff
11512 && inst
.size_req
!= 4)
11514 /* Insn may have a 16-bit form. */
11515 Rn
= inst
.operands
[1].reg
;
11516 if (inst
.operands
[1].immisreg
)
11518 inst
.instruction
= THUMB_OP16 (opcode
);
11520 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11522 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11523 reject_bad_reg (inst
.operands
[1].imm
);
11525 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11526 && opcode
!= T_MNEM_ldrsb
)
11527 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11528 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11535 if (inst
.reloc
.pc_rel
)
11536 opcode
= T_MNEM_ldr_pc2
;
11538 opcode
= T_MNEM_ldr_pc
;
11542 if (opcode
== T_MNEM_ldr
)
11543 opcode
= T_MNEM_ldr_sp
;
11545 opcode
= T_MNEM_str_sp
;
11547 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11551 inst
.instruction
= inst
.operands
[0].reg
;
11552 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11554 inst
.instruction
|= THUMB_OP16 (opcode
);
11555 if (inst
.size_req
== 2)
11556 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11558 inst
.relax
= opcode
;
11562 /* Definitely a 32-bit variant. */
11564 /* Warning for Erratum 752419. */
11565 if (opcode
== T_MNEM_ldr
11566 && inst
.operands
[0].reg
== REG_SP
11567 && inst
.operands
[1].writeback
== 1
11568 && !inst
.operands
[1].immisreg
)
11570 if (no_cpu_selected ()
11571 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11572 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11573 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11574 as_warn (_("This instruction may be unpredictable "
11575 "if executed on M-profile cores "
11576 "with interrupts enabled."));
11579 /* Do some validations regarding addressing modes. */
11580 if (inst
.operands
[1].immisreg
)
11581 reject_bad_reg (inst
.operands
[1].imm
);
11583 constraint (inst
.operands
[1].writeback
== 1
11584 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11587 inst
.instruction
= THUMB_OP32 (opcode
);
11588 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11589 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11590 check_ldr_r15_aligned ();
11594 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11596 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11598 /* Only [Rn,Rm] is acceptable. */
11599 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11600 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11601 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11602 || inst
.operands
[1].negative
,
11603 _("Thumb does not support this addressing mode"));
11604 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11608 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11609 if (!inst
.operands
[1].isreg
)
11610 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11613 constraint (!inst
.operands
[1].preind
11614 || inst
.operands
[1].shifted
11615 || inst
.operands
[1].writeback
,
11616 _("Thumb does not support this addressing mode"));
11617 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11619 constraint (inst
.instruction
& 0x0600,
11620 _("byte or halfword not valid for base register"));
11621 constraint (inst
.operands
[1].reg
== REG_PC
11622 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11623 _("r15 based store not allowed"));
11624 constraint (inst
.operands
[1].immisreg
,
11625 _("invalid base register for register offset"));
11627 if (inst
.operands
[1].reg
== REG_PC
)
11628 inst
.instruction
= T_OPCODE_LDR_PC
;
11629 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11630 inst
.instruction
= T_OPCODE_LDR_SP
;
11632 inst
.instruction
= T_OPCODE_STR_SP
;
11634 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11635 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11639 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11640 if (!inst
.operands
[1].immisreg
)
11642 /* Immediate offset. */
11643 inst
.instruction
|= inst
.operands
[0].reg
;
11644 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11645 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11649 /* Register offset. */
11650 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11651 constraint (inst
.operands
[1].negative
,
11652 _("Thumb does not support this addressing mode"));
11655 switch (inst
.instruction
)
11657 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11658 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11659 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11660 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11661 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11662 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11663 case 0x5600 /* ldrsb */:
11664 case 0x5e00 /* ldrsh */: break;
11668 inst
.instruction
|= inst
.operands
[0].reg
;
11669 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11670 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11676 if (!inst
.operands
[1].present
)
11678 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11679 constraint (inst
.operands
[0].reg
== REG_LR
,
11680 _("r14 not allowed here"));
11681 constraint (inst
.operands
[0].reg
== REG_R12
,
11682 _("r12 not allowed here"));
11685 if (inst
.operands
[2].writeback
11686 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11687 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11688 as_warn (_("base register written back, and overlaps "
11689 "one of transfer registers"));
11691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11692 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11693 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11699 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11700 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11706 unsigned Rd
, Rn
, Rm
, Ra
;
11708 Rd
= inst
.operands
[0].reg
;
11709 Rn
= inst
.operands
[1].reg
;
11710 Rm
= inst
.operands
[2].reg
;
11711 Ra
= inst
.operands
[3].reg
;
11713 reject_bad_reg (Rd
);
11714 reject_bad_reg (Rn
);
11715 reject_bad_reg (Rm
);
11716 reject_bad_reg (Ra
);
11718 inst
.instruction
|= Rd
<< 8;
11719 inst
.instruction
|= Rn
<< 16;
11720 inst
.instruction
|= Rm
;
11721 inst
.instruction
|= Ra
<< 12;
11727 unsigned RdLo
, RdHi
, Rn
, Rm
;
11729 RdLo
= inst
.operands
[0].reg
;
11730 RdHi
= inst
.operands
[1].reg
;
11731 Rn
= inst
.operands
[2].reg
;
11732 Rm
= inst
.operands
[3].reg
;
11734 reject_bad_reg (RdLo
);
11735 reject_bad_reg (RdHi
);
11736 reject_bad_reg (Rn
);
11737 reject_bad_reg (Rm
);
11739 inst
.instruction
|= RdLo
<< 12;
11740 inst
.instruction
|= RdHi
<< 8;
11741 inst
.instruction
|= Rn
<< 16;
11742 inst
.instruction
|= Rm
;
11746 do_t_mov_cmp (void)
11750 Rn
= inst
.operands
[0].reg
;
11751 Rm
= inst
.operands
[1].reg
;
11754 set_it_insn_type_last ();
11756 if (unified_syntax
)
11758 int r0off
= (inst
.instruction
== T_MNEM_mov
11759 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11760 unsigned long opcode
;
11761 bfd_boolean narrow
;
11762 bfd_boolean low_regs
;
11764 low_regs
= (Rn
<= 7 && Rm
<= 7);
11765 opcode
= inst
.instruction
;
11766 if (in_it_block ())
11767 narrow
= opcode
!= T_MNEM_movs
;
11769 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11770 if (inst
.size_req
== 4
11771 || inst
.operands
[1].shifted
)
11774 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11775 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11776 && !inst
.operands
[1].shifted
11780 inst
.instruction
= T2_SUBS_PC_LR
;
11784 if (opcode
== T_MNEM_cmp
)
11786 constraint (Rn
== REG_PC
, BAD_PC
);
11789 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11791 warn_deprecated_sp (Rm
);
11792 /* R15 was documented as a valid choice for Rm in ARMv6,
11793 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11794 tools reject R15, so we do too. */
11795 constraint (Rm
== REG_PC
, BAD_PC
);
11798 reject_bad_reg (Rm
);
11800 else if (opcode
== T_MNEM_mov
11801 || opcode
== T_MNEM_movs
)
11803 if (inst
.operands
[1].isreg
)
11805 if (opcode
== T_MNEM_movs
)
11807 reject_bad_reg (Rn
);
11808 reject_bad_reg (Rm
);
11812 /* This is mov.n. */
11813 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11814 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11816 as_tsktsk (_("Use of r%u as a source register is "
11817 "deprecated when r%u is the destination "
11818 "register."), Rm
, Rn
);
11823 /* This is mov.w. */
11824 constraint (Rn
== REG_PC
, BAD_PC
);
11825 constraint (Rm
== REG_PC
, BAD_PC
);
11826 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11830 reject_bad_reg (Rn
);
11833 if (!inst
.operands
[1].isreg
)
11835 /* Immediate operand. */
11836 if (!in_it_block () && opcode
== T_MNEM_mov
)
11838 if (low_regs
&& narrow
)
11840 inst
.instruction
= THUMB_OP16 (opcode
);
11841 inst
.instruction
|= Rn
<< 8;
11842 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11843 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11845 if (inst
.size_req
== 2)
11846 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11848 inst
.relax
= opcode
;
11853 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11854 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11855 THUMB1_RELOC_ONLY
);
11857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11858 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11859 inst
.instruction
|= Rn
<< r0off
;
11860 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11863 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11864 && (inst
.instruction
== T_MNEM_mov
11865 || inst
.instruction
== T_MNEM_movs
))
11867 /* Register shifts are encoded as separate shift instructions. */
11868 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11870 if (in_it_block ())
11875 if (inst
.size_req
== 4)
11878 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11884 switch (inst
.operands
[1].shift_kind
)
11887 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11890 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11893 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11896 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11902 inst
.instruction
= opcode
;
11905 inst
.instruction
|= Rn
;
11906 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11911 inst
.instruction
|= CONDS_BIT
;
11913 inst
.instruction
|= Rn
<< 8;
11914 inst
.instruction
|= Rm
<< 16;
11915 inst
.instruction
|= inst
.operands
[1].imm
;
11920 /* Some mov with immediate shift have narrow variants.
11921 Register shifts are handled above. */
11922 if (low_regs
&& inst
.operands
[1].shifted
11923 && (inst
.instruction
== T_MNEM_mov
11924 || inst
.instruction
== T_MNEM_movs
))
11926 if (in_it_block ())
11927 narrow
= (inst
.instruction
== T_MNEM_mov
);
11929 narrow
= (inst
.instruction
== T_MNEM_movs
);
11934 switch (inst
.operands
[1].shift_kind
)
11936 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11937 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11938 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11939 default: narrow
= FALSE
; break;
11945 inst
.instruction
|= Rn
;
11946 inst
.instruction
|= Rm
<< 3;
11947 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11951 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11952 inst
.instruction
|= Rn
<< r0off
;
11953 encode_thumb32_shifted_operand (1);
11957 switch (inst
.instruction
)
11960 /* In v4t or v5t a move of two lowregs produces unpredictable
11961 results. Don't allow this. */
11964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11965 "MOV Rd, Rs with two low registers is not "
11966 "permitted on this architecture");
11967 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11971 inst
.instruction
= T_OPCODE_MOV_HR
;
11972 inst
.instruction
|= (Rn
& 0x8) << 4;
11973 inst
.instruction
|= (Rn
& 0x7);
11974 inst
.instruction
|= Rm
<< 3;
11978 /* We know we have low registers at this point.
11979 Generate LSLS Rd, Rs, #0. */
11980 inst
.instruction
= T_OPCODE_LSL_I
;
11981 inst
.instruction
|= Rn
;
11982 inst
.instruction
|= Rm
<< 3;
11988 inst
.instruction
= T_OPCODE_CMP_LR
;
11989 inst
.instruction
|= Rn
;
11990 inst
.instruction
|= Rm
<< 3;
11994 inst
.instruction
= T_OPCODE_CMP_HR
;
11995 inst
.instruction
|= (Rn
& 0x8) << 4;
11996 inst
.instruction
|= (Rn
& 0x7);
11997 inst
.instruction
|= Rm
<< 3;
12004 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12006 /* PR 10443: Do not silently ignore shifted operands. */
12007 constraint (inst
.operands
[1].shifted
,
12008 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12010 if (inst
.operands
[1].isreg
)
12012 if (Rn
< 8 && Rm
< 8)
12014 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12015 since a MOV instruction produces unpredictable results. */
12016 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12017 inst
.instruction
= T_OPCODE_ADD_I3
;
12019 inst
.instruction
= T_OPCODE_CMP_LR
;
12021 inst
.instruction
|= Rn
;
12022 inst
.instruction
|= Rm
<< 3;
12026 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12027 inst
.instruction
= T_OPCODE_MOV_HR
;
12029 inst
.instruction
= T_OPCODE_CMP_HR
;
12035 constraint (Rn
> 7,
12036 _("only lo regs allowed with immediate"));
12037 inst
.instruction
|= Rn
<< 8;
12038 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12049 top
= (inst
.instruction
& 0x00800000) != 0;
12050 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12052 constraint (top
, _(":lower16: not allowed this instruction"));
12053 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12055 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12057 constraint (!top
, _(":upper16: not allowed this instruction"));
12058 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12061 Rd
= inst
.operands
[0].reg
;
12062 reject_bad_reg (Rd
);
12064 inst
.instruction
|= Rd
<< 8;
12065 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12067 imm
= inst
.reloc
.exp
.X_add_number
;
12068 inst
.instruction
|= (imm
& 0xf000) << 4;
12069 inst
.instruction
|= (imm
& 0x0800) << 15;
12070 inst
.instruction
|= (imm
& 0x0700) << 4;
12071 inst
.instruction
|= (imm
& 0x00ff);
12076 do_t_mvn_tst (void)
12080 Rn
= inst
.operands
[0].reg
;
12081 Rm
= inst
.operands
[1].reg
;
12083 if (inst
.instruction
== T_MNEM_cmp
12084 || inst
.instruction
== T_MNEM_cmn
)
12085 constraint (Rn
== REG_PC
, BAD_PC
);
12087 reject_bad_reg (Rn
);
12088 reject_bad_reg (Rm
);
12090 if (unified_syntax
)
12092 int r0off
= (inst
.instruction
== T_MNEM_mvn
12093 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12094 bfd_boolean narrow
;
12096 if (inst
.size_req
== 4
12097 || inst
.instruction
> 0xffff
12098 || inst
.operands
[1].shifted
12099 || Rn
> 7 || Rm
> 7)
12101 else if (inst
.instruction
== T_MNEM_cmn
12102 || inst
.instruction
== T_MNEM_tst
)
12104 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12105 narrow
= !in_it_block ();
12107 narrow
= in_it_block ();
12109 if (!inst
.operands
[1].isreg
)
12111 /* For an immediate, we always generate a 32-bit opcode;
12112 section relaxation will shrink it later if possible. */
12113 if (inst
.instruction
< 0xffff)
12114 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12115 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12116 inst
.instruction
|= Rn
<< r0off
;
12117 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12121 /* See if we can do this with a 16-bit instruction. */
12124 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12125 inst
.instruction
|= Rn
;
12126 inst
.instruction
|= Rm
<< 3;
12130 constraint (inst
.operands
[1].shifted
12131 && inst
.operands
[1].immisreg
,
12132 _("shift must be constant"));
12133 if (inst
.instruction
< 0xffff)
12134 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12135 inst
.instruction
|= Rn
<< r0off
;
12136 encode_thumb32_shifted_operand (1);
12142 constraint (inst
.instruction
> 0xffff
12143 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12144 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12145 _("unshifted register required"));
12146 constraint (Rn
> 7 || Rm
> 7,
12149 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12150 inst
.instruction
|= Rn
;
12151 inst
.instruction
|= Rm
<< 3;
12160 if (do_vfp_nsyn_mrs () == SUCCESS
)
12163 Rd
= inst
.operands
[0].reg
;
12164 reject_bad_reg (Rd
);
12165 inst
.instruction
|= Rd
<< 8;
12167 if (inst
.operands
[1].isreg
)
12169 unsigned br
= inst
.operands
[1].reg
;
12170 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12171 as_bad (_("bad register for mrs"));
12173 inst
.instruction
|= br
& (0xf << 16);
12174 inst
.instruction
|= (br
& 0x300) >> 4;
12175 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12179 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12181 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12183 /* PR gas/12698: The constraint is only applied for m_profile.
12184 If the user has specified -march=all, we want to ignore it as
12185 we are building for any CPU type, including non-m variants. */
12186 bfd_boolean m_profile
=
12187 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12188 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12189 "not support requested special purpose register"));
12192 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12194 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12195 _("'APSR', 'CPSR' or 'SPSR' expected"));
12197 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12198 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12199 inst
.instruction
|= 0xf0000;
12209 if (do_vfp_nsyn_msr () == SUCCESS
)
12212 constraint (!inst
.operands
[1].isreg
,
12213 _("Thumb encoding does not support an immediate here"));
12215 if (inst
.operands
[0].isreg
)
12216 flags
= (int)(inst
.operands
[0].reg
);
12218 flags
= inst
.operands
[0].imm
;
12220 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12222 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12224 /* PR gas/12698: The constraint is only applied for m_profile.
12225 If the user has specified -march=all, we want to ignore it as
12226 we are building for any CPU type, including non-m variants. */
12227 bfd_boolean m_profile
=
12228 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12229 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12230 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12231 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12232 && bits
!= PSR_f
)) && m_profile
,
12233 _("selected processor does not support requested special "
12234 "purpose register"));
12237 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12238 "requested special purpose register"));
12240 Rn
= inst
.operands
[1].reg
;
12241 reject_bad_reg (Rn
);
12243 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12244 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12245 inst
.instruction
|= (flags
& 0x300) >> 4;
12246 inst
.instruction
|= (flags
& 0xff);
12247 inst
.instruction
|= Rn
<< 16;
12253 bfd_boolean narrow
;
12254 unsigned Rd
, Rn
, Rm
;
12256 if (!inst
.operands
[2].present
)
12257 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12259 Rd
= inst
.operands
[0].reg
;
12260 Rn
= inst
.operands
[1].reg
;
12261 Rm
= inst
.operands
[2].reg
;
12263 if (unified_syntax
)
12265 if (inst
.size_req
== 4
12271 else if (inst
.instruction
== T_MNEM_muls
)
12272 narrow
= !in_it_block ();
12274 narrow
= in_it_block ();
12278 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12279 constraint (Rn
> 7 || Rm
> 7,
12286 /* 16-bit MULS/Conditional MUL. */
12287 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12288 inst
.instruction
|= Rd
;
12291 inst
.instruction
|= Rm
<< 3;
12293 inst
.instruction
|= Rn
<< 3;
12295 constraint (1, _("dest must overlap one source register"));
12299 constraint (inst
.instruction
!= T_MNEM_mul
,
12300 _("Thumb-2 MUL must not set flags"));
12302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12303 inst
.instruction
|= Rd
<< 8;
12304 inst
.instruction
|= Rn
<< 16;
12305 inst
.instruction
|= Rm
<< 0;
12307 reject_bad_reg (Rd
);
12308 reject_bad_reg (Rn
);
12309 reject_bad_reg (Rm
);
12316 unsigned RdLo
, RdHi
, Rn
, Rm
;
12318 RdLo
= inst
.operands
[0].reg
;
12319 RdHi
= inst
.operands
[1].reg
;
12320 Rn
= inst
.operands
[2].reg
;
12321 Rm
= inst
.operands
[3].reg
;
12323 reject_bad_reg (RdLo
);
12324 reject_bad_reg (RdHi
);
12325 reject_bad_reg (Rn
);
12326 reject_bad_reg (Rm
);
12328 inst
.instruction
|= RdLo
<< 12;
12329 inst
.instruction
|= RdHi
<< 8;
12330 inst
.instruction
|= Rn
<< 16;
12331 inst
.instruction
|= Rm
;
12334 as_tsktsk (_("rdhi and rdlo must be different"));
12340 set_it_insn_type (NEUTRAL_IT_INSN
);
12342 if (unified_syntax
)
12344 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12346 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12347 inst
.instruction
|= inst
.operands
[0].imm
;
12351 /* PR9722: Check for Thumb2 availability before
12352 generating a thumb2 nop instruction. */
12353 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12355 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12356 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12359 inst
.instruction
= 0x46c0;
12364 constraint (inst
.operands
[0].present
,
12365 _("Thumb does not support NOP with hints"));
12366 inst
.instruction
= 0x46c0;
12373 if (unified_syntax
)
12375 bfd_boolean narrow
;
12377 if (THUMB_SETS_FLAGS (inst
.instruction
))
12378 narrow
= !in_it_block ();
12380 narrow
= in_it_block ();
12381 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12383 if (inst
.size_req
== 4)
12388 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12389 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12390 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12394 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12395 inst
.instruction
|= inst
.operands
[0].reg
;
12396 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12401 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12403 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12405 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12406 inst
.instruction
|= inst
.operands
[0].reg
;
12407 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12416 Rd
= inst
.operands
[0].reg
;
12417 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12419 reject_bad_reg (Rd
);
12420 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12421 reject_bad_reg (Rn
);
12423 inst
.instruction
|= Rd
<< 8;
12424 inst
.instruction
|= Rn
<< 16;
12426 if (!inst
.operands
[2].isreg
)
12428 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12429 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12435 Rm
= inst
.operands
[2].reg
;
12436 reject_bad_reg (Rm
);
12438 constraint (inst
.operands
[2].shifted
12439 && inst
.operands
[2].immisreg
,
12440 _("shift must be constant"));
12441 encode_thumb32_shifted_operand (2);
12448 unsigned Rd
, Rn
, Rm
;
12450 Rd
= inst
.operands
[0].reg
;
12451 Rn
= inst
.operands
[1].reg
;
12452 Rm
= inst
.operands
[2].reg
;
12454 reject_bad_reg (Rd
);
12455 reject_bad_reg (Rn
);
12456 reject_bad_reg (Rm
);
12458 inst
.instruction
|= Rd
<< 8;
12459 inst
.instruction
|= Rn
<< 16;
12460 inst
.instruction
|= Rm
;
12461 if (inst
.operands
[3].present
)
12463 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12464 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12465 _("expression too complex"));
12466 inst
.instruction
|= (val
& 0x1c) << 10;
12467 inst
.instruction
|= (val
& 0x03) << 6;
12474 if (!inst
.operands
[3].present
)
12478 inst
.instruction
&= ~0x00000020;
12480 /* PR 10168. Swap the Rm and Rn registers. */
12481 Rtmp
= inst
.operands
[1].reg
;
12482 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12483 inst
.operands
[2].reg
= Rtmp
;
12491 if (inst
.operands
[0].immisreg
)
12492 reject_bad_reg (inst
.operands
[0].imm
);
12494 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12498 do_t_push_pop (void)
12502 constraint (inst
.operands
[0].writeback
,
12503 _("push/pop do not support {reglist}^"));
12504 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12505 _("expression too complex"));
12507 mask
= inst
.operands
[0].imm
;
12508 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12509 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12510 else if (inst
.size_req
!= 4
12511 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12512 ? REG_LR
: REG_PC
)))
12514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12515 inst
.instruction
|= THUMB_PP_PC_LR
;
12516 inst
.instruction
|= mask
& 0xff;
12518 else if (unified_syntax
)
12520 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12521 encode_thumb2_ldmstm (13, mask
, TRUE
);
12525 inst
.error
= _("invalid register list to push/pop instruction");
12535 Rd
= inst
.operands
[0].reg
;
12536 Rm
= inst
.operands
[1].reg
;
12538 reject_bad_reg (Rd
);
12539 reject_bad_reg (Rm
);
12541 inst
.instruction
|= Rd
<< 8;
12542 inst
.instruction
|= Rm
<< 16;
12543 inst
.instruction
|= Rm
;
12551 Rd
= inst
.operands
[0].reg
;
12552 Rm
= inst
.operands
[1].reg
;
12554 reject_bad_reg (Rd
);
12555 reject_bad_reg (Rm
);
12557 if (Rd
<= 7 && Rm
<= 7
12558 && inst
.size_req
!= 4)
12560 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12561 inst
.instruction
|= Rd
;
12562 inst
.instruction
|= Rm
<< 3;
12564 else if (unified_syntax
)
12566 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12567 inst
.instruction
|= Rd
<< 8;
12568 inst
.instruction
|= Rm
<< 16;
12569 inst
.instruction
|= Rm
;
12572 inst
.error
= BAD_HIREG
;
12580 Rd
= inst
.operands
[0].reg
;
12581 Rm
= inst
.operands
[1].reg
;
12583 reject_bad_reg (Rd
);
12584 reject_bad_reg (Rm
);
12586 inst
.instruction
|= Rd
<< 8;
12587 inst
.instruction
|= Rm
;
12595 Rd
= inst
.operands
[0].reg
;
12596 Rs
= (inst
.operands
[1].present
12597 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12598 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12600 reject_bad_reg (Rd
);
12601 reject_bad_reg (Rs
);
12602 if (inst
.operands
[2].isreg
)
12603 reject_bad_reg (inst
.operands
[2].reg
);
12605 inst
.instruction
|= Rd
<< 8;
12606 inst
.instruction
|= Rs
<< 16;
12607 if (!inst
.operands
[2].isreg
)
12609 bfd_boolean narrow
;
12611 if ((inst
.instruction
& 0x00100000) != 0)
12612 narrow
= !in_it_block ();
12614 narrow
= in_it_block ();
12616 if (Rd
> 7 || Rs
> 7)
12619 if (inst
.size_req
== 4 || !unified_syntax
)
12622 if (inst
.reloc
.exp
.X_op
!= O_constant
12623 || inst
.reloc
.exp
.X_add_number
!= 0)
12626 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12627 relaxation, but it doesn't seem worth the hassle. */
12630 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12631 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12632 inst
.instruction
|= Rs
<< 3;
12633 inst
.instruction
|= Rd
;
12637 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12638 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12642 encode_thumb32_shifted_operand (2);
12648 if (warn_on_deprecated
12649 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12650 as_tsktsk (_("setend use is deprecated for ARMv8"));
12652 set_it_insn_type (OUTSIDE_IT_INSN
);
12653 if (inst
.operands
[0].imm
)
12654 inst
.instruction
|= 0x8;
12660 if (!inst
.operands
[1].present
)
12661 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12663 if (unified_syntax
)
12665 bfd_boolean narrow
;
12668 switch (inst
.instruction
)
12671 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12673 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12675 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12677 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12681 if (THUMB_SETS_FLAGS (inst
.instruction
))
12682 narrow
= !in_it_block ();
12684 narrow
= in_it_block ();
12685 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12687 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12689 if (inst
.operands
[2].isreg
12690 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12691 || inst
.operands
[2].reg
> 7))
12693 if (inst
.size_req
== 4)
12696 reject_bad_reg (inst
.operands
[0].reg
);
12697 reject_bad_reg (inst
.operands
[1].reg
);
12701 if (inst
.operands
[2].isreg
)
12703 reject_bad_reg (inst
.operands
[2].reg
);
12704 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12705 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12706 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12707 inst
.instruction
|= inst
.operands
[2].reg
;
12709 /* PR 12854: Error on extraneous shifts. */
12710 constraint (inst
.operands
[2].shifted
,
12711 _("extraneous shift as part of operand to shift insn"));
12715 inst
.operands
[1].shifted
= 1;
12716 inst
.operands
[1].shift_kind
= shift_kind
;
12717 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12718 ? T_MNEM_movs
: T_MNEM_mov
);
12719 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12720 encode_thumb32_shifted_operand (1);
12721 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12722 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12727 if (inst
.operands
[2].isreg
)
12729 switch (shift_kind
)
12731 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12732 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12733 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12734 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12738 inst
.instruction
|= inst
.operands
[0].reg
;
12739 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12741 /* PR 12854: Error on extraneous shifts. */
12742 constraint (inst
.operands
[2].shifted
,
12743 _("extraneous shift as part of operand to shift insn"));
12747 switch (shift_kind
)
12749 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12750 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12751 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12754 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12755 inst
.instruction
|= inst
.operands
[0].reg
;
12756 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12762 constraint (inst
.operands
[0].reg
> 7
12763 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12764 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12766 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12768 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12769 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12770 _("source1 and dest must be same register"));
12772 switch (inst
.instruction
)
12774 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12775 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12776 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12777 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12781 inst
.instruction
|= inst
.operands
[0].reg
;
12782 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12784 /* PR 12854: Error on extraneous shifts. */
12785 constraint (inst
.operands
[2].shifted
,
12786 _("extraneous shift as part of operand to shift insn"));
12790 switch (inst
.instruction
)
12792 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12793 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12794 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12795 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12798 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12799 inst
.instruction
|= inst
.operands
[0].reg
;
12800 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12808 unsigned Rd
, Rn
, Rm
;
12810 Rd
= inst
.operands
[0].reg
;
12811 Rn
= inst
.operands
[1].reg
;
12812 Rm
= inst
.operands
[2].reg
;
12814 reject_bad_reg (Rd
);
12815 reject_bad_reg (Rn
);
12816 reject_bad_reg (Rm
);
12818 inst
.instruction
|= Rd
<< 8;
12819 inst
.instruction
|= Rn
<< 16;
12820 inst
.instruction
|= Rm
;
12826 unsigned Rd
, Rn
, Rm
;
12828 Rd
= inst
.operands
[0].reg
;
12829 Rm
= inst
.operands
[1].reg
;
12830 Rn
= inst
.operands
[2].reg
;
12832 reject_bad_reg (Rd
);
12833 reject_bad_reg (Rn
);
12834 reject_bad_reg (Rm
);
12836 inst
.instruction
|= Rd
<< 8;
12837 inst
.instruction
|= Rn
<< 16;
12838 inst
.instruction
|= Rm
;
12844 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12846 _("SMC is not permitted on this architecture"));
12847 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12848 _("expression too complex"));
12849 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12850 inst
.instruction
|= (value
& 0xf000) >> 12;
12851 inst
.instruction
|= (value
& 0x0ff0);
12852 inst
.instruction
|= (value
& 0x000f) << 16;
12853 /* PR gas/15623: SMC instructions must be last in an IT block. */
12854 set_it_insn_type_last ();
12860 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12862 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12863 inst
.instruction
|= (value
& 0x0fff);
12864 inst
.instruction
|= (value
& 0xf000) << 4;
12868 do_t_ssat_usat (int bias
)
12872 Rd
= inst
.operands
[0].reg
;
12873 Rn
= inst
.operands
[2].reg
;
12875 reject_bad_reg (Rd
);
12876 reject_bad_reg (Rn
);
12878 inst
.instruction
|= Rd
<< 8;
12879 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12880 inst
.instruction
|= Rn
<< 16;
12882 if (inst
.operands
[3].present
)
12884 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12886 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12888 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12889 _("expression too complex"));
12891 if (shift_amount
!= 0)
12893 constraint (shift_amount
> 31,
12894 _("shift expression is too large"));
12896 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12897 inst
.instruction
|= 0x00200000; /* sh bit. */
12899 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12900 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12908 do_t_ssat_usat (1);
12916 Rd
= inst
.operands
[0].reg
;
12917 Rn
= inst
.operands
[2].reg
;
12919 reject_bad_reg (Rd
);
12920 reject_bad_reg (Rn
);
12922 inst
.instruction
|= Rd
<< 8;
12923 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12924 inst
.instruction
|= Rn
<< 16;
12930 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12931 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12932 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12933 || inst
.operands
[2].negative
,
12936 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12938 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12939 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12940 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12941 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12947 if (!inst
.operands
[2].present
)
12948 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12950 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12951 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12952 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12955 inst
.instruction
|= inst
.operands
[0].reg
;
12956 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12957 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12958 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12964 unsigned Rd
, Rn
, Rm
;
12966 Rd
= inst
.operands
[0].reg
;
12967 Rn
= inst
.operands
[1].reg
;
12968 Rm
= inst
.operands
[2].reg
;
12970 reject_bad_reg (Rd
);
12971 reject_bad_reg (Rn
);
12972 reject_bad_reg (Rm
);
12974 inst
.instruction
|= Rd
<< 8;
12975 inst
.instruction
|= Rn
<< 16;
12976 inst
.instruction
|= Rm
;
12977 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12985 Rd
= inst
.operands
[0].reg
;
12986 Rm
= inst
.operands
[1].reg
;
12988 reject_bad_reg (Rd
);
12989 reject_bad_reg (Rm
);
12991 if (inst
.instruction
<= 0xffff
12992 && inst
.size_req
!= 4
12993 && Rd
<= 7 && Rm
<= 7
12994 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12996 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12997 inst
.instruction
|= Rd
;
12998 inst
.instruction
|= Rm
<< 3;
13000 else if (unified_syntax
)
13002 if (inst
.instruction
<= 0xffff)
13003 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13004 inst
.instruction
|= Rd
<< 8;
13005 inst
.instruction
|= Rm
;
13006 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13010 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13011 _("Thumb encoding does not support rotation"));
13012 constraint (1, BAD_HIREG
);
13019 /* We have to do the following check manually as ARM_EXT_OS only applies
13021 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13023 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13024 /* This only applies to the v6m howver, not later architectures. */
13025 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13026 as_bad (_("SVC is not permitted on this architecture"));
13027 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13030 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13039 half
= (inst
.instruction
& 0x10) != 0;
13040 set_it_insn_type_last ();
13041 constraint (inst
.operands
[0].immisreg
,
13042 _("instruction requires register index"));
13044 Rn
= inst
.operands
[0].reg
;
13045 Rm
= inst
.operands
[0].imm
;
13047 constraint (Rn
== REG_SP
, BAD_SP
);
13048 reject_bad_reg (Rm
);
13050 constraint (!half
&& inst
.operands
[0].shifted
,
13051 _("instruction does not allow shifted index"));
13052 inst
.instruction
|= (Rn
<< 16) | Rm
;
13058 if (!inst
.operands
[0].present
)
13059 inst
.operands
[0].imm
= 0;
13061 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13063 constraint (inst
.size_req
== 2,
13064 _("immediate value out of range"));
13065 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13066 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13067 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13071 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13072 inst
.instruction
|= inst
.operands
[0].imm
;
13075 set_it_insn_type (NEUTRAL_IT_INSN
);
13082 do_t_ssat_usat (0);
13090 Rd
= inst
.operands
[0].reg
;
13091 Rn
= inst
.operands
[2].reg
;
13093 reject_bad_reg (Rd
);
13094 reject_bad_reg (Rn
);
13096 inst
.instruction
|= Rd
<< 8;
13097 inst
.instruction
|= inst
.operands
[1].imm
;
13098 inst
.instruction
|= Rn
<< 16;
13101 /* Neon instruction encoder helpers. */
13103 /* Encodings for the different types for various Neon opcodes. */
13105 /* An "invalid" code for the following tables. */
13108 struct neon_tab_entry
13111 unsigned float_or_poly
;
13112 unsigned scalar_or_imm
;
13115 /* Map overloaded Neon opcodes to their respective encodings. */
13116 #define NEON_ENC_TAB \
13117 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13118 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13119 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13120 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13121 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13122 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13123 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13124 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13125 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13126 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13127 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13128 /* Register variants of the following two instructions are encoded as
13129 vcge / vcgt with the operands reversed. */ \
13130 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13131 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13132 X(vfma, N_INV, 0x0000c10, N_INV), \
13133 X(vfms, N_INV, 0x0200c10, N_INV), \
13134 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13135 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13136 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13137 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13138 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13139 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13140 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13141 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13142 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13143 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13144 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13145 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13146 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13147 X(vshl, 0x0000400, N_INV, 0x0800510), \
13148 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13149 X(vand, 0x0000110, N_INV, 0x0800030), \
13150 X(vbic, 0x0100110, N_INV, 0x0800030), \
13151 X(veor, 0x1000110, N_INV, N_INV), \
13152 X(vorn, 0x0300110, N_INV, 0x0800010), \
13153 X(vorr, 0x0200110, N_INV, 0x0800010), \
13154 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13155 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13156 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13157 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13158 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13159 X(vst1, 0x0000000, 0x0800000, N_INV), \
13160 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13161 X(vst2, 0x0000100, 0x0800100, N_INV), \
13162 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13163 X(vst3, 0x0000200, 0x0800200, N_INV), \
13164 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13165 X(vst4, 0x0000300, 0x0800300, N_INV), \
13166 X(vmovn, 0x1b20200, N_INV, N_INV), \
13167 X(vtrn, 0x1b20080, N_INV, N_INV), \
13168 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13169 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13170 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13171 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13172 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13173 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13174 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13175 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13176 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13177 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13178 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13179 X(vseleq, 0xe000a00, N_INV, N_INV), \
13180 X(vselvs, 0xe100a00, N_INV, N_INV), \
13181 X(vselge, 0xe200a00, N_INV, N_INV), \
13182 X(vselgt, 0xe300a00, N_INV, N_INV), \
13183 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13184 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13185 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13186 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13187 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13188 X(aes, 0x3b00300, N_INV, N_INV), \
13189 X(sha3op, 0x2000c00, N_INV, N_INV), \
13190 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13191 X(sha2op, 0x3ba0380, N_INV, N_INV)
13195 #define X(OPC,I,F,S) N_MNEM_##OPC
13200 static const struct neon_tab_entry neon_enc_tab
[] =
13202 #define X(OPC,I,F,S) { (I), (F), (S) }
13207 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13208 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13209 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13210 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13211 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13212 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13213 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13214 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13215 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13216 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13217 #define NEON_ENC_SINGLE_(X) \
13218 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13219 #define NEON_ENC_DOUBLE_(X) \
13220 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13221 #define NEON_ENC_FPV8_(X) \
13222 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13224 #define NEON_ENCODE(type, inst) \
13227 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13228 inst.is_neon = 1; \
13232 #define check_neon_suffixes \
13235 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13237 as_bad (_("invalid neon suffix for non neon instruction")); \
13243 /* Define shapes for instruction operands. The following mnemonic characters
13244 are used in this table:
13246 F - VFP S<n> register
13247 D - Neon D<n> register
13248 Q - Neon Q<n> register
13252 L - D<n> register list
13254 This table is used to generate various data:
13255 - enumerations of the form NS_DDR to be used as arguments to
13257 - a table classifying shapes into single, double, quad, mixed.
13258 - a table used to drive neon_select_shape. */
13260 #define NEON_SHAPE_DEF \
13261 X(3, (D, D, D), DOUBLE), \
13262 X(3, (Q, Q, Q), QUAD), \
13263 X(3, (D, D, I), DOUBLE), \
13264 X(3, (Q, Q, I), QUAD), \
13265 X(3, (D, D, S), DOUBLE), \
13266 X(3, (Q, Q, S), QUAD), \
13267 X(2, (D, D), DOUBLE), \
13268 X(2, (Q, Q), QUAD), \
13269 X(2, (D, S), DOUBLE), \
13270 X(2, (Q, S), QUAD), \
13271 X(2, (D, R), DOUBLE), \
13272 X(2, (Q, R), QUAD), \
13273 X(2, (D, I), DOUBLE), \
13274 X(2, (Q, I), QUAD), \
13275 X(3, (D, L, D), DOUBLE), \
13276 X(2, (D, Q), MIXED), \
13277 X(2, (Q, D), MIXED), \
13278 X(3, (D, Q, I), MIXED), \
13279 X(3, (Q, D, I), MIXED), \
13280 X(3, (Q, D, D), MIXED), \
13281 X(3, (D, Q, Q), MIXED), \
13282 X(3, (Q, Q, D), MIXED), \
13283 X(3, (Q, D, S), MIXED), \
13284 X(3, (D, Q, S), MIXED), \
13285 X(4, (D, D, D, I), DOUBLE), \
13286 X(4, (Q, Q, Q, I), QUAD), \
13287 X(2, (F, F), SINGLE), \
13288 X(3, (F, F, F), SINGLE), \
13289 X(2, (F, I), SINGLE), \
13290 X(2, (F, D), MIXED), \
13291 X(2, (D, F), MIXED), \
13292 X(3, (F, F, I), MIXED), \
13293 X(4, (R, R, F, F), SINGLE), \
13294 X(4, (F, F, R, R), SINGLE), \
13295 X(3, (D, R, R), DOUBLE), \
13296 X(3, (R, R, D), DOUBLE), \
13297 X(2, (S, R), SINGLE), \
13298 X(2, (R, S), SINGLE), \
13299 X(2, (F, R), SINGLE), \
13300 X(2, (R, F), SINGLE), \
13301 /* Half float shape supported so far. */\
13302 X (2, (H, D), MIXED), \
13303 X (2, (D, H), MIXED), \
13304 X (2, (H, F), MIXED), \
13305 X (2, (F, H), MIXED), \
13306 X (2, (H, H), HALF), \
13307 X (2, (H, R), HALF), \
13308 X (2, (R, H), HALF), \
13309 X (2, (H, I), HALF), \
13310 X (3, (H, H, H), HALF), \
13311 X (3, (H, F, I), MIXED), \
13312 X (3, (F, H, I), MIXED)
13314 #define S2(A,B) NS_##A##B
13315 #define S3(A,B,C) NS_##A##B##C
13316 #define S4(A,B,C,D) NS_##A##B##C##D
13318 #define X(N, L, C) S##N L
13331 enum neon_shape_class
13340 #define X(N, L, C) SC_##C
13342 static enum neon_shape_class neon_shape_class
[] =
13361 /* Register widths of above. */
13362 static unsigned neon_shape_el_size
[] =
13374 struct neon_shape_info
13377 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13380 #define S2(A,B) { SE_##A, SE_##B }
13381 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13382 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13384 #define X(N, L, C) { N, S##N L }
13386 static struct neon_shape_info neon_shape_tab
[] =
13396 /* Bit masks used in type checking given instructions.
13397 'N_EQK' means the type must be the same as (or based on in some way) the key
13398 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13399 set, various other bits can be set as well in order to modify the meaning of
13400 the type constraint. */
13402 enum neon_type_mask
13426 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13427 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13428 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13429 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13430 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13431 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13432 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13433 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13434 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13435 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13436 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13438 N_MAX_NONSPECIAL
= N_P64
13441 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13443 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13444 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13445 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13446 #define N_S_32 (N_S8 | N_S16 | N_S32)
13447 #define N_F_16_32 (N_F16 | N_F32)
13448 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13449 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13450 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13451 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13453 /* Pass this as the first type argument to neon_check_type to ignore types
13455 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13457 /* Select a "shape" for the current instruction (describing register types or
13458 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13459 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13460 function of operand parsing, so this function doesn't need to be called.
13461 Shapes should be listed in order of decreasing length. */
13463 static enum neon_shape
13464 neon_select_shape (enum neon_shape shape
, ...)
13467 enum neon_shape first_shape
= shape
;
13469 /* Fix missing optional operands. FIXME: we don't know at this point how
13470 many arguments we should have, so this makes the assumption that we have
13471 > 1. This is true of all current Neon opcodes, I think, but may not be
13472 true in the future. */
13473 if (!inst
.operands
[1].present
)
13474 inst
.operands
[1] = inst
.operands
[0];
13476 va_start (ap
, shape
);
13478 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13483 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13485 if (!inst
.operands
[j
].present
)
13491 switch (neon_shape_tab
[shape
].el
[j
])
13493 /* If a .f16, .16, .u16, .s16 type specifier is given over
13494 a VFP single precision register operand, it's essentially
13495 means only half of the register is used.
13497 If the type specifier is given after the mnemonics, the
13498 information is stored in inst.vectype. If the type specifier
13499 is given after register operand, the information is stored
13500 in inst.operands[].vectype.
13502 When there is only one type specifier, and all the register
13503 operands are the same type of hardware register, the type
13504 specifier applies to all register operands.
13506 If no type specifier is given, the shape is inferred from
13507 operand information.
13510 vadd.f16 s0, s1, s2: NS_HHH
13511 vabs.f16 s0, s1: NS_HH
13512 vmov.f16 s0, r1: NS_HR
13513 vmov.f16 r0, s1: NS_RH
13514 vcvt.f16 r0, s1: NS_RH
13515 vcvt.f16.s32 s2, s2, #29: NS_HFI
13516 vcvt.f16.s32 s2, s2: NS_HF
13519 if (!(inst
.operands
[j
].isreg
13520 && inst
.operands
[j
].isvec
13521 && inst
.operands
[j
].issingle
13522 && !inst
.operands
[j
].isquad
13523 && ((inst
.vectype
.elems
== 1
13524 && inst
.vectype
.el
[0].size
== 16)
13525 || (inst
.vectype
.elems
> 1
13526 && inst
.vectype
.el
[j
].size
== 16)
13527 || (inst
.vectype
.elems
== 0
13528 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13529 && inst
.operands
[j
].vectype
.size
== 16))))
13534 if (!(inst
.operands
[j
].isreg
13535 && inst
.operands
[j
].isvec
13536 && inst
.operands
[j
].issingle
13537 && !inst
.operands
[j
].isquad
13538 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13539 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13540 || (inst
.vectype
.elems
== 0
13541 && (inst
.operands
[j
].vectype
.size
== 32
13542 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13547 if (!(inst
.operands
[j
].isreg
13548 && inst
.operands
[j
].isvec
13549 && !inst
.operands
[j
].isquad
13550 && !inst
.operands
[j
].issingle
))
13555 if (!(inst
.operands
[j
].isreg
13556 && !inst
.operands
[j
].isvec
))
13561 if (!(inst
.operands
[j
].isreg
13562 && inst
.operands
[j
].isvec
13563 && inst
.operands
[j
].isquad
13564 && !inst
.operands
[j
].issingle
))
13569 if (!(!inst
.operands
[j
].isreg
13570 && !inst
.operands
[j
].isscalar
))
13575 if (!(!inst
.operands
[j
].isreg
13576 && inst
.operands
[j
].isscalar
))
13586 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13587 /* We've matched all the entries in the shape table, and we don't
13588 have any left over operands which have not been matched. */
13594 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13595 first_error (_("invalid instruction shape"));
13600 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13601 means the Q bit should be set). */
13604 neon_quad (enum neon_shape shape
)
13606 return neon_shape_class
[shape
] == SC_QUAD
;
13610 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13613 /* Allow modification to be made to types which are constrained to be
13614 based on the key element, based on bits set alongside N_EQK. */
13615 if ((typebits
& N_EQK
) != 0)
13617 if ((typebits
& N_HLF
) != 0)
13619 else if ((typebits
& N_DBL
) != 0)
13621 if ((typebits
& N_SGN
) != 0)
13622 *g_type
= NT_signed
;
13623 else if ((typebits
& N_UNS
) != 0)
13624 *g_type
= NT_unsigned
;
13625 else if ((typebits
& N_INT
) != 0)
13626 *g_type
= NT_integer
;
13627 else if ((typebits
& N_FLT
) != 0)
13628 *g_type
= NT_float
;
13629 else if ((typebits
& N_SIZ
) != 0)
13630 *g_type
= NT_untyped
;
13634 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13635 operand type, i.e. the single type specified in a Neon instruction when it
13636 is the only one given. */
13638 static struct neon_type_el
13639 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13641 struct neon_type_el dest
= *key
;
13643 gas_assert ((thisarg
& N_EQK
) != 0);
13645 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13650 /* Convert Neon type and size into compact bitmask representation. */
13652 static enum neon_type_mask
13653 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13660 case 8: return N_8
;
13661 case 16: return N_16
;
13662 case 32: return N_32
;
13663 case 64: return N_64
;
13671 case 8: return N_I8
;
13672 case 16: return N_I16
;
13673 case 32: return N_I32
;
13674 case 64: return N_I64
;
13682 case 16: return N_F16
;
13683 case 32: return N_F32
;
13684 case 64: return N_F64
;
13692 case 8: return N_P8
;
13693 case 16: return N_P16
;
13694 case 64: return N_P64
;
13702 case 8: return N_S8
;
13703 case 16: return N_S16
;
13704 case 32: return N_S32
;
13705 case 64: return N_S64
;
13713 case 8: return N_U8
;
13714 case 16: return N_U16
;
13715 case 32: return N_U32
;
13716 case 64: return N_U64
;
13727 /* Convert compact Neon bitmask type representation to a type and size. Only
13728 handles the case where a single bit is set in the mask. */
13731 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13732 enum neon_type_mask mask
)
13734 if ((mask
& N_EQK
) != 0)
13737 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13739 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13741 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13743 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13748 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13750 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13751 *type
= NT_unsigned
;
13752 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13753 *type
= NT_integer
;
13754 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13755 *type
= NT_untyped
;
13756 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13758 else if ((mask
& (N_F_ALL
)) != 0)
13766 /* Modify a bitmask of allowed types. This is only needed for type
13770 modify_types_allowed (unsigned allowed
, unsigned mods
)
13773 enum neon_el_type type
;
13779 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13781 if (el_type_of_type_chk (&type
, &size
,
13782 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13784 neon_modify_type_size (mods
, &type
, &size
);
13785 destmask
|= type_chk_of_el_type (type
, size
);
13792 /* Check type and return type classification.
13793 The manual states (paraphrase): If one datatype is given, it indicates the
13795 - the second operand, if there is one
13796 - the operand, if there is no second operand
13797 - the result, if there are no operands.
13798 This isn't quite good enough though, so we use a concept of a "key" datatype
13799 which is set on a per-instruction basis, which is the one which matters when
13800 only one data type is written.
13801 Note: this function has side-effects (e.g. filling in missing operands). All
13802 Neon instructions should call it before performing bit encoding. */
13804 static struct neon_type_el
13805 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13808 unsigned i
, pass
, key_el
= 0;
13809 unsigned types
[NEON_MAX_TYPE_ELS
];
13810 enum neon_el_type k_type
= NT_invtype
;
13811 unsigned k_size
= -1u;
13812 struct neon_type_el badtype
= {NT_invtype
, -1};
13813 unsigned key_allowed
= 0;
13815 /* Optional registers in Neon instructions are always (not) in operand 1.
13816 Fill in the missing operand here, if it was omitted. */
13817 if (els
> 1 && !inst
.operands
[1].present
)
13818 inst
.operands
[1] = inst
.operands
[0];
13820 /* Suck up all the varargs. */
13822 for (i
= 0; i
< els
; i
++)
13824 unsigned thisarg
= va_arg (ap
, unsigned);
13825 if (thisarg
== N_IGNORE_TYPE
)
13830 types
[i
] = thisarg
;
13831 if ((thisarg
& N_KEY
) != 0)
13836 if (inst
.vectype
.elems
> 0)
13837 for (i
= 0; i
< els
; i
++)
13838 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13840 first_error (_("types specified in both the mnemonic and operands"));
13844 /* Duplicate inst.vectype elements here as necessary.
13845 FIXME: No idea if this is exactly the same as the ARM assembler,
13846 particularly when an insn takes one register and one non-register
13848 if (inst
.vectype
.elems
== 1 && els
> 1)
13851 inst
.vectype
.elems
= els
;
13852 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13853 for (j
= 0; j
< els
; j
++)
13855 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13858 else if (inst
.vectype
.elems
== 0 && els
> 0)
13861 /* No types were given after the mnemonic, so look for types specified
13862 after each operand. We allow some flexibility here; as long as the
13863 "key" operand has a type, we can infer the others. */
13864 for (j
= 0; j
< els
; j
++)
13865 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13866 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13868 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13870 for (j
= 0; j
< els
; j
++)
13871 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13872 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13877 first_error (_("operand types can't be inferred"));
13881 else if (inst
.vectype
.elems
!= els
)
13883 first_error (_("type specifier has the wrong number of parts"));
13887 for (pass
= 0; pass
< 2; pass
++)
13889 for (i
= 0; i
< els
; i
++)
13891 unsigned thisarg
= types
[i
];
13892 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13893 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13894 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13895 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13897 /* Decay more-specific signed & unsigned types to sign-insensitive
13898 integer types if sign-specific variants are unavailable. */
13899 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13900 && (types_allowed
& N_SU_ALL
) == 0)
13901 g_type
= NT_integer
;
13903 /* If only untyped args are allowed, decay any more specific types to
13904 them. Some instructions only care about signs for some element
13905 sizes, so handle that properly. */
13906 if (((types_allowed
& N_UNT
) == 0)
13907 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13908 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13909 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13910 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13911 g_type
= NT_untyped
;
13915 if ((thisarg
& N_KEY
) != 0)
13919 key_allowed
= thisarg
& ~N_KEY
;
13921 /* Check architecture constraint on FP16 extension. */
13923 && k_type
== NT_float
13924 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13926 inst
.error
= _(BAD_FP16
);
13933 if ((thisarg
& N_VFP
) != 0)
13935 enum neon_shape_el regshape
;
13936 unsigned regwidth
, match
;
13938 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13941 first_error (_("invalid instruction shape"));
13944 regshape
= neon_shape_tab
[ns
].el
[i
];
13945 regwidth
= neon_shape_el_size
[regshape
];
13947 /* In VFP mode, operands must match register widths. If we
13948 have a key operand, use its width, else use the width of
13949 the current operand. */
13955 /* FP16 will use a single precision register. */
13956 if (regwidth
== 32 && match
== 16)
13958 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13962 inst
.error
= _(BAD_FP16
);
13967 if (regwidth
!= match
)
13969 first_error (_("operand size must match register width"));
13974 if ((thisarg
& N_EQK
) == 0)
13976 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13978 if ((given_type
& types_allowed
) == 0)
13980 first_error (_("bad type in Neon instruction"));
13986 enum neon_el_type mod_k_type
= k_type
;
13987 unsigned mod_k_size
= k_size
;
13988 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13989 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13991 first_error (_("inconsistent types in Neon instruction"));
13999 return inst
.vectype
.el
[key_el
];
14002 /* Neon-style VFP instruction forwarding. */
14004 /* Thumb VFP instructions have 0xE in the condition field. */
14007 do_vfp_cond_or_thumb (void)
14012 inst
.instruction
|= 0xe0000000;
14014 inst
.instruction
|= inst
.cond
<< 28;
14017 /* Look up and encode a simple mnemonic, for use as a helper function for the
14018 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14019 etc. It is assumed that operand parsing has already been done, and that the
14020 operands are in the form expected by the given opcode (this isn't necessarily
14021 the same as the form in which they were parsed, hence some massaging must
14022 take place before this function is called).
14023 Checks current arch version against that in the looked-up opcode. */
14026 do_vfp_nsyn_opcode (const char *opname
)
14028 const struct asm_opcode
*opcode
;
14030 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14035 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14036 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14043 inst
.instruction
= opcode
->tvalue
;
14044 opcode
->tencode ();
14048 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14049 opcode
->aencode ();
14054 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14056 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14058 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14061 do_vfp_nsyn_opcode ("fadds");
14063 do_vfp_nsyn_opcode ("fsubs");
14065 /* ARMv8.2 fp16 instruction. */
14067 do_scalar_fp16_v82_encode ();
14072 do_vfp_nsyn_opcode ("faddd");
14074 do_vfp_nsyn_opcode ("fsubd");
14078 /* Check operand types to see if this is a VFP instruction, and if so call
14082 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14084 enum neon_shape rs
;
14085 struct neon_type_el et
;
14090 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14091 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14095 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14096 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14097 N_F_ALL
| N_KEY
| N_VFP
);
14104 if (et
.type
!= NT_invtype
)
14115 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14117 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14119 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14122 do_vfp_nsyn_opcode ("fmacs");
14124 do_vfp_nsyn_opcode ("fnmacs");
14126 /* ARMv8.2 fp16 instruction. */
14128 do_scalar_fp16_v82_encode ();
14133 do_vfp_nsyn_opcode ("fmacd");
14135 do_vfp_nsyn_opcode ("fnmacd");
14140 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14142 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14144 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14147 do_vfp_nsyn_opcode ("ffmas");
14149 do_vfp_nsyn_opcode ("ffnmas");
14151 /* ARMv8.2 fp16 instruction. */
14153 do_scalar_fp16_v82_encode ();
14158 do_vfp_nsyn_opcode ("ffmad");
14160 do_vfp_nsyn_opcode ("ffnmad");
14165 do_vfp_nsyn_mul (enum neon_shape rs
)
14167 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14169 do_vfp_nsyn_opcode ("fmuls");
14171 /* ARMv8.2 fp16 instruction. */
14173 do_scalar_fp16_v82_encode ();
14176 do_vfp_nsyn_opcode ("fmuld");
14180 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14182 int is_neg
= (inst
.instruction
& 0x80) != 0;
14183 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14185 if (rs
== NS_FF
|| rs
== NS_HH
)
14188 do_vfp_nsyn_opcode ("fnegs");
14190 do_vfp_nsyn_opcode ("fabss");
14192 /* ARMv8.2 fp16 instruction. */
14194 do_scalar_fp16_v82_encode ();
14199 do_vfp_nsyn_opcode ("fnegd");
14201 do_vfp_nsyn_opcode ("fabsd");
14205 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14206 insns belong to Neon, and are handled elsewhere. */
14209 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14211 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14215 do_vfp_nsyn_opcode ("fldmdbs");
14217 do_vfp_nsyn_opcode ("fldmias");
14222 do_vfp_nsyn_opcode ("fstmdbs");
14224 do_vfp_nsyn_opcode ("fstmias");
14229 do_vfp_nsyn_sqrt (void)
14231 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14232 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14234 if (rs
== NS_FF
|| rs
== NS_HH
)
14236 do_vfp_nsyn_opcode ("fsqrts");
14238 /* ARMv8.2 fp16 instruction. */
14240 do_scalar_fp16_v82_encode ();
14243 do_vfp_nsyn_opcode ("fsqrtd");
14247 do_vfp_nsyn_div (void)
14249 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14250 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14251 N_F_ALL
| N_KEY
| N_VFP
);
14253 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14255 do_vfp_nsyn_opcode ("fdivs");
14257 /* ARMv8.2 fp16 instruction. */
14259 do_scalar_fp16_v82_encode ();
14262 do_vfp_nsyn_opcode ("fdivd");
14266 do_vfp_nsyn_nmul (void)
14268 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14269 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14270 N_F_ALL
| N_KEY
| N_VFP
);
14272 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14274 NEON_ENCODE (SINGLE
, inst
);
14275 do_vfp_sp_dyadic ();
14277 /* ARMv8.2 fp16 instruction. */
14279 do_scalar_fp16_v82_encode ();
14283 NEON_ENCODE (DOUBLE
, inst
);
14284 do_vfp_dp_rd_rn_rm ();
14286 do_vfp_cond_or_thumb ();
14291 do_vfp_nsyn_cmp (void)
14293 enum neon_shape rs
;
14294 if (inst
.operands
[1].isreg
)
14296 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14297 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14299 if (rs
== NS_FF
|| rs
== NS_HH
)
14301 NEON_ENCODE (SINGLE
, inst
);
14302 do_vfp_sp_monadic ();
14306 NEON_ENCODE (DOUBLE
, inst
);
14307 do_vfp_dp_rd_rm ();
14312 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14313 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14315 switch (inst
.instruction
& 0x0fffffff)
14318 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14321 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14327 if (rs
== NS_FI
|| rs
== NS_HI
)
14329 NEON_ENCODE (SINGLE
, inst
);
14330 do_vfp_sp_compare_z ();
14334 NEON_ENCODE (DOUBLE
, inst
);
14338 do_vfp_cond_or_thumb ();
14340 /* ARMv8.2 fp16 instruction. */
14341 if (rs
== NS_HI
|| rs
== NS_HH
)
14342 do_scalar_fp16_v82_encode ();
14346 nsyn_insert_sp (void)
14348 inst
.operands
[1] = inst
.operands
[0];
14349 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14350 inst
.operands
[0].reg
= REG_SP
;
14351 inst
.operands
[0].isreg
= 1;
14352 inst
.operands
[0].writeback
= 1;
14353 inst
.operands
[0].present
= 1;
14357 do_vfp_nsyn_push (void)
14360 if (inst
.operands
[1].issingle
)
14361 do_vfp_nsyn_opcode ("fstmdbs");
14363 do_vfp_nsyn_opcode ("fstmdbd");
14367 do_vfp_nsyn_pop (void)
14370 if (inst
.operands
[1].issingle
)
14371 do_vfp_nsyn_opcode ("fldmias");
14373 do_vfp_nsyn_opcode ("fldmiad");
14376 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14377 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14380 neon_dp_fixup (struct arm_it
* insn
)
14382 unsigned int i
= insn
->instruction
;
14387 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14398 insn
->instruction
= i
;
14401 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14405 neon_logbits (unsigned x
)
14407 return ffs (x
) - 4;
14410 #define LOW4(R) ((R) & 0xf)
14411 #define HI1(R) (((R) >> 4) & 1)
14413 /* Encode insns with bit pattern:
14415 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14416 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14418 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14419 different meaning for some instruction. */
14422 neon_three_same (int isquad
, int ubit
, int size
)
14424 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14425 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14426 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14427 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14428 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14429 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14430 inst
.instruction
|= (isquad
!= 0) << 6;
14431 inst
.instruction
|= (ubit
!= 0) << 24;
14433 inst
.instruction
|= neon_logbits (size
) << 20;
14435 neon_dp_fixup (&inst
);
14438 /* Encode instructions of the form:
14440 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14441 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14443 Don't write size if SIZE == -1. */
14446 neon_two_same (int qbit
, int ubit
, int size
)
14448 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14449 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14450 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14451 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14452 inst
.instruction
|= (qbit
!= 0) << 6;
14453 inst
.instruction
|= (ubit
!= 0) << 24;
14456 inst
.instruction
|= neon_logbits (size
) << 18;
14458 neon_dp_fixup (&inst
);
14461 /* Neon instruction encoders, in approximate order of appearance. */
14464 do_neon_dyadic_i_su (void)
14466 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14467 struct neon_type_el et
= neon_check_type (3, rs
,
14468 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14469 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14473 do_neon_dyadic_i64_su (void)
14475 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14476 struct neon_type_el et
= neon_check_type (3, rs
,
14477 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14478 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14482 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14485 unsigned size
= et
.size
>> 3;
14486 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14487 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14488 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14489 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14490 inst
.instruction
|= (isquad
!= 0) << 6;
14491 inst
.instruction
|= immbits
<< 16;
14492 inst
.instruction
|= (size
>> 3) << 7;
14493 inst
.instruction
|= (size
& 0x7) << 19;
14495 inst
.instruction
|= (uval
!= 0) << 24;
14497 neon_dp_fixup (&inst
);
14501 do_neon_shl_imm (void)
14503 if (!inst
.operands
[2].isreg
)
14505 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14506 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14507 int imm
= inst
.operands
[2].imm
;
14509 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14510 _("immediate out of range for shift"));
14511 NEON_ENCODE (IMMED
, inst
);
14512 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14516 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14517 struct neon_type_el et
= neon_check_type (3, rs
,
14518 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14521 /* VSHL/VQSHL 3-register variants have syntax such as:
14523 whereas other 3-register operations encoded by neon_three_same have
14526 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14528 tmp
= inst
.operands
[2].reg
;
14529 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14530 inst
.operands
[1].reg
= tmp
;
14531 NEON_ENCODE (INTEGER
, inst
);
14532 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14537 do_neon_qshl_imm (void)
14539 if (!inst
.operands
[2].isreg
)
14541 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14542 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14543 int imm
= inst
.operands
[2].imm
;
14545 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14546 _("immediate out of range for shift"));
14547 NEON_ENCODE (IMMED
, inst
);
14548 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14552 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14553 struct neon_type_el et
= neon_check_type (3, rs
,
14554 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14557 /* See note in do_neon_shl_imm. */
14558 tmp
= inst
.operands
[2].reg
;
14559 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14560 inst
.operands
[1].reg
= tmp
;
14561 NEON_ENCODE (INTEGER
, inst
);
14562 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14567 do_neon_rshl (void)
14569 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14570 struct neon_type_el et
= neon_check_type (3, rs
,
14571 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14574 tmp
= inst
.operands
[2].reg
;
14575 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14576 inst
.operands
[1].reg
= tmp
;
14577 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14581 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14583 /* Handle .I8 pseudo-instructions. */
14586 /* Unfortunately, this will make everything apart from zero out-of-range.
14587 FIXME is this the intended semantics? There doesn't seem much point in
14588 accepting .I8 if so. */
14589 immediate
|= immediate
<< 8;
14595 if (immediate
== (immediate
& 0x000000ff))
14597 *immbits
= immediate
;
14600 else if (immediate
== (immediate
& 0x0000ff00))
14602 *immbits
= immediate
>> 8;
14605 else if (immediate
== (immediate
& 0x00ff0000))
14607 *immbits
= immediate
>> 16;
14610 else if (immediate
== (immediate
& 0xff000000))
14612 *immbits
= immediate
>> 24;
14615 if ((immediate
& 0xffff) != (immediate
>> 16))
14616 goto bad_immediate
;
14617 immediate
&= 0xffff;
14620 if (immediate
== (immediate
& 0x000000ff))
14622 *immbits
= immediate
;
14625 else if (immediate
== (immediate
& 0x0000ff00))
14627 *immbits
= immediate
>> 8;
14632 first_error (_("immediate value out of range"));
14637 do_neon_logic (void)
14639 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14641 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14642 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14643 /* U bit and size field were set as part of the bitmask. */
14644 NEON_ENCODE (INTEGER
, inst
);
14645 neon_three_same (neon_quad (rs
), 0, -1);
14649 const int three_ops_form
= (inst
.operands
[2].present
14650 && !inst
.operands
[2].isreg
);
14651 const int immoperand
= (three_ops_form
? 2 : 1);
14652 enum neon_shape rs
= (three_ops_form
14653 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14654 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14655 struct neon_type_el et
= neon_check_type (2, rs
,
14656 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14657 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14661 if (et
.type
== NT_invtype
)
14664 if (three_ops_form
)
14665 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14666 _("first and second operands shall be the same register"));
14668 NEON_ENCODE (IMMED
, inst
);
14670 immbits
= inst
.operands
[immoperand
].imm
;
14673 /* .i64 is a pseudo-op, so the immediate must be a repeating
14675 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14676 inst
.operands
[immoperand
].reg
: 0))
14678 /* Set immbits to an invalid constant. */
14679 immbits
= 0xdeadbeef;
14686 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14690 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14694 /* Pseudo-instruction for VBIC. */
14695 neon_invert_size (&immbits
, 0, et
.size
);
14696 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14700 /* Pseudo-instruction for VORR. */
14701 neon_invert_size (&immbits
, 0, et
.size
);
14702 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14712 inst
.instruction
|= neon_quad (rs
) << 6;
14713 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14714 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14715 inst
.instruction
|= cmode
<< 8;
14716 neon_write_immbits (immbits
);
14718 neon_dp_fixup (&inst
);
14723 do_neon_bitfield (void)
14725 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14726 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14727 neon_three_same (neon_quad (rs
), 0, -1);
14731 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14734 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14735 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14737 if (et
.type
== NT_float
)
14739 NEON_ENCODE (FLOAT
, inst
);
14740 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14744 NEON_ENCODE (INTEGER
, inst
);
14745 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14750 do_neon_dyadic_if_su (void)
14752 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14756 do_neon_dyadic_if_su_d (void)
14758 /* This version only allow D registers, but that constraint is enforced during
14759 operand parsing so we don't need to do anything extra here. */
14760 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14764 do_neon_dyadic_if_i_d (void)
14766 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14767 affected if we specify unsigned args. */
14768 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14771 enum vfp_or_neon_is_neon_bits
14774 NEON_CHECK_ARCH
= 2,
14775 NEON_CHECK_ARCH8
= 4
14778 /* Call this function if an instruction which may have belonged to the VFP or
14779 Neon instruction sets, but turned out to be a Neon instruction (due to the
14780 operand types involved, etc.). We have to check and/or fix-up a couple of
14783 - Make sure the user hasn't attempted to make a Neon instruction
14785 - Alter the value in the condition code field if necessary.
14786 - Make sure that the arch supports Neon instructions.
14788 Which of these operations take place depends on bits from enum
14789 vfp_or_neon_is_neon_bits.
14791 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14792 current instruction's condition is COND_ALWAYS, the condition field is
14793 changed to inst.uncond_value. This is necessary because instructions shared
14794 between VFP and Neon may be conditional for the VFP variants only, and the
14795 unconditional Neon version must have, e.g., 0xF in the condition field. */
14798 vfp_or_neon_is_neon (unsigned check
)
14800 /* Conditions are always legal in Thumb mode (IT blocks). */
14801 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14803 if (inst
.cond
!= COND_ALWAYS
)
14805 first_error (_(BAD_COND
));
14808 if (inst
.uncond_value
!= -1)
14809 inst
.instruction
|= inst
.uncond_value
<< 28;
14812 if ((check
& NEON_CHECK_ARCH
)
14813 && !mark_feature_used (&fpu_neon_ext_v1
))
14815 first_error (_(BAD_FPU
));
14819 if ((check
& NEON_CHECK_ARCH8
)
14820 && !mark_feature_used (&fpu_neon_ext_armv8
))
14822 first_error (_(BAD_FPU
));
14830 do_neon_addsub_if_i (void)
14832 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14835 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14838 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14839 affected if we specify unsigned args. */
14840 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14843 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14845 V<op> A,B (A is operand 0, B is operand 2)
14850 so handle that case specially. */
14853 neon_exchange_operands (void)
14855 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14856 if (inst
.operands
[1].present
)
14858 /* Swap operands[1] and operands[2]. */
14859 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14860 inst
.operands
[1] = inst
.operands
[2];
14861 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14865 inst
.operands
[1] = inst
.operands
[2];
14866 inst
.operands
[2] = inst
.operands
[0];
14871 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14873 if (inst
.operands
[2].isreg
)
14876 neon_exchange_operands ();
14877 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14881 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14882 struct neon_type_el et
= neon_check_type (2, rs
,
14883 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14885 NEON_ENCODE (IMMED
, inst
);
14886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14887 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14888 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14889 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14890 inst
.instruction
|= neon_quad (rs
) << 6;
14891 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14892 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14894 neon_dp_fixup (&inst
);
14901 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14905 do_neon_cmp_inv (void)
14907 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14913 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14916 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14917 scalars, which are encoded in 5 bits, M : Rm.
14918 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14919 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14923 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14925 unsigned regno
= NEON_SCALAR_REG (scalar
);
14926 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14931 if (regno
> 7 || elno
> 3)
14933 return regno
| (elno
<< 3);
14936 if (regno
> 15 || elno
> 1)
14938 return regno
| (elno
<< 4);
14942 first_error (_("scalar out of range for multiply instruction"));
14948 /* Encode multiply / multiply-accumulate scalar instructions. */
14951 neon_mul_mac (struct neon_type_el et
, int ubit
)
14955 /* Give a more helpful error message if we have an invalid type. */
14956 if (et
.type
== NT_invtype
)
14959 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14960 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14961 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14962 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14963 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14964 inst
.instruction
|= LOW4 (scalar
);
14965 inst
.instruction
|= HI1 (scalar
) << 5;
14966 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14967 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14968 inst
.instruction
|= (ubit
!= 0) << 24;
14970 neon_dp_fixup (&inst
);
14974 do_neon_mac_maybe_scalar (void)
14976 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14979 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14982 if (inst
.operands
[2].isscalar
)
14984 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14985 struct neon_type_el et
= neon_check_type (3, rs
,
14986 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14987 NEON_ENCODE (SCALAR
, inst
);
14988 neon_mul_mac (et
, neon_quad (rs
));
14992 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14993 affected if we specify unsigned args. */
14994 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14999 do_neon_fmac (void)
15001 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15004 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15007 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15013 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15014 struct neon_type_el et
= neon_check_type (3, rs
,
15015 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15016 neon_three_same (neon_quad (rs
), 0, et
.size
);
15019 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15020 same types as the MAC equivalents. The polynomial type for this instruction
15021 is encoded the same as the integer type. */
15026 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15029 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15032 if (inst
.operands
[2].isscalar
)
15033 do_neon_mac_maybe_scalar ();
15035 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15039 do_neon_qdmulh (void)
15041 if (inst
.operands
[2].isscalar
)
15043 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15044 struct neon_type_el et
= neon_check_type (3, rs
,
15045 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15046 NEON_ENCODE (SCALAR
, inst
);
15047 neon_mul_mac (et
, neon_quad (rs
));
15051 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15052 struct neon_type_el et
= neon_check_type (3, rs
,
15053 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15054 NEON_ENCODE (INTEGER
, inst
);
15055 /* The U bit (rounding) comes from bit mask. */
15056 neon_three_same (neon_quad (rs
), 0, et
.size
);
15061 do_neon_qrdmlah (void)
15063 /* Check we're on the correct architecture. */
15064 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15066 _("instruction form not available on this architecture.");
15067 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15069 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15070 record_feature_use (&fpu_neon_ext_v8_1
);
15073 if (inst
.operands
[2].isscalar
)
15075 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15076 struct neon_type_el et
= neon_check_type (3, rs
,
15077 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15078 NEON_ENCODE (SCALAR
, inst
);
15079 neon_mul_mac (et
, neon_quad (rs
));
15083 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15084 struct neon_type_el et
= neon_check_type (3, rs
,
15085 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15086 NEON_ENCODE (INTEGER
, inst
);
15087 /* The U bit (rounding) comes from bit mask. */
15088 neon_three_same (neon_quad (rs
), 0, et
.size
);
15093 do_neon_fcmp_absolute (void)
15095 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15096 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15097 N_F_16_32
| N_KEY
);
15098 /* Size field comes from bit mask. */
15099 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15103 do_neon_fcmp_absolute_inv (void)
15105 neon_exchange_operands ();
15106 do_neon_fcmp_absolute ();
15110 do_neon_step (void)
15112 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15113 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15114 N_F_16_32
| N_KEY
);
15115 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15119 do_neon_abs_neg (void)
15121 enum neon_shape rs
;
15122 struct neon_type_el et
;
15124 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15127 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15130 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15131 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15133 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15135 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15136 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15137 inst
.instruction
|= neon_quad (rs
) << 6;
15138 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15139 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15141 neon_dp_fixup (&inst
);
15147 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15148 struct neon_type_el et
= neon_check_type (2, rs
,
15149 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15150 int imm
= inst
.operands
[2].imm
;
15151 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15152 _("immediate out of range for insert"));
15153 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15159 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15160 struct neon_type_el et
= neon_check_type (2, rs
,
15161 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15162 int imm
= inst
.operands
[2].imm
;
15163 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15164 _("immediate out of range for insert"));
15165 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15169 do_neon_qshlu_imm (void)
15171 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15172 struct neon_type_el et
= neon_check_type (2, rs
,
15173 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15174 int imm
= inst
.operands
[2].imm
;
15175 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15176 _("immediate out of range for shift"));
15177 /* Only encodes the 'U present' variant of the instruction.
15178 In this case, signed types have OP (bit 8) set to 0.
15179 Unsigned types have OP set to 1. */
15180 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15181 /* The rest of the bits are the same as other immediate shifts. */
15182 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15186 do_neon_qmovn (void)
15188 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15189 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15190 /* Saturating move where operands can be signed or unsigned, and the
15191 destination has the same signedness. */
15192 NEON_ENCODE (INTEGER
, inst
);
15193 if (et
.type
== NT_unsigned
)
15194 inst
.instruction
|= 0xc0;
15196 inst
.instruction
|= 0x80;
15197 neon_two_same (0, 1, et
.size
/ 2);
15201 do_neon_qmovun (void)
15203 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15204 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15205 /* Saturating move with unsigned results. Operands must be signed. */
15206 NEON_ENCODE (INTEGER
, inst
);
15207 neon_two_same (0, 1, et
.size
/ 2);
15211 do_neon_rshift_sat_narrow (void)
15213 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15214 or unsigned. If operands are unsigned, results must also be unsigned. */
15215 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15216 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15217 int imm
= inst
.operands
[2].imm
;
15218 /* This gets the bounds check, size encoding and immediate bits calculation
15222 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15223 VQMOVN.I<size> <Dd>, <Qm>. */
15226 inst
.operands
[2].present
= 0;
15227 inst
.instruction
= N_MNEM_vqmovn
;
15232 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15233 _("immediate out of range"));
15234 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15238 do_neon_rshift_sat_narrow_u (void)
15240 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15241 or unsigned. If operands are unsigned, results must also be unsigned. */
15242 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15243 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15244 int imm
= inst
.operands
[2].imm
;
15245 /* This gets the bounds check, size encoding and immediate bits calculation
15249 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15250 VQMOVUN.I<size> <Dd>, <Qm>. */
15253 inst
.operands
[2].present
= 0;
15254 inst
.instruction
= N_MNEM_vqmovun
;
15259 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15260 _("immediate out of range"));
15261 /* FIXME: The manual is kind of unclear about what value U should have in
15262 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15264 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15268 do_neon_movn (void)
15270 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15271 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15272 NEON_ENCODE (INTEGER
, inst
);
15273 neon_two_same (0, 1, et
.size
/ 2);
15277 do_neon_rshift_narrow (void)
15279 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15280 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15281 int imm
= inst
.operands
[2].imm
;
15282 /* This gets the bounds check, size encoding and immediate bits calculation
15286 /* If immediate is zero then we are a pseudo-instruction for
15287 VMOVN.I<size> <Dd>, <Qm> */
15290 inst
.operands
[2].present
= 0;
15291 inst
.instruction
= N_MNEM_vmovn
;
15296 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15297 _("immediate out of range for narrowing operation"));
15298 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15302 do_neon_shll (void)
15304 /* FIXME: Type checking when lengthening. */
15305 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15306 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15307 unsigned imm
= inst
.operands
[2].imm
;
15309 if (imm
== et
.size
)
15311 /* Maximum shift variant. */
15312 NEON_ENCODE (INTEGER
, inst
);
15313 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15314 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15315 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15316 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15317 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15319 neon_dp_fixup (&inst
);
15323 /* A more-specific type check for non-max versions. */
15324 et
= neon_check_type (2, NS_QDI
,
15325 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15326 NEON_ENCODE (IMMED
, inst
);
15327 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15331 /* Check the various types for the VCVT instruction, and return which version
15332 the current instruction is. */
15334 #define CVT_FLAVOUR_VAR \
15335 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15336 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15337 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15338 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15339 /* Half-precision conversions. */ \
15340 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15341 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15342 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15343 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15344 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15345 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15346 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15347 Compared with single/double precision variants, only the co-processor \
15348 field is different, so the encoding flow is reused here. */ \
15349 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15350 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15351 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15352 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15353 /* VFP instructions. */ \
15354 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15355 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15356 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15357 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15358 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15359 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15360 /* VFP instructions with bitshift. */ \
15361 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15362 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15363 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15364 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15365 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15366 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15367 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15368 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15370 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15371 neon_cvt_flavour_##C,
15373 /* The different types of conversions we can do. */
15374 enum neon_cvt_flavour
15377 neon_cvt_flavour_invalid
,
15378 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15383 static enum neon_cvt_flavour
15384 get_neon_cvt_flavour (enum neon_shape rs
)
15386 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15387 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15388 if (et.type != NT_invtype) \
15390 inst.error = NULL; \
15391 return (neon_cvt_flavour_##C); \
15394 struct neon_type_el et
;
15395 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15396 || rs
== NS_FF
) ? N_VFP
: 0;
15397 /* The instruction versions which take an immediate take one register
15398 argument, which is extended to the width of the full register. Thus the
15399 "source" and "destination" registers must have the same width. Hack that
15400 here by making the size equal to the key (wider, in this case) operand. */
15401 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15405 return neon_cvt_flavour_invalid
;
15420 /* Neon-syntax VFP conversions. */
15423 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15425 const char *opname
= 0;
15427 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15428 || rs
== NS_FHI
|| rs
== NS_HFI
)
15430 /* Conversions with immediate bitshift. */
15431 const char *enc
[] =
15433 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15439 if (flavour
< (int) ARRAY_SIZE (enc
))
15441 opname
= enc
[flavour
];
15442 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15443 _("operands 0 and 1 must be the same register"));
15444 inst
.operands
[1] = inst
.operands
[2];
15445 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15450 /* Conversions without bitshift. */
15451 const char *enc
[] =
15453 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15459 if (flavour
< (int) ARRAY_SIZE (enc
))
15460 opname
= enc
[flavour
];
15464 do_vfp_nsyn_opcode (opname
);
15466 /* ARMv8.2 fp16 VCVT instruction. */
15467 if (flavour
== neon_cvt_flavour_s32_f16
15468 || flavour
== neon_cvt_flavour_u32_f16
15469 || flavour
== neon_cvt_flavour_f16_u32
15470 || flavour
== neon_cvt_flavour_f16_s32
)
15471 do_scalar_fp16_v82_encode ();
15475 do_vfp_nsyn_cvtz (void)
15477 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15478 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15479 const char *enc
[] =
15481 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15487 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15488 do_vfp_nsyn_opcode (enc
[flavour
]);
15492 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15493 enum neon_cvt_mode mode
)
15498 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15499 D register operands. */
15500 if (flavour
== neon_cvt_flavour_s32_f64
15501 || flavour
== neon_cvt_flavour_u32_f64
)
15502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15505 if (flavour
== neon_cvt_flavour_s32_f16
15506 || flavour
== neon_cvt_flavour_u32_f16
)
15507 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15510 set_it_insn_type (OUTSIDE_IT_INSN
);
15514 case neon_cvt_flavour_s32_f64
:
15518 case neon_cvt_flavour_s32_f32
:
15522 case neon_cvt_flavour_s32_f16
:
15526 case neon_cvt_flavour_u32_f64
:
15530 case neon_cvt_flavour_u32_f32
:
15534 case neon_cvt_flavour_u32_f16
:
15539 first_error (_("invalid instruction shape"));
15545 case neon_cvt_mode_a
: rm
= 0; break;
15546 case neon_cvt_mode_n
: rm
= 1; break;
15547 case neon_cvt_mode_p
: rm
= 2; break;
15548 case neon_cvt_mode_m
: rm
= 3; break;
15549 default: first_error (_("invalid rounding mode")); return;
15552 NEON_ENCODE (FPV8
, inst
);
15553 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15554 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15555 inst
.instruction
|= sz
<< 8;
15557 /* ARMv8.2 fp16 VCVT instruction. */
15558 if (flavour
== neon_cvt_flavour_s32_f16
15559 ||flavour
== neon_cvt_flavour_u32_f16
)
15560 do_scalar_fp16_v82_encode ();
15561 inst
.instruction
|= op
<< 7;
15562 inst
.instruction
|= rm
<< 16;
15563 inst
.instruction
|= 0xf0000000;
15564 inst
.is_neon
= TRUE
;
15568 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15570 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15571 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15572 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15574 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15576 if (flavour
== neon_cvt_flavour_invalid
)
15579 /* PR11109: Handle round-to-zero for VCVT conversions. */
15580 if (mode
== neon_cvt_mode_z
15581 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15582 && (flavour
== neon_cvt_flavour_s16_f16
15583 || flavour
== neon_cvt_flavour_u16_f16
15584 || flavour
== neon_cvt_flavour_s32_f32
15585 || flavour
== neon_cvt_flavour_u32_f32
15586 || flavour
== neon_cvt_flavour_s32_f64
15587 || flavour
== neon_cvt_flavour_u32_f64
)
15588 && (rs
== NS_FD
|| rs
== NS_FF
))
15590 do_vfp_nsyn_cvtz ();
15594 /* ARMv8.2 fp16 VCVT conversions. */
15595 if (mode
== neon_cvt_mode_z
15596 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15597 && (flavour
== neon_cvt_flavour_s32_f16
15598 || flavour
== neon_cvt_flavour_u32_f16
)
15601 do_vfp_nsyn_cvtz ();
15602 do_scalar_fp16_v82_encode ();
15606 /* VFP rather than Neon conversions. */
15607 if (flavour
>= neon_cvt_flavour_first_fp
)
15609 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15610 do_vfp_nsyn_cvt (rs
, flavour
);
15612 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15623 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15624 0x0000100, 0x1000100, 0x0, 0x1000000};
15626 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15629 /* Fixed-point conversion with #0 immediate is encoded as an
15630 integer conversion. */
15631 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15633 NEON_ENCODE (IMMED
, inst
);
15634 if (flavour
!= neon_cvt_flavour_invalid
)
15635 inst
.instruction
|= enctab
[flavour
];
15636 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15637 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15638 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15639 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15640 inst
.instruction
|= neon_quad (rs
) << 6;
15641 inst
.instruction
|= 1 << 21;
15642 if (flavour
< neon_cvt_flavour_s16_f16
)
15644 inst
.instruction
|= 1 << 21;
15645 immbits
= 32 - inst
.operands
[2].imm
;
15646 inst
.instruction
|= immbits
<< 16;
15650 inst
.instruction
|= 3 << 20;
15651 immbits
= 16 - inst
.operands
[2].imm
;
15652 inst
.instruction
|= immbits
<< 16;
15653 inst
.instruction
&= ~(1 << 9);
15656 neon_dp_fixup (&inst
);
15662 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15664 NEON_ENCODE (FLOAT
, inst
);
15665 set_it_insn_type (OUTSIDE_IT_INSN
);
15667 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15670 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15671 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15672 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15673 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15674 inst
.instruction
|= neon_quad (rs
) << 6;
15675 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15676 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15677 inst
.instruction
|= mode
<< 8;
15678 if (flavour
== neon_cvt_flavour_u16_f16
15679 || flavour
== neon_cvt_flavour_s16_f16
)
15680 /* Mask off the original size bits and reencode them. */
15681 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15684 inst
.instruction
|= 0xfc000000;
15686 inst
.instruction
|= 0xf0000000;
15692 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15693 0x100, 0x180, 0x0, 0x080};
15695 NEON_ENCODE (INTEGER
, inst
);
15697 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15700 if (flavour
!= neon_cvt_flavour_invalid
)
15701 inst
.instruction
|= enctab
[flavour
];
15703 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15704 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15705 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15706 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15707 inst
.instruction
|= neon_quad (rs
) << 6;
15708 if (flavour
>= neon_cvt_flavour_s16_f16
15709 && flavour
<= neon_cvt_flavour_f16_u16
)
15710 /* Half precision. */
15711 inst
.instruction
|= 1 << 18;
15713 inst
.instruction
|= 2 << 18;
15715 neon_dp_fixup (&inst
);
15720 /* Half-precision conversions for Advanced SIMD -- neon. */
15725 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15727 as_bad (_("operand size must match register width"));
15732 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15734 as_bad (_("operand size must match register width"));
15739 inst
.instruction
= 0x3b60600;
15741 inst
.instruction
= 0x3b60700;
15743 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15744 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15745 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15746 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15747 neon_dp_fixup (&inst
);
15751 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15752 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15753 do_vfp_nsyn_cvt (rs
, flavour
);
15755 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15760 do_neon_cvtr (void)
15762 do_neon_cvt_1 (neon_cvt_mode_x
);
15768 do_neon_cvt_1 (neon_cvt_mode_z
);
15772 do_neon_cvta (void)
15774 do_neon_cvt_1 (neon_cvt_mode_a
);
15778 do_neon_cvtn (void)
15780 do_neon_cvt_1 (neon_cvt_mode_n
);
15784 do_neon_cvtp (void)
15786 do_neon_cvt_1 (neon_cvt_mode_p
);
15790 do_neon_cvtm (void)
15792 do_neon_cvt_1 (neon_cvt_mode_m
);
15796 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15799 mark_feature_used (&fpu_vfp_ext_armv8
);
15801 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15802 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15803 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15804 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15805 inst
.instruction
|= to
? 0x10000 : 0;
15806 inst
.instruction
|= t
? 0x80 : 0;
15807 inst
.instruction
|= is_double
? 0x100 : 0;
15808 do_vfp_cond_or_thumb ();
15812 do_neon_cvttb_1 (bfd_boolean t
)
15814 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15815 NS_DF
, NS_DH
, NS_NULL
);
15819 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15822 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15824 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15827 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15829 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15831 /* The VCVTB and VCVTT instructions with D-register operands
15832 don't work for SP only targets. */
15833 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15837 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15839 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15841 /* The VCVTB and VCVTT instructions with D-register operands
15842 don't work for SP only targets. */
15843 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15847 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15854 do_neon_cvtb (void)
15856 do_neon_cvttb_1 (FALSE
);
15861 do_neon_cvtt (void)
15863 do_neon_cvttb_1 (TRUE
);
15867 neon_move_immediate (void)
15869 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15870 struct neon_type_el et
= neon_check_type (2, rs
,
15871 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15872 unsigned immlo
, immhi
= 0, immbits
;
15873 int op
, cmode
, float_p
;
15875 constraint (et
.type
== NT_invtype
,
15876 _("operand size must be specified for immediate VMOV"));
15878 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15879 op
= (inst
.instruction
& (1 << 5)) != 0;
15881 immlo
= inst
.operands
[1].imm
;
15882 if (inst
.operands
[1].regisimm
)
15883 immhi
= inst
.operands
[1].reg
;
15885 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15886 _("immediate has bits set outside the operand size"));
15888 float_p
= inst
.operands
[1].immisfloat
;
15890 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15891 et
.size
, et
.type
)) == FAIL
)
15893 /* Invert relevant bits only. */
15894 neon_invert_size (&immlo
, &immhi
, et
.size
);
15895 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15896 with one or the other; those cases are caught by
15897 neon_cmode_for_move_imm. */
15899 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15900 &op
, et
.size
, et
.type
)) == FAIL
)
15902 first_error (_("immediate out of range"));
15907 inst
.instruction
&= ~(1 << 5);
15908 inst
.instruction
|= op
<< 5;
15910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15911 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15912 inst
.instruction
|= neon_quad (rs
) << 6;
15913 inst
.instruction
|= cmode
<< 8;
15915 neon_write_immbits (immbits
);
15921 if (inst
.operands
[1].isreg
)
15923 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15925 NEON_ENCODE (INTEGER
, inst
);
15926 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15927 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15928 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15930 inst
.instruction
|= neon_quad (rs
) << 6;
15934 NEON_ENCODE (IMMED
, inst
);
15935 neon_move_immediate ();
15938 neon_dp_fixup (&inst
);
15941 /* Encode instructions of form:
15943 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15944 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15947 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15949 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15950 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15951 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15952 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15953 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15954 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15955 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15956 inst
.instruction
|= neon_logbits (size
) << 20;
15958 neon_dp_fixup (&inst
);
15962 do_neon_dyadic_long (void)
15964 /* FIXME: Type checking for lengthening op. */
15965 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15966 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15967 neon_mixed_length (et
, et
.size
);
15971 do_neon_abal (void)
15973 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15974 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15975 neon_mixed_length (et
, et
.size
);
15979 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15981 if (inst
.operands
[2].isscalar
)
15983 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15984 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15985 NEON_ENCODE (SCALAR
, inst
);
15986 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15990 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15991 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15992 NEON_ENCODE (INTEGER
, inst
);
15993 neon_mixed_length (et
, et
.size
);
15998 do_neon_mac_maybe_scalar_long (void)
16000 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16004 do_neon_dyadic_wide (void)
16006 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16007 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16008 neon_mixed_length (et
, et
.size
);
16012 do_neon_dyadic_narrow (void)
16014 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16015 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16016 /* Operand sign is unimportant, and the U bit is part of the opcode,
16017 so force the operand type to integer. */
16018 et
.type
= NT_integer
;
16019 neon_mixed_length (et
, et
.size
/ 2);
16023 do_neon_mul_sat_scalar_long (void)
16025 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16029 do_neon_vmull (void)
16031 if (inst
.operands
[2].isscalar
)
16032 do_neon_mac_maybe_scalar_long ();
16035 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16036 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16038 if (et
.type
== NT_poly
)
16039 NEON_ENCODE (POLY
, inst
);
16041 NEON_ENCODE (INTEGER
, inst
);
16043 /* For polynomial encoding the U bit must be zero, and the size must
16044 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16045 obviously, as 0b10). */
16048 /* Check we're on the correct architecture. */
16049 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16051 _("Instruction form not available on this architecture.");
16056 neon_mixed_length (et
, et
.size
);
16063 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16064 struct neon_type_el et
= neon_check_type (3, rs
,
16065 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16066 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16068 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16069 _("shift out of range"));
16070 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16071 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16072 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16073 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16074 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16075 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16076 inst
.instruction
|= neon_quad (rs
) << 6;
16077 inst
.instruction
|= imm
<< 8;
16079 neon_dp_fixup (&inst
);
16085 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16086 struct neon_type_el et
= neon_check_type (2, rs
,
16087 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16088 unsigned op
= (inst
.instruction
>> 7) & 3;
16089 /* N (width of reversed regions) is encoded as part of the bitmask. We
16090 extract it here to check the elements to be reversed are smaller.
16091 Otherwise we'd get a reserved instruction. */
16092 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16093 gas_assert (elsize
!= 0);
16094 constraint (et
.size
>= elsize
,
16095 _("elements must be smaller than reversal region"));
16096 neon_two_same (neon_quad (rs
), 1, et
.size
);
16102 if (inst
.operands
[1].isscalar
)
16104 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16105 struct neon_type_el et
= neon_check_type (2, rs
,
16106 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16107 unsigned sizebits
= et
.size
>> 3;
16108 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16109 int logsize
= neon_logbits (et
.size
);
16110 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16112 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16115 NEON_ENCODE (SCALAR
, inst
);
16116 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16118 inst
.instruction
|= LOW4 (dm
);
16119 inst
.instruction
|= HI1 (dm
) << 5;
16120 inst
.instruction
|= neon_quad (rs
) << 6;
16121 inst
.instruction
|= x
<< 17;
16122 inst
.instruction
|= sizebits
<< 16;
16124 neon_dp_fixup (&inst
);
16128 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16129 struct neon_type_el et
= neon_check_type (2, rs
,
16130 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16131 /* Duplicate ARM register to lanes of vector. */
16132 NEON_ENCODE (ARMREG
, inst
);
16135 case 8: inst
.instruction
|= 0x400000; break;
16136 case 16: inst
.instruction
|= 0x000020; break;
16137 case 32: inst
.instruction
|= 0x000000; break;
16140 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16141 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16142 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16143 inst
.instruction
|= neon_quad (rs
) << 21;
16144 /* The encoding for this instruction is identical for the ARM and Thumb
16145 variants, except for the condition field. */
16146 do_vfp_cond_or_thumb ();
16150 /* VMOV has particularly many variations. It can be one of:
16151 0. VMOV<c><q> <Qd>, <Qm>
16152 1. VMOV<c><q> <Dd>, <Dm>
16153 (Register operations, which are VORR with Rm = Rn.)
16154 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16155 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16157 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16158 (ARM register to scalar.)
16159 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16160 (Two ARM registers to vector.)
16161 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16162 (Scalar to ARM register.)
16163 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16164 (Vector to two ARM registers.)
16165 8. VMOV.F32 <Sd>, <Sm>
16166 9. VMOV.F64 <Dd>, <Dm>
16167 (VFP register moves.)
16168 10. VMOV.F32 <Sd>, #imm
16169 11. VMOV.F64 <Dd>, #imm
16170 (VFP float immediate load.)
16171 12. VMOV <Rd>, <Sm>
16172 (VFP single to ARM reg.)
16173 13. VMOV <Sd>, <Rm>
16174 (ARM reg to VFP single.)
16175 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16176 (Two ARM regs to two VFP singles.)
16177 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16178 (Two VFP singles to two ARM regs.)
16180 These cases can be disambiguated using neon_select_shape, except cases 1/9
16181 and 3/11 which depend on the operand type too.
16183 All the encoded bits are hardcoded by this function.
16185 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16186 Cases 5, 7 may be used with VFPv2 and above.
16188 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16189 can specify a type where it doesn't make sense to, and is ignored). */
16194 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16195 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16196 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16197 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16198 struct neon_type_el et
;
16199 const char *ldconst
= 0;
16203 case NS_DD
: /* case 1/9. */
16204 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16205 /* It is not an error here if no type is given. */
16207 if (et
.type
== NT_float
&& et
.size
== 64)
16209 do_vfp_nsyn_opcode ("fcpyd");
16212 /* fall through. */
16214 case NS_QQ
: /* case 0/1. */
16216 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16218 /* The architecture manual I have doesn't explicitly state which
16219 value the U bit should have for register->register moves, but
16220 the equivalent VORR instruction has U = 0, so do that. */
16221 inst
.instruction
= 0x0200110;
16222 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16223 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16224 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16225 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16226 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16227 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16228 inst
.instruction
|= neon_quad (rs
) << 6;
16230 neon_dp_fixup (&inst
);
16234 case NS_DI
: /* case 3/11. */
16235 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16237 if (et
.type
== NT_float
&& et
.size
== 64)
16239 /* case 11 (fconstd). */
16240 ldconst
= "fconstd";
16241 goto encode_fconstd
;
16243 /* fall through. */
16245 case NS_QI
: /* case 2/3. */
16246 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16248 inst
.instruction
= 0x0800010;
16249 neon_move_immediate ();
16250 neon_dp_fixup (&inst
);
16253 case NS_SR
: /* case 4. */
16255 unsigned bcdebits
= 0;
16257 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16258 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16260 /* .<size> is optional here, defaulting to .32. */
16261 if (inst
.vectype
.elems
== 0
16262 && inst
.operands
[0].vectype
.type
== NT_invtype
16263 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16265 inst
.vectype
.el
[0].type
= NT_untyped
;
16266 inst
.vectype
.el
[0].size
= 32;
16267 inst
.vectype
.elems
= 1;
16270 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16271 logsize
= neon_logbits (et
.size
);
16273 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16275 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16276 && et
.size
!= 32, _(BAD_FPU
));
16277 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16278 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16282 case 8: bcdebits
= 0x8; break;
16283 case 16: bcdebits
= 0x1; break;
16284 case 32: bcdebits
= 0x0; break;
16288 bcdebits
|= x
<< logsize
;
16290 inst
.instruction
= 0xe000b10;
16291 do_vfp_cond_or_thumb ();
16292 inst
.instruction
|= LOW4 (dn
) << 16;
16293 inst
.instruction
|= HI1 (dn
) << 7;
16294 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16295 inst
.instruction
|= (bcdebits
& 3) << 5;
16296 inst
.instruction
|= (bcdebits
>> 2) << 21;
16300 case NS_DRR
: /* case 5 (fmdrr). */
16301 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16304 inst
.instruction
= 0xc400b10;
16305 do_vfp_cond_or_thumb ();
16306 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16307 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16308 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16309 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16312 case NS_RS
: /* case 6. */
16315 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16316 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16317 unsigned abcdebits
= 0;
16319 /* .<dt> is optional here, defaulting to .32. */
16320 if (inst
.vectype
.elems
== 0
16321 && inst
.operands
[0].vectype
.type
== NT_invtype
16322 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16324 inst
.vectype
.el
[0].type
= NT_untyped
;
16325 inst
.vectype
.el
[0].size
= 32;
16326 inst
.vectype
.elems
= 1;
16329 et
= neon_check_type (2, NS_NULL
,
16330 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16331 logsize
= neon_logbits (et
.size
);
16333 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16335 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16336 && et
.size
!= 32, _(BAD_FPU
));
16337 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16338 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16342 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16343 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16344 case 32: abcdebits
= 0x00; break;
16348 abcdebits
|= x
<< logsize
;
16349 inst
.instruction
= 0xe100b10;
16350 do_vfp_cond_or_thumb ();
16351 inst
.instruction
|= LOW4 (dn
) << 16;
16352 inst
.instruction
|= HI1 (dn
) << 7;
16353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16354 inst
.instruction
|= (abcdebits
& 3) << 5;
16355 inst
.instruction
|= (abcdebits
>> 2) << 21;
16359 case NS_RRD
: /* case 7 (fmrrd). */
16360 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16363 inst
.instruction
= 0xc500b10;
16364 do_vfp_cond_or_thumb ();
16365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16366 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16367 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16368 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16371 case NS_FF
: /* case 8 (fcpys). */
16372 do_vfp_nsyn_opcode ("fcpys");
16376 case NS_FI
: /* case 10 (fconsts). */
16377 ldconst
= "fconsts";
16379 if (is_quarter_float (inst
.operands
[1].imm
))
16381 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16382 do_vfp_nsyn_opcode (ldconst
);
16384 /* ARMv8.2 fp16 vmov.f16 instruction. */
16386 do_scalar_fp16_v82_encode ();
16389 first_error (_("immediate out of range"));
16393 case NS_RF
: /* case 12 (fmrs). */
16394 do_vfp_nsyn_opcode ("fmrs");
16395 /* ARMv8.2 fp16 vmov.f16 instruction. */
16397 do_scalar_fp16_v82_encode ();
16401 case NS_FR
: /* case 13 (fmsr). */
16402 do_vfp_nsyn_opcode ("fmsr");
16403 /* ARMv8.2 fp16 vmov.f16 instruction. */
16405 do_scalar_fp16_v82_encode ();
16408 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16409 (one of which is a list), but we have parsed four. Do some fiddling to
16410 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16412 case NS_RRFF
: /* case 14 (fmrrs). */
16413 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16414 _("VFP registers must be adjacent"));
16415 inst
.operands
[2].imm
= 2;
16416 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16417 do_vfp_nsyn_opcode ("fmrrs");
16420 case NS_FFRR
: /* case 15 (fmsrr). */
16421 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16422 _("VFP registers must be adjacent"));
16423 inst
.operands
[1] = inst
.operands
[2];
16424 inst
.operands
[2] = inst
.operands
[3];
16425 inst
.operands
[0].imm
= 2;
16426 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16427 do_vfp_nsyn_opcode ("fmsrr");
16431 /* neon_select_shape has determined that the instruction
16432 shape is wrong and has already set the error message. */
16441 do_neon_rshift_round_imm (void)
16443 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16444 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16445 int imm
= inst
.operands
[2].imm
;
16447 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16450 inst
.operands
[2].present
= 0;
16455 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16456 _("immediate out of range for shift"));
16457 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16462 do_neon_movhf (void)
16464 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16465 constraint (rs
!= NS_HH
, _("invalid suffix"));
16467 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16470 do_vfp_sp_monadic ();
16473 inst
.instruction
|= 0xf0000000;
16477 do_neon_movl (void)
16479 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16480 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16481 unsigned sizebits
= et
.size
>> 3;
16482 inst
.instruction
|= sizebits
<< 19;
16483 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16489 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16490 struct neon_type_el et
= neon_check_type (2, rs
,
16491 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16492 NEON_ENCODE (INTEGER
, inst
);
16493 neon_two_same (neon_quad (rs
), 1, et
.size
);
16497 do_neon_zip_uzp (void)
16499 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16500 struct neon_type_el et
= neon_check_type (2, rs
,
16501 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16502 if (rs
== NS_DD
&& et
.size
== 32)
16504 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16505 inst
.instruction
= N_MNEM_vtrn
;
16509 neon_two_same (neon_quad (rs
), 1, et
.size
);
16513 do_neon_sat_abs_neg (void)
16515 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16516 struct neon_type_el et
= neon_check_type (2, rs
,
16517 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16518 neon_two_same (neon_quad (rs
), 1, et
.size
);
16522 do_neon_pair_long (void)
16524 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16525 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16526 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16527 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16528 neon_two_same (neon_quad (rs
), 1, et
.size
);
16532 do_neon_recip_est (void)
16534 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16535 struct neon_type_el et
= neon_check_type (2, rs
,
16536 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16537 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16538 neon_two_same (neon_quad (rs
), 1, et
.size
);
16544 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16545 struct neon_type_el et
= neon_check_type (2, rs
,
16546 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16547 neon_two_same (neon_quad (rs
), 1, et
.size
);
16553 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16554 struct neon_type_el et
= neon_check_type (2, rs
,
16555 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16556 neon_two_same (neon_quad (rs
), 1, et
.size
);
16562 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16563 struct neon_type_el et
= neon_check_type (2, rs
,
16564 N_EQK
| N_INT
, N_8
| N_KEY
);
16565 neon_two_same (neon_quad (rs
), 1, et
.size
);
16571 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16572 neon_two_same (neon_quad (rs
), 1, -1);
16576 do_neon_tbl_tbx (void)
16578 unsigned listlenbits
;
16579 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16581 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16583 first_error (_("bad list length for table lookup"));
16587 listlenbits
= inst
.operands
[1].imm
- 1;
16588 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16589 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16590 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16591 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16592 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16593 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16594 inst
.instruction
|= listlenbits
<< 8;
16596 neon_dp_fixup (&inst
);
16600 do_neon_ldm_stm (void)
16602 /* P, U and L bits are part of bitmask. */
16603 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16604 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16606 if (inst
.operands
[1].issingle
)
16608 do_vfp_nsyn_ldm_stm (is_dbmode
);
16612 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16613 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16615 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16616 _("register list must contain at least 1 and at most 16 "
16619 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16620 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16621 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16622 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16624 inst
.instruction
|= offsetbits
;
16626 do_vfp_cond_or_thumb ();
16630 do_neon_ldr_str (void)
16632 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16634 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16635 And is UNPREDICTABLE in thumb mode. */
16637 && inst
.operands
[1].reg
== REG_PC
16638 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16641 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16642 else if (warn_on_deprecated
)
16643 as_tsktsk (_("Use of PC here is deprecated"));
16646 if (inst
.operands
[0].issingle
)
16649 do_vfp_nsyn_opcode ("flds");
16651 do_vfp_nsyn_opcode ("fsts");
16653 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16654 if (inst
.vectype
.el
[0].size
== 16)
16655 do_scalar_fp16_v82_encode ();
16660 do_vfp_nsyn_opcode ("fldd");
16662 do_vfp_nsyn_opcode ("fstd");
16666 /* "interleave" version also handles non-interleaving register VLD1/VST1
16670 do_neon_ld_st_interleave (void)
16672 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16673 N_8
| N_16
| N_32
| N_64
);
16674 unsigned alignbits
= 0;
16676 /* The bits in this table go:
16677 0: register stride of one (0) or two (1)
16678 1,2: register list length, minus one (1, 2, 3, 4).
16679 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16680 We use -1 for invalid entries. */
16681 const int typetable
[] =
16683 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16684 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16685 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16686 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16690 if (et
.type
== NT_invtype
)
16693 if (inst
.operands
[1].immisalign
)
16694 switch (inst
.operands
[1].imm
>> 8)
16696 case 64: alignbits
= 1; break;
16698 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16699 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16700 goto bad_alignment
;
16704 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16705 goto bad_alignment
;
16710 first_error (_("bad alignment"));
16714 inst
.instruction
|= alignbits
<< 4;
16715 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16717 /* Bits [4:6] of the immediate in a list specifier encode register stride
16718 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16719 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16720 up the right value for "type" in a table based on this value and the given
16721 list style, then stick it back. */
16722 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16723 | (((inst
.instruction
>> 8) & 3) << 3);
16725 typebits
= typetable
[idx
];
16727 constraint (typebits
== -1, _("bad list type for instruction"));
16728 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16729 _("bad element type for instruction"));
16731 inst
.instruction
&= ~0xf00;
16732 inst
.instruction
|= typebits
<< 8;
16735 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16736 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16737 otherwise. The variable arguments are a list of pairs of legal (size, align)
16738 values, terminated with -1. */
16741 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16744 int result
= FAIL
, thissize
, thisalign
;
16746 if (!inst
.operands
[1].immisalign
)
16752 va_start (ap
, do_alignment
);
16756 thissize
= va_arg (ap
, int);
16757 if (thissize
== -1)
16759 thisalign
= va_arg (ap
, int);
16761 if (size
== thissize
&& align
== thisalign
)
16764 while (result
!= SUCCESS
);
16768 if (result
== SUCCESS
)
16771 first_error (_("unsupported alignment for instruction"));
16777 do_neon_ld_st_lane (void)
16779 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16780 int align_good
, do_alignment
= 0;
16781 int logsize
= neon_logbits (et
.size
);
16782 int align
= inst
.operands
[1].imm
>> 8;
16783 int n
= (inst
.instruction
>> 8) & 3;
16784 int max_el
= 64 / et
.size
;
16786 if (et
.type
== NT_invtype
)
16789 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16790 _("bad list length"));
16791 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16792 _("scalar index out of range"));
16793 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16795 _("stride of 2 unavailable when element size is 8"));
16799 case 0: /* VLD1 / VST1. */
16800 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16802 if (align_good
== FAIL
)
16806 unsigned alignbits
= 0;
16809 case 16: alignbits
= 0x1; break;
16810 case 32: alignbits
= 0x3; break;
16813 inst
.instruction
|= alignbits
<< 4;
16817 case 1: /* VLD2 / VST2. */
16818 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16819 16, 32, 32, 64, -1);
16820 if (align_good
== FAIL
)
16823 inst
.instruction
|= 1 << 4;
16826 case 2: /* VLD3 / VST3. */
16827 constraint (inst
.operands
[1].immisalign
,
16828 _("can't use alignment with this instruction"));
16831 case 3: /* VLD4 / VST4. */
16832 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16833 16, 64, 32, 64, 32, 128, -1);
16834 if (align_good
== FAIL
)
16838 unsigned alignbits
= 0;
16841 case 8: alignbits
= 0x1; break;
16842 case 16: alignbits
= 0x1; break;
16843 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16846 inst
.instruction
|= alignbits
<< 4;
16853 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16854 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16855 inst
.instruction
|= 1 << (4 + logsize
);
16857 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16858 inst
.instruction
|= logsize
<< 10;
16861 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16864 do_neon_ld_dup (void)
16866 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16867 int align_good
, do_alignment
= 0;
16869 if (et
.type
== NT_invtype
)
16872 switch ((inst
.instruction
>> 8) & 3)
16874 case 0: /* VLD1. */
16875 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16876 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16877 &do_alignment
, 16, 16, 32, 32, -1);
16878 if (align_good
== FAIL
)
16880 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16883 case 2: inst
.instruction
|= 1 << 5; break;
16884 default: first_error (_("bad list length")); return;
16886 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16889 case 1: /* VLD2. */
16890 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16891 &do_alignment
, 8, 16, 16, 32, 32, 64,
16893 if (align_good
== FAIL
)
16895 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16896 _("bad list length"));
16897 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16898 inst
.instruction
|= 1 << 5;
16899 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16902 case 2: /* VLD3. */
16903 constraint (inst
.operands
[1].immisalign
,
16904 _("can't use alignment with this instruction"));
16905 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16906 _("bad list length"));
16907 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16908 inst
.instruction
|= 1 << 5;
16909 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16912 case 3: /* VLD4. */
16914 int align
= inst
.operands
[1].imm
>> 8;
16915 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16916 16, 64, 32, 64, 32, 128, -1);
16917 if (align_good
== FAIL
)
16919 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16920 _("bad list length"));
16921 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16922 inst
.instruction
|= 1 << 5;
16923 if (et
.size
== 32 && align
== 128)
16924 inst
.instruction
|= 0x3 << 6;
16926 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16933 inst
.instruction
|= do_alignment
<< 4;
16936 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16937 apart from bits [11:4]. */
16940 do_neon_ldx_stx (void)
16942 if (inst
.operands
[1].isreg
)
16943 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16945 switch (NEON_LANE (inst
.operands
[0].imm
))
16947 case NEON_INTERLEAVE_LANES
:
16948 NEON_ENCODE (INTERLV
, inst
);
16949 do_neon_ld_st_interleave ();
16952 case NEON_ALL_LANES
:
16953 NEON_ENCODE (DUP
, inst
);
16954 if (inst
.instruction
== N_INV
)
16956 first_error ("only loads support such operands");
16963 NEON_ENCODE (LANE
, inst
);
16964 do_neon_ld_st_lane ();
16967 /* L bit comes from bit mask. */
16968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16972 if (inst
.operands
[1].postind
)
16974 int postreg
= inst
.operands
[1].imm
& 0xf;
16975 constraint (!inst
.operands
[1].immisreg
,
16976 _("post-index must be a register"));
16977 constraint (postreg
== 0xd || postreg
== 0xf,
16978 _("bad register for post-index"));
16979 inst
.instruction
|= postreg
;
16983 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16984 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16985 || inst
.reloc
.exp
.X_add_number
!= 0,
16988 if (inst
.operands
[1].writeback
)
16990 inst
.instruction
|= 0xd;
16993 inst
.instruction
|= 0xf;
16997 inst
.instruction
|= 0xf9000000;
16999 inst
.instruction
|= 0xf4000000;
17004 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17006 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17007 D register operands. */
17008 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17009 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17012 NEON_ENCODE (FPV8
, inst
);
17014 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17016 do_vfp_sp_dyadic ();
17018 /* ARMv8.2 fp16 instruction. */
17020 do_scalar_fp16_v82_encode ();
17023 do_vfp_dp_rd_rn_rm ();
17026 inst
.instruction
|= 0x100;
17028 inst
.instruction
|= 0xf0000000;
17034 set_it_insn_type (OUTSIDE_IT_INSN
);
17036 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17037 first_error (_("invalid instruction shape"));
17043 set_it_insn_type (OUTSIDE_IT_INSN
);
17045 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17048 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17051 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17055 do_vrint_1 (enum neon_cvt_mode mode
)
17057 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17058 struct neon_type_el et
;
17063 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17064 D register operands. */
17065 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17066 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17069 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17071 if (et
.type
!= NT_invtype
)
17073 /* VFP encodings. */
17074 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17075 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17076 set_it_insn_type (OUTSIDE_IT_INSN
);
17078 NEON_ENCODE (FPV8
, inst
);
17079 if (rs
== NS_FF
|| rs
== NS_HH
)
17080 do_vfp_sp_monadic ();
17082 do_vfp_dp_rd_rm ();
17086 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17087 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17088 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17089 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17090 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17091 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17092 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17096 inst
.instruction
|= (rs
== NS_DD
) << 8;
17097 do_vfp_cond_or_thumb ();
17099 /* ARMv8.2 fp16 vrint instruction. */
17101 do_scalar_fp16_v82_encode ();
17105 /* Neon encodings (or something broken...). */
17107 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17109 if (et
.type
== NT_invtype
)
17112 set_it_insn_type (OUTSIDE_IT_INSN
);
17113 NEON_ENCODE (FLOAT
, inst
);
17115 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17118 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17119 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17120 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17121 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17122 inst
.instruction
|= neon_quad (rs
) << 6;
17123 /* Mask off the original size bits and reencode them. */
17124 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17125 | neon_logbits (et
.size
) << 18);
17129 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17130 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17131 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17132 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17133 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17134 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17135 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17140 inst
.instruction
|= 0xfc000000;
17142 inst
.instruction
|= 0xf0000000;
17149 do_vrint_1 (neon_cvt_mode_x
);
17155 do_vrint_1 (neon_cvt_mode_z
);
17161 do_vrint_1 (neon_cvt_mode_r
);
17167 do_vrint_1 (neon_cvt_mode_a
);
17173 do_vrint_1 (neon_cvt_mode_n
);
17179 do_vrint_1 (neon_cvt_mode_p
);
17185 do_vrint_1 (neon_cvt_mode_m
);
17188 /* Crypto v1 instructions. */
17190 do_crypto_2op_1 (unsigned elttype
, int op
)
17192 set_it_insn_type (OUTSIDE_IT_INSN
);
17194 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17200 NEON_ENCODE (INTEGER
, inst
);
17201 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17202 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17203 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17204 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17206 inst
.instruction
|= op
<< 6;
17209 inst
.instruction
|= 0xfc000000;
17211 inst
.instruction
|= 0xf0000000;
17215 do_crypto_3op_1 (int u
, int op
)
17217 set_it_insn_type (OUTSIDE_IT_INSN
);
17219 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17220 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17225 NEON_ENCODE (INTEGER
, inst
);
17226 neon_three_same (1, u
, 8 << op
);
17232 do_crypto_2op_1 (N_8
, 0);
17238 do_crypto_2op_1 (N_8
, 1);
17244 do_crypto_2op_1 (N_8
, 2);
17250 do_crypto_2op_1 (N_8
, 3);
17256 do_crypto_3op_1 (0, 0);
17262 do_crypto_3op_1 (0, 1);
17268 do_crypto_3op_1 (0, 2);
17274 do_crypto_3op_1 (0, 3);
17280 do_crypto_3op_1 (1, 0);
17286 do_crypto_3op_1 (1, 1);
17290 do_sha256su1 (void)
17292 do_crypto_3op_1 (1, 2);
17298 do_crypto_2op_1 (N_32
, -1);
17304 do_crypto_2op_1 (N_32
, 0);
17308 do_sha256su0 (void)
17310 do_crypto_2op_1 (N_32
, 1);
17314 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17316 unsigned int Rd
= inst
.operands
[0].reg
;
17317 unsigned int Rn
= inst
.operands
[1].reg
;
17318 unsigned int Rm
= inst
.operands
[2].reg
;
17320 set_it_insn_type (OUTSIDE_IT_INSN
);
17321 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17322 inst
.instruction
|= LOW4 (Rn
) << 16;
17323 inst
.instruction
|= LOW4 (Rm
);
17324 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17325 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17327 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17328 as_warn (UNPRED_REG ("r15"));
17329 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17330 as_warn (UNPRED_REG ("r13"));
17370 /* Overall per-instruction processing. */
17372 /* We need to be able to fix up arbitrary expressions in some statements.
17373 This is so that we can handle symbols that are an arbitrary distance from
17374 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17375 which returns part of an address in a form which will be valid for
17376 a data instruction. We do this by pushing the expression into a symbol
17377 in the expr_section, and creating a fix for that. */
17380 fix_new_arm (fragS
* frag
,
17394 /* Create an absolute valued symbol, so we have something to
17395 refer to in the object file. Unfortunately for us, gas's
17396 generic expression parsing will already have folded out
17397 any use of .set foo/.type foo %function that may have
17398 been used to set type information of the target location,
17399 that's being specified symbolically. We have to presume
17400 the user knows what they are doing. */
17404 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17406 symbol
= symbol_find_or_make (name
);
17407 S_SET_SEGMENT (symbol
, absolute_section
);
17408 symbol_set_frag (symbol
, &zero_address_frag
);
17409 S_SET_VALUE (symbol
, exp
->X_add_number
);
17410 exp
->X_op
= O_symbol
;
17411 exp
->X_add_symbol
= symbol
;
17412 exp
->X_add_number
= 0;
17418 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17419 (enum bfd_reloc_code_real
) reloc
);
17423 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17424 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17428 /* Mark whether the fix is to a THUMB instruction, or an ARM
17430 new_fix
->tc_fix_data
= thumb_mode
;
17433 /* Create a frg for an instruction requiring relaxation. */
17435 output_relax_insn (void)
17441 /* The size of the instruction is unknown, so tie the debug info to the
17442 start of the instruction. */
17443 dwarf2_emit_insn (0);
17445 switch (inst
.reloc
.exp
.X_op
)
17448 sym
= inst
.reloc
.exp
.X_add_symbol
;
17449 offset
= inst
.reloc
.exp
.X_add_number
;
17453 offset
= inst
.reloc
.exp
.X_add_number
;
17456 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17460 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17461 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17462 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17465 /* Write a 32-bit thumb instruction to buf. */
17467 put_thumb32_insn (char * buf
, unsigned long insn
)
17469 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17470 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17474 output_inst (const char * str
)
17480 as_bad ("%s -- `%s'", inst
.error
, str
);
17485 output_relax_insn ();
17488 if (inst
.size
== 0)
17491 to
= frag_more (inst
.size
);
17492 /* PR 9814: Record the thumb mode into the current frag so that we know
17493 what type of NOP padding to use, if necessary. We override any previous
17494 setting so that if the mode has changed then the NOPS that we use will
17495 match the encoding of the last instruction in the frag. */
17496 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17498 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17500 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17501 put_thumb32_insn (to
, inst
.instruction
);
17503 else if (inst
.size
> INSN_SIZE
)
17505 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17506 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17507 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17510 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17512 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17513 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17514 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17517 dwarf2_emit_insn (inst
.size
);
17521 output_it_inst (int cond
, int mask
, char * to
)
17523 unsigned long instruction
= 0xbf00;
17526 instruction
|= mask
;
17527 instruction
|= cond
<< 4;
17531 to
= frag_more (2);
17533 dwarf2_emit_insn (2);
17537 md_number_to_chars (to
, instruction
, 2);
17542 /* Tag values used in struct asm_opcode's tag field. */
17545 OT_unconditional
, /* Instruction cannot be conditionalized.
17546 The ARM condition field is still 0xE. */
17547 OT_unconditionalF
, /* Instruction cannot be conditionalized
17548 and carries 0xF in its ARM condition field. */
17549 OT_csuffix
, /* Instruction takes a conditional suffix. */
17550 OT_csuffixF
, /* Some forms of the instruction take a conditional
17551 suffix, others place 0xF where the condition field
17553 OT_cinfix3
, /* Instruction takes a conditional infix,
17554 beginning at character index 3. (In
17555 unified mode, it becomes a suffix.) */
17556 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17557 tsts, cmps, cmns, and teqs. */
17558 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17559 character index 3, even in unified mode. Used for
17560 legacy instructions where suffix and infix forms
17561 may be ambiguous. */
17562 OT_csuf_or_in3
, /* Instruction takes either a conditional
17563 suffix or an infix at character index 3. */
17564 OT_odd_infix_unc
, /* This is the unconditional variant of an
17565 instruction that takes a conditional infix
17566 at an unusual position. In unified mode,
17567 this variant will accept a suffix. */
17568 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17569 are the conditional variants of instructions that
17570 take conditional infixes in unusual positions.
17571 The infix appears at character index
17572 (tag - OT_odd_infix_0). These are not accepted
17573 in unified mode. */
17576 /* Subroutine of md_assemble, responsible for looking up the primary
17577 opcode from the mnemonic the user wrote. STR points to the
17578 beginning of the mnemonic.
17580 This is not simply a hash table lookup, because of conditional
17581 variants. Most instructions have conditional variants, which are
17582 expressed with a _conditional affix_ to the mnemonic. If we were
17583 to encode each conditional variant as a literal string in the opcode
17584 table, it would have approximately 20,000 entries.
17586 Most mnemonics take this affix as a suffix, and in unified syntax,
17587 'most' is upgraded to 'all'. However, in the divided syntax, some
17588 instructions take the affix as an infix, notably the s-variants of
17589 the arithmetic instructions. Of those instructions, all but six
17590 have the infix appear after the third character of the mnemonic.
17592 Accordingly, the algorithm for looking up primary opcodes given
17595 1. Look up the identifier in the opcode table.
17596 If we find a match, go to step U.
17598 2. Look up the last two characters of the identifier in the
17599 conditions table. If we find a match, look up the first N-2
17600 characters of the identifier in the opcode table. If we
17601 find a match, go to step CE.
17603 3. Look up the fourth and fifth characters of the identifier in
17604 the conditions table. If we find a match, extract those
17605 characters from the identifier, and look up the remaining
17606 characters in the opcode table. If we find a match, go
17611 U. Examine the tag field of the opcode structure, in case this is
17612 one of the six instructions with its conditional infix in an
17613 unusual place. If it is, the tag tells us where to find the
17614 infix; look it up in the conditions table and set inst.cond
17615 accordingly. Otherwise, this is an unconditional instruction.
17616 Again set inst.cond accordingly. Return the opcode structure.
17618 CE. Examine the tag field to make sure this is an instruction that
17619 should receive a conditional suffix. If it is not, fail.
17620 Otherwise, set inst.cond from the suffix we already looked up,
17621 and return the opcode structure.
17623 CM. Examine the tag field to make sure this is an instruction that
17624 should receive a conditional infix after the third character.
17625 If it is not, fail. Otherwise, undo the edits to the current
17626 line of input and proceed as for case CE. */
17628 static const struct asm_opcode
*
17629 opcode_lookup (char **str
)
17633 const struct asm_opcode
*opcode
;
17634 const struct asm_cond
*cond
;
17637 /* Scan up to the end of the mnemonic, which must end in white space,
17638 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17639 for (base
= end
= *str
; *end
!= '\0'; end
++)
17640 if (*end
== ' ' || *end
== '.')
17646 /* Handle a possible width suffix and/or Neon type suffix. */
17651 /* The .w and .n suffixes are only valid if the unified syntax is in
17653 if (unified_syntax
&& end
[1] == 'w')
17655 else if (unified_syntax
&& end
[1] == 'n')
17660 inst
.vectype
.elems
= 0;
17662 *str
= end
+ offset
;
17664 if (end
[offset
] == '.')
17666 /* See if we have a Neon type suffix (possible in either unified or
17667 non-unified ARM syntax mode). */
17668 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17671 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17677 /* Look for unaffixed or special-case affixed mnemonic. */
17678 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17683 if (opcode
->tag
< OT_odd_infix_0
)
17685 inst
.cond
= COND_ALWAYS
;
17689 if (warn_on_deprecated
&& unified_syntax
)
17690 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17691 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17692 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17695 inst
.cond
= cond
->value
;
17699 /* Cannot have a conditional suffix on a mnemonic of less than two
17701 if (end
- base
< 3)
17704 /* Look for suffixed mnemonic. */
17706 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17707 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17709 if (opcode
&& cond
)
17712 switch (opcode
->tag
)
17714 case OT_cinfix3_legacy
:
17715 /* Ignore conditional suffixes matched on infix only mnemonics. */
17719 case OT_cinfix3_deprecated
:
17720 case OT_odd_infix_unc
:
17721 if (!unified_syntax
)
17723 /* else fall through */
17727 case OT_csuf_or_in3
:
17728 inst
.cond
= cond
->value
;
17731 case OT_unconditional
:
17732 case OT_unconditionalF
:
17734 inst
.cond
= cond
->value
;
17737 /* Delayed diagnostic. */
17738 inst
.error
= BAD_COND
;
17739 inst
.cond
= COND_ALWAYS
;
17748 /* Cannot have a usual-position infix on a mnemonic of less than
17749 six characters (five would be a suffix). */
17750 if (end
- base
< 6)
17753 /* Look for infixed mnemonic in the usual position. */
17755 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17759 memcpy (save
, affix
, 2);
17760 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17761 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17763 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17764 memcpy (affix
, save
, 2);
17767 && (opcode
->tag
== OT_cinfix3
17768 || opcode
->tag
== OT_cinfix3_deprecated
17769 || opcode
->tag
== OT_csuf_or_in3
17770 || opcode
->tag
== OT_cinfix3_legacy
))
17773 if (warn_on_deprecated
&& unified_syntax
17774 && (opcode
->tag
== OT_cinfix3
17775 || opcode
->tag
== OT_cinfix3_deprecated
))
17776 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17778 inst
.cond
= cond
->value
;
17785 /* This function generates an initial IT instruction, leaving its block
17786 virtually open for the new instructions. Eventually,
17787 the mask will be updated by now_it_add_mask () each time
17788 a new instruction needs to be included in the IT block.
17789 Finally, the block is closed with close_automatic_it_block ().
17790 The block closure can be requested either from md_assemble (),
17791 a tencode (), or due to a label hook. */
17794 new_automatic_it_block (int cond
)
17796 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17797 now_it
.mask
= 0x18;
17799 now_it
.block_length
= 1;
17800 mapping_state (MAP_THUMB
);
17801 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17802 now_it
.warn_deprecated
= FALSE
;
17803 now_it
.insn_cond
= TRUE
;
17806 /* Close an automatic IT block.
17807 See comments in new_automatic_it_block (). */
17810 close_automatic_it_block (void)
17812 now_it
.mask
= 0x10;
17813 now_it
.block_length
= 0;
17816 /* Update the mask of the current automatically-generated IT
17817 instruction. See comments in new_automatic_it_block (). */
17820 now_it_add_mask (int cond
)
17822 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17823 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17824 | ((bitvalue) << (nbit)))
17825 const int resulting_bit
= (cond
& 1);
17827 now_it
.mask
&= 0xf;
17828 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17830 (5 - now_it
.block_length
));
17831 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17833 ((5 - now_it
.block_length
) - 1) );
17834 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17837 #undef SET_BIT_VALUE
17840 /* The IT blocks handling machinery is accessed through the these functions:
17841 it_fsm_pre_encode () from md_assemble ()
17842 set_it_insn_type () optional, from the tencode functions
17843 set_it_insn_type_last () ditto
17844 in_it_block () ditto
17845 it_fsm_post_encode () from md_assemble ()
17846 force_automatic_it_block_close () from label habdling functions
17849 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17850 initializing the IT insn type with a generic initial value depending
17851 on the inst.condition.
17852 2) During the tencode function, two things may happen:
17853 a) The tencode function overrides the IT insn type by
17854 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17855 b) The tencode function queries the IT block state by
17856 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17858 Both set_it_insn_type and in_it_block run the internal FSM state
17859 handling function (handle_it_state), because: a) setting the IT insn
17860 type may incur in an invalid state (exiting the function),
17861 and b) querying the state requires the FSM to be updated.
17862 Specifically we want to avoid creating an IT block for conditional
17863 branches, so it_fsm_pre_encode is actually a guess and we can't
17864 determine whether an IT block is required until the tencode () routine
17865 has decided what type of instruction this actually it.
17866 Because of this, if set_it_insn_type and in_it_block have to be used,
17867 set_it_insn_type has to be called first.
17869 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17870 determines the insn IT type depending on the inst.cond code.
17871 When a tencode () routine encodes an instruction that can be
17872 either outside an IT block, or, in the case of being inside, has to be
17873 the last one, set_it_insn_type_last () will determine the proper
17874 IT instruction type based on the inst.cond code. Otherwise,
17875 set_it_insn_type can be called for overriding that logic or
17876 for covering other cases.
17878 Calling handle_it_state () may not transition the IT block state to
17879 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17880 still queried. Instead, if the FSM determines that the state should
17881 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17882 after the tencode () function: that's what it_fsm_post_encode () does.
17884 Since in_it_block () calls the state handling function to get an
17885 updated state, an error may occur (due to invalid insns combination).
17886 In that case, inst.error is set.
17887 Therefore, inst.error has to be checked after the execution of
17888 the tencode () routine.
17890 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17891 any pending state change (if any) that didn't take place in
17892 handle_it_state () as explained above. */
17895 it_fsm_pre_encode (void)
17897 if (inst
.cond
!= COND_ALWAYS
)
17898 inst
.it_insn_type
= INSIDE_IT_INSN
;
17900 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17902 now_it
.state_handled
= 0;
17905 /* IT state FSM handling function. */
17908 handle_it_state (void)
17910 now_it
.state_handled
= 1;
17911 now_it
.insn_cond
= FALSE
;
17913 switch (now_it
.state
)
17915 case OUTSIDE_IT_BLOCK
:
17916 switch (inst
.it_insn_type
)
17918 case OUTSIDE_IT_INSN
:
17921 case INSIDE_IT_INSN
:
17922 case INSIDE_IT_LAST_INSN
:
17923 if (thumb_mode
== 0)
17926 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17927 as_tsktsk (_("Warning: conditional outside an IT block"\
17932 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17933 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17935 /* Automatically generate the IT instruction. */
17936 new_automatic_it_block (inst
.cond
);
17937 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17938 close_automatic_it_block ();
17942 inst
.error
= BAD_OUT_IT
;
17948 case IF_INSIDE_IT_LAST_INSN
:
17949 case NEUTRAL_IT_INSN
:
17953 now_it
.state
= MANUAL_IT_BLOCK
;
17954 now_it
.block_length
= 0;
17959 case AUTOMATIC_IT_BLOCK
:
17960 /* Three things may happen now:
17961 a) We should increment current it block size;
17962 b) We should close current it block (closing insn or 4 insns);
17963 c) We should close current it block and start a new one (due
17964 to incompatible conditions or
17965 4 insns-length block reached). */
17967 switch (inst
.it_insn_type
)
17969 case OUTSIDE_IT_INSN
:
17970 /* The closure of the block shall happen immediatelly,
17971 so any in_it_block () call reports the block as closed. */
17972 force_automatic_it_block_close ();
17975 case INSIDE_IT_INSN
:
17976 case INSIDE_IT_LAST_INSN
:
17977 case IF_INSIDE_IT_LAST_INSN
:
17978 now_it
.block_length
++;
17980 if (now_it
.block_length
> 4
17981 || !now_it_compatible (inst
.cond
))
17983 force_automatic_it_block_close ();
17984 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17985 new_automatic_it_block (inst
.cond
);
17989 now_it
.insn_cond
= TRUE
;
17990 now_it_add_mask (inst
.cond
);
17993 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17994 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17995 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17996 close_automatic_it_block ();
17999 case NEUTRAL_IT_INSN
:
18000 now_it
.block_length
++;
18001 now_it
.insn_cond
= TRUE
;
18003 if (now_it
.block_length
> 4)
18004 force_automatic_it_block_close ();
18006 now_it_add_mask (now_it
.cc
& 1);
18010 close_automatic_it_block ();
18011 now_it
.state
= MANUAL_IT_BLOCK
;
18016 case MANUAL_IT_BLOCK
:
18018 /* Check conditional suffixes. */
18019 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18022 now_it
.mask
&= 0x1f;
18023 is_last
= (now_it
.mask
== 0x10);
18024 now_it
.insn_cond
= TRUE
;
18026 switch (inst
.it_insn_type
)
18028 case OUTSIDE_IT_INSN
:
18029 inst
.error
= BAD_NOT_IT
;
18032 case INSIDE_IT_INSN
:
18033 if (cond
!= inst
.cond
)
18035 inst
.error
= BAD_IT_COND
;
18040 case INSIDE_IT_LAST_INSN
:
18041 case IF_INSIDE_IT_LAST_INSN
:
18042 if (cond
!= inst
.cond
)
18044 inst
.error
= BAD_IT_COND
;
18049 inst
.error
= BAD_BRANCH
;
18054 case NEUTRAL_IT_INSN
:
18055 /* The BKPT instruction is unconditional even in an IT block. */
18059 inst
.error
= BAD_IT_IT
;
18069 struct depr_insn_mask
18071 unsigned long pattern
;
18072 unsigned long mask
;
18073 const char* description
;
18076 /* List of 16-bit instruction patterns deprecated in an IT block in
18078 static const struct depr_insn_mask depr_it_insns
[] = {
18079 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18080 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18081 { 0xa000, 0xb800, N_("ADR") },
18082 { 0x4800, 0xf800, N_("Literal loads") },
18083 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18084 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18085 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18086 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18087 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18092 it_fsm_post_encode (void)
18096 if (!now_it
.state_handled
)
18097 handle_it_state ();
18099 if (now_it
.insn_cond
18100 && !now_it
.warn_deprecated
18101 && warn_on_deprecated
18102 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18104 if (inst
.instruction
>= 0x10000)
18106 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18107 "deprecated in ARMv8"));
18108 now_it
.warn_deprecated
= TRUE
;
18112 const struct depr_insn_mask
*p
= depr_it_insns
;
18114 while (p
->mask
!= 0)
18116 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18118 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18119 "of the following class are deprecated in ARMv8: "
18120 "%s"), p
->description
);
18121 now_it
.warn_deprecated
= TRUE
;
18129 if (now_it
.block_length
> 1)
18131 as_tsktsk (_("IT blocks containing more than one conditional "
18132 "instruction are deprecated in ARMv8"));
18133 now_it
.warn_deprecated
= TRUE
;
18137 is_last
= (now_it
.mask
== 0x10);
18140 now_it
.state
= OUTSIDE_IT_BLOCK
;
18146 force_automatic_it_block_close (void)
18148 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18150 close_automatic_it_block ();
18151 now_it
.state
= OUTSIDE_IT_BLOCK
;
18159 if (!now_it
.state_handled
)
18160 handle_it_state ();
18162 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18165 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18166 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18167 here, hence the "known" in the function name. */
18170 known_t32_only_insn (const struct asm_opcode
*opcode
)
18172 /* Original Thumb-1 wide instruction. */
18173 if (opcode
->tencode
== do_t_blx
18174 || opcode
->tencode
== do_t_branch23
18175 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18176 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18179 /* Wide-only instruction added to ARMv8-M. */
18180 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m
)
18181 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18182 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18183 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18189 /* Whether wide instruction variant can be used if available for a valid OPCODE
18193 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18195 if (known_t32_only_insn (opcode
))
18198 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18199 of variant T3 of B.W is checked in do_t_branch. */
18200 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18201 && opcode
->tencode
== do_t_branch
)
18204 /* Wide instruction variants of all instructions with narrow *and* wide
18205 variants become available with ARMv6t2. Other opcodes are either
18206 narrow-only or wide-only and are thus available if OPCODE is valid. */
18207 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18210 /* OPCODE with narrow only instruction variant or wide variant not
18216 md_assemble (char *str
)
18219 const struct asm_opcode
* opcode
;
18221 /* Align the previous label if needed. */
18222 if (last_label_seen
!= NULL
)
18224 symbol_set_frag (last_label_seen
, frag_now
);
18225 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18226 S_SET_SEGMENT (last_label_seen
, now_seg
);
18229 memset (&inst
, '\0', sizeof (inst
));
18230 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18232 opcode
= opcode_lookup (&p
);
18235 /* It wasn't an instruction, but it might be a register alias of
18236 the form alias .req reg, or a Neon .dn/.qn directive. */
18237 if (! create_register_alias (str
, p
)
18238 && ! create_neon_reg_alias (str
, p
))
18239 as_bad (_("bad instruction `%s'"), str
);
18244 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18245 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18247 /* The value which unconditional instructions should have in place of the
18248 condition field. */
18249 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18253 arm_feature_set variant
;
18255 variant
= cpu_variant
;
18256 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18257 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18258 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18259 /* Check that this instruction is supported for this CPU. */
18260 if (!opcode
->tvariant
18261 || (thumb_mode
== 1
18262 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18264 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18267 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18268 && opcode
->tencode
!= do_t_branch
)
18270 as_bad (_("Thumb does not support conditional execution"));
18274 /* Two things are addressed here:
18275 1) Implicit require narrow instructions on Thumb-1.
18276 This avoids relaxation accidentally introducing Thumb-2
18278 2) Reject wide instructions in non Thumb-2 cores.
18280 Only instructions with narrow and wide variants need to be handled
18281 but selecting all non wide-only instructions is easier. */
18282 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18283 && !t32_insn_ok (variant
, opcode
))
18285 if (inst
.size_req
== 0)
18287 else if (inst
.size_req
== 4)
18289 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18290 as_bad (_("selected processor does not support 32bit wide "
18291 "variant of instruction `%s'"), str
);
18293 as_bad (_("selected processor does not support `%s' in "
18294 "Thumb-2 mode"), str
);
18299 inst
.instruction
= opcode
->tvalue
;
18301 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18303 /* Prepare the it_insn_type for those encodings that don't set
18305 it_fsm_pre_encode ();
18307 opcode
->tencode ();
18309 it_fsm_post_encode ();
18312 if (!(inst
.error
|| inst
.relax
))
18314 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18315 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18316 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18318 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18323 /* Something has gone badly wrong if we try to relax a fixed size
18325 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18327 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18328 *opcode
->tvariant
);
18329 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18330 set those bits when Thumb-2 32-bit instructions are seen. The impact
18331 of relaxable instructions will be considered later after we finish all
18333 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18334 variant
= arm_arch_none
;
18336 variant
= cpu_variant
;
18337 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18338 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18341 check_neon_suffixes
;
18345 mapping_state (MAP_THUMB
);
18348 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18352 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18353 is_bx
= (opcode
->aencode
== do_bx
);
18355 /* Check that this instruction is supported for this CPU. */
18356 if (!(is_bx
&& fix_v4bx
)
18357 && !(opcode
->avariant
&&
18358 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18360 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18365 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18369 inst
.instruction
= opcode
->avalue
;
18370 if (opcode
->tag
== OT_unconditionalF
)
18371 inst
.instruction
|= 0xFU
<< 28;
18373 inst
.instruction
|= inst
.cond
<< 28;
18374 inst
.size
= INSN_SIZE
;
18375 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18377 it_fsm_pre_encode ();
18378 opcode
->aencode ();
18379 it_fsm_post_encode ();
18381 /* Arm mode bx is marked as both v4T and v5 because it's still required
18382 on a hypothetical non-thumb v5 core. */
18384 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18386 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18387 *opcode
->avariant
);
18389 check_neon_suffixes
;
18393 mapping_state (MAP_ARM
);
18398 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18406 check_it_blocks_finished (void)
18411 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18412 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18413 == MANUAL_IT_BLOCK
)
18415 as_warn (_("section '%s' finished with an open IT block."),
18419 if (now_it
.state
== MANUAL_IT_BLOCK
)
18420 as_warn (_("file finished with an open IT block."));
18424 /* Various frobbings of labels and their addresses. */
18427 arm_start_line_hook (void)
18429 last_label_seen
= NULL
;
18433 arm_frob_label (symbolS
* sym
)
18435 last_label_seen
= sym
;
18437 ARM_SET_THUMB (sym
, thumb_mode
);
18439 #if defined OBJ_COFF || defined OBJ_ELF
18440 ARM_SET_INTERWORK (sym
, support_interwork
);
18443 force_automatic_it_block_close ();
18445 /* Note - do not allow local symbols (.Lxxx) to be labelled
18446 as Thumb functions. This is because these labels, whilst
18447 they exist inside Thumb code, are not the entry points for
18448 possible ARM->Thumb calls. Also, these labels can be used
18449 as part of a computed goto or switch statement. eg gcc
18450 can generate code that looks like this:
18452 ldr r2, [pc, .Laaa]
18462 The first instruction loads the address of the jump table.
18463 The second instruction converts a table index into a byte offset.
18464 The third instruction gets the jump address out of the table.
18465 The fourth instruction performs the jump.
18467 If the address stored at .Laaa is that of a symbol which has the
18468 Thumb_Func bit set, then the linker will arrange for this address
18469 to have the bottom bit set, which in turn would mean that the
18470 address computation performed by the third instruction would end
18471 up with the bottom bit set. Since the ARM is capable of unaligned
18472 word loads, the instruction would then load the incorrect address
18473 out of the jump table, and chaos would ensue. */
18474 if (label_is_thumb_function_name
18475 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18476 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18478 /* When the address of a Thumb function is taken the bottom
18479 bit of that address should be set. This will allow
18480 interworking between Arm and Thumb functions to work
18483 THUMB_SET_FUNC (sym
, 1);
18485 label_is_thumb_function_name
= FALSE
;
18488 dwarf2_emit_label (sym
);
18492 arm_data_in_code (void)
18494 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18496 *input_line_pointer
= '/';
18497 input_line_pointer
+= 5;
18498 *input_line_pointer
= 0;
18506 arm_canonicalize_symbol_name (char * name
)
18510 if (thumb_mode
&& (len
= strlen (name
)) > 5
18511 && streq (name
+ len
- 5, "/data"))
18512 *(name
+ len
- 5) = 0;
18517 /* Table of all register names defined by default. The user can
18518 define additional names with .req. Note that all register names
18519 should appear in both upper and lowercase variants. Some registers
18520 also have mixed-case names. */
18522 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18523 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18524 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18525 #define REGSET(p,t) \
18526 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18527 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18528 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18529 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18530 #define REGSETH(p,t) \
18531 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18532 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18533 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18534 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18535 #define REGSET2(p,t) \
18536 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18537 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18538 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18539 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18540 #define SPLRBANK(base,bank,t) \
18541 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18542 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18543 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18544 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18545 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18546 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18548 static const struct reg_entry reg_names
[] =
18550 /* ARM integer registers. */
18551 REGSET(r
, RN
), REGSET(R
, RN
),
18553 /* ATPCS synonyms. */
18554 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18555 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18556 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18558 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18559 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18560 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18562 /* Well-known aliases. */
18563 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18564 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18566 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18567 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18569 /* Coprocessor numbers. */
18570 REGSET(p
, CP
), REGSET(P
, CP
),
18572 /* Coprocessor register numbers. The "cr" variants are for backward
18574 REGSET(c
, CN
), REGSET(C
, CN
),
18575 REGSET(cr
, CN
), REGSET(CR
, CN
),
18577 /* ARM banked registers. */
18578 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18579 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18580 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18581 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18582 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18583 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18584 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18586 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18587 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18588 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18589 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18590 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18591 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18592 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18593 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18595 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18596 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18597 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18598 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18599 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18600 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18601 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18602 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18603 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18605 /* FPA registers. */
18606 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18607 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18609 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18610 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18612 /* VFP SP registers. */
18613 REGSET(s
,VFS
), REGSET(S
,VFS
),
18614 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18616 /* VFP DP Registers. */
18617 REGSET(d
,VFD
), REGSET(D
,VFD
),
18618 /* Extra Neon DP registers. */
18619 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18621 /* Neon QP registers. */
18622 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18624 /* VFP control registers. */
18625 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18626 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18627 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18628 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18629 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18630 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18632 /* Maverick DSP coprocessor registers. */
18633 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18634 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18636 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18637 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18638 REGDEF(dspsc
,0,DSPSC
),
18640 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18641 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18642 REGDEF(DSPSC
,0,DSPSC
),
18644 /* iWMMXt data registers - p0, c0-15. */
18645 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18647 /* iWMMXt control registers - p1, c0-3. */
18648 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18649 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18650 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18651 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18653 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18654 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18655 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18656 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18657 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18659 /* XScale accumulator registers. */
18660 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18666 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18667 within psr_required_here. */
18668 static const struct asm_psr psrs
[] =
18670 /* Backward compatibility notation. Note that "all" is no longer
18671 truly all possible PSR bits. */
18672 {"all", PSR_c
| PSR_f
},
18676 /* Individual flags. */
18682 /* Combinations of flags. */
18683 {"fs", PSR_f
| PSR_s
},
18684 {"fx", PSR_f
| PSR_x
},
18685 {"fc", PSR_f
| PSR_c
},
18686 {"sf", PSR_s
| PSR_f
},
18687 {"sx", PSR_s
| PSR_x
},
18688 {"sc", PSR_s
| PSR_c
},
18689 {"xf", PSR_x
| PSR_f
},
18690 {"xs", PSR_x
| PSR_s
},
18691 {"xc", PSR_x
| PSR_c
},
18692 {"cf", PSR_c
| PSR_f
},
18693 {"cs", PSR_c
| PSR_s
},
18694 {"cx", PSR_c
| PSR_x
},
18695 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18696 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18697 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18698 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18699 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18700 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18701 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18702 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18703 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18704 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18705 {"scf", PSR_s
| PSR_c
| PSR_f
},
18706 {"scx", PSR_s
| PSR_c
| PSR_x
},
18707 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18708 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18709 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18710 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18711 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18712 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18713 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18714 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18715 {"csf", PSR_c
| PSR_s
| PSR_f
},
18716 {"csx", PSR_c
| PSR_s
| PSR_x
},
18717 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18718 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18719 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18720 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18721 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18722 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18723 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18724 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18725 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18726 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18727 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18728 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18729 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18730 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18731 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18732 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18733 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18734 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18735 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18736 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18737 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18738 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18739 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18740 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18741 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18742 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18745 /* Table of V7M psr names. */
18746 static const struct asm_psr v7m_psrs
[] =
18748 {"apsr", 0 }, {"APSR", 0 },
18749 {"iapsr", 1 }, {"IAPSR", 1 },
18750 {"eapsr", 2 }, {"EAPSR", 2 },
18751 {"psr", 3 }, {"PSR", 3 },
18752 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18753 {"ipsr", 5 }, {"IPSR", 5 },
18754 {"epsr", 6 }, {"EPSR", 6 },
18755 {"iepsr", 7 }, {"IEPSR", 7 },
18756 {"msp", 8 }, {"MSP", 8 },
18757 {"psp", 9 }, {"PSP", 9 },
18758 {"primask", 16}, {"PRIMASK", 16},
18759 {"basepri", 17}, {"BASEPRI", 17},
18760 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18761 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18762 {"faultmask", 19}, {"FAULTMASK", 19},
18763 {"control", 20}, {"CONTROL", 20}
18766 /* Table of all shift-in-operand names. */
18767 static const struct asm_shift_name shift_names
[] =
18769 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18770 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18771 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18772 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18773 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18774 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18777 /* Table of all explicit relocation names. */
18779 static struct reloc_entry reloc_names
[] =
18781 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18782 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18783 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18784 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18785 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18786 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18787 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18788 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18789 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18790 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18791 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18792 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18793 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18794 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18795 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18796 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18797 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18798 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18802 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18803 static const struct asm_cond conds
[] =
18807 {"cs", 0x2}, {"hs", 0x2},
18808 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18822 #define UL_BARRIER(L,U,CODE,FEAT) \
18823 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18824 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18826 static struct asm_barrier_opt barrier_opt_names
[] =
18828 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18829 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18830 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18831 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18832 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18833 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18834 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18835 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18836 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18837 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18838 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18839 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18840 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18841 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18842 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18843 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18848 /* Table of ARM-format instructions. */
18850 /* Macros for gluing together operand strings. N.B. In all cases
18851 other than OPS0, the trailing OP_stop comes from default
18852 zero-initialization of the unspecified elements of the array. */
18853 #define OPS0() { OP_stop, }
18854 #define OPS1(a) { OP_##a, }
18855 #define OPS2(a,b) { OP_##a,OP_##b, }
18856 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18857 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18858 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18859 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18861 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18862 This is useful when mixing operands for ARM and THUMB, i.e. using the
18863 MIX_ARM_THUMB_OPERANDS macro.
18864 In order to use these macros, prefix the number of operands with _
18866 #define OPS_1(a) { a, }
18867 #define OPS_2(a,b) { a,b, }
18868 #define OPS_3(a,b,c) { a,b,c, }
18869 #define OPS_4(a,b,c,d) { a,b,c,d, }
18870 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18871 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18873 /* These macros abstract out the exact format of the mnemonic table and
18874 save some repeated characters. */
18876 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18877 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18878 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18879 THUMB_VARIANT, do_##ae, do_##te }
18881 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18882 a T_MNEM_xyz enumerator. */
18883 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18884 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18885 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18886 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18888 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18889 infix after the third character. */
18890 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18891 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18892 THUMB_VARIANT, do_##ae, do_##te }
18893 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18894 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18895 THUMB_VARIANT, do_##ae, do_##te }
18896 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18897 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18898 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18899 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18900 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18901 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18902 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18903 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18905 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18906 field is still 0xE. Many of the Thumb variants can be executed
18907 conditionally, so this is checked separately. */
18908 #define TUE(mnem, op, top, nops, ops, ae, te) \
18909 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18910 THUMB_VARIANT, do_##ae, do_##te }
18912 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18913 Used by mnemonics that have very minimal differences in the encoding for
18914 ARM and Thumb variants and can be handled in a common function. */
18915 #define TUEc(mnem, op, top, nops, ops, en) \
18916 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18917 THUMB_VARIANT, do_##en, do_##en }
18919 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18920 condition code field. */
18921 #define TUF(mnem, op, top, nops, ops, ae, te) \
18922 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18923 THUMB_VARIANT, do_##ae, do_##te }
18925 /* ARM-only variants of all the above. */
18926 #define CE(mnem, op, nops, ops, ae) \
18927 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18929 #define C3(mnem, op, nops, ops, ae) \
18930 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18932 /* Legacy mnemonics that always have conditional infix after the third
18934 #define CL(mnem, op, nops, ops, ae) \
18935 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18936 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18938 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18939 #define cCE(mnem, op, nops, ops, ae) \
18940 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18942 /* Legacy coprocessor instructions where conditional infix and conditional
18943 suffix are ambiguous. For consistency this includes all FPA instructions,
18944 not just the potentially ambiguous ones. */
18945 #define cCL(mnem, op, nops, ops, ae) \
18946 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18947 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18949 /* Coprocessor, takes either a suffix or a position-3 infix
18950 (for an FPA corner case). */
18951 #define C3E(mnem, op, nops, ops, ae) \
18952 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18953 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18955 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18956 { m1 #m2 m3, OPS##nops ops, \
18957 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18958 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18960 #define CM(m1, m2, op, nops, ops, ae) \
18961 xCM_ (m1, , m2, op, nops, ops, ae), \
18962 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18963 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18964 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18965 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18966 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18967 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18968 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18969 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18970 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18971 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18972 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18973 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18974 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18975 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18976 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18977 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18978 xCM_ (m1, le, m2, op, nops, ops, ae), \
18979 xCM_ (m1, al, m2, op, nops, ops, ae)
18981 #define UE(mnem, op, nops, ops, ae) \
18982 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18984 #define UF(mnem, op, nops, ops, ae) \
18985 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18987 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18988 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18989 use the same encoding function for each. */
18990 #define NUF(mnem, op, nops, ops, enc) \
18991 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18992 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18994 /* Neon data processing, version which indirects through neon_enc_tab for
18995 the various overloaded versions of opcodes. */
18996 #define nUF(mnem, op, nops, ops, enc) \
18997 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18998 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19000 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19002 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19003 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19004 THUMB_VARIANT, do_##enc, do_##enc }
19006 #define NCE(mnem, op, nops, ops, enc) \
19007 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19009 #define NCEF(mnem, op, nops, ops, enc) \
19010 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19012 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19013 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19014 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19015 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19017 #define nCE(mnem, op, nops, ops, enc) \
19018 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19020 #define nCEF(mnem, op, nops, ops, enc) \
19021 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19025 static const struct asm_opcode insns
[] =
19027 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19028 #define THUMB_VARIANT & arm_ext_v4t
19029 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19030 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19031 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19032 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19033 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19034 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19035 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19036 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19037 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19038 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19039 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19040 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19041 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19042 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19043 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19044 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19046 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19047 for setting PSR flag bits. They are obsolete in V6 and do not
19048 have Thumb equivalents. */
19049 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19050 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19051 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19052 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19053 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19054 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19055 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19056 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19057 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19059 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19060 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19061 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19062 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19064 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19065 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19066 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19068 OP_ADDRGLDR
),ldst
, t_ldst
),
19069 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19071 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19072 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19073 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19074 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19075 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19076 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19078 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19079 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19080 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19081 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19084 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19085 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19086 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19087 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19089 /* Thumb-compatibility pseudo ops. */
19090 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19091 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19092 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19093 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19094 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19095 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19096 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19097 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19098 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19099 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19100 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19101 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19103 /* These may simplify to neg. */
19104 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19105 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19107 #undef THUMB_VARIANT
19108 #define THUMB_VARIANT & arm_ext_v6
19110 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19112 /* V1 instructions with no Thumb analogue prior to V6T2. */
19113 #undef THUMB_VARIANT
19114 #define THUMB_VARIANT & arm_ext_v6t2
19116 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19117 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19118 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19120 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19121 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19122 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19123 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19125 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19126 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19128 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19129 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19131 /* V1 instructions with no Thumb analogue at all. */
19132 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19133 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19135 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19136 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19137 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19138 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19139 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19140 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19141 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19142 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19145 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19146 #undef THUMB_VARIANT
19147 #define THUMB_VARIANT & arm_ext_v4t
19149 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19150 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19152 #undef THUMB_VARIANT
19153 #define THUMB_VARIANT & arm_ext_v6t2
19155 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19156 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19158 /* Generic coprocessor instructions. */
19159 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19160 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19161 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19162 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19163 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19164 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19165 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19168 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19170 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19171 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19174 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19175 #undef THUMB_VARIANT
19176 #define THUMB_VARIANT & arm_ext_msr
19178 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19179 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19182 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19183 #undef THUMB_VARIANT
19184 #define THUMB_VARIANT & arm_ext_v6t2
19186 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19187 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19188 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19189 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19190 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19191 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19192 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19193 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19196 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19197 #undef THUMB_VARIANT
19198 #define THUMB_VARIANT & arm_ext_v4t
19200 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19201 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19202 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19203 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19204 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19205 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19208 #define ARM_VARIANT & arm_ext_v4t_5
19210 /* ARM Architecture 4T. */
19211 /* Note: bx (and blx) are required on V5, even if the processor does
19212 not support Thumb. */
19213 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19216 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19217 #undef THUMB_VARIANT
19218 #define THUMB_VARIANT & arm_ext_v5t
19220 /* Note: blx has 2 variants; the .value coded here is for
19221 BLX(2). Only this variant has conditional execution. */
19222 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19223 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19225 #undef THUMB_VARIANT
19226 #define THUMB_VARIANT & arm_ext_v6t2
19228 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19229 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19230 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19231 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19232 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19233 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19234 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19235 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19238 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19239 #undef THUMB_VARIANT
19240 #define THUMB_VARIANT & arm_ext_v5exp
19242 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19243 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19244 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19245 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19247 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19248 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19250 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19251 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19252 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19253 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19255 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19256 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19257 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19258 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19260 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19261 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19263 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19264 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19265 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19266 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19269 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19270 #undef THUMB_VARIANT
19271 #define THUMB_VARIANT & arm_ext_v6t2
19273 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19274 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19276 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19277 ADDRGLDRS
), ldrd
, t_ldstd
),
19279 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19280 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19283 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19285 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19288 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19289 #undef THUMB_VARIANT
19290 #define THUMB_VARIANT & arm_ext_v6
19292 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19293 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19294 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19295 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19296 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19297 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19298 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19299 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19300 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19301 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19303 #undef THUMB_VARIANT
19304 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19306 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19307 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19309 #undef THUMB_VARIANT
19310 #define THUMB_VARIANT & arm_ext_v6t2
19312 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19313 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19315 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19316 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19318 /* ARM V6 not included in V7M. */
19319 #undef THUMB_VARIANT
19320 #define THUMB_VARIANT & arm_ext_v6_notm
19321 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19322 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19323 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19324 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19325 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19326 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19327 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19328 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19329 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19330 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19331 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19332 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19333 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19334 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19335 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19336 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19337 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19338 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19339 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19341 /* ARM V6 not included in V7M (eg. integer SIMD). */
19342 #undef THUMB_VARIANT
19343 #define THUMB_VARIANT & arm_ext_v6_dsp
19344 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19345 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19346 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19347 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19348 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19349 /* Old name for QASX. */
19350 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19351 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19352 /* Old name for QSAX. */
19353 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19354 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19355 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19356 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19357 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19358 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19359 /* Old name for SASX. */
19360 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19361 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19362 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19363 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19364 /* Old name for SHASX. */
19365 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19366 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19367 /* Old name for SHSAX. */
19368 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19369 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19370 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19371 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19372 /* Old name for SSAX. */
19373 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19374 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19375 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19376 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19377 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19378 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19379 /* Old name for UASX. */
19380 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19381 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19382 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19383 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19384 /* Old name for UHASX. */
19385 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19386 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19387 /* Old name for UHSAX. */
19388 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19389 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19390 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19391 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19392 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19393 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19394 /* Old name for UQASX. */
19395 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19396 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19397 /* Old name for UQSAX. */
19398 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19399 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19400 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19401 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19402 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19403 /* Old name for USAX. */
19404 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19405 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19406 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19407 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19408 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19409 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19410 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19411 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19412 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19413 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19414 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19415 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19416 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19417 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19418 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19419 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19420 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19421 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19422 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19423 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19424 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19425 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19426 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19427 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19428 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19429 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19430 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19431 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19432 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19433 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19434 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19435 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19436 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19437 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19440 #define ARM_VARIANT & arm_ext_v6k
19441 #undef THUMB_VARIANT
19442 #define THUMB_VARIANT & arm_ext_v6k
19444 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19445 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19446 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19447 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19449 #undef THUMB_VARIANT
19450 #define THUMB_VARIANT & arm_ext_v6_notm
19451 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19453 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19454 RRnpcb
), strexd
, t_strexd
),
19456 #undef THUMB_VARIANT
19457 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19458 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19460 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19462 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19464 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19466 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19469 #define ARM_VARIANT & arm_ext_sec
19470 #undef THUMB_VARIANT
19471 #define THUMB_VARIANT & arm_ext_sec
19473 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19476 #define ARM_VARIANT & arm_ext_virt
19477 #undef THUMB_VARIANT
19478 #define THUMB_VARIANT & arm_ext_virt
19480 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19481 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19484 #define ARM_VARIANT & arm_ext_pan
19485 #undef THUMB_VARIANT
19486 #define THUMB_VARIANT & arm_ext_pan
19488 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19491 #define ARM_VARIANT & arm_ext_v6t2
19492 #undef THUMB_VARIANT
19493 #define THUMB_VARIANT & arm_ext_v6t2
19495 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19496 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19497 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19498 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19500 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19501 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19503 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19504 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19505 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19506 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19508 #undef THUMB_VARIANT
19509 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19510 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19511 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19513 /* Thumb-only instructions. */
19515 #define ARM_VARIANT NULL
19516 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19517 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19519 /* ARM does not really have an IT instruction, so always allow it.
19520 The opcode is copied from Thumb in order to allow warnings in
19521 -mimplicit-it=[never | arm] modes. */
19523 #define ARM_VARIANT & arm_ext_v1
19524 #undef THUMB_VARIANT
19525 #define THUMB_VARIANT & arm_ext_v6t2
19527 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19528 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19529 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19530 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19531 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19532 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19533 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19534 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19535 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19536 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19537 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19538 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19539 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19540 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19541 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19542 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19543 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19544 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19546 /* Thumb2 only instructions. */
19548 #define ARM_VARIANT NULL
19550 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19551 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19552 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19553 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19554 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19555 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19557 /* Hardware division instructions. */
19559 #define ARM_VARIANT & arm_ext_adiv
19560 #undef THUMB_VARIANT
19561 #define THUMB_VARIANT & arm_ext_div
19563 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19564 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19566 /* ARM V6M/V7 instructions. */
19568 #define ARM_VARIANT & arm_ext_barrier
19569 #undef THUMB_VARIANT
19570 #define THUMB_VARIANT & arm_ext_barrier
19572 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19573 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19574 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19576 /* ARM V7 instructions. */
19578 #define ARM_VARIANT & arm_ext_v7
19579 #undef THUMB_VARIANT
19580 #define THUMB_VARIANT & arm_ext_v7
19582 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19583 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19586 #define ARM_VARIANT & arm_ext_mp
19587 #undef THUMB_VARIANT
19588 #define THUMB_VARIANT & arm_ext_mp
19590 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19592 /* AArchv8 instructions. */
19594 #define ARM_VARIANT & arm_ext_v8
19596 /* Instructions shared between armv8-a and armv8-m. */
19597 #undef THUMB_VARIANT
19598 #define THUMB_VARIANT & arm_ext_atomics
19600 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19601 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19602 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19603 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19604 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19605 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19606 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19607 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19608 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19609 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19611 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19613 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19615 #undef THUMB_VARIANT
19616 #define THUMB_VARIANT & arm_ext_v8
19618 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19619 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19620 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19622 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19624 /* ARMv8 T32 only. */
19626 #define ARM_VARIANT NULL
19627 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19628 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19629 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19631 /* FP for ARMv8. */
19633 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19634 #undef THUMB_VARIANT
19635 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19637 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19638 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19639 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19640 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19641 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19642 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19643 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19644 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19645 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19646 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19647 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19648 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19649 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19650 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19651 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19652 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19653 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19655 /* Crypto v1 extensions. */
19657 #define ARM_VARIANT & fpu_crypto_ext_armv8
19658 #undef THUMB_VARIANT
19659 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19661 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19662 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19663 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19664 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19665 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19666 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19667 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19668 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19669 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19670 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19671 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19672 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19673 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19674 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19677 #define ARM_VARIANT & crc_ext_armv8
19678 #undef THUMB_VARIANT
19679 #define THUMB_VARIANT & crc_ext_armv8
19680 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19681 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19682 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19683 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19684 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19685 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19687 /* ARMv8.2 RAS extension. */
19689 #define ARM_VARIANT & arm_ext_v8_2
19690 #undef THUMB_VARIANT
19691 #define THUMB_VARIANT & arm_ext_v8_2
19692 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19695 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19696 #undef THUMB_VARIANT
19697 #define THUMB_VARIANT NULL
19699 cCE("wfs", e200110
, 1, (RR
), rd
),
19700 cCE("rfs", e300110
, 1, (RR
), rd
),
19701 cCE("wfc", e400110
, 1, (RR
), rd
),
19702 cCE("rfc", e500110
, 1, (RR
), rd
),
19704 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19705 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19706 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19707 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19709 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19710 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19711 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19712 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19714 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19715 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19716 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19717 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19718 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19719 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19720 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19721 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19722 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19723 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19724 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19725 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19727 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19728 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19729 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19730 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19731 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19732 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19733 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19734 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19735 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19736 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19737 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19738 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19740 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19741 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19742 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19743 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19744 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19745 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19748 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19749 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19923 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19924 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19925 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19926 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19927 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19928 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19929 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19930 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19931 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19932 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19933 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19935 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19936 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19937 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19938 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19939 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19940 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19941 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19942 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19943 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19944 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19945 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19946 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19948 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19949 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19950 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19951 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19952 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19953 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19956 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19957 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20092 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20093 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20094 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20096 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20097 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20098 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20099 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20100 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20101 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20102 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20103 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20104 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20105 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20106 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20107 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20109 /* The implementation of the FIX instruction is broken on some
20110 assemblers, in that it accepts a precision specifier as well as a
20111 rounding specifier, despite the fact that this is meaningless.
20112 To be more compatible, we accept it as well, though of course it
20113 does not set any bits. */
20114 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20115 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20116 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20117 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20118 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20119 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20120 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20121 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20122 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20123 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20124 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20125 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20126 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20128 /* Instructions that were new with the real FPA, call them V2. */
20130 #define ARM_VARIANT & fpu_fpa_ext_v2
20132 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20133 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20134 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20135 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20136 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20137 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20140 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20142 /* Moves and type conversions. */
20143 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20144 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20145 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20146 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20147 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20148 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20149 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20150 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20151 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20152 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20153 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20154 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20155 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20156 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20158 /* Memory operations. */
20159 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20160 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20161 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20162 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20163 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20164 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20165 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20166 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20167 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20168 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20169 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20170 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20171 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20172 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20173 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20174 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20175 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20176 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20178 /* Monadic operations. */
20179 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20180 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20181 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20183 /* Dyadic operations. */
20184 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20185 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20186 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20187 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20188 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20189 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20190 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20191 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20192 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20195 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20196 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20197 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20198 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20200 /* Double precision load/store are still present on single precision
20201 implementations. */
20202 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20203 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20204 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20205 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20206 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20207 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20208 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20209 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20210 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20211 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20214 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20216 /* Moves and type conversions. */
20217 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20218 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20219 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20220 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20221 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20222 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20223 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20224 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20225 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20226 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20227 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20228 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20229 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20231 /* Monadic operations. */
20232 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20233 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20234 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20236 /* Dyadic operations. */
20237 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20238 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20239 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20240 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20241 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20242 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20243 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20244 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20245 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20248 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20249 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20250 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20251 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20254 #define ARM_VARIANT & fpu_vfp_ext_v2
20256 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20257 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20258 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20259 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20261 /* Instructions which may belong to either the Neon or VFP instruction sets.
20262 Individual encoder functions perform additional architecture checks. */
20264 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20265 #undef THUMB_VARIANT
20266 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20268 /* These mnemonics are unique to VFP. */
20269 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20270 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20271 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20272 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20273 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20274 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20275 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20276 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20277 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20278 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20280 /* Mnemonics shared by Neon and VFP. */
20281 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20282 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20283 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20285 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20286 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20288 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20289 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20291 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20292 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20293 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20294 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20295 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20296 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20297 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20298 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20300 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20301 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20302 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20303 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20306 /* NOTE: All VMOV encoding is special-cased! */
20307 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20308 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20311 #define ARM_VARIANT & arm_ext_fp16
20312 #undef THUMB_VARIANT
20313 #define THUMB_VARIANT & arm_ext_fp16
20314 /* New instructions added from v8.2, allowing the extraction and insertion of
20315 the upper 16 bits of a 32-bit vector register. */
20316 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20317 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20319 #undef THUMB_VARIANT
20320 #define THUMB_VARIANT & fpu_neon_ext_v1
20322 #define ARM_VARIANT & fpu_neon_ext_v1
20324 /* Data processing with three registers of the same length. */
20325 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20326 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20327 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20328 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20329 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20330 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20331 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20332 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20333 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20334 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20335 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20336 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20337 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20338 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20339 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20340 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20341 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20342 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20343 /* If not immediate, fall back to neon_dyadic_i64_su.
20344 shl_imm should accept I8 I16 I32 I64,
20345 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20346 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20347 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20348 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20349 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20350 /* Logic ops, types optional & ignored. */
20351 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20352 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20353 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20354 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20355 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20356 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20357 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20358 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20359 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20360 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20361 /* Bitfield ops, untyped. */
20362 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20363 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20364 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20365 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20366 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20367 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20368 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20369 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20370 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20371 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20372 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20373 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20374 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20375 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20376 back to neon_dyadic_if_su. */
20377 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20378 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20379 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20380 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20381 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20382 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20383 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20384 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20385 /* Comparison. Type I8 I16 I32 F32. */
20386 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20387 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20388 /* As above, D registers only. */
20389 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20390 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20391 /* Int and float variants, signedness unimportant. */
20392 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20393 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20394 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20395 /* Add/sub take types I8 I16 I32 I64 F32. */
20396 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20397 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20398 /* vtst takes sizes 8, 16, 32. */
20399 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20400 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20401 /* VMUL takes I8 I16 I32 F32 P8. */
20402 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20403 /* VQD{R}MULH takes S16 S32. */
20404 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20405 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20406 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20407 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20408 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20409 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20410 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20411 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20412 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20413 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20414 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20415 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20416 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20417 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20418 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20419 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20420 /* ARM v8.1 extension. */
20421 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20422 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20423 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20424 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20426 /* Two address, int/float. Types S8 S16 S32 F32. */
20427 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20428 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20430 /* Data processing with two registers and a shift amount. */
20431 /* Right shifts, and variants with rounding.
20432 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20433 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20434 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20435 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20436 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20437 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20438 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20439 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20440 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20441 /* Shift and insert. Sizes accepted 8 16 32 64. */
20442 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20443 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20444 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20445 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20446 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20447 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20448 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20449 /* Right shift immediate, saturating & narrowing, with rounding variants.
20450 Types accepted S16 S32 S64 U16 U32 U64. */
20451 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20452 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20453 /* As above, unsigned. Types accepted S16 S32 S64. */
20454 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20455 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20456 /* Right shift narrowing. Types accepted I16 I32 I64. */
20457 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20458 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20459 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20460 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20461 /* CVT with optional immediate for fixed-point variant. */
20462 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20464 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20465 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20467 /* Data processing, three registers of different lengths. */
20468 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20469 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20470 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20471 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20472 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20473 /* If not scalar, fall back to neon_dyadic_long.
20474 Vector types as above, scalar types S16 S32 U16 U32. */
20475 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20476 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20477 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20478 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20479 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20480 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20481 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20482 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20483 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20484 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20485 /* Saturating doubling multiplies. Types S16 S32. */
20486 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20487 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20488 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20489 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20490 S16 S32 U16 U32. */
20491 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20493 /* Extract. Size 8. */
20494 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20495 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20497 /* Two registers, miscellaneous. */
20498 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20499 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20500 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20501 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20502 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20503 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20504 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20505 /* Vector replicate. Sizes 8 16 32. */
20506 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20507 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20508 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20509 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20510 /* VMOVN. Types I16 I32 I64. */
20511 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20512 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20513 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20514 /* VQMOVUN. Types S16 S32 S64. */
20515 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20516 /* VZIP / VUZP. Sizes 8 16 32. */
20517 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20518 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20519 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20520 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20521 /* VQABS / VQNEG. Types S8 S16 S32. */
20522 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20523 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20524 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20525 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20526 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20527 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20528 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20529 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20530 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20531 /* Reciprocal estimates. Types U32 F16 F32. */
20532 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20533 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20534 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20535 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20536 /* VCLS. Types S8 S16 S32. */
20537 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20538 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20539 /* VCLZ. Types I8 I16 I32. */
20540 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20541 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20542 /* VCNT. Size 8. */
20543 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20544 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20545 /* Two address, untyped. */
20546 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20547 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20548 /* VTRN. Sizes 8 16 32. */
20549 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20550 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20552 /* Table lookup. Size 8. */
20553 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20554 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20556 #undef THUMB_VARIANT
20557 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20559 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20561 /* Neon element/structure load/store. */
20562 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20563 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20564 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20565 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20566 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20567 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20568 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20569 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20571 #undef THUMB_VARIANT
20572 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20574 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20575 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20576 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20577 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20578 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20579 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20580 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20581 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20582 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20583 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20585 #undef THUMB_VARIANT
20586 #define THUMB_VARIANT & fpu_vfp_ext_v3
20588 #define ARM_VARIANT & fpu_vfp_ext_v3
20590 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20591 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20592 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20593 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20594 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20595 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20596 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20597 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20598 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20601 #define ARM_VARIANT & fpu_vfp_ext_fma
20602 #undef THUMB_VARIANT
20603 #define THUMB_VARIANT & fpu_vfp_ext_fma
20604 /* Mnemonics shared by Neon and VFP. These are included in the
20605 VFP FMA variant; NEON and VFP FMA always includes the NEON
20606 FMA instructions. */
20607 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20608 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20609 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20610 the v form should always be used. */
20611 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20612 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20613 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20614 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20615 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20616 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20618 #undef THUMB_VARIANT
20620 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20622 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20623 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20624 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20625 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20626 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20627 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20628 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20629 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20632 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20634 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20635 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20636 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20637 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20638 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20639 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20640 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20641 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20642 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20643 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20644 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20645 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20646 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20647 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20648 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20649 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20650 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20651 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20652 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20653 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20654 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20655 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20656 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20657 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20658 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20659 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20660 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20661 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20662 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20663 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20664 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20665 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20666 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20667 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20668 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20669 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20670 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20671 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20672 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20673 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20674 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20675 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20676 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20677 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20678 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20679 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20680 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20681 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20682 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20683 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20684 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20685 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20686 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20687 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20688 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20689 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20690 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20691 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20692 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20693 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20694 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20695 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20696 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20697 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20698 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20699 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20700 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20701 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20702 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20703 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20704 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20705 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20706 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20707 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20708 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20709 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20710 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20711 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20712 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20713 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20714 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20715 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20716 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20717 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20718 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20723 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20728 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20729 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20730 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20731 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20732 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20733 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20734 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20735 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20736 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20737 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20738 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20739 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20740 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20745 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20746 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20747 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20748 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20749 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20750 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20751 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20752 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20753 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20754 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20755 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20756 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20757 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20758 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20759 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20760 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20761 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20762 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20763 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20764 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20765 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20766 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20767 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20768 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20771 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20772 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20773 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20774 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20775 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20776 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20777 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20778 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20779 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20780 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20781 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20782 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20786 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20787 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20788 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20789 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20790 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20791 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20792 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20793 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20794 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20795 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20798 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20800 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20801 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20802 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20803 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20804 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20805 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20806 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20808 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20809 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20810 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20811 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20812 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20813 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20814 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20815 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20816 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20817 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20818 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20819 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20821 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20823 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20824 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20825 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20826 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20827 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20828 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20829 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20830 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20831 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20832 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20833 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20834 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20835 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20836 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20837 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20841 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20842 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20843 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20844 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20845 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20846 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20861 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20862 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20863 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20864 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20865 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20866 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20867 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20868 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20869 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20870 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20871 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20872 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20873 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20874 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20875 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20876 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20877 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20878 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20879 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20880 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20881 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20882 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20883 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20884 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20885 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20886 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20887 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20888 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20889 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20890 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20891 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20892 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20893 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20894 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20895 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20896 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20897 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20898 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20899 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20900 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20901 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20902 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20903 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20904 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20905 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20906 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20907 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20908 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20909 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20910 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20911 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20912 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20913 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20914 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20915 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20916 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20917 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20918 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20919 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20920 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20921 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20922 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20923 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20924 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20925 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20926 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20927 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20928 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20929 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20930 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20931 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20932 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20933 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20934 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20935 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20936 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20939 #define ARM_VARIANT NULL
20940 #undef THUMB_VARIANT
20941 #define THUMB_VARIANT & arm_ext_v8m
20942 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20943 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20946 #undef THUMB_VARIANT
20972 /* MD interface: bits in the object file. */
20974 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20975 for use in the a.out file, and stores them in the array pointed to by buf.
20976 This knows about the endian-ness of the target machine and does
20977 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20978 2 (short) and 4 (long) Floating numbers are put out as a series of
20979 LITTLENUMS (shorts, here at least). */
20982 md_number_to_chars (char * buf
, valueT val
, int n
)
20984 if (target_big_endian
)
20985 number_to_chars_bigendian (buf
, val
, n
);
20987 number_to_chars_littleendian (buf
, val
, n
);
20991 md_chars_to_number (char * buf
, int n
)
20994 unsigned char * where
= (unsigned char *) buf
;
20996 if (target_big_endian
)
21001 result
|= (*where
++ & 255);
21009 result
|= (where
[n
] & 255);
21016 /* MD interface: Sections. */
21018 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21019 that an rs_machine_dependent frag may reach. */
21022 arm_frag_max_var (fragS
*fragp
)
21024 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21025 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21027 Note that we generate relaxable instructions even for cases that don't
21028 really need it, like an immediate that's a trivial constant. So we're
21029 overestimating the instruction size for some of those cases. Rather
21030 than putting more intelligence here, it would probably be better to
21031 avoid generating a relaxation frag in the first place when it can be
21032 determined up front that a short instruction will suffice. */
21034 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21038 /* Estimate the size of a frag before relaxing. Assume everything fits in
21042 md_estimate_size_before_relax (fragS
* fragp
,
21043 segT segtype ATTRIBUTE_UNUSED
)
21049 /* Convert a machine dependent frag. */
21052 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21054 unsigned long insn
;
21055 unsigned long old_op
;
21063 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21065 old_op
= bfd_get_16(abfd
, buf
);
21066 if (fragp
->fr_symbol
)
21068 exp
.X_op
= O_symbol
;
21069 exp
.X_add_symbol
= fragp
->fr_symbol
;
21073 exp
.X_op
= O_constant
;
21075 exp
.X_add_number
= fragp
->fr_offset
;
21076 opcode
= fragp
->fr_subtype
;
21079 case T_MNEM_ldr_pc
:
21080 case T_MNEM_ldr_pc2
:
21081 case T_MNEM_ldr_sp
:
21082 case T_MNEM_str_sp
:
21089 if (fragp
->fr_var
== 4)
21091 insn
= THUMB_OP32 (opcode
);
21092 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21094 insn
|= (old_op
& 0x700) << 4;
21098 insn
|= (old_op
& 7) << 12;
21099 insn
|= (old_op
& 0x38) << 13;
21101 insn
|= 0x00000c00;
21102 put_thumb32_insn (buf
, insn
);
21103 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21107 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21109 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21112 if (fragp
->fr_var
== 4)
21114 insn
= THUMB_OP32 (opcode
);
21115 insn
|= (old_op
& 0xf0) << 4;
21116 put_thumb32_insn (buf
, insn
);
21117 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21121 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21122 exp
.X_add_number
-= 4;
21130 if (fragp
->fr_var
== 4)
21132 int r0off
= (opcode
== T_MNEM_mov
21133 || opcode
== T_MNEM_movs
) ? 0 : 8;
21134 insn
= THUMB_OP32 (opcode
);
21135 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21136 insn
|= (old_op
& 0x700) << r0off
;
21137 put_thumb32_insn (buf
, insn
);
21138 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21142 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21147 if (fragp
->fr_var
== 4)
21149 insn
= THUMB_OP32(opcode
);
21150 put_thumb32_insn (buf
, insn
);
21151 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21154 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21158 if (fragp
->fr_var
== 4)
21160 insn
= THUMB_OP32(opcode
);
21161 insn
|= (old_op
& 0xf00) << 14;
21162 put_thumb32_insn (buf
, insn
);
21163 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21166 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21169 case T_MNEM_add_sp
:
21170 case T_MNEM_add_pc
:
21171 case T_MNEM_inc_sp
:
21172 case T_MNEM_dec_sp
:
21173 if (fragp
->fr_var
== 4)
21175 /* ??? Choose between add and addw. */
21176 insn
= THUMB_OP32 (opcode
);
21177 insn
|= (old_op
& 0xf0) << 4;
21178 put_thumb32_insn (buf
, insn
);
21179 if (opcode
== T_MNEM_add_pc
)
21180 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21182 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21185 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21193 if (fragp
->fr_var
== 4)
21195 insn
= THUMB_OP32 (opcode
);
21196 insn
|= (old_op
& 0xf0) << 4;
21197 insn
|= (old_op
& 0xf) << 16;
21198 put_thumb32_insn (buf
, insn
);
21199 if (insn
& (1 << 20))
21200 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21202 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21205 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21211 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21212 (enum bfd_reloc_code_real
) reloc_type
);
21213 fixp
->fx_file
= fragp
->fr_file
;
21214 fixp
->fx_line
= fragp
->fr_line
;
21215 fragp
->fr_fix
+= fragp
->fr_var
;
21217 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21218 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21219 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21220 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21223 /* Return the size of a relaxable immediate operand instruction.
21224 SHIFT and SIZE specify the form of the allowable immediate. */
21226 relax_immediate (fragS
*fragp
, int size
, int shift
)
21232 /* ??? Should be able to do better than this. */
21233 if (fragp
->fr_symbol
)
21236 low
= (1 << shift
) - 1;
21237 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21238 offset
= fragp
->fr_offset
;
21239 /* Force misaligned offsets to 32-bit variant. */
21242 if (offset
& ~mask
)
21247 /* Get the address of a symbol during relaxation. */
21249 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21255 sym
= fragp
->fr_symbol
;
21256 sym_frag
= symbol_get_frag (sym
);
21257 know (S_GET_SEGMENT (sym
) != absolute_section
21258 || sym_frag
== &zero_address_frag
);
21259 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21261 /* If frag has yet to be reached on this pass, assume it will
21262 move by STRETCH just as we did. If this is not so, it will
21263 be because some frag between grows, and that will force
21267 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21271 /* Adjust stretch for any alignment frag. Note that if have
21272 been expanding the earlier code, the symbol may be
21273 defined in what appears to be an earlier frag. FIXME:
21274 This doesn't handle the fr_subtype field, which specifies
21275 a maximum number of bytes to skip when doing an
21277 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21279 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21282 stretch
= - ((- stretch
)
21283 & ~ ((1 << (int) f
->fr_offset
) - 1));
21285 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21297 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21300 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21305 /* Assume worst case for symbols not known to be in the same section. */
21306 if (fragp
->fr_symbol
== NULL
21307 || !S_IS_DEFINED (fragp
->fr_symbol
)
21308 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21309 || S_IS_WEAK (fragp
->fr_symbol
))
21312 val
= relaxed_symbol_addr (fragp
, stretch
);
21313 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21314 addr
= (addr
+ 4) & ~3;
21315 /* Force misaligned targets to 32-bit variant. */
21319 if (val
< 0 || val
> 1020)
21324 /* Return the size of a relaxable add/sub immediate instruction. */
21326 relax_addsub (fragS
*fragp
, asection
*sec
)
21331 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21332 op
= bfd_get_16(sec
->owner
, buf
);
21333 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21334 return relax_immediate (fragp
, 8, 0);
21336 return relax_immediate (fragp
, 3, 0);
21339 /* Return TRUE iff the definition of symbol S could be pre-empted
21340 (overridden) at link or load time. */
21342 symbol_preemptible (symbolS
*s
)
21344 /* Weak symbols can always be pre-empted. */
21348 /* Non-global symbols cannot be pre-empted. */
21349 if (! S_IS_EXTERNAL (s
))
21353 /* In ELF, a global symbol can be marked protected, or private. In that
21354 case it can't be pre-empted (other definitions in the same link unit
21355 would violate the ODR). */
21356 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21360 /* Other global symbols might be pre-empted. */
21364 /* Return the size of a relaxable branch instruction. BITS is the
21365 size of the offset field in the narrow instruction. */
21368 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21374 /* Assume worst case for symbols not known to be in the same section. */
21375 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21376 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21377 || S_IS_WEAK (fragp
->fr_symbol
))
21381 /* A branch to a function in ARM state will require interworking. */
21382 if (S_IS_DEFINED (fragp
->fr_symbol
)
21383 && ARM_IS_FUNC (fragp
->fr_symbol
))
21387 if (symbol_preemptible (fragp
->fr_symbol
))
21390 val
= relaxed_symbol_addr (fragp
, stretch
);
21391 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21394 /* Offset is a signed value *2 */
21396 if (val
>= limit
|| val
< -limit
)
21402 /* Relax a machine dependent frag. This returns the amount by which
21403 the current size of the frag should change. */
21406 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21411 oldsize
= fragp
->fr_var
;
21412 switch (fragp
->fr_subtype
)
21414 case T_MNEM_ldr_pc2
:
21415 newsize
= relax_adr (fragp
, sec
, stretch
);
21417 case T_MNEM_ldr_pc
:
21418 case T_MNEM_ldr_sp
:
21419 case T_MNEM_str_sp
:
21420 newsize
= relax_immediate (fragp
, 8, 2);
21424 newsize
= relax_immediate (fragp
, 5, 2);
21428 newsize
= relax_immediate (fragp
, 5, 1);
21432 newsize
= relax_immediate (fragp
, 5, 0);
21435 newsize
= relax_adr (fragp
, sec
, stretch
);
21441 newsize
= relax_immediate (fragp
, 8, 0);
21444 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21447 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21449 case T_MNEM_add_sp
:
21450 case T_MNEM_add_pc
:
21451 newsize
= relax_immediate (fragp
, 8, 2);
21453 case T_MNEM_inc_sp
:
21454 case T_MNEM_dec_sp
:
21455 newsize
= relax_immediate (fragp
, 7, 2);
21461 newsize
= relax_addsub (fragp
, sec
);
21467 fragp
->fr_var
= newsize
;
21468 /* Freeze wide instructions that are at or before the same location as
21469 in the previous pass. This avoids infinite loops.
21470 Don't freeze them unconditionally because targets may be artificially
21471 misaligned by the expansion of preceding frags. */
21472 if (stretch
<= 0 && newsize
> 2)
21474 md_convert_frag (sec
->owner
, sec
, fragp
);
21478 return newsize
- oldsize
;
21481 /* Round up a section size to the appropriate boundary. */
21484 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21487 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21488 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21490 /* For a.out, force the section size to be aligned. If we don't do
21491 this, BFD will align it for us, but it will not write out the
21492 final bytes of the section. This may be a bug in BFD, but it is
21493 easier to fix it here since that is how the other a.out targets
21497 align
= bfd_get_section_alignment (stdoutput
, segment
);
21498 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21505 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21506 of an rs_align_code fragment. */
21509 arm_handle_align (fragS
* fragP
)
21511 static char const arm_noop
[2][2][4] =
21514 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21515 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21518 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21519 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21522 static char const thumb_noop
[2][2][2] =
21525 {0xc0, 0x46}, /* LE */
21526 {0x46, 0xc0}, /* BE */
21529 {0x00, 0xbf}, /* LE */
21530 {0xbf, 0x00} /* BE */
21533 static char const wide_thumb_noop
[2][4] =
21534 { /* Wide Thumb-2 */
21535 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21536 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21539 unsigned bytes
, fix
, noop_size
;
21542 const char *narrow_noop
= NULL
;
21547 if (fragP
->fr_type
!= rs_align_code
)
21550 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21551 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21554 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21555 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21557 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21559 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21561 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21562 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21564 narrow_noop
= thumb_noop
[1][target_big_endian
];
21565 noop
= wide_thumb_noop
[target_big_endian
];
21568 noop
= thumb_noop
[0][target_big_endian
];
21576 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21577 ? selected_cpu
: arm_arch_none
,
21579 [target_big_endian
];
21586 fragP
->fr_var
= noop_size
;
21588 if (bytes
& (noop_size
- 1))
21590 fix
= bytes
& (noop_size
- 1);
21592 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21594 memset (p
, 0, fix
);
21601 if (bytes
& noop_size
)
21603 /* Insert a narrow noop. */
21604 memcpy (p
, narrow_noop
, noop_size
);
21606 bytes
-= noop_size
;
21610 /* Use wide noops for the remainder */
21614 while (bytes
>= noop_size
)
21616 memcpy (p
, noop
, noop_size
);
21618 bytes
-= noop_size
;
21622 fragP
->fr_fix
+= fix
;
21625 /* Called from md_do_align. Used to create an alignment
21626 frag in a code section. */
21629 arm_frag_align_code (int n
, int max
)
21633 /* We assume that there will never be a requirement
21634 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21635 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21640 _("alignments greater than %d bytes not supported in .text sections."),
21641 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21642 as_fatal ("%s", err_msg
);
21645 p
= frag_var (rs_align_code
,
21646 MAX_MEM_FOR_RS_ALIGN_CODE
,
21648 (relax_substateT
) max
,
21655 /* Perform target specific initialisation of a frag.
21656 Note - despite the name this initialisation is not done when the frag
21657 is created, but only when its type is assigned. A frag can be created
21658 and used a long time before its type is set, so beware of assuming that
21659 this initialisationis performed first. */
21663 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21665 /* Record whether this frag is in an ARM or a THUMB area. */
21666 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21669 #else /* OBJ_ELF is defined. */
21671 arm_init_frag (fragS
* fragP
, int max_chars
)
21673 int frag_thumb_mode
;
21675 /* If the current ARM vs THUMB mode has not already
21676 been recorded into this frag then do so now. */
21677 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21678 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21680 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21682 /* Record a mapping symbol for alignment frags. We will delete this
21683 later if the alignment ends up empty. */
21684 switch (fragP
->fr_type
)
21687 case rs_align_test
:
21689 mapping_state_2 (MAP_DATA
, max_chars
);
21691 case rs_align_code
:
21692 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21699 /* When we change sections we need to issue a new mapping symbol. */
21702 arm_elf_change_section (void)
21704 /* Link an unlinked unwind index table section to the .text section. */
21705 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21706 && elf_linked_to_section (now_seg
) == NULL
)
21707 elf_linked_to_section (now_seg
) = text_section
;
21711 arm_elf_section_type (const char * str
, size_t len
)
21713 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21714 return SHT_ARM_EXIDX
;
21719 /* Code to deal with unwinding tables. */
21721 static void add_unwind_adjustsp (offsetT
);
21723 /* Generate any deferred unwind frame offset. */
21726 flush_pending_unwind (void)
21730 offset
= unwind
.pending_offset
;
21731 unwind
.pending_offset
= 0;
21733 add_unwind_adjustsp (offset
);
21736 /* Add an opcode to this list for this function. Two-byte opcodes should
21737 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21741 add_unwind_opcode (valueT op
, int length
)
21743 /* Add any deferred stack adjustment. */
21744 if (unwind
.pending_offset
)
21745 flush_pending_unwind ();
21747 unwind
.sp_restored
= 0;
21749 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21751 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21752 if (unwind
.opcodes
)
21753 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21754 unwind
.opcode_alloc
);
21756 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21761 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21763 unwind
.opcode_count
++;
21767 /* Add unwind opcodes to adjust the stack pointer. */
21770 add_unwind_adjustsp (offsetT offset
)
21774 if (offset
> 0x200)
21776 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21781 /* Long form: 0xb2, uleb128. */
21782 /* This might not fit in a word so add the individual bytes,
21783 remembering the list is built in reverse order. */
21784 o
= (valueT
) ((offset
- 0x204) >> 2);
21786 add_unwind_opcode (0, 1);
21788 /* Calculate the uleb128 encoding of the offset. */
21792 bytes
[n
] = o
& 0x7f;
21798 /* Add the insn. */
21800 add_unwind_opcode (bytes
[n
- 1], 1);
21801 add_unwind_opcode (0xb2, 1);
21803 else if (offset
> 0x100)
21805 /* Two short opcodes. */
21806 add_unwind_opcode (0x3f, 1);
21807 op
= (offset
- 0x104) >> 2;
21808 add_unwind_opcode (op
, 1);
21810 else if (offset
> 0)
21812 /* Short opcode. */
21813 op
= (offset
- 4) >> 2;
21814 add_unwind_opcode (op
, 1);
21816 else if (offset
< 0)
21819 while (offset
> 0x100)
21821 add_unwind_opcode (0x7f, 1);
21824 op
= ((offset
- 4) >> 2) | 0x40;
21825 add_unwind_opcode (op
, 1);
21829 /* Finish the list of unwind opcodes for this function. */
21831 finish_unwind_opcodes (void)
21835 if (unwind
.fp_used
)
21837 /* Adjust sp as necessary. */
21838 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21839 flush_pending_unwind ();
21841 /* After restoring sp from the frame pointer. */
21842 op
= 0x90 | unwind
.fp_reg
;
21843 add_unwind_opcode (op
, 1);
21846 flush_pending_unwind ();
21850 /* Start an exception table entry. If idx is nonzero this is an index table
21854 start_unwind_section (const segT text_seg
, int idx
)
21856 const char * text_name
;
21857 const char * prefix
;
21858 const char * prefix_once
;
21859 const char * group_name
;
21863 size_t sec_name_len
;
21870 prefix
= ELF_STRING_ARM_unwind
;
21871 prefix_once
= ELF_STRING_ARM_unwind_once
;
21872 type
= SHT_ARM_EXIDX
;
21876 prefix
= ELF_STRING_ARM_unwind_info
;
21877 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21878 type
= SHT_PROGBITS
;
21881 text_name
= segment_name (text_seg
);
21882 if (streq (text_name
, ".text"))
21885 if (strncmp (text_name
, ".gnu.linkonce.t.",
21886 strlen (".gnu.linkonce.t.")) == 0)
21888 prefix
= prefix_once
;
21889 text_name
+= strlen (".gnu.linkonce.t.");
21892 prefix_len
= strlen (prefix
);
21893 text_len
= strlen (text_name
);
21894 sec_name_len
= prefix_len
+ text_len
;
21895 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21896 memcpy (sec_name
, prefix
, prefix_len
);
21897 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21898 sec_name
[prefix_len
+ text_len
] = '\0';
21904 /* Handle COMDAT group. */
21905 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21907 group_name
= elf_group_name (text_seg
);
21908 if (group_name
== NULL
)
21910 as_bad (_("Group section `%s' has no group signature"),
21911 segment_name (text_seg
));
21912 ignore_rest_of_line ();
21915 flags
|= SHF_GROUP
;
21919 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21921 /* Set the section link for index tables. */
21923 elf_linked_to_section (now_seg
) = text_seg
;
21927 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21928 personality routine data. Returns zero, or the index table value for
21929 an inline entry. */
21932 create_unwind_entry (int have_data
)
21937 /* The current word of data. */
21939 /* The number of bytes left in this word. */
21942 finish_unwind_opcodes ();
21944 /* Remember the current text section. */
21945 unwind
.saved_seg
= now_seg
;
21946 unwind
.saved_subseg
= now_subseg
;
21948 start_unwind_section (now_seg
, 0);
21950 if (unwind
.personality_routine
== NULL
)
21952 if (unwind
.personality_index
== -2)
21955 as_bad (_("handlerdata in cantunwind frame"));
21956 return 1; /* EXIDX_CANTUNWIND. */
21959 /* Use a default personality routine if none is specified. */
21960 if (unwind
.personality_index
== -1)
21962 if (unwind
.opcode_count
> 3)
21963 unwind
.personality_index
= 1;
21965 unwind
.personality_index
= 0;
21968 /* Space for the personality routine entry. */
21969 if (unwind
.personality_index
== 0)
21971 if (unwind
.opcode_count
> 3)
21972 as_bad (_("too many unwind opcodes for personality routine 0"));
21976 /* All the data is inline in the index table. */
21979 while (unwind
.opcode_count
> 0)
21981 unwind
.opcode_count
--;
21982 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21986 /* Pad with "finish" opcodes. */
21988 data
= (data
<< 8) | 0xb0;
21995 /* We get two opcodes "free" in the first word. */
21996 size
= unwind
.opcode_count
- 2;
22000 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22001 if (unwind
.personality_index
!= -1)
22003 as_bad (_("attempt to recreate an unwind entry"));
22007 /* An extra byte is required for the opcode count. */
22008 size
= unwind
.opcode_count
+ 1;
22011 size
= (size
+ 3) >> 2;
22013 as_bad (_("too many unwind opcodes"));
22015 frag_align (2, 0, 0);
22016 record_alignment (now_seg
, 2);
22017 unwind
.table_entry
= expr_build_dot ();
22019 /* Allocate the table entry. */
22020 ptr
= frag_more ((size
<< 2) + 4);
22021 /* PR 13449: Zero the table entries in case some of them are not used. */
22022 memset (ptr
, 0, (size
<< 2) + 4);
22023 where
= frag_now_fix () - ((size
<< 2) + 4);
22025 switch (unwind
.personality_index
)
22028 /* ??? Should this be a PLT generating relocation? */
22029 /* Custom personality routine. */
22030 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22031 BFD_RELOC_ARM_PREL31
);
22036 /* Set the first byte to the number of additional words. */
22037 data
= size
> 0 ? size
- 1 : 0;
22041 /* ABI defined personality routines. */
22043 /* Three opcodes bytes are packed into the first word. */
22050 /* The size and first two opcode bytes go in the first word. */
22051 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22056 /* Should never happen. */
22060 /* Pack the opcodes into words (MSB first), reversing the list at the same
22062 while (unwind
.opcode_count
> 0)
22066 md_number_to_chars (ptr
, data
, 4);
22071 unwind
.opcode_count
--;
22073 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22076 /* Finish off the last word. */
22079 /* Pad with "finish" opcodes. */
22081 data
= (data
<< 8) | 0xb0;
22083 md_number_to_chars (ptr
, data
, 4);
22088 /* Add an empty descriptor if there is no user-specified data. */
22089 ptr
= frag_more (4);
22090 md_number_to_chars (ptr
, 0, 4);
22097 /* Initialize the DWARF-2 unwind information for this procedure. */
22100 tc_arm_frame_initial_instructions (void)
22102 cfi_add_CFA_def_cfa (REG_SP
, 0);
22104 #endif /* OBJ_ELF */
22106 /* Convert REGNAME to a DWARF-2 register number. */
22109 tc_arm_regname_to_dw2regnum (char *regname
)
22111 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22115 /* PR 16694: Allow VFP registers as well. */
22116 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22120 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22129 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22133 exp
.X_op
= O_secrel
;
22134 exp
.X_add_symbol
= symbol
;
22135 exp
.X_add_number
= 0;
22136 emit_expr (&exp
, size
);
22140 /* MD interface: Symbol and relocation handling. */
22142 /* Return the address within the segment that a PC-relative fixup is
22143 relative to. For ARM, PC-relative fixups applied to instructions
22144 are generally relative to the location of the fixup plus 8 bytes.
22145 Thumb branches are offset by 4, and Thumb loads relative to PC
22146 require special handling. */
22149 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22151 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22153 /* If this is pc-relative and we are going to emit a relocation
22154 then we just want to put out any pipeline compensation that the linker
22155 will need. Otherwise we want to use the calculated base.
22156 For WinCE we skip the bias for externals as well, since this
22157 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22159 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22160 || (arm_force_relocation (fixP
)
22162 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22168 switch (fixP
->fx_r_type
)
22170 /* PC relative addressing on the Thumb is slightly odd as the
22171 bottom two bits of the PC are forced to zero for the
22172 calculation. This happens *after* application of the
22173 pipeline offset. However, Thumb adrl already adjusts for
22174 this, so we need not do it again. */
22175 case BFD_RELOC_ARM_THUMB_ADD
:
22178 case BFD_RELOC_ARM_THUMB_OFFSET
:
22179 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22180 case BFD_RELOC_ARM_T32_ADD_PC12
:
22181 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22182 return (base
+ 4) & ~3;
22184 /* Thumb branches are simply offset by +4. */
22185 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22186 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22187 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22188 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22189 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22192 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22194 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22195 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22196 && ARM_IS_FUNC (fixP
->fx_addsy
)
22197 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22198 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22201 /* BLX is like branches above, but forces the low two bits of PC to
22203 case BFD_RELOC_THUMB_PCREL_BLX
:
22205 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22206 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22207 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22208 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22209 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22210 return (base
+ 4) & ~3;
22212 /* ARM mode branches are offset by +8. However, the Windows CE
22213 loader expects the relocation not to take this into account. */
22214 case BFD_RELOC_ARM_PCREL_BLX
:
22216 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22217 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22218 && ARM_IS_FUNC (fixP
->fx_addsy
)
22219 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22220 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22223 case BFD_RELOC_ARM_PCREL_CALL
:
22225 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22226 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22227 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22228 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22229 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22232 case BFD_RELOC_ARM_PCREL_BRANCH
:
22233 case BFD_RELOC_ARM_PCREL_JUMP
:
22234 case BFD_RELOC_ARM_PLT32
:
22236 /* When handling fixups immediately, because we have already
22237 discovered the value of a symbol, or the address of the frag involved
22238 we must account for the offset by +8, as the OS loader will never see the reloc.
22239 see fixup_segment() in write.c
22240 The S_IS_EXTERNAL test handles the case of global symbols.
22241 Those need the calculated base, not just the pipe compensation the linker will need. */
22243 && fixP
->fx_addsy
!= NULL
22244 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22245 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22253 /* ARM mode loads relative to PC are also offset by +8. Unlike
22254 branches, the Windows CE loader *does* expect the relocation
22255 to take this into account. */
22256 case BFD_RELOC_ARM_OFFSET_IMM
:
22257 case BFD_RELOC_ARM_OFFSET_IMM8
:
22258 case BFD_RELOC_ARM_HWLITERAL
:
22259 case BFD_RELOC_ARM_LITERAL
:
22260 case BFD_RELOC_ARM_CP_OFF_IMM
:
22264 /* Other PC-relative relocations are un-offset. */
22270 static bfd_boolean flag_warn_syms
= TRUE
;
22273 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22275 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22276 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22277 does mean that the resulting code might be very confusing to the reader.
22278 Also this warning can be triggered if the user omits an operand before
22279 an immediate address, eg:
22283 GAS treats this as an assignment of the value of the symbol foo to a
22284 symbol LDR, and so (without this code) it will not issue any kind of
22285 warning or error message.
22287 Note - ARM instructions are case-insensitive but the strings in the hash
22288 table are all stored in lower case, so we must first ensure that name is
22290 if (flag_warn_syms
&& arm_ops_hsh
)
22292 char * nbuf
= strdup (name
);
22295 for (p
= nbuf
; *p
; p
++)
22297 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22299 static struct hash_control
* already_warned
= NULL
;
22301 if (already_warned
== NULL
)
22302 already_warned
= hash_new ();
22303 /* Only warn about the symbol once. To keep the code
22304 simple we let hash_insert do the lookup for us. */
22305 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22306 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22315 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22316 Otherwise we have no need to default values of symbols. */
22319 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22322 if (name
[0] == '_' && name
[1] == 'G'
22323 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22327 if (symbol_find (name
))
22328 as_bad (_("GOT already in the symbol table"));
22330 GOT_symbol
= symbol_new (name
, undefined_section
,
22331 (valueT
) 0, & zero_address_frag
);
22341 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22342 computed as two separate immediate values, added together. We
22343 already know that this value cannot be computed by just one ARM
22346 static unsigned int
22347 validate_immediate_twopart (unsigned int val
,
22348 unsigned int * highpart
)
22353 for (i
= 0; i
< 32; i
+= 2)
22354 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22360 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22362 else if (a
& 0xff0000)
22364 if (a
& 0xff000000)
22366 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22370 gas_assert (a
& 0xff000000);
22371 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22374 return (a
& 0xff) | (i
<< 7);
22381 validate_offset_imm (unsigned int val
, int hwse
)
22383 if ((hwse
&& val
> 255) || val
> 4095)
22388 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22389 negative immediate constant by altering the instruction. A bit of
22394 by inverting the second operand, and
22397 by negating the second operand. */
22400 negate_data_op (unsigned long * instruction
,
22401 unsigned long value
)
22404 unsigned long negated
, inverted
;
22406 negated
= encode_arm_immediate (-value
);
22407 inverted
= encode_arm_immediate (~value
);
22409 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22412 /* First negates. */
22413 case OPCODE_SUB
: /* ADD <-> SUB */
22414 new_inst
= OPCODE_ADD
;
22419 new_inst
= OPCODE_SUB
;
22423 case OPCODE_CMP
: /* CMP <-> CMN */
22424 new_inst
= OPCODE_CMN
;
22429 new_inst
= OPCODE_CMP
;
22433 /* Now Inverted ops. */
22434 case OPCODE_MOV
: /* MOV <-> MVN */
22435 new_inst
= OPCODE_MVN
;
22440 new_inst
= OPCODE_MOV
;
22444 case OPCODE_AND
: /* AND <-> BIC */
22445 new_inst
= OPCODE_BIC
;
22450 new_inst
= OPCODE_AND
;
22454 case OPCODE_ADC
: /* ADC <-> SBC */
22455 new_inst
= OPCODE_SBC
;
22460 new_inst
= OPCODE_ADC
;
22464 /* We cannot do anything. */
22469 if (value
== (unsigned) FAIL
)
22472 *instruction
&= OPCODE_MASK
;
22473 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22477 /* Like negate_data_op, but for Thumb-2. */
22479 static unsigned int
22480 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22484 unsigned int negated
, inverted
;
22486 negated
= encode_thumb32_immediate (-value
);
22487 inverted
= encode_thumb32_immediate (~value
);
22489 rd
= (*instruction
>> 8) & 0xf;
22490 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22493 /* ADD <-> SUB. Includes CMP <-> CMN. */
22494 case T2_OPCODE_SUB
:
22495 new_inst
= T2_OPCODE_ADD
;
22499 case T2_OPCODE_ADD
:
22500 new_inst
= T2_OPCODE_SUB
;
22504 /* ORR <-> ORN. Includes MOV <-> MVN. */
22505 case T2_OPCODE_ORR
:
22506 new_inst
= T2_OPCODE_ORN
;
22510 case T2_OPCODE_ORN
:
22511 new_inst
= T2_OPCODE_ORR
;
22515 /* AND <-> BIC. TST has no inverted equivalent. */
22516 case T2_OPCODE_AND
:
22517 new_inst
= T2_OPCODE_BIC
;
22524 case T2_OPCODE_BIC
:
22525 new_inst
= T2_OPCODE_AND
;
22530 case T2_OPCODE_ADC
:
22531 new_inst
= T2_OPCODE_SBC
;
22535 case T2_OPCODE_SBC
:
22536 new_inst
= T2_OPCODE_ADC
;
22540 /* We cannot do anything. */
22545 if (value
== (unsigned int)FAIL
)
22548 *instruction
&= T2_OPCODE_MASK
;
22549 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22553 /* Read a 32-bit thumb instruction from buf. */
22554 static unsigned long
22555 get_thumb32_insn (char * buf
)
22557 unsigned long insn
;
22558 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22559 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22565 /* We usually want to set the low bit on the address of thumb function
22566 symbols. In particular .word foo - . should have the low bit set.
22567 Generic code tries to fold the difference of two symbols to
22568 a constant. Prevent this and force a relocation when the first symbols
22569 is a thumb function. */
22572 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22574 if (op
== O_subtract
22575 && l
->X_op
== O_symbol
22576 && r
->X_op
== O_symbol
22577 && THUMB_IS_FUNC (l
->X_add_symbol
))
22579 l
->X_op
= O_subtract
;
22580 l
->X_op_symbol
= r
->X_add_symbol
;
22581 l
->X_add_number
-= r
->X_add_number
;
22585 /* Process as normal. */
22589 /* Encode Thumb2 unconditional branches and calls. The encoding
22590 for the 2 are identical for the immediate values. */
22593 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22595 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22598 addressT S
, I1
, I2
, lo
, hi
;
22600 S
= (value
>> 24) & 0x01;
22601 I1
= (value
>> 23) & 0x01;
22602 I2
= (value
>> 22) & 0x01;
22603 hi
= (value
>> 12) & 0x3ff;
22604 lo
= (value
>> 1) & 0x7ff;
22605 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22606 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22607 newval
|= (S
<< 10) | hi
;
22608 newval2
&= ~T2I1I2MASK
;
22609 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22610 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22611 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22615 md_apply_fix (fixS
* fixP
,
22619 offsetT value
= * valP
;
22621 unsigned int newimm
;
22622 unsigned long temp
;
22624 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22626 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22628 /* Note whether this will delete the relocation. */
22630 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22633 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22634 consistency with the behaviour on 32-bit hosts. Remember value
22636 value
&= 0xffffffff;
22637 value
^= 0x80000000;
22638 value
-= 0x80000000;
22641 fixP
->fx_addnumber
= value
;
22643 /* Same treatment for fixP->fx_offset. */
22644 fixP
->fx_offset
&= 0xffffffff;
22645 fixP
->fx_offset
^= 0x80000000;
22646 fixP
->fx_offset
-= 0x80000000;
22648 switch (fixP
->fx_r_type
)
22650 case BFD_RELOC_NONE
:
22651 /* This will need to go in the object file. */
22655 case BFD_RELOC_ARM_IMMEDIATE
:
22656 /* We claim that this fixup has been processed here,
22657 even if in fact we generate an error because we do
22658 not have a reloc for it, so tc_gen_reloc will reject it. */
22661 if (fixP
->fx_addsy
)
22663 const char *msg
= 0;
22665 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22666 msg
= _("undefined symbol %s used as an immediate value");
22667 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22668 msg
= _("symbol %s is in a different section");
22669 else if (S_IS_WEAK (fixP
->fx_addsy
))
22670 msg
= _("symbol %s is weak and may be overridden later");
22674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22675 msg
, S_GET_NAME (fixP
->fx_addsy
));
22680 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22682 /* If the offset is negative, we should use encoding A2 for ADR. */
22683 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22684 newimm
= negate_data_op (&temp
, value
);
22687 newimm
= encode_arm_immediate (value
);
22689 /* If the instruction will fail, see if we can fix things up by
22690 changing the opcode. */
22691 if (newimm
== (unsigned int) FAIL
)
22692 newimm
= negate_data_op (&temp
, value
);
22695 if (newimm
== (unsigned int) FAIL
)
22697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22698 _("invalid constant (%lx) after fixup"),
22699 (unsigned long) value
);
22703 newimm
|= (temp
& 0xfffff000);
22704 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22707 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22709 unsigned int highpart
= 0;
22710 unsigned int newinsn
= 0xe1a00000; /* nop. */
22712 if (fixP
->fx_addsy
)
22714 const char *msg
= 0;
22716 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22717 msg
= _("undefined symbol %s used as an immediate value");
22718 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22719 msg
= _("symbol %s is in a different section");
22720 else if (S_IS_WEAK (fixP
->fx_addsy
))
22721 msg
= _("symbol %s is weak and may be overridden later");
22725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22726 msg
, S_GET_NAME (fixP
->fx_addsy
));
22731 newimm
= encode_arm_immediate (value
);
22732 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22734 /* If the instruction will fail, see if we can fix things up by
22735 changing the opcode. */
22736 if (newimm
== (unsigned int) FAIL
22737 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22739 /* No ? OK - try using two ADD instructions to generate
22741 newimm
= validate_immediate_twopart (value
, & highpart
);
22743 /* Yes - then make sure that the second instruction is
22745 if (newimm
!= (unsigned int) FAIL
)
22747 /* Still No ? Try using a negated value. */
22748 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22749 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22750 /* Otherwise - give up. */
22753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22754 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22759 /* Replace the first operand in the 2nd instruction (which
22760 is the PC) with the destination register. We have
22761 already added in the PC in the first instruction and we
22762 do not want to do it again. */
22763 newinsn
&= ~ 0xf0000;
22764 newinsn
|= ((newinsn
& 0x0f000) << 4);
22767 newimm
|= (temp
& 0xfffff000);
22768 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22770 highpart
|= (newinsn
& 0xfffff000);
22771 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22775 case BFD_RELOC_ARM_OFFSET_IMM
:
22776 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22779 case BFD_RELOC_ARM_LITERAL
:
22785 if (validate_offset_imm (value
, 0) == FAIL
)
22787 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22789 _("invalid literal constant: pool needs to be closer"));
22791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22792 _("bad immediate value for offset (%ld)"),
22797 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22799 newval
&= 0xfffff000;
22802 newval
&= 0xff7ff000;
22803 newval
|= value
| (sign
? INDEX_UP
: 0);
22805 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22808 case BFD_RELOC_ARM_OFFSET_IMM8
:
22809 case BFD_RELOC_ARM_HWLITERAL
:
22815 if (validate_offset_imm (value
, 1) == FAIL
)
22817 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22819 _("invalid literal constant: pool needs to be closer"));
22821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22822 _("bad immediate value for 8-bit offset (%ld)"),
22827 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22829 newval
&= 0xfffff0f0;
22832 newval
&= 0xff7ff0f0;
22833 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22835 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22838 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22839 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22841 _("bad immediate value for offset (%ld)"), (long) value
);
22844 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22846 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22849 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22850 /* This is a complicated relocation used for all varieties of Thumb32
22851 load/store instruction with immediate offset:
22853 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22854 *4, optional writeback(W)
22855 (doubleword load/store)
22857 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22858 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22859 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22860 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22861 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22863 Uppercase letters indicate bits that are already encoded at
22864 this point. Lowercase letters are our problem. For the
22865 second block of instructions, the secondary opcode nybble
22866 (bits 8..11) is present, and bit 23 is zero, even if this is
22867 a PC-relative operation. */
22868 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22870 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22872 if ((newval
& 0xf0000000) == 0xe0000000)
22874 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22876 newval
|= (1 << 23);
22879 if (value
% 4 != 0)
22881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22882 _("offset not a multiple of 4"));
22888 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22889 _("offset out of range"));
22894 else if ((newval
& 0x000f0000) == 0x000f0000)
22896 /* PC-relative, 12-bit offset. */
22898 newval
|= (1 << 23);
22903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22904 _("offset out of range"));
22909 else if ((newval
& 0x00000100) == 0x00000100)
22911 /* Writeback: 8-bit, +/- offset. */
22913 newval
|= (1 << 9);
22918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22919 _("offset out of range"));
22924 else if ((newval
& 0x00000f00) == 0x00000e00)
22926 /* T-instruction: positive 8-bit offset. */
22927 if (value
< 0 || value
> 0xff)
22929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22930 _("offset out of range"));
22938 /* Positive 12-bit or negative 8-bit offset. */
22942 newval
|= (1 << 23);
22952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22953 _("offset out of range"));
22960 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22961 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22964 case BFD_RELOC_ARM_SHIFT_IMM
:
22965 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22966 if (((unsigned long) value
) > 32
22968 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22971 _("shift expression is too large"));
22976 /* Shifts of zero must be done as lsl. */
22978 else if (value
== 32)
22980 newval
&= 0xfffff07f;
22981 newval
|= (value
& 0x1f) << 7;
22982 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22985 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22986 case BFD_RELOC_ARM_T32_ADD_IMM
:
22987 case BFD_RELOC_ARM_T32_IMM12
:
22988 case BFD_RELOC_ARM_T32_ADD_PC12
:
22989 /* We claim that this fixup has been processed here,
22990 even if in fact we generate an error because we do
22991 not have a reloc for it, so tc_gen_reloc will reject it. */
22995 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22998 _("undefined symbol %s used as an immediate value"),
22999 S_GET_NAME (fixP
->fx_addsy
));
23003 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23005 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23008 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23009 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23011 newimm
= encode_thumb32_immediate (value
);
23012 if (newimm
== (unsigned int) FAIL
)
23013 newimm
= thumb32_negate_data_op (&newval
, value
);
23015 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23016 && newimm
== (unsigned int) FAIL
)
23018 /* Turn add/sum into addw/subw. */
23019 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23020 newval
= (newval
& 0xfeffffff) | 0x02000000;
23021 /* No flat 12-bit imm encoding for addsw/subsw. */
23022 if ((newval
& 0x00100000) == 0)
23024 /* 12 bit immediate for addw/subw. */
23028 newval
^= 0x00a00000;
23031 newimm
= (unsigned int) FAIL
;
23037 if (newimm
== (unsigned int)FAIL
)
23039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23040 _("invalid constant (%lx) after fixup"),
23041 (unsigned long) value
);
23045 newval
|= (newimm
& 0x800) << 15;
23046 newval
|= (newimm
& 0x700) << 4;
23047 newval
|= (newimm
& 0x0ff);
23049 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23050 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23053 case BFD_RELOC_ARM_SMC
:
23054 if (((unsigned long) value
) > 0xffff)
23055 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23056 _("invalid smc expression"));
23057 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23058 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23059 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23062 case BFD_RELOC_ARM_HVC
:
23063 if (((unsigned long) value
) > 0xffff)
23064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23065 _("invalid hvc expression"));
23066 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23067 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23068 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23071 case BFD_RELOC_ARM_SWI
:
23072 if (fixP
->tc_fix_data
!= 0)
23074 if (((unsigned long) value
) > 0xff)
23075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23076 _("invalid swi expression"));
23077 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23079 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23083 if (((unsigned long) value
) > 0x00ffffff)
23084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23085 _("invalid swi expression"));
23086 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23088 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23092 case BFD_RELOC_ARM_MULTI
:
23093 if (((unsigned long) value
) > 0xffff)
23094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23095 _("invalid expression in load/store multiple"));
23096 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23097 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23101 case BFD_RELOC_ARM_PCREL_CALL
:
23103 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23105 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23106 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23107 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23108 /* Flip the bl to blx. This is a simple flip
23109 bit here because we generate PCREL_CALL for
23110 unconditional bls. */
23112 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23113 newval
= newval
| 0x10000000;
23114 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23120 goto arm_branch_common
;
23122 case BFD_RELOC_ARM_PCREL_JUMP
:
23123 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23125 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23126 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23127 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23129 /* This would map to a bl<cond>, b<cond>,
23130 b<always> to a Thumb function. We
23131 need to force a relocation for this particular
23133 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23137 case BFD_RELOC_ARM_PLT32
:
23139 case BFD_RELOC_ARM_PCREL_BRANCH
:
23141 goto arm_branch_common
;
23143 case BFD_RELOC_ARM_PCREL_BLX
:
23146 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23148 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23149 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23150 && ARM_IS_FUNC (fixP
->fx_addsy
))
23152 /* Flip the blx to a bl and warn. */
23153 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23154 newval
= 0xeb000000;
23155 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23156 _("blx to '%s' an ARM ISA state function changed to bl"),
23158 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23164 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23165 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23169 /* We are going to store value (shifted right by two) in the
23170 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23171 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23172 also be be clear. */
23174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23175 _("misaligned branch destination"));
23176 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23177 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23180 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23182 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23183 newval
|= (value
>> 2) & 0x00ffffff;
23184 /* Set the H bit on BLX instructions. */
23188 newval
|= 0x01000000;
23190 newval
&= ~0x01000000;
23192 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23196 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23197 /* CBZ can only branch forward. */
23199 /* Attempts to use CBZ to branch to the next instruction
23200 (which, strictly speaking, are prohibited) will be turned into
23203 FIXME: It may be better to remove the instruction completely and
23204 perform relaxation. */
23207 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23208 newval
= 0xbf00; /* NOP encoding T1 */
23209 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23216 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23218 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23219 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23220 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23225 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23226 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23229 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23231 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23232 newval
|= (value
& 0x1ff) >> 1;
23233 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23237 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23238 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23241 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23243 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23244 newval
|= (value
& 0xfff) >> 1;
23245 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23249 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23251 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23252 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23253 && ARM_IS_FUNC (fixP
->fx_addsy
)
23254 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23256 /* Force a relocation for a branch 20 bits wide. */
23259 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23261 _("conditional branch out of range"));
23263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23266 addressT S
, J1
, J2
, lo
, hi
;
23268 S
= (value
& 0x00100000) >> 20;
23269 J2
= (value
& 0x00080000) >> 19;
23270 J1
= (value
& 0x00040000) >> 18;
23271 hi
= (value
& 0x0003f000) >> 12;
23272 lo
= (value
& 0x00000ffe) >> 1;
23274 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23275 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23276 newval
|= (S
<< 10) | hi
;
23277 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23278 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23279 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23283 case BFD_RELOC_THUMB_PCREL_BLX
:
23284 /* If there is a blx from a thumb state function to
23285 another thumb function flip this to a bl and warn
23289 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23290 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23291 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23293 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23294 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23295 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23297 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23298 newval
= newval
| 0x1000;
23299 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23300 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23305 goto thumb_bl_common
;
23307 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23308 /* A bl from Thumb state ISA to an internal ARM state function
23309 is converted to a blx. */
23311 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23312 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23313 && ARM_IS_FUNC (fixP
->fx_addsy
)
23314 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23316 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23317 newval
= newval
& ~0x1000;
23318 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23319 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23325 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23326 /* For a BLX instruction, make sure that the relocation is rounded up
23327 to a word boundary. This follows the semantics of the instruction
23328 which specifies that bit 1 of the target address will come from bit
23329 1 of the base address. */
23330 value
= (value
+ 3) & ~ 3;
23333 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23334 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23335 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23338 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23340 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23342 else if ((value
& ~0x1ffffff)
23343 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23345 _("Thumb2 branch out of range"));
23348 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23349 encode_thumb2_b_bl_offset (buf
, value
);
23353 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23354 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23357 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23358 encode_thumb2_b_bl_offset (buf
, value
);
23363 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23368 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23369 md_number_to_chars (buf
, value
, 2);
23373 case BFD_RELOC_ARM_TLS_CALL
:
23374 case BFD_RELOC_ARM_THM_TLS_CALL
:
23375 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23376 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23377 case BFD_RELOC_ARM_TLS_GOTDESC
:
23378 case BFD_RELOC_ARM_TLS_GD32
:
23379 case BFD_RELOC_ARM_TLS_LE32
:
23380 case BFD_RELOC_ARM_TLS_IE32
:
23381 case BFD_RELOC_ARM_TLS_LDM32
:
23382 case BFD_RELOC_ARM_TLS_LDO32
:
23383 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23386 case BFD_RELOC_ARM_GOT32
:
23387 case BFD_RELOC_ARM_GOTOFF
:
23390 case BFD_RELOC_ARM_GOT_PREL
:
23391 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23392 md_number_to_chars (buf
, value
, 4);
23395 case BFD_RELOC_ARM_TARGET2
:
23396 /* TARGET2 is not partial-inplace, so we need to write the
23397 addend here for REL targets, because it won't be written out
23398 during reloc processing later. */
23399 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23400 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23404 case BFD_RELOC_RVA
:
23406 case BFD_RELOC_ARM_TARGET1
:
23407 case BFD_RELOC_ARM_ROSEGREL32
:
23408 case BFD_RELOC_ARM_SBREL32
:
23409 case BFD_RELOC_32_PCREL
:
23411 case BFD_RELOC_32_SECREL
:
23413 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23415 /* For WinCE we only do this for pcrel fixups. */
23416 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23418 md_number_to_chars (buf
, value
, 4);
23422 case BFD_RELOC_ARM_PREL31
:
23423 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23425 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23426 if ((value
^ (value
>> 1)) & 0x40000000)
23428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23429 _("rel31 relocation overflow"));
23431 newval
|= value
& 0x7fffffff;
23432 md_number_to_chars (buf
, newval
, 4);
23437 case BFD_RELOC_ARM_CP_OFF_IMM
:
23438 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23439 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23440 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23442 newval
= get_thumb32_insn (buf
);
23443 if ((newval
& 0x0f200f00) == 0x0d000900)
23445 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23446 has permitted values that are multiples of 2, in the range 0
23448 if (value
< -510 || value
> 510 || (value
& 1))
23449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23450 _("co-processor offset out of range"));
23452 else if (value
< -1023 || value
> 1023 || (value
& 3))
23453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23454 _("co-processor offset out of range"));
23459 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23460 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23461 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23463 newval
= get_thumb32_insn (buf
);
23465 newval
&= 0xffffff00;
23468 newval
&= 0xff7fff00;
23469 if ((newval
& 0x0f200f00) == 0x0d000900)
23471 /* This is a fp16 vstr/vldr.
23473 It requires the immediate offset in the instruction is shifted
23474 left by 1 to be a half-word offset.
23476 Here, left shift by 1 first, and later right shift by 2
23477 should get the right offset. */
23480 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23482 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23483 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23484 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23486 put_thumb32_insn (buf
, newval
);
23489 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23490 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23491 if (value
< -255 || value
> 255)
23492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23493 _("co-processor offset out of range"));
23495 goto cp_off_common
;
23497 case BFD_RELOC_ARM_THUMB_OFFSET
:
23498 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23499 /* Exactly what ranges, and where the offset is inserted depends
23500 on the type of instruction, we can establish this from the
23502 switch (newval
>> 12)
23504 case 4: /* PC load. */
23505 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23506 forced to zero for these loads; md_pcrel_from has already
23507 compensated for this. */
23509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23510 _("invalid offset, target not word aligned (0x%08lX)"),
23511 (((unsigned long) fixP
->fx_frag
->fr_address
23512 + (unsigned long) fixP
->fx_where
) & ~3)
23513 + (unsigned long) value
);
23515 if (value
& ~0x3fc)
23516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23517 _("invalid offset, value too big (0x%08lX)"),
23520 newval
|= value
>> 2;
23523 case 9: /* SP load/store. */
23524 if (value
& ~0x3fc)
23525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23526 _("invalid offset, value too big (0x%08lX)"),
23528 newval
|= value
>> 2;
23531 case 6: /* Word load/store. */
23533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23534 _("invalid offset, value too big (0x%08lX)"),
23536 newval
|= value
<< 4; /* 6 - 2. */
23539 case 7: /* Byte load/store. */
23541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23542 _("invalid offset, value too big (0x%08lX)"),
23544 newval
|= value
<< 6;
23547 case 8: /* Halfword load/store. */
23549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23550 _("invalid offset, value too big (0x%08lX)"),
23552 newval
|= value
<< 5; /* 6 - 1. */
23556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23557 "Unable to process relocation for thumb opcode: %lx",
23558 (unsigned long) newval
);
23561 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23564 case BFD_RELOC_ARM_THUMB_ADD
:
23565 /* This is a complicated relocation, since we use it for all of
23566 the following immediate relocations:
23570 9bit ADD/SUB SP word-aligned
23571 10bit ADD PC/SP word-aligned
23573 The type of instruction being processed is encoded in the
23580 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23582 int rd
= (newval
>> 4) & 0xf;
23583 int rs
= newval
& 0xf;
23584 int subtract
= !!(newval
& 0x8000);
23586 /* Check for HI regs, only very restricted cases allowed:
23587 Adjusting SP, and using PC or SP to get an address. */
23588 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23589 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23590 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23591 _("invalid Hi register with immediate"));
23593 /* If value is negative, choose the opposite instruction. */
23597 subtract
= !subtract
;
23599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23600 _("immediate value out of range"));
23605 if (value
& ~0x1fc)
23606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23607 _("invalid immediate for stack address calculation"));
23608 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23609 newval
|= value
>> 2;
23611 else if (rs
== REG_PC
|| rs
== REG_SP
)
23613 /* PR gas/18541. If the addition is for a defined symbol
23614 within range of an ADR instruction then accept it. */
23617 && fixP
->fx_addsy
!= NULL
)
23621 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23622 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23623 || S_IS_WEAK (fixP
->fx_addsy
))
23625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23626 _("address calculation needs a strongly defined nearby symbol"));
23630 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23632 /* Round up to the next 4-byte boundary. */
23637 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23642 _("symbol too far away"));
23652 if (subtract
|| value
& ~0x3fc)
23653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23654 _("invalid immediate for address calculation (value = 0x%08lX)"),
23655 (unsigned long) (subtract
? - value
: value
));
23656 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23658 newval
|= value
>> 2;
23663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23664 _("immediate value out of range"));
23665 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23666 newval
|= (rd
<< 8) | value
;
23671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23672 _("immediate value out of range"));
23673 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23674 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23677 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23680 case BFD_RELOC_ARM_THUMB_IMM
:
23681 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23682 if (value
< 0 || value
> 255)
23683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23684 _("invalid immediate: %ld is out of range"),
23687 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23690 case BFD_RELOC_ARM_THUMB_SHIFT
:
23691 /* 5bit shift value (0..32). LSL cannot take 32. */
23692 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23693 temp
= newval
& 0xf800;
23694 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23696 _("invalid shift value: %ld"), (long) value
);
23697 /* Shifts of zero must be encoded as LSL. */
23699 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23700 /* Shifts of 32 are encoded as zero. */
23701 else if (value
== 32)
23703 newval
|= value
<< 6;
23704 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23707 case BFD_RELOC_VTABLE_INHERIT
:
23708 case BFD_RELOC_VTABLE_ENTRY
:
23712 case BFD_RELOC_ARM_MOVW
:
23713 case BFD_RELOC_ARM_MOVT
:
23714 case BFD_RELOC_ARM_THUMB_MOVW
:
23715 case BFD_RELOC_ARM_THUMB_MOVT
:
23716 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23718 /* REL format relocations are limited to a 16-bit addend. */
23719 if (!fixP
->fx_done
)
23721 if (value
< -0x8000 || value
> 0x7fff)
23722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23723 _("offset out of range"));
23725 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23726 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23731 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23732 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23734 newval
= get_thumb32_insn (buf
);
23735 newval
&= 0xfbf08f00;
23736 newval
|= (value
& 0xf000) << 4;
23737 newval
|= (value
& 0x0800) << 15;
23738 newval
|= (value
& 0x0700) << 4;
23739 newval
|= (value
& 0x00ff);
23740 put_thumb32_insn (buf
, newval
);
23744 newval
= md_chars_to_number (buf
, 4);
23745 newval
&= 0xfff0f000;
23746 newval
|= value
& 0x0fff;
23747 newval
|= (value
& 0xf000) << 4;
23748 md_number_to_chars (buf
, newval
, 4);
23753 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23754 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23755 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23756 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23757 gas_assert (!fixP
->fx_done
);
23760 bfd_boolean is_mov
;
23761 bfd_vma encoded_addend
= value
;
23763 /* Check that addend can be encoded in instruction. */
23764 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23766 _("the offset 0x%08lX is not representable"),
23767 (unsigned long) encoded_addend
);
23769 /* Extract the instruction. */
23770 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23771 is_mov
= (insn
& 0xf800) == 0x2000;
23776 if (!seg
->use_rela_p
)
23777 insn
|= encoded_addend
;
23783 /* Extract the instruction. */
23784 /* Encoding is the following
23789 /* The following conditions must be true :
23794 rd
= (insn
>> 4) & 0xf;
23796 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23798 _("Unable to process relocation for thumb opcode: %lx"),
23799 (unsigned long) insn
);
23801 /* Encode as ADD immediate8 thumb 1 code. */
23802 insn
= 0x3000 | (rd
<< 8);
23804 /* Place the encoded addend into the first 8 bits of the
23806 if (!seg
->use_rela_p
)
23807 insn
|= encoded_addend
;
23810 /* Update the instruction. */
23811 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23815 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23816 case BFD_RELOC_ARM_ALU_PC_G0
:
23817 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23818 case BFD_RELOC_ARM_ALU_PC_G1
:
23819 case BFD_RELOC_ARM_ALU_PC_G2
:
23820 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23821 case BFD_RELOC_ARM_ALU_SB_G0
:
23822 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23823 case BFD_RELOC_ARM_ALU_SB_G1
:
23824 case BFD_RELOC_ARM_ALU_SB_G2
:
23825 gas_assert (!fixP
->fx_done
);
23826 if (!seg
->use_rela_p
)
23829 bfd_vma encoded_addend
;
23830 bfd_vma addend_abs
= abs (value
);
23832 /* Check that the absolute value of the addend can be
23833 expressed as an 8-bit constant plus a rotation. */
23834 encoded_addend
= encode_arm_immediate (addend_abs
);
23835 if (encoded_addend
== (unsigned int) FAIL
)
23836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23837 _("the offset 0x%08lX is not representable"),
23838 (unsigned long) addend_abs
);
23840 /* Extract the instruction. */
23841 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23843 /* If the addend is positive, use an ADD instruction.
23844 Otherwise use a SUB. Take care not to destroy the S bit. */
23845 insn
&= 0xff1fffff;
23851 /* Place the encoded addend into the first 12 bits of the
23853 insn
&= 0xfffff000;
23854 insn
|= encoded_addend
;
23856 /* Update the instruction. */
23857 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23861 case BFD_RELOC_ARM_LDR_PC_G0
:
23862 case BFD_RELOC_ARM_LDR_PC_G1
:
23863 case BFD_RELOC_ARM_LDR_PC_G2
:
23864 case BFD_RELOC_ARM_LDR_SB_G0
:
23865 case BFD_RELOC_ARM_LDR_SB_G1
:
23866 case BFD_RELOC_ARM_LDR_SB_G2
:
23867 gas_assert (!fixP
->fx_done
);
23868 if (!seg
->use_rela_p
)
23871 bfd_vma addend_abs
= abs (value
);
23873 /* Check that the absolute value of the addend can be
23874 encoded in 12 bits. */
23875 if (addend_abs
>= 0x1000)
23876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23877 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23878 (unsigned long) addend_abs
);
23880 /* Extract the instruction. */
23881 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23883 /* If the addend is negative, clear bit 23 of the instruction.
23884 Otherwise set it. */
23886 insn
&= ~(1 << 23);
23890 /* Place the absolute value of the addend into the first 12 bits
23891 of the instruction. */
23892 insn
&= 0xfffff000;
23893 insn
|= addend_abs
;
23895 /* Update the instruction. */
23896 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23900 case BFD_RELOC_ARM_LDRS_PC_G0
:
23901 case BFD_RELOC_ARM_LDRS_PC_G1
:
23902 case BFD_RELOC_ARM_LDRS_PC_G2
:
23903 case BFD_RELOC_ARM_LDRS_SB_G0
:
23904 case BFD_RELOC_ARM_LDRS_SB_G1
:
23905 case BFD_RELOC_ARM_LDRS_SB_G2
:
23906 gas_assert (!fixP
->fx_done
);
23907 if (!seg
->use_rela_p
)
23910 bfd_vma addend_abs
= abs (value
);
23912 /* Check that the absolute value of the addend can be
23913 encoded in 8 bits. */
23914 if (addend_abs
>= 0x100)
23915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23916 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23917 (unsigned long) addend_abs
);
23919 /* Extract the instruction. */
23920 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23922 /* If the addend is negative, clear bit 23 of the instruction.
23923 Otherwise set it. */
23925 insn
&= ~(1 << 23);
23929 /* Place the first four bits of the absolute value of the addend
23930 into the first 4 bits of the instruction, and the remaining
23931 four into bits 8 .. 11. */
23932 insn
&= 0xfffff0f0;
23933 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23935 /* Update the instruction. */
23936 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23940 case BFD_RELOC_ARM_LDC_PC_G0
:
23941 case BFD_RELOC_ARM_LDC_PC_G1
:
23942 case BFD_RELOC_ARM_LDC_PC_G2
:
23943 case BFD_RELOC_ARM_LDC_SB_G0
:
23944 case BFD_RELOC_ARM_LDC_SB_G1
:
23945 case BFD_RELOC_ARM_LDC_SB_G2
:
23946 gas_assert (!fixP
->fx_done
);
23947 if (!seg
->use_rela_p
)
23950 bfd_vma addend_abs
= abs (value
);
23952 /* Check that the absolute value of the addend is a multiple of
23953 four and, when divided by four, fits in 8 bits. */
23954 if (addend_abs
& 0x3)
23955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23956 _("bad offset 0x%08lX (must be word-aligned)"),
23957 (unsigned long) addend_abs
);
23959 if ((addend_abs
>> 2) > 0xff)
23960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23961 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23962 (unsigned long) addend_abs
);
23964 /* Extract the instruction. */
23965 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23967 /* If the addend is negative, clear bit 23 of the instruction.
23968 Otherwise set it. */
23970 insn
&= ~(1 << 23);
23974 /* Place the addend (divided by four) into the first eight
23975 bits of the instruction. */
23976 insn
&= 0xfffffff0;
23977 insn
|= addend_abs
>> 2;
23979 /* Update the instruction. */
23980 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23984 case BFD_RELOC_ARM_V4BX
:
23985 /* This will need to go in the object file. */
23989 case BFD_RELOC_UNUSED
:
23991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23992 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23996 /* Translate internal representation of relocation info to BFD target
24000 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24003 bfd_reloc_code_real_type code
;
24005 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
24007 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
24008 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24009 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24011 if (fixp
->fx_pcrel
)
24013 if (section
->use_rela_p
)
24014 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24016 fixp
->fx_offset
= reloc
->address
;
24018 reloc
->addend
= fixp
->fx_offset
;
24020 switch (fixp
->fx_r_type
)
24023 if (fixp
->fx_pcrel
)
24025 code
= BFD_RELOC_8_PCREL
;
24030 if (fixp
->fx_pcrel
)
24032 code
= BFD_RELOC_16_PCREL
;
24037 if (fixp
->fx_pcrel
)
24039 code
= BFD_RELOC_32_PCREL
;
24043 case BFD_RELOC_ARM_MOVW
:
24044 if (fixp
->fx_pcrel
)
24046 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24050 case BFD_RELOC_ARM_MOVT
:
24051 if (fixp
->fx_pcrel
)
24053 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24057 case BFD_RELOC_ARM_THUMB_MOVW
:
24058 if (fixp
->fx_pcrel
)
24060 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24064 case BFD_RELOC_ARM_THUMB_MOVT
:
24065 if (fixp
->fx_pcrel
)
24067 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24071 case BFD_RELOC_NONE
:
24072 case BFD_RELOC_ARM_PCREL_BRANCH
:
24073 case BFD_RELOC_ARM_PCREL_BLX
:
24074 case BFD_RELOC_RVA
:
24075 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24076 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24077 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24078 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24079 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24080 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24081 case BFD_RELOC_VTABLE_ENTRY
:
24082 case BFD_RELOC_VTABLE_INHERIT
:
24084 case BFD_RELOC_32_SECREL
:
24086 code
= fixp
->fx_r_type
;
24089 case BFD_RELOC_THUMB_PCREL_BLX
:
24091 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24092 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24095 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24098 case BFD_RELOC_ARM_LITERAL
:
24099 case BFD_RELOC_ARM_HWLITERAL
:
24100 /* If this is called then the a literal has
24101 been referenced across a section boundary. */
24102 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24103 _("literal referenced across section boundary"));
24107 case BFD_RELOC_ARM_TLS_CALL
:
24108 case BFD_RELOC_ARM_THM_TLS_CALL
:
24109 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24110 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24111 case BFD_RELOC_ARM_GOT32
:
24112 case BFD_RELOC_ARM_GOTOFF
:
24113 case BFD_RELOC_ARM_GOT_PREL
:
24114 case BFD_RELOC_ARM_PLT32
:
24115 case BFD_RELOC_ARM_TARGET1
:
24116 case BFD_RELOC_ARM_ROSEGREL32
:
24117 case BFD_RELOC_ARM_SBREL32
:
24118 case BFD_RELOC_ARM_PREL31
:
24119 case BFD_RELOC_ARM_TARGET2
:
24120 case BFD_RELOC_ARM_TLS_LDO32
:
24121 case BFD_RELOC_ARM_PCREL_CALL
:
24122 case BFD_RELOC_ARM_PCREL_JUMP
:
24123 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24124 case BFD_RELOC_ARM_ALU_PC_G0
:
24125 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24126 case BFD_RELOC_ARM_ALU_PC_G1
:
24127 case BFD_RELOC_ARM_ALU_PC_G2
:
24128 case BFD_RELOC_ARM_LDR_PC_G0
:
24129 case BFD_RELOC_ARM_LDR_PC_G1
:
24130 case BFD_RELOC_ARM_LDR_PC_G2
:
24131 case BFD_RELOC_ARM_LDRS_PC_G0
:
24132 case BFD_RELOC_ARM_LDRS_PC_G1
:
24133 case BFD_RELOC_ARM_LDRS_PC_G2
:
24134 case BFD_RELOC_ARM_LDC_PC_G0
:
24135 case BFD_RELOC_ARM_LDC_PC_G1
:
24136 case BFD_RELOC_ARM_LDC_PC_G2
:
24137 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24138 case BFD_RELOC_ARM_ALU_SB_G0
:
24139 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24140 case BFD_RELOC_ARM_ALU_SB_G1
:
24141 case BFD_RELOC_ARM_ALU_SB_G2
:
24142 case BFD_RELOC_ARM_LDR_SB_G0
:
24143 case BFD_RELOC_ARM_LDR_SB_G1
:
24144 case BFD_RELOC_ARM_LDR_SB_G2
:
24145 case BFD_RELOC_ARM_LDRS_SB_G0
:
24146 case BFD_RELOC_ARM_LDRS_SB_G1
:
24147 case BFD_RELOC_ARM_LDRS_SB_G2
:
24148 case BFD_RELOC_ARM_LDC_SB_G0
:
24149 case BFD_RELOC_ARM_LDC_SB_G1
:
24150 case BFD_RELOC_ARM_LDC_SB_G2
:
24151 case BFD_RELOC_ARM_V4BX
:
24152 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24153 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24154 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24155 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24156 code
= fixp
->fx_r_type
;
24159 case BFD_RELOC_ARM_TLS_GOTDESC
:
24160 case BFD_RELOC_ARM_TLS_GD32
:
24161 case BFD_RELOC_ARM_TLS_LE32
:
24162 case BFD_RELOC_ARM_TLS_IE32
:
24163 case BFD_RELOC_ARM_TLS_LDM32
:
24164 /* BFD will include the symbol's address in the addend.
24165 But we don't want that, so subtract it out again here. */
24166 if (!S_IS_COMMON (fixp
->fx_addsy
))
24167 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24168 code
= fixp
->fx_r_type
;
24172 case BFD_RELOC_ARM_IMMEDIATE
:
24173 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24174 _("internal relocation (type: IMMEDIATE) not fixed up"));
24177 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24178 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24179 _("ADRL used for a symbol not defined in the same file"));
24182 case BFD_RELOC_ARM_OFFSET_IMM
:
24183 if (section
->use_rela_p
)
24185 code
= fixp
->fx_r_type
;
24189 if (fixp
->fx_addsy
!= NULL
24190 && !S_IS_DEFINED (fixp
->fx_addsy
)
24191 && S_IS_LOCAL (fixp
->fx_addsy
))
24193 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24194 _("undefined local label `%s'"),
24195 S_GET_NAME (fixp
->fx_addsy
));
24199 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24200 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24207 switch (fixp
->fx_r_type
)
24209 case BFD_RELOC_NONE
: type
= "NONE"; break;
24210 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24211 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24212 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24213 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24214 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24215 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24216 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24217 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24218 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24219 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24220 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24221 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24222 default: type
= _("<unknown>"); break;
24224 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24225 _("cannot represent %s relocation in this object file format"),
24232 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24234 && fixp
->fx_addsy
== GOT_symbol
)
24236 code
= BFD_RELOC_ARM_GOTPC
;
24237 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24241 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24243 if (reloc
->howto
== NULL
)
24245 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24246 _("cannot represent %s relocation in this object file format"),
24247 bfd_get_reloc_code_name (code
));
24251 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24252 vtable entry to be used in the relocation's section offset. */
24253 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24254 reloc
->address
= fixp
->fx_offset
;
24259 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24262 cons_fix_new_arm (fragS
* frag
,
24266 bfd_reloc_code_real_type reloc
)
24271 FIXME: @@ Should look at CPU word size. */
24275 reloc
= BFD_RELOC_8
;
24278 reloc
= BFD_RELOC_16
;
24282 reloc
= BFD_RELOC_32
;
24285 reloc
= BFD_RELOC_64
;
24290 if (exp
->X_op
== O_secrel
)
24292 exp
->X_op
= O_symbol
;
24293 reloc
= BFD_RELOC_32_SECREL
;
24297 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24300 #if defined (OBJ_COFF)
24302 arm_validate_fix (fixS
* fixP
)
24304 /* If the destination of the branch is a defined symbol which does not have
24305 the THUMB_FUNC attribute, then we must be calling a function which has
24306 the (interfacearm) attribute. We look for the Thumb entry point to that
24307 function and change the branch to refer to that function instead. */
24308 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24309 && fixP
->fx_addsy
!= NULL
24310 && S_IS_DEFINED (fixP
->fx_addsy
)
24311 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24313 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24320 arm_force_relocation (struct fix
* fixp
)
24322 #if defined (OBJ_COFF) && defined (TE_PE)
24323 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24327 /* In case we have a call or a branch to a function in ARM ISA mode from
24328 a thumb function or vice-versa force the relocation. These relocations
24329 are cleared off for some cores that might have blx and simple transformations
24333 switch (fixp
->fx_r_type
)
24335 case BFD_RELOC_ARM_PCREL_JUMP
:
24336 case BFD_RELOC_ARM_PCREL_CALL
:
24337 case BFD_RELOC_THUMB_PCREL_BLX
:
24338 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24342 case BFD_RELOC_ARM_PCREL_BLX
:
24343 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24344 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24345 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24346 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24355 /* Resolve these relocations even if the symbol is extern or weak.
24356 Technically this is probably wrong due to symbol preemption.
24357 In practice these relocations do not have enough range to be useful
24358 at dynamic link time, and some code (e.g. in the Linux kernel)
24359 expects these references to be resolved. */
24360 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24361 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24362 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24363 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24364 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24365 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24366 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24367 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24368 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24369 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24370 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24371 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24372 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24373 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24376 /* Always leave these relocations for the linker. */
24377 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24378 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24379 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24382 /* Always generate relocations against function symbols. */
24383 if (fixp
->fx_r_type
== BFD_RELOC_32
24385 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24388 return generic_force_reloc (fixp
);
24391 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24392 /* Relocations against function names must be left unadjusted,
24393 so that the linker can use this information to generate interworking
24394 stubs. The MIPS version of this function
24395 also prevents relocations that are mips-16 specific, but I do not
24396 know why it does this.
24399 There is one other problem that ought to be addressed here, but
24400 which currently is not: Taking the address of a label (rather
24401 than a function) and then later jumping to that address. Such
24402 addresses also ought to have their bottom bit set (assuming that
24403 they reside in Thumb code), but at the moment they will not. */
24406 arm_fix_adjustable (fixS
* fixP
)
24408 if (fixP
->fx_addsy
== NULL
)
24411 /* Preserve relocations against symbols with function type. */
24412 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24415 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24416 && fixP
->fx_subsy
== NULL
)
24419 /* We need the symbol name for the VTABLE entries. */
24420 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24421 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24424 /* Don't allow symbols to be discarded on GOT related relocs. */
24425 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24426 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24427 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24428 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24429 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24430 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24431 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24432 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24433 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24434 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24435 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24436 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24437 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24438 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24441 /* Similarly for group relocations. */
24442 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24443 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24444 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24447 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24448 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24449 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24450 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24451 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24452 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24453 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24454 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24455 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24458 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24459 offsets, so keep these symbols. */
24460 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24461 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24466 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24470 elf32_arm_target_format (void)
24473 return (target_big_endian
24474 ? "elf32-bigarm-symbian"
24475 : "elf32-littlearm-symbian");
24476 #elif defined (TE_VXWORKS)
24477 return (target_big_endian
24478 ? "elf32-bigarm-vxworks"
24479 : "elf32-littlearm-vxworks");
24480 #elif defined (TE_NACL)
24481 return (target_big_endian
24482 ? "elf32-bigarm-nacl"
24483 : "elf32-littlearm-nacl");
24485 if (target_big_endian
)
24486 return "elf32-bigarm";
24488 return "elf32-littlearm";
24493 armelf_frob_symbol (symbolS
* symp
,
24496 elf_frob_symbol (symp
, puntp
);
24500 /* MD interface: Finalization. */
24505 literal_pool
* pool
;
24507 /* Ensure that all the IT blocks are properly closed. */
24508 check_it_blocks_finished ();
24510 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24512 /* Put it at the end of the relevant section. */
24513 subseg_set (pool
->section
, pool
->sub_section
);
24515 arm_elf_change_section ();
24522 /* Remove any excess mapping symbols generated for alignment frags in
24523 SEC. We may have created a mapping symbol before a zero byte
24524 alignment; remove it if there's a mapping symbol after the
24527 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24528 void *dummy ATTRIBUTE_UNUSED
)
24530 segment_info_type
*seginfo
= seg_info (sec
);
24533 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24536 for (fragp
= seginfo
->frchainP
->frch_root
;
24538 fragp
= fragp
->fr_next
)
24540 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24541 fragS
*next
= fragp
->fr_next
;
24543 /* Variable-sized frags have been converted to fixed size by
24544 this point. But if this was variable-sized to start with,
24545 there will be a fixed-size frag after it. So don't handle
24547 if (sym
== NULL
|| next
== NULL
)
24550 if (S_GET_VALUE (sym
) < next
->fr_address
)
24551 /* Not at the end of this frag. */
24553 know (S_GET_VALUE (sym
) == next
->fr_address
);
24557 if (next
->tc_frag_data
.first_map
!= NULL
)
24559 /* Next frag starts with a mapping symbol. Discard this
24561 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24565 if (next
->fr_next
== NULL
)
24567 /* This mapping symbol is at the end of the section. Discard
24569 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24570 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24574 /* As long as we have empty frags without any mapping symbols,
24576 /* If the next frag is non-empty and does not start with a
24577 mapping symbol, then this mapping symbol is required. */
24578 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24581 next
= next
->fr_next
;
24583 while (next
!= NULL
);
24588 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24592 arm_adjust_symtab (void)
24597 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24599 if (ARM_IS_THUMB (sym
))
24601 if (THUMB_IS_FUNC (sym
))
24603 /* Mark the symbol as a Thumb function. */
24604 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24605 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24606 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24608 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24609 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24611 as_bad (_("%s: unexpected function type: %d"),
24612 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24614 else switch (S_GET_STORAGE_CLASS (sym
))
24617 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24620 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24623 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24631 if (ARM_IS_INTERWORK (sym
))
24632 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24639 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24641 if (ARM_IS_THUMB (sym
))
24643 elf_symbol_type
* elf_sym
;
24645 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24646 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24648 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24649 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24651 /* If it's a .thumb_func, declare it as so,
24652 otherwise tag label as .code 16. */
24653 if (THUMB_IS_FUNC (sym
))
24654 elf_sym
->internal_elf_sym
.st_target_internal
24655 = ST_BRANCH_TO_THUMB
;
24656 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24657 elf_sym
->internal_elf_sym
.st_info
=
24658 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24663 /* Remove any overlapping mapping symbols generated by alignment frags. */
24664 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24665 /* Now do generic ELF adjustments. */
24666 elf_adjust_symtab ();
24670 /* MD interface: Initialization. */
24673 set_constant_flonums (void)
24677 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24678 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24682 /* Auto-select Thumb mode if it's the only available instruction set for the
24683 given architecture. */
24686 autoselect_thumb_from_cpu_variant (void)
24688 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24689 opcode_select (16);
24698 if ( (arm_ops_hsh
= hash_new ()) == NULL
24699 || (arm_cond_hsh
= hash_new ()) == NULL
24700 || (arm_shift_hsh
= hash_new ()) == NULL
24701 || (arm_psr_hsh
= hash_new ()) == NULL
24702 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24703 || (arm_reg_hsh
= hash_new ()) == NULL
24704 || (arm_reloc_hsh
= hash_new ()) == NULL
24705 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24706 as_fatal (_("virtual memory exhausted"));
24708 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24709 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24710 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24711 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24712 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24713 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24714 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24715 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24716 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24717 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24718 (void *) (v7m_psrs
+ i
));
24719 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24720 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24722 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24724 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24725 (void *) (barrier_opt_names
+ i
));
24727 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24729 struct reloc_entry
* entry
= reloc_names
+ i
;
24731 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24732 /* This makes encode_branch() use the EABI versions of this relocation. */
24733 entry
->reloc
= BFD_RELOC_UNUSED
;
24735 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24739 set_constant_flonums ();
24741 /* Set the cpu variant based on the command-line options. We prefer
24742 -mcpu= over -march= if both are set (as for GCC); and we prefer
24743 -mfpu= over any other way of setting the floating point unit.
24744 Use of legacy options with new options are faulted. */
24747 if (mcpu_cpu_opt
|| march_cpu_opt
)
24748 as_bad (_("use of old and new-style options to set CPU type"));
24750 mcpu_cpu_opt
= legacy_cpu
;
24752 else if (!mcpu_cpu_opt
)
24753 mcpu_cpu_opt
= march_cpu_opt
;
24758 as_bad (_("use of old and new-style options to set FPU type"));
24760 mfpu_opt
= legacy_fpu
;
24762 else if (!mfpu_opt
)
24764 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24765 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24766 /* Some environments specify a default FPU. If they don't, infer it
24767 from the processor. */
24769 mfpu_opt
= mcpu_fpu_opt
;
24771 mfpu_opt
= march_fpu_opt
;
24773 mfpu_opt
= &fpu_default
;
24779 if (mcpu_cpu_opt
!= NULL
)
24780 mfpu_opt
= &fpu_default
;
24781 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24782 mfpu_opt
= &fpu_arch_vfp_v2
;
24784 mfpu_opt
= &fpu_arch_fpa
;
24790 mcpu_cpu_opt
= &cpu_default
;
24791 selected_cpu
= cpu_default
;
24793 else if (no_cpu_selected ())
24794 selected_cpu
= cpu_default
;
24797 selected_cpu
= *mcpu_cpu_opt
;
24799 mcpu_cpu_opt
= &arm_arch_any
;
24802 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24804 autoselect_thumb_from_cpu_variant ();
24806 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24808 #if defined OBJ_COFF || defined OBJ_ELF
24810 unsigned int flags
= 0;
24812 #if defined OBJ_ELF
24813 flags
= meabi_flags
;
24815 switch (meabi_flags
)
24817 case EF_ARM_EABI_UNKNOWN
:
24819 /* Set the flags in the private structure. */
24820 if (uses_apcs_26
) flags
|= F_APCS26
;
24821 if (support_interwork
) flags
|= F_INTERWORK
;
24822 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24823 if (pic_code
) flags
|= F_PIC
;
24824 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24825 flags
|= F_SOFT_FLOAT
;
24827 switch (mfloat_abi_opt
)
24829 case ARM_FLOAT_ABI_SOFT
:
24830 case ARM_FLOAT_ABI_SOFTFP
:
24831 flags
|= F_SOFT_FLOAT
;
24834 case ARM_FLOAT_ABI_HARD
:
24835 if (flags
& F_SOFT_FLOAT
)
24836 as_bad (_("hard-float conflicts with specified fpu"));
24840 /* Using pure-endian doubles (even if soft-float). */
24841 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24842 flags
|= F_VFP_FLOAT
;
24844 #if defined OBJ_ELF
24845 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24846 flags
|= EF_ARM_MAVERICK_FLOAT
;
24849 case EF_ARM_EABI_VER4
:
24850 case EF_ARM_EABI_VER5
:
24851 /* No additional flags to set. */
24858 bfd_set_private_flags (stdoutput
, flags
);
24860 /* We have run out flags in the COFF header to encode the
24861 status of ATPCS support, so instead we create a dummy,
24862 empty, debug section called .arm.atpcs. */
24867 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24871 bfd_set_section_flags
24872 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24873 bfd_set_section_size (stdoutput
, sec
, 0);
24874 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24880 /* Record the CPU type as well. */
24881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24882 mach
= bfd_mach_arm_iWMMXt2
;
24883 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24884 mach
= bfd_mach_arm_iWMMXt
;
24885 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24886 mach
= bfd_mach_arm_XScale
;
24887 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24888 mach
= bfd_mach_arm_ep9312
;
24889 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24890 mach
= bfd_mach_arm_5TE
;
24891 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24894 mach
= bfd_mach_arm_5T
;
24896 mach
= bfd_mach_arm_5
;
24898 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24900 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24901 mach
= bfd_mach_arm_4T
;
24903 mach
= bfd_mach_arm_4
;
24905 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24906 mach
= bfd_mach_arm_3M
;
24907 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24908 mach
= bfd_mach_arm_3
;
24909 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24910 mach
= bfd_mach_arm_2a
;
24911 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24912 mach
= bfd_mach_arm_2
;
24914 mach
= bfd_mach_arm_unknown
;
24916 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24919 /* Command line processing. */
24922 Invocation line includes a switch not recognized by the base assembler.
24923 See if it's a processor-specific option.
24925 This routine is somewhat complicated by the need for backwards
24926 compatibility (since older releases of gcc can't be changed).
24927 The new options try to make the interface as compatible as
24930 New options (supported) are:
24932 -mcpu=<cpu name> Assemble for selected processor
24933 -march=<architecture name> Assemble for selected architecture
24934 -mfpu=<fpu architecture> Assemble for selected FPU.
24935 -EB/-mbig-endian Big-endian
24936 -EL/-mlittle-endian Little-endian
24937 -k Generate PIC code
24938 -mthumb Start in Thumb mode
24939 -mthumb-interwork Code supports ARM/Thumb interworking
24941 -m[no-]warn-deprecated Warn about deprecated features
24942 -m[no-]warn-syms Warn when symbols match instructions
24944 For now we will also provide support for:
24946 -mapcs-32 32-bit Program counter
24947 -mapcs-26 26-bit Program counter
24948 -macps-float Floats passed in FP registers
24949 -mapcs-reentrant Reentrant code
24951 (sometime these will probably be replaced with -mapcs=<list of options>
24952 and -matpcs=<list of options>)
24954 The remaining options are only supported for back-wards compatibility.
24955 Cpu variants, the arm part is optional:
24956 -m[arm]1 Currently not supported.
24957 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24958 -m[arm]3 Arm 3 processor
24959 -m[arm]6[xx], Arm 6 processors
24960 -m[arm]7[xx][t][[d]m] Arm 7 processors
24961 -m[arm]8[10] Arm 8 processors
24962 -m[arm]9[20][tdmi] Arm 9 processors
24963 -mstrongarm[110[0]] StrongARM processors
24964 -mxscale XScale processors
24965 -m[arm]v[2345[t[e]]] Arm architectures
24966 -mall All (except the ARM1)
24968 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24969 -mfpe-old (No float load/store multiples)
24970 -mvfpxd VFP Single precision
24972 -mno-fpu Disable all floating point instructions
24974 The following CPU names are recognized:
24975 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24976 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24977 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24978 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24979 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24980 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24981 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24985 const char * md_shortopts
= "m:k";
24987 #ifdef ARM_BI_ENDIAN
24988 #define OPTION_EB (OPTION_MD_BASE + 0)
24989 #define OPTION_EL (OPTION_MD_BASE + 1)
24991 #if TARGET_BYTES_BIG_ENDIAN
24992 #define OPTION_EB (OPTION_MD_BASE + 0)
24994 #define OPTION_EL (OPTION_MD_BASE + 1)
24997 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24999 struct option md_longopts
[] =
25002 {"EB", no_argument
, NULL
, OPTION_EB
},
25005 {"EL", no_argument
, NULL
, OPTION_EL
},
25007 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25008 {NULL
, no_argument
, NULL
, 0}
25012 size_t md_longopts_size
= sizeof (md_longopts
);
25014 struct arm_option_table
25016 const char *option
; /* Option name to match. */
25017 const char *help
; /* Help information. */
25018 int *var
; /* Variable to change. */
25019 int value
; /* What to change it to. */
25020 const char *deprecated
; /* If non-null, print this message. */
25023 struct arm_option_table arm_opts
[] =
25025 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25026 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25027 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25028 &support_interwork
, 1, NULL
},
25029 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25030 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25031 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25033 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25034 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25035 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25036 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25039 /* These are recognized by the assembler, but have no affect on code. */
25040 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25041 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25043 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25044 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25045 &warn_on_deprecated
, 0, NULL
},
25046 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25047 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25048 {NULL
, NULL
, NULL
, 0, NULL
}
25051 struct arm_legacy_option_table
25053 const char *option
; /* Option name to match. */
25054 const arm_feature_set
**var
; /* Variable to change. */
25055 const arm_feature_set value
; /* What to change it to. */
25056 const char *deprecated
; /* If non-null, print this message. */
25059 const struct arm_legacy_option_table arm_legacy_opts
[] =
25061 /* DON'T add any new processors to this list -- we want the whole list
25062 to go away... Add them to the processors table instead. */
25063 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25064 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25065 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25066 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25067 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25068 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25069 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25070 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25071 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25072 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25073 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25074 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25075 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25076 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25077 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25078 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25079 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25080 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25081 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25082 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25083 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25084 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25085 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25086 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25087 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25088 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25089 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25090 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25091 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25092 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25093 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25094 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25095 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25096 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25097 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25098 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25099 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25100 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25101 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25102 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25103 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25104 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25105 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25106 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25107 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25108 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25109 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25110 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25111 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25112 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25113 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25114 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25115 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25116 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25117 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25118 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25119 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25120 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25121 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25122 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25123 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25124 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25125 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25126 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25127 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25128 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25129 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25130 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25131 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25132 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25133 N_("use -mcpu=strongarm110")},
25134 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25135 N_("use -mcpu=strongarm1100")},
25136 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25137 N_("use -mcpu=strongarm1110")},
25138 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25139 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25140 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25142 /* Architecture variants -- don't add any more to this list either. */
25143 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25144 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25145 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25146 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25147 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25148 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25149 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25150 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25151 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25152 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25153 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25154 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25155 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25156 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25157 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25158 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25159 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25160 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25162 /* Floating point variants -- don't add any more to this list either. */
25163 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25164 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25165 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25166 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25167 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25169 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25172 struct arm_cpu_option_table
25176 const arm_feature_set value
;
25177 /* For some CPUs we assume an FPU unless the user explicitly sets
25179 const arm_feature_set default_fpu
;
25180 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25182 const char *canonical_name
;
25185 /* This list should, at a minimum, contain all the cpu names
25186 recognized by GCC. */
25187 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25188 static const struct arm_cpu_option_table arm_cpus
[] =
25190 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25191 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25192 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25193 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25194 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25195 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25196 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25197 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25198 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25199 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25200 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25201 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25202 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25203 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25204 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25205 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25206 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25207 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25208 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25209 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25210 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25211 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25212 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25213 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25214 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25215 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25216 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25217 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25218 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25219 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25220 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25221 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25222 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25223 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25224 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25225 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25226 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25227 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25228 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25229 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25230 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25231 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25232 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25233 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25234 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25235 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25236 /* For V5 or later processors we default to using VFP; but the user
25237 should really set the FPU type explicitly. */
25238 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25239 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25240 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25241 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25242 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25243 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25244 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25245 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25246 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25247 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25248 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25249 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25250 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25251 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25252 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25253 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25254 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25255 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25256 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25257 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25259 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25260 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25261 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25262 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25263 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25264 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25265 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25266 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25267 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25269 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25270 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25271 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25272 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25273 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25274 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25275 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25276 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25277 FPU_NONE
, "Cortex-A5"),
25278 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25280 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25281 ARM_FEATURE_COPROC (FPU_VFP_V3
25282 | FPU_NEON_EXT_V1
),
25284 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25285 ARM_FEATURE_COPROC (FPU_VFP_V3
25286 | FPU_NEON_EXT_V1
),
25288 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25290 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25292 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25294 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25296 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25298 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25300 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25302 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25304 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25305 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25307 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25308 FPU_NONE
, "Cortex-R5"),
25309 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25310 FPU_ARCH_VFP_V3D16
,
25312 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25313 FPU_ARCH_VFP_V3D16
,
25315 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25316 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25317 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25318 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25319 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25320 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25321 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25324 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25328 /* ??? XSCALE is really an architecture. */
25329 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25330 /* ??? iwmmxt is not a processor. */
25331 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25332 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25333 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25335 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25336 FPU_ARCH_MAVERICK
, "ARM920T"),
25337 /* Marvell processors. */
25338 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25340 ARM_EXT2_V6T2_V8M
),
25341 FPU_ARCH_VFP_V3D16
, NULL
),
25342 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25344 ARM_EXT2_V6T2_V8M
),
25345 FPU_ARCH_NEON_VFP_V4
, NULL
),
25346 /* APM X-Gene family. */
25347 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25349 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25352 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25356 struct arm_arch_option_table
25360 const arm_feature_set value
;
25361 const arm_feature_set default_fpu
;
25364 /* This list should, at a minimum, contain all the architecture names
25365 recognized by GCC. */
25366 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25367 static const struct arm_arch_option_table arm_archs
[] =
25369 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25370 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25371 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25372 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25373 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25374 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25375 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25376 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25377 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25378 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25379 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25380 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25381 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25382 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25383 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25384 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25385 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25386 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25387 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25388 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25389 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25390 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25391 kept to preserve existing behaviour. */
25392 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25393 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25394 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25395 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25396 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25397 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25398 kept to preserve existing behaviour. */
25399 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25400 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25401 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25402 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25403 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25404 /* The official spelling of the ARMv7 profile variants is the dashed form.
25405 Accept the non-dashed form for compatibility with old toolchains. */
25406 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25407 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25408 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25409 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25410 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25411 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25412 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25413 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25414 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25415 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25416 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25417 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25418 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25419 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25420 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25421 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25422 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25424 #undef ARM_ARCH_OPT
25426 /* ISA extensions in the co-processor and main instruction set space. */
25427 struct arm_option_extension_value_table
25431 const arm_feature_set merge_value
;
25432 const arm_feature_set clear_value
;
25433 const arm_feature_set allowed_archs
;
25436 /* The following table must be in alphabetical order with a NULL last entry.
25438 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
25439 static const struct arm_option_extension_value_table arm_extensions
[] =
25441 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25442 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25443 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25444 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25445 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25446 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25447 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25448 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25449 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25451 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25452 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25453 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25454 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25455 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
25456 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25457 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
25458 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25459 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
25460 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25461 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25462 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25463 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25464 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25465 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25466 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25467 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25468 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25469 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25470 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25471 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25472 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25473 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25474 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
25475 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25476 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25477 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25478 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25480 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25481 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25482 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25483 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
25484 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25488 /* ISA floating-point and Advanced SIMD extensions. */
25489 struct arm_option_fpu_value_table
25492 const arm_feature_set value
;
25495 /* This list should, at a minimum, contain all the fpu names
25496 recognized by GCC. */
25497 static const struct arm_option_fpu_value_table arm_fpus
[] =
25499 {"softfpa", FPU_NONE
},
25500 {"fpe", FPU_ARCH_FPE
},
25501 {"fpe2", FPU_ARCH_FPE
},
25502 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25503 {"fpa", FPU_ARCH_FPA
},
25504 {"fpa10", FPU_ARCH_FPA
},
25505 {"fpa11", FPU_ARCH_FPA
},
25506 {"arm7500fe", FPU_ARCH_FPA
},
25507 {"softvfp", FPU_ARCH_VFP
},
25508 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25509 {"vfp", FPU_ARCH_VFP_V2
},
25510 {"vfp9", FPU_ARCH_VFP_V2
},
25511 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25512 {"vfp10", FPU_ARCH_VFP_V2
},
25513 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25514 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25515 {"vfpv2", FPU_ARCH_VFP_V2
},
25516 {"vfpv3", FPU_ARCH_VFP_V3
},
25517 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25518 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25519 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25520 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25521 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25522 {"arm1020t", FPU_ARCH_VFP_V1
},
25523 {"arm1020e", FPU_ARCH_VFP_V2
},
25524 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25525 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25526 {"maverick", FPU_ARCH_MAVERICK
},
25527 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25528 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25529 {"vfpv4", FPU_ARCH_VFP_V4
},
25530 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25531 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25532 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25533 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25534 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25535 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25536 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25537 {"crypto-neon-fp-armv8",
25538 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25539 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25540 {"crypto-neon-fp-armv8.1",
25541 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25542 {NULL
, ARM_ARCH_NONE
}
25545 struct arm_option_value_table
25551 static const struct arm_option_value_table arm_float_abis
[] =
25553 {"hard", ARM_FLOAT_ABI_HARD
},
25554 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25555 {"soft", ARM_FLOAT_ABI_SOFT
},
25560 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25561 static const struct arm_option_value_table arm_eabis
[] =
25563 {"gnu", EF_ARM_EABI_UNKNOWN
},
25564 {"4", EF_ARM_EABI_VER4
},
25565 {"5", EF_ARM_EABI_VER5
},
25570 struct arm_long_option_table
25572 const char * option
; /* Substring to match. */
25573 const char * help
; /* Help information. */
25574 int (* func
) (char * subopt
); /* Function to decode sub-option. */
25575 const char * deprecated
; /* If non-null, print this message. */
25579 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
25581 arm_feature_set
*ext_set
= (arm_feature_set
*)
25582 xmalloc (sizeof (arm_feature_set
));
25584 /* We insist on extensions being specified in alphabetical order, and with
25585 extensions being added before being removed. We achieve this by having
25586 the global ARM_EXTENSIONS table in alphabetical order, and using the
25587 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25588 or removing it (0) and only allowing it to change in the order
25590 const struct arm_option_extension_value_table
* opt
= NULL
;
25591 int adding_value
= -1;
25593 /* Copy the feature set, so that we can modify it. */
25594 *ext_set
= **opt_p
;
25597 while (str
!= NULL
&& *str
!= 0)
25604 as_bad (_("invalid architectural extension"));
25609 ext
= strchr (str
, '+');
25614 len
= strlen (str
);
25616 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25618 if (adding_value
!= 0)
25621 opt
= arm_extensions
;
25629 if (adding_value
== -1)
25632 opt
= arm_extensions
;
25634 else if (adding_value
!= 1)
25636 as_bad (_("must specify extensions to add before specifying "
25637 "those to remove"));
25644 as_bad (_("missing architectural extension"));
25648 gas_assert (adding_value
!= -1);
25649 gas_assert (opt
!= NULL
);
25651 /* Scan over the options table trying to find an exact match. */
25652 for (; opt
->name
!= NULL
; opt
++)
25653 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25655 /* Check we can apply the extension to this architecture. */
25656 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25658 as_bad (_("extension does not apply to the base architecture"));
25662 /* Add or remove the extension. */
25664 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25666 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25671 if (opt
->name
== NULL
)
25673 /* Did we fail to find an extension because it wasn't specified in
25674 alphabetical order, or because it does not exist? */
25676 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25677 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25680 if (opt
->name
== NULL
)
25681 as_bad (_("unknown architectural extension `%s'"), str
);
25683 as_bad (_("architectural extensions must be specified in "
25684 "alphabetical order"));
25690 /* We should skip the extension we've just matched the next time
25702 arm_parse_cpu (char *str
)
25704 const struct arm_cpu_option_table
*opt
;
25705 char *ext
= strchr (str
, '+');
25711 len
= strlen (str
);
25715 as_bad (_("missing cpu name `%s'"), str
);
25719 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25720 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25722 mcpu_cpu_opt
= &opt
->value
;
25723 mcpu_fpu_opt
= &opt
->default_fpu
;
25724 if (opt
->canonical_name
)
25726 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25727 strcpy (selected_cpu_name
, opt
->canonical_name
);
25733 if (len
>= sizeof selected_cpu_name
)
25734 len
= (sizeof selected_cpu_name
) - 1;
25736 for (i
= 0; i
< len
; i
++)
25737 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25738 selected_cpu_name
[i
] = 0;
25742 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25747 as_bad (_("unknown cpu `%s'"), str
);
25752 arm_parse_arch (char *str
)
25754 const struct arm_arch_option_table
*opt
;
25755 char *ext
= strchr (str
, '+');
25761 len
= strlen (str
);
25765 as_bad (_("missing architecture name `%s'"), str
);
25769 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25770 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25772 march_cpu_opt
= &opt
->value
;
25773 march_fpu_opt
= &opt
->default_fpu
;
25774 strcpy (selected_cpu_name
, opt
->name
);
25777 return arm_parse_extension (ext
, &march_cpu_opt
);
25782 as_bad (_("unknown architecture `%s'\n"), str
);
25787 arm_parse_fpu (char * str
)
25789 const struct arm_option_fpu_value_table
* opt
;
25791 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25792 if (streq (opt
->name
, str
))
25794 mfpu_opt
= &opt
->value
;
25798 as_bad (_("unknown floating point format `%s'\n"), str
);
25803 arm_parse_float_abi (char * str
)
25805 const struct arm_option_value_table
* opt
;
25807 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25808 if (streq (opt
->name
, str
))
25810 mfloat_abi_opt
= opt
->value
;
25814 as_bad (_("unknown floating point abi `%s'\n"), str
);
25820 arm_parse_eabi (char * str
)
25822 const struct arm_option_value_table
*opt
;
25824 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25825 if (streq (opt
->name
, str
))
25827 meabi_flags
= opt
->value
;
25830 as_bad (_("unknown EABI `%s'\n"), str
);
25836 arm_parse_it_mode (char * str
)
25838 bfd_boolean ret
= TRUE
;
25840 if (streq ("arm", str
))
25841 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25842 else if (streq ("thumb", str
))
25843 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25844 else if (streq ("always", str
))
25845 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25846 else if (streq ("never", str
))
25847 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25850 as_bad (_("unknown implicit IT mode `%s', should be "\
25851 "arm, thumb, always, or never."), str
);
25859 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25861 codecomposer_syntax
= TRUE
;
25862 arm_comment_chars
[0] = ';';
25863 arm_line_separator_chars
[0] = 0;
25867 struct arm_long_option_table arm_long_opts
[] =
25869 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25870 arm_parse_cpu
, NULL
},
25871 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25872 arm_parse_arch
, NULL
},
25873 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25874 arm_parse_fpu
, NULL
},
25875 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25876 arm_parse_float_abi
, NULL
},
25878 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25879 arm_parse_eabi
, NULL
},
25881 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25882 arm_parse_it_mode
, NULL
},
25883 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25884 arm_ccs_mode
, NULL
},
25885 {NULL
, NULL
, 0, NULL
}
25889 md_parse_option (int c
, char * arg
)
25891 struct arm_option_table
*opt
;
25892 const struct arm_legacy_option_table
*fopt
;
25893 struct arm_long_option_table
*lopt
;
25899 target_big_endian
= 1;
25905 target_big_endian
= 0;
25909 case OPTION_FIX_V4BX
:
25914 /* Listing option. Just ignore these, we don't support additional
25919 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25921 if (c
== opt
->option
[0]
25922 && ((arg
== NULL
&& opt
->option
[1] == 0)
25923 || streq (arg
, opt
->option
+ 1)))
25925 /* If the option is deprecated, tell the user. */
25926 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25927 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25928 arg
? arg
: "", _(opt
->deprecated
));
25930 if (opt
->var
!= NULL
)
25931 *opt
->var
= opt
->value
;
25937 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25939 if (c
== fopt
->option
[0]
25940 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25941 || streq (arg
, fopt
->option
+ 1)))
25943 /* If the option is deprecated, tell the user. */
25944 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25945 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25946 arg
? arg
: "", _(fopt
->deprecated
));
25948 if (fopt
->var
!= NULL
)
25949 *fopt
->var
= &fopt
->value
;
25955 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25957 /* These options are expected to have an argument. */
25958 if (c
== lopt
->option
[0]
25960 && strncmp (arg
, lopt
->option
+ 1,
25961 strlen (lopt
->option
+ 1)) == 0)
25963 /* If the option is deprecated, tell the user. */
25964 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25965 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25966 _(lopt
->deprecated
));
25968 /* Call the sup-option parser. */
25969 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25980 md_show_usage (FILE * fp
)
25982 struct arm_option_table
*opt
;
25983 struct arm_long_option_table
*lopt
;
25985 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25987 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25988 if (opt
->help
!= NULL
)
25989 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25991 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25992 if (lopt
->help
!= NULL
)
25993 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25997 -EB assemble code for a big-endian cpu\n"));
26002 -EL assemble code for a little-endian cpu\n"));
26006 --fix-v4bx Allow BX in ARMv4 code\n"));
26014 arm_feature_set flags
;
26015 } cpu_arch_ver_table
;
26017 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26018 must be sorted least features first but some reordering is needed, eg. for
26019 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26020 static const cpu_arch_ver_table cpu_arch_ver
[] =
26026 {4, ARM_ARCH_V5TE
},
26027 {5, ARM_ARCH_V5TEJ
},
26031 {11, ARM_ARCH_V6M
},
26032 {12, ARM_ARCH_V6SM
},
26033 {8, ARM_ARCH_V6T2
},
26034 {10, ARM_ARCH_V7VE
},
26035 {10, ARM_ARCH_V7R
},
26036 {10, ARM_ARCH_V7M
},
26037 {14, ARM_ARCH_V8A
},
26038 {16, ARM_ARCH_V8M_BASE
},
26039 {17, ARM_ARCH_V8M_MAIN
},
26043 /* Set an attribute if it has not already been set by the user. */
26045 aeabi_set_attribute_int (int tag
, int value
)
26048 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26049 || !attributes_set_explicitly
[tag
])
26050 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26054 aeabi_set_attribute_string (int tag
, const char *value
)
26057 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26058 || !attributes_set_explicitly
[tag
])
26059 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26062 /* Set the public EABI object attributes. */
26064 aeabi_set_public_attributes (void)
26069 int fp16_optional
= 0;
26070 arm_feature_set flags
;
26071 arm_feature_set tmp
;
26072 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26073 const cpu_arch_ver_table
*p
;
26075 /* Choose the architecture based on the capabilities of the requested cpu
26076 (if any) and/or the instructions actually used. */
26077 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26078 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26079 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26081 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26082 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26084 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26085 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26087 selected_cpu
= flags
;
26089 /* Allow the user to override the reported architecture. */
26092 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26093 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26096 /* We need to make sure that the attributes do not identify us as v6S-M
26097 when the only v6S-M feature in use is the Operating System Extensions. */
26098 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26099 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26100 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26104 for (p
= cpu_arch_ver
; p
->val
; p
++)
26106 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26109 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26113 /* The table lookup above finds the last architecture to contribute
26114 a new feature. Unfortunately, Tag13 is a subset of the union of
26115 v6T2 and v7-M, so it is never seen as contributing a new feature.
26116 We can not search for the last entry which is entirely used,
26117 because if no CPU is specified we build up only those flags
26118 actually used. Perhaps we should separate out the specified
26119 and implicit cases. Avoid taking this path for -march=all by
26120 checking for contradictory v7-A / v7-M features. */
26121 if (arch
== TAG_CPU_ARCH_V7
26122 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26123 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26124 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26125 arch
= TAG_CPU_ARCH_V7E_M
;
26127 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26128 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26129 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26131 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26132 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26133 ARMv8-M, -march=all must be detected as ARMv8-A. */
26134 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26135 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26136 arch
= TAG_CPU_ARCH_V8
;
26138 /* Tag_CPU_name. */
26139 if (selected_cpu_name
[0])
26143 q
= selected_cpu_name
;
26144 if (strncmp (q
, "armv", 4) == 0)
26149 for (i
= 0; q
[i
]; i
++)
26150 q
[i
] = TOUPPER (q
[i
]);
26152 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26155 /* Tag_CPU_arch. */
26156 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26158 /* Tag_CPU_arch_profile. */
26159 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26160 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26161 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26162 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
)))
26164 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26166 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26171 if (profile
!= '\0')
26172 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26174 /* Tag_ARM_ISA_use. */
26175 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26177 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26179 /* Tag_THUMB_ISA_use. */
26180 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26185 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26186 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26188 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26192 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26195 /* Tag_VFP_arch. */
26196 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26197 aeabi_set_attribute_int (Tag_VFP_arch
,
26198 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26200 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26201 aeabi_set_attribute_int (Tag_VFP_arch
,
26202 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26204 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26207 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26209 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26211 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26214 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26215 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26216 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26217 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26218 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26220 /* Tag_ABI_HardFP_use. */
26221 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26222 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26223 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26225 /* Tag_WMMX_arch. */
26226 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26227 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26228 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26229 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26231 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26232 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26233 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26234 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26235 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26236 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26238 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26240 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26244 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26249 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26250 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26251 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26255 We set Tag_DIV_use to two when integer divide instructions have been used
26256 in ARM state, or when Thumb integer divide instructions have been used,
26257 but we have no architecture profile set, nor have we any ARM instructions.
26259 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26260 by the base architecture.
26262 For new architectures we will have to check these tests. */
26263 gas_assert (arch
<= TAG_CPU_ARCH_V8
26264 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26265 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26266 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26267 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26268 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26269 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26270 || (profile
== '\0'
26271 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26272 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26273 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26275 /* Tag_MP_extension_use. */
26276 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26277 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26279 /* Tag Virtualization_use. */
26280 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26282 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26285 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26288 /* Add the default contents for the .ARM.attributes section. */
26292 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26295 aeabi_set_public_attributes ();
26297 #endif /* OBJ_ELF */
26300 /* Parse a .cpu directive. */
26303 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26305 const struct arm_cpu_option_table
*opt
;
26309 name
= input_line_pointer
;
26310 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26311 input_line_pointer
++;
26312 saved_char
= *input_line_pointer
;
26313 *input_line_pointer
= 0;
26315 /* Skip the first "all" entry. */
26316 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26317 if (streq (opt
->name
, name
))
26319 mcpu_cpu_opt
= &opt
->value
;
26320 selected_cpu
= opt
->value
;
26321 if (opt
->canonical_name
)
26322 strcpy (selected_cpu_name
, opt
->canonical_name
);
26326 for (i
= 0; opt
->name
[i
]; i
++)
26327 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26329 selected_cpu_name
[i
] = 0;
26331 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26332 *input_line_pointer
= saved_char
;
26333 demand_empty_rest_of_line ();
26336 as_bad (_("unknown cpu `%s'"), name
);
26337 *input_line_pointer
= saved_char
;
26338 ignore_rest_of_line ();
26342 /* Parse a .arch directive. */
26345 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26347 const struct arm_arch_option_table
*opt
;
26351 name
= input_line_pointer
;
26352 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26353 input_line_pointer
++;
26354 saved_char
= *input_line_pointer
;
26355 *input_line_pointer
= 0;
26357 /* Skip the first "all" entry. */
26358 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26359 if (streq (opt
->name
, name
))
26361 mcpu_cpu_opt
= &opt
->value
;
26362 selected_cpu
= opt
->value
;
26363 strcpy (selected_cpu_name
, opt
->name
);
26364 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26365 *input_line_pointer
= saved_char
;
26366 demand_empty_rest_of_line ();
26370 as_bad (_("unknown architecture `%s'\n"), name
);
26371 *input_line_pointer
= saved_char
;
26372 ignore_rest_of_line ();
26376 /* Parse a .object_arch directive. */
26379 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26381 const struct arm_arch_option_table
*opt
;
26385 name
= input_line_pointer
;
26386 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26387 input_line_pointer
++;
26388 saved_char
= *input_line_pointer
;
26389 *input_line_pointer
= 0;
26391 /* Skip the first "all" entry. */
26392 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26393 if (streq (opt
->name
, name
))
26395 object_arch
= &opt
->value
;
26396 *input_line_pointer
= saved_char
;
26397 demand_empty_rest_of_line ();
26401 as_bad (_("unknown architecture `%s'\n"), name
);
26402 *input_line_pointer
= saved_char
;
26403 ignore_rest_of_line ();
26406 /* Parse a .arch_extension directive. */
26409 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26411 const struct arm_option_extension_value_table
*opt
;
26414 int adding_value
= 1;
26416 name
= input_line_pointer
;
26417 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26418 input_line_pointer
++;
26419 saved_char
= *input_line_pointer
;
26420 *input_line_pointer
= 0;
26422 if (strlen (name
) >= 2
26423 && strncmp (name
, "no", 2) == 0)
26429 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26430 if (streq (opt
->name
, name
))
26432 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
26434 as_bad (_("architectural extension `%s' is not allowed for the "
26435 "current base architecture"), name
);
26440 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26443 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26445 mcpu_cpu_opt
= &selected_cpu
;
26446 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26447 *input_line_pointer
= saved_char
;
26448 demand_empty_rest_of_line ();
26452 if (opt
->name
== NULL
)
26453 as_bad (_("unknown architecture extension `%s'\n"), name
);
26455 *input_line_pointer
= saved_char
;
26456 ignore_rest_of_line ();
26459 /* Parse a .fpu directive. */
26462 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26464 const struct arm_option_fpu_value_table
*opt
;
26468 name
= input_line_pointer
;
26469 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26470 input_line_pointer
++;
26471 saved_char
= *input_line_pointer
;
26472 *input_line_pointer
= 0;
26474 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26475 if (streq (opt
->name
, name
))
26477 mfpu_opt
= &opt
->value
;
26478 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26479 *input_line_pointer
= saved_char
;
26480 demand_empty_rest_of_line ();
26484 as_bad (_("unknown floating point format `%s'\n"), name
);
26485 *input_line_pointer
= saved_char
;
26486 ignore_rest_of_line ();
26489 /* Copy symbol information. */
26492 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26494 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26498 /* Given a symbolic attribute NAME, return the proper integer value.
26499 Returns -1 if the attribute is not known. */
26502 arm_convert_symbolic_attribute (const char *name
)
26504 static const struct
26509 attribute_table
[] =
26511 /* When you modify this table you should
26512 also modify the list in doc/c-arm.texi. */
26513 #define T(tag) {#tag, tag}
26514 T (Tag_CPU_raw_name
),
26517 T (Tag_CPU_arch_profile
),
26518 T (Tag_ARM_ISA_use
),
26519 T (Tag_THUMB_ISA_use
),
26523 T (Tag_Advanced_SIMD_arch
),
26524 T (Tag_PCS_config
),
26525 T (Tag_ABI_PCS_R9_use
),
26526 T (Tag_ABI_PCS_RW_data
),
26527 T (Tag_ABI_PCS_RO_data
),
26528 T (Tag_ABI_PCS_GOT_use
),
26529 T (Tag_ABI_PCS_wchar_t
),
26530 T (Tag_ABI_FP_rounding
),
26531 T (Tag_ABI_FP_denormal
),
26532 T (Tag_ABI_FP_exceptions
),
26533 T (Tag_ABI_FP_user_exceptions
),
26534 T (Tag_ABI_FP_number_model
),
26535 T (Tag_ABI_align_needed
),
26536 T (Tag_ABI_align8_needed
),
26537 T (Tag_ABI_align_preserved
),
26538 T (Tag_ABI_align8_preserved
),
26539 T (Tag_ABI_enum_size
),
26540 T (Tag_ABI_HardFP_use
),
26541 T (Tag_ABI_VFP_args
),
26542 T (Tag_ABI_WMMX_args
),
26543 T (Tag_ABI_optimization_goals
),
26544 T (Tag_ABI_FP_optimization_goals
),
26545 T (Tag_compatibility
),
26546 T (Tag_CPU_unaligned_access
),
26547 T (Tag_FP_HP_extension
),
26548 T (Tag_VFP_HP_extension
),
26549 T (Tag_ABI_FP_16bit_format
),
26550 T (Tag_MPextension_use
),
26552 T (Tag_nodefaults
),
26553 T (Tag_also_compatible_with
),
26554 T (Tag_conformance
),
26556 T (Tag_Virtualization_use
),
26557 /* We deliberately do not include Tag_MPextension_use_legacy. */
26565 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26566 if (streq (name
, attribute_table
[i
].name
))
26567 return attribute_table
[i
].tag
;
26573 /* Apply sym value for relocations only in the case that they are for
26574 local symbols in the same segment as the fixup and you have the
26575 respective architectural feature for blx and simple switches. */
26577 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26580 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26581 /* PR 17444: If the local symbol is in a different section then a reloc
26582 will always be generated for it, so applying the symbol value now
26583 will result in a double offset being stored in the relocation. */
26584 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26585 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26587 switch (fixP
->fx_r_type
)
26589 case BFD_RELOC_ARM_PCREL_BLX
:
26590 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26591 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26595 case BFD_RELOC_ARM_PCREL_CALL
:
26596 case BFD_RELOC_THUMB_PCREL_BLX
:
26597 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26608 #endif /* OBJ_ELF */