1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
357 unsigned long instruction
;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype
;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type
;
379 enum it_instruction_type it_insn_type
;
385 struct neon_type_el vectype
;
386 unsigned present
: 1; /* Operand present. */
387 unsigned isreg
: 1; /* Operand was a register. */
388 unsigned immisreg
: 1; /* .imm field is a second register. */
389 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
399 unsigned writeback
: 1; /* Operand has trailing ! */
400 unsigned preind
: 1; /* Preindexed address. */
401 unsigned postind
: 1; /* Postindexed address. */
402 unsigned negative
: 1; /* Index register was negated. */
403 unsigned shifted
: 1; /* Shift applied to operation. */
404 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst
;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const
[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name
;
444 #define COND_ALWAYS 0xE
448 const char * template_name
;
452 struct asm_barrier_opt
454 const char * template_name
;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc
;
475 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
476 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
481 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined
;
492 struct neon_type_el eltype
;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin
;
533 struct neon_typed_alias
* neon
;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs
[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name
;
576 /* Parameters to instruction. */
577 unsigned int operands
[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag
: 4;
582 /* Basic instruction code. */
583 unsigned int avalue
: 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set
* avariant
;
590 const arm_feature_set
* tvariant
;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode
) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode
) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control
* arm_ops_hsh
;
729 static struct hash_control
* arm_cond_hsh
;
730 static struct hash_control
* arm_shift_hsh
;
731 static struct hash_control
* arm_psr_hsh
;
732 static struct hash_control
* arm_v7m_psr_hsh
;
733 static struct hash_control
* arm_reg_hsh
;
734 static struct hash_control
* arm_reloc_hsh
;
735 static struct hash_control
* arm_barrier_opt_hsh
;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS
* last_label_seen
;
747 static int label_is_thumb_function_name
= FALSE
;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
756 unsigned int next_free_entry
;
761 struct literal_pool
* next
;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool
* list_of_pools
= NULL
;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it
;
774 now_it_compatible (int cond
)
776 return (cond
& ~1) == (now_it
.cc
& ~1);
780 conditional_insn (void)
782 return inst
.cond
!= COND_ALWAYS
;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars
[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars
[] = "#";
836 const char line_separator_chars
[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS
[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str
, char c
)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS
* sp
)
877 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
880 if (symbol_get_value_expression (sp
)->X_add_symbol
)
882 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
883 || (symbol_get_value_expression (sp
)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
890 static int in_my_get_expression
= 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
913 case GE_NO_PREFIX
: break;
915 if (!is_immediate_prefix (**str
))
917 inst
.error
= _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG
:
924 if (is_immediate_prefix (**str
))
930 memset (ep
, 0, sizeof (expressionS
));
932 save_in
= input_line_pointer
;
933 input_line_pointer
= *str
;
934 in_my_get_expression
= 1;
935 seg
= expression (ep
);
936 in_my_get_expression
= 0;
938 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
940 /* We found a bad or missing expression in md_operand(). */
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
943 if (inst
.error
== NULL
)
944 inst
.error
= (ep
->X_op
== O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg
!= absolute_section
951 && seg
!= text_section
952 && seg
!= data_section
953 && seg
!= bss_section
954 && seg
!= undefined_section
)
956 inst
.error
= _("bad segment");
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode
!= GE_OPT_PREFIX_BIG
969 && (ep
->X_op
== O_big
971 && (walk_no_bignums (ep
->X_add_symbol
)
973 && walk_no_bignums (ep
->X_op_symbol
))))))
975 inst
.error
= _("invalid constant");
976 *str
= input_line_pointer
;
977 input_line_pointer
= save_in
;
981 *str
= input_line_pointer
;
982 input_line_pointer
= save_in
;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type
, char * litP
, int * sizeP
)
1004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t
= atof_ieee (input_line_pointer
, type
, words
);
1041 input_line_pointer
= t
;
1042 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1044 if (target_big_endian
)
1046 for (i
= 0; i
< prec
; i
++)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1055 for (i
= prec
- 1; i
>= 0; i
--)
1057 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1058 litP
+= sizeof (LITTLENUM_TYPE
);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i
= 0; i
< prec
; i
+= 2)
1065 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1066 sizeof (LITTLENUM_TYPE
));
1067 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1068 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1069 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS
* exp
)
1081 if (in_my_get_expression
)
1082 exp
->X_op
= O_illegal
;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val
)
1095 exp
.X_op
= O_illegal
;
1097 if (is_immediate_prefix (*input_line_pointer
))
1099 input_line_pointer
++;
1103 if (exp
.X_op
!= O_constant
)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val
= exp
.X_add_number
;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry
*
1122 arm_reg_parse_multi (char **ccp
)
1126 struct reg_entry
*reg
;
1128 #ifdef REGISTER_PREFIX
1129 if (*start
!= REGISTER_PREFIX
)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1139 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1144 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1146 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1156 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1157 enum arm_reg_type type
)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg
&& reg
->type
== REG_TYPE_CN
)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor
= strtoul (start
, ccp
, 10);
1175 if (*ccp
!= start
&& processor
<= 15)
1179 case REG_TYPE_MMXWC
:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1200 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1207 if (reg
&& reg
->type
== type
)
1210 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type
*type
, char **str
)
1239 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1241 enum neon_el_type thistype
= NT_untyped
;
1242 unsigned thissize
= -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr
))
1255 case 'i': thistype
= NT_integer
; break;
1256 case 'f': thistype
= NT_float
; break;
1257 case 'p': thistype
= NT_poly
; break;
1258 case 's': thistype
= NT_signed
; break;
1259 case 'u': thistype
= NT_unsigned
; break;
1261 thistype
= NT_float
;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1278 thissize
= strtoul (ptr
, &ptr
, 10);
1280 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1283 as_bad (_("bad size %d in type specifier"), thissize
);
1291 type
->el
[type
->elems
].type
= thistype
;
1292 type
->el
[type
->elems
].size
= thissize
;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type
->elems
== 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err
)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1323 struct neon_type optype
;
1327 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1329 if (optype
.elems
== 1)
1330 *vectype
= optype
.el
[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1364 enum arm_reg_type
*rtype
,
1365 struct neon_typed_alias
*typeinfo
)
1368 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1369 struct neon_typed_alias atype
;
1370 struct neon_type_el parsetype
;
1374 atype
.eltype
.type
= NT_invtype
;
1375 atype
.eltype
.size
= -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type
== REG_TYPE_NDQ
1391 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1392 || (type
== REG_TYPE_VFSD
1393 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1394 || (type
== REG_TYPE_NSDQ
1395 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1396 || reg
->type
== REG_TYPE_NQ
))
1397 || (type
== REG_TYPE_MMXWC
1398 && (reg
->type
== REG_TYPE_MMXWCG
)))
1399 type
= (enum arm_reg_type
) reg
->type
;
1401 if (type
!= reg
->type
)
1407 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1409 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype
.defined
|= NTA_HASTYPE
;
1415 atype
.eltype
= parsetype
;
1418 if (skip_past_char (&str
, '[') == SUCCESS
)
1420 if (type
!= REG_TYPE_VFD
)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype
.defined
|= NTA_HASINDEX
;
1434 if (skip_past_char (&str
, ']') == SUCCESS
)
1435 atype
.index
= NEON_ALL_LANES
;
1440 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1442 if (exp
.X_op
!= O_constant
)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str
, ']') == FAIL
)
1451 atype
.index
= exp
.X_add_number
;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1475 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1477 struct neon_typed_alias atype
;
1479 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype
= atype
.eltype
;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1515 struct neon_typed_alias atype
;
1517 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1519 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1522 if (atype
.index
== NEON_ALL_LANES
)
1524 first_error (_("scalar must have an index"));
1527 else if (atype
.index
>= 64 / elsize
)
1529 first_error (_("scalar index out of range"));
1534 *type
= atype
.eltype
;
1538 return reg
* 16 + atype
.index
;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp
)
1546 char * str
= * strp
;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1567 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1577 first_error (_("bad range in register list"));
1581 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1583 if (range
& (1 << i
))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range
& (1 << reg
))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg
<= cur_reg
)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str
) != FAIL
1603 || (in_range
= 1, *str
++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1619 if (exp
.X_op
== O_constant
)
1621 if (exp
.X_add_number
1622 != (exp
.X_add_number
& 0x0000ffff))
1624 inst
.error
= _("invalid register mask");
1628 if ((range
& exp
.X_add_number
) != 0)
1630 int regno
= range
& exp
.X_add_number
;
1633 regno
= (1 << regno
) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range
|= exp
.X_add_number
;
1643 if (inst
.reloc
.type
!= 0)
1645 inst
.error
= _("expression too complex");
1649 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1650 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1651 inst
.reloc
.pc_rel
= 0;
1655 if (*str
== '|' || *str
== '+')
1661 while (another_range
);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1697 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1701 unsigned long mask
= 0;
1706 inst
.error
= _("expecting {");
1715 regtype
= REG_TYPE_VFS
;
1720 regtype
= REG_TYPE_VFD
;
1723 case REGLIST_NEON_D
:
1724 regtype
= REG_TYPE_NDQ
;
1728 if (etype
!= REGLIST_VFP_S
)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1745 base_reg
= max_regs
;
1749 int setmask
= 1, addregs
= 1;
1751 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1753 if (new_base
== FAIL
)
1755 first_error (_(reg_expected_msgs
[regtype
]));
1759 if (new_base
>= max_regs
)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype
== REG_TYPE_NQ
)
1772 if (new_base
< base_reg
)
1773 base_reg
= new_base
;
1775 if (mask
& (setmask
<< new_base
))
1777 first_error (_("invalid register list"));
1781 if ((mask
>> new_base
) != 0 && ! warned
)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask
|= setmask
<< new_base
;
1790 if (*str
== '-') /* We have the start of a range expression */
1796 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1799 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1803 if (high_range
>= max_regs
)
1805 first_error (_("register out of range in list"));
1809 if (regtype
== REG_TYPE_NQ
)
1810 high_range
= high_range
+ 1;
1812 if (high_range
<= new_base
)
1814 inst
.error
= _("register range not in ascending order");
1818 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1820 if (mask
& (setmask
<< new_base
))
1822 inst
.error
= _("invalid register list");
1826 mask
|= setmask
<< new_base
;
1831 while (skip_past_comma (&str
) != FAIL
);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count
== 0 || count
> max_regs
)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i
= 0; i
< count
; i
++)
1845 if ((mask
& (1u << i
)) == 0)
1847 inst
.error
= _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1868 if (a
->defined
!= b
->defined
)
1871 if ((a
->defined
& NTA_HASTYPE
) != 0
1872 && (a
->eltype
.type
!= b
->eltype
.type
1873 || a
->eltype
.size
!= b
->eltype
.size
))
1876 if ((a
->defined
& NTA_HASINDEX
) != 0
1877 && (a
->index
!= b
->index
))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1897 struct neon_type_el
*eltype
)
1904 int leading_brace
= 0;
1905 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1906 const char *const incr_error
= _("register stride must be 1 or 2");
1907 const char *const type_error
= _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype
;
1910 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1915 struct neon_typed_alias atype
;
1916 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1920 first_error (_(reg_expected_msgs
[rtype
]));
1927 if (rtype
== REG_TYPE_NQ
)
1933 else if (reg_incr
== -1)
1935 reg_incr
= getreg
- base_reg
;
1936 if (reg_incr
< 1 || reg_incr
> 2)
1938 first_error (_(incr_error
));
1942 else if (getreg
!= base_reg
+ reg_incr
* count
)
1944 first_error (_(incr_error
));
1948 if (! neon_alias_types_same (&atype
, &firsttype
))
1950 first_error (_(type_error
));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype
;
1959 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1961 lane
= NEON_INTERLEAVE_LANES
;
1962 else if (lane
!= NEON_INTERLEAVE_LANES
)
1964 first_error (_(type_error
));
1969 else if (reg_incr
!= 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1978 first_error (_(reg_expected_msgs
[rtype
]));
1981 if (! neon_alias_types_same (&htype
, &firsttype
))
1983 first_error (_(type_error
));
1986 count
+= hireg
+ dregs
- getreg
;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype
== REG_TYPE_NQ
)
1997 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2001 else if (lane
!= atype
.index
)
2003 first_error (_(type_error
));
2007 else if (lane
== -1)
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane
= NEON_INTERLEAVE_LANES
;
2023 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2024 || (count
> 1 && reg_incr
== -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2032 first_error (_("expected }"));
2040 *eltype
= firsttype
.eltype
;
2045 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str
)
2056 struct reloc_entry
*r
;
2060 return BFD_RELOC_UNUSED
;
2065 while (*q
&& *q
!= ')' && *q
!= ',')
2070 if ((r
= (struct reloc_entry
*)
2071 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2078 /* Directives: register aliases. */
2080 static struct reg_entry
*
2081 insert_reg_alias (char *str
, unsigned number
, int type
)
2083 struct reg_entry
*new_reg
;
2086 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2088 if (new_reg
->builtin
)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2099 name
= xstrdup (str
);
2100 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2102 new_reg
->name
= name
;
2103 new_reg
->number
= number
;
2104 new_reg
->type
= type
;
2105 new_reg
->builtin
= FALSE
;
2106 new_reg
->neon
= NULL
;
2108 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2115 insert_neon_reg_alias (char *str
, int number
, int type
,
2116 struct neon_typed_alias
*atype
)
2118 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg
->neon
= (struct neon_typed_alias
*)
2129 xmalloc (sizeof (struct neon_typed_alias
));
2130 *reg
->neon
= *atype
;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname
, char *p
)
2144 struct reg_entry
*old
;
2145 char *oldname
, *nbuf
;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname
, " .req ", 6) != 0)
2155 if (*oldname
== '\0')
2158 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname
= original_case_string
;
2172 nlen
= strlen (newname
);
2175 nbuf
= (char *) alloca (nlen
+ 1);
2176 memcpy (nbuf
, newname
, nlen
);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2184 for (p
= nbuf
; *p
; p
++)
2187 if (strncmp (nbuf
, newname
, nlen
))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2202 for (p
= nbuf
; *p
; p
++)
2205 if (strncmp (nbuf
, newname
, nlen
))
2206 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname
, char *p
)
2225 enum arm_reg_type basetype
;
2226 struct reg_entry
*basereg
;
2227 struct reg_entry mybasereg
;
2228 struct neon_type ntype
;
2229 struct neon_typed_alias typeinfo
;
2230 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2233 typeinfo
.defined
= 0;
2234 typeinfo
.eltype
.type
= NT_invtype
;
2235 typeinfo
.eltype
.size
= -1;
2236 typeinfo
.index
= -1;
2240 if (strncmp (p
, " .dn ", 5) == 0)
2241 basetype
= REG_TYPE_VFD
;
2242 else if (strncmp (p
, " .qn ", 5) == 0)
2243 basetype
= REG_TYPE_NQ
;
2252 basereg
= arm_reg_parse_multi (&p
);
2254 if (basereg
&& basereg
->type
!= basetype
)
2256 as_bad (_("bad type for register"));
2260 if (basereg
== NULL
)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2265 if (exp
.X_op
!= O_constant
)
2267 as_bad (_("expression must be constant"));
2270 basereg
= &mybasereg
;
2271 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2277 typeinfo
= *basereg
->neon
;
2279 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2281 /* We got a type. */
2282 if (typeinfo
.defined
& NTA_HASTYPE
)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo
.defined
|= NTA_HASTYPE
;
2289 if (ntype
.elems
!= 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo
.eltype
= ntype
.el
[0];
2297 if (skip_past_char (&p
, '[') == SUCCESS
)
2300 /* We got a scalar index. */
2302 if (typeinfo
.defined
& NTA_HASINDEX
)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2310 if (exp
.X_op
!= O_constant
)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo
.defined
|= NTA_HASINDEX
;
2317 typeinfo
.index
= exp
.X_add_number
;
2319 if (skip_past_char (&p
, ']') == FAIL
)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen
= nameend
- newname
;
2332 newname
= original_case_string
;
2333 namelen
= strlen (newname
);
2336 namebuf
= (char *) alloca (namelen
+ 1);
2337 strncpy (namebuf
, newname
, namelen
);
2338 namebuf
[namelen
] = '\0';
2340 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2341 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2343 /* Insert name in all uppercase. */
2344 for (p
= namebuf
; *p
; p
++)
2347 if (strncmp (namebuf
, newname
, namelen
))
2348 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2349 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2351 /* Insert name in all lowercase. */
2352 for (p
= namebuf
; *p
; p
++)
2355 if (strncmp (namebuf
, newname
, namelen
))
2356 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2357 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED
)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED
)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED
)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED
)
2395 name
= input_line_pointer
;
2397 while (*input_line_pointer
!= 0
2398 && *input_line_pointer
!= ' '
2399 && *input_line_pointer
!= '\n')
2400 ++input_line_pointer
;
2402 saved_char
= *input_line_pointer
;
2403 *input_line_pointer
= 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2413 as_bad (_("unknown register alias '%s'"), name
);
2414 else if (reg
->builtin
)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh
, name
, FALSE
);
2423 free ((char *) reg
->name
);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf
= strdup (name
);
2433 for (p
= nbuf
; *p
; p
++)
2435 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2438 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2439 free ((char *) reg
->name
);
2445 for (p
= nbuf
; *p
; p
++)
2447 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2450 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2451 free ((char *) reg
->name
);
2461 *input_line_pointer
= saved_char
;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2479 const char * symname
;
2486 type
= BSF_NO_FLAGS
;
2490 type
= BSF_NO_FLAGS
;
2494 type
= BSF_NO_FLAGS
;
2500 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2501 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2506 THUMB_SET_FUNC (symbolP
, 0);
2507 ARM_SET_THUMB (symbolP
, 0);
2508 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2512 THUMB_SET_FUNC (symbolP
, 1);
2513 ARM_SET_THUMB (symbolP
, 1);
2514 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag
->tc_frag_data
.first_map
!= NULL
)
2535 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2536 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2538 frag
->tc_frag_data
.first_map
= symbolP
;
2540 if (frag
->tc_frag_data
.last_map
!= NULL
)
2542 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2543 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2544 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2546 frag
->tc_frag_data
.last_map
= symbolP
;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state
,
2555 valueT value
, fragS
*frag
, offsetT bytes
)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag
->tc_frag_data
.last_map
!= NULL
2559 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2561 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2565 know (frag
->tc_frag_data
.first_map
== symp
);
2566 frag
->tc_frag_data
.first_map
= NULL
;
2568 frag
->tc_frag_data
.last_map
= NULL
;
2569 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2572 make_mapping_symbol (MAP_DATA
, value
, frag
);
2573 make_mapping_symbol (state
, value
+ bytes
, frag
);
2576 static void mapping_state_2 (enum mstate state
, int max_chars
);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state
)
2584 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate
== state
)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2592 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2593 /* This case will be evaluated later in the next else. */
2595 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2596 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2598 /* Only add the symbol if the offset is > 0:
2599 if we're at the first frag, check it's size > 0;
2600 if we're not at the first frag, then for sure
2601 the offset is > 0. */
2602 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2603 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2606 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2609 mapping_state_2 (state
, 0);
2613 /* Same as mapping_state, but MAX_CHARS bytes have already been
2614 allocated. Put the mapping symbol that far back. */
2617 mapping_state_2 (enum mstate state
, int max_chars
)
2619 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2621 if (!SEG_NORMAL (now_seg
))
2624 if (mapstate
== state
)
2625 /* The mapping symbol has already been emitted.
2626 There is nothing else to do. */
2629 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2630 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2633 #define mapping_state(x) ((void)0)
2634 #define mapping_state_2(x, y) ((void)0)
2637 /* Find the real, Thumb encoded start of a Thumb function. */
2641 find_real_start (symbolS
* symbolP
)
2644 const char * name
= S_GET_NAME (symbolP
);
2645 symbolS
* new_target
;
2647 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2648 #define STUB_NAME ".real_start_of"
2653 /* The compiler may generate BL instructions to local labels because
2654 it needs to perform a branch to a far away location. These labels
2655 do not have a corresponding ".real_start_of" label. We check
2656 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2657 the ".real_start_of" convention for nonlocal branches. */
2658 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2661 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2662 new_target
= symbol_find (real_start
);
2664 if (new_target
== NULL
)
2666 as_warn (_("Failed to find real start of function: %s\n"), name
);
2667 new_target
= symbolP
;
2675 opcode_select (int width
)
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2683 as_bad (_("selected processor does not support THUMB opcodes"));
2686 /* No need to force the alignment, since we will have been
2687 coming from ARM mode, which is word-aligned. */
2688 record_alignment (now_seg
, 1);
2695 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2696 as_bad (_("selected processor does not support ARM opcodes"));
2701 frag_align (2, 0, 0);
2703 record_alignment (now_seg
, 1);
2708 as_bad (_("invalid instruction size selected (%d)"), width
);
2713 s_arm (int ignore ATTRIBUTE_UNUSED
)
2716 demand_empty_rest_of_line ();
2720 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2723 demand_empty_rest_of_line ();
2727 s_code (int unused ATTRIBUTE_UNUSED
)
2731 temp
= get_absolute_expression ();
2736 opcode_select (temp
);
2740 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2745 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2747 /* If we are not already in thumb mode go into it, EVEN if
2748 the target processor does not support thumb instructions.
2749 This is used by gcc/config/arm/lib1funcs.asm for example
2750 to compile interworking support functions even if the
2751 target processor should not support interworking. */
2755 record_alignment (now_seg
, 1);
2758 demand_empty_rest_of_line ();
2762 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2766 /* The following label is the name/address of the start of a Thumb function.
2767 We need to know this for the interworking support. */
2768 label_is_thumb_function_name
= TRUE
;
2771 /* Perform a .set directive, but also mark the alias as
2772 being a thumb function. */
2775 s_thumb_set (int equiv
)
2777 /* XXX the following is a duplicate of the code for s_set() in read.c
2778 We cannot just call that code as we need to get at the symbol that
2785 /* Especial apologies for the random logic:
2786 This just grew, and could be parsed much more simply!
2788 name
= input_line_pointer
;
2789 delim
= get_symbol_end ();
2790 end_name
= input_line_pointer
;
2793 if (*input_line_pointer
!= ',')
2796 as_bad (_("expected comma after name \"%s\""), name
);
2798 ignore_rest_of_line ();
2802 input_line_pointer
++;
2805 if (name
[0] == '.' && name
[1] == '\0')
2807 /* XXX - this should not happen to .thumb_set. */
2811 if ((symbolP
= symbol_find (name
)) == NULL
2812 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2815 /* When doing symbol listings, play games with dummy fragments living
2816 outside the normal fragment chain to record the file and line info
2818 if (listing
& LISTING_SYMBOLS
)
2820 extern struct list_info_struct
* listing_tail
;
2821 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2823 memset (dummy_frag
, 0, sizeof (fragS
));
2824 dummy_frag
->fr_type
= rs_fill
;
2825 dummy_frag
->line
= listing_tail
;
2826 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2827 dummy_frag
->fr_symbol
= symbolP
;
2831 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2834 /* "set" symbols are local unless otherwise specified. */
2835 SF_SET_LOCAL (symbolP
);
2836 #endif /* OBJ_COFF */
2837 } /* Make a new symbol. */
2839 symbol_table_insert (symbolP
);
2844 && S_IS_DEFINED (symbolP
)
2845 && S_GET_SEGMENT (symbolP
) != reg_section
)
2846 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2848 pseudo_set (symbolP
);
2850 demand_empty_rest_of_line ();
2852 /* XXX Now we come to the Thumb specific bit of code. */
2854 THUMB_SET_FUNC (symbolP
, 1);
2855 ARM_SET_THUMB (symbolP
, 1);
2856 #if defined OBJ_ELF || defined OBJ_COFF
2857 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2861 /* Directives: Mode selection. */
2863 /* .syntax [unified|divided] - choose the new unified syntax
2864 (same for Arm and Thumb encoding, modulo slight differences in what
2865 can be represented) or the old divergent syntax for each mode. */
2867 s_syntax (int unused ATTRIBUTE_UNUSED
)
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2874 if (!strcasecmp (name
, "unified"))
2875 unified_syntax
= TRUE
;
2876 else if (!strcasecmp (name
, "divided"))
2877 unified_syntax
= FALSE
;
2880 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2883 *input_line_pointer
= delim
;
2884 demand_empty_rest_of_line ();
2887 /* Directives: sectioning and alignment. */
2889 /* Same as s_align_ptwo but align 0 => align 2. */
2892 s_align (int unused ATTRIBUTE_UNUSED
)
2897 long max_alignment
= 15;
2899 temp
= get_absolute_expression ();
2900 if (temp
> max_alignment
)
2901 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2904 as_bad (_("alignment negative. 0 assumed."));
2908 if (*input_line_pointer
== ',')
2910 input_line_pointer
++;
2911 temp_fill
= get_absolute_expression ();
2923 /* Only make a frag if we HAVE to. */
2924 if (temp
&& !need_pass_2
)
2926 if (!fill_p
&& subseg_text_p (now_seg
))
2927 frag_align_code (temp
, 0);
2929 frag_align (temp
, (int) temp_fill
, 0);
2931 demand_empty_rest_of_line ();
2933 record_alignment (now_seg
, temp
);
2937 s_bss (int ignore ATTRIBUTE_UNUSED
)
2939 /* We don't support putting frags in the BSS segment, we fake it by
2940 marking in_bss, then looking at s_skip for clues. */
2941 subseg_set (bss_section
, 0);
2942 demand_empty_rest_of_line ();
2944 #ifdef md_elf_section_change_hook
2945 md_elf_section_change_hook ();
2950 s_even (int ignore ATTRIBUTE_UNUSED
)
2952 /* Never make frag if expect extra pass. */
2954 frag_align (1, 0, 0);
2956 record_alignment (now_seg
, 1);
2958 demand_empty_rest_of_line ();
2961 /* Directives: Literal pools. */
2963 static literal_pool
*
2964 find_literal_pool (void)
2966 literal_pool
* pool
;
2968 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2970 if (pool
->section
== now_seg
2971 && pool
->sub_section
== now_subseg
)
2978 static literal_pool
*
2979 find_or_make_literal_pool (void)
2981 /* Next literal pool ID number. */
2982 static unsigned int latest_pool_num
= 1;
2983 literal_pool
* pool
;
2985 pool
= find_literal_pool ();
2989 /* Create a new pool. */
2990 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2994 pool
->next_free_entry
= 0;
2995 pool
->section
= now_seg
;
2996 pool
->sub_section
= now_subseg
;
2997 pool
->next
= list_of_pools
;
2998 pool
->symbol
= NULL
;
3000 /* Add it to the list. */
3001 list_of_pools
= pool
;
3004 /* New pools, and emptied pools, will have a NULL symbol. */
3005 if (pool
->symbol
== NULL
)
3007 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3008 (valueT
) 0, &zero_address_frag
);
3009 pool
->id
= latest_pool_num
++;
3016 /* Add the literal in the global 'inst'
3017 structure to the relevant literal pool. */
3020 add_to_lit_pool (void)
3022 literal_pool
* pool
;
3025 pool
= find_or_make_literal_pool ();
3027 /* Check if this literal value is already in the pool. */
3028 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3030 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3031 && (inst
.reloc
.exp
.X_op
== O_constant
)
3032 && (pool
->literals
[entry
].X_add_number
3033 == inst
.reloc
.exp
.X_add_number
)
3034 && (pool
->literals
[entry
].X_unsigned
3035 == inst
.reloc
.exp
.X_unsigned
))
3038 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3039 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3040 && (pool
->literals
[entry
].X_add_number
3041 == inst
.reloc
.exp
.X_add_number
)
3042 && (pool
->literals
[entry
].X_add_symbol
3043 == inst
.reloc
.exp
.X_add_symbol
)
3044 && (pool
->literals
[entry
].X_op_symbol
3045 == inst
.reloc
.exp
.X_op_symbol
))
3049 /* Do we need to create a new entry? */
3050 if (entry
== pool
->next_free_entry
)
3052 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3054 inst
.error
= _("literal pool overflow");
3058 pool
->literals
[entry
] = inst
.reloc
.exp
;
3059 pool
->next_free_entry
+= 1;
3062 inst
.reloc
.exp
.X_op
= O_symbol
;
3063 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3064 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3069 /* Can't use symbol_new here, so have to create a symbol and then at
3070 a later date assign it a value. Thats what these functions do. */
3073 symbol_locate (symbolS
* symbolP
,
3074 const char * name
, /* It is copied, the caller can modify. */
3075 segT segment
, /* Segment identifier (SEG_<something>). */
3076 valueT valu
, /* Symbol value. */
3077 fragS
* frag
) /* Associated fragment. */
3079 unsigned int name_length
;
3080 char * preserved_copy_of_name
;
3082 name_length
= strlen (name
) + 1; /* +1 for \0. */
3083 obstack_grow (¬es
, name
, name_length
);
3084 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3086 #ifdef tc_canonicalize_symbol_name
3087 preserved_copy_of_name
=
3088 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3091 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3093 S_SET_SEGMENT (symbolP
, segment
);
3094 S_SET_VALUE (symbolP
, valu
);
3095 symbol_clear_list_pointers (symbolP
);
3097 symbol_set_frag (symbolP
, frag
);
3099 /* Link to end of symbol chain. */
3101 extern int symbol_table_frozen
;
3103 if (symbol_table_frozen
)
3107 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3109 obj_symbol_new_hook (symbolP
);
3111 #ifdef tc_symbol_new_hook
3112 tc_symbol_new_hook (symbolP
);
3116 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3117 #endif /* DEBUG_SYMS */
3122 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3125 literal_pool
* pool
;
3128 pool
= find_literal_pool ();
3130 || pool
->symbol
== NULL
3131 || pool
->next_free_entry
== 0)
3134 mapping_state (MAP_DATA
);
3136 /* Align pool as you have word accesses.
3137 Only make a frag if we have to. */
3139 frag_align (2, 0, 0);
3141 record_alignment (now_seg
, 2);
3143 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3145 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3146 (valueT
) frag_now_fix (), frag_now
);
3147 symbol_table_insert (pool
->symbol
);
3149 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3151 #if defined OBJ_COFF || defined OBJ_ELF
3152 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3155 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3156 /* First output the expression in the instruction to the pool. */
3157 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3159 /* Mark the pool as empty. */
3160 pool
->next_free_entry
= 0;
3161 pool
->symbol
= NULL
;
3165 /* Forward declarations for functions below, in the MD interface
3167 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3168 static valueT
create_unwind_entry (int);
3169 static void start_unwind_section (const segT
, int);
3170 static void add_unwind_opcode (valueT
, int);
3171 static void flush_pending_unwind (void);
3173 /* Directives: Data. */
3176 s_arm_elf_cons (int nbytes
)
3180 #ifdef md_flush_pending_output
3181 md_flush_pending_output ();
3184 if (is_it_end_of_statement ())
3186 demand_empty_rest_of_line ();
3190 #ifdef md_cons_align
3191 md_cons_align (nbytes
);
3194 mapping_state (MAP_DATA
);
3198 char *base
= input_line_pointer
;
3202 if (exp
.X_op
!= O_symbol
)
3203 emit_expr (&exp
, (unsigned int) nbytes
);
3206 char *before_reloc
= input_line_pointer
;
3207 reloc
= parse_reloc (&input_line_pointer
);
3210 as_bad (_("unrecognized relocation suffix"));
3211 ignore_rest_of_line ();
3214 else if (reloc
== BFD_RELOC_UNUSED
)
3215 emit_expr (&exp
, (unsigned int) nbytes
);
3218 reloc_howto_type
*howto
= (reloc_howto_type
*)
3219 bfd_reloc_type_lookup (stdoutput
,
3220 (bfd_reloc_code_real_type
) reloc
);
3221 int size
= bfd_get_reloc_size (howto
);
3223 if (reloc
== BFD_RELOC_ARM_PLT32
)
3225 as_bad (_("(plt) is only valid on branch targets"));
3226 reloc
= BFD_RELOC_UNUSED
;
3231 as_bad (_("%s relocations do not fit in %d bytes"),
3232 howto
->name
, nbytes
);
3235 /* We've parsed an expression stopping at O_symbol.
3236 But there may be more expression left now that we
3237 have parsed the relocation marker. Parse it again.
3238 XXX Surely there is a cleaner way to do this. */
3239 char *p
= input_line_pointer
;
3241 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3242 memcpy (save_buf
, base
, input_line_pointer
- base
);
3243 memmove (base
+ (input_line_pointer
- before_reloc
),
3244 base
, before_reloc
- base
);
3246 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3248 memcpy (base
, save_buf
, p
- base
);
3250 offset
= nbytes
- size
;
3251 p
= frag_more ((int) nbytes
);
3252 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3253 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3258 while (*input_line_pointer
++ == ',');
3260 /* Put terminator back into stream. */
3261 input_line_pointer
--;
3262 demand_empty_rest_of_line ();
3265 /* Emit an expression containing a 32-bit thumb instruction.
3266 Implementation based on put_thumb32_insn. */
3269 emit_thumb32_expr (expressionS
* exp
)
3271 expressionS exp_high
= *exp
;
3273 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3274 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3275 exp
->X_add_number
&= 0xffff;
3276 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3279 /* Guess the instruction size based on the opcode. */
3282 thumb_insn_size (int opcode
)
3284 if ((unsigned int) opcode
< 0xe800u
)
3286 else if ((unsigned int) opcode
>= 0xe8000000u
)
3293 emit_insn (expressionS
*exp
, int nbytes
)
3297 if (exp
->X_op
== O_constant
)
3302 size
= thumb_insn_size (exp
->X_add_number
);
3306 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3308 as_bad (_(".inst.n operand too big. "\
3309 "Use .inst.w instead"));
3314 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3315 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3317 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3319 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3320 emit_thumb32_expr (exp
);
3322 emit_expr (exp
, (unsigned int) size
);
3324 it_fsm_post_encode ();
3328 as_bad (_("cannot determine Thumb instruction size. " \
3329 "Use .inst.n/.inst.w instead"));
3332 as_bad (_("constant expression required"));
3337 /* Like s_arm_elf_cons but do not use md_cons_align and
3338 set the mapping state to MAP_ARM/MAP_THUMB. */
3341 s_arm_elf_inst (int nbytes
)
3343 if (is_it_end_of_statement ())
3345 demand_empty_rest_of_line ();
3349 /* Calling mapping_state () here will not change ARM/THUMB,
3350 but will ensure not to be in DATA state. */
3353 mapping_state (MAP_THUMB
);
3358 as_bad (_("width suffixes are invalid in ARM mode"));
3359 ignore_rest_of_line ();
3365 mapping_state (MAP_ARM
);
3374 if (! emit_insn (& exp
, nbytes
))
3376 ignore_rest_of_line ();
3380 while (*input_line_pointer
++ == ',');
3382 /* Put terminator back into stream. */
3383 input_line_pointer
--;
3384 demand_empty_rest_of_line ();
3387 /* Parse a .rel31 directive. */
3390 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3397 if (*input_line_pointer
== '1')
3398 highbit
= 0x80000000;
3399 else if (*input_line_pointer
!= '0')
3400 as_bad (_("expected 0 or 1"));
3402 input_line_pointer
++;
3403 if (*input_line_pointer
!= ',')
3404 as_bad (_("missing comma"));
3405 input_line_pointer
++;
3407 #ifdef md_flush_pending_output
3408 md_flush_pending_output ();
3411 #ifdef md_cons_align
3415 mapping_state (MAP_DATA
);
3420 md_number_to_chars (p
, highbit
, 4);
3421 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3422 BFD_RELOC_ARM_PREL31
);
3424 demand_empty_rest_of_line ();
3427 /* Directives: AEABI stack-unwind tables. */
3429 /* Parse an unwind_fnstart directive. Simply records the current location. */
3432 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (unwind
.proc_start
)
3437 as_bad (_("duplicate .fnstart directive"));
3441 /* Mark the start of the function. */
3442 unwind
.proc_start
= expr_build_dot ();
3444 /* Reset the rest of the unwind info. */
3445 unwind
.opcode_count
= 0;
3446 unwind
.table_entry
= NULL
;
3447 unwind
.personality_routine
= NULL
;
3448 unwind
.personality_index
= -1;
3449 unwind
.frame_size
= 0;
3450 unwind
.fp_offset
= 0;
3451 unwind
.fp_reg
= REG_SP
;
3453 unwind
.sp_restored
= 0;
3457 /* Parse a handlerdata directive. Creates the exception handling table entry
3458 for the function. */
3461 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3463 demand_empty_rest_of_line ();
3464 if (!unwind
.proc_start
)
3465 as_bad (MISSING_FNSTART
);
3467 if (unwind
.table_entry
)
3468 as_bad (_("duplicate .handlerdata directive"));
3470 create_unwind_entry (1);
3473 /* Parse an unwind_fnend directive. Generates the index table entry. */
3476 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3481 unsigned int marked_pr_dependency
;
3483 demand_empty_rest_of_line ();
3485 if (!unwind
.proc_start
)
3487 as_bad (_(".fnend directive without .fnstart"));
3491 /* Add eh table entry. */
3492 if (unwind
.table_entry
== NULL
)
3493 val
= create_unwind_entry (0);
3497 /* Add index table entry. This is two words. */
3498 start_unwind_section (unwind
.saved_seg
, 1);
3499 frag_align (2, 0, 0);
3500 record_alignment (now_seg
, 2);
3502 ptr
= frag_more (8);
3503 where
= frag_now_fix () - 8;
3505 /* Self relative offset of the function start. */
3506 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3507 BFD_RELOC_ARM_PREL31
);
3509 /* Indicate dependency on EHABI-defined personality routines to the
3510 linker, if it hasn't been done already. */
3511 marked_pr_dependency
3512 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3513 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3514 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3516 static const char *const name
[] =
3518 "__aeabi_unwind_cpp_pr0",
3519 "__aeabi_unwind_cpp_pr1",
3520 "__aeabi_unwind_cpp_pr2"
3522 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3523 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3524 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3525 |= 1 << unwind
.personality_index
;
3529 /* Inline exception table entry. */
3530 md_number_to_chars (ptr
+ 4, val
, 4);
3532 /* Self relative offset of the table entry. */
3533 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3534 BFD_RELOC_ARM_PREL31
);
3536 /* Restore the original section. */
3537 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3539 unwind
.proc_start
= NULL
;
3543 /* Parse an unwind_cantunwind directive. */
3546 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3548 demand_empty_rest_of_line ();
3549 if (!unwind
.proc_start
)
3550 as_bad (MISSING_FNSTART
);
3552 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3553 as_bad (_("personality routine specified for cantunwind frame"));
3555 unwind
.personality_index
= -2;
3559 /* Parse a personalityindex directive. */
3562 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personalityindex directive"));
3574 if (exp
.X_op
!= O_constant
3575 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3577 as_bad (_("bad personality routine number"));
3578 ignore_rest_of_line ();
3582 unwind
.personality_index
= exp
.X_add_number
;
3584 demand_empty_rest_of_line ();
3588 /* Parse a personality directive. */
3591 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3595 if (!unwind
.proc_start
)
3596 as_bad (MISSING_FNSTART
);
3598 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3599 as_bad (_("duplicate .personality directive"));
3601 name
= input_line_pointer
;
3602 c
= get_symbol_end ();
3603 p
= input_line_pointer
;
3604 unwind
.personality_routine
= symbol_find_or_make (name
);
3606 demand_empty_rest_of_line ();
3610 /* Parse a directive saving core registers. */
3613 s_arm_unwind_save_core (void)
3619 range
= parse_reg_list (&input_line_pointer
);
3622 as_bad (_("expected register list"));
3623 ignore_rest_of_line ();
3627 demand_empty_rest_of_line ();
3629 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3630 into .unwind_save {..., sp...}. We aren't bothered about the value of
3631 ip because it is clobbered by calls. */
3632 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3633 && (range
& 0x3000) == 0x1000)
3635 unwind
.opcode_count
--;
3636 unwind
.sp_restored
= 0;
3637 range
= (range
| 0x2000) & ~0x1000;
3638 unwind
.pending_offset
= 0;
3644 /* See if we can use the short opcodes. These pop a block of up to 8
3645 registers starting with r4, plus maybe r14. */
3646 for (n
= 0; n
< 8; n
++)
3648 /* Break at the first non-saved register. */
3649 if ((range
& (1 << (n
+ 4))) == 0)
3652 /* See if there are any other bits set. */
3653 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3655 /* Use the long form. */
3656 op
= 0x8000 | ((range
>> 4) & 0xfff);
3657 add_unwind_opcode (op
, 2);
3661 /* Use the short form. */
3663 op
= 0xa8; /* Pop r14. */
3665 op
= 0xa0; /* Do not pop r14. */
3667 add_unwind_opcode (op
, 1);
3674 op
= 0xb100 | (range
& 0xf);
3675 add_unwind_opcode (op
, 2);
3678 /* Record the number of bytes pushed. */
3679 for (n
= 0; n
< 16; n
++)
3681 if (range
& (1 << n
))
3682 unwind
.frame_size
+= 4;
3687 /* Parse a directive saving FPA registers. */
3690 s_arm_unwind_save_fpa (int reg
)
3696 /* Get Number of registers to transfer. */
3697 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3700 exp
.X_op
= O_illegal
;
3702 if (exp
.X_op
!= O_constant
)
3704 as_bad (_("expected , <constant>"));
3705 ignore_rest_of_line ();
3709 num_regs
= exp
.X_add_number
;
3711 if (num_regs
< 1 || num_regs
> 4)
3713 as_bad (_("number of registers must be in the range [1:4]"));
3714 ignore_rest_of_line ();
3718 demand_empty_rest_of_line ();
3723 op
= 0xb4 | (num_regs
- 1);
3724 add_unwind_opcode (op
, 1);
3729 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3730 add_unwind_opcode (op
, 2);
3732 unwind
.frame_size
+= num_regs
* 12;
3736 /* Parse a directive saving VFP registers for ARMv6 and above. */
3739 s_arm_unwind_save_vfp_armv6 (void)
3744 int num_vfpv3_regs
= 0;
3745 int num_regs_below_16
;
3747 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3757 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3758 than FSTMX/FLDMX-style ones). */
3760 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3762 num_vfpv3_regs
= count
;
3763 else if (start
+ count
> 16)
3764 num_vfpv3_regs
= start
+ count
- 16;
3766 if (num_vfpv3_regs
> 0)
3768 int start_offset
= start
> 16 ? start
- 16 : 0;
3769 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3770 add_unwind_opcode (op
, 2);
3773 /* Generate opcode for registers numbered in the range 0 .. 15. */
3774 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3775 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3776 if (num_regs_below_16
> 0)
3778 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3779 add_unwind_opcode (op
, 2);
3782 unwind
.frame_size
+= count
* 8;
3786 /* Parse a directive saving VFP registers for pre-ARMv6. */
3789 s_arm_unwind_save_vfp (void)
3795 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3798 as_bad (_("expected register list"));
3799 ignore_rest_of_line ();
3803 demand_empty_rest_of_line ();
3808 op
= 0xb8 | (count
- 1);
3809 add_unwind_opcode (op
, 1);
3814 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3815 add_unwind_opcode (op
, 2);
3817 unwind
.frame_size
+= count
* 8 + 4;
3821 /* Parse a directive saving iWMMXt data registers. */
3824 s_arm_unwind_save_mmxwr (void)
3832 if (*input_line_pointer
== '{')
3833 input_line_pointer
++;
3837 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3841 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3846 as_tsktsk (_("register list not in ascending order"));
3849 if (*input_line_pointer
== '-')
3851 input_line_pointer
++;
3852 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3855 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3858 else if (reg
>= hi_reg
)
3860 as_bad (_("bad register range"));
3863 for (; reg
< hi_reg
; reg
++)
3867 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3869 if (*input_line_pointer
== '}')
3870 input_line_pointer
++;
3872 demand_empty_rest_of_line ();
3874 /* Generate any deferred opcodes because we're going to be looking at
3876 flush_pending_unwind ();
3878 for (i
= 0; i
< 16; i
++)
3880 if (mask
& (1 << i
))
3881 unwind
.frame_size
+= 8;
3884 /* Attempt to combine with a previous opcode. We do this because gcc
3885 likes to output separate unwind directives for a single block of
3887 if (unwind
.opcode_count
> 0)
3889 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3890 if ((i
& 0xf8) == 0xc0)
3893 /* Only merge if the blocks are contiguous. */
3896 if ((mask
& 0xfe00) == (1 << 9))
3898 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3899 unwind
.opcode_count
--;
3902 else if (i
== 6 && unwind
.opcode_count
>= 2)
3904 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3908 op
= 0xffff << (reg
- 1);
3910 && ((mask
& op
) == (1u << (reg
- 1))))
3912 op
= (1 << (reg
+ i
+ 1)) - 1;
3913 op
&= ~((1 << reg
) - 1);
3915 unwind
.opcode_count
-= 2;
3922 /* We want to generate opcodes in the order the registers have been
3923 saved, ie. descending order. */
3924 for (reg
= 15; reg
>= -1; reg
--)
3926 /* Save registers in blocks. */
3928 || !(mask
& (1 << reg
)))
3930 /* We found an unsaved reg. Generate opcodes to save the
3937 op
= 0xc0 | (hi_reg
- 10);
3938 add_unwind_opcode (op
, 1);
3943 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3944 add_unwind_opcode (op
, 2);
3953 ignore_rest_of_line ();
3957 s_arm_unwind_save_mmxwcg (void)
3964 if (*input_line_pointer
== '{')
3965 input_line_pointer
++;
3969 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3973 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3979 as_tsktsk (_("register list not in ascending order"));
3982 if (*input_line_pointer
== '-')
3984 input_line_pointer
++;
3985 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3988 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3991 else if (reg
>= hi_reg
)
3993 as_bad (_("bad register range"));
3996 for (; reg
< hi_reg
; reg
++)
4000 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4002 if (*input_line_pointer
== '}')
4003 input_line_pointer
++;
4005 demand_empty_rest_of_line ();
4007 /* Generate any deferred opcodes because we're going to be looking at
4009 flush_pending_unwind ();
4011 for (reg
= 0; reg
< 16; reg
++)
4013 if (mask
& (1 << reg
))
4014 unwind
.frame_size
+= 4;
4017 add_unwind_opcode (op
, 2);
4020 ignore_rest_of_line ();
4024 /* Parse an unwind_save directive.
4025 If the argument is non-zero, this is a .vsave directive. */
4028 s_arm_unwind_save (int arch_v6
)
4031 struct reg_entry
*reg
;
4032 bfd_boolean had_brace
= FALSE
;
4034 if (!unwind
.proc_start
)
4035 as_bad (MISSING_FNSTART
);
4037 /* Figure out what sort of save we have. */
4038 peek
= input_line_pointer
;
4046 reg
= arm_reg_parse_multi (&peek
);
4050 as_bad (_("register expected"));
4051 ignore_rest_of_line ();
4060 as_bad (_("FPA .unwind_save does not take a register list"));
4061 ignore_rest_of_line ();
4064 input_line_pointer
= peek
;
4065 s_arm_unwind_save_fpa (reg
->number
);
4068 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4071 s_arm_unwind_save_vfp_armv6 ();
4073 s_arm_unwind_save_vfp ();
4075 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4076 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4079 as_bad (_(".unwind_save does not support this kind of register"));
4080 ignore_rest_of_line ();
4085 /* Parse an unwind_movsp directive. */
4088 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4094 if (!unwind
.proc_start
)
4095 as_bad (MISSING_FNSTART
);
4097 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4100 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4101 ignore_rest_of_line ();
4105 /* Optional constant. */
4106 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4108 if (immediate_for_directive (&offset
) == FAIL
)
4114 demand_empty_rest_of_line ();
4116 if (reg
== REG_SP
|| reg
== REG_PC
)
4118 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4122 if (unwind
.fp_reg
!= REG_SP
)
4123 as_bad (_("unexpected .unwind_movsp directive"));
4125 /* Generate opcode to restore the value. */
4127 add_unwind_opcode (op
, 1);
4129 /* Record the information for later. */
4130 unwind
.fp_reg
= reg
;
4131 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4132 unwind
.sp_restored
= 1;
4135 /* Parse an unwind_pad directive. */
4138 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 if (immediate_for_directive (&offset
) == FAIL
)
4150 as_bad (_("stack increment must be multiple of 4"));
4151 ignore_rest_of_line ();
4155 /* Don't generate any opcodes, just record the details for later. */
4156 unwind
.frame_size
+= offset
;
4157 unwind
.pending_offset
+= offset
;
4159 demand_empty_rest_of_line ();
4162 /* Parse an unwind_setfp directive. */
4165 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4171 if (!unwind
.proc_start
)
4172 as_bad (MISSING_FNSTART
);
4174 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4175 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4178 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4180 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4182 as_bad (_("expected <reg>, <reg>"));
4183 ignore_rest_of_line ();
4187 /* Optional constant. */
4188 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4190 if (immediate_for_directive (&offset
) == FAIL
)
4196 demand_empty_rest_of_line ();
4198 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4200 as_bad (_("register must be either sp or set by a previous"
4201 "unwind_movsp directive"));
4205 /* Don't generate any opcodes, just record the information for later. */
4206 unwind
.fp_reg
= fp_reg
;
4208 if (sp_reg
== REG_SP
)
4209 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4211 unwind
.fp_offset
-= offset
;
4214 /* Parse an unwind_raw directive. */
4217 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4220 /* This is an arbitrary limit. */
4221 unsigned char op
[16];
4224 if (!unwind
.proc_start
)
4225 as_bad (MISSING_FNSTART
);
4228 if (exp
.X_op
== O_constant
4229 && skip_past_comma (&input_line_pointer
) != FAIL
)
4231 unwind
.frame_size
+= exp
.X_add_number
;
4235 exp
.X_op
= O_illegal
;
4237 if (exp
.X_op
!= O_constant
)
4239 as_bad (_("expected <offset>, <opcode>"));
4240 ignore_rest_of_line ();
4246 /* Parse the opcode. */
4251 as_bad (_("unwind opcode too long"));
4252 ignore_rest_of_line ();
4254 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4256 as_bad (_("invalid unwind opcode"));
4257 ignore_rest_of_line ();
4260 op
[count
++] = exp
.X_add_number
;
4262 /* Parse the next byte. */
4263 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4269 /* Add the opcode bytes in reverse order. */
4271 add_unwind_opcode (op
[count
], 1);
4273 demand_empty_rest_of_line ();
4277 /* Parse a .eabi_attribute directive. */
4280 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4282 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4284 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4285 attributes_set_explicitly
[tag
] = 1;
4288 /* Emit a tls fix for the symbol. */
4291 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4295 #ifdef md_flush_pending_output
4296 md_flush_pending_output ();
4299 #ifdef md_cons_align
4303 /* Since we're just labelling the code, there's no need to define a
4306 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4307 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4308 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4309 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4311 #endif /* OBJ_ELF */
4313 static void s_arm_arch (int);
4314 static void s_arm_object_arch (int);
4315 static void s_arm_cpu (int);
4316 static void s_arm_fpu (int);
4317 static void s_arm_arch_extension (int);
4322 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4329 if (exp
.X_op
== O_symbol
)
4330 exp
.X_op
= O_secrel
;
4332 emit_expr (&exp
, 4);
4334 while (*input_line_pointer
++ == ',');
4336 input_line_pointer
--;
4337 demand_empty_rest_of_line ();
4341 /* This table describes all the machine specific pseudo-ops the assembler
4342 has to support. The fields are:
4343 pseudo-op name without dot
4344 function to call to execute this pseudo-op
4345 Integer arg to pass to the function. */
4347 const pseudo_typeS md_pseudo_table
[] =
4349 /* Never called because '.req' does not start a line. */
4350 { "req", s_req
, 0 },
4351 /* Following two are likewise never called. */
4354 { "unreq", s_unreq
, 0 },
4355 { "bss", s_bss
, 0 },
4356 { "align", s_align
, 0 },
4357 { "arm", s_arm
, 0 },
4358 { "thumb", s_thumb
, 0 },
4359 { "code", s_code
, 0 },
4360 { "force_thumb", s_force_thumb
, 0 },
4361 { "thumb_func", s_thumb_func
, 0 },
4362 { "thumb_set", s_thumb_set
, 0 },
4363 { "even", s_even
, 0 },
4364 { "ltorg", s_ltorg
, 0 },
4365 { "pool", s_ltorg
, 0 },
4366 { "syntax", s_syntax
, 0 },
4367 { "cpu", s_arm_cpu
, 0 },
4368 { "arch", s_arm_arch
, 0 },
4369 { "object_arch", s_arm_object_arch
, 0 },
4370 { "fpu", s_arm_fpu
, 0 },
4371 { "arch_extension", s_arm_arch_extension
, 0 },
4373 { "word", s_arm_elf_cons
, 4 },
4374 { "long", s_arm_elf_cons
, 4 },
4375 { "inst.n", s_arm_elf_inst
, 2 },
4376 { "inst.w", s_arm_elf_inst
, 4 },
4377 { "inst", s_arm_elf_inst
, 0 },
4378 { "rel31", s_arm_rel31
, 0 },
4379 { "fnstart", s_arm_unwind_fnstart
, 0 },
4380 { "fnend", s_arm_unwind_fnend
, 0 },
4381 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4382 { "personality", s_arm_unwind_personality
, 0 },
4383 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4384 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4385 { "save", s_arm_unwind_save
, 0 },
4386 { "vsave", s_arm_unwind_save
, 1 },
4387 { "movsp", s_arm_unwind_movsp
, 0 },
4388 { "pad", s_arm_unwind_pad
, 0 },
4389 { "setfp", s_arm_unwind_setfp
, 0 },
4390 { "unwind_raw", s_arm_unwind_raw
, 0 },
4391 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4392 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4396 /* These are used for dwarf. */
4400 /* These are used for dwarf2. */
4401 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4402 { "loc", dwarf2_directive_loc
, 0 },
4403 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4405 { "extend", float_cons
, 'x' },
4406 { "ldouble", float_cons
, 'x' },
4407 { "packed", float_cons
, 'p' },
4409 {"secrel32", pe_directive_secrel
, 0},
4414 /* Parser functions used exclusively in instruction operands. */
4416 /* Generic immediate-value read function for use in insn parsing.
4417 STR points to the beginning of the immediate (the leading #);
4418 VAL receives the value; if the value is outside [MIN, MAX]
4419 issue an error. PREFIX_OPT is true if the immediate prefix is
4423 parse_immediate (char **str
, int *val
, int min
, int max
,
4424 bfd_boolean prefix_opt
)
4427 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4428 if (exp
.X_op
!= O_constant
)
4430 inst
.error
= _("constant expression required");
4434 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4436 inst
.error
= _("immediate value out of range");
4440 *val
= exp
.X_add_number
;
4444 /* Less-generic immediate-value read function with the possibility of loading a
4445 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4446 instructions. Puts the result directly in inst.operands[i]. */
4449 parse_big_immediate (char **str
, int i
)
4454 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4456 if (exp
.X_op
== O_constant
)
4458 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4459 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4460 O_constant. We have to be careful not to break compilation for
4461 32-bit X_add_number, though. */
4462 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4464 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4465 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4466 inst
.operands
[i
].regisimm
= 1;
4469 else if (exp
.X_op
== O_big
4470 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4472 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4474 /* Bignums have their least significant bits in
4475 generic_bignum[0]. Make sure we put 32 bits in imm and
4476 32 bits in reg, in a (hopefully) portable way. */
4477 gas_assert (parts
!= 0);
4479 /* Make sure that the number is not too big.
4480 PR 11972: Bignums can now be sign-extended to the
4481 size of a .octa so check that the out of range bits
4482 are all zero or all one. */
4483 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4485 LITTLENUM_TYPE m
= -1;
4487 if (generic_bignum
[parts
* 2] != 0
4488 && generic_bignum
[parts
* 2] != m
)
4491 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4492 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4496 inst
.operands
[i
].imm
= 0;
4497 for (j
= 0; j
< parts
; j
++, idx
++)
4498 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4499 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4500 inst
.operands
[i
].reg
= 0;
4501 for (j
= 0; j
< parts
; j
++, idx
++)
4502 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4503 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4504 inst
.operands
[i
].regisimm
= 1;
4514 /* Returns the pseudo-register number of an FPA immediate constant,
4515 or FAIL if there isn't a valid constant here. */
4518 parse_fpa_immediate (char ** str
)
4520 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4526 /* First try and match exact strings, this is to guarantee
4527 that some formats will work even for cross assembly. */
4529 for (i
= 0; fp_const
[i
]; i
++)
4531 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4535 *str
+= strlen (fp_const
[i
]);
4536 if (is_end_of_line
[(unsigned char) **str
])
4542 /* Just because we didn't get a match doesn't mean that the constant
4543 isn't valid, just that it is in a format that we don't
4544 automatically recognize. Try parsing it with the standard
4545 expression routines. */
4547 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4549 /* Look for a raw floating point number. */
4550 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4551 && is_end_of_line
[(unsigned char) *save_in
])
4553 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4555 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4557 if (words
[j
] != fp_values
[i
][j
])
4561 if (j
== MAX_LITTLENUMS
)
4569 /* Try and parse a more complex expression, this will probably fail
4570 unless the code uses a floating point prefix (eg "0f"). */
4571 save_in
= input_line_pointer
;
4572 input_line_pointer
= *str
;
4573 if (expression (&exp
) == absolute_section
4574 && exp
.X_op
== O_big
4575 && exp
.X_add_number
< 0)
4577 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4579 if (gen_to_words (words
, 5, (long) 15) == 0)
4581 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4583 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4585 if (words
[j
] != fp_values
[i
][j
])
4589 if (j
== MAX_LITTLENUMS
)
4591 *str
= input_line_pointer
;
4592 input_line_pointer
= save_in
;
4599 *str
= input_line_pointer
;
4600 input_line_pointer
= save_in
;
4601 inst
.error
= _("invalid FPA immediate expression");
4605 /* Returns 1 if a number has "quarter-precision" float format
4606 0baBbbbbbc defgh000 00000000 00000000. */
4609 is_quarter_float (unsigned imm
)
4611 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4612 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4615 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4616 0baBbbbbbc defgh000 00000000 00000000.
4617 The zero and minus-zero cases need special handling, since they can't be
4618 encoded in the "quarter-precision" float format, but can nonetheless be
4619 loaded as integer constants. */
4622 parse_qfloat_immediate (char **ccp
, int *immed
)
4626 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4627 int found_fpchar
= 0;
4629 skip_past_char (&str
, '#');
4631 /* We must not accidentally parse an integer as a floating-point number. Make
4632 sure that the value we parse is not an integer by checking for special
4633 characters '.' or 'e'.
4634 FIXME: This is a horrible hack, but doing better is tricky because type
4635 information isn't in a very usable state at parse time. */
4637 skip_whitespace (fpnum
);
4639 if (strncmp (fpnum
, "0x", 2) == 0)
4643 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4644 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4654 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4656 unsigned fpword
= 0;
4659 /* Our FP word must be 32 bits (single-precision FP). */
4660 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4662 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4666 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4679 /* Shift operands. */
4682 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4685 struct asm_shift_name
4688 enum shift_kind kind
;
4691 /* Third argument to parse_shift. */
4692 enum parse_shift_mode
4694 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4695 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4696 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4697 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4698 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4701 /* Parse a <shift> specifier on an ARM data processing instruction.
4702 This has three forms:
4704 (LSL|LSR|ASL|ASR|ROR) Rs
4705 (LSL|LSR|ASL|ASR|ROR) #imm
4708 Note that ASL is assimilated to LSL in the instruction encoding, and
4709 RRX to ROR #0 (which cannot be written as such). */
4712 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4714 const struct asm_shift_name
*shift_name
;
4715 enum shift_kind shift
;
4720 for (p
= *str
; ISALPHA (*p
); p
++)
4725 inst
.error
= _("shift expression expected");
4729 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4732 if (shift_name
== NULL
)
4734 inst
.error
= _("shift expression expected");
4738 shift
= shift_name
->kind
;
4742 case NO_SHIFT_RESTRICT
:
4743 case SHIFT_IMMEDIATE
: break;
4745 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4746 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4748 inst
.error
= _("'LSL' or 'ASR' required");
4753 case SHIFT_LSL_IMMEDIATE
:
4754 if (shift
!= SHIFT_LSL
)
4756 inst
.error
= _("'LSL' required");
4761 case SHIFT_ASR_IMMEDIATE
:
4762 if (shift
!= SHIFT_ASR
)
4764 inst
.error
= _("'ASR' required");
4772 if (shift
!= SHIFT_RRX
)
4774 /* Whitespace can appear here if the next thing is a bare digit. */
4775 skip_whitespace (p
);
4777 if (mode
== NO_SHIFT_RESTRICT
4778 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4780 inst
.operands
[i
].imm
= reg
;
4781 inst
.operands
[i
].immisreg
= 1;
4783 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4786 inst
.operands
[i
].shift_kind
= shift
;
4787 inst
.operands
[i
].shifted
= 1;
4792 /* Parse a <shifter_operand> for an ARM data processing instruction:
4795 #<immediate>, <rotate>
4799 where <shift> is defined by parse_shift above, and <rotate> is a
4800 multiple of 2 between 0 and 30. Validation of immediate operands
4801 is deferred to md_apply_fix. */
4804 parse_shifter_operand (char **str
, int i
)
4809 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4811 inst
.operands
[i
].reg
= value
;
4812 inst
.operands
[i
].isreg
= 1;
4814 /* parse_shift will override this if appropriate */
4815 inst
.reloc
.exp
.X_op
= O_constant
;
4816 inst
.reloc
.exp
.X_add_number
= 0;
4818 if (skip_past_comma (str
) == FAIL
)
4821 /* Shift operation on register. */
4822 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4825 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4828 if (skip_past_comma (str
) == SUCCESS
)
4830 /* #x, y -- ie explicit rotation by Y. */
4831 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4834 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4836 inst
.error
= _("constant expression expected");
4840 value
= exp
.X_add_number
;
4841 if (value
< 0 || value
> 30 || value
% 2 != 0)
4843 inst
.error
= _("invalid rotation");
4846 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4848 inst
.error
= _("invalid constant");
4852 /* Convert to decoded value. md_apply_fix will put it back. */
4853 inst
.reloc
.exp
.X_add_number
4854 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4855 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4858 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4859 inst
.reloc
.pc_rel
= 0;
4863 /* Group relocation information. Each entry in the table contains the
4864 textual name of the relocation as may appear in assembler source
4865 and must end with a colon.
4866 Along with this textual name are the relocation codes to be used if
4867 the corresponding instruction is an ALU instruction (ADD or SUB only),
4868 an LDR, an LDRS, or an LDC. */
4870 struct group_reloc_table_entry
4881 /* Varieties of non-ALU group relocation. */
4888 static struct group_reloc_table_entry group_reloc_table
[] =
4889 { /* Program counter relative: */
4891 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4896 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4897 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4898 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4899 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4901 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4906 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4907 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4908 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4909 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4911 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4912 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4913 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4914 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4915 /* Section base relative */
4917 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4922 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4923 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4924 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4925 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4927 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4932 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4933 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4934 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4935 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4937 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4938 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4939 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4940 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4942 /* Given the address of a pointer pointing to the textual name of a group
4943 relocation as may appear in assembler source, attempt to find its details
4944 in group_reloc_table. The pointer will be updated to the character after
4945 the trailing colon. On failure, FAIL will be returned; SUCCESS
4946 otherwise. On success, *entry will be updated to point at the relevant
4947 group_reloc_table entry. */
4950 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4953 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4955 int length
= strlen (group_reloc_table
[i
].name
);
4957 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4958 && (*str
)[length
] == ':')
4960 *out
= &group_reloc_table
[i
];
4961 *str
+= (length
+ 1);
4969 /* Parse a <shifter_operand> for an ARM data processing instruction
4970 (as for parse_shifter_operand) where group relocations are allowed:
4973 #<immediate>, <rotate>
4974 #:<group_reloc>:<expression>
4978 where <group_reloc> is one of the strings defined in group_reloc_table.
4979 The hashes are optional.
4981 Everything else is as for parse_shifter_operand. */
4983 static parse_operand_result
4984 parse_shifter_operand_group_reloc (char **str
, int i
)
4986 /* Determine if we have the sequence of characters #: or just :
4987 coming next. If we do, then we check for a group relocation.
4988 If we don't, punt the whole lot to parse_shifter_operand. */
4990 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4991 || (*str
)[0] == ':')
4993 struct group_reloc_table_entry
*entry
;
4995 if ((*str
)[0] == '#')
5000 /* Try to parse a group relocation. Anything else is an error. */
5001 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5003 inst
.error
= _("unknown group relocation");
5004 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5007 /* We now have the group relocation table entry corresponding to
5008 the name in the assembler source. Next, we parse the expression. */
5009 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5010 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5012 /* Record the relocation type (always the ALU variant here). */
5013 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5014 gas_assert (inst
.reloc
.type
!= 0);
5016 return PARSE_OPERAND_SUCCESS
;
5019 return parse_shifter_operand (str
, i
) == SUCCESS
5020 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5022 /* Never reached. */
5025 /* Parse a Neon alignment expression. Information is written to
5026 inst.operands[i]. We assume the initial ':' has been skipped.
5028 align .imm = align << 8, .immisalign=1, .preind=0 */
5029 static parse_operand_result
5030 parse_neon_alignment (char **str
, int i
)
5035 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5037 if (exp
.X_op
!= O_constant
)
5039 inst
.error
= _("alignment must be constant");
5040 return PARSE_OPERAND_FAIL
;
5043 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5044 inst
.operands
[i
].immisalign
= 1;
5045 /* Alignments are not pre-indexes. */
5046 inst
.operands
[i
].preind
= 0;
5049 return PARSE_OPERAND_SUCCESS
;
5052 /* Parse all forms of an ARM address expression. Information is written
5053 to inst.operands[i] and/or inst.reloc.
5055 Preindexed addressing (.preind=1):
5057 [Rn, #offset] .reg=Rn .reloc.exp=offset
5058 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 These three may have a trailing ! which causes .writeback to be set also.
5064 Postindexed addressing (.postind=1, .writeback=1):
5066 [Rn], #offset .reg=Rn .reloc.exp=offset
5067 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5068 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5069 .shift_kind=shift .reloc.exp=shift_imm
5071 Unindexed addressing (.preind=0, .postind=0):
5073 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5077 [Rn]{!} shorthand for [Rn,#0]{!}
5078 =immediate .isreg=0 .reloc.exp=immediate
5079 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5081 It is the caller's responsibility to check for addressing modes not
5082 supported by the instruction, and to set inst.reloc.type. */
5084 static parse_operand_result
5085 parse_address_main (char **str
, int i
, int group_relocations
,
5086 group_reloc_type group_type
)
5091 if (skip_past_char (&p
, '[') == FAIL
)
5093 if (skip_past_char (&p
, '=') == FAIL
)
5095 /* Bare address - translate to PC-relative offset. */
5096 inst
.reloc
.pc_rel
= 1;
5097 inst
.operands
[i
].reg
= REG_PC
;
5098 inst
.operands
[i
].isreg
= 1;
5099 inst
.operands
[i
].preind
= 1;
5101 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5103 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5104 return PARSE_OPERAND_FAIL
;
5107 return PARSE_OPERAND_SUCCESS
;
5110 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5112 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5113 return PARSE_OPERAND_FAIL
;
5115 inst
.operands
[i
].reg
= reg
;
5116 inst
.operands
[i
].isreg
= 1;
5118 if (skip_past_comma (&p
) == SUCCESS
)
5120 inst
.operands
[i
].preind
= 1;
5123 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5127 inst
.operands
[i
].imm
= reg
;
5128 inst
.operands
[i
].immisreg
= 1;
5130 if (skip_past_comma (&p
) == SUCCESS
)
5131 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5132 return PARSE_OPERAND_FAIL
;
5134 else if (skip_past_char (&p
, ':') == SUCCESS
)
5136 /* FIXME: '@' should be used here, but it's filtered out by generic
5137 code before we get to see it here. This may be subject to
5139 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5141 if (result
!= PARSE_OPERAND_SUCCESS
)
5146 if (inst
.operands
[i
].negative
)
5148 inst
.operands
[i
].negative
= 0;
5152 if (group_relocations
5153 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5155 struct group_reloc_table_entry
*entry
;
5157 /* Skip over the #: or : sequence. */
5163 /* Try to parse a group relocation. Anything else is an
5165 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5167 inst
.error
= _("unknown group relocation");
5168 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5171 /* We now have the group relocation table entry corresponding to
5172 the name in the assembler source. Next, we parse the
5174 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5175 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5177 /* Record the relocation type. */
5181 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5185 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5189 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5196 if (inst
.reloc
.type
== 0)
5198 inst
.error
= _("this group relocation is not allowed on this instruction");
5199 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5203 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5204 return PARSE_OPERAND_FAIL
;
5207 else if (skip_past_char (&p
, ':') == SUCCESS
)
5209 /* FIXME: '@' should be used here, but it's filtered out by generic code
5210 before we get to see it here. This may be subject to change. */
5211 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5213 if (result
!= PARSE_OPERAND_SUCCESS
)
5217 if (skip_past_char (&p
, ']') == FAIL
)
5219 inst
.error
= _("']' expected");
5220 return PARSE_OPERAND_FAIL
;
5223 if (skip_past_char (&p
, '!') == SUCCESS
)
5224 inst
.operands
[i
].writeback
= 1;
5226 else if (skip_past_comma (&p
) == SUCCESS
)
5228 if (skip_past_char (&p
, '{') == SUCCESS
)
5230 /* [Rn], {expr} - unindexed, with option */
5231 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5232 0, 255, TRUE
) == FAIL
)
5233 return PARSE_OPERAND_FAIL
;
5235 if (skip_past_char (&p
, '}') == FAIL
)
5237 inst
.error
= _("'}' expected at end of 'option' field");
5238 return PARSE_OPERAND_FAIL
;
5240 if (inst
.operands
[i
].preind
)
5242 inst
.error
= _("cannot combine index with option");
5243 return PARSE_OPERAND_FAIL
;
5246 return PARSE_OPERAND_SUCCESS
;
5250 inst
.operands
[i
].postind
= 1;
5251 inst
.operands
[i
].writeback
= 1;
5253 if (inst
.operands
[i
].preind
)
5255 inst
.error
= _("cannot combine pre- and post-indexing");
5256 return PARSE_OPERAND_FAIL
;
5260 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5262 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5264 /* We might be using the immediate for alignment already. If we
5265 are, OR the register number into the low-order bits. */
5266 if (inst
.operands
[i
].immisalign
)
5267 inst
.operands
[i
].imm
|= reg
;
5269 inst
.operands
[i
].imm
= reg
;
5270 inst
.operands
[i
].immisreg
= 1;
5272 if (skip_past_comma (&p
) == SUCCESS
)
5273 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5274 return PARSE_OPERAND_FAIL
;
5278 if (inst
.operands
[i
].negative
)
5280 inst
.operands
[i
].negative
= 0;
5283 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5284 return PARSE_OPERAND_FAIL
;
5289 /* If at this point neither .preind nor .postind is set, we have a
5290 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5291 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5293 inst
.operands
[i
].preind
= 1;
5294 inst
.reloc
.exp
.X_op
= O_constant
;
5295 inst
.reloc
.exp
.X_add_number
= 0;
5298 return PARSE_OPERAND_SUCCESS
;
5302 parse_address (char **str
, int i
)
5304 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5308 static parse_operand_result
5309 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5311 return parse_address_main (str
, i
, 1, type
);
5314 /* Parse an operand for a MOVW or MOVT instruction. */
5316 parse_half (char **str
)
5321 skip_past_char (&p
, '#');
5322 if (strncasecmp (p
, ":lower16:", 9) == 0)
5323 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5324 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5325 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5327 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5330 skip_whitespace (p
);
5333 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5336 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5338 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5340 inst
.error
= _("constant expression expected");
5343 if (inst
.reloc
.exp
.X_add_number
< 0
5344 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5346 inst
.error
= _("immediate value out of range");
5354 /* Miscellaneous. */
5356 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5357 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5359 parse_psr (char **str
, bfd_boolean lhs
)
5362 unsigned long psr_field
;
5363 const struct asm_psr
*psr
;
5365 bfd_boolean is_apsr
= FALSE
;
5366 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5368 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5369 feature for ease of use and backwards compatibility. */
5371 if (strncasecmp (p
, "SPSR", 4) == 0)
5374 goto unsupported_psr
;
5376 psr_field
= SPSR_BIT
;
5378 else if (strncasecmp (p
, "CPSR", 4) == 0)
5381 goto unsupported_psr
;
5385 else if (strncasecmp (p
, "APSR", 4) == 0)
5387 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5388 and ARMv7-R architecture CPUs. */
5397 while (ISALNUM (*p
) || *p
== '_');
5399 if (strncasecmp (start
, "iapsr", 5) == 0
5400 || strncasecmp (start
, "eapsr", 5) == 0
5401 || strncasecmp (start
, "xpsr", 4) == 0
5402 || strncasecmp (start
, "psr", 3) == 0)
5403 p
= start
+ strcspn (start
, "rR") + 1;
5405 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5411 /* If APSR is being written, a bitfield may be specified. Note that
5412 APSR itself is handled above. */
5413 if (psr
->field
<= 3)
5415 psr_field
= psr
->field
;
5421 /* M-profile MSR instructions have the mask field set to "10", except
5422 *PSR variants which modify APSR, which may use a different mask (and
5423 have been handled already). Do that by setting the PSR_f field
5425 return psr
->field
| (lhs
? PSR_f
: 0);
5428 goto unsupported_psr
;
5434 /* A suffix follows. */
5440 while (ISALNUM (*p
) || *p
== '_');
5444 /* APSR uses a notation for bits, rather than fields. */
5445 unsigned int nzcvq_bits
= 0;
5446 unsigned int g_bit
= 0;
5449 for (bit
= start
; bit
!= p
; bit
++)
5451 switch (TOLOWER (*bit
))
5454 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5458 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5462 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5466 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5470 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5474 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5478 inst
.error
= _("unexpected bit specified after APSR");
5483 if (nzcvq_bits
== 0x1f)
5488 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5490 inst
.error
= _("selected processor does not "
5491 "support DSP extension");
5498 if ((nzcvq_bits
& 0x20) != 0
5499 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5500 || (g_bit
& 0x2) != 0)
5502 inst
.error
= _("bad bitmask specified after APSR");
5508 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5513 psr_field
|= psr
->field
;
5519 goto error
; /* Garbage after "[CS]PSR". */
5521 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5522 is deprecated, but allow it anyway. */
5526 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5529 else if (!m_profile
)
5530 /* These bits are never right for M-profile devices: don't set them
5531 (only code paths which read/write APSR reach here). */
5532 psr_field
|= (PSR_c
| PSR_f
);
5538 inst
.error
= _("selected processor does not support requested special "
5539 "purpose register");
5543 inst
.error
= _("flag for {c}psr instruction expected");
5547 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5548 value suitable for splatting into the AIF field of the instruction. */
5551 parse_cps_flags (char **str
)
5560 case '\0': case ',':
5563 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5564 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5565 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5568 inst
.error
= _("unrecognized CPS flag");
5573 if (saw_a_flag
== 0)
5575 inst
.error
= _("missing CPS flags");
5583 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5584 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5587 parse_endian_specifier (char **str
)
5592 if (strncasecmp (s
, "BE", 2))
5594 else if (strncasecmp (s
, "LE", 2))
5598 inst
.error
= _("valid endian specifiers are be or le");
5602 if (ISALNUM (s
[2]) || s
[2] == '_')
5604 inst
.error
= _("valid endian specifiers are be or le");
5609 return little_endian
;
5612 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5613 value suitable for poking into the rotate field of an sxt or sxta
5614 instruction, or FAIL on error. */
5617 parse_ror (char **str
)
5622 if (strncasecmp (s
, "ROR", 3) == 0)
5626 inst
.error
= _("missing rotation field after comma");
5630 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5635 case 0: *str
= s
; return 0x0;
5636 case 8: *str
= s
; return 0x1;
5637 case 16: *str
= s
; return 0x2;
5638 case 24: *str
= s
; return 0x3;
5641 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5646 /* Parse a conditional code (from conds[] below). The value returned is in the
5647 range 0 .. 14, or FAIL. */
5649 parse_cond (char **str
)
5652 const struct asm_cond
*c
;
5654 /* Condition codes are always 2 characters, so matching up to
5655 3 characters is sufficient. */
5660 while (ISALPHA (*q
) && n
< 3)
5662 cond
[n
] = TOLOWER (*q
);
5667 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5670 inst
.error
= _("condition required");
5678 /* Parse an option for a barrier instruction. Returns the encoding for the
5681 parse_barrier (char **str
)
5684 const struct asm_barrier_opt
*o
;
5687 while (ISALPHA (*q
))
5690 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5699 /* Parse the operands of a table branch instruction. Similar to a memory
5702 parse_tb (char **str
)
5707 if (skip_past_char (&p
, '[') == FAIL
)
5709 inst
.error
= _("'[' expected");
5713 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5715 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5718 inst
.operands
[0].reg
= reg
;
5720 if (skip_past_comma (&p
) == FAIL
)
5722 inst
.error
= _("',' expected");
5726 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5728 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5731 inst
.operands
[0].imm
= reg
;
5733 if (skip_past_comma (&p
) == SUCCESS
)
5735 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5737 if (inst
.reloc
.exp
.X_add_number
!= 1)
5739 inst
.error
= _("invalid shift");
5742 inst
.operands
[0].shifted
= 1;
5745 if (skip_past_char (&p
, ']') == FAIL
)
5747 inst
.error
= _("']' expected");
5754 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5755 information on the types the operands can take and how they are encoded.
5756 Up to four operands may be read; this function handles setting the
5757 ".present" field for each read operand itself.
5758 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5759 else returns FAIL. */
5762 parse_neon_mov (char **str
, int *which_operand
)
5764 int i
= *which_operand
, val
;
5765 enum arm_reg_type rtype
;
5767 struct neon_type_el optype
;
5769 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5771 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5772 inst
.operands
[i
].reg
= val
;
5773 inst
.operands
[i
].isscalar
= 1;
5774 inst
.operands
[i
].vectype
= optype
;
5775 inst
.operands
[i
++].present
= 1;
5777 if (skip_past_comma (&ptr
) == FAIL
)
5780 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5783 inst
.operands
[i
].reg
= val
;
5784 inst
.operands
[i
].isreg
= 1;
5785 inst
.operands
[i
].present
= 1;
5787 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5790 /* Cases 0, 1, 2, 3, 5 (D only). */
5791 if (skip_past_comma (&ptr
) == FAIL
)
5794 inst
.operands
[i
].reg
= val
;
5795 inst
.operands
[i
].isreg
= 1;
5796 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5797 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5798 inst
.operands
[i
].isvec
= 1;
5799 inst
.operands
[i
].vectype
= optype
;
5800 inst
.operands
[i
++].present
= 1;
5802 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5804 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5805 Case 13: VMOV <Sd>, <Rm> */
5806 inst
.operands
[i
].reg
= val
;
5807 inst
.operands
[i
].isreg
= 1;
5808 inst
.operands
[i
].present
= 1;
5810 if (rtype
== REG_TYPE_NQ
)
5812 first_error (_("can't use Neon quad register here"));
5815 else if (rtype
!= REG_TYPE_VFS
)
5818 if (skip_past_comma (&ptr
) == FAIL
)
5820 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5822 inst
.operands
[i
].reg
= val
;
5823 inst
.operands
[i
].isreg
= 1;
5824 inst
.operands
[i
].present
= 1;
5827 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5830 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5831 Case 1: VMOV<c><q> <Dd>, <Dm>
5832 Case 8: VMOV.F32 <Sd>, <Sm>
5833 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5835 inst
.operands
[i
].reg
= val
;
5836 inst
.operands
[i
].isreg
= 1;
5837 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5838 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5839 inst
.operands
[i
].isvec
= 1;
5840 inst
.operands
[i
].vectype
= optype
;
5841 inst
.operands
[i
].present
= 1;
5843 if (skip_past_comma (&ptr
) == SUCCESS
)
5848 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5851 inst
.operands
[i
].reg
= val
;
5852 inst
.operands
[i
].isreg
= 1;
5853 inst
.operands
[i
++].present
= 1;
5855 if (skip_past_comma (&ptr
) == FAIL
)
5858 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5861 inst
.operands
[i
].reg
= val
;
5862 inst
.operands
[i
].isreg
= 1;
5863 inst
.operands
[i
++].present
= 1;
5866 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5867 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5868 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5869 Case 10: VMOV.F32 <Sd>, #<imm>
5870 Case 11: VMOV.F64 <Dd>, #<imm> */
5871 inst
.operands
[i
].immisfloat
= 1;
5872 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5873 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5874 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5878 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5882 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5885 inst
.operands
[i
].reg
= val
;
5886 inst
.operands
[i
].isreg
= 1;
5887 inst
.operands
[i
++].present
= 1;
5889 if (skip_past_comma (&ptr
) == FAIL
)
5892 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5894 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5895 inst
.operands
[i
].reg
= val
;
5896 inst
.operands
[i
].isscalar
= 1;
5897 inst
.operands
[i
].present
= 1;
5898 inst
.operands
[i
].vectype
= optype
;
5900 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5902 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5903 inst
.operands
[i
].reg
= val
;
5904 inst
.operands
[i
].isreg
= 1;
5905 inst
.operands
[i
++].present
= 1;
5907 if (skip_past_comma (&ptr
) == FAIL
)
5910 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5913 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5917 inst
.operands
[i
].reg
= val
;
5918 inst
.operands
[i
].isreg
= 1;
5919 inst
.operands
[i
].isvec
= 1;
5920 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5921 inst
.operands
[i
].vectype
= optype
;
5922 inst
.operands
[i
].present
= 1;
5924 if (rtype
== REG_TYPE_VFS
)
5928 if (skip_past_comma (&ptr
) == FAIL
)
5930 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5933 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5936 inst
.operands
[i
].reg
= val
;
5937 inst
.operands
[i
].isreg
= 1;
5938 inst
.operands
[i
].isvec
= 1;
5939 inst
.operands
[i
].issingle
= 1;
5940 inst
.operands
[i
].vectype
= optype
;
5941 inst
.operands
[i
].present
= 1;
5944 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5948 inst
.operands
[i
].reg
= val
;
5949 inst
.operands
[i
].isreg
= 1;
5950 inst
.operands
[i
].isvec
= 1;
5951 inst
.operands
[i
].issingle
= 1;
5952 inst
.operands
[i
].vectype
= optype
;
5953 inst
.operands
[i
++].present
= 1;
5958 first_error (_("parse error"));
5962 /* Successfully parsed the operands. Update args. */
5968 first_error (_("expected comma"));
5972 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5976 /* Use this macro when the operand constraints are different
5977 for ARM and THUMB (e.g. ldrd). */
5978 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5979 ((arm_operand) | ((thumb_operand) << 16))
5981 /* Matcher codes for parse_operands. */
5982 enum operand_parse_code
5984 OP_stop
, /* end of line */
5986 OP_RR
, /* ARM register */
5987 OP_RRnpc
, /* ARM register, not r15 */
5988 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5989 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5990 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5991 optional trailing ! */
5992 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5993 OP_RCP
, /* Coprocessor number */
5994 OP_RCN
, /* Coprocessor register */
5995 OP_RF
, /* FPA register */
5996 OP_RVS
, /* VFP single precision register */
5997 OP_RVD
, /* VFP double precision register (0..15) */
5998 OP_RND
, /* Neon double precision register (0..31) */
5999 OP_RNQ
, /* Neon quad precision register */
6000 OP_RVSD
, /* VFP single or double precision register */
6001 OP_RNDQ
, /* Neon double or quad precision register */
6002 OP_RNSDQ
, /* Neon single, double or quad precision register */
6003 OP_RNSC
, /* Neon scalar D[X] */
6004 OP_RVC
, /* VFP control register */
6005 OP_RMF
, /* Maverick F register */
6006 OP_RMD
, /* Maverick D register */
6007 OP_RMFX
, /* Maverick FX register */
6008 OP_RMDX
, /* Maverick DX register */
6009 OP_RMAX
, /* Maverick AX register */
6010 OP_RMDS
, /* Maverick DSPSC register */
6011 OP_RIWR
, /* iWMMXt wR register */
6012 OP_RIWC
, /* iWMMXt wC register */
6013 OP_RIWG
, /* iWMMXt wCG register */
6014 OP_RXA
, /* XScale accumulator register */
6016 OP_REGLST
, /* ARM register list */
6017 OP_VRSLST
, /* VFP single-precision register list */
6018 OP_VRDLST
, /* VFP double-precision register list */
6019 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6020 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6021 OP_NSTRLST
, /* Neon element/structure list */
6023 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6024 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6025 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6026 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6027 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6028 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6029 OP_VMOV
, /* Neon VMOV operands. */
6030 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6031 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6032 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6034 OP_I0
, /* immediate zero */
6035 OP_I7
, /* immediate value 0 .. 7 */
6036 OP_I15
, /* 0 .. 15 */
6037 OP_I16
, /* 1 .. 16 */
6038 OP_I16z
, /* 0 .. 16 */
6039 OP_I31
, /* 0 .. 31 */
6040 OP_I31w
, /* 0 .. 31, optional trailing ! */
6041 OP_I32
, /* 1 .. 32 */
6042 OP_I32z
, /* 0 .. 32 */
6043 OP_I63
, /* 0 .. 63 */
6044 OP_I63s
, /* -64 .. 63 */
6045 OP_I64
, /* 1 .. 64 */
6046 OP_I64z
, /* 0 .. 64 */
6047 OP_I255
, /* 0 .. 255 */
6049 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6050 OP_I7b
, /* 0 .. 7 */
6051 OP_I15b
, /* 0 .. 15 */
6052 OP_I31b
, /* 0 .. 31 */
6054 OP_SH
, /* shifter operand */
6055 OP_SHG
, /* shifter operand with possible group relocation */
6056 OP_ADDR
, /* Memory address expression (any mode) */
6057 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6058 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6059 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6060 OP_EXP
, /* arbitrary expression */
6061 OP_EXPi
, /* same, with optional immediate prefix */
6062 OP_EXPr
, /* same, with optional relocation suffix */
6063 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6065 OP_CPSF
, /* CPS flags */
6066 OP_ENDI
, /* Endianness specifier */
6067 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6068 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6069 OP_COND
, /* conditional code */
6070 OP_TB
, /* Table branch. */
6072 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6074 OP_RRnpc_I0
, /* ARM register or literal 0 */
6075 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6076 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6077 OP_RF_IF
, /* FPA register or immediate */
6078 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6079 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6081 /* Optional operands. */
6082 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6083 OP_oI31b
, /* 0 .. 31 */
6084 OP_oI32b
, /* 1 .. 32 */
6085 OP_oIffffb
, /* 0 .. 65535 */
6086 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6088 OP_oRR
, /* ARM register */
6089 OP_oRRnpc
, /* ARM register, not the PC */
6090 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6091 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6092 OP_oRND
, /* Optional Neon double precision register */
6093 OP_oRNQ
, /* Optional Neon quad precision register */
6094 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6095 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6096 OP_oSHll
, /* LSL immediate */
6097 OP_oSHar
, /* ASR immediate */
6098 OP_oSHllar
, /* LSL or ASR immediate */
6099 OP_oROR
, /* ROR 0/8/16/24 */
6100 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6102 /* Some pre-defined mixed (ARM/THUMB) operands. */
6103 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6104 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6105 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6107 OP_FIRST_OPTIONAL
= OP_oI7b
6110 /* Generic instruction operand parser. This does no encoding and no
6111 semantic validation; it merely squirrels values away in the inst
6112 structure. Returns SUCCESS or FAIL depending on whether the
6113 specified grammar matched. */
6115 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6117 unsigned const int *upat
= pattern
;
6118 char *backtrack_pos
= 0;
6119 const char *backtrack_error
= 0;
6120 int i
, val
, backtrack_index
= 0;
6121 enum arm_reg_type rtype
;
6122 parse_operand_result result
;
6123 unsigned int op_parse_code
;
6125 #define po_char_or_fail(chr) \
6128 if (skip_past_char (&str, chr) == FAIL) \
6133 #define po_reg_or_fail(regtype) \
6136 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6137 & inst.operands[i].vectype); \
6140 first_error (_(reg_expected_msgs[regtype])); \
6143 inst.operands[i].reg = val; \
6144 inst.operands[i].isreg = 1; \
6145 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6146 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6147 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6148 || rtype == REG_TYPE_VFD \
6149 || rtype == REG_TYPE_NQ); \
6153 #define po_reg_or_goto(regtype, label) \
6156 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6157 & inst.operands[i].vectype); \
6161 inst.operands[i].reg = val; \
6162 inst.operands[i].isreg = 1; \
6163 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6164 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6165 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6166 || rtype == REG_TYPE_VFD \
6167 || rtype == REG_TYPE_NQ); \
6171 #define po_imm_or_fail(min, max, popt) \
6174 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6176 inst.operands[i].imm = val; \
6180 #define po_scalar_or_goto(elsz, label) \
6183 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6186 inst.operands[i].reg = val; \
6187 inst.operands[i].isscalar = 1; \
6191 #define po_misc_or_fail(expr) \
6199 #define po_misc_or_fail_no_backtrack(expr) \
6203 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6204 backtrack_pos = 0; \
6205 if (result != PARSE_OPERAND_SUCCESS) \
6210 #define po_barrier_or_imm(str) \
6213 val = parse_barrier (&str); \
6216 if (ISALPHA (*str)) \
6223 if ((inst.instruction & 0xf0) == 0x60 \
6226 /* ISB can only take SY as an option. */ \
6227 inst.error = _("invalid barrier type"); \
6234 skip_whitespace (str
);
6236 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6238 op_parse_code
= upat
[i
];
6239 if (op_parse_code
>= 1<<16)
6240 op_parse_code
= thumb
? (op_parse_code
>> 16)
6241 : (op_parse_code
& ((1<<16)-1));
6243 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6245 /* Remember where we are in case we need to backtrack. */
6246 gas_assert (!backtrack_pos
);
6247 backtrack_pos
= str
;
6248 backtrack_error
= inst
.error
;
6249 backtrack_index
= i
;
6252 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6253 po_char_or_fail (',');
6255 switch (op_parse_code
)
6263 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6264 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6265 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6266 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6267 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6268 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6270 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6272 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6274 /* Also accept generic coprocessor regs for unknown registers. */
6276 po_reg_or_fail (REG_TYPE_CN
);
6278 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6279 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6280 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6281 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6282 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6283 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6284 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6285 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6286 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6287 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6289 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6291 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6292 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6294 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6296 /* Neon scalar. Using an element size of 8 means that some invalid
6297 scalars are accepted here, so deal with those in later code. */
6298 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6302 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6305 po_imm_or_fail (0, 0, TRUE
);
6310 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6315 po_scalar_or_goto (8, try_rr
);
6318 po_reg_or_fail (REG_TYPE_RN
);
6324 po_scalar_or_goto (8, try_nsdq
);
6327 po_reg_or_fail (REG_TYPE_NSDQ
);
6333 po_scalar_or_goto (8, try_ndq
);
6336 po_reg_or_fail (REG_TYPE_NDQ
);
6342 po_scalar_or_goto (8, try_vfd
);
6345 po_reg_or_fail (REG_TYPE_VFD
);
6350 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6351 not careful then bad things might happen. */
6352 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6357 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6360 /* There's a possibility of getting a 64-bit immediate here, so
6361 we need special handling. */
6362 if (parse_big_immediate (&str
, i
) == FAIL
)
6364 inst
.error
= _("immediate value is out of range");
6372 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6375 po_imm_or_fail (0, 63, TRUE
);
6380 po_char_or_fail ('[');
6381 po_reg_or_fail (REG_TYPE_RN
);
6382 po_char_or_fail (']');
6388 po_reg_or_fail (REG_TYPE_RN
);
6389 if (skip_past_char (&str
, '!') == SUCCESS
)
6390 inst
.operands
[i
].writeback
= 1;
6394 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6395 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6396 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6397 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6398 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6399 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6400 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6401 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6402 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6403 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6404 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6405 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6407 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6409 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6410 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6412 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6413 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6414 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6416 /* Immediate variants */
6418 po_char_or_fail ('{');
6419 po_imm_or_fail (0, 255, TRUE
);
6420 po_char_or_fail ('}');
6424 /* The expression parser chokes on a trailing !, so we have
6425 to find it first and zap it. */
6428 while (*s
&& *s
!= ',')
6433 inst
.operands
[i
].writeback
= 1;
6435 po_imm_or_fail (0, 31, TRUE
);
6443 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6448 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6453 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6455 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6457 val
= parse_reloc (&str
);
6460 inst
.error
= _("unrecognized relocation suffix");
6463 else if (val
!= BFD_RELOC_UNUSED
)
6465 inst
.operands
[i
].imm
= val
;
6466 inst
.operands
[i
].hasreloc
= 1;
6471 /* Operand for MOVW or MOVT. */
6473 po_misc_or_fail (parse_half (&str
));
6476 /* Register or expression. */
6477 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6478 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6480 /* Register or immediate. */
6481 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6482 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6484 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6486 if (!is_immediate_prefix (*str
))
6489 val
= parse_fpa_immediate (&str
);
6492 /* FPA immediates are encoded as registers 8-15.
6493 parse_fpa_immediate has already applied the offset. */
6494 inst
.operands
[i
].reg
= val
;
6495 inst
.operands
[i
].isreg
= 1;
6498 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6499 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6501 /* Two kinds of register. */
6504 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6506 || (rege
->type
!= REG_TYPE_MMXWR
6507 && rege
->type
!= REG_TYPE_MMXWC
6508 && rege
->type
!= REG_TYPE_MMXWCG
))
6510 inst
.error
= _("iWMMXt data or control register expected");
6513 inst
.operands
[i
].reg
= rege
->number
;
6514 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6520 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6522 || (rege
->type
!= REG_TYPE_MMXWC
6523 && rege
->type
!= REG_TYPE_MMXWCG
))
6525 inst
.error
= _("iWMMXt control register expected");
6528 inst
.operands
[i
].reg
= rege
->number
;
6529 inst
.operands
[i
].isreg
= 1;
6534 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6535 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6536 case OP_oROR
: val
= parse_ror (&str
); break;
6537 case OP_COND
: val
= parse_cond (&str
); break;
6538 case OP_oBARRIER_I15
:
6539 po_barrier_or_imm (str
); break;
6541 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6547 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6548 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6550 inst
.error
= _("Banked registers are not available with this "
6556 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6560 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6563 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6565 if (strncasecmp (str
, "APSR_", 5) == 0)
6572 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6573 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6574 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6575 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6576 default: found
= 16;
6580 inst
.operands
[i
].isvec
= 1;
6581 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6582 inst
.operands
[i
].reg
= REG_PC
;
6589 po_misc_or_fail (parse_tb (&str
));
6592 /* Register lists. */
6594 val
= parse_reg_list (&str
);
6597 inst
.operands
[1].writeback
= 1;
6603 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6607 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6611 /* Allow Q registers too. */
6612 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6617 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6619 inst
.operands
[i
].issingle
= 1;
6624 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6629 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6630 &inst
.operands
[i
].vectype
);
6633 /* Addressing modes */
6635 po_misc_or_fail (parse_address (&str
, i
));
6639 po_misc_or_fail_no_backtrack (
6640 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6644 po_misc_or_fail_no_backtrack (
6645 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6649 po_misc_or_fail_no_backtrack (
6650 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6654 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6658 po_misc_or_fail_no_backtrack (
6659 parse_shifter_operand_group_reloc (&str
, i
));
6663 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6667 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6671 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6675 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6678 /* Various value-based sanity checks and shared operations. We
6679 do not signal immediate failures for the register constraints;
6680 this allows a syntax error to take precedence. */
6681 switch (op_parse_code
)
6689 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6690 inst
.error
= BAD_PC
;
6695 if (inst
.operands
[i
].isreg
)
6697 if (inst
.operands
[i
].reg
== REG_PC
)
6698 inst
.error
= BAD_PC
;
6699 else if (inst
.operands
[i
].reg
== REG_SP
)
6700 inst
.error
= BAD_SP
;
6705 if (inst
.operands
[i
].isreg
6706 && inst
.operands
[i
].reg
== REG_PC
6707 && (inst
.operands
[i
].writeback
|| thumb
))
6708 inst
.error
= BAD_PC
;
6717 case OP_oBARRIER_I15
:
6726 inst
.operands
[i
].imm
= val
;
6733 /* If we get here, this operand was successfully parsed. */
6734 inst
.operands
[i
].present
= 1;
6738 inst
.error
= BAD_ARGS
;
6743 /* The parse routine should already have set inst.error, but set a
6744 default here just in case. */
6746 inst
.error
= _("syntax error");
6750 /* Do not backtrack over a trailing optional argument that
6751 absorbed some text. We will only fail again, with the
6752 'garbage following instruction' error message, which is
6753 probably less helpful than the current one. */
6754 if (backtrack_index
== i
&& backtrack_pos
!= str
6755 && upat
[i
+1] == OP_stop
)
6758 inst
.error
= _("syntax error");
6762 /* Try again, skipping the optional argument at backtrack_pos. */
6763 str
= backtrack_pos
;
6764 inst
.error
= backtrack_error
;
6765 inst
.operands
[backtrack_index
].present
= 0;
6766 i
= backtrack_index
;
6770 /* Check that we have parsed all the arguments. */
6771 if (*str
!= '\0' && !inst
.error
)
6772 inst
.error
= _("garbage following instruction");
6774 return inst
.error
? FAIL
: SUCCESS
;
6777 #undef po_char_or_fail
6778 #undef po_reg_or_fail
6779 #undef po_reg_or_goto
6780 #undef po_imm_or_fail
6781 #undef po_scalar_or_fail
6782 #undef po_barrier_or_imm
6784 /* Shorthand macro for instruction encoding functions issuing errors. */
6785 #define constraint(expr, err) \
6796 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6797 instructions are unpredictable if these registers are used. This
6798 is the BadReg predicate in ARM's Thumb-2 documentation. */
6799 #define reject_bad_reg(reg) \
6801 if (reg == REG_SP || reg == REG_PC) \
6803 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6808 /* If REG is R13 (the stack pointer), warn that its use is
6810 #define warn_deprecated_sp(reg) \
6812 if (warn_on_deprecated && reg == REG_SP) \
6813 as_warn (_("use of r13 is deprecated")); \
6816 /* Functions for operand encoding. ARM, then Thumb. */
6818 #define rotate_left(v, n) (v << n | v >> (32 - n))
6820 /* If VAL can be encoded in the immediate field of an ARM instruction,
6821 return the encoded form. Otherwise, return FAIL. */
6824 encode_arm_immediate (unsigned int val
)
6828 for (i
= 0; i
< 32; i
+= 2)
6829 if ((a
= rotate_left (val
, i
)) <= 0xff)
6830 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6835 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6836 return the encoded form. Otherwise, return FAIL. */
6838 encode_thumb32_immediate (unsigned int val
)
6845 for (i
= 1; i
<= 24; i
++)
6848 if ((val
& ~(0xff << i
)) == 0)
6849 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6853 if (val
== ((a
<< 16) | a
))
6855 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6859 if (val
== ((a
<< 16) | a
))
6860 return 0x200 | (a
>> 8);
6864 /* Encode a VFP SP or DP register number into inst.instruction. */
6867 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6869 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6875 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6878 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6883 first_error (_("D register out of range for selected VFP version"));
6891 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6895 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6899 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6903 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6907 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6911 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6919 /* Encode a <shift> in an ARM-format instruction. The immediate,
6920 if any, is handled by md_apply_fix. */
6922 encode_arm_shift (int i
)
6924 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6925 inst
.instruction
|= SHIFT_ROR
<< 5;
6928 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6929 if (inst
.operands
[i
].immisreg
)
6931 inst
.instruction
|= SHIFT_BY_REG
;
6932 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6935 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6940 encode_arm_shifter_operand (int i
)
6942 if (inst
.operands
[i
].isreg
)
6944 inst
.instruction
|= inst
.operands
[i
].reg
;
6945 encode_arm_shift (i
);
6948 inst
.instruction
|= INST_IMMEDIATE
;
6951 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6953 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6955 gas_assert (inst
.operands
[i
].isreg
);
6956 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6958 if (inst
.operands
[i
].preind
)
6962 inst
.error
= _("instruction does not accept preindexed addressing");
6965 inst
.instruction
|= PRE_INDEX
;
6966 if (inst
.operands
[i
].writeback
)
6967 inst
.instruction
|= WRITE_BACK
;
6970 else if (inst
.operands
[i
].postind
)
6972 gas_assert (inst
.operands
[i
].writeback
);
6974 inst
.instruction
|= WRITE_BACK
;
6976 else /* unindexed - only for coprocessor */
6978 inst
.error
= _("instruction does not accept unindexed addressing");
6982 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6983 && (((inst
.instruction
& 0x000f0000) >> 16)
6984 == ((inst
.instruction
& 0x0000f000) >> 12)))
6985 as_warn ((inst
.instruction
& LOAD_BIT
)
6986 ? _("destination register same as write-back base")
6987 : _("source register same as write-back base"));
6990 /* inst.operands[i] was set up by parse_address. Encode it into an
6991 ARM-format mode 2 load or store instruction. If is_t is true,
6992 reject forms that cannot be used with a T instruction (i.e. not
6995 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6997 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6999 encode_arm_addr_mode_common (i
, is_t
);
7001 if (inst
.operands
[i
].immisreg
)
7003 constraint ((inst
.operands
[i
].imm
== REG_PC
7004 || (is_pc
&& inst
.operands
[i
].writeback
)),
7006 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7007 inst
.instruction
|= inst
.operands
[i
].imm
;
7008 if (!inst
.operands
[i
].negative
)
7009 inst
.instruction
|= INDEX_UP
;
7010 if (inst
.operands
[i
].shifted
)
7012 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7013 inst
.instruction
|= SHIFT_ROR
<< 5;
7016 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7017 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7021 else /* immediate offset in inst.reloc */
7023 if (is_pc
&& !inst
.reloc
.pc_rel
)
7025 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7027 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7028 cannot use PC in addressing.
7029 PC cannot be used in writeback addressing, either. */
7030 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7033 /* Use of PC in str is deprecated for ARMv7. */
7034 if (warn_on_deprecated
7036 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7037 as_warn (_("use of PC in this instruction is deprecated"));
7040 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7041 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7045 /* inst.operands[i] was set up by parse_address. Encode it into an
7046 ARM-format mode 3 load or store instruction. Reject forms that
7047 cannot be used with such instructions. If is_t is true, reject
7048 forms that cannot be used with a T instruction (i.e. not
7051 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7053 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7055 inst
.error
= _("instruction does not accept scaled register index");
7059 encode_arm_addr_mode_common (i
, is_t
);
7061 if (inst
.operands
[i
].immisreg
)
7063 constraint ((inst
.operands
[i
].imm
== REG_PC
7064 || inst
.operands
[i
].reg
== REG_PC
),
7066 inst
.instruction
|= inst
.operands
[i
].imm
;
7067 if (!inst
.operands
[i
].negative
)
7068 inst
.instruction
|= INDEX_UP
;
7070 else /* immediate offset in inst.reloc */
7072 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7073 && inst
.operands
[i
].writeback
),
7075 inst
.instruction
|= HWOFFSET_IMM
;
7076 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7077 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7081 /* inst.operands[i] was set up by parse_address. Encode it into an
7082 ARM-format instruction. Reject all forms which cannot be encoded
7083 into a coprocessor load/store instruction. If wb_ok is false,
7084 reject use of writeback; if unind_ok is false, reject use of
7085 unindexed addressing. If reloc_override is not 0, use it instead
7086 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7087 (in which case it is preserved). */
7090 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7092 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7094 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7096 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7098 gas_assert (!inst
.operands
[i
].writeback
);
7101 inst
.error
= _("instruction does not support unindexed addressing");
7104 inst
.instruction
|= inst
.operands
[i
].imm
;
7105 inst
.instruction
|= INDEX_UP
;
7109 if (inst
.operands
[i
].preind
)
7110 inst
.instruction
|= PRE_INDEX
;
7112 if (inst
.operands
[i
].writeback
)
7114 if (inst
.operands
[i
].reg
== REG_PC
)
7116 inst
.error
= _("pc may not be used with write-back");
7121 inst
.error
= _("instruction does not support writeback");
7124 inst
.instruction
|= WRITE_BACK
;
7128 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7129 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7130 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7131 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7134 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7136 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7142 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7143 Determine whether it can be performed with a move instruction; if
7144 it can, convert inst.instruction to that move instruction and
7145 return TRUE; if it can't, convert inst.instruction to a literal-pool
7146 load and return FALSE. If this is not a valid thing to do in the
7147 current context, set inst.error and return TRUE.
7149 inst.operands[i] describes the destination register. */
7152 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7157 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7161 if ((inst
.instruction
& tbit
) == 0)
7163 inst
.error
= _("invalid pseudo operation");
7166 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7168 inst
.error
= _("constant expression expected");
7171 if (inst
.reloc
.exp
.X_op
== O_constant
)
7175 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7177 /* This can be done with a mov(1) instruction. */
7178 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7179 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7185 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7188 /* This can be done with a mov instruction. */
7189 inst
.instruction
&= LITERAL_MASK
;
7190 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7191 inst
.instruction
|= value
& 0xfff;
7195 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7198 /* This can be done with a mvn instruction. */
7199 inst
.instruction
&= LITERAL_MASK
;
7200 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7201 inst
.instruction
|= value
& 0xfff;
7207 if (add_to_lit_pool () == FAIL
)
7209 inst
.error
= _("literal pool insertion failed");
7212 inst
.operands
[1].reg
= REG_PC
;
7213 inst
.operands
[1].isreg
= 1;
7214 inst
.operands
[1].preind
= 1;
7215 inst
.reloc
.pc_rel
= 1;
7216 inst
.reloc
.type
= (thumb_p
7217 ? BFD_RELOC_ARM_THUMB_OFFSET
7219 ? BFD_RELOC_ARM_HWLITERAL
7220 : BFD_RELOC_ARM_LITERAL
));
7224 /* Functions for instruction encoding, sorted by sub-architecture.
7225 First some generics; their names are taken from the conventional
7226 bit positions for register arguments in ARM format instructions. */
7236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7243 inst
.instruction
|= inst
.operands
[1].reg
;
7249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7250 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7256 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7257 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7263 unsigned Rn
= inst
.operands
[2].reg
;
7264 /* Enforce restrictions on SWP instruction. */
7265 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7267 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7268 _("Rn must not overlap other operands"));
7270 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7271 if (warn_on_deprecated
7272 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7273 as_warn (_("swp{b} use is deprecated for this architecture"));
7276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7277 inst
.instruction
|= inst
.operands
[1].reg
;
7278 inst
.instruction
|= Rn
<< 16;
7284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7285 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7286 inst
.instruction
|= inst
.operands
[2].reg
;
7292 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7293 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7294 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7295 || inst
.reloc
.exp
.X_add_number
!= 0),
7297 inst
.instruction
|= inst
.operands
[0].reg
;
7298 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7299 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7305 inst
.instruction
|= inst
.operands
[0].imm
;
7311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7312 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7315 /* ARM instructions, in alphabetical order by function name (except
7316 that wrapper functions appear immediately after the function they
7319 /* This is a pseudo-op of the form "adr rd, label" to be converted
7320 into a relative address of the form "add rd, pc, #label-.-8". */
7325 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7327 /* Frag hacking will turn this into a sub instruction if the offset turns
7328 out to be negative. */
7329 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7330 inst
.reloc
.pc_rel
= 1;
7331 inst
.reloc
.exp
.X_add_number
-= 8;
7334 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7335 into a relative address of the form:
7336 add rd, pc, #low(label-.-8)"
7337 add rd, rd, #high(label-.-8)" */
7342 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7344 /* Frag hacking will turn this into a sub instruction if the offset turns
7345 out to be negative. */
7346 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7347 inst
.reloc
.pc_rel
= 1;
7348 inst
.size
= INSN_SIZE
* 2;
7349 inst
.reloc
.exp
.X_add_number
-= 8;
7355 if (!inst
.operands
[1].present
)
7356 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7358 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7359 encode_arm_shifter_operand (2);
7365 if (inst
.operands
[0].present
)
7367 constraint ((inst
.instruction
& 0xf0) != 0x40
7368 && inst
.operands
[0].imm
> 0xf
7369 && inst
.operands
[0].imm
< 0x0,
7370 _("bad barrier type"));
7371 inst
.instruction
|= inst
.operands
[0].imm
;
7374 inst
.instruction
|= 0xf;
7380 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7381 constraint (msb
> 32, _("bit-field extends past end of register"));
7382 /* The instruction encoding stores the LSB and MSB,
7383 not the LSB and width. */
7384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7385 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7386 inst
.instruction
|= (msb
- 1) << 16;
7394 /* #0 in second position is alternative syntax for bfc, which is
7395 the same instruction but with REG_PC in the Rm field. */
7396 if (!inst
.operands
[1].isreg
)
7397 inst
.operands
[1].reg
= REG_PC
;
7399 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7400 constraint (msb
> 32, _("bit-field extends past end of register"));
7401 /* The instruction encoding stores the LSB and MSB,
7402 not the LSB and width. */
7403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7404 inst
.instruction
|= inst
.operands
[1].reg
;
7405 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7406 inst
.instruction
|= (msb
- 1) << 16;
7412 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7413 _("bit-field extends past end of register"));
7414 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7415 inst
.instruction
|= inst
.operands
[1].reg
;
7416 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7417 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7420 /* ARM V5 breakpoint instruction (argument parse)
7421 BKPT <16 bit unsigned immediate>
7422 Instruction is not conditional.
7423 The bit pattern given in insns[] has the COND_ALWAYS condition,
7424 and it is an error if the caller tried to override that. */
7429 /* Top 12 of 16 bits to bits 19:8. */
7430 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7432 /* Bottom 4 of 16 bits to bits 3:0. */
7433 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7437 encode_branch (int default_reloc
)
7439 if (inst
.operands
[0].hasreloc
)
7441 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7442 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7443 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7444 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7445 ? BFD_RELOC_ARM_PLT32
7446 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7449 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7450 inst
.reloc
.pc_rel
= 1;
7457 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7458 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7461 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7468 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7470 if (inst
.cond
== COND_ALWAYS
)
7471 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7473 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7477 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7480 /* ARM V5 branch-link-exchange instruction (argument parse)
7481 BLX <target_addr> ie BLX(1)
7482 BLX{<condition>} <Rm> ie BLX(2)
7483 Unfortunately, there are two different opcodes for this mnemonic.
7484 So, the insns[].value is not used, and the code here zaps values
7485 into inst.instruction.
7486 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7491 if (inst
.operands
[0].isreg
)
7493 /* Arg is a register; the opcode provided by insns[] is correct.
7494 It is not illegal to do "blx pc", just useless. */
7495 if (inst
.operands
[0].reg
== REG_PC
)
7496 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7498 inst
.instruction
|= inst
.operands
[0].reg
;
7502 /* Arg is an address; this instruction cannot be executed
7503 conditionally, and the opcode must be adjusted.
7504 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7505 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7506 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7507 inst
.instruction
= 0xfa000000;
7508 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7515 bfd_boolean want_reloc
;
7517 if (inst
.operands
[0].reg
== REG_PC
)
7518 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7520 inst
.instruction
|= inst
.operands
[0].reg
;
7521 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7522 it is for ARMv4t or earlier. */
7523 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7524 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7528 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7533 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7537 /* ARM v5TEJ. Jump to Jazelle code. */
7542 if (inst
.operands
[0].reg
== REG_PC
)
7543 as_tsktsk (_("use of r15 in bxj is not really useful"));
7545 inst
.instruction
|= inst
.operands
[0].reg
;
7548 /* Co-processor data operation:
7549 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7550 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7554 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7555 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7556 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7557 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7558 inst
.instruction
|= inst
.operands
[4].reg
;
7559 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7565 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7566 encode_arm_shifter_operand (1);
7569 /* Transfer between coprocessor and ARM registers.
7570 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7575 No special properties. */
7582 Rd
= inst
.operands
[2].reg
;
7585 if (inst
.instruction
== 0xee000010
7586 || inst
.instruction
== 0xfe000010)
7588 reject_bad_reg (Rd
);
7591 constraint (Rd
== REG_SP
, BAD_SP
);
7596 if (inst
.instruction
== 0xe000010)
7597 constraint (Rd
== REG_PC
, BAD_PC
);
7601 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7602 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7603 inst
.instruction
|= Rd
<< 12;
7604 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7605 inst
.instruction
|= inst
.operands
[4].reg
;
7606 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7609 /* Transfer between coprocessor register and pair of ARM registers.
7610 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7615 Two XScale instructions are special cases of these:
7617 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7618 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7620 Result unpredictable if Rd or Rn is R15. */
7627 Rd
= inst
.operands
[2].reg
;
7628 Rn
= inst
.operands
[3].reg
;
7632 reject_bad_reg (Rd
);
7633 reject_bad_reg (Rn
);
7637 constraint (Rd
== REG_PC
, BAD_PC
);
7638 constraint (Rn
== REG_PC
, BAD_PC
);
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7642 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7643 inst
.instruction
|= Rd
<< 12;
7644 inst
.instruction
|= Rn
<< 16;
7645 inst
.instruction
|= inst
.operands
[4].reg
;
7651 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7652 if (inst
.operands
[1].present
)
7654 inst
.instruction
|= CPSI_MMOD
;
7655 inst
.instruction
|= inst
.operands
[1].imm
;
7662 inst
.instruction
|= inst
.operands
[0].imm
;
7668 unsigned Rd
, Rn
, Rm
;
7670 Rd
= inst
.operands
[0].reg
;
7671 Rn
= (inst
.operands
[1].present
7672 ? inst
.operands
[1].reg
: Rd
);
7673 Rm
= inst
.operands
[2].reg
;
7675 constraint ((Rd
== REG_PC
), BAD_PC
);
7676 constraint ((Rn
== REG_PC
), BAD_PC
);
7677 constraint ((Rm
== REG_PC
), BAD_PC
);
7679 inst
.instruction
|= Rd
<< 16;
7680 inst
.instruction
|= Rn
<< 0;
7681 inst
.instruction
|= Rm
<< 8;
7687 /* There is no IT instruction in ARM mode. We
7688 process it to do the validation as if in
7689 thumb mode, just in case the code gets
7690 assembled for thumb using the unified syntax. */
7695 set_it_insn_type (IT_INSN
);
7696 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7697 now_it
.cc
= inst
.operands
[0].imm
;
7704 int base_reg
= inst
.operands
[0].reg
;
7705 int range
= inst
.operands
[1].imm
;
7707 inst
.instruction
|= base_reg
<< 16;
7708 inst
.instruction
|= range
;
7710 if (inst
.operands
[1].writeback
)
7711 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7713 if (inst
.operands
[0].writeback
)
7715 inst
.instruction
|= WRITE_BACK
;
7716 /* Check for unpredictable uses of writeback. */
7717 if (inst
.instruction
& LOAD_BIT
)
7719 /* Not allowed in LDM type 2. */
7720 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7721 && ((range
& (1 << REG_PC
)) == 0))
7722 as_warn (_("writeback of base register is UNPREDICTABLE"));
7723 /* Only allowed if base reg not in list for other types. */
7724 else if (range
& (1 << base_reg
))
7725 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7729 /* Not allowed for type 2. */
7730 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7731 as_warn (_("writeback of base register is UNPREDICTABLE"));
7732 /* Only allowed if base reg not in list, or first in list. */
7733 else if ((range
& (1 << base_reg
))
7734 && (range
& ((1 << base_reg
) - 1)))
7735 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7740 /* ARMv5TE load-consecutive (argument parse)
7749 constraint (inst
.operands
[0].reg
% 2 != 0,
7750 _("first destination register must be even"));
7751 constraint (inst
.operands
[1].present
7752 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7753 _("can only load two consecutive registers"));
7754 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7755 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7757 if (!inst
.operands
[1].present
)
7758 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7760 if (inst
.instruction
& LOAD_BIT
)
7762 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7763 register and the first register written; we have to diagnose
7764 overlap between the base and the second register written here. */
7766 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7767 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7768 as_warn (_("base register written back, and overlaps "
7769 "second destination register"));
7771 /* For an index-register load, the index register must not overlap the
7772 destination (even if not write-back). */
7773 else if (inst
.operands
[2].immisreg
7774 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7775 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7776 as_warn (_("index register overlaps destination register"));
7779 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7780 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7786 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7787 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7788 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7789 || inst
.operands
[1].negative
7790 /* This can arise if the programmer has written
7792 or if they have mistakenly used a register name as the last
7795 It is very difficult to distinguish between these two cases
7796 because "rX" might actually be a label. ie the register
7797 name has been occluded by a symbol of the same name. So we
7798 just generate a general 'bad addressing mode' type error
7799 message and leave it up to the programmer to discover the
7800 true cause and fix their mistake. */
7801 || (inst
.operands
[1].reg
== REG_PC
),
7804 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7805 || inst
.reloc
.exp
.X_add_number
!= 0,
7806 _("offset must be zero in ARM encoding"));
7808 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7810 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7811 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7812 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7818 constraint (inst
.operands
[0].reg
% 2 != 0,
7819 _("even register required"));
7820 constraint (inst
.operands
[1].present
7821 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7822 _("can only load two consecutive registers"));
7823 /* If op 1 were present and equal to PC, this function wouldn't
7824 have been called in the first place. */
7825 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7827 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7828 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7835 if (!inst
.operands
[1].isreg
)
7836 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7838 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7844 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7846 if (inst
.operands
[1].preind
)
7848 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7849 || inst
.reloc
.exp
.X_add_number
!= 0,
7850 _("this instruction requires a post-indexed address"));
7852 inst
.operands
[1].preind
= 0;
7853 inst
.operands
[1].postind
= 1;
7854 inst
.operands
[1].writeback
= 1;
7856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7857 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7860 /* Halfword and signed-byte load/store operations. */
7865 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7867 if (!inst
.operands
[1].isreg
)
7868 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7870 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7876 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7878 if (inst
.operands
[1].preind
)
7880 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7881 || inst
.reloc
.exp
.X_add_number
!= 0,
7882 _("this instruction requires a post-indexed address"));
7884 inst
.operands
[1].preind
= 0;
7885 inst
.operands
[1].postind
= 1;
7886 inst
.operands
[1].writeback
= 1;
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7889 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7892 /* Co-processor register load/store.
7893 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7897 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7898 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7899 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7905 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7906 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7907 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7908 && !(inst
.instruction
& 0x00400000))
7909 as_tsktsk (_("Rd and Rm should be different in mla"));
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7912 inst
.instruction
|= inst
.operands
[1].reg
;
7913 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7914 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7921 encode_arm_shifter_operand (1);
7924 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7931 top
= (inst
.instruction
& 0x00400000) != 0;
7932 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7933 _(":lower16: not allowed this instruction"));
7934 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7935 _(":upper16: not allowed instruction"));
7936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7937 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7939 imm
= inst
.reloc
.exp
.X_add_number
;
7940 /* The value is in two pieces: 0:11, 16:19. */
7941 inst
.instruction
|= (imm
& 0x00000fff);
7942 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7946 static void do_vfp_nsyn_opcode (const char *);
7949 do_vfp_nsyn_mrs (void)
7951 if (inst
.operands
[0].isvec
)
7953 if (inst
.operands
[1].reg
!= 1)
7954 first_error (_("operand 1 must be FPSCR"));
7955 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7956 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7957 do_vfp_nsyn_opcode ("fmstat");
7959 else if (inst
.operands
[1].isvec
)
7960 do_vfp_nsyn_opcode ("fmrx");
7968 do_vfp_nsyn_msr (void)
7970 if (inst
.operands
[0].isvec
)
7971 do_vfp_nsyn_opcode ("fmxr");
7981 unsigned Rt
= inst
.operands
[0].reg
;
7983 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7985 inst
.error
= BAD_SP
;
7989 /* APSR_ sets isvec. All other refs to PC are illegal. */
7990 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7992 inst
.error
= BAD_PC
;
7996 if (inst
.operands
[1].reg
!= 1)
7997 first_error (_("operand 1 must be FPSCR"));
7999 inst
.instruction
|= (Rt
<< 12);
8005 unsigned Rt
= inst
.operands
[1].reg
;
8008 reject_bad_reg (Rt
);
8009 else if (Rt
== REG_PC
)
8011 inst
.error
= BAD_PC
;
8015 if (inst
.operands
[0].reg
!= 1)
8016 first_error (_("operand 0 must be FPSCR"));
8018 inst
.instruction
|= (Rt
<< 12);
8026 if (do_vfp_nsyn_mrs () == SUCCESS
)
8029 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8032 if (inst
.operands
[1].isreg
)
8034 br
= inst
.operands
[1].reg
;
8035 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8036 as_bad (_("bad register for mrs"));
8040 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8041 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8043 _("'APSR', 'CPSR' or 'SPSR' expected"));
8044 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8047 inst
.instruction
|= br
;
8050 /* Two possible forms:
8051 "{C|S}PSR_<field>, Rm",
8052 "{C|S}PSR_f, #expression". */
8057 if (do_vfp_nsyn_msr () == SUCCESS
)
8060 inst
.instruction
|= inst
.operands
[0].imm
;
8061 if (inst
.operands
[1].isreg
)
8062 inst
.instruction
|= inst
.operands
[1].reg
;
8065 inst
.instruction
|= INST_IMMEDIATE
;
8066 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8067 inst
.reloc
.pc_rel
= 0;
8074 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8076 if (!inst
.operands
[2].present
)
8077 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8078 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8079 inst
.instruction
|= inst
.operands
[1].reg
;
8080 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8082 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8083 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8084 as_tsktsk (_("Rd and Rm should be different in mul"));
8087 /* Long Multiply Parser
8088 UMULL RdLo, RdHi, Rm, Rs
8089 SMULL RdLo, RdHi, Rm, Rs
8090 UMLAL RdLo, RdHi, Rm, Rs
8091 SMLAL RdLo, RdHi, Rm, Rs. */
8096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8097 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8098 inst
.instruction
|= inst
.operands
[2].reg
;
8099 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8101 /* rdhi and rdlo must be different. */
8102 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8103 as_tsktsk (_("rdhi and rdlo must be different"));
8105 /* rdhi, rdlo and rm must all be different before armv6. */
8106 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8107 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8108 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8109 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8115 if (inst
.operands
[0].present
8116 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8118 /* Architectural NOP hints are CPSR sets with no bits selected. */
8119 inst
.instruction
&= 0xf0000000;
8120 inst
.instruction
|= 0x0320f000;
8121 if (inst
.operands
[0].present
)
8122 inst
.instruction
|= inst
.operands
[0].imm
;
8126 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8127 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8128 Condition defaults to COND_ALWAYS.
8129 Error if Rd, Rn or Rm are R15. */
8134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8135 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8136 inst
.instruction
|= inst
.operands
[2].reg
;
8137 if (inst
.operands
[3].present
)
8138 encode_arm_shift (3);
8141 /* ARM V6 PKHTB (Argument Parse). */
8146 if (!inst
.operands
[3].present
)
8148 /* If the shift specifier is omitted, turn the instruction
8149 into pkhbt rd, rm, rn. */
8150 inst
.instruction
&= 0xfff00010;
8151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8152 inst
.instruction
|= inst
.operands
[1].reg
;
8153 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8157 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8158 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8159 inst
.instruction
|= inst
.operands
[2].reg
;
8160 encode_arm_shift (3);
8164 /* ARMv5TE: Preload-Cache
8165 MP Extensions: Preload for write
8169 Syntactically, like LDR with B=1, W=0, L=1. */
8174 constraint (!inst
.operands
[0].isreg
,
8175 _("'[' expected after PLD mnemonic"));
8176 constraint (inst
.operands
[0].postind
,
8177 _("post-indexed expression used in preload instruction"));
8178 constraint (inst
.operands
[0].writeback
,
8179 _("writeback used in preload instruction"));
8180 constraint (!inst
.operands
[0].preind
,
8181 _("unindexed addressing used in preload instruction"));
8182 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8185 /* ARMv7: PLI <addr_mode> */
8189 constraint (!inst
.operands
[0].isreg
,
8190 _("'[' expected after PLI mnemonic"));
8191 constraint (inst
.operands
[0].postind
,
8192 _("post-indexed expression used in preload instruction"));
8193 constraint (inst
.operands
[0].writeback
,
8194 _("writeback used in preload instruction"));
8195 constraint (!inst
.operands
[0].preind
,
8196 _("unindexed addressing used in preload instruction"));
8197 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8198 inst
.instruction
&= ~PRE_INDEX
;
8204 inst
.operands
[1] = inst
.operands
[0];
8205 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8206 inst
.operands
[0].isreg
= 1;
8207 inst
.operands
[0].writeback
= 1;
8208 inst
.operands
[0].reg
= REG_SP
;
8212 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8213 word at the specified address and the following word
8215 Unconditionally executed.
8216 Error if Rn is R15. */
8221 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8222 if (inst
.operands
[0].writeback
)
8223 inst
.instruction
|= WRITE_BACK
;
8226 /* ARM V6 ssat (argument parse). */
8231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8232 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8233 inst
.instruction
|= inst
.operands
[2].reg
;
8235 if (inst
.operands
[3].present
)
8236 encode_arm_shift (3);
8239 /* ARM V6 usat (argument parse). */
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8246 inst
.instruction
|= inst
.operands
[2].reg
;
8248 if (inst
.operands
[3].present
)
8249 encode_arm_shift (3);
8252 /* ARM V6 ssat16 (argument parse). */
8257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8258 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8259 inst
.instruction
|= inst
.operands
[2].reg
;
8265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8266 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8267 inst
.instruction
|= inst
.operands
[2].reg
;
8270 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8271 preserving the other bits.
8273 setend <endian_specifier>, where <endian_specifier> is either
8279 if (inst
.operands
[0].imm
)
8280 inst
.instruction
|= 0x200;
8286 unsigned int Rm
= (inst
.operands
[1].present
8287 ? inst
.operands
[1].reg
8288 : inst
.operands
[0].reg
);
8290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8291 inst
.instruction
|= Rm
;
8292 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8294 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8295 inst
.instruction
|= SHIFT_BY_REG
;
8298 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8304 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8305 inst
.reloc
.pc_rel
= 0;
8311 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8312 inst
.reloc
.pc_rel
= 0;
8318 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8319 inst
.reloc
.pc_rel
= 0;
8322 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8323 SMLAxy{cond} Rd,Rm,Rs,Rn
8324 SMLAWy{cond} Rd,Rm,Rs,Rn
8325 Error if any register is R15. */
8330 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8331 inst
.instruction
|= inst
.operands
[1].reg
;
8332 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8333 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8336 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8337 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8338 Error if any register is R15.
8339 Warning if Rdlo == Rdhi. */
8344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8345 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8346 inst
.instruction
|= inst
.operands
[2].reg
;
8347 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8349 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8350 as_tsktsk (_("rdhi and rdlo must be different"));
8353 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8354 SMULxy{cond} Rd,Rm,Rs
8355 Error if any register is R15. */
8360 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8361 inst
.instruction
|= inst
.operands
[1].reg
;
8362 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8365 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8366 the same for both ARM and Thumb-2. */
8373 if (inst
.operands
[0].present
)
8375 reg
= inst
.operands
[0].reg
;
8376 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8381 inst
.instruction
|= reg
<< 16;
8382 inst
.instruction
|= inst
.operands
[1].imm
;
8383 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8384 inst
.instruction
|= WRITE_BACK
;
8387 /* ARM V6 strex (argument parse). */
8392 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8393 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8394 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8395 || inst
.operands
[2].negative
8396 /* See comment in do_ldrex(). */
8397 || (inst
.operands
[2].reg
== REG_PC
),
8400 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8401 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8403 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8404 || inst
.reloc
.exp
.X_add_number
!= 0,
8405 _("offset must be zero in ARM encoding"));
8407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8408 inst
.instruction
|= inst
.operands
[1].reg
;
8409 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8410 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8416 constraint (inst
.operands
[1].reg
% 2 != 0,
8417 _("even register required"));
8418 constraint (inst
.operands
[2].present
8419 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8420 _("can only store two consecutive registers"));
8421 /* If op 2 were present and equal to PC, this function wouldn't
8422 have been called in the first place. */
8423 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8425 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8426 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8427 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8431 inst
.instruction
|= inst
.operands
[1].reg
;
8432 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8435 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8436 extends it to 32-bits, and adds the result to a value in another
8437 register. You can specify a rotation by 0, 8, 16, or 24 bits
8438 before extracting the 16-bit value.
8439 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8440 Condition defaults to COND_ALWAYS.
8441 Error if any register uses R15. */
8446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8447 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8448 inst
.instruction
|= inst
.operands
[2].reg
;
8449 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8454 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8455 Condition defaults to COND_ALWAYS.
8456 Error if any register uses R15. */
8461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8462 inst
.instruction
|= inst
.operands
[1].reg
;
8463 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8466 /* VFP instructions. In a logical order: SP variant first, monad
8467 before dyad, arithmetic then move then load/store. */
8470 do_vfp_sp_monadic (void)
8472 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8473 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8477 do_vfp_sp_dyadic (void)
8479 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8480 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8481 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8485 do_vfp_sp_compare_z (void)
8487 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8491 do_vfp_dp_sp_cvt (void)
8493 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8494 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8498 do_vfp_sp_dp_cvt (void)
8500 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8501 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8505 do_vfp_reg_from_sp (void)
8507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8508 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8512 do_vfp_reg2_from_sp2 (void)
8514 constraint (inst
.operands
[2].imm
!= 2,
8515 _("only two consecutive VFP SP registers allowed here"));
8516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8517 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8518 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8522 do_vfp_sp_from_reg (void)
8524 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8525 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8529 do_vfp_sp2_from_reg2 (void)
8531 constraint (inst
.operands
[0].imm
!= 2,
8532 _("only two consecutive VFP SP registers allowed here"));
8533 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8534 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8535 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8539 do_vfp_sp_ldst (void)
8541 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8542 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8546 do_vfp_dp_ldst (void)
8548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8549 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8554 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8556 if (inst
.operands
[0].writeback
)
8557 inst
.instruction
|= WRITE_BACK
;
8559 constraint (ldstm_type
!= VFP_LDSTMIA
,
8560 _("this addressing mode requires base-register writeback"));
8561 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8562 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8563 inst
.instruction
|= inst
.operands
[1].imm
;
8567 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8571 if (inst
.operands
[0].writeback
)
8572 inst
.instruction
|= WRITE_BACK
;
8574 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8575 _("this addressing mode requires base-register writeback"));
8577 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8578 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8580 count
= inst
.operands
[1].imm
<< 1;
8581 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8584 inst
.instruction
|= count
;
8588 do_vfp_sp_ldstmia (void)
8590 vfp_sp_ldstm (VFP_LDSTMIA
);
8594 do_vfp_sp_ldstmdb (void)
8596 vfp_sp_ldstm (VFP_LDSTMDB
);
8600 do_vfp_dp_ldstmia (void)
8602 vfp_dp_ldstm (VFP_LDSTMIA
);
8606 do_vfp_dp_ldstmdb (void)
8608 vfp_dp_ldstm (VFP_LDSTMDB
);
8612 do_vfp_xp_ldstmia (void)
8614 vfp_dp_ldstm (VFP_LDSTMIAX
);
8618 do_vfp_xp_ldstmdb (void)
8620 vfp_dp_ldstm (VFP_LDSTMDBX
);
8624 do_vfp_dp_rd_rm (void)
8626 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8627 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8631 do_vfp_dp_rn_rd (void)
8633 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8634 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8638 do_vfp_dp_rd_rn (void)
8640 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8641 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8645 do_vfp_dp_rd_rn_rm (void)
8647 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8648 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8649 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8659 do_vfp_dp_rm_rd_rn (void)
8661 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8662 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8663 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8666 /* VFPv3 instructions. */
8668 do_vfp_sp_const (void)
8670 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8671 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8672 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8676 do_vfp_dp_const (void)
8678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8679 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8680 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8684 vfp_conv (int srcsize
)
8686 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8687 inst
.instruction
|= (immbits
& 1) << 5;
8688 inst
.instruction
|= (immbits
>> 1);
8692 do_vfp_sp_conv_16 (void)
8694 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8699 do_vfp_dp_conv_16 (void)
8701 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8706 do_vfp_sp_conv_32 (void)
8708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8713 do_vfp_dp_conv_32 (void)
8715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8719 /* FPA instructions. Also in a logical order. */
8724 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8725 inst
.instruction
|= inst
.operands
[1].reg
;
8729 do_fpa_ldmstm (void)
8731 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8732 switch (inst
.operands
[1].imm
)
8734 case 1: inst
.instruction
|= CP_T_X
; break;
8735 case 2: inst
.instruction
|= CP_T_Y
; break;
8736 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8741 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8743 /* The instruction specified "ea" or "fd", so we can only accept
8744 [Rn]{!}. The instruction does not really support stacking or
8745 unstacking, so we have to emulate these by setting appropriate
8746 bits and offsets. */
8747 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8748 || inst
.reloc
.exp
.X_add_number
!= 0,
8749 _("this instruction does not support indexing"));
8751 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8752 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8754 if (!(inst
.instruction
& INDEX_UP
))
8755 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8757 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8759 inst
.operands
[2].preind
= 0;
8760 inst
.operands
[2].postind
= 1;
8764 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8767 /* iWMMXt instructions: strictly in alphabetical order. */
8770 do_iwmmxt_tandorc (void)
8772 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8776 do_iwmmxt_textrc (void)
8778 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8779 inst
.instruction
|= inst
.operands
[1].imm
;
8783 do_iwmmxt_textrm (void)
8785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8786 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8787 inst
.instruction
|= inst
.operands
[2].imm
;
8791 do_iwmmxt_tinsr (void)
8793 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8794 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8795 inst
.instruction
|= inst
.operands
[2].imm
;
8799 do_iwmmxt_tmia (void)
8801 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8802 inst
.instruction
|= inst
.operands
[1].reg
;
8803 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8807 do_iwmmxt_waligni (void)
8809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8810 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8811 inst
.instruction
|= inst
.operands
[2].reg
;
8812 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8816 do_iwmmxt_wmerge (void)
8818 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8820 inst
.instruction
|= inst
.operands
[2].reg
;
8821 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8825 do_iwmmxt_wmov (void)
8827 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8829 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8830 inst
.instruction
|= inst
.operands
[1].reg
;
8834 do_iwmmxt_wldstbh (void)
8837 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8839 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8841 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8842 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8846 do_iwmmxt_wldstw (void)
8848 /* RIWR_RIWC clears .isreg for a control register. */
8849 if (!inst
.operands
[0].isreg
)
8851 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8852 inst
.instruction
|= 0xf0000000;
8855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8856 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8860 do_iwmmxt_wldstd (void)
8862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8863 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8864 && inst
.operands
[1].immisreg
)
8866 inst
.instruction
&= ~0x1a000ff;
8867 inst
.instruction
|= (0xf << 28);
8868 if (inst
.operands
[1].preind
)
8869 inst
.instruction
|= PRE_INDEX
;
8870 if (!inst
.operands
[1].negative
)
8871 inst
.instruction
|= INDEX_UP
;
8872 if (inst
.operands
[1].writeback
)
8873 inst
.instruction
|= WRITE_BACK
;
8874 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8875 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8876 inst
.instruction
|= inst
.operands
[1].imm
;
8879 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8883 do_iwmmxt_wshufh (void)
8885 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8886 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8887 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8888 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8892 do_iwmmxt_wzero (void)
8894 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8895 inst
.instruction
|= inst
.operands
[0].reg
;
8896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8897 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8901 do_iwmmxt_wrwrwr_or_imm5 (void)
8903 if (inst
.operands
[2].isreg
)
8906 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8907 _("immediate operand requires iWMMXt2"));
8909 if (inst
.operands
[2].imm
== 0)
8911 switch ((inst
.instruction
>> 20) & 0xf)
8917 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8918 inst
.operands
[2].imm
= 16;
8919 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8925 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8926 inst
.operands
[2].imm
= 32;
8927 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8934 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8936 wrn
= (inst
.instruction
>> 16) & 0xf;
8937 inst
.instruction
&= 0xff0fff0f;
8938 inst
.instruction
|= wrn
;
8939 /* Bail out here; the instruction is now assembled. */
8944 /* Map 32 -> 0, etc. */
8945 inst
.operands
[2].imm
&= 0x1f;
8946 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8950 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8951 operations first, then control, shift, and load/store. */
8953 /* Insns like "foo X,Y,Z". */
8956 do_mav_triple (void)
8958 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8959 inst
.instruction
|= inst
.operands
[1].reg
;
8960 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8963 /* Insns like "foo W,X,Y,Z".
8964 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8969 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8970 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8971 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8972 inst
.instruction
|= inst
.operands
[3].reg
;
8975 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8979 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8982 /* Maverick shift immediate instructions.
8983 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8984 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8989 int imm
= inst
.operands
[2].imm
;
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8992 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8994 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8995 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8996 Bit 4 should be 0. */
8997 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8999 inst
.instruction
|= imm
;
9002 /* XScale instructions. Also sorted arithmetic before move. */
9004 /* Xscale multiply-accumulate (argument parse)
9007 MIAxycc acc0,Rm,Rs. */
9012 inst
.instruction
|= inst
.operands
[1].reg
;
9013 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9016 /* Xscale move-accumulator-register (argument parse)
9018 MARcc acc0,RdLo,RdHi. */
9023 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9024 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9027 /* Xscale move-register-accumulator (argument parse)
9029 MRAcc RdLo,RdHi,acc0. */
9034 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9036 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9039 /* Encoding functions relevant only to Thumb. */
9041 /* inst.operands[i] is a shifted-register operand; encode
9042 it into inst.instruction in the format used by Thumb32. */
9045 encode_thumb32_shifted_operand (int i
)
9047 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9048 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9050 constraint (inst
.operands
[i
].immisreg
,
9051 _("shift by register not allowed in thumb mode"));
9052 inst
.instruction
|= inst
.operands
[i
].reg
;
9053 if (shift
== SHIFT_RRX
)
9054 inst
.instruction
|= SHIFT_ROR
<< 4;
9057 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9058 _("expression too complex"));
9060 constraint (value
> 32
9061 || (value
== 32 && (shift
== SHIFT_LSL
9062 || shift
== SHIFT_ROR
)),
9063 _("shift expression is too large"));
9067 else if (value
== 32)
9070 inst
.instruction
|= shift
<< 4;
9071 inst
.instruction
|= (value
& 0x1c) << 10;
9072 inst
.instruction
|= (value
& 0x03) << 6;
9077 /* inst.operands[i] was set up by parse_address. Encode it into a
9078 Thumb32 format load or store instruction. Reject forms that cannot
9079 be used with such instructions. If is_t is true, reject forms that
9080 cannot be used with a T instruction; if is_d is true, reject forms
9081 that cannot be used with a D instruction. If it is a store insn,
9085 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9087 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9089 constraint (!inst
.operands
[i
].isreg
,
9090 _("Instruction does not support =N addresses"));
9092 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9093 if (inst
.operands
[i
].immisreg
)
9095 constraint (is_pc
, BAD_PC_ADDRESSING
);
9096 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9097 constraint (inst
.operands
[i
].negative
,
9098 _("Thumb does not support negative register indexing"));
9099 constraint (inst
.operands
[i
].postind
,
9100 _("Thumb does not support register post-indexing"));
9101 constraint (inst
.operands
[i
].writeback
,
9102 _("Thumb does not support register indexing with writeback"));
9103 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9104 _("Thumb supports only LSL in shifted register indexing"));
9106 inst
.instruction
|= inst
.operands
[i
].imm
;
9107 if (inst
.operands
[i
].shifted
)
9109 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9110 _("expression too complex"));
9111 constraint (inst
.reloc
.exp
.X_add_number
< 0
9112 || inst
.reloc
.exp
.X_add_number
> 3,
9113 _("shift out of range"));
9114 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9116 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9118 else if (inst
.operands
[i
].preind
)
9120 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9121 constraint (is_t
&& inst
.operands
[i
].writeback
,
9122 _("cannot use writeback with this instruction"));
9123 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9124 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9128 inst
.instruction
|= 0x01000000;
9129 if (inst
.operands
[i
].writeback
)
9130 inst
.instruction
|= 0x00200000;
9134 inst
.instruction
|= 0x00000c00;
9135 if (inst
.operands
[i
].writeback
)
9136 inst
.instruction
|= 0x00000100;
9138 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9140 else if (inst
.operands
[i
].postind
)
9142 gas_assert (inst
.operands
[i
].writeback
);
9143 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9144 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9147 inst
.instruction
|= 0x00200000;
9149 inst
.instruction
|= 0x00000900;
9150 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9152 else /* unindexed - only for coprocessor */
9153 inst
.error
= _("instruction does not accept unindexed addressing");
9156 /* Table of Thumb instructions which exist in both 16- and 32-bit
9157 encodings (the latter only in post-V6T2 cores). The index is the
9158 value used in the insns table below. When there is more than one
9159 possible 16-bit encoding for the instruction, this table always
9161 Also contains several pseudo-instructions used during relaxation. */
9162 #define T16_32_TAB \
9163 X(_adc, 4140, eb400000), \
9164 X(_adcs, 4140, eb500000), \
9165 X(_add, 1c00, eb000000), \
9166 X(_adds, 1c00, eb100000), \
9167 X(_addi, 0000, f1000000), \
9168 X(_addis, 0000, f1100000), \
9169 X(_add_pc,000f, f20f0000), \
9170 X(_add_sp,000d, f10d0000), \
9171 X(_adr, 000f, f20f0000), \
9172 X(_and, 4000, ea000000), \
9173 X(_ands, 4000, ea100000), \
9174 X(_asr, 1000, fa40f000), \
9175 X(_asrs, 1000, fa50f000), \
9176 X(_b, e000, f000b000), \
9177 X(_bcond, d000, f0008000), \
9178 X(_bic, 4380, ea200000), \
9179 X(_bics, 4380, ea300000), \
9180 X(_cmn, 42c0, eb100f00), \
9181 X(_cmp, 2800, ebb00f00), \
9182 X(_cpsie, b660, f3af8400), \
9183 X(_cpsid, b670, f3af8600), \
9184 X(_cpy, 4600, ea4f0000), \
9185 X(_dec_sp,80dd, f1ad0d00), \
9186 X(_eor, 4040, ea800000), \
9187 X(_eors, 4040, ea900000), \
9188 X(_inc_sp,00dd, f10d0d00), \
9189 X(_ldmia, c800, e8900000), \
9190 X(_ldr, 6800, f8500000), \
9191 X(_ldrb, 7800, f8100000), \
9192 X(_ldrh, 8800, f8300000), \
9193 X(_ldrsb, 5600, f9100000), \
9194 X(_ldrsh, 5e00, f9300000), \
9195 X(_ldr_pc,4800, f85f0000), \
9196 X(_ldr_pc2,4800, f85f0000), \
9197 X(_ldr_sp,9800, f85d0000), \
9198 X(_lsl, 0000, fa00f000), \
9199 X(_lsls, 0000, fa10f000), \
9200 X(_lsr, 0800, fa20f000), \
9201 X(_lsrs, 0800, fa30f000), \
9202 X(_mov, 2000, ea4f0000), \
9203 X(_movs, 2000, ea5f0000), \
9204 X(_mul, 4340, fb00f000), \
9205 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9206 X(_mvn, 43c0, ea6f0000), \
9207 X(_mvns, 43c0, ea7f0000), \
9208 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9209 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9210 X(_orr, 4300, ea400000), \
9211 X(_orrs, 4300, ea500000), \
9212 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9213 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9214 X(_rev, ba00, fa90f080), \
9215 X(_rev16, ba40, fa90f090), \
9216 X(_revsh, bac0, fa90f0b0), \
9217 X(_ror, 41c0, fa60f000), \
9218 X(_rors, 41c0, fa70f000), \
9219 X(_sbc, 4180, eb600000), \
9220 X(_sbcs, 4180, eb700000), \
9221 X(_stmia, c000, e8800000), \
9222 X(_str, 6000, f8400000), \
9223 X(_strb, 7000, f8000000), \
9224 X(_strh, 8000, f8200000), \
9225 X(_str_sp,9000, f84d0000), \
9226 X(_sub, 1e00, eba00000), \
9227 X(_subs, 1e00, ebb00000), \
9228 X(_subi, 8000, f1a00000), \
9229 X(_subis, 8000, f1b00000), \
9230 X(_sxtb, b240, fa4ff080), \
9231 X(_sxth, b200, fa0ff080), \
9232 X(_tst, 4200, ea100f00), \
9233 X(_uxtb, b2c0, fa5ff080), \
9234 X(_uxth, b280, fa1ff080), \
9235 X(_nop, bf00, f3af8000), \
9236 X(_yield, bf10, f3af8001), \
9237 X(_wfe, bf20, f3af8002), \
9238 X(_wfi, bf30, f3af8003), \
9239 X(_sev, bf40, f3af8004),
9241 /* To catch errors in encoding functions, the codes are all offset by
9242 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9243 as 16-bit instructions. */
9244 #define X(a,b,c) T_MNEM##a
9245 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9248 #define X(a,b,c) 0x##b
9249 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9250 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9253 #define X(a,b,c) 0x##c
9254 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9255 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9256 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9260 /* Thumb instruction encoders, in alphabetical order. */
9265 do_t_add_sub_w (void)
9269 Rd
= inst
.operands
[0].reg
;
9270 Rn
= inst
.operands
[1].reg
;
9272 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9273 is the SP-{plus,minus}-immediate form of the instruction. */
9275 constraint (Rd
== REG_PC
, BAD_PC
);
9277 reject_bad_reg (Rd
);
9279 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9280 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9283 /* Parse an add or subtract instruction. We get here with inst.instruction
9284 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9291 Rd
= inst
.operands
[0].reg
;
9292 Rs
= (inst
.operands
[1].present
9293 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9294 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9297 set_it_insn_type_last ();
9305 flags
= (inst
.instruction
== T_MNEM_adds
9306 || inst
.instruction
== T_MNEM_subs
);
9308 narrow
= !in_it_block ();
9310 narrow
= in_it_block ();
9311 if (!inst
.operands
[2].isreg
)
9315 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9317 add
= (inst
.instruction
== T_MNEM_add
9318 || inst
.instruction
== T_MNEM_adds
);
9320 if (inst
.size_req
!= 4)
9322 /* Attempt to use a narrow opcode, with relaxation if
9324 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9325 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9326 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9327 opcode
= T_MNEM_add_sp
;
9328 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9329 opcode
= T_MNEM_add_pc
;
9330 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9333 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9335 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9339 inst
.instruction
= THUMB_OP16(opcode
);
9340 inst
.instruction
|= (Rd
<< 4) | Rs
;
9341 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9342 if (inst
.size_req
!= 2)
9343 inst
.relax
= opcode
;
9346 constraint (inst
.size_req
== 2, BAD_HIREG
);
9348 if (inst
.size_req
== 4
9349 || (inst
.size_req
!= 2 && !opcode
))
9353 constraint (add
, BAD_PC
);
9354 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9355 _("only SUBS PC, LR, #const allowed"));
9356 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9357 _("expression too complex"));
9358 constraint (inst
.reloc
.exp
.X_add_number
< 0
9359 || inst
.reloc
.exp
.X_add_number
> 0xff,
9360 _("immediate value out of range"));
9361 inst
.instruction
= T2_SUBS_PC_LR
9362 | inst
.reloc
.exp
.X_add_number
;
9363 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9366 else if (Rs
== REG_PC
)
9368 /* Always use addw/subw. */
9369 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9370 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9374 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9375 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9378 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9380 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9382 inst
.instruction
|= Rd
<< 8;
9383 inst
.instruction
|= Rs
<< 16;
9388 Rn
= inst
.operands
[2].reg
;
9389 /* See if we can do this with a 16-bit instruction. */
9390 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9392 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9397 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9398 || inst
.instruction
== T_MNEM_add
)
9401 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9405 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9407 /* Thumb-1 cores (except v6-M) require at least one high
9408 register in a narrow non flag setting add. */
9409 if (Rd
> 7 || Rn
> 7
9410 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9411 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9418 inst
.instruction
= T_OPCODE_ADD_HI
;
9419 inst
.instruction
|= (Rd
& 8) << 4;
9420 inst
.instruction
|= (Rd
& 7);
9421 inst
.instruction
|= Rn
<< 3;
9427 constraint (Rd
== REG_PC
, BAD_PC
);
9428 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9429 constraint (Rs
== REG_PC
, BAD_PC
);
9430 reject_bad_reg (Rn
);
9432 /* If we get here, it can't be done in 16 bits. */
9433 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9434 _("shift must be constant"));
9435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9436 inst
.instruction
|= Rd
<< 8;
9437 inst
.instruction
|= Rs
<< 16;
9438 encode_thumb32_shifted_operand (2);
9443 constraint (inst
.instruction
== T_MNEM_adds
9444 || inst
.instruction
== T_MNEM_subs
,
9447 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9449 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9450 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9453 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9455 inst
.instruction
|= (Rd
<< 4) | Rs
;
9456 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9460 Rn
= inst
.operands
[2].reg
;
9461 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9463 /* We now have Rd, Rs, and Rn set to registers. */
9464 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9466 /* Can't do this for SUB. */
9467 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9468 inst
.instruction
= T_OPCODE_ADD_HI
;
9469 inst
.instruction
|= (Rd
& 8) << 4;
9470 inst
.instruction
|= (Rd
& 7);
9472 inst
.instruction
|= Rn
<< 3;
9474 inst
.instruction
|= Rs
<< 3;
9476 constraint (1, _("dest must overlap one source register"));
9480 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9481 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9482 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9492 Rd
= inst
.operands
[0].reg
;
9493 reject_bad_reg (Rd
);
9495 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9497 /* Defer to section relaxation. */
9498 inst
.relax
= inst
.instruction
;
9499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9500 inst
.instruction
|= Rd
<< 4;
9502 else if (unified_syntax
&& inst
.size_req
!= 2)
9504 /* Generate a 32-bit opcode. */
9505 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9506 inst
.instruction
|= Rd
<< 8;
9507 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9508 inst
.reloc
.pc_rel
= 1;
9512 /* Generate a 16-bit opcode. */
9513 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9514 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9515 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9516 inst
.reloc
.pc_rel
= 1;
9518 inst
.instruction
|= Rd
<< 4;
9522 /* Arithmetic instructions for which there is just one 16-bit
9523 instruction encoding, and it allows only two low registers.
9524 For maximal compatibility with ARM syntax, we allow three register
9525 operands even when Thumb-32 instructions are not available, as long
9526 as the first two are identical. For instance, both "sbc r0,r1" and
9527 "sbc r0,r0,r1" are allowed. */
9533 Rd
= inst
.operands
[0].reg
;
9534 Rs
= (inst
.operands
[1].present
9535 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9536 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9537 Rn
= inst
.operands
[2].reg
;
9539 reject_bad_reg (Rd
);
9540 reject_bad_reg (Rs
);
9541 if (inst
.operands
[2].isreg
)
9542 reject_bad_reg (Rn
);
9546 if (!inst
.operands
[2].isreg
)
9548 /* For an immediate, we always generate a 32-bit opcode;
9549 section relaxation will shrink it later if possible. */
9550 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9551 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9552 inst
.instruction
|= Rd
<< 8;
9553 inst
.instruction
|= Rs
<< 16;
9554 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9560 /* See if we can do this with a 16-bit instruction. */
9561 if (THUMB_SETS_FLAGS (inst
.instruction
))
9562 narrow
= !in_it_block ();
9564 narrow
= in_it_block ();
9566 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9568 if (inst
.operands
[2].shifted
)
9570 if (inst
.size_req
== 4)
9576 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9577 inst
.instruction
|= Rd
;
9578 inst
.instruction
|= Rn
<< 3;
9582 /* If we get here, it can't be done in 16 bits. */
9583 constraint (inst
.operands
[2].shifted
9584 && inst
.operands
[2].immisreg
,
9585 _("shift must be constant"));
9586 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9587 inst
.instruction
|= Rd
<< 8;
9588 inst
.instruction
|= Rs
<< 16;
9589 encode_thumb32_shifted_operand (2);
9594 /* On its face this is a lie - the instruction does set the
9595 flags. However, the only supported mnemonic in this mode
9597 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9599 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9600 _("unshifted register required"));
9601 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9602 constraint (Rd
!= Rs
,
9603 _("dest and source1 must be the same register"));
9605 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9606 inst
.instruction
|= Rd
;
9607 inst
.instruction
|= Rn
<< 3;
9611 /* Similarly, but for instructions where the arithmetic operation is
9612 commutative, so we can allow either of them to be different from
9613 the destination operand in a 16-bit instruction. For instance, all
9614 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9621 Rd
= inst
.operands
[0].reg
;
9622 Rs
= (inst
.operands
[1].present
9623 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9624 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9625 Rn
= inst
.operands
[2].reg
;
9627 reject_bad_reg (Rd
);
9628 reject_bad_reg (Rs
);
9629 if (inst
.operands
[2].isreg
)
9630 reject_bad_reg (Rn
);
9634 if (!inst
.operands
[2].isreg
)
9636 /* For an immediate, we always generate a 32-bit opcode;
9637 section relaxation will shrink it later if possible. */
9638 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9639 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9640 inst
.instruction
|= Rd
<< 8;
9641 inst
.instruction
|= Rs
<< 16;
9642 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9648 /* See if we can do this with a 16-bit instruction. */
9649 if (THUMB_SETS_FLAGS (inst
.instruction
))
9650 narrow
= !in_it_block ();
9652 narrow
= in_it_block ();
9654 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9656 if (inst
.operands
[2].shifted
)
9658 if (inst
.size_req
== 4)
9665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9666 inst
.instruction
|= Rd
;
9667 inst
.instruction
|= Rn
<< 3;
9672 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9673 inst
.instruction
|= Rd
;
9674 inst
.instruction
|= Rs
<< 3;
9679 /* If we get here, it can't be done in 16 bits. */
9680 constraint (inst
.operands
[2].shifted
9681 && inst
.operands
[2].immisreg
,
9682 _("shift must be constant"));
9683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9684 inst
.instruction
|= Rd
<< 8;
9685 inst
.instruction
|= Rs
<< 16;
9686 encode_thumb32_shifted_operand (2);
9691 /* On its face this is a lie - the instruction does set the
9692 flags. However, the only supported mnemonic in this mode
9694 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9696 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9697 _("unshifted register required"));
9698 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9701 inst
.instruction
|= Rd
;
9704 inst
.instruction
|= Rn
<< 3;
9706 inst
.instruction
|= Rs
<< 3;
9708 constraint (1, _("dest must overlap one source register"));
9715 if (inst
.operands
[0].present
)
9717 constraint ((inst
.instruction
& 0xf0) != 0x40
9718 && inst
.operands
[0].imm
> 0xf
9719 && inst
.operands
[0].imm
< 0x0,
9720 _("bad barrier type"));
9721 inst
.instruction
|= inst
.operands
[0].imm
;
9724 inst
.instruction
|= 0xf;
9731 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9732 constraint (msb
> 32, _("bit-field extends past end of register"));
9733 /* The instruction encoding stores the LSB and MSB,
9734 not the LSB and width. */
9735 Rd
= inst
.operands
[0].reg
;
9736 reject_bad_reg (Rd
);
9737 inst
.instruction
|= Rd
<< 8;
9738 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9739 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9740 inst
.instruction
|= msb
- 1;
9749 Rd
= inst
.operands
[0].reg
;
9750 reject_bad_reg (Rd
);
9752 /* #0 in second position is alternative syntax for bfc, which is
9753 the same instruction but with REG_PC in the Rm field. */
9754 if (!inst
.operands
[1].isreg
)
9758 Rn
= inst
.operands
[1].reg
;
9759 reject_bad_reg (Rn
);
9762 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9763 constraint (msb
> 32, _("bit-field extends past end of register"));
9764 /* The instruction encoding stores the LSB and MSB,
9765 not the LSB and width. */
9766 inst
.instruction
|= Rd
<< 8;
9767 inst
.instruction
|= Rn
<< 16;
9768 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9769 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9770 inst
.instruction
|= msb
- 1;
9778 Rd
= inst
.operands
[0].reg
;
9779 Rn
= inst
.operands
[1].reg
;
9781 reject_bad_reg (Rd
);
9782 reject_bad_reg (Rn
);
9784 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9785 _("bit-field extends past end of register"));
9786 inst
.instruction
|= Rd
<< 8;
9787 inst
.instruction
|= Rn
<< 16;
9788 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9789 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9790 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9793 /* ARM V5 Thumb BLX (argument parse)
9794 BLX <target_addr> which is BLX(1)
9795 BLX <Rm> which is BLX(2)
9796 Unfortunately, there are two different opcodes for this mnemonic.
9797 So, the insns[].value is not used, and the code here zaps values
9798 into inst.instruction.
9800 ??? How to take advantage of the additional two bits of displacement
9801 available in Thumb32 mode? Need new relocation? */
9806 set_it_insn_type_last ();
9808 if (inst
.operands
[0].isreg
)
9810 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9811 /* We have a register, so this is BLX(2). */
9812 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9816 /* No register. This must be BLX(1). */
9817 inst
.instruction
= 0xf000e800;
9818 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9830 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9834 /* Conditional branches inside IT blocks are encoded as unconditional
9841 if (cond
!= COND_ALWAYS
)
9842 opcode
= T_MNEM_bcond
;
9844 opcode
= inst
.instruction
;
9847 && (inst
.size_req
== 4
9848 || (inst
.size_req
!= 2
9849 && (inst
.operands
[0].hasreloc
9850 || inst
.reloc
.exp
.X_op
== O_constant
))))
9852 inst
.instruction
= THUMB_OP32(opcode
);
9853 if (cond
== COND_ALWAYS
)
9854 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9857 gas_assert (cond
!= 0xF);
9858 inst
.instruction
|= cond
<< 22;
9859 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9864 inst
.instruction
= THUMB_OP16(opcode
);
9865 if (cond
== COND_ALWAYS
)
9866 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9869 inst
.instruction
|= cond
<< 8;
9870 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9872 /* Allow section relaxation. */
9873 if (unified_syntax
&& inst
.size_req
!= 2)
9874 inst
.relax
= opcode
;
9876 inst
.reloc
.type
= reloc
;
9877 inst
.reloc
.pc_rel
= 1;
9883 constraint (inst
.cond
!= COND_ALWAYS
,
9884 _("instruction is always unconditional"));
9885 if (inst
.operands
[0].present
)
9887 constraint (inst
.operands
[0].imm
> 255,
9888 _("immediate value out of range"));
9889 inst
.instruction
|= inst
.operands
[0].imm
;
9890 set_it_insn_type (NEUTRAL_IT_INSN
);
9895 do_t_branch23 (void)
9897 set_it_insn_type_last ();
9898 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9900 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9901 this file. We used to simply ignore the PLT reloc type here --
9902 the branch encoding is now needed to deal with TLSCALL relocs.
9903 So if we see a PLT reloc now, put it back to how it used to be to
9904 keep the preexisting behaviour. */
9905 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
9906 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9908 #if defined(OBJ_COFF)
9909 /* If the destination of the branch is a defined symbol which does not have
9910 the THUMB_FUNC attribute, then we must be calling a function which has
9911 the (interfacearm) attribute. We look for the Thumb entry point to that
9912 function and change the branch to refer to that function instead. */
9913 if ( inst
.reloc
.exp
.X_op
== O_symbol
9914 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9915 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9916 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9917 inst
.reloc
.exp
.X_add_symbol
=
9918 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9925 set_it_insn_type_last ();
9926 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9927 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9928 should cause the alignment to be checked once it is known. This is
9929 because BX PC only works if the instruction is word aligned. */
9937 set_it_insn_type_last ();
9938 Rm
= inst
.operands
[0].reg
;
9939 reject_bad_reg (Rm
);
9940 inst
.instruction
|= Rm
<< 16;
9949 Rd
= inst
.operands
[0].reg
;
9950 Rm
= inst
.operands
[1].reg
;
9952 reject_bad_reg (Rd
);
9953 reject_bad_reg (Rm
);
9955 inst
.instruction
|= Rd
<< 8;
9956 inst
.instruction
|= Rm
<< 16;
9957 inst
.instruction
|= Rm
;
9963 set_it_insn_type (OUTSIDE_IT_INSN
);
9964 inst
.instruction
|= inst
.operands
[0].imm
;
9970 set_it_insn_type (OUTSIDE_IT_INSN
);
9972 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9973 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9975 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9976 inst
.instruction
= 0xf3af8000;
9977 inst
.instruction
|= imod
<< 9;
9978 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9979 if (inst
.operands
[1].present
)
9980 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9985 && (inst
.operands
[0].imm
& 4),
9986 _("selected processor does not support 'A' form "
9987 "of this instruction"));
9988 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9989 _("Thumb does not support the 2-argument "
9990 "form of this instruction"));
9991 inst
.instruction
|= inst
.operands
[0].imm
;
9995 /* THUMB CPY instruction (argument parse). */
10000 if (inst
.size_req
== 4)
10002 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10003 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10004 inst
.instruction
|= inst
.operands
[1].reg
;
10008 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10009 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10010 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10017 set_it_insn_type (OUTSIDE_IT_INSN
);
10018 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10019 inst
.instruction
|= inst
.operands
[0].reg
;
10020 inst
.reloc
.pc_rel
= 1;
10021 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10027 inst
.instruction
|= inst
.operands
[0].imm
;
10033 unsigned Rd
, Rn
, Rm
;
10035 Rd
= inst
.operands
[0].reg
;
10036 Rn
= (inst
.operands
[1].present
10037 ? inst
.operands
[1].reg
: Rd
);
10038 Rm
= inst
.operands
[2].reg
;
10040 reject_bad_reg (Rd
);
10041 reject_bad_reg (Rn
);
10042 reject_bad_reg (Rm
);
10044 inst
.instruction
|= Rd
<< 8;
10045 inst
.instruction
|= Rn
<< 16;
10046 inst
.instruction
|= Rm
;
10052 if (unified_syntax
&& inst
.size_req
== 4)
10053 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10055 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10061 unsigned int cond
= inst
.operands
[0].imm
;
10063 set_it_insn_type (IT_INSN
);
10064 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10067 /* If the condition is a negative condition, invert the mask. */
10068 if ((cond
& 0x1) == 0x0)
10070 unsigned int mask
= inst
.instruction
& 0x000f;
10072 if ((mask
& 0x7) == 0)
10073 /* no conversion needed */;
10074 else if ((mask
& 0x3) == 0)
10076 else if ((mask
& 0x1) == 0)
10081 inst
.instruction
&= 0xfff0;
10082 inst
.instruction
|= mask
;
10085 inst
.instruction
|= cond
<< 4;
10088 /* Helper function used for both push/pop and ldm/stm. */
10090 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10094 load
= (inst
.instruction
& (1 << 20)) != 0;
10096 if (mask
& (1 << 13))
10097 inst
.error
= _("SP not allowed in register list");
10099 if ((mask
& (1 << base
)) != 0
10101 inst
.error
= _("having the base register in the register list when "
10102 "using write back is UNPREDICTABLE");
10106 if (mask
& (1 << 15))
10108 if (mask
& (1 << 14))
10109 inst
.error
= _("LR and PC should not both be in register list");
10111 set_it_insn_type_last ();
10116 if (mask
& (1 << 15))
10117 inst
.error
= _("PC not allowed in register list");
10120 if ((mask
& (mask
- 1)) == 0)
10122 /* Single register transfers implemented as str/ldr. */
10125 if (inst
.instruction
& (1 << 23))
10126 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10128 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10132 if (inst
.instruction
& (1 << 23))
10133 inst
.instruction
= 0x00800000; /* ia -> [base] */
10135 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10138 inst
.instruction
|= 0xf8400000;
10140 inst
.instruction
|= 0x00100000;
10142 mask
= ffs (mask
) - 1;
10145 else if (writeback
)
10146 inst
.instruction
|= WRITE_BACK
;
10148 inst
.instruction
|= mask
;
10149 inst
.instruction
|= base
<< 16;
10155 /* This really doesn't seem worth it. */
10156 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10157 _("expression too complex"));
10158 constraint (inst
.operands
[1].writeback
,
10159 _("Thumb load/store multiple does not support {reglist}^"));
10161 if (unified_syntax
)
10163 bfd_boolean narrow
;
10167 /* See if we can use a 16-bit instruction. */
10168 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10169 && inst
.size_req
!= 4
10170 && !(inst
.operands
[1].imm
& ~0xff))
10172 mask
= 1 << inst
.operands
[0].reg
;
10174 if (inst
.operands
[0].reg
<= 7)
10176 if (inst
.instruction
== T_MNEM_stmia
10177 ? inst
.operands
[0].writeback
10178 : (inst
.operands
[0].writeback
10179 == !(inst
.operands
[1].imm
& mask
)))
10181 if (inst
.instruction
== T_MNEM_stmia
10182 && (inst
.operands
[1].imm
& mask
)
10183 && (inst
.operands
[1].imm
& (mask
- 1)))
10184 as_warn (_("value stored for r%d is UNKNOWN"),
10185 inst
.operands
[0].reg
);
10187 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10189 inst
.instruction
|= inst
.operands
[1].imm
;
10192 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10194 /* This means 1 register in reg list one of 3 situations:
10195 1. Instruction is stmia, but without writeback.
10196 2. lmdia without writeback, but with Rn not in
10198 3. ldmia with writeback, but with Rn in reglist.
10199 Case 3 is UNPREDICTABLE behaviour, so we handle
10200 case 1 and 2 which can be converted into a 16-bit
10201 str or ldr. The SP cases are handled below. */
10202 unsigned long opcode
;
10203 /* First, record an error for Case 3. */
10204 if (inst
.operands
[1].imm
& mask
10205 && inst
.operands
[0].writeback
)
10207 _("having the base register in the register list when "
10208 "using write back is UNPREDICTABLE");
10210 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10212 inst
.instruction
= THUMB_OP16 (opcode
);
10213 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10214 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10218 else if (inst
.operands
[0] .reg
== REG_SP
)
10220 if (inst
.operands
[0].writeback
)
10223 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10224 ? T_MNEM_push
: T_MNEM_pop
);
10225 inst
.instruction
|= inst
.operands
[1].imm
;
10228 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10231 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10232 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10233 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10241 if (inst
.instruction
< 0xffff)
10242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10244 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10245 inst
.operands
[0].writeback
);
10250 constraint (inst
.operands
[0].reg
> 7
10251 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10252 constraint (inst
.instruction
!= T_MNEM_ldmia
10253 && inst
.instruction
!= T_MNEM_stmia
,
10254 _("Thumb-2 instruction only valid in unified syntax"));
10255 if (inst
.instruction
== T_MNEM_stmia
)
10257 if (!inst
.operands
[0].writeback
)
10258 as_warn (_("this instruction will write back the base register"));
10259 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10260 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10261 as_warn (_("value stored for r%d is UNKNOWN"),
10262 inst
.operands
[0].reg
);
10266 if (!inst
.operands
[0].writeback
10267 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10268 as_warn (_("this instruction will write back the base register"));
10269 else if (inst
.operands
[0].writeback
10270 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10271 as_warn (_("this instruction will not write back the base register"));
10274 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10275 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10276 inst
.instruction
|= inst
.operands
[1].imm
;
10283 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10284 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10285 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10286 || inst
.operands
[1].negative
,
10289 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10292 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10293 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10299 if (!inst
.operands
[1].present
)
10301 constraint (inst
.operands
[0].reg
== REG_LR
,
10302 _("r14 not allowed as first register "
10303 "when second register is omitted"));
10304 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10306 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10310 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10311 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10317 unsigned long opcode
;
10320 if (inst
.operands
[0].isreg
10321 && !inst
.operands
[0].preind
10322 && inst
.operands
[0].reg
== REG_PC
)
10323 set_it_insn_type_last ();
10325 opcode
= inst
.instruction
;
10326 if (unified_syntax
)
10328 if (!inst
.operands
[1].isreg
)
10330 if (opcode
<= 0xffff)
10331 inst
.instruction
= THUMB_OP32 (opcode
);
10332 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10335 if (inst
.operands
[1].isreg
10336 && !inst
.operands
[1].writeback
10337 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10338 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10339 && opcode
<= 0xffff
10340 && inst
.size_req
!= 4)
10342 /* Insn may have a 16-bit form. */
10343 Rn
= inst
.operands
[1].reg
;
10344 if (inst
.operands
[1].immisreg
)
10346 inst
.instruction
= THUMB_OP16 (opcode
);
10348 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10350 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10351 reject_bad_reg (inst
.operands
[1].imm
);
10353 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10354 && opcode
!= T_MNEM_ldrsb
)
10355 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10356 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10363 if (inst
.reloc
.pc_rel
)
10364 opcode
= T_MNEM_ldr_pc2
;
10366 opcode
= T_MNEM_ldr_pc
;
10370 if (opcode
== T_MNEM_ldr
)
10371 opcode
= T_MNEM_ldr_sp
;
10373 opcode
= T_MNEM_str_sp
;
10375 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10379 inst
.instruction
= inst
.operands
[0].reg
;
10380 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10382 inst
.instruction
|= THUMB_OP16 (opcode
);
10383 if (inst
.size_req
== 2)
10384 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10386 inst
.relax
= opcode
;
10390 /* Definitely a 32-bit variant. */
10392 /* Warning for Erratum 752419. */
10393 if (opcode
== T_MNEM_ldr
10394 && inst
.operands
[0].reg
== REG_SP
10395 && inst
.operands
[1].writeback
== 1
10396 && !inst
.operands
[1].immisreg
)
10398 if (no_cpu_selected ()
10399 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10400 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10401 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10402 as_warn (_("This instruction may be unpredictable "
10403 "if executed on M-profile cores "
10404 "with interrupts enabled."));
10407 /* Do some validations regarding addressing modes. */
10408 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10409 && opcode
!= T_MNEM_str
)
10410 reject_bad_reg (inst
.operands
[1].imm
);
10412 inst
.instruction
= THUMB_OP32 (opcode
);
10413 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10414 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10418 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10420 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10422 /* Only [Rn,Rm] is acceptable. */
10423 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10424 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10425 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10426 || inst
.operands
[1].negative
,
10427 _("Thumb does not support this addressing mode"));
10428 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10432 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10433 if (!inst
.operands
[1].isreg
)
10434 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10437 constraint (!inst
.operands
[1].preind
10438 || inst
.operands
[1].shifted
10439 || inst
.operands
[1].writeback
,
10440 _("Thumb does not support this addressing mode"));
10441 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10443 constraint (inst
.instruction
& 0x0600,
10444 _("byte or halfword not valid for base register"));
10445 constraint (inst
.operands
[1].reg
== REG_PC
10446 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10447 _("r15 based store not allowed"));
10448 constraint (inst
.operands
[1].immisreg
,
10449 _("invalid base register for register offset"));
10451 if (inst
.operands
[1].reg
== REG_PC
)
10452 inst
.instruction
= T_OPCODE_LDR_PC
;
10453 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10454 inst
.instruction
= T_OPCODE_LDR_SP
;
10456 inst
.instruction
= T_OPCODE_STR_SP
;
10458 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10459 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10463 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10464 if (!inst
.operands
[1].immisreg
)
10466 /* Immediate offset. */
10467 inst
.instruction
|= inst
.operands
[0].reg
;
10468 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10469 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10473 /* Register offset. */
10474 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10475 constraint (inst
.operands
[1].negative
,
10476 _("Thumb does not support this addressing mode"));
10479 switch (inst
.instruction
)
10481 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10482 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10483 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10484 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10485 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10486 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10487 case 0x5600 /* ldrsb */:
10488 case 0x5e00 /* ldrsh */: break;
10492 inst
.instruction
|= inst
.operands
[0].reg
;
10493 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10494 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10500 if (!inst
.operands
[1].present
)
10502 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10503 constraint (inst
.operands
[0].reg
== REG_LR
,
10504 _("r14 not allowed here"));
10506 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10507 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10508 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10515 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10521 unsigned Rd
, Rn
, Rm
, Ra
;
10523 Rd
= inst
.operands
[0].reg
;
10524 Rn
= inst
.operands
[1].reg
;
10525 Rm
= inst
.operands
[2].reg
;
10526 Ra
= inst
.operands
[3].reg
;
10528 reject_bad_reg (Rd
);
10529 reject_bad_reg (Rn
);
10530 reject_bad_reg (Rm
);
10531 reject_bad_reg (Ra
);
10533 inst
.instruction
|= Rd
<< 8;
10534 inst
.instruction
|= Rn
<< 16;
10535 inst
.instruction
|= Rm
;
10536 inst
.instruction
|= Ra
<< 12;
10542 unsigned RdLo
, RdHi
, Rn
, Rm
;
10544 RdLo
= inst
.operands
[0].reg
;
10545 RdHi
= inst
.operands
[1].reg
;
10546 Rn
= inst
.operands
[2].reg
;
10547 Rm
= inst
.operands
[3].reg
;
10549 reject_bad_reg (RdLo
);
10550 reject_bad_reg (RdHi
);
10551 reject_bad_reg (Rn
);
10552 reject_bad_reg (Rm
);
10554 inst
.instruction
|= RdLo
<< 12;
10555 inst
.instruction
|= RdHi
<< 8;
10556 inst
.instruction
|= Rn
<< 16;
10557 inst
.instruction
|= Rm
;
10561 do_t_mov_cmp (void)
10565 Rn
= inst
.operands
[0].reg
;
10566 Rm
= inst
.operands
[1].reg
;
10569 set_it_insn_type_last ();
10571 if (unified_syntax
)
10573 int r0off
= (inst
.instruction
== T_MNEM_mov
10574 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10575 unsigned long opcode
;
10576 bfd_boolean narrow
;
10577 bfd_boolean low_regs
;
10579 low_regs
= (Rn
<= 7 && Rm
<= 7);
10580 opcode
= inst
.instruction
;
10581 if (in_it_block ())
10582 narrow
= opcode
!= T_MNEM_movs
;
10584 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10585 if (inst
.size_req
== 4
10586 || inst
.operands
[1].shifted
)
10589 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10590 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10591 && !inst
.operands
[1].shifted
10595 inst
.instruction
= T2_SUBS_PC_LR
;
10599 if (opcode
== T_MNEM_cmp
)
10601 constraint (Rn
== REG_PC
, BAD_PC
);
10604 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10606 warn_deprecated_sp (Rm
);
10607 /* R15 was documented as a valid choice for Rm in ARMv6,
10608 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10609 tools reject R15, so we do too. */
10610 constraint (Rm
== REG_PC
, BAD_PC
);
10613 reject_bad_reg (Rm
);
10615 else if (opcode
== T_MNEM_mov
10616 || opcode
== T_MNEM_movs
)
10618 if (inst
.operands
[1].isreg
)
10620 if (opcode
== T_MNEM_movs
)
10622 reject_bad_reg (Rn
);
10623 reject_bad_reg (Rm
);
10627 /* This is mov.n. */
10628 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10629 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10631 as_warn (_("Use of r%u as a source register is "
10632 "deprecated when r%u is the destination "
10633 "register."), Rm
, Rn
);
10638 /* This is mov.w. */
10639 constraint (Rn
== REG_PC
, BAD_PC
);
10640 constraint (Rm
== REG_PC
, BAD_PC
);
10641 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10645 reject_bad_reg (Rn
);
10648 if (!inst
.operands
[1].isreg
)
10650 /* Immediate operand. */
10651 if (!in_it_block () && opcode
== T_MNEM_mov
)
10653 if (low_regs
&& narrow
)
10655 inst
.instruction
= THUMB_OP16 (opcode
);
10656 inst
.instruction
|= Rn
<< 8;
10657 if (inst
.size_req
== 2)
10658 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10660 inst
.relax
= opcode
;
10664 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10665 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10666 inst
.instruction
|= Rn
<< r0off
;
10667 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10670 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10671 && (inst
.instruction
== T_MNEM_mov
10672 || inst
.instruction
== T_MNEM_movs
))
10674 /* Register shifts are encoded as separate shift instructions. */
10675 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10677 if (in_it_block ())
10682 if (inst
.size_req
== 4)
10685 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10691 switch (inst
.operands
[1].shift_kind
)
10694 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10697 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10700 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10703 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10709 inst
.instruction
= opcode
;
10712 inst
.instruction
|= Rn
;
10713 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10718 inst
.instruction
|= CONDS_BIT
;
10720 inst
.instruction
|= Rn
<< 8;
10721 inst
.instruction
|= Rm
<< 16;
10722 inst
.instruction
|= inst
.operands
[1].imm
;
10727 /* Some mov with immediate shift have narrow variants.
10728 Register shifts are handled above. */
10729 if (low_regs
&& inst
.operands
[1].shifted
10730 && (inst
.instruction
== T_MNEM_mov
10731 || inst
.instruction
== T_MNEM_movs
))
10733 if (in_it_block ())
10734 narrow
= (inst
.instruction
== T_MNEM_mov
);
10736 narrow
= (inst
.instruction
== T_MNEM_movs
);
10741 switch (inst
.operands
[1].shift_kind
)
10743 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10744 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10745 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10746 default: narrow
= FALSE
; break;
10752 inst
.instruction
|= Rn
;
10753 inst
.instruction
|= Rm
<< 3;
10754 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10758 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10759 inst
.instruction
|= Rn
<< r0off
;
10760 encode_thumb32_shifted_operand (1);
10764 switch (inst
.instruction
)
10767 inst
.instruction
= T_OPCODE_MOV_HR
;
10768 inst
.instruction
|= (Rn
& 0x8) << 4;
10769 inst
.instruction
|= (Rn
& 0x7);
10770 inst
.instruction
|= Rm
<< 3;
10774 /* We know we have low registers at this point.
10775 Generate LSLS Rd, Rs, #0. */
10776 inst
.instruction
= T_OPCODE_LSL_I
;
10777 inst
.instruction
|= Rn
;
10778 inst
.instruction
|= Rm
<< 3;
10784 inst
.instruction
= T_OPCODE_CMP_LR
;
10785 inst
.instruction
|= Rn
;
10786 inst
.instruction
|= Rm
<< 3;
10790 inst
.instruction
= T_OPCODE_CMP_HR
;
10791 inst
.instruction
|= (Rn
& 0x8) << 4;
10792 inst
.instruction
|= (Rn
& 0x7);
10793 inst
.instruction
|= Rm
<< 3;
10800 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10802 /* PR 10443: Do not silently ignore shifted operands. */
10803 constraint (inst
.operands
[1].shifted
,
10804 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10806 if (inst
.operands
[1].isreg
)
10808 if (Rn
< 8 && Rm
< 8)
10810 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10811 since a MOV instruction produces unpredictable results. */
10812 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10813 inst
.instruction
= T_OPCODE_ADD_I3
;
10815 inst
.instruction
= T_OPCODE_CMP_LR
;
10817 inst
.instruction
|= Rn
;
10818 inst
.instruction
|= Rm
<< 3;
10822 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10823 inst
.instruction
= T_OPCODE_MOV_HR
;
10825 inst
.instruction
= T_OPCODE_CMP_HR
;
10831 constraint (Rn
> 7,
10832 _("only lo regs allowed with immediate"));
10833 inst
.instruction
|= Rn
<< 8;
10834 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10845 top
= (inst
.instruction
& 0x00800000) != 0;
10846 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10848 constraint (top
, _(":lower16: not allowed this instruction"));
10849 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10851 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10853 constraint (!top
, _(":upper16: not allowed this instruction"));
10854 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10857 Rd
= inst
.operands
[0].reg
;
10858 reject_bad_reg (Rd
);
10860 inst
.instruction
|= Rd
<< 8;
10861 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10863 imm
= inst
.reloc
.exp
.X_add_number
;
10864 inst
.instruction
|= (imm
& 0xf000) << 4;
10865 inst
.instruction
|= (imm
& 0x0800) << 15;
10866 inst
.instruction
|= (imm
& 0x0700) << 4;
10867 inst
.instruction
|= (imm
& 0x00ff);
10872 do_t_mvn_tst (void)
10876 Rn
= inst
.operands
[0].reg
;
10877 Rm
= inst
.operands
[1].reg
;
10879 if (inst
.instruction
== T_MNEM_cmp
10880 || inst
.instruction
== T_MNEM_cmn
)
10881 constraint (Rn
== REG_PC
, BAD_PC
);
10883 reject_bad_reg (Rn
);
10884 reject_bad_reg (Rm
);
10886 if (unified_syntax
)
10888 int r0off
= (inst
.instruction
== T_MNEM_mvn
10889 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10890 bfd_boolean narrow
;
10892 if (inst
.size_req
== 4
10893 || inst
.instruction
> 0xffff
10894 || inst
.operands
[1].shifted
10895 || Rn
> 7 || Rm
> 7)
10897 else if (inst
.instruction
== T_MNEM_cmn
)
10899 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10900 narrow
= !in_it_block ();
10902 narrow
= in_it_block ();
10904 if (!inst
.operands
[1].isreg
)
10906 /* For an immediate, we always generate a 32-bit opcode;
10907 section relaxation will shrink it later if possible. */
10908 if (inst
.instruction
< 0xffff)
10909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10910 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10911 inst
.instruction
|= Rn
<< r0off
;
10912 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10916 /* See if we can do this with a 16-bit instruction. */
10919 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10920 inst
.instruction
|= Rn
;
10921 inst
.instruction
|= Rm
<< 3;
10925 constraint (inst
.operands
[1].shifted
10926 && inst
.operands
[1].immisreg
,
10927 _("shift must be constant"));
10928 if (inst
.instruction
< 0xffff)
10929 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10930 inst
.instruction
|= Rn
<< r0off
;
10931 encode_thumb32_shifted_operand (1);
10937 constraint (inst
.instruction
> 0xffff
10938 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10939 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10940 _("unshifted register required"));
10941 constraint (Rn
> 7 || Rm
> 7,
10944 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10945 inst
.instruction
|= Rn
;
10946 inst
.instruction
|= Rm
<< 3;
10955 if (do_vfp_nsyn_mrs () == SUCCESS
)
10958 Rd
= inst
.operands
[0].reg
;
10959 reject_bad_reg (Rd
);
10960 inst
.instruction
|= Rd
<< 8;
10962 if (inst
.operands
[1].isreg
)
10964 unsigned br
= inst
.operands
[1].reg
;
10965 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
10966 as_bad (_("bad register for mrs"));
10968 inst
.instruction
|= br
& (0xf << 16);
10969 inst
.instruction
|= (br
& 0x300) >> 4;
10970 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
10974 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10976 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
10977 constraint (flags
!= 0, _("selected processor does not support "
10978 "requested special purpose register"));
10980 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
10982 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10983 _("'APSR', 'CPSR' or 'SPSR' expected"));
10985 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10986 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10987 inst
.instruction
|= 0xf0000;
10997 if (do_vfp_nsyn_msr () == SUCCESS
)
11000 constraint (!inst
.operands
[1].isreg
,
11001 _("Thumb encoding does not support an immediate here"));
11003 if (inst
.operands
[0].isreg
)
11004 flags
= (int)(inst
.operands
[0].reg
);
11006 flags
= inst
.operands
[0].imm
;
11008 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11010 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11012 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11013 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11014 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11016 _("selected processor does not support requested special "
11017 "purpose register"));
11020 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11021 "requested special purpose register"));
11023 Rn
= inst
.operands
[1].reg
;
11024 reject_bad_reg (Rn
);
11026 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11027 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11028 inst
.instruction
|= (flags
& 0x300) >> 4;
11029 inst
.instruction
|= (flags
& 0xff);
11030 inst
.instruction
|= Rn
<< 16;
11036 bfd_boolean narrow
;
11037 unsigned Rd
, Rn
, Rm
;
11039 if (!inst
.operands
[2].present
)
11040 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11042 Rd
= inst
.operands
[0].reg
;
11043 Rn
= inst
.operands
[1].reg
;
11044 Rm
= inst
.operands
[2].reg
;
11046 if (unified_syntax
)
11048 if (inst
.size_req
== 4
11054 else if (inst
.instruction
== T_MNEM_muls
)
11055 narrow
= !in_it_block ();
11057 narrow
= in_it_block ();
11061 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11062 constraint (Rn
> 7 || Rm
> 7,
11069 /* 16-bit MULS/Conditional MUL. */
11070 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11071 inst
.instruction
|= Rd
;
11074 inst
.instruction
|= Rm
<< 3;
11076 inst
.instruction
|= Rn
<< 3;
11078 constraint (1, _("dest must overlap one source register"));
11082 constraint (inst
.instruction
!= T_MNEM_mul
,
11083 _("Thumb-2 MUL must not set flags"));
11085 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11086 inst
.instruction
|= Rd
<< 8;
11087 inst
.instruction
|= Rn
<< 16;
11088 inst
.instruction
|= Rm
<< 0;
11090 reject_bad_reg (Rd
);
11091 reject_bad_reg (Rn
);
11092 reject_bad_reg (Rm
);
11099 unsigned RdLo
, RdHi
, Rn
, Rm
;
11101 RdLo
= inst
.operands
[0].reg
;
11102 RdHi
= inst
.operands
[1].reg
;
11103 Rn
= inst
.operands
[2].reg
;
11104 Rm
= inst
.operands
[3].reg
;
11106 reject_bad_reg (RdLo
);
11107 reject_bad_reg (RdHi
);
11108 reject_bad_reg (Rn
);
11109 reject_bad_reg (Rm
);
11111 inst
.instruction
|= RdLo
<< 12;
11112 inst
.instruction
|= RdHi
<< 8;
11113 inst
.instruction
|= Rn
<< 16;
11114 inst
.instruction
|= Rm
;
11117 as_tsktsk (_("rdhi and rdlo must be different"));
11123 set_it_insn_type (NEUTRAL_IT_INSN
);
11125 if (unified_syntax
)
11127 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11129 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11130 inst
.instruction
|= inst
.operands
[0].imm
;
11134 /* PR9722: Check for Thumb2 availability before
11135 generating a thumb2 nop instruction. */
11136 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11138 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11139 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11142 inst
.instruction
= 0x46c0;
11147 constraint (inst
.operands
[0].present
,
11148 _("Thumb does not support NOP with hints"));
11149 inst
.instruction
= 0x46c0;
11156 if (unified_syntax
)
11158 bfd_boolean narrow
;
11160 if (THUMB_SETS_FLAGS (inst
.instruction
))
11161 narrow
= !in_it_block ();
11163 narrow
= in_it_block ();
11164 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11166 if (inst
.size_req
== 4)
11171 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11172 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11177 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11178 inst
.instruction
|= inst
.operands
[0].reg
;
11179 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11184 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11186 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11188 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11189 inst
.instruction
|= inst
.operands
[0].reg
;
11190 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11199 Rd
= inst
.operands
[0].reg
;
11200 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11202 reject_bad_reg (Rd
);
11203 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11204 reject_bad_reg (Rn
);
11206 inst
.instruction
|= Rd
<< 8;
11207 inst
.instruction
|= Rn
<< 16;
11209 if (!inst
.operands
[2].isreg
)
11211 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11212 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11218 Rm
= inst
.operands
[2].reg
;
11219 reject_bad_reg (Rm
);
11221 constraint (inst
.operands
[2].shifted
11222 && inst
.operands
[2].immisreg
,
11223 _("shift must be constant"));
11224 encode_thumb32_shifted_operand (2);
11231 unsigned Rd
, Rn
, Rm
;
11233 Rd
= inst
.operands
[0].reg
;
11234 Rn
= inst
.operands
[1].reg
;
11235 Rm
= inst
.operands
[2].reg
;
11237 reject_bad_reg (Rd
);
11238 reject_bad_reg (Rn
);
11239 reject_bad_reg (Rm
);
11241 inst
.instruction
|= Rd
<< 8;
11242 inst
.instruction
|= Rn
<< 16;
11243 inst
.instruction
|= Rm
;
11244 if (inst
.operands
[3].present
)
11246 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11247 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11248 _("expression too complex"));
11249 inst
.instruction
|= (val
& 0x1c) << 10;
11250 inst
.instruction
|= (val
& 0x03) << 6;
11257 if (!inst
.operands
[3].present
)
11261 inst
.instruction
&= ~0x00000020;
11263 /* PR 10168. Swap the Rm and Rn registers. */
11264 Rtmp
= inst
.operands
[1].reg
;
11265 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11266 inst
.operands
[2].reg
= Rtmp
;
11274 if (inst
.operands
[0].immisreg
)
11275 reject_bad_reg (inst
.operands
[0].imm
);
11277 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11281 do_t_push_pop (void)
11285 constraint (inst
.operands
[0].writeback
,
11286 _("push/pop do not support {reglist}^"));
11287 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11288 _("expression too complex"));
11290 mask
= inst
.operands
[0].imm
;
11291 if ((mask
& ~0xff) == 0)
11292 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11293 else if ((inst
.instruction
== T_MNEM_push
11294 && (mask
& ~0xff) == 1 << REG_LR
)
11295 || (inst
.instruction
== T_MNEM_pop
11296 && (mask
& ~0xff) == 1 << REG_PC
))
11298 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11299 inst
.instruction
|= THUMB_PP_PC_LR
;
11300 inst
.instruction
|= mask
& 0xff;
11302 else if (unified_syntax
)
11304 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11305 encode_thumb2_ldmstm (13, mask
, TRUE
);
11309 inst
.error
= _("invalid register list to push/pop instruction");
11319 Rd
= inst
.operands
[0].reg
;
11320 Rm
= inst
.operands
[1].reg
;
11322 reject_bad_reg (Rd
);
11323 reject_bad_reg (Rm
);
11325 inst
.instruction
|= Rd
<< 8;
11326 inst
.instruction
|= Rm
<< 16;
11327 inst
.instruction
|= Rm
;
11335 Rd
= inst
.operands
[0].reg
;
11336 Rm
= inst
.operands
[1].reg
;
11338 reject_bad_reg (Rd
);
11339 reject_bad_reg (Rm
);
11341 if (Rd
<= 7 && Rm
<= 7
11342 && inst
.size_req
!= 4)
11344 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11345 inst
.instruction
|= Rd
;
11346 inst
.instruction
|= Rm
<< 3;
11348 else if (unified_syntax
)
11350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11351 inst
.instruction
|= Rd
<< 8;
11352 inst
.instruction
|= Rm
<< 16;
11353 inst
.instruction
|= Rm
;
11356 inst
.error
= BAD_HIREG
;
11364 Rd
= inst
.operands
[0].reg
;
11365 Rm
= inst
.operands
[1].reg
;
11367 reject_bad_reg (Rd
);
11368 reject_bad_reg (Rm
);
11370 inst
.instruction
|= Rd
<< 8;
11371 inst
.instruction
|= Rm
;
11379 Rd
= inst
.operands
[0].reg
;
11380 Rs
= (inst
.operands
[1].present
11381 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11382 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11384 reject_bad_reg (Rd
);
11385 reject_bad_reg (Rs
);
11386 if (inst
.operands
[2].isreg
)
11387 reject_bad_reg (inst
.operands
[2].reg
);
11389 inst
.instruction
|= Rd
<< 8;
11390 inst
.instruction
|= Rs
<< 16;
11391 if (!inst
.operands
[2].isreg
)
11393 bfd_boolean narrow
;
11395 if ((inst
.instruction
& 0x00100000) != 0)
11396 narrow
= !in_it_block ();
11398 narrow
= in_it_block ();
11400 if (Rd
> 7 || Rs
> 7)
11403 if (inst
.size_req
== 4 || !unified_syntax
)
11406 if (inst
.reloc
.exp
.X_op
!= O_constant
11407 || inst
.reloc
.exp
.X_add_number
!= 0)
11410 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11411 relaxation, but it doesn't seem worth the hassle. */
11414 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11415 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11416 inst
.instruction
|= Rs
<< 3;
11417 inst
.instruction
|= Rd
;
11421 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11422 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11426 encode_thumb32_shifted_operand (2);
11432 set_it_insn_type (OUTSIDE_IT_INSN
);
11433 if (inst
.operands
[0].imm
)
11434 inst
.instruction
|= 0x8;
11440 if (!inst
.operands
[1].present
)
11441 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11443 if (unified_syntax
)
11445 bfd_boolean narrow
;
11448 switch (inst
.instruction
)
11451 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11453 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11455 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11457 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11461 if (THUMB_SETS_FLAGS (inst
.instruction
))
11462 narrow
= !in_it_block ();
11464 narrow
= in_it_block ();
11465 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11467 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11469 if (inst
.operands
[2].isreg
11470 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11471 || inst
.operands
[2].reg
> 7))
11473 if (inst
.size_req
== 4)
11476 reject_bad_reg (inst
.operands
[0].reg
);
11477 reject_bad_reg (inst
.operands
[1].reg
);
11481 if (inst
.operands
[2].isreg
)
11483 reject_bad_reg (inst
.operands
[2].reg
);
11484 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11485 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11486 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11487 inst
.instruction
|= inst
.operands
[2].reg
;
11491 inst
.operands
[1].shifted
= 1;
11492 inst
.operands
[1].shift_kind
= shift_kind
;
11493 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11494 ? T_MNEM_movs
: T_MNEM_mov
);
11495 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11496 encode_thumb32_shifted_operand (1);
11497 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11498 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11503 if (inst
.operands
[2].isreg
)
11505 switch (shift_kind
)
11507 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11508 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11509 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11510 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11514 inst
.instruction
|= inst
.operands
[0].reg
;
11515 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11519 switch (shift_kind
)
11521 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11522 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11523 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11526 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11527 inst
.instruction
|= inst
.operands
[0].reg
;
11528 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11534 constraint (inst
.operands
[0].reg
> 7
11535 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11536 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11538 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11540 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11541 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11542 _("source1 and dest must be same register"));
11544 switch (inst
.instruction
)
11546 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11547 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11548 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11549 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11553 inst
.instruction
|= inst
.operands
[0].reg
;
11554 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11558 switch (inst
.instruction
)
11560 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11561 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11562 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11563 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11566 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11567 inst
.instruction
|= inst
.operands
[0].reg
;
11568 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11576 unsigned Rd
, Rn
, Rm
;
11578 Rd
= inst
.operands
[0].reg
;
11579 Rn
= inst
.operands
[1].reg
;
11580 Rm
= inst
.operands
[2].reg
;
11582 reject_bad_reg (Rd
);
11583 reject_bad_reg (Rn
);
11584 reject_bad_reg (Rm
);
11586 inst
.instruction
|= Rd
<< 8;
11587 inst
.instruction
|= Rn
<< 16;
11588 inst
.instruction
|= Rm
;
11594 unsigned Rd
, Rn
, Rm
;
11596 Rd
= inst
.operands
[0].reg
;
11597 Rm
= inst
.operands
[1].reg
;
11598 Rn
= inst
.operands
[2].reg
;
11600 reject_bad_reg (Rd
);
11601 reject_bad_reg (Rn
);
11602 reject_bad_reg (Rm
);
11604 inst
.instruction
|= Rd
<< 8;
11605 inst
.instruction
|= Rn
<< 16;
11606 inst
.instruction
|= Rm
;
11612 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11613 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11614 _("SMC is not permitted on this architecture"));
11615 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11616 _("expression too complex"));
11617 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11618 inst
.instruction
|= (value
& 0xf000) >> 12;
11619 inst
.instruction
|= (value
& 0x0ff0);
11620 inst
.instruction
|= (value
& 0x000f) << 16;
11626 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11628 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11629 inst
.instruction
|= (value
& 0x0fff);
11630 inst
.instruction
|= (value
& 0xf000) << 4;
11634 do_t_ssat_usat (int bias
)
11638 Rd
= inst
.operands
[0].reg
;
11639 Rn
= inst
.operands
[2].reg
;
11641 reject_bad_reg (Rd
);
11642 reject_bad_reg (Rn
);
11644 inst
.instruction
|= Rd
<< 8;
11645 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11646 inst
.instruction
|= Rn
<< 16;
11648 if (inst
.operands
[3].present
)
11650 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11652 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11654 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11655 _("expression too complex"));
11657 if (shift_amount
!= 0)
11659 constraint (shift_amount
> 31,
11660 _("shift expression is too large"));
11662 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11663 inst
.instruction
|= 0x00200000; /* sh bit. */
11665 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11666 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11674 do_t_ssat_usat (1);
11682 Rd
= inst
.operands
[0].reg
;
11683 Rn
= inst
.operands
[2].reg
;
11685 reject_bad_reg (Rd
);
11686 reject_bad_reg (Rn
);
11688 inst
.instruction
|= Rd
<< 8;
11689 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11690 inst
.instruction
|= Rn
<< 16;
11696 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11697 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11698 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11699 || inst
.operands
[2].negative
,
11702 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11704 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11705 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11706 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11707 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11713 if (!inst
.operands
[2].present
)
11714 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11716 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11717 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11718 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11721 inst
.instruction
|= inst
.operands
[0].reg
;
11722 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11723 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11724 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11730 unsigned Rd
, Rn
, Rm
;
11732 Rd
= inst
.operands
[0].reg
;
11733 Rn
= inst
.operands
[1].reg
;
11734 Rm
= inst
.operands
[2].reg
;
11736 reject_bad_reg (Rd
);
11737 reject_bad_reg (Rn
);
11738 reject_bad_reg (Rm
);
11740 inst
.instruction
|= Rd
<< 8;
11741 inst
.instruction
|= Rn
<< 16;
11742 inst
.instruction
|= Rm
;
11743 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11751 Rd
= inst
.operands
[0].reg
;
11752 Rm
= inst
.operands
[1].reg
;
11754 reject_bad_reg (Rd
);
11755 reject_bad_reg (Rm
);
11757 if (inst
.instruction
<= 0xffff
11758 && inst
.size_req
!= 4
11759 && Rd
<= 7 && Rm
<= 7
11760 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11763 inst
.instruction
|= Rd
;
11764 inst
.instruction
|= Rm
<< 3;
11766 else if (unified_syntax
)
11768 if (inst
.instruction
<= 0xffff)
11769 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11770 inst
.instruction
|= Rd
<< 8;
11771 inst
.instruction
|= Rm
;
11772 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11776 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11777 _("Thumb encoding does not support rotation"));
11778 constraint (1, BAD_HIREG
);
11785 /* We have to do the following check manually as ARM_EXT_OS only applies
11787 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11789 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11790 /* This only applies to the v6m howver, not later architectures. */
11791 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11792 as_bad (_("SVC is not permitted on this architecture"));
11793 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11796 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11805 half
= (inst
.instruction
& 0x10) != 0;
11806 set_it_insn_type_last ();
11807 constraint (inst
.operands
[0].immisreg
,
11808 _("instruction requires register index"));
11810 Rn
= inst
.operands
[0].reg
;
11811 Rm
= inst
.operands
[0].imm
;
11813 constraint (Rn
== REG_SP
, BAD_SP
);
11814 reject_bad_reg (Rm
);
11816 constraint (!half
&& inst
.operands
[0].shifted
,
11817 _("instruction does not allow shifted index"));
11818 inst
.instruction
|= (Rn
<< 16) | Rm
;
11824 do_t_ssat_usat (0);
11832 Rd
= inst
.operands
[0].reg
;
11833 Rn
= inst
.operands
[2].reg
;
11835 reject_bad_reg (Rd
);
11836 reject_bad_reg (Rn
);
11838 inst
.instruction
|= Rd
<< 8;
11839 inst
.instruction
|= inst
.operands
[1].imm
;
11840 inst
.instruction
|= Rn
<< 16;
11843 /* Neon instruction encoder helpers. */
11845 /* Encodings for the different types for various Neon opcodes. */
11847 /* An "invalid" code for the following tables. */
11850 struct neon_tab_entry
11853 unsigned float_or_poly
;
11854 unsigned scalar_or_imm
;
11857 /* Map overloaded Neon opcodes to their respective encodings. */
11858 #define NEON_ENC_TAB \
11859 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11860 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11861 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11862 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11863 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11864 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11865 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11866 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11867 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11868 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11869 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11870 /* Register variants of the following two instructions are encoded as
11871 vcge / vcgt with the operands reversed. */ \
11872 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11873 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11874 X(vfma, N_INV, 0x0000c10, N_INV), \
11875 X(vfms, N_INV, 0x0200c10, N_INV), \
11876 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11877 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11878 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11879 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11880 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11881 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11882 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11883 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11884 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11885 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11886 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11887 X(vshl, 0x0000400, N_INV, 0x0800510), \
11888 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11889 X(vand, 0x0000110, N_INV, 0x0800030), \
11890 X(vbic, 0x0100110, N_INV, 0x0800030), \
11891 X(veor, 0x1000110, N_INV, N_INV), \
11892 X(vorn, 0x0300110, N_INV, 0x0800010), \
11893 X(vorr, 0x0200110, N_INV, 0x0800010), \
11894 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11895 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11896 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11897 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11898 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11899 X(vst1, 0x0000000, 0x0800000, N_INV), \
11900 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11901 X(vst2, 0x0000100, 0x0800100, N_INV), \
11902 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11903 X(vst3, 0x0000200, 0x0800200, N_INV), \
11904 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11905 X(vst4, 0x0000300, 0x0800300, N_INV), \
11906 X(vmovn, 0x1b20200, N_INV, N_INV), \
11907 X(vtrn, 0x1b20080, N_INV, N_INV), \
11908 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11909 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11910 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11911 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11912 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11913 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11914 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11915 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11916 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11917 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11918 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11922 #define X(OPC,I,F,S) N_MNEM_##OPC
11927 static const struct neon_tab_entry neon_enc_tab
[] =
11929 #define X(OPC,I,F,S) { (I), (F), (S) }
11934 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11935 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11936 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11937 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11938 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11939 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11940 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11941 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11942 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11943 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11944 #define NEON_ENC_SINGLE_(X) \
11945 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11946 #define NEON_ENC_DOUBLE_(X) \
11947 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11949 #define NEON_ENCODE(type, inst) \
11952 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11953 inst.is_neon = 1; \
11957 #define check_neon_suffixes \
11960 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11962 as_bad (_("invalid neon suffix for non neon instruction")); \
11968 /* Define shapes for instruction operands. The following mnemonic characters
11969 are used in this table:
11971 F - VFP S<n> register
11972 D - Neon D<n> register
11973 Q - Neon Q<n> register
11977 L - D<n> register list
11979 This table is used to generate various data:
11980 - enumerations of the form NS_DDR to be used as arguments to
11982 - a table classifying shapes into single, double, quad, mixed.
11983 - a table used to drive neon_select_shape. */
11985 #define NEON_SHAPE_DEF \
11986 X(3, (D, D, D), DOUBLE), \
11987 X(3, (Q, Q, Q), QUAD), \
11988 X(3, (D, D, I), DOUBLE), \
11989 X(3, (Q, Q, I), QUAD), \
11990 X(3, (D, D, S), DOUBLE), \
11991 X(3, (Q, Q, S), QUAD), \
11992 X(2, (D, D), DOUBLE), \
11993 X(2, (Q, Q), QUAD), \
11994 X(2, (D, S), DOUBLE), \
11995 X(2, (Q, S), QUAD), \
11996 X(2, (D, R), DOUBLE), \
11997 X(2, (Q, R), QUAD), \
11998 X(2, (D, I), DOUBLE), \
11999 X(2, (Q, I), QUAD), \
12000 X(3, (D, L, D), DOUBLE), \
12001 X(2, (D, Q), MIXED), \
12002 X(2, (Q, D), MIXED), \
12003 X(3, (D, Q, I), MIXED), \
12004 X(3, (Q, D, I), MIXED), \
12005 X(3, (Q, D, D), MIXED), \
12006 X(3, (D, Q, Q), MIXED), \
12007 X(3, (Q, Q, D), MIXED), \
12008 X(3, (Q, D, S), MIXED), \
12009 X(3, (D, Q, S), MIXED), \
12010 X(4, (D, D, D, I), DOUBLE), \
12011 X(4, (Q, Q, Q, I), QUAD), \
12012 X(2, (F, F), SINGLE), \
12013 X(3, (F, F, F), SINGLE), \
12014 X(2, (F, I), SINGLE), \
12015 X(2, (F, D), MIXED), \
12016 X(2, (D, F), MIXED), \
12017 X(3, (F, F, I), MIXED), \
12018 X(4, (R, R, F, F), SINGLE), \
12019 X(4, (F, F, R, R), SINGLE), \
12020 X(3, (D, R, R), DOUBLE), \
12021 X(3, (R, R, D), DOUBLE), \
12022 X(2, (S, R), SINGLE), \
12023 X(2, (R, S), SINGLE), \
12024 X(2, (F, R), SINGLE), \
12025 X(2, (R, F), SINGLE)
12027 #define S2(A,B) NS_##A##B
12028 #define S3(A,B,C) NS_##A##B##C
12029 #define S4(A,B,C,D) NS_##A##B##C##D
12031 #define X(N, L, C) S##N L
12044 enum neon_shape_class
12052 #define X(N, L, C) SC_##C
12054 static enum neon_shape_class neon_shape_class
[] =
12072 /* Register widths of above. */
12073 static unsigned neon_shape_el_size
[] =
12084 struct neon_shape_info
12087 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12090 #define S2(A,B) { SE_##A, SE_##B }
12091 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12092 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12094 #define X(N, L, C) { N, S##N L }
12096 static struct neon_shape_info neon_shape_tab
[] =
12106 /* Bit masks used in type checking given instructions.
12107 'N_EQK' means the type must be the same as (or based on in some way) the key
12108 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12109 set, various other bits can be set as well in order to modify the meaning of
12110 the type constraint. */
12112 enum neon_type_mask
12135 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12136 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12137 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12138 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12139 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12140 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12141 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12142 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12143 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12144 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12146 N_MAX_NONSPECIAL
= N_F64
12149 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12151 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12152 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12153 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12154 #define N_SUF_32 (N_SU_32 | N_F32)
12155 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12156 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12158 /* Pass this as the first type argument to neon_check_type to ignore types
12160 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12162 /* Select a "shape" for the current instruction (describing register types or
12163 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12164 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12165 function of operand parsing, so this function doesn't need to be called.
12166 Shapes should be listed in order of decreasing length. */
12168 static enum neon_shape
12169 neon_select_shape (enum neon_shape shape
, ...)
12172 enum neon_shape first_shape
= shape
;
12174 /* Fix missing optional operands. FIXME: we don't know at this point how
12175 many arguments we should have, so this makes the assumption that we have
12176 > 1. This is true of all current Neon opcodes, I think, but may not be
12177 true in the future. */
12178 if (!inst
.operands
[1].present
)
12179 inst
.operands
[1] = inst
.operands
[0];
12181 va_start (ap
, shape
);
12183 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12188 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12190 if (!inst
.operands
[j
].present
)
12196 switch (neon_shape_tab
[shape
].el
[j
])
12199 if (!(inst
.operands
[j
].isreg
12200 && inst
.operands
[j
].isvec
12201 && inst
.operands
[j
].issingle
12202 && !inst
.operands
[j
].isquad
))
12207 if (!(inst
.operands
[j
].isreg
12208 && inst
.operands
[j
].isvec
12209 && !inst
.operands
[j
].isquad
12210 && !inst
.operands
[j
].issingle
))
12215 if (!(inst
.operands
[j
].isreg
12216 && !inst
.operands
[j
].isvec
))
12221 if (!(inst
.operands
[j
].isreg
12222 && inst
.operands
[j
].isvec
12223 && inst
.operands
[j
].isquad
12224 && !inst
.operands
[j
].issingle
))
12229 if (!(!inst
.operands
[j
].isreg
12230 && !inst
.operands
[j
].isscalar
))
12235 if (!(!inst
.operands
[j
].isreg
12236 && inst
.operands
[j
].isscalar
))
12252 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12253 first_error (_("invalid instruction shape"));
12258 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12259 means the Q bit should be set). */
12262 neon_quad (enum neon_shape shape
)
12264 return neon_shape_class
[shape
] == SC_QUAD
;
12268 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12271 /* Allow modification to be made to types which are constrained to be
12272 based on the key element, based on bits set alongside N_EQK. */
12273 if ((typebits
& N_EQK
) != 0)
12275 if ((typebits
& N_HLF
) != 0)
12277 else if ((typebits
& N_DBL
) != 0)
12279 if ((typebits
& N_SGN
) != 0)
12280 *g_type
= NT_signed
;
12281 else if ((typebits
& N_UNS
) != 0)
12282 *g_type
= NT_unsigned
;
12283 else if ((typebits
& N_INT
) != 0)
12284 *g_type
= NT_integer
;
12285 else if ((typebits
& N_FLT
) != 0)
12286 *g_type
= NT_float
;
12287 else if ((typebits
& N_SIZ
) != 0)
12288 *g_type
= NT_untyped
;
12292 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12293 operand type, i.e. the single type specified in a Neon instruction when it
12294 is the only one given. */
12296 static struct neon_type_el
12297 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12299 struct neon_type_el dest
= *key
;
12301 gas_assert ((thisarg
& N_EQK
) != 0);
12303 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12308 /* Convert Neon type and size into compact bitmask representation. */
12310 static enum neon_type_mask
12311 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12318 case 8: return N_8
;
12319 case 16: return N_16
;
12320 case 32: return N_32
;
12321 case 64: return N_64
;
12329 case 8: return N_I8
;
12330 case 16: return N_I16
;
12331 case 32: return N_I32
;
12332 case 64: return N_I64
;
12340 case 16: return N_F16
;
12341 case 32: return N_F32
;
12342 case 64: return N_F64
;
12350 case 8: return N_P8
;
12351 case 16: return N_P16
;
12359 case 8: return N_S8
;
12360 case 16: return N_S16
;
12361 case 32: return N_S32
;
12362 case 64: return N_S64
;
12370 case 8: return N_U8
;
12371 case 16: return N_U16
;
12372 case 32: return N_U32
;
12373 case 64: return N_U64
;
12384 /* Convert compact Neon bitmask type representation to a type and size. Only
12385 handles the case where a single bit is set in the mask. */
12388 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12389 enum neon_type_mask mask
)
12391 if ((mask
& N_EQK
) != 0)
12394 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12396 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12398 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12400 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12405 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12407 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12408 *type
= NT_unsigned
;
12409 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12410 *type
= NT_integer
;
12411 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12412 *type
= NT_untyped
;
12413 else if ((mask
& (N_P8
| N_P16
)) != 0)
12415 else if ((mask
& (N_F32
| N_F64
)) != 0)
12423 /* Modify a bitmask of allowed types. This is only needed for type
12427 modify_types_allowed (unsigned allowed
, unsigned mods
)
12430 enum neon_el_type type
;
12436 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12438 if (el_type_of_type_chk (&type
, &size
,
12439 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12441 neon_modify_type_size (mods
, &type
, &size
);
12442 destmask
|= type_chk_of_el_type (type
, size
);
12449 /* Check type and return type classification.
12450 The manual states (paraphrase): If one datatype is given, it indicates the
12452 - the second operand, if there is one
12453 - the operand, if there is no second operand
12454 - the result, if there are no operands.
12455 This isn't quite good enough though, so we use a concept of a "key" datatype
12456 which is set on a per-instruction basis, which is the one which matters when
12457 only one data type is written.
12458 Note: this function has side-effects (e.g. filling in missing operands). All
12459 Neon instructions should call it before performing bit encoding. */
12461 static struct neon_type_el
12462 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12465 unsigned i
, pass
, key_el
= 0;
12466 unsigned types
[NEON_MAX_TYPE_ELS
];
12467 enum neon_el_type k_type
= NT_invtype
;
12468 unsigned k_size
= -1u;
12469 struct neon_type_el badtype
= {NT_invtype
, -1};
12470 unsigned key_allowed
= 0;
12472 /* Optional registers in Neon instructions are always (not) in operand 1.
12473 Fill in the missing operand here, if it was omitted. */
12474 if (els
> 1 && !inst
.operands
[1].present
)
12475 inst
.operands
[1] = inst
.operands
[0];
12477 /* Suck up all the varargs. */
12479 for (i
= 0; i
< els
; i
++)
12481 unsigned thisarg
= va_arg (ap
, unsigned);
12482 if (thisarg
== N_IGNORE_TYPE
)
12487 types
[i
] = thisarg
;
12488 if ((thisarg
& N_KEY
) != 0)
12493 if (inst
.vectype
.elems
> 0)
12494 for (i
= 0; i
< els
; i
++)
12495 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12497 first_error (_("types specified in both the mnemonic and operands"));
12501 /* Duplicate inst.vectype elements here as necessary.
12502 FIXME: No idea if this is exactly the same as the ARM assembler,
12503 particularly when an insn takes one register and one non-register
12505 if (inst
.vectype
.elems
== 1 && els
> 1)
12508 inst
.vectype
.elems
= els
;
12509 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12510 for (j
= 0; j
< els
; j
++)
12512 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12515 else if (inst
.vectype
.elems
== 0 && els
> 0)
12518 /* No types were given after the mnemonic, so look for types specified
12519 after each operand. We allow some flexibility here; as long as the
12520 "key" operand has a type, we can infer the others. */
12521 for (j
= 0; j
< els
; j
++)
12522 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12523 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12525 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12527 for (j
= 0; j
< els
; j
++)
12528 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12529 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12534 first_error (_("operand types can't be inferred"));
12538 else if (inst
.vectype
.elems
!= els
)
12540 first_error (_("type specifier has the wrong number of parts"));
12544 for (pass
= 0; pass
< 2; pass
++)
12546 for (i
= 0; i
< els
; i
++)
12548 unsigned thisarg
= types
[i
];
12549 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12550 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12551 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12552 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12554 /* Decay more-specific signed & unsigned types to sign-insensitive
12555 integer types if sign-specific variants are unavailable. */
12556 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12557 && (types_allowed
& N_SU_ALL
) == 0)
12558 g_type
= NT_integer
;
12560 /* If only untyped args are allowed, decay any more specific types to
12561 them. Some instructions only care about signs for some element
12562 sizes, so handle that properly. */
12563 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12564 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12565 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12566 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12567 g_type
= NT_untyped
;
12571 if ((thisarg
& N_KEY
) != 0)
12575 key_allowed
= thisarg
& ~N_KEY
;
12580 if ((thisarg
& N_VFP
) != 0)
12582 enum neon_shape_el regshape
;
12583 unsigned regwidth
, match
;
12585 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12588 first_error (_("invalid instruction shape"));
12591 regshape
= neon_shape_tab
[ns
].el
[i
];
12592 regwidth
= neon_shape_el_size
[regshape
];
12594 /* In VFP mode, operands must match register widths. If we
12595 have a key operand, use its width, else use the width of
12596 the current operand. */
12602 if (regwidth
!= match
)
12604 first_error (_("operand size must match register width"));
12609 if ((thisarg
& N_EQK
) == 0)
12611 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12613 if ((given_type
& types_allowed
) == 0)
12615 first_error (_("bad type in Neon instruction"));
12621 enum neon_el_type mod_k_type
= k_type
;
12622 unsigned mod_k_size
= k_size
;
12623 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12624 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12626 first_error (_("inconsistent types in Neon instruction"));
12634 return inst
.vectype
.el
[key_el
];
12637 /* Neon-style VFP instruction forwarding. */
12639 /* Thumb VFP instructions have 0xE in the condition field. */
12642 do_vfp_cond_or_thumb (void)
12647 inst
.instruction
|= 0xe0000000;
12649 inst
.instruction
|= inst
.cond
<< 28;
12652 /* Look up and encode a simple mnemonic, for use as a helper function for the
12653 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12654 etc. It is assumed that operand parsing has already been done, and that the
12655 operands are in the form expected by the given opcode (this isn't necessarily
12656 the same as the form in which they were parsed, hence some massaging must
12657 take place before this function is called).
12658 Checks current arch version against that in the looked-up opcode. */
12661 do_vfp_nsyn_opcode (const char *opname
)
12663 const struct asm_opcode
*opcode
;
12665 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12671 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12678 inst
.instruction
= opcode
->tvalue
;
12679 opcode
->tencode ();
12683 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12684 opcode
->aencode ();
12689 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12691 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12696 do_vfp_nsyn_opcode ("fadds");
12698 do_vfp_nsyn_opcode ("fsubs");
12703 do_vfp_nsyn_opcode ("faddd");
12705 do_vfp_nsyn_opcode ("fsubd");
12709 /* Check operand types to see if this is a VFP instruction, and if so call
12713 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12715 enum neon_shape rs
;
12716 struct neon_type_el et
;
12721 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12722 et
= neon_check_type (2, rs
,
12723 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12727 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12728 et
= neon_check_type (3, rs
,
12729 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12736 if (et
.type
!= NT_invtype
)
12747 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12749 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12754 do_vfp_nsyn_opcode ("fmacs");
12756 do_vfp_nsyn_opcode ("fnmacs");
12761 do_vfp_nsyn_opcode ("fmacd");
12763 do_vfp_nsyn_opcode ("fnmacd");
12768 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12770 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12775 do_vfp_nsyn_opcode ("ffmas");
12777 do_vfp_nsyn_opcode ("ffnmas");
12782 do_vfp_nsyn_opcode ("ffmad");
12784 do_vfp_nsyn_opcode ("ffnmad");
12789 do_vfp_nsyn_mul (enum neon_shape rs
)
12792 do_vfp_nsyn_opcode ("fmuls");
12794 do_vfp_nsyn_opcode ("fmuld");
12798 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12800 int is_neg
= (inst
.instruction
& 0x80) != 0;
12801 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12806 do_vfp_nsyn_opcode ("fnegs");
12808 do_vfp_nsyn_opcode ("fabss");
12813 do_vfp_nsyn_opcode ("fnegd");
12815 do_vfp_nsyn_opcode ("fabsd");
12819 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12820 insns belong to Neon, and are handled elsewhere. */
12823 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12825 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12829 do_vfp_nsyn_opcode ("fldmdbs");
12831 do_vfp_nsyn_opcode ("fldmias");
12836 do_vfp_nsyn_opcode ("fstmdbs");
12838 do_vfp_nsyn_opcode ("fstmias");
12843 do_vfp_nsyn_sqrt (void)
12845 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12846 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12849 do_vfp_nsyn_opcode ("fsqrts");
12851 do_vfp_nsyn_opcode ("fsqrtd");
12855 do_vfp_nsyn_div (void)
12857 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12858 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12859 N_F32
| N_F64
| N_KEY
| N_VFP
);
12862 do_vfp_nsyn_opcode ("fdivs");
12864 do_vfp_nsyn_opcode ("fdivd");
12868 do_vfp_nsyn_nmul (void)
12870 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12871 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12872 N_F32
| N_F64
| N_KEY
| N_VFP
);
12876 NEON_ENCODE (SINGLE
, inst
);
12877 do_vfp_sp_dyadic ();
12881 NEON_ENCODE (DOUBLE
, inst
);
12882 do_vfp_dp_rd_rn_rm ();
12884 do_vfp_cond_or_thumb ();
12888 do_vfp_nsyn_cmp (void)
12890 if (inst
.operands
[1].isreg
)
12892 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12893 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12897 NEON_ENCODE (SINGLE
, inst
);
12898 do_vfp_sp_monadic ();
12902 NEON_ENCODE (DOUBLE
, inst
);
12903 do_vfp_dp_rd_rm ();
12908 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12909 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12911 switch (inst
.instruction
& 0x0fffffff)
12914 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12917 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12925 NEON_ENCODE (SINGLE
, inst
);
12926 do_vfp_sp_compare_z ();
12930 NEON_ENCODE (DOUBLE
, inst
);
12934 do_vfp_cond_or_thumb ();
12938 nsyn_insert_sp (void)
12940 inst
.operands
[1] = inst
.operands
[0];
12941 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12942 inst
.operands
[0].reg
= REG_SP
;
12943 inst
.operands
[0].isreg
= 1;
12944 inst
.operands
[0].writeback
= 1;
12945 inst
.operands
[0].present
= 1;
12949 do_vfp_nsyn_push (void)
12952 if (inst
.operands
[1].issingle
)
12953 do_vfp_nsyn_opcode ("fstmdbs");
12955 do_vfp_nsyn_opcode ("fstmdbd");
12959 do_vfp_nsyn_pop (void)
12962 if (inst
.operands
[1].issingle
)
12963 do_vfp_nsyn_opcode ("fldmias");
12965 do_vfp_nsyn_opcode ("fldmiad");
12968 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12969 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12972 neon_dp_fixup (struct arm_it
* insn
)
12974 unsigned int i
= insn
->instruction
;
12979 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12990 insn
->instruction
= i
;
12993 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12997 neon_logbits (unsigned x
)
12999 return ffs (x
) - 4;
13002 #define LOW4(R) ((R) & 0xf)
13003 #define HI1(R) (((R) >> 4) & 1)
13005 /* Encode insns with bit pattern:
13007 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13008 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13010 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13011 different meaning for some instruction. */
13014 neon_three_same (int isquad
, int ubit
, int size
)
13016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13017 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13018 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13019 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13020 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13021 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13022 inst
.instruction
|= (isquad
!= 0) << 6;
13023 inst
.instruction
|= (ubit
!= 0) << 24;
13025 inst
.instruction
|= neon_logbits (size
) << 20;
13027 neon_dp_fixup (&inst
);
13030 /* Encode instructions of the form:
13032 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13033 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13035 Don't write size if SIZE == -1. */
13038 neon_two_same (int qbit
, int ubit
, int size
)
13040 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13041 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13042 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13043 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13044 inst
.instruction
|= (qbit
!= 0) << 6;
13045 inst
.instruction
|= (ubit
!= 0) << 24;
13048 inst
.instruction
|= neon_logbits (size
) << 18;
13050 neon_dp_fixup (&inst
);
13053 /* Neon instruction encoders, in approximate order of appearance. */
13056 do_neon_dyadic_i_su (void)
13058 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13059 struct neon_type_el et
= neon_check_type (3, rs
,
13060 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13061 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13065 do_neon_dyadic_i64_su (void)
13067 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13068 struct neon_type_el et
= neon_check_type (3, rs
,
13069 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13070 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13074 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13077 unsigned size
= et
.size
>> 3;
13078 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13079 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13080 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13081 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13082 inst
.instruction
|= (isquad
!= 0) << 6;
13083 inst
.instruction
|= immbits
<< 16;
13084 inst
.instruction
|= (size
>> 3) << 7;
13085 inst
.instruction
|= (size
& 0x7) << 19;
13087 inst
.instruction
|= (uval
!= 0) << 24;
13089 neon_dp_fixup (&inst
);
13093 do_neon_shl_imm (void)
13095 if (!inst
.operands
[2].isreg
)
13097 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13098 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13099 NEON_ENCODE (IMMED
, inst
);
13100 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13104 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13105 struct neon_type_el et
= neon_check_type (3, rs
,
13106 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13109 /* VSHL/VQSHL 3-register variants have syntax such as:
13111 whereas other 3-register operations encoded by neon_three_same have
13114 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13116 tmp
= inst
.operands
[2].reg
;
13117 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13118 inst
.operands
[1].reg
= tmp
;
13119 NEON_ENCODE (INTEGER
, inst
);
13120 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13125 do_neon_qshl_imm (void)
13127 if (!inst
.operands
[2].isreg
)
13129 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13130 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13132 NEON_ENCODE (IMMED
, inst
);
13133 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13134 inst
.operands
[2].imm
);
13138 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13139 struct neon_type_el et
= neon_check_type (3, rs
,
13140 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13143 /* See note in do_neon_shl_imm. */
13144 tmp
= inst
.operands
[2].reg
;
13145 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13146 inst
.operands
[1].reg
= tmp
;
13147 NEON_ENCODE (INTEGER
, inst
);
13148 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13153 do_neon_rshl (void)
13155 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13156 struct neon_type_el et
= neon_check_type (3, rs
,
13157 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13160 tmp
= inst
.operands
[2].reg
;
13161 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13162 inst
.operands
[1].reg
= tmp
;
13163 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13167 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13169 /* Handle .I8 pseudo-instructions. */
13172 /* Unfortunately, this will make everything apart from zero out-of-range.
13173 FIXME is this the intended semantics? There doesn't seem much point in
13174 accepting .I8 if so. */
13175 immediate
|= immediate
<< 8;
13181 if (immediate
== (immediate
& 0x000000ff))
13183 *immbits
= immediate
;
13186 else if (immediate
== (immediate
& 0x0000ff00))
13188 *immbits
= immediate
>> 8;
13191 else if (immediate
== (immediate
& 0x00ff0000))
13193 *immbits
= immediate
>> 16;
13196 else if (immediate
== (immediate
& 0xff000000))
13198 *immbits
= immediate
>> 24;
13201 if ((immediate
& 0xffff) != (immediate
>> 16))
13202 goto bad_immediate
;
13203 immediate
&= 0xffff;
13206 if (immediate
== (immediate
& 0x000000ff))
13208 *immbits
= immediate
;
13211 else if (immediate
== (immediate
& 0x0000ff00))
13213 *immbits
= immediate
>> 8;
13218 first_error (_("immediate value out of range"));
13222 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13226 neon_bits_same_in_bytes (unsigned imm
)
13228 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13229 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13230 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13231 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13234 /* For immediate of above form, return 0bABCD. */
13237 neon_squash_bits (unsigned imm
)
13239 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13240 | ((imm
& 0x01000000) >> 21);
13243 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13246 neon_qfloat_bits (unsigned imm
)
13248 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13251 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13252 the instruction. *OP is passed as the initial value of the op field, and
13253 may be set to a different value depending on the constant (i.e.
13254 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13255 MVN). If the immediate looks like a repeated pattern then also
13256 try smaller element sizes. */
13259 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13260 unsigned *immbits
, int *op
, int size
,
13261 enum neon_el_type type
)
13263 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13265 if (type
== NT_float
&& !float_p
)
13268 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13270 if (size
!= 32 || *op
== 1)
13272 *immbits
= neon_qfloat_bits (immlo
);
13278 if (neon_bits_same_in_bytes (immhi
)
13279 && neon_bits_same_in_bytes (immlo
))
13283 *immbits
= (neon_squash_bits (immhi
) << 4)
13284 | neon_squash_bits (immlo
);
13289 if (immhi
!= immlo
)
13295 if (immlo
== (immlo
& 0x000000ff))
13300 else if (immlo
== (immlo
& 0x0000ff00))
13302 *immbits
= immlo
>> 8;
13305 else if (immlo
== (immlo
& 0x00ff0000))
13307 *immbits
= immlo
>> 16;
13310 else if (immlo
== (immlo
& 0xff000000))
13312 *immbits
= immlo
>> 24;
13315 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13317 *immbits
= (immlo
>> 8) & 0xff;
13320 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13322 *immbits
= (immlo
>> 16) & 0xff;
13326 if ((immlo
& 0xffff) != (immlo
>> 16))
13333 if (immlo
== (immlo
& 0x000000ff))
13338 else if (immlo
== (immlo
& 0x0000ff00))
13340 *immbits
= immlo
>> 8;
13344 if ((immlo
& 0xff) != (immlo
>> 8))
13349 if (immlo
== (immlo
& 0x000000ff))
13351 /* Don't allow MVN with 8-bit immediate. */
13361 /* Write immediate bits [7:0] to the following locations:
13363 |28/24|23 19|18 16|15 4|3 0|
13364 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13366 This function is used by VMOV/VMVN/VORR/VBIC. */
13369 neon_write_immbits (unsigned immbits
)
13371 inst
.instruction
|= immbits
& 0xf;
13372 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13373 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13376 /* Invert low-order SIZE bits of XHI:XLO. */
13379 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13381 unsigned immlo
= xlo
? *xlo
: 0;
13382 unsigned immhi
= xhi
? *xhi
: 0;
13387 immlo
= (~immlo
) & 0xff;
13391 immlo
= (~immlo
) & 0xffff;
13395 immhi
= (~immhi
) & 0xffffffff;
13396 /* fall through. */
13399 immlo
= (~immlo
) & 0xffffffff;
13414 do_neon_logic (void)
13416 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13418 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13419 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13420 /* U bit and size field were set as part of the bitmask. */
13421 NEON_ENCODE (INTEGER
, inst
);
13422 neon_three_same (neon_quad (rs
), 0, -1);
13426 const int three_ops_form
= (inst
.operands
[2].present
13427 && !inst
.operands
[2].isreg
);
13428 const int immoperand
= (three_ops_form
? 2 : 1);
13429 enum neon_shape rs
= (three_ops_form
13430 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13431 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13432 struct neon_type_el et
= neon_check_type (2, rs
,
13433 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13434 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13438 if (et
.type
== NT_invtype
)
13441 if (three_ops_form
)
13442 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13443 _("first and second operands shall be the same register"));
13445 NEON_ENCODE (IMMED
, inst
);
13447 immbits
= inst
.operands
[immoperand
].imm
;
13450 /* .i64 is a pseudo-op, so the immediate must be a repeating
13452 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13453 inst
.operands
[immoperand
].reg
: 0))
13455 /* Set immbits to an invalid constant. */
13456 immbits
= 0xdeadbeef;
13463 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13467 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13471 /* Pseudo-instruction for VBIC. */
13472 neon_invert_size (&immbits
, 0, et
.size
);
13473 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13477 /* Pseudo-instruction for VORR. */
13478 neon_invert_size (&immbits
, 0, et
.size
);
13479 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13489 inst
.instruction
|= neon_quad (rs
) << 6;
13490 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13491 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13492 inst
.instruction
|= cmode
<< 8;
13493 neon_write_immbits (immbits
);
13495 neon_dp_fixup (&inst
);
13500 do_neon_bitfield (void)
13502 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13503 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13504 neon_three_same (neon_quad (rs
), 0, -1);
13508 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13511 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13512 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13514 if (et
.type
== NT_float
)
13516 NEON_ENCODE (FLOAT
, inst
);
13517 neon_three_same (neon_quad (rs
), 0, -1);
13521 NEON_ENCODE (INTEGER
, inst
);
13522 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13527 do_neon_dyadic_if_su (void)
13529 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13533 do_neon_dyadic_if_su_d (void)
13535 /* This version only allow D registers, but that constraint is enforced during
13536 operand parsing so we don't need to do anything extra here. */
13537 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13541 do_neon_dyadic_if_i_d (void)
13543 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13544 affected if we specify unsigned args. */
13545 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13548 enum vfp_or_neon_is_neon_bits
13551 NEON_CHECK_ARCH
= 2
13554 /* Call this function if an instruction which may have belonged to the VFP or
13555 Neon instruction sets, but turned out to be a Neon instruction (due to the
13556 operand types involved, etc.). We have to check and/or fix-up a couple of
13559 - Make sure the user hasn't attempted to make a Neon instruction
13561 - Alter the value in the condition code field if necessary.
13562 - Make sure that the arch supports Neon instructions.
13564 Which of these operations take place depends on bits from enum
13565 vfp_or_neon_is_neon_bits.
13567 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13568 current instruction's condition is COND_ALWAYS, the condition field is
13569 changed to inst.uncond_value. This is necessary because instructions shared
13570 between VFP and Neon may be conditional for the VFP variants only, and the
13571 unconditional Neon version must have, e.g., 0xF in the condition field. */
13574 vfp_or_neon_is_neon (unsigned check
)
13576 /* Conditions are always legal in Thumb mode (IT blocks). */
13577 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13579 if (inst
.cond
!= COND_ALWAYS
)
13581 first_error (_(BAD_COND
));
13584 if (inst
.uncond_value
!= -1)
13585 inst
.instruction
|= inst
.uncond_value
<< 28;
13588 if ((check
& NEON_CHECK_ARCH
)
13589 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13591 first_error (_(BAD_FPU
));
13599 do_neon_addsub_if_i (void)
13601 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13604 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13607 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13608 affected if we specify unsigned args. */
13609 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13612 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13614 V<op> A,B (A is operand 0, B is operand 2)
13619 so handle that case specially. */
13622 neon_exchange_operands (void)
13624 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13625 if (inst
.operands
[1].present
)
13627 /* Swap operands[1] and operands[2]. */
13628 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13629 inst
.operands
[1] = inst
.operands
[2];
13630 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13634 inst
.operands
[1] = inst
.operands
[2];
13635 inst
.operands
[2] = inst
.operands
[0];
13640 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13642 if (inst
.operands
[2].isreg
)
13645 neon_exchange_operands ();
13646 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13650 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13651 struct neon_type_el et
= neon_check_type (2, rs
,
13652 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13654 NEON_ENCODE (IMMED
, inst
);
13655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13659 inst
.instruction
|= neon_quad (rs
) << 6;
13660 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13661 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13663 neon_dp_fixup (&inst
);
13670 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13674 do_neon_cmp_inv (void)
13676 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13682 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13685 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13686 scalars, which are encoded in 5 bits, M : Rm.
13687 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13688 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13692 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13694 unsigned regno
= NEON_SCALAR_REG (scalar
);
13695 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13700 if (regno
> 7 || elno
> 3)
13702 return regno
| (elno
<< 3);
13705 if (regno
> 15 || elno
> 1)
13707 return regno
| (elno
<< 4);
13711 first_error (_("scalar out of range for multiply instruction"));
13717 /* Encode multiply / multiply-accumulate scalar instructions. */
13720 neon_mul_mac (struct neon_type_el et
, int ubit
)
13724 /* Give a more helpful error message if we have an invalid type. */
13725 if (et
.type
== NT_invtype
)
13728 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13729 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13730 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13731 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13732 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13733 inst
.instruction
|= LOW4 (scalar
);
13734 inst
.instruction
|= HI1 (scalar
) << 5;
13735 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13736 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13737 inst
.instruction
|= (ubit
!= 0) << 24;
13739 neon_dp_fixup (&inst
);
13743 do_neon_mac_maybe_scalar (void)
13745 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13748 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13751 if (inst
.operands
[2].isscalar
)
13753 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13754 struct neon_type_el et
= neon_check_type (3, rs
,
13755 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13756 NEON_ENCODE (SCALAR
, inst
);
13757 neon_mul_mac (et
, neon_quad (rs
));
13761 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13762 affected if we specify unsigned args. */
13763 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13768 do_neon_fmac (void)
13770 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13773 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13776 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13782 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13783 struct neon_type_el et
= neon_check_type (3, rs
,
13784 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13785 neon_three_same (neon_quad (rs
), 0, et
.size
);
13788 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13789 same types as the MAC equivalents. The polynomial type for this instruction
13790 is encoded the same as the integer type. */
13795 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13798 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13801 if (inst
.operands
[2].isscalar
)
13802 do_neon_mac_maybe_scalar ();
13804 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13808 do_neon_qdmulh (void)
13810 if (inst
.operands
[2].isscalar
)
13812 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13813 struct neon_type_el et
= neon_check_type (3, rs
,
13814 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13815 NEON_ENCODE (SCALAR
, inst
);
13816 neon_mul_mac (et
, neon_quad (rs
));
13820 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13821 struct neon_type_el et
= neon_check_type (3, rs
,
13822 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13823 NEON_ENCODE (INTEGER
, inst
);
13824 /* The U bit (rounding) comes from bit mask. */
13825 neon_three_same (neon_quad (rs
), 0, et
.size
);
13830 do_neon_fcmp_absolute (void)
13832 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13833 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13834 /* Size field comes from bit mask. */
13835 neon_three_same (neon_quad (rs
), 1, -1);
13839 do_neon_fcmp_absolute_inv (void)
13841 neon_exchange_operands ();
13842 do_neon_fcmp_absolute ();
13846 do_neon_step (void)
13848 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13849 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13850 neon_three_same (neon_quad (rs
), 0, -1);
13854 do_neon_abs_neg (void)
13856 enum neon_shape rs
;
13857 struct neon_type_el et
;
13859 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13862 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13865 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13866 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13870 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13871 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13872 inst
.instruction
|= neon_quad (rs
) << 6;
13873 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13874 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13876 neon_dp_fixup (&inst
);
13882 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13883 struct neon_type_el et
= neon_check_type (2, rs
,
13884 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13885 int imm
= inst
.operands
[2].imm
;
13886 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13887 _("immediate out of range for insert"));
13888 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13894 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13895 struct neon_type_el et
= neon_check_type (2, rs
,
13896 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13897 int imm
= inst
.operands
[2].imm
;
13898 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13899 _("immediate out of range for insert"));
13900 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13904 do_neon_qshlu_imm (void)
13906 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13907 struct neon_type_el et
= neon_check_type (2, rs
,
13908 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13909 int imm
= inst
.operands
[2].imm
;
13910 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13911 _("immediate out of range for shift"));
13912 /* Only encodes the 'U present' variant of the instruction.
13913 In this case, signed types have OP (bit 8) set to 0.
13914 Unsigned types have OP set to 1. */
13915 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13916 /* The rest of the bits are the same as other immediate shifts. */
13917 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13921 do_neon_qmovn (void)
13923 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13924 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13925 /* Saturating move where operands can be signed or unsigned, and the
13926 destination has the same signedness. */
13927 NEON_ENCODE (INTEGER
, inst
);
13928 if (et
.type
== NT_unsigned
)
13929 inst
.instruction
|= 0xc0;
13931 inst
.instruction
|= 0x80;
13932 neon_two_same (0, 1, et
.size
/ 2);
13936 do_neon_qmovun (void)
13938 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13939 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13940 /* Saturating move with unsigned results. Operands must be signed. */
13941 NEON_ENCODE (INTEGER
, inst
);
13942 neon_two_same (0, 1, et
.size
/ 2);
13946 do_neon_rshift_sat_narrow (void)
13948 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13949 or unsigned. If operands are unsigned, results must also be unsigned. */
13950 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13951 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13952 int imm
= inst
.operands
[2].imm
;
13953 /* This gets the bounds check, size encoding and immediate bits calculation
13957 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13958 VQMOVN.I<size> <Dd>, <Qm>. */
13961 inst
.operands
[2].present
= 0;
13962 inst
.instruction
= N_MNEM_vqmovn
;
13967 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13968 _("immediate out of range"));
13969 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13973 do_neon_rshift_sat_narrow_u (void)
13975 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13976 or unsigned. If operands are unsigned, results must also be unsigned. */
13977 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13978 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13979 int imm
= inst
.operands
[2].imm
;
13980 /* This gets the bounds check, size encoding and immediate bits calculation
13984 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13985 VQMOVUN.I<size> <Dd>, <Qm>. */
13988 inst
.operands
[2].present
= 0;
13989 inst
.instruction
= N_MNEM_vqmovun
;
13994 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13995 _("immediate out of range"));
13996 /* FIXME: The manual is kind of unclear about what value U should have in
13997 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13999 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14003 do_neon_movn (void)
14005 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14006 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14007 NEON_ENCODE (INTEGER
, inst
);
14008 neon_two_same (0, 1, et
.size
/ 2);
14012 do_neon_rshift_narrow (void)
14014 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14015 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14016 int imm
= inst
.operands
[2].imm
;
14017 /* This gets the bounds check, size encoding and immediate bits calculation
14021 /* If immediate is zero then we are a pseudo-instruction for
14022 VMOVN.I<size> <Dd>, <Qm> */
14025 inst
.operands
[2].present
= 0;
14026 inst
.instruction
= N_MNEM_vmovn
;
14031 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14032 _("immediate out of range for narrowing operation"));
14033 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14037 do_neon_shll (void)
14039 /* FIXME: Type checking when lengthening. */
14040 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14041 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14042 unsigned imm
= inst
.operands
[2].imm
;
14044 if (imm
== et
.size
)
14046 /* Maximum shift variant. */
14047 NEON_ENCODE (INTEGER
, inst
);
14048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14049 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14050 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14051 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14052 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14054 neon_dp_fixup (&inst
);
14058 /* A more-specific type check for non-max versions. */
14059 et
= neon_check_type (2, NS_QDI
,
14060 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14061 NEON_ENCODE (IMMED
, inst
);
14062 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14066 /* Check the various types for the VCVT instruction, and return which version
14067 the current instruction is. */
14070 neon_cvt_flavour (enum neon_shape rs
)
14072 #define CVT_VAR(C,X,Y) \
14073 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14074 if (et.type != NT_invtype) \
14076 inst.error = NULL; \
14079 struct neon_type_el et
;
14080 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14081 || rs
== NS_FF
) ? N_VFP
: 0;
14082 /* The instruction versions which take an immediate take one register
14083 argument, which is extended to the width of the full register. Thus the
14084 "source" and "destination" registers must have the same width. Hack that
14085 here by making the size equal to the key (wider, in this case) operand. */
14086 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14088 CVT_VAR (0, N_S32
, N_F32
);
14089 CVT_VAR (1, N_U32
, N_F32
);
14090 CVT_VAR (2, N_F32
, N_S32
);
14091 CVT_VAR (3, N_F32
, N_U32
);
14092 /* Half-precision conversions. */
14093 CVT_VAR (4, N_F32
, N_F16
);
14094 CVT_VAR (5, N_F16
, N_F32
);
14098 /* VFP instructions. */
14099 CVT_VAR (6, N_F32
, N_F64
);
14100 CVT_VAR (7, N_F64
, N_F32
);
14101 CVT_VAR (8, N_S32
, N_F64
| key
);
14102 CVT_VAR (9, N_U32
, N_F64
| key
);
14103 CVT_VAR (10, N_F64
| key
, N_S32
);
14104 CVT_VAR (11, N_F64
| key
, N_U32
);
14105 /* VFP instructions with bitshift. */
14106 CVT_VAR (12, N_F32
| key
, N_S16
);
14107 CVT_VAR (13, N_F32
| key
, N_U16
);
14108 CVT_VAR (14, N_F64
| key
, N_S16
);
14109 CVT_VAR (15, N_F64
| key
, N_U16
);
14110 CVT_VAR (16, N_S16
, N_F32
| key
);
14111 CVT_VAR (17, N_U16
, N_F32
| key
);
14112 CVT_VAR (18, N_S16
, N_F64
| key
);
14113 CVT_VAR (19, N_U16
, N_F64
| key
);
14119 /* Neon-syntax VFP conversions. */
14122 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14124 const char *opname
= 0;
14126 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14128 /* Conversions with immediate bitshift. */
14129 const char *enc
[] =
14153 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14155 opname
= enc
[flavour
];
14156 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14157 _("operands 0 and 1 must be the same register"));
14158 inst
.operands
[1] = inst
.operands
[2];
14159 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14164 /* Conversions without bitshift. */
14165 const char *enc
[] =
14181 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14182 opname
= enc
[flavour
];
14186 do_vfp_nsyn_opcode (opname
);
14190 do_vfp_nsyn_cvtz (void)
14192 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14193 int flavour
= neon_cvt_flavour (rs
);
14194 const char *enc
[] =
14208 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14209 do_vfp_nsyn_opcode (enc
[flavour
]);
14213 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14215 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14216 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14217 int flavour
= neon_cvt_flavour (rs
);
14219 /* PR11109: Handle round-to-zero for VCVT conversions. */
14221 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14222 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14223 && (rs
== NS_FD
|| rs
== NS_FF
))
14225 do_vfp_nsyn_cvtz ();
14229 /* VFP rather than Neon conversions. */
14232 do_vfp_nsyn_cvt (rs
, flavour
);
14242 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14244 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14247 /* Fixed-point conversion with #0 immediate is encoded as an
14248 integer conversion. */
14249 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14251 immbits
= 32 - inst
.operands
[2].imm
;
14252 NEON_ENCODE (IMMED
, inst
);
14254 inst
.instruction
|= enctab
[flavour
];
14255 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14256 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14257 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14258 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14259 inst
.instruction
|= neon_quad (rs
) << 6;
14260 inst
.instruction
|= 1 << 21;
14261 inst
.instruction
|= immbits
<< 16;
14263 neon_dp_fixup (&inst
);
14271 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14273 NEON_ENCODE (INTEGER
, inst
);
14275 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14279 inst
.instruction
|= enctab
[flavour
];
14281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14282 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14283 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14284 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14285 inst
.instruction
|= neon_quad (rs
) << 6;
14286 inst
.instruction
|= 2 << 18;
14288 neon_dp_fixup (&inst
);
14292 /* Half-precision conversions for Advanced SIMD -- neon. */
14297 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14299 as_bad (_("operand size must match register width"));
14304 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14306 as_bad (_("operand size must match register width"));
14311 inst
.instruction
= 0x3b60600;
14313 inst
.instruction
= 0x3b60700;
14315 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14316 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14317 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14318 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14319 neon_dp_fixup (&inst
);
14323 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14324 do_vfp_nsyn_cvt (rs
, flavour
);
14329 do_neon_cvtr (void)
14331 do_neon_cvt_1 (FALSE
);
14337 do_neon_cvt_1 (TRUE
);
14341 do_neon_cvtb (void)
14343 inst
.instruction
= 0xeb20a40;
14345 /* The sizes are attached to the mnemonic. */
14346 if (inst
.vectype
.el
[0].type
!= NT_invtype
14347 && inst
.vectype
.el
[0].size
== 16)
14348 inst
.instruction
|= 0x00010000;
14350 /* Programmer's syntax: the sizes are attached to the operands. */
14351 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14352 && inst
.operands
[0].vectype
.size
== 16)
14353 inst
.instruction
|= 0x00010000;
14355 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14356 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14357 do_vfp_cond_or_thumb ();
14362 do_neon_cvtt (void)
14365 inst
.instruction
|= 0x80;
14369 neon_move_immediate (void)
14371 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14372 struct neon_type_el et
= neon_check_type (2, rs
,
14373 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14374 unsigned immlo
, immhi
= 0, immbits
;
14375 int op
, cmode
, float_p
;
14377 constraint (et
.type
== NT_invtype
,
14378 _("operand size must be specified for immediate VMOV"));
14380 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14381 op
= (inst
.instruction
& (1 << 5)) != 0;
14383 immlo
= inst
.operands
[1].imm
;
14384 if (inst
.operands
[1].regisimm
)
14385 immhi
= inst
.operands
[1].reg
;
14387 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14388 _("immediate has bits set outside the operand size"));
14390 float_p
= inst
.operands
[1].immisfloat
;
14392 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14393 et
.size
, et
.type
)) == FAIL
)
14395 /* Invert relevant bits only. */
14396 neon_invert_size (&immlo
, &immhi
, et
.size
);
14397 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14398 with one or the other; those cases are caught by
14399 neon_cmode_for_move_imm. */
14401 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14402 &op
, et
.size
, et
.type
)) == FAIL
)
14404 first_error (_("immediate out of range"));
14409 inst
.instruction
&= ~(1 << 5);
14410 inst
.instruction
|= op
<< 5;
14412 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14414 inst
.instruction
|= neon_quad (rs
) << 6;
14415 inst
.instruction
|= cmode
<< 8;
14417 neon_write_immbits (immbits
);
14423 if (inst
.operands
[1].isreg
)
14425 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14427 NEON_ENCODE (INTEGER
, inst
);
14428 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14429 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14430 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14431 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14432 inst
.instruction
|= neon_quad (rs
) << 6;
14436 NEON_ENCODE (IMMED
, inst
);
14437 neon_move_immediate ();
14440 neon_dp_fixup (&inst
);
14443 /* Encode instructions of form:
14445 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14446 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14449 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14451 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14453 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14455 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14456 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14457 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14458 inst
.instruction
|= neon_logbits (size
) << 20;
14460 neon_dp_fixup (&inst
);
14464 do_neon_dyadic_long (void)
14466 /* FIXME: Type checking for lengthening op. */
14467 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14468 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14469 neon_mixed_length (et
, et
.size
);
14473 do_neon_abal (void)
14475 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14476 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14477 neon_mixed_length (et
, et
.size
);
14481 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14483 if (inst
.operands
[2].isscalar
)
14485 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14486 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14487 NEON_ENCODE (SCALAR
, inst
);
14488 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14492 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14493 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14494 NEON_ENCODE (INTEGER
, inst
);
14495 neon_mixed_length (et
, et
.size
);
14500 do_neon_mac_maybe_scalar_long (void)
14502 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14506 do_neon_dyadic_wide (void)
14508 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14509 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14510 neon_mixed_length (et
, et
.size
);
14514 do_neon_dyadic_narrow (void)
14516 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14517 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14518 /* Operand sign is unimportant, and the U bit is part of the opcode,
14519 so force the operand type to integer. */
14520 et
.type
= NT_integer
;
14521 neon_mixed_length (et
, et
.size
/ 2);
14525 do_neon_mul_sat_scalar_long (void)
14527 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14531 do_neon_vmull (void)
14533 if (inst
.operands
[2].isscalar
)
14534 do_neon_mac_maybe_scalar_long ();
14537 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14538 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14539 if (et
.type
== NT_poly
)
14540 NEON_ENCODE (POLY
, inst
);
14542 NEON_ENCODE (INTEGER
, inst
);
14543 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14544 zero. Should be OK as-is. */
14545 neon_mixed_length (et
, et
.size
);
14552 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14553 struct neon_type_el et
= neon_check_type (3, rs
,
14554 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14555 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14557 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14558 _("shift out of range"));
14559 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14560 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14561 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14562 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14563 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14564 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14565 inst
.instruction
|= neon_quad (rs
) << 6;
14566 inst
.instruction
|= imm
<< 8;
14568 neon_dp_fixup (&inst
);
14574 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14575 struct neon_type_el et
= neon_check_type (2, rs
,
14576 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14577 unsigned op
= (inst
.instruction
>> 7) & 3;
14578 /* N (width of reversed regions) is encoded as part of the bitmask. We
14579 extract it here to check the elements to be reversed are smaller.
14580 Otherwise we'd get a reserved instruction. */
14581 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14582 gas_assert (elsize
!= 0);
14583 constraint (et
.size
>= elsize
,
14584 _("elements must be smaller than reversal region"));
14585 neon_two_same (neon_quad (rs
), 1, et
.size
);
14591 if (inst
.operands
[1].isscalar
)
14593 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14594 struct neon_type_el et
= neon_check_type (2, rs
,
14595 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14596 unsigned sizebits
= et
.size
>> 3;
14597 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14598 int logsize
= neon_logbits (et
.size
);
14599 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14601 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14604 NEON_ENCODE (SCALAR
, inst
);
14605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14607 inst
.instruction
|= LOW4 (dm
);
14608 inst
.instruction
|= HI1 (dm
) << 5;
14609 inst
.instruction
|= neon_quad (rs
) << 6;
14610 inst
.instruction
|= x
<< 17;
14611 inst
.instruction
|= sizebits
<< 16;
14613 neon_dp_fixup (&inst
);
14617 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14618 struct neon_type_el et
= neon_check_type (2, rs
,
14619 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14620 /* Duplicate ARM register to lanes of vector. */
14621 NEON_ENCODE (ARMREG
, inst
);
14624 case 8: inst
.instruction
|= 0x400000; break;
14625 case 16: inst
.instruction
|= 0x000020; break;
14626 case 32: inst
.instruction
|= 0x000000; break;
14629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14630 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14631 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14632 inst
.instruction
|= neon_quad (rs
) << 21;
14633 /* The encoding for this instruction is identical for the ARM and Thumb
14634 variants, except for the condition field. */
14635 do_vfp_cond_or_thumb ();
14639 /* VMOV has particularly many variations. It can be one of:
14640 0. VMOV<c><q> <Qd>, <Qm>
14641 1. VMOV<c><q> <Dd>, <Dm>
14642 (Register operations, which are VORR with Rm = Rn.)
14643 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14644 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14646 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14647 (ARM register to scalar.)
14648 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14649 (Two ARM registers to vector.)
14650 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14651 (Scalar to ARM register.)
14652 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14653 (Vector to two ARM registers.)
14654 8. VMOV.F32 <Sd>, <Sm>
14655 9. VMOV.F64 <Dd>, <Dm>
14656 (VFP register moves.)
14657 10. VMOV.F32 <Sd>, #imm
14658 11. VMOV.F64 <Dd>, #imm
14659 (VFP float immediate load.)
14660 12. VMOV <Rd>, <Sm>
14661 (VFP single to ARM reg.)
14662 13. VMOV <Sd>, <Rm>
14663 (ARM reg to VFP single.)
14664 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14665 (Two ARM regs to two VFP singles.)
14666 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14667 (Two VFP singles to two ARM regs.)
14669 These cases can be disambiguated using neon_select_shape, except cases 1/9
14670 and 3/11 which depend on the operand type too.
14672 All the encoded bits are hardcoded by this function.
14674 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14675 Cases 5, 7 may be used with VFPv2 and above.
14677 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14678 can specify a type where it doesn't make sense to, and is ignored). */
14683 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14684 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14686 struct neon_type_el et
;
14687 const char *ldconst
= 0;
14691 case NS_DD
: /* case 1/9. */
14692 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14693 /* It is not an error here if no type is given. */
14695 if (et
.type
== NT_float
&& et
.size
== 64)
14697 do_vfp_nsyn_opcode ("fcpyd");
14700 /* fall through. */
14702 case NS_QQ
: /* case 0/1. */
14704 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14706 /* The architecture manual I have doesn't explicitly state which
14707 value the U bit should have for register->register moves, but
14708 the equivalent VORR instruction has U = 0, so do that. */
14709 inst
.instruction
= 0x0200110;
14710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14716 inst
.instruction
|= neon_quad (rs
) << 6;
14718 neon_dp_fixup (&inst
);
14722 case NS_DI
: /* case 3/11. */
14723 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14725 if (et
.type
== NT_float
&& et
.size
== 64)
14727 /* case 11 (fconstd). */
14728 ldconst
= "fconstd";
14729 goto encode_fconstd
;
14731 /* fall through. */
14733 case NS_QI
: /* case 2/3. */
14734 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14736 inst
.instruction
= 0x0800010;
14737 neon_move_immediate ();
14738 neon_dp_fixup (&inst
);
14741 case NS_SR
: /* case 4. */
14743 unsigned bcdebits
= 0;
14745 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14746 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14748 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14749 logsize
= neon_logbits (et
.size
);
14751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14754 && et
.size
!= 32, _(BAD_FPU
));
14755 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14756 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14760 case 8: bcdebits
= 0x8; break;
14761 case 16: bcdebits
= 0x1; break;
14762 case 32: bcdebits
= 0x0; break;
14766 bcdebits
|= x
<< logsize
;
14768 inst
.instruction
= 0xe000b10;
14769 do_vfp_cond_or_thumb ();
14770 inst
.instruction
|= LOW4 (dn
) << 16;
14771 inst
.instruction
|= HI1 (dn
) << 7;
14772 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14773 inst
.instruction
|= (bcdebits
& 3) << 5;
14774 inst
.instruction
|= (bcdebits
>> 2) << 21;
14778 case NS_DRR
: /* case 5 (fmdrr). */
14779 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14782 inst
.instruction
= 0xc400b10;
14783 do_vfp_cond_or_thumb ();
14784 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14785 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14786 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14787 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14790 case NS_RS
: /* case 6. */
14793 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14794 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14795 unsigned abcdebits
= 0;
14797 et
= neon_check_type (2, NS_NULL
,
14798 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14799 logsize
= neon_logbits (et
.size
);
14801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14803 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14804 && et
.size
!= 32, _(BAD_FPU
));
14805 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14806 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14810 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14811 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14812 case 32: abcdebits
= 0x00; break;
14816 abcdebits
|= x
<< logsize
;
14817 inst
.instruction
= 0xe100b10;
14818 do_vfp_cond_or_thumb ();
14819 inst
.instruction
|= LOW4 (dn
) << 16;
14820 inst
.instruction
|= HI1 (dn
) << 7;
14821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14822 inst
.instruction
|= (abcdebits
& 3) << 5;
14823 inst
.instruction
|= (abcdebits
>> 2) << 21;
14827 case NS_RRD
: /* case 7 (fmrrd). */
14828 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14831 inst
.instruction
= 0xc500b10;
14832 do_vfp_cond_or_thumb ();
14833 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14834 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14835 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14836 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14839 case NS_FF
: /* case 8 (fcpys). */
14840 do_vfp_nsyn_opcode ("fcpys");
14843 case NS_FI
: /* case 10 (fconsts). */
14844 ldconst
= "fconsts";
14846 if (is_quarter_float (inst
.operands
[1].imm
))
14848 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14849 do_vfp_nsyn_opcode (ldconst
);
14852 first_error (_("immediate out of range"));
14855 case NS_RF
: /* case 12 (fmrs). */
14856 do_vfp_nsyn_opcode ("fmrs");
14859 case NS_FR
: /* case 13 (fmsr). */
14860 do_vfp_nsyn_opcode ("fmsr");
14863 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14864 (one of which is a list), but we have parsed four. Do some fiddling to
14865 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14867 case NS_RRFF
: /* case 14 (fmrrs). */
14868 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14869 _("VFP registers must be adjacent"));
14870 inst
.operands
[2].imm
= 2;
14871 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14872 do_vfp_nsyn_opcode ("fmrrs");
14875 case NS_FFRR
: /* case 15 (fmsrr). */
14876 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14877 _("VFP registers must be adjacent"));
14878 inst
.operands
[1] = inst
.operands
[2];
14879 inst
.operands
[2] = inst
.operands
[3];
14880 inst
.operands
[0].imm
= 2;
14881 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14882 do_vfp_nsyn_opcode ("fmsrr");
14891 do_neon_rshift_round_imm (void)
14893 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14894 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14895 int imm
= inst
.operands
[2].imm
;
14897 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14900 inst
.operands
[2].present
= 0;
14905 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14906 _("immediate out of range for shift"));
14907 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14912 do_neon_movl (void)
14914 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14915 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14916 unsigned sizebits
= et
.size
>> 3;
14917 inst
.instruction
|= sizebits
<< 19;
14918 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14924 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14925 struct neon_type_el et
= neon_check_type (2, rs
,
14926 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14927 NEON_ENCODE (INTEGER
, inst
);
14928 neon_two_same (neon_quad (rs
), 1, et
.size
);
14932 do_neon_zip_uzp (void)
14934 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14935 struct neon_type_el et
= neon_check_type (2, rs
,
14936 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14937 if (rs
== NS_DD
&& et
.size
== 32)
14939 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14940 inst
.instruction
= N_MNEM_vtrn
;
14944 neon_two_same (neon_quad (rs
), 1, et
.size
);
14948 do_neon_sat_abs_neg (void)
14950 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14951 struct neon_type_el et
= neon_check_type (2, rs
,
14952 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14953 neon_two_same (neon_quad (rs
), 1, et
.size
);
14957 do_neon_pair_long (void)
14959 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14960 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14961 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14962 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14963 neon_two_same (neon_quad (rs
), 1, et
.size
);
14967 do_neon_recip_est (void)
14969 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14970 struct neon_type_el et
= neon_check_type (2, rs
,
14971 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14972 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14973 neon_two_same (neon_quad (rs
), 1, et
.size
);
14979 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14980 struct neon_type_el et
= neon_check_type (2, rs
,
14981 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14982 neon_two_same (neon_quad (rs
), 1, et
.size
);
14988 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14989 struct neon_type_el et
= neon_check_type (2, rs
,
14990 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14991 neon_two_same (neon_quad (rs
), 1, et
.size
);
14997 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14998 struct neon_type_el et
= neon_check_type (2, rs
,
14999 N_EQK
| N_INT
, N_8
| N_KEY
);
15000 neon_two_same (neon_quad (rs
), 1, et
.size
);
15006 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15007 neon_two_same (neon_quad (rs
), 1, -1);
15011 do_neon_tbl_tbx (void)
15013 unsigned listlenbits
;
15014 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15016 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15018 first_error (_("bad list length for table lookup"));
15022 listlenbits
= inst
.operands
[1].imm
- 1;
15023 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15024 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15025 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15026 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15027 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15028 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15029 inst
.instruction
|= listlenbits
<< 8;
15031 neon_dp_fixup (&inst
);
15035 do_neon_ldm_stm (void)
15037 /* P, U and L bits are part of bitmask. */
15038 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15039 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15041 if (inst
.operands
[1].issingle
)
15043 do_vfp_nsyn_ldm_stm (is_dbmode
);
15047 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15048 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15050 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15051 _("register list must contain at least 1 and at most 16 "
15054 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15055 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15056 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15057 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15059 inst
.instruction
|= offsetbits
;
15061 do_vfp_cond_or_thumb ();
15065 do_neon_ldr_str (void)
15067 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15069 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15070 And is UNPREDICTABLE in thumb mode. */
15072 && inst
.operands
[1].reg
== REG_PC
15073 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15075 if (!thumb_mode
&& warn_on_deprecated
)
15076 as_warn (_("Use of PC here is deprecated"));
15078 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15081 if (inst
.operands
[0].issingle
)
15084 do_vfp_nsyn_opcode ("flds");
15086 do_vfp_nsyn_opcode ("fsts");
15091 do_vfp_nsyn_opcode ("fldd");
15093 do_vfp_nsyn_opcode ("fstd");
15097 /* "interleave" version also handles non-interleaving register VLD1/VST1
15101 do_neon_ld_st_interleave (void)
15103 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15104 N_8
| N_16
| N_32
| N_64
);
15105 unsigned alignbits
= 0;
15107 /* The bits in this table go:
15108 0: register stride of one (0) or two (1)
15109 1,2: register list length, minus one (1, 2, 3, 4).
15110 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15111 We use -1 for invalid entries. */
15112 const int typetable
[] =
15114 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15115 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15116 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15117 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15121 if (et
.type
== NT_invtype
)
15124 if (inst
.operands
[1].immisalign
)
15125 switch (inst
.operands
[1].imm
>> 8)
15127 case 64: alignbits
= 1; break;
15129 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15130 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15131 goto bad_alignment
;
15135 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15136 goto bad_alignment
;
15141 first_error (_("bad alignment"));
15145 inst
.instruction
|= alignbits
<< 4;
15146 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15148 /* Bits [4:6] of the immediate in a list specifier encode register stride
15149 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15150 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15151 up the right value for "type" in a table based on this value and the given
15152 list style, then stick it back. */
15153 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15154 | (((inst
.instruction
>> 8) & 3) << 3);
15156 typebits
= typetable
[idx
];
15158 constraint (typebits
== -1, _("bad list type for instruction"));
15160 inst
.instruction
&= ~0xf00;
15161 inst
.instruction
|= typebits
<< 8;
15164 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15165 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15166 otherwise. The variable arguments are a list of pairs of legal (size, align)
15167 values, terminated with -1. */
15170 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15173 int result
= FAIL
, thissize
, thisalign
;
15175 if (!inst
.operands
[1].immisalign
)
15181 va_start (ap
, do_align
);
15185 thissize
= va_arg (ap
, int);
15186 if (thissize
== -1)
15188 thisalign
= va_arg (ap
, int);
15190 if (size
== thissize
&& align
== thisalign
)
15193 while (result
!= SUCCESS
);
15197 if (result
== SUCCESS
)
15200 first_error (_("unsupported alignment for instruction"));
15206 do_neon_ld_st_lane (void)
15208 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15209 int align_good
, do_align
= 0;
15210 int logsize
= neon_logbits (et
.size
);
15211 int align
= inst
.operands
[1].imm
>> 8;
15212 int n
= (inst
.instruction
>> 8) & 3;
15213 int max_el
= 64 / et
.size
;
15215 if (et
.type
== NT_invtype
)
15218 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15219 _("bad list length"));
15220 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15221 _("scalar index out of range"));
15222 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15224 _("stride of 2 unavailable when element size is 8"));
15228 case 0: /* VLD1 / VST1. */
15229 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15231 if (align_good
== FAIL
)
15235 unsigned alignbits
= 0;
15238 case 16: alignbits
= 0x1; break;
15239 case 32: alignbits
= 0x3; break;
15242 inst
.instruction
|= alignbits
<< 4;
15246 case 1: /* VLD2 / VST2. */
15247 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15249 if (align_good
== FAIL
)
15252 inst
.instruction
|= 1 << 4;
15255 case 2: /* VLD3 / VST3. */
15256 constraint (inst
.operands
[1].immisalign
,
15257 _("can't use alignment with this instruction"));
15260 case 3: /* VLD4 / VST4. */
15261 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15262 16, 64, 32, 64, 32, 128, -1);
15263 if (align_good
== FAIL
)
15267 unsigned alignbits
= 0;
15270 case 8: alignbits
= 0x1; break;
15271 case 16: alignbits
= 0x1; break;
15272 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15275 inst
.instruction
|= alignbits
<< 4;
15282 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15283 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15284 inst
.instruction
|= 1 << (4 + logsize
);
15286 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15287 inst
.instruction
|= logsize
<< 10;
15290 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15293 do_neon_ld_dup (void)
15295 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15296 int align_good
, do_align
= 0;
15298 if (et
.type
== NT_invtype
)
15301 switch ((inst
.instruction
>> 8) & 3)
15303 case 0: /* VLD1. */
15304 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15305 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15306 &do_align
, 16, 16, 32, 32, -1);
15307 if (align_good
== FAIL
)
15309 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15312 case 2: inst
.instruction
|= 1 << 5; break;
15313 default: first_error (_("bad list length")); return;
15315 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15318 case 1: /* VLD2. */
15319 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15320 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15321 if (align_good
== FAIL
)
15323 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15324 _("bad list length"));
15325 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15326 inst
.instruction
|= 1 << 5;
15327 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15330 case 2: /* VLD3. */
15331 constraint (inst
.operands
[1].immisalign
,
15332 _("can't use alignment with this instruction"));
15333 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15334 _("bad list length"));
15335 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15336 inst
.instruction
|= 1 << 5;
15337 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15340 case 3: /* VLD4. */
15342 int align
= inst
.operands
[1].imm
>> 8;
15343 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15344 16, 64, 32, 64, 32, 128, -1);
15345 if (align_good
== FAIL
)
15347 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15348 _("bad list length"));
15349 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15350 inst
.instruction
|= 1 << 5;
15351 if (et
.size
== 32 && align
== 128)
15352 inst
.instruction
|= 0x3 << 6;
15354 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15361 inst
.instruction
|= do_align
<< 4;
15364 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15365 apart from bits [11:4]. */
15368 do_neon_ldx_stx (void)
15370 if (inst
.operands
[1].isreg
)
15371 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15373 switch (NEON_LANE (inst
.operands
[0].imm
))
15375 case NEON_INTERLEAVE_LANES
:
15376 NEON_ENCODE (INTERLV
, inst
);
15377 do_neon_ld_st_interleave ();
15380 case NEON_ALL_LANES
:
15381 NEON_ENCODE (DUP
, inst
);
15386 NEON_ENCODE (LANE
, inst
);
15387 do_neon_ld_st_lane ();
15390 /* L bit comes from bit mask. */
15391 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15392 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15393 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15395 if (inst
.operands
[1].postind
)
15397 int postreg
= inst
.operands
[1].imm
& 0xf;
15398 constraint (!inst
.operands
[1].immisreg
,
15399 _("post-index must be a register"));
15400 constraint (postreg
== 0xd || postreg
== 0xf,
15401 _("bad register for post-index"));
15402 inst
.instruction
|= postreg
;
15404 else if (inst
.operands
[1].writeback
)
15406 inst
.instruction
|= 0xd;
15409 inst
.instruction
|= 0xf;
15412 inst
.instruction
|= 0xf9000000;
15414 inst
.instruction
|= 0xf4000000;
15417 /* Overall per-instruction processing. */
15419 /* We need to be able to fix up arbitrary expressions in some statements.
15420 This is so that we can handle symbols that are an arbitrary distance from
15421 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15422 which returns part of an address in a form which will be valid for
15423 a data instruction. We do this by pushing the expression into a symbol
15424 in the expr_section, and creating a fix for that. */
15427 fix_new_arm (fragS
* frag
,
15441 /* Create an absolute valued symbol, so we have something to
15442 refer to in the object file. Unfortunately for us, gas's
15443 generic expression parsing will already have folded out
15444 any use of .set foo/.type foo %function that may have
15445 been used to set type information of the target location,
15446 that's being specified symbolically. We have to presume
15447 the user knows what they are doing. */
15451 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15453 symbol
= symbol_find_or_make (name
);
15454 S_SET_SEGMENT (symbol
, absolute_section
);
15455 symbol_set_frag (symbol
, &zero_address_frag
);
15456 S_SET_VALUE (symbol
, exp
->X_add_number
);
15457 exp
->X_op
= O_symbol
;
15458 exp
->X_add_symbol
= symbol
;
15459 exp
->X_add_number
= 0;
15465 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15466 (enum bfd_reloc_code_real
) reloc
);
15470 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15471 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15475 /* Mark whether the fix is to a THUMB instruction, or an ARM
15477 new_fix
->tc_fix_data
= thumb_mode
;
15480 /* Create a frg for an instruction requiring relaxation. */
15482 output_relax_insn (void)
15488 /* The size of the instruction is unknown, so tie the debug info to the
15489 start of the instruction. */
15490 dwarf2_emit_insn (0);
15492 switch (inst
.reloc
.exp
.X_op
)
15495 sym
= inst
.reloc
.exp
.X_add_symbol
;
15496 offset
= inst
.reloc
.exp
.X_add_number
;
15500 offset
= inst
.reloc
.exp
.X_add_number
;
15503 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15507 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15508 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15509 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15512 /* Write a 32-bit thumb instruction to buf. */
15514 put_thumb32_insn (char * buf
, unsigned long insn
)
15516 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15517 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15521 output_inst (const char * str
)
15527 as_bad ("%s -- `%s'", inst
.error
, str
);
15532 output_relax_insn ();
15535 if (inst
.size
== 0)
15538 to
= frag_more (inst
.size
);
15539 /* PR 9814: Record the thumb mode into the current frag so that we know
15540 what type of NOP padding to use, if necessary. We override any previous
15541 setting so that if the mode has changed then the NOPS that we use will
15542 match the encoding of the last instruction in the frag. */
15543 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15545 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15547 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15548 put_thumb32_insn (to
, inst
.instruction
);
15550 else if (inst
.size
> INSN_SIZE
)
15552 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15553 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15554 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15557 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15559 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15560 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15561 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15564 dwarf2_emit_insn (inst
.size
);
15568 output_it_inst (int cond
, int mask
, char * to
)
15570 unsigned long instruction
= 0xbf00;
15573 instruction
|= mask
;
15574 instruction
|= cond
<< 4;
15578 to
= frag_more (2);
15580 dwarf2_emit_insn (2);
15584 md_number_to_chars (to
, instruction
, 2);
15589 /* Tag values used in struct asm_opcode's tag field. */
15592 OT_unconditional
, /* Instruction cannot be conditionalized.
15593 The ARM condition field is still 0xE. */
15594 OT_unconditionalF
, /* Instruction cannot be conditionalized
15595 and carries 0xF in its ARM condition field. */
15596 OT_csuffix
, /* Instruction takes a conditional suffix. */
15597 OT_csuffixF
, /* Some forms of the instruction take a conditional
15598 suffix, others place 0xF where the condition field
15600 OT_cinfix3
, /* Instruction takes a conditional infix,
15601 beginning at character index 3. (In
15602 unified mode, it becomes a suffix.) */
15603 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15604 tsts, cmps, cmns, and teqs. */
15605 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15606 character index 3, even in unified mode. Used for
15607 legacy instructions where suffix and infix forms
15608 may be ambiguous. */
15609 OT_csuf_or_in3
, /* Instruction takes either a conditional
15610 suffix or an infix at character index 3. */
15611 OT_odd_infix_unc
, /* This is the unconditional variant of an
15612 instruction that takes a conditional infix
15613 at an unusual position. In unified mode,
15614 this variant will accept a suffix. */
15615 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15616 are the conditional variants of instructions that
15617 take conditional infixes in unusual positions.
15618 The infix appears at character index
15619 (tag - OT_odd_infix_0). These are not accepted
15620 in unified mode. */
15623 /* Subroutine of md_assemble, responsible for looking up the primary
15624 opcode from the mnemonic the user wrote. STR points to the
15625 beginning of the mnemonic.
15627 This is not simply a hash table lookup, because of conditional
15628 variants. Most instructions have conditional variants, which are
15629 expressed with a _conditional affix_ to the mnemonic. If we were
15630 to encode each conditional variant as a literal string in the opcode
15631 table, it would have approximately 20,000 entries.
15633 Most mnemonics take this affix as a suffix, and in unified syntax,
15634 'most' is upgraded to 'all'. However, in the divided syntax, some
15635 instructions take the affix as an infix, notably the s-variants of
15636 the arithmetic instructions. Of those instructions, all but six
15637 have the infix appear after the third character of the mnemonic.
15639 Accordingly, the algorithm for looking up primary opcodes given
15642 1. Look up the identifier in the opcode table.
15643 If we find a match, go to step U.
15645 2. Look up the last two characters of the identifier in the
15646 conditions table. If we find a match, look up the first N-2
15647 characters of the identifier in the opcode table. If we
15648 find a match, go to step CE.
15650 3. Look up the fourth and fifth characters of the identifier in
15651 the conditions table. If we find a match, extract those
15652 characters from the identifier, and look up the remaining
15653 characters in the opcode table. If we find a match, go
15658 U. Examine the tag field of the opcode structure, in case this is
15659 one of the six instructions with its conditional infix in an
15660 unusual place. If it is, the tag tells us where to find the
15661 infix; look it up in the conditions table and set inst.cond
15662 accordingly. Otherwise, this is an unconditional instruction.
15663 Again set inst.cond accordingly. Return the opcode structure.
15665 CE. Examine the tag field to make sure this is an instruction that
15666 should receive a conditional suffix. If it is not, fail.
15667 Otherwise, set inst.cond from the suffix we already looked up,
15668 and return the opcode structure.
15670 CM. Examine the tag field to make sure this is an instruction that
15671 should receive a conditional infix after the third character.
15672 If it is not, fail. Otherwise, undo the edits to the current
15673 line of input and proceed as for case CE. */
15675 static const struct asm_opcode
*
15676 opcode_lookup (char **str
)
15680 const struct asm_opcode
*opcode
;
15681 const struct asm_cond
*cond
;
15684 /* Scan up to the end of the mnemonic, which must end in white space,
15685 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15686 for (base
= end
= *str
; *end
!= '\0'; end
++)
15687 if (*end
== ' ' || *end
== '.')
15693 /* Handle a possible width suffix and/or Neon type suffix. */
15698 /* The .w and .n suffixes are only valid if the unified syntax is in
15700 if (unified_syntax
&& end
[1] == 'w')
15702 else if (unified_syntax
&& end
[1] == 'n')
15707 inst
.vectype
.elems
= 0;
15709 *str
= end
+ offset
;
15711 if (end
[offset
] == '.')
15713 /* See if we have a Neon type suffix (possible in either unified or
15714 non-unified ARM syntax mode). */
15715 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15718 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15724 /* Look for unaffixed or special-case affixed mnemonic. */
15725 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15730 if (opcode
->tag
< OT_odd_infix_0
)
15732 inst
.cond
= COND_ALWAYS
;
15736 if (warn_on_deprecated
&& unified_syntax
)
15737 as_warn (_("conditional infixes are deprecated in unified syntax"));
15738 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15739 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15742 inst
.cond
= cond
->value
;
15746 /* Cannot have a conditional suffix on a mnemonic of less than two
15748 if (end
- base
< 3)
15751 /* Look for suffixed mnemonic. */
15753 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15754 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15756 if (opcode
&& cond
)
15759 switch (opcode
->tag
)
15761 case OT_cinfix3_legacy
:
15762 /* Ignore conditional suffixes matched on infix only mnemonics. */
15766 case OT_cinfix3_deprecated
:
15767 case OT_odd_infix_unc
:
15768 if (!unified_syntax
)
15770 /* else fall through */
15774 case OT_csuf_or_in3
:
15775 inst
.cond
= cond
->value
;
15778 case OT_unconditional
:
15779 case OT_unconditionalF
:
15781 inst
.cond
= cond
->value
;
15784 /* Delayed diagnostic. */
15785 inst
.error
= BAD_COND
;
15786 inst
.cond
= COND_ALWAYS
;
15795 /* Cannot have a usual-position infix on a mnemonic of less than
15796 six characters (five would be a suffix). */
15797 if (end
- base
< 6)
15800 /* Look for infixed mnemonic in the usual position. */
15802 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15806 memcpy (save
, affix
, 2);
15807 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15808 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15810 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15811 memcpy (affix
, save
, 2);
15814 && (opcode
->tag
== OT_cinfix3
15815 || opcode
->tag
== OT_cinfix3_deprecated
15816 || opcode
->tag
== OT_csuf_or_in3
15817 || opcode
->tag
== OT_cinfix3_legacy
))
15820 if (warn_on_deprecated
&& unified_syntax
15821 && (opcode
->tag
== OT_cinfix3
15822 || opcode
->tag
== OT_cinfix3_deprecated
))
15823 as_warn (_("conditional infixes are deprecated in unified syntax"));
15825 inst
.cond
= cond
->value
;
15832 /* This function generates an initial IT instruction, leaving its block
15833 virtually open for the new instructions. Eventually,
15834 the mask will be updated by now_it_add_mask () each time
15835 a new instruction needs to be included in the IT block.
15836 Finally, the block is closed with close_automatic_it_block ().
15837 The block closure can be requested either from md_assemble (),
15838 a tencode (), or due to a label hook. */
15841 new_automatic_it_block (int cond
)
15843 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15844 now_it
.mask
= 0x18;
15846 now_it
.block_length
= 1;
15847 mapping_state (MAP_THUMB
);
15848 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15851 /* Close an automatic IT block.
15852 See comments in new_automatic_it_block (). */
15855 close_automatic_it_block (void)
15857 now_it
.mask
= 0x10;
15858 now_it
.block_length
= 0;
15861 /* Update the mask of the current automatically-generated IT
15862 instruction. See comments in new_automatic_it_block (). */
15865 now_it_add_mask (int cond
)
15867 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15868 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15869 | ((bitvalue) << (nbit)))
15870 const int resulting_bit
= (cond
& 1);
15872 now_it
.mask
&= 0xf;
15873 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15875 (5 - now_it
.block_length
));
15876 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15878 ((5 - now_it
.block_length
) - 1) );
15879 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15882 #undef SET_BIT_VALUE
15885 /* The IT blocks handling machinery is accessed through the these functions:
15886 it_fsm_pre_encode () from md_assemble ()
15887 set_it_insn_type () optional, from the tencode functions
15888 set_it_insn_type_last () ditto
15889 in_it_block () ditto
15890 it_fsm_post_encode () from md_assemble ()
15891 force_automatic_it_block_close () from label habdling functions
15894 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15895 initializing the IT insn type with a generic initial value depending
15896 on the inst.condition.
15897 2) During the tencode function, two things may happen:
15898 a) The tencode function overrides the IT insn type by
15899 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15900 b) The tencode function queries the IT block state by
15901 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15903 Both set_it_insn_type and in_it_block run the internal FSM state
15904 handling function (handle_it_state), because: a) setting the IT insn
15905 type may incur in an invalid state (exiting the function),
15906 and b) querying the state requires the FSM to be updated.
15907 Specifically we want to avoid creating an IT block for conditional
15908 branches, so it_fsm_pre_encode is actually a guess and we can't
15909 determine whether an IT block is required until the tencode () routine
15910 has decided what type of instruction this actually it.
15911 Because of this, if set_it_insn_type and in_it_block have to be used,
15912 set_it_insn_type has to be called first.
15914 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15915 determines the insn IT type depending on the inst.cond code.
15916 When a tencode () routine encodes an instruction that can be
15917 either outside an IT block, or, in the case of being inside, has to be
15918 the last one, set_it_insn_type_last () will determine the proper
15919 IT instruction type based on the inst.cond code. Otherwise,
15920 set_it_insn_type can be called for overriding that logic or
15921 for covering other cases.
15923 Calling handle_it_state () may not transition the IT block state to
15924 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15925 still queried. Instead, if the FSM determines that the state should
15926 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15927 after the tencode () function: that's what it_fsm_post_encode () does.
15929 Since in_it_block () calls the state handling function to get an
15930 updated state, an error may occur (due to invalid insns combination).
15931 In that case, inst.error is set.
15932 Therefore, inst.error has to be checked after the execution of
15933 the tencode () routine.
15935 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15936 any pending state change (if any) that didn't take place in
15937 handle_it_state () as explained above. */
15940 it_fsm_pre_encode (void)
15942 if (inst
.cond
!= COND_ALWAYS
)
15943 inst
.it_insn_type
= INSIDE_IT_INSN
;
15945 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15947 now_it
.state_handled
= 0;
15950 /* IT state FSM handling function. */
15953 handle_it_state (void)
15955 now_it
.state_handled
= 1;
15957 switch (now_it
.state
)
15959 case OUTSIDE_IT_BLOCK
:
15960 switch (inst
.it_insn_type
)
15962 case OUTSIDE_IT_INSN
:
15965 case INSIDE_IT_INSN
:
15966 case INSIDE_IT_LAST_INSN
:
15967 if (thumb_mode
== 0)
15970 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15971 as_tsktsk (_("Warning: conditional outside an IT block"\
15976 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15977 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15979 /* Automatically generate the IT instruction. */
15980 new_automatic_it_block (inst
.cond
);
15981 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15982 close_automatic_it_block ();
15986 inst
.error
= BAD_OUT_IT
;
15992 case IF_INSIDE_IT_LAST_INSN
:
15993 case NEUTRAL_IT_INSN
:
15997 now_it
.state
= MANUAL_IT_BLOCK
;
15998 now_it
.block_length
= 0;
16003 case AUTOMATIC_IT_BLOCK
:
16004 /* Three things may happen now:
16005 a) We should increment current it block size;
16006 b) We should close current it block (closing insn or 4 insns);
16007 c) We should close current it block and start a new one (due
16008 to incompatible conditions or
16009 4 insns-length block reached). */
16011 switch (inst
.it_insn_type
)
16013 case OUTSIDE_IT_INSN
:
16014 /* The closure of the block shall happen immediatelly,
16015 so any in_it_block () call reports the block as closed. */
16016 force_automatic_it_block_close ();
16019 case INSIDE_IT_INSN
:
16020 case INSIDE_IT_LAST_INSN
:
16021 case IF_INSIDE_IT_LAST_INSN
:
16022 now_it
.block_length
++;
16024 if (now_it
.block_length
> 4
16025 || !now_it_compatible (inst
.cond
))
16027 force_automatic_it_block_close ();
16028 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16029 new_automatic_it_block (inst
.cond
);
16033 now_it_add_mask (inst
.cond
);
16036 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16037 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16038 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16039 close_automatic_it_block ();
16042 case NEUTRAL_IT_INSN
:
16043 now_it
.block_length
++;
16045 if (now_it
.block_length
> 4)
16046 force_automatic_it_block_close ();
16048 now_it_add_mask (now_it
.cc
& 1);
16052 close_automatic_it_block ();
16053 now_it
.state
= MANUAL_IT_BLOCK
;
16058 case MANUAL_IT_BLOCK
:
16060 /* Check conditional suffixes. */
16061 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16064 now_it
.mask
&= 0x1f;
16065 is_last
= (now_it
.mask
== 0x10);
16067 switch (inst
.it_insn_type
)
16069 case OUTSIDE_IT_INSN
:
16070 inst
.error
= BAD_NOT_IT
;
16073 case INSIDE_IT_INSN
:
16074 if (cond
!= inst
.cond
)
16076 inst
.error
= BAD_IT_COND
;
16081 case INSIDE_IT_LAST_INSN
:
16082 case IF_INSIDE_IT_LAST_INSN
:
16083 if (cond
!= inst
.cond
)
16085 inst
.error
= BAD_IT_COND
;
16090 inst
.error
= BAD_BRANCH
;
16095 case NEUTRAL_IT_INSN
:
16096 /* The BKPT instruction is unconditional even in an IT block. */
16100 inst
.error
= BAD_IT_IT
;
16111 it_fsm_post_encode (void)
16115 if (!now_it
.state_handled
)
16116 handle_it_state ();
16118 is_last
= (now_it
.mask
== 0x10);
16121 now_it
.state
= OUTSIDE_IT_BLOCK
;
16127 force_automatic_it_block_close (void)
16129 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16131 close_automatic_it_block ();
16132 now_it
.state
= OUTSIDE_IT_BLOCK
;
16140 if (!now_it
.state_handled
)
16141 handle_it_state ();
16143 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16147 md_assemble (char *str
)
16150 const struct asm_opcode
* opcode
;
16152 /* Align the previous label if needed. */
16153 if (last_label_seen
!= NULL
)
16155 symbol_set_frag (last_label_seen
, frag_now
);
16156 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16157 S_SET_SEGMENT (last_label_seen
, now_seg
);
16160 memset (&inst
, '\0', sizeof (inst
));
16161 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16163 opcode
= opcode_lookup (&p
);
16166 /* It wasn't an instruction, but it might be a register alias of
16167 the form alias .req reg, or a Neon .dn/.qn directive. */
16168 if (! create_register_alias (str
, p
)
16169 && ! create_neon_reg_alias (str
, p
))
16170 as_bad (_("bad instruction `%s'"), str
);
16175 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16176 as_warn (_("s suffix on comparison instruction is deprecated"));
16178 /* The value which unconditional instructions should have in place of the
16179 condition field. */
16180 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16184 arm_feature_set variant
;
16186 variant
= cpu_variant
;
16187 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16188 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16189 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16190 /* Check that this instruction is supported for this CPU. */
16191 if (!opcode
->tvariant
16192 || (thumb_mode
== 1
16193 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16195 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16198 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16199 && opcode
->tencode
!= do_t_branch
)
16201 as_bad (_("Thumb does not support conditional execution"));
16205 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16207 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16208 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16209 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16211 /* Two things are addressed here.
16212 1) Implicit require narrow instructions on Thumb-1.
16213 This avoids relaxation accidentally introducing Thumb-2
16215 2) Reject wide instructions in non Thumb-2 cores. */
16216 if (inst
.size_req
== 0)
16218 else if (inst
.size_req
== 4)
16220 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16226 inst
.instruction
= opcode
->tvalue
;
16228 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16230 /* Prepare the it_insn_type for those encodings that don't set
16232 it_fsm_pre_encode ();
16234 opcode
->tencode ();
16236 it_fsm_post_encode ();
16239 if (!(inst
.error
|| inst
.relax
))
16241 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16242 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16243 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16245 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16250 /* Something has gone badly wrong if we try to relax a fixed size
16252 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16254 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16255 *opcode
->tvariant
);
16256 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16257 set those bits when Thumb-2 32-bit instructions are seen. ie.
16258 anything other than bl/blx and v6-M instructions.
16259 This is overly pessimistic for relaxable instructions. */
16260 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16262 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16263 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16264 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16267 check_neon_suffixes
;
16271 mapping_state (MAP_THUMB
);
16274 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16278 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16279 is_bx
= (opcode
->aencode
== do_bx
);
16281 /* Check that this instruction is supported for this CPU. */
16282 if (!(is_bx
&& fix_v4bx
)
16283 && !(opcode
->avariant
&&
16284 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16286 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16291 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16295 inst
.instruction
= opcode
->avalue
;
16296 if (opcode
->tag
== OT_unconditionalF
)
16297 inst
.instruction
|= 0xF << 28;
16299 inst
.instruction
|= inst
.cond
<< 28;
16300 inst
.size
= INSN_SIZE
;
16301 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16303 it_fsm_pre_encode ();
16304 opcode
->aencode ();
16305 it_fsm_post_encode ();
16307 /* Arm mode bx is marked as both v4T and v5 because it's still required
16308 on a hypothetical non-thumb v5 core. */
16310 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16312 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16313 *opcode
->avariant
);
16315 check_neon_suffixes
;
16319 mapping_state (MAP_ARM
);
16324 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16332 check_it_blocks_finished (void)
16337 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16338 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16339 == MANUAL_IT_BLOCK
)
16341 as_warn (_("section '%s' finished with an open IT block."),
16345 if (now_it
.state
== MANUAL_IT_BLOCK
)
16346 as_warn (_("file finished with an open IT block."));
16350 /* Various frobbings of labels and their addresses. */
16353 arm_start_line_hook (void)
16355 last_label_seen
= NULL
;
16359 arm_frob_label (symbolS
* sym
)
16361 last_label_seen
= sym
;
16363 ARM_SET_THUMB (sym
, thumb_mode
);
16365 #if defined OBJ_COFF || defined OBJ_ELF
16366 ARM_SET_INTERWORK (sym
, support_interwork
);
16369 force_automatic_it_block_close ();
16371 /* Note - do not allow local symbols (.Lxxx) to be labelled
16372 as Thumb functions. This is because these labels, whilst
16373 they exist inside Thumb code, are not the entry points for
16374 possible ARM->Thumb calls. Also, these labels can be used
16375 as part of a computed goto or switch statement. eg gcc
16376 can generate code that looks like this:
16378 ldr r2, [pc, .Laaa]
16388 The first instruction loads the address of the jump table.
16389 The second instruction converts a table index into a byte offset.
16390 The third instruction gets the jump address out of the table.
16391 The fourth instruction performs the jump.
16393 If the address stored at .Laaa is that of a symbol which has the
16394 Thumb_Func bit set, then the linker will arrange for this address
16395 to have the bottom bit set, which in turn would mean that the
16396 address computation performed by the third instruction would end
16397 up with the bottom bit set. Since the ARM is capable of unaligned
16398 word loads, the instruction would then load the incorrect address
16399 out of the jump table, and chaos would ensue. */
16400 if (label_is_thumb_function_name
16401 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16402 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16404 /* When the address of a Thumb function is taken the bottom
16405 bit of that address should be set. This will allow
16406 interworking between Arm and Thumb functions to work
16409 THUMB_SET_FUNC (sym
, 1);
16411 label_is_thumb_function_name
= FALSE
;
16414 dwarf2_emit_label (sym
);
16418 arm_data_in_code (void)
16420 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16422 *input_line_pointer
= '/';
16423 input_line_pointer
+= 5;
16424 *input_line_pointer
= 0;
16432 arm_canonicalize_symbol_name (char * name
)
16436 if (thumb_mode
&& (len
= strlen (name
)) > 5
16437 && streq (name
+ len
- 5, "/data"))
16438 *(name
+ len
- 5) = 0;
16443 /* Table of all register names defined by default. The user can
16444 define additional names with .req. Note that all register names
16445 should appear in both upper and lowercase variants. Some registers
16446 also have mixed-case names. */
16448 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16449 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16450 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16451 #define REGSET(p,t) \
16452 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16453 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16454 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16455 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16456 #define REGSETH(p,t) \
16457 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16458 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16459 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16460 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16461 #define REGSET2(p,t) \
16462 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16463 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16464 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16465 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16466 #define SPLRBANK(base,bank,t) \
16467 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16468 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16469 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16470 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16471 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16472 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16474 static const struct reg_entry reg_names
[] =
16476 /* ARM integer registers. */
16477 REGSET(r
, RN
), REGSET(R
, RN
),
16479 /* ATPCS synonyms. */
16480 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16481 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16482 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16484 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16485 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16486 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16488 /* Well-known aliases. */
16489 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16490 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16492 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16493 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16495 /* Coprocessor numbers. */
16496 REGSET(p
, CP
), REGSET(P
, CP
),
16498 /* Coprocessor register numbers. The "cr" variants are for backward
16500 REGSET(c
, CN
), REGSET(C
, CN
),
16501 REGSET(cr
, CN
), REGSET(CR
, CN
),
16503 /* ARM banked registers. */
16504 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16505 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16506 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16507 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16508 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16509 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16510 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16512 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16513 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16514 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16515 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16516 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16517 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16518 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16519 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16521 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16522 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16523 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16524 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16525 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16526 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16527 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16528 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16529 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16531 /* FPA registers. */
16532 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16533 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16535 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16536 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16538 /* VFP SP registers. */
16539 REGSET(s
,VFS
), REGSET(S
,VFS
),
16540 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16542 /* VFP DP Registers. */
16543 REGSET(d
,VFD
), REGSET(D
,VFD
),
16544 /* Extra Neon DP registers. */
16545 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16547 /* Neon QP registers. */
16548 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16550 /* VFP control registers. */
16551 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16552 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16553 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16554 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16555 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16556 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16558 /* Maverick DSP coprocessor registers. */
16559 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16560 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16562 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16563 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16564 REGDEF(dspsc
,0,DSPSC
),
16566 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16567 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16568 REGDEF(DSPSC
,0,DSPSC
),
16570 /* iWMMXt data registers - p0, c0-15. */
16571 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16573 /* iWMMXt control registers - p1, c0-3. */
16574 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16575 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16576 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16577 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16579 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16580 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16581 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16582 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16583 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16585 /* XScale accumulator registers. */
16586 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16592 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16593 within psr_required_here. */
16594 static const struct asm_psr psrs
[] =
16596 /* Backward compatibility notation. Note that "all" is no longer
16597 truly all possible PSR bits. */
16598 {"all", PSR_c
| PSR_f
},
16602 /* Individual flags. */
16608 /* Combinations of flags. */
16609 {"fs", PSR_f
| PSR_s
},
16610 {"fx", PSR_f
| PSR_x
},
16611 {"fc", PSR_f
| PSR_c
},
16612 {"sf", PSR_s
| PSR_f
},
16613 {"sx", PSR_s
| PSR_x
},
16614 {"sc", PSR_s
| PSR_c
},
16615 {"xf", PSR_x
| PSR_f
},
16616 {"xs", PSR_x
| PSR_s
},
16617 {"xc", PSR_x
| PSR_c
},
16618 {"cf", PSR_c
| PSR_f
},
16619 {"cs", PSR_c
| PSR_s
},
16620 {"cx", PSR_c
| PSR_x
},
16621 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16622 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16623 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16624 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16625 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16626 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16627 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16628 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16629 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16630 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16631 {"scf", PSR_s
| PSR_c
| PSR_f
},
16632 {"scx", PSR_s
| PSR_c
| PSR_x
},
16633 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16634 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16635 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16636 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16637 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16638 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16639 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16640 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16641 {"csf", PSR_c
| PSR_s
| PSR_f
},
16642 {"csx", PSR_c
| PSR_s
| PSR_x
},
16643 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16644 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16645 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16646 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16647 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16648 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16649 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16650 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16651 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16652 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16653 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16654 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16655 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16656 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16657 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16658 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16659 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16660 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16661 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16662 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16663 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16664 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16665 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16666 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16667 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16668 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16671 /* Table of V7M psr names. */
16672 static const struct asm_psr v7m_psrs
[] =
16674 {"apsr", 0 }, {"APSR", 0 },
16675 {"iapsr", 1 }, {"IAPSR", 1 },
16676 {"eapsr", 2 }, {"EAPSR", 2 },
16677 {"psr", 3 }, {"PSR", 3 },
16678 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16679 {"ipsr", 5 }, {"IPSR", 5 },
16680 {"epsr", 6 }, {"EPSR", 6 },
16681 {"iepsr", 7 }, {"IEPSR", 7 },
16682 {"msp", 8 }, {"MSP", 8 },
16683 {"psp", 9 }, {"PSP", 9 },
16684 {"primask", 16}, {"PRIMASK", 16},
16685 {"basepri", 17}, {"BASEPRI", 17},
16686 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16687 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16688 {"faultmask", 19}, {"FAULTMASK", 19},
16689 {"control", 20}, {"CONTROL", 20}
16692 /* Table of all shift-in-operand names. */
16693 static const struct asm_shift_name shift_names
[] =
16695 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16696 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16697 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16698 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16699 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16700 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16703 /* Table of all explicit relocation names. */
16705 static struct reloc_entry reloc_names
[] =
16707 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16708 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16709 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16710 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16711 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16712 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16713 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16714 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16715 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16716 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16717 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16718 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16719 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16720 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16721 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16722 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16723 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16724 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16728 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16729 static const struct asm_cond conds
[] =
16733 {"cs", 0x2}, {"hs", 0x2},
16734 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16748 static struct asm_barrier_opt barrier_opt_names
[] =
16750 { "sy", 0xf }, { "SY", 0xf },
16751 { "un", 0x7 }, { "UN", 0x7 },
16752 { "st", 0xe }, { "ST", 0xe },
16753 { "unst", 0x6 }, { "UNST", 0x6 },
16754 { "ish", 0xb }, { "ISH", 0xb },
16755 { "sh", 0xb }, { "SH", 0xb },
16756 { "ishst", 0xa }, { "ISHST", 0xa },
16757 { "shst", 0xa }, { "SHST", 0xa },
16758 { "nsh", 0x7 }, { "NSH", 0x7 },
16759 { "nshst", 0x6 }, { "NSHST", 0x6 },
16760 { "osh", 0x3 }, { "OSH", 0x3 },
16761 { "oshst", 0x2 }, { "OSHST", 0x2 }
16764 /* Table of ARM-format instructions. */
16766 /* Macros for gluing together operand strings. N.B. In all cases
16767 other than OPS0, the trailing OP_stop comes from default
16768 zero-initialization of the unspecified elements of the array. */
16769 #define OPS0() { OP_stop, }
16770 #define OPS1(a) { OP_##a, }
16771 #define OPS2(a,b) { OP_##a,OP_##b, }
16772 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16773 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16774 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16775 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16777 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16778 This is useful when mixing operands for ARM and THUMB, i.e. using the
16779 MIX_ARM_THUMB_OPERANDS macro.
16780 In order to use these macros, prefix the number of operands with _
16782 #define OPS_1(a) { a, }
16783 #define OPS_2(a,b) { a,b, }
16784 #define OPS_3(a,b,c) { a,b,c, }
16785 #define OPS_4(a,b,c,d) { a,b,c,d, }
16786 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16787 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16789 /* These macros abstract out the exact format of the mnemonic table and
16790 save some repeated characters. */
16792 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16793 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16794 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16795 THUMB_VARIANT, do_##ae, do_##te }
16797 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16798 a T_MNEM_xyz enumerator. */
16799 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16800 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16801 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16802 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16804 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16805 infix after the third character. */
16806 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16807 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16808 THUMB_VARIANT, do_##ae, do_##te }
16809 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16810 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16811 THUMB_VARIANT, do_##ae, do_##te }
16812 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16813 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16814 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16815 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16816 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16817 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16818 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16819 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16821 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16822 appear in the condition table. */
16823 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16824 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16825 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16827 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16828 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16829 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16830 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16831 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16832 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16833 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16834 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16835 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16836 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16837 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16838 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16839 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16840 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16841 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16842 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16843 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16844 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16845 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16846 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16848 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16849 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16850 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16851 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16853 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16854 field is still 0xE. Many of the Thumb variants can be executed
16855 conditionally, so this is checked separately. */
16856 #define TUE(mnem, op, top, nops, ops, ae, te) \
16857 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16858 THUMB_VARIANT, do_##ae, do_##te }
16860 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16861 condition code field. */
16862 #define TUF(mnem, op, top, nops, ops, ae, te) \
16863 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16864 THUMB_VARIANT, do_##ae, do_##te }
16866 /* ARM-only variants of all the above. */
16867 #define CE(mnem, op, nops, ops, ae) \
16868 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16870 #define C3(mnem, op, nops, ops, ae) \
16871 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16873 /* Legacy mnemonics that always have conditional infix after the third
16875 #define CL(mnem, op, nops, ops, ae) \
16876 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16877 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16879 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16880 #define cCE(mnem, op, nops, ops, ae) \
16881 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16883 /* Legacy coprocessor instructions where conditional infix and conditional
16884 suffix are ambiguous. For consistency this includes all FPA instructions,
16885 not just the potentially ambiguous ones. */
16886 #define cCL(mnem, op, nops, ops, ae) \
16887 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16888 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16890 /* Coprocessor, takes either a suffix or a position-3 infix
16891 (for an FPA corner case). */
16892 #define C3E(mnem, op, nops, ops, ae) \
16893 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16894 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16896 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16897 { m1 #m2 m3, OPS##nops ops, \
16898 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16899 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16901 #define CM(m1, m2, op, nops, ops, ae) \
16902 xCM_ (m1, , m2, op, nops, ops, ae), \
16903 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16904 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16905 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16906 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16907 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16908 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16909 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16910 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16911 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16912 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16913 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16914 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16915 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16916 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16917 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16918 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16919 xCM_ (m1, le, m2, op, nops, ops, ae), \
16920 xCM_ (m1, al, m2, op, nops, ops, ae)
16922 #define UE(mnem, op, nops, ops, ae) \
16923 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16925 #define UF(mnem, op, nops, ops, ae) \
16926 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16928 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16929 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16930 use the same encoding function for each. */
16931 #define NUF(mnem, op, nops, ops, enc) \
16932 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16933 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16935 /* Neon data processing, version which indirects through neon_enc_tab for
16936 the various overloaded versions of opcodes. */
16937 #define nUF(mnem, op, nops, ops, enc) \
16938 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16939 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16941 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16943 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16944 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16945 THUMB_VARIANT, do_##enc, do_##enc }
16947 #define NCE(mnem, op, nops, ops, enc) \
16948 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16950 #define NCEF(mnem, op, nops, ops, enc) \
16951 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16953 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16954 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16955 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16956 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16958 #define nCE(mnem, op, nops, ops, enc) \
16959 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16961 #define nCEF(mnem, op, nops, ops, enc) \
16962 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16966 static const struct asm_opcode insns
[] =
16968 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16969 #define THUMB_VARIANT &arm_ext_v4t
16970 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16971 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16972 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16973 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16974 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16975 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16976 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16977 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16978 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16979 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16980 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16981 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16982 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16983 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16984 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16985 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16987 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16988 for setting PSR flag bits. They are obsolete in V6 and do not
16989 have Thumb equivalents. */
16990 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16991 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16992 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16993 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16994 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16995 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16996 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16997 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16998 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17000 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17001 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17002 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17003 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17005 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17006 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17007 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17009 OP_ADDRGLDR
),ldst
, t_ldst
),
17010 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17012 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17013 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17014 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17015 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17016 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17017 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17019 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17020 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17021 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17022 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17025 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17026 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17027 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17029 /* Thumb-compatibility pseudo ops. */
17030 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17031 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17032 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17033 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17034 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17035 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17036 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17037 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17038 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17039 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17040 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17041 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17043 /* These may simplify to neg. */
17044 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17045 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17047 #undef THUMB_VARIANT
17048 #define THUMB_VARIANT & arm_ext_v6
17050 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17052 /* V1 instructions with no Thumb analogue prior to V6T2. */
17053 #undef THUMB_VARIANT
17054 #define THUMB_VARIANT & arm_ext_v6t2
17056 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17057 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17058 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17060 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17061 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17062 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17063 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17065 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17066 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17068 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17069 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17071 /* V1 instructions with no Thumb analogue at all. */
17072 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17073 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17075 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17076 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17077 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17078 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17079 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17080 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17081 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17082 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17085 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17086 #undef THUMB_VARIANT
17087 #define THUMB_VARIANT & arm_ext_v4t
17089 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17090 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17092 #undef THUMB_VARIANT
17093 #define THUMB_VARIANT & arm_ext_v6t2
17095 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17096 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17098 /* Generic coprocessor instructions. */
17099 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17100 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17101 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17102 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17103 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17104 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17105 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17108 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17110 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17111 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17114 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17115 #undef THUMB_VARIANT
17116 #define THUMB_VARIANT & arm_ext_msr
17118 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17119 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17122 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17123 #undef THUMB_VARIANT
17124 #define THUMB_VARIANT & arm_ext_v6t2
17126 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17127 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17128 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17129 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17130 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17131 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17132 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17133 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17136 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17137 #undef THUMB_VARIANT
17138 #define THUMB_VARIANT & arm_ext_v4t
17140 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17141 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17142 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17143 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17144 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17145 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17148 #define ARM_VARIANT & arm_ext_v4t_5
17150 /* ARM Architecture 4T. */
17151 /* Note: bx (and blx) are required on V5, even if the processor does
17152 not support Thumb. */
17153 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17156 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17157 #undef THUMB_VARIANT
17158 #define THUMB_VARIANT & arm_ext_v5t
17160 /* Note: blx has 2 variants; the .value coded here is for
17161 BLX(2). Only this variant has conditional execution. */
17162 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17163 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17165 #undef THUMB_VARIANT
17166 #define THUMB_VARIANT & arm_ext_v6t2
17168 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17169 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17170 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17171 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17172 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17173 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17174 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17175 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17178 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17179 #undef THUMB_VARIANT
17180 #define THUMB_VARIANT &arm_ext_v5exp
17182 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17183 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17184 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17185 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17187 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17188 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17190 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17191 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17192 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17193 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17195 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17196 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17197 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17198 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17200 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17201 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17203 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17204 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17205 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17206 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17209 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17210 #undef THUMB_VARIANT
17211 #define THUMB_VARIANT &arm_ext_v6t2
17213 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17214 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17216 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17217 ADDRGLDRS
), ldrd
, t_ldstd
),
17219 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17220 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17223 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17225 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17228 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17229 #undef THUMB_VARIANT
17230 #define THUMB_VARIANT & arm_ext_v6
17232 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17233 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17234 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17235 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17236 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17237 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17238 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17239 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17240 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17241 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17243 #undef THUMB_VARIANT
17244 #define THUMB_VARIANT & arm_ext_v6t2
17246 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17247 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17249 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17250 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17252 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17253 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17255 /* ARM V6 not included in V7M. */
17256 #undef THUMB_VARIANT
17257 #define THUMB_VARIANT & arm_ext_v6_notm
17258 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17259 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17260 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17261 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17262 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17263 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17264 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17265 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17266 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17267 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17268 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17269 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17271 /* ARM V6 not included in V7M (eg. integer SIMD). */
17272 #undef THUMB_VARIANT
17273 #define THUMB_VARIANT & arm_ext_v6_dsp
17274 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17275 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17276 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17277 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17278 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17279 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17280 /* Old name for QASX. */
17281 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17282 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17283 /* Old name for QSAX. */
17284 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17285 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17286 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17287 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17288 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17289 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17290 /* Old name for SASX. */
17291 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17292 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17293 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17294 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17295 /* Old name for SHASX. */
17296 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17297 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17298 /* Old name for SHSAX. */
17299 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17300 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17301 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17302 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17303 /* Old name for SSAX. */
17304 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17305 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17306 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17307 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17308 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17309 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17310 /* Old name for UASX. */
17311 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17312 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17313 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17314 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17315 /* Old name for UHASX. */
17316 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17317 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17318 /* Old name for UHSAX. */
17319 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17320 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17321 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17322 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17323 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17324 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17325 /* Old name for UQASX. */
17326 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17327 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17328 /* Old name for UQSAX. */
17329 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17330 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17331 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17332 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17333 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17334 /* Old name for USAX. */
17335 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17336 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17337 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17338 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17339 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17340 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17341 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17342 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17343 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17344 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17345 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17346 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17347 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17348 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17349 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17350 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17351 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17352 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17353 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17354 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17355 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17356 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17357 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17358 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17359 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17360 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17361 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17362 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17363 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17364 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17365 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17366 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17367 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17368 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17371 #define ARM_VARIANT & arm_ext_v6k
17372 #undef THUMB_VARIANT
17373 #define THUMB_VARIANT & arm_ext_v6k
17375 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17376 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17377 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17378 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17380 #undef THUMB_VARIANT
17381 #define THUMB_VARIANT & arm_ext_v6_notm
17382 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17384 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17385 RRnpcb
), strexd
, t_strexd
),
17387 #undef THUMB_VARIANT
17388 #define THUMB_VARIANT & arm_ext_v6t2
17389 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17391 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17393 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17395 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17397 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17400 #define ARM_VARIANT & arm_ext_sec
17401 #undef THUMB_VARIANT
17402 #define THUMB_VARIANT & arm_ext_sec
17404 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17407 #define ARM_VARIANT & arm_ext_virt
17408 #undef THUMB_VARIANT
17409 #define THUMB_VARIANT & arm_ext_virt
17411 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17412 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17415 #define ARM_VARIANT & arm_ext_v6t2
17416 #undef THUMB_VARIANT
17417 #define THUMB_VARIANT & arm_ext_v6t2
17419 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17420 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17421 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17422 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17424 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17425 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17426 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17427 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17429 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17430 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17431 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17432 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17434 /* Thumb-only instructions. */
17436 #define ARM_VARIANT NULL
17437 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17438 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17440 /* ARM does not really have an IT instruction, so always allow it.
17441 The opcode is copied from Thumb in order to allow warnings in
17442 -mimplicit-it=[never | arm] modes. */
17444 #define ARM_VARIANT & arm_ext_v1
17446 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17447 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17448 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17449 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17450 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17451 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17452 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17453 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17454 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17455 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17456 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17457 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17458 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17459 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17460 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17461 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17462 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17463 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17465 /* Thumb2 only instructions. */
17467 #define ARM_VARIANT NULL
17469 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17470 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17471 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17472 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17473 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17474 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17476 /* Hardware division instructions. */
17478 #define ARM_VARIANT & arm_ext_adiv
17479 #undef THUMB_VARIANT
17480 #define THUMB_VARIANT & arm_ext_div
17482 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17483 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17485 /* ARM V6M/V7 instructions. */
17487 #define ARM_VARIANT & arm_ext_barrier
17488 #undef THUMB_VARIANT
17489 #define THUMB_VARIANT & arm_ext_barrier
17491 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17492 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17493 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17495 /* ARM V7 instructions. */
17497 #define ARM_VARIANT & arm_ext_v7
17498 #undef THUMB_VARIANT
17499 #define THUMB_VARIANT & arm_ext_v7
17501 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17502 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17505 #define ARM_VARIANT & arm_ext_mp
17506 #undef THUMB_VARIANT
17507 #define THUMB_VARIANT & arm_ext_mp
17509 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17512 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17514 cCE("wfs", e200110
, 1, (RR
), rd
),
17515 cCE("rfs", e300110
, 1, (RR
), rd
),
17516 cCE("wfc", e400110
, 1, (RR
), rd
),
17517 cCE("rfc", e500110
, 1, (RR
), rd
),
17519 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17520 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17521 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17522 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17524 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17525 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17526 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17527 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17529 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17530 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17531 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17532 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17533 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17534 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17535 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17536 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17537 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17538 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17539 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17540 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17542 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17543 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17544 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17545 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17546 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17547 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17548 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17549 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17550 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17551 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17552 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17553 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17555 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17556 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17557 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17558 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17559 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17560 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17561 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17562 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17563 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17564 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17565 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17566 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17568 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17569 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17570 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17571 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17572 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17573 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17574 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17575 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17576 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17577 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17578 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17579 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17581 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17582 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17583 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17584 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17585 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17586 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17587 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17588 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17589 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17590 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17591 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17592 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17594 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17595 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17596 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17597 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17598 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17599 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17600 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17601 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17602 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17603 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17604 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17605 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17607 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17608 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17609 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17610 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17611 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17612 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17613 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17614 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17615 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17616 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17617 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17618 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17620 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17621 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17622 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17623 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17624 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17625 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17626 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17627 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17628 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17629 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17630 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17631 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17633 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17634 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17635 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17636 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17637 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17641 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17646 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17649 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17650 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17654 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17659 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17662 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17663 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17667 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17672 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17675 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17676 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17680 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17685 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17686 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17687 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17688 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17689 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17690 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17691 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17692 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17693 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17694 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17695 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17696 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17698 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17699 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17700 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17701 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17702 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17703 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17704 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17705 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17706 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17711 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17713 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17714 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17715 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17716 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17717 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17718 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17719 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17720 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17721 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17722 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17724 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17725 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17726 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17727 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17728 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17729 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17730 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17731 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17732 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17733 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17734 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17735 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17737 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17738 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17739 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17740 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17741 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17742 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17743 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17744 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17745 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17746 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17747 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17748 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17750 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17751 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17752 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17753 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17754 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17755 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17756 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17757 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17758 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17759 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17760 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17761 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17763 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17764 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17765 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17766 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17767 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17768 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17769 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17770 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17771 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17772 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17773 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17774 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17776 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17777 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17778 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17779 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17780 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17781 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17782 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17783 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17784 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17785 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17786 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17787 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17789 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17790 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17791 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17792 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17793 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17794 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17795 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17796 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17797 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17798 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17799 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17800 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17802 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17803 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17804 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17805 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17806 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17807 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17808 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17809 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17810 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17811 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17812 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17813 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17815 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17816 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17817 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17818 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17819 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17820 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17821 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17822 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17823 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17824 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17825 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17826 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17828 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17829 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17830 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17831 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17832 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17833 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17834 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17835 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17836 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17837 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17838 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17839 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17841 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17842 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17843 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17844 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17845 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17849 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17854 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17855 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17856 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17857 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17858 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17859 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17860 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17861 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17862 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17863 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17864 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17865 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17867 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17868 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17869 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17870 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17871 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17872 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17873 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17874 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17875 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17876 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17877 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17878 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17880 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17881 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17882 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17883 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17884 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17885 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17886 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17887 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17888 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17889 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17890 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17891 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17893 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17894 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17895 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17896 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17897 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17898 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17899 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17900 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17901 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17902 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17903 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17904 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17906 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17907 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17908 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17909 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17911 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17912 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17913 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17914 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17915 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17916 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17917 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17918 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17919 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17920 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17921 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17922 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17924 /* The implementation of the FIX instruction is broken on some
17925 assemblers, in that it accepts a precision specifier as well as a
17926 rounding specifier, despite the fact that this is meaningless.
17927 To be more compatible, we accept it as well, though of course it
17928 does not set any bits. */
17929 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17930 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17931 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17932 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17933 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17934 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17935 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17936 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17937 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17938 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17939 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17940 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17941 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17943 /* Instructions that were new with the real FPA, call them V2. */
17945 #define ARM_VARIANT & fpu_fpa_ext_v2
17947 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17948 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17949 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17950 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17951 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17952 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17955 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17957 /* Moves and type conversions. */
17958 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17959 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17960 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17961 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17962 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17963 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17964 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17965 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17966 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17967 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17968 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17969 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17970 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17971 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17973 /* Memory operations. */
17974 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17975 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17976 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17977 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17978 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17979 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17980 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17981 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17982 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17983 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17984 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17985 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17986 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17987 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17988 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17989 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17990 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17991 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17993 /* Monadic operations. */
17994 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17995 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17996 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17998 /* Dyadic operations. */
17999 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18000 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18001 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18002 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18003 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18004 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18005 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18006 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18007 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18010 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18011 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18012 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18013 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18015 /* Double precision load/store are still present on single precision
18016 implementations. */
18017 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18018 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18019 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18020 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18021 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18022 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18023 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18024 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18025 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18026 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18029 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18031 /* Moves and type conversions. */
18032 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18033 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18034 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18035 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18036 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18037 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18038 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18039 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18040 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18041 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18042 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18043 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18044 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18046 /* Monadic operations. */
18047 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18048 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18049 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18051 /* Dyadic operations. */
18052 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18053 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18054 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18055 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18056 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18057 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18058 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18059 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18060 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18063 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18064 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18065 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18066 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18069 #define ARM_VARIANT & fpu_vfp_ext_v2
18071 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18072 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18073 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18074 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18076 /* Instructions which may belong to either the Neon or VFP instruction sets.
18077 Individual encoder functions perform additional architecture checks. */
18079 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18080 #undef THUMB_VARIANT
18081 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18083 /* These mnemonics are unique to VFP. */
18084 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18085 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18086 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18087 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18088 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18089 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18090 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18091 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18092 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18093 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18095 /* Mnemonics shared by Neon and VFP. */
18096 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18097 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18098 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18100 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18101 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18103 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18104 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18106 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18107 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18108 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18109 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18110 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18111 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18112 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18113 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18115 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
18116 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18117 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18118 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18121 /* NOTE: All VMOV encoding is special-cased! */
18122 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18123 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18125 #undef THUMB_VARIANT
18126 #define THUMB_VARIANT & fpu_neon_ext_v1
18128 #define ARM_VARIANT & fpu_neon_ext_v1
18130 /* Data processing with three registers of the same length. */
18131 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18132 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18133 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18134 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18135 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18136 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18137 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18138 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18139 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18140 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18141 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18142 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18143 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18144 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18145 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18146 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18147 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18148 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18149 /* If not immediate, fall back to neon_dyadic_i64_su.
18150 shl_imm should accept I8 I16 I32 I64,
18151 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18152 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18153 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18154 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18155 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18156 /* Logic ops, types optional & ignored. */
18157 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18158 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18159 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18160 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18161 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18162 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18163 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18164 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18165 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18166 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18167 /* Bitfield ops, untyped. */
18168 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18169 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18170 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18171 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18172 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18173 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18174 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18175 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18176 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18177 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18178 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18179 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18180 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18181 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18182 back to neon_dyadic_if_su. */
18183 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18184 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18185 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18186 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18187 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18188 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18189 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18190 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18191 /* Comparison. Type I8 I16 I32 F32. */
18192 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18193 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18194 /* As above, D registers only. */
18195 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18196 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18197 /* Int and float variants, signedness unimportant. */
18198 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18199 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18200 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18201 /* Add/sub take types I8 I16 I32 I64 F32. */
18202 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18203 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18204 /* vtst takes sizes 8, 16, 32. */
18205 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18206 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18207 /* VMUL takes I8 I16 I32 F32 P8. */
18208 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18209 /* VQD{R}MULH takes S16 S32. */
18210 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18211 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18212 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18213 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18214 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18215 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18216 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18217 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18218 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18219 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18220 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18221 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18222 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18223 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18224 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18225 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18227 /* Two address, int/float. Types S8 S16 S32 F32. */
18228 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18229 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18231 /* Data processing with two registers and a shift amount. */
18232 /* Right shifts, and variants with rounding.
18233 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18234 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18235 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18236 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18237 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18238 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18239 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18240 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18241 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18242 /* Shift and insert. Sizes accepted 8 16 32 64. */
18243 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18244 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18245 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18246 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18247 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18248 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18249 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18250 /* Right shift immediate, saturating & narrowing, with rounding variants.
18251 Types accepted S16 S32 S64 U16 U32 U64. */
18252 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18253 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18254 /* As above, unsigned. Types accepted S16 S32 S64. */
18255 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18256 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18257 /* Right shift narrowing. Types accepted I16 I32 I64. */
18258 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18259 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18260 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18261 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18262 /* CVT with optional immediate for fixed-point variant. */
18263 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18265 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18266 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18268 /* Data processing, three registers of different lengths. */
18269 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18270 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18271 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18272 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18273 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18274 /* If not scalar, fall back to neon_dyadic_long.
18275 Vector types as above, scalar types S16 S32 U16 U32. */
18276 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18277 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18278 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18279 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18280 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18281 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18282 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18283 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18284 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18285 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18286 /* Saturating doubling multiplies. Types S16 S32. */
18287 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18288 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18289 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18290 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18291 S16 S32 U16 U32. */
18292 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18294 /* Extract. Size 8. */
18295 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18296 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18298 /* Two registers, miscellaneous. */
18299 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18300 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18301 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18302 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18303 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18304 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18305 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18306 /* Vector replicate. Sizes 8 16 32. */
18307 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18308 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18309 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18310 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18311 /* VMOVN. Types I16 I32 I64. */
18312 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18313 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18314 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18315 /* VQMOVUN. Types S16 S32 S64. */
18316 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18317 /* VZIP / VUZP. Sizes 8 16 32. */
18318 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18319 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18320 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18321 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18322 /* VQABS / VQNEG. Types S8 S16 S32. */
18323 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18324 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18325 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18326 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18327 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18328 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18329 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18330 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18331 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18332 /* Reciprocal estimates. Types U32 F32. */
18333 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18334 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18335 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18336 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18337 /* VCLS. Types S8 S16 S32. */
18338 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18339 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18340 /* VCLZ. Types I8 I16 I32. */
18341 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18342 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18343 /* VCNT. Size 8. */
18344 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18345 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18346 /* Two address, untyped. */
18347 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18348 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18349 /* VTRN. Sizes 8 16 32. */
18350 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18351 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18353 /* Table lookup. Size 8. */
18354 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18355 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18357 #undef THUMB_VARIANT
18358 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18360 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18362 /* Neon element/structure load/store. */
18363 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18364 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18365 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18366 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18367 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18368 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18369 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18370 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18372 #undef THUMB_VARIANT
18373 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18375 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18376 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18377 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18378 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18379 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18380 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18381 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18382 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18383 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18384 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18386 #undef THUMB_VARIANT
18387 #define THUMB_VARIANT & fpu_vfp_ext_v3
18389 #define ARM_VARIANT & fpu_vfp_ext_v3
18391 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18392 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18393 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18394 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18395 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18396 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18397 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18398 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18399 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18402 #define ARM_VARIANT &fpu_vfp_ext_fma
18403 #undef THUMB_VARIANT
18404 #define THUMB_VARIANT &fpu_vfp_ext_fma
18405 /* Mnemonics shared by Neon and VFP. These are included in the
18406 VFP FMA variant; NEON and VFP FMA always includes the NEON
18407 FMA instructions. */
18408 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18409 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18410 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18411 the v form should always be used. */
18412 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18413 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18414 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18415 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18416 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18417 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18419 #undef THUMB_VARIANT
18421 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18423 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18424 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18425 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18426 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18427 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18428 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18429 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18430 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18433 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18435 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18436 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18437 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18438 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18439 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18440 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18441 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18442 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18443 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18444 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18445 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18446 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18447 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18448 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18449 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18450 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18451 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18452 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18453 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18454 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18455 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18456 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18457 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18458 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18459 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18460 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18461 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18462 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18463 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18464 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18465 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18466 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18467 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18468 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18469 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18470 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18471 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18472 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18473 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18474 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18475 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18476 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18477 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18478 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18479 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18480 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18481 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18482 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18483 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18484 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18485 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18486 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18487 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18488 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18489 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18490 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18491 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18492 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18493 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18494 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18495 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18496 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18497 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18498 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18499 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18500 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18501 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18502 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18503 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18504 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18505 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18506 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18507 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18508 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18509 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18510 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18511 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18512 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18513 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18514 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18515 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18516 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18517 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18518 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18519 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18520 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18521 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18522 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18523 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18524 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18525 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18526 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18527 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18528 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18529 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18530 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18531 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18532 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18533 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18534 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18535 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18536 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18537 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18538 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18539 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18540 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18541 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18542 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18543 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18544 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18545 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18546 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18547 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18548 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18549 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18550 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18551 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18552 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18553 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18554 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18555 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18556 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18557 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18558 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18559 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18560 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18561 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18562 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18563 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18564 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18565 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18566 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18567 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18568 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18569 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18570 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18571 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18572 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18573 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18574 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18575 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18576 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18577 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18578 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18579 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18580 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18581 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18582 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18583 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18585 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18586 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18587 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18588 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18589 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18590 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18591 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18592 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18599 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18601 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18602 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18603 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18604 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18605 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18606 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18607 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18609 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18610 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18611 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18612 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18613 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18614 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18615 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18616 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18617 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18618 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18619 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18620 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18621 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18622 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18623 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18624 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18625 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18626 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18627 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18628 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18629 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18630 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18631 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18632 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18633 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18634 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18635 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18636 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18637 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18638 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18639 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18640 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18641 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18642 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18643 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18644 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18645 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18646 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18647 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18648 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18649 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18650 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18651 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18652 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18653 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18654 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18655 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18656 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18657 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18660 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18662 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18663 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18664 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18665 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18666 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18667 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18668 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18669 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18670 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18671 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18672 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18673 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18674 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18675 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18676 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18677 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18678 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18679 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18680 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18681 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18682 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18683 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18684 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18685 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18686 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18687 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18688 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18689 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18690 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18691 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18692 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18693 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18694 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18695 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18696 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18697 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18698 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18699 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18700 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18701 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18702 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18703 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18704 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18705 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18706 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18707 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18708 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18709 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18710 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18711 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18712 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18713 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18714 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18715 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18716 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18717 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18718 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18719 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18720 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18721 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18722 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18723 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18724 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18725 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18726 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18727 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18728 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18729 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18730 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18731 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18732 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18733 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18734 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18735 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18736 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18737 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18740 #undef THUMB_VARIANT
18767 /* MD interface: bits in the object file. */
18769 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18770 for use in the a.out file, and stores them in the array pointed to by buf.
18771 This knows about the endian-ness of the target machine and does
18772 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18773 2 (short) and 4 (long) Floating numbers are put out as a series of
18774 LITTLENUMS (shorts, here at least). */
18777 md_number_to_chars (char * buf
, valueT val
, int n
)
18779 if (target_big_endian
)
18780 number_to_chars_bigendian (buf
, val
, n
);
18782 number_to_chars_littleendian (buf
, val
, n
);
18786 md_chars_to_number (char * buf
, int n
)
18789 unsigned char * where
= (unsigned char *) buf
;
18791 if (target_big_endian
)
18796 result
|= (*where
++ & 255);
18804 result
|= (where
[n
] & 255);
18811 /* MD interface: Sections. */
18813 /* Estimate the size of a frag before relaxing. Assume everything fits in
18817 md_estimate_size_before_relax (fragS
* fragp
,
18818 segT segtype ATTRIBUTE_UNUSED
)
18824 /* Convert a machine dependent frag. */
18827 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18829 unsigned long insn
;
18830 unsigned long old_op
;
18838 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18840 old_op
= bfd_get_16(abfd
, buf
);
18841 if (fragp
->fr_symbol
)
18843 exp
.X_op
= O_symbol
;
18844 exp
.X_add_symbol
= fragp
->fr_symbol
;
18848 exp
.X_op
= O_constant
;
18850 exp
.X_add_number
= fragp
->fr_offset
;
18851 opcode
= fragp
->fr_subtype
;
18854 case T_MNEM_ldr_pc
:
18855 case T_MNEM_ldr_pc2
:
18856 case T_MNEM_ldr_sp
:
18857 case T_MNEM_str_sp
:
18864 if (fragp
->fr_var
== 4)
18866 insn
= THUMB_OP32 (opcode
);
18867 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18869 insn
|= (old_op
& 0x700) << 4;
18873 insn
|= (old_op
& 7) << 12;
18874 insn
|= (old_op
& 0x38) << 13;
18876 insn
|= 0x00000c00;
18877 put_thumb32_insn (buf
, insn
);
18878 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18882 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18884 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18887 if (fragp
->fr_var
== 4)
18889 insn
= THUMB_OP32 (opcode
);
18890 insn
|= (old_op
& 0xf0) << 4;
18891 put_thumb32_insn (buf
, insn
);
18892 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18896 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18897 exp
.X_add_number
-= 4;
18905 if (fragp
->fr_var
== 4)
18907 int r0off
= (opcode
== T_MNEM_mov
18908 || opcode
== T_MNEM_movs
) ? 0 : 8;
18909 insn
= THUMB_OP32 (opcode
);
18910 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18911 insn
|= (old_op
& 0x700) << r0off
;
18912 put_thumb32_insn (buf
, insn
);
18913 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18917 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18922 if (fragp
->fr_var
== 4)
18924 insn
= THUMB_OP32(opcode
);
18925 put_thumb32_insn (buf
, insn
);
18926 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18929 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18933 if (fragp
->fr_var
== 4)
18935 insn
= THUMB_OP32(opcode
);
18936 insn
|= (old_op
& 0xf00) << 14;
18937 put_thumb32_insn (buf
, insn
);
18938 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18941 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18944 case T_MNEM_add_sp
:
18945 case T_MNEM_add_pc
:
18946 case T_MNEM_inc_sp
:
18947 case T_MNEM_dec_sp
:
18948 if (fragp
->fr_var
== 4)
18950 /* ??? Choose between add and addw. */
18951 insn
= THUMB_OP32 (opcode
);
18952 insn
|= (old_op
& 0xf0) << 4;
18953 put_thumb32_insn (buf
, insn
);
18954 if (opcode
== T_MNEM_add_pc
)
18955 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18957 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18960 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18968 if (fragp
->fr_var
== 4)
18970 insn
= THUMB_OP32 (opcode
);
18971 insn
|= (old_op
& 0xf0) << 4;
18972 insn
|= (old_op
& 0xf) << 16;
18973 put_thumb32_insn (buf
, insn
);
18974 if (insn
& (1 << 20))
18975 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18977 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18980 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18986 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18987 (enum bfd_reloc_code_real
) reloc_type
);
18988 fixp
->fx_file
= fragp
->fr_file
;
18989 fixp
->fx_line
= fragp
->fr_line
;
18990 fragp
->fr_fix
+= fragp
->fr_var
;
18993 /* Return the size of a relaxable immediate operand instruction.
18994 SHIFT and SIZE specify the form of the allowable immediate. */
18996 relax_immediate (fragS
*fragp
, int size
, int shift
)
19002 /* ??? Should be able to do better than this. */
19003 if (fragp
->fr_symbol
)
19006 low
= (1 << shift
) - 1;
19007 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19008 offset
= fragp
->fr_offset
;
19009 /* Force misaligned offsets to 32-bit variant. */
19012 if (offset
& ~mask
)
19017 /* Get the address of a symbol during relaxation. */
19019 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19025 sym
= fragp
->fr_symbol
;
19026 sym_frag
= symbol_get_frag (sym
);
19027 know (S_GET_SEGMENT (sym
) != absolute_section
19028 || sym_frag
== &zero_address_frag
);
19029 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19031 /* If frag has yet to be reached on this pass, assume it will
19032 move by STRETCH just as we did. If this is not so, it will
19033 be because some frag between grows, and that will force
19037 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19041 /* Adjust stretch for any alignment frag. Note that if have
19042 been expanding the earlier code, the symbol may be
19043 defined in what appears to be an earlier frag. FIXME:
19044 This doesn't handle the fr_subtype field, which specifies
19045 a maximum number of bytes to skip when doing an
19047 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19049 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19052 stretch
= - ((- stretch
)
19053 & ~ ((1 << (int) f
->fr_offset
) - 1));
19055 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19067 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19070 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19075 /* Assume worst case for symbols not known to be in the same section. */
19076 if (fragp
->fr_symbol
== NULL
19077 || !S_IS_DEFINED (fragp
->fr_symbol
)
19078 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19079 || S_IS_WEAK (fragp
->fr_symbol
))
19082 val
= relaxed_symbol_addr (fragp
, stretch
);
19083 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19084 addr
= (addr
+ 4) & ~3;
19085 /* Force misaligned targets to 32-bit variant. */
19089 if (val
< 0 || val
> 1020)
19094 /* Return the size of a relaxable add/sub immediate instruction. */
19096 relax_addsub (fragS
*fragp
, asection
*sec
)
19101 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19102 op
= bfd_get_16(sec
->owner
, buf
);
19103 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19104 return relax_immediate (fragp
, 8, 0);
19106 return relax_immediate (fragp
, 3, 0);
19110 /* Return the size of a relaxable branch instruction. BITS is the
19111 size of the offset field in the narrow instruction. */
19114 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19120 /* Assume worst case for symbols not known to be in the same section. */
19121 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19122 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19123 || S_IS_WEAK (fragp
->fr_symbol
))
19127 if (S_IS_DEFINED (fragp
->fr_symbol
)
19128 && ARM_IS_FUNC (fragp
->fr_symbol
))
19131 /* PR 12532. Global symbols with default visibility might
19132 be preempted, so do not relax relocations to them. */
19133 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19134 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19138 val
= relaxed_symbol_addr (fragp
, stretch
);
19139 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19142 /* Offset is a signed value *2 */
19144 if (val
>= limit
|| val
< -limit
)
19150 /* Relax a machine dependent frag. This returns the amount by which
19151 the current size of the frag should change. */
19154 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19159 oldsize
= fragp
->fr_var
;
19160 switch (fragp
->fr_subtype
)
19162 case T_MNEM_ldr_pc2
:
19163 newsize
= relax_adr (fragp
, sec
, stretch
);
19165 case T_MNEM_ldr_pc
:
19166 case T_MNEM_ldr_sp
:
19167 case T_MNEM_str_sp
:
19168 newsize
= relax_immediate (fragp
, 8, 2);
19172 newsize
= relax_immediate (fragp
, 5, 2);
19176 newsize
= relax_immediate (fragp
, 5, 1);
19180 newsize
= relax_immediate (fragp
, 5, 0);
19183 newsize
= relax_adr (fragp
, sec
, stretch
);
19189 newsize
= relax_immediate (fragp
, 8, 0);
19192 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19195 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19197 case T_MNEM_add_sp
:
19198 case T_MNEM_add_pc
:
19199 newsize
= relax_immediate (fragp
, 8, 2);
19201 case T_MNEM_inc_sp
:
19202 case T_MNEM_dec_sp
:
19203 newsize
= relax_immediate (fragp
, 7, 2);
19209 newsize
= relax_addsub (fragp
, sec
);
19215 fragp
->fr_var
= newsize
;
19216 /* Freeze wide instructions that are at or before the same location as
19217 in the previous pass. This avoids infinite loops.
19218 Don't freeze them unconditionally because targets may be artificially
19219 misaligned by the expansion of preceding frags. */
19220 if (stretch
<= 0 && newsize
> 2)
19222 md_convert_frag (sec
->owner
, sec
, fragp
);
19226 return newsize
- oldsize
;
19229 /* Round up a section size to the appropriate boundary. */
19232 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19235 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19236 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19238 /* For a.out, force the section size to be aligned. If we don't do
19239 this, BFD will align it for us, but it will not write out the
19240 final bytes of the section. This may be a bug in BFD, but it is
19241 easier to fix it here since that is how the other a.out targets
19245 align
= bfd_get_section_alignment (stdoutput
, segment
);
19246 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19253 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19254 of an rs_align_code fragment. */
19257 arm_handle_align (fragS
* fragP
)
19259 static char const arm_noop
[2][2][4] =
19262 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19263 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19266 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19267 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19270 static char const thumb_noop
[2][2][2] =
19273 {0xc0, 0x46}, /* LE */
19274 {0x46, 0xc0}, /* BE */
19277 {0x00, 0xbf}, /* LE */
19278 {0xbf, 0x00} /* BE */
19281 static char const wide_thumb_noop
[2][4] =
19282 { /* Wide Thumb-2 */
19283 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19284 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19287 unsigned bytes
, fix
, noop_size
;
19290 const char *narrow_noop
= NULL
;
19295 if (fragP
->fr_type
!= rs_align_code
)
19298 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19299 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19302 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19303 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19305 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19307 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19309 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19311 narrow_noop
= thumb_noop
[1][target_big_endian
];
19312 noop
= wide_thumb_noop
[target_big_endian
];
19315 noop
= thumb_noop
[0][target_big_endian
];
19323 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19324 [target_big_endian
];
19331 fragP
->fr_var
= noop_size
;
19333 if (bytes
& (noop_size
- 1))
19335 fix
= bytes
& (noop_size
- 1);
19337 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19339 memset (p
, 0, fix
);
19346 if (bytes
& noop_size
)
19348 /* Insert a narrow noop. */
19349 memcpy (p
, narrow_noop
, noop_size
);
19351 bytes
-= noop_size
;
19355 /* Use wide noops for the remainder */
19359 while (bytes
>= noop_size
)
19361 memcpy (p
, noop
, noop_size
);
19363 bytes
-= noop_size
;
19367 fragP
->fr_fix
+= fix
;
19370 /* Called from md_do_align. Used to create an alignment
19371 frag in a code section. */
19374 arm_frag_align_code (int n
, int max
)
19378 /* We assume that there will never be a requirement
19379 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19380 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19385 _("alignments greater than %d bytes not supported in .text sections."),
19386 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19387 as_fatal ("%s", err_msg
);
19390 p
= frag_var (rs_align_code
,
19391 MAX_MEM_FOR_RS_ALIGN_CODE
,
19393 (relax_substateT
) max
,
19400 /* Perform target specific initialisation of a frag.
19401 Note - despite the name this initialisation is not done when the frag
19402 is created, but only when its type is assigned. A frag can be created
19403 and used a long time before its type is set, so beware of assuming that
19404 this initialisationis performed first. */
19408 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19410 /* Record whether this frag is in an ARM or a THUMB area. */
19411 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19414 #else /* OBJ_ELF is defined. */
19416 arm_init_frag (fragS
* fragP
, int max_chars
)
19418 /* If the current ARM vs THUMB mode has not already
19419 been recorded into this frag then do so now. */
19420 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19422 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19424 /* Record a mapping symbol for alignment frags. We will delete this
19425 later if the alignment ends up empty. */
19426 switch (fragP
->fr_type
)
19429 case rs_align_test
:
19431 mapping_state_2 (MAP_DATA
, max_chars
);
19433 case rs_align_code
:
19434 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19442 /* When we change sections we need to issue a new mapping symbol. */
19445 arm_elf_change_section (void)
19447 /* Link an unlinked unwind index table section to the .text section. */
19448 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19449 && elf_linked_to_section (now_seg
) == NULL
)
19450 elf_linked_to_section (now_seg
) = text_section
;
19454 arm_elf_section_type (const char * str
, size_t len
)
19456 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19457 return SHT_ARM_EXIDX
;
19462 /* Code to deal with unwinding tables. */
19464 static void add_unwind_adjustsp (offsetT
);
19466 /* Generate any deferred unwind frame offset. */
19469 flush_pending_unwind (void)
19473 offset
= unwind
.pending_offset
;
19474 unwind
.pending_offset
= 0;
19476 add_unwind_adjustsp (offset
);
19479 /* Add an opcode to this list for this function. Two-byte opcodes should
19480 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19484 add_unwind_opcode (valueT op
, int length
)
19486 /* Add any deferred stack adjustment. */
19487 if (unwind
.pending_offset
)
19488 flush_pending_unwind ();
19490 unwind
.sp_restored
= 0;
19492 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19494 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19495 if (unwind
.opcodes
)
19496 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19497 unwind
.opcode_alloc
);
19499 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19504 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19506 unwind
.opcode_count
++;
19510 /* Add unwind opcodes to adjust the stack pointer. */
19513 add_unwind_adjustsp (offsetT offset
)
19517 if (offset
> 0x200)
19519 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19524 /* Long form: 0xb2, uleb128. */
19525 /* This might not fit in a word so add the individual bytes,
19526 remembering the list is built in reverse order. */
19527 o
= (valueT
) ((offset
- 0x204) >> 2);
19529 add_unwind_opcode (0, 1);
19531 /* Calculate the uleb128 encoding of the offset. */
19535 bytes
[n
] = o
& 0x7f;
19541 /* Add the insn. */
19543 add_unwind_opcode (bytes
[n
- 1], 1);
19544 add_unwind_opcode (0xb2, 1);
19546 else if (offset
> 0x100)
19548 /* Two short opcodes. */
19549 add_unwind_opcode (0x3f, 1);
19550 op
= (offset
- 0x104) >> 2;
19551 add_unwind_opcode (op
, 1);
19553 else if (offset
> 0)
19555 /* Short opcode. */
19556 op
= (offset
- 4) >> 2;
19557 add_unwind_opcode (op
, 1);
19559 else if (offset
< 0)
19562 while (offset
> 0x100)
19564 add_unwind_opcode (0x7f, 1);
19567 op
= ((offset
- 4) >> 2) | 0x40;
19568 add_unwind_opcode (op
, 1);
19572 /* Finish the list of unwind opcodes for this function. */
19574 finish_unwind_opcodes (void)
19578 if (unwind
.fp_used
)
19580 /* Adjust sp as necessary. */
19581 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19582 flush_pending_unwind ();
19584 /* After restoring sp from the frame pointer. */
19585 op
= 0x90 | unwind
.fp_reg
;
19586 add_unwind_opcode (op
, 1);
19589 flush_pending_unwind ();
19593 /* Start an exception table entry. If idx is nonzero this is an index table
19597 start_unwind_section (const segT text_seg
, int idx
)
19599 const char * text_name
;
19600 const char * prefix
;
19601 const char * prefix_once
;
19602 const char * group_name
;
19606 size_t sec_name_len
;
19613 prefix
= ELF_STRING_ARM_unwind
;
19614 prefix_once
= ELF_STRING_ARM_unwind_once
;
19615 type
= SHT_ARM_EXIDX
;
19619 prefix
= ELF_STRING_ARM_unwind_info
;
19620 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19621 type
= SHT_PROGBITS
;
19624 text_name
= segment_name (text_seg
);
19625 if (streq (text_name
, ".text"))
19628 if (strncmp (text_name
, ".gnu.linkonce.t.",
19629 strlen (".gnu.linkonce.t.")) == 0)
19631 prefix
= prefix_once
;
19632 text_name
+= strlen (".gnu.linkonce.t.");
19635 prefix_len
= strlen (prefix
);
19636 text_len
= strlen (text_name
);
19637 sec_name_len
= prefix_len
+ text_len
;
19638 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19639 memcpy (sec_name
, prefix
, prefix_len
);
19640 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19641 sec_name
[prefix_len
+ text_len
] = '\0';
19647 /* Handle COMDAT group. */
19648 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19650 group_name
= elf_group_name (text_seg
);
19651 if (group_name
== NULL
)
19653 as_bad (_("Group section `%s' has no group signature"),
19654 segment_name (text_seg
));
19655 ignore_rest_of_line ();
19658 flags
|= SHF_GROUP
;
19662 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19664 /* Set the section link for index tables. */
19666 elf_linked_to_section (now_seg
) = text_seg
;
19670 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19671 personality routine data. Returns zero, or the index table value for
19672 and inline entry. */
19675 create_unwind_entry (int have_data
)
19680 /* The current word of data. */
19682 /* The number of bytes left in this word. */
19685 finish_unwind_opcodes ();
19687 /* Remember the current text section. */
19688 unwind
.saved_seg
= now_seg
;
19689 unwind
.saved_subseg
= now_subseg
;
19691 start_unwind_section (now_seg
, 0);
19693 if (unwind
.personality_routine
== NULL
)
19695 if (unwind
.personality_index
== -2)
19698 as_bad (_("handlerdata in cantunwind frame"));
19699 return 1; /* EXIDX_CANTUNWIND. */
19702 /* Use a default personality routine if none is specified. */
19703 if (unwind
.personality_index
== -1)
19705 if (unwind
.opcode_count
> 3)
19706 unwind
.personality_index
= 1;
19708 unwind
.personality_index
= 0;
19711 /* Space for the personality routine entry. */
19712 if (unwind
.personality_index
== 0)
19714 if (unwind
.opcode_count
> 3)
19715 as_bad (_("too many unwind opcodes for personality routine 0"));
19719 /* All the data is inline in the index table. */
19722 while (unwind
.opcode_count
> 0)
19724 unwind
.opcode_count
--;
19725 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19729 /* Pad with "finish" opcodes. */
19731 data
= (data
<< 8) | 0xb0;
19738 /* We get two opcodes "free" in the first word. */
19739 size
= unwind
.opcode_count
- 2;
19742 /* An extra byte is required for the opcode count. */
19743 size
= unwind
.opcode_count
+ 1;
19745 size
= (size
+ 3) >> 2;
19747 as_bad (_("too many unwind opcodes"));
19749 frag_align (2, 0, 0);
19750 record_alignment (now_seg
, 2);
19751 unwind
.table_entry
= expr_build_dot ();
19753 /* Allocate the table entry. */
19754 ptr
= frag_more ((size
<< 2) + 4);
19755 where
= frag_now_fix () - ((size
<< 2) + 4);
19757 switch (unwind
.personality_index
)
19760 /* ??? Should this be a PLT generating relocation? */
19761 /* Custom personality routine. */
19762 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19763 BFD_RELOC_ARM_PREL31
);
19768 /* Set the first byte to the number of additional words. */
19773 /* ABI defined personality routines. */
19775 /* Three opcodes bytes are packed into the first word. */
19782 /* The size and first two opcode bytes go in the first word. */
19783 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19788 /* Should never happen. */
19792 /* Pack the opcodes into words (MSB first), reversing the list at the same
19794 while (unwind
.opcode_count
> 0)
19798 md_number_to_chars (ptr
, data
, 4);
19803 unwind
.opcode_count
--;
19805 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19808 /* Finish off the last word. */
19811 /* Pad with "finish" opcodes. */
19813 data
= (data
<< 8) | 0xb0;
19815 md_number_to_chars (ptr
, data
, 4);
19820 /* Add an empty descriptor if there is no user-specified data. */
19821 ptr
= frag_more (4);
19822 md_number_to_chars (ptr
, 0, 4);
19829 /* Initialize the DWARF-2 unwind information for this procedure. */
19832 tc_arm_frame_initial_instructions (void)
19834 cfi_add_CFA_def_cfa (REG_SP
, 0);
19836 #endif /* OBJ_ELF */
19838 /* Convert REGNAME to a DWARF-2 register number. */
19841 tc_arm_regname_to_dw2regnum (char *regname
)
19843 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19853 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19857 exp
.X_op
= O_secrel
;
19858 exp
.X_add_symbol
= symbol
;
19859 exp
.X_add_number
= 0;
19860 emit_expr (&exp
, size
);
19864 /* MD interface: Symbol and relocation handling. */
19866 /* Return the address within the segment that a PC-relative fixup is
19867 relative to. For ARM, PC-relative fixups applied to instructions
19868 are generally relative to the location of the fixup plus 8 bytes.
19869 Thumb branches are offset by 4, and Thumb loads relative to PC
19870 require special handling. */
19873 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19875 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19877 /* If this is pc-relative and we are going to emit a relocation
19878 then we just want to put out any pipeline compensation that the linker
19879 will need. Otherwise we want to use the calculated base.
19880 For WinCE we skip the bias for externals as well, since this
19881 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19883 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19884 || (arm_force_relocation (fixP
)
19886 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19892 switch (fixP
->fx_r_type
)
19894 /* PC relative addressing on the Thumb is slightly odd as the
19895 bottom two bits of the PC are forced to zero for the
19896 calculation. This happens *after* application of the
19897 pipeline offset. However, Thumb adrl already adjusts for
19898 this, so we need not do it again. */
19899 case BFD_RELOC_ARM_THUMB_ADD
:
19902 case BFD_RELOC_ARM_THUMB_OFFSET
:
19903 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19904 case BFD_RELOC_ARM_T32_ADD_PC12
:
19905 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19906 return (base
+ 4) & ~3;
19908 /* Thumb branches are simply offset by +4. */
19909 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19910 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19911 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19912 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19913 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19916 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19918 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19919 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19920 && ARM_IS_FUNC (fixP
->fx_addsy
)
19921 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19922 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19925 /* BLX is like branches above, but forces the low two bits of PC to
19927 case BFD_RELOC_THUMB_PCREL_BLX
:
19929 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19930 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19931 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19932 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19933 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19934 return (base
+ 4) & ~3;
19936 /* ARM mode branches are offset by +8. However, the Windows CE
19937 loader expects the relocation not to take this into account. */
19938 case BFD_RELOC_ARM_PCREL_BLX
:
19940 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19941 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19942 && ARM_IS_FUNC (fixP
->fx_addsy
)
19943 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19944 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19947 case BFD_RELOC_ARM_PCREL_CALL
:
19949 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19950 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19951 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19952 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19953 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19956 case BFD_RELOC_ARM_PCREL_BRANCH
:
19957 case BFD_RELOC_ARM_PCREL_JUMP
:
19958 case BFD_RELOC_ARM_PLT32
:
19960 /* When handling fixups immediately, because we have already
19961 discovered the value of a symbol, or the address of the frag involved
19962 we must account for the offset by +8, as the OS loader will never see the reloc.
19963 see fixup_segment() in write.c
19964 The S_IS_EXTERNAL test handles the case of global symbols.
19965 Those need the calculated base, not just the pipe compensation the linker will need. */
19967 && fixP
->fx_addsy
!= NULL
19968 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19969 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19977 /* ARM mode loads relative to PC are also offset by +8. Unlike
19978 branches, the Windows CE loader *does* expect the relocation
19979 to take this into account. */
19980 case BFD_RELOC_ARM_OFFSET_IMM
:
19981 case BFD_RELOC_ARM_OFFSET_IMM8
:
19982 case BFD_RELOC_ARM_HWLITERAL
:
19983 case BFD_RELOC_ARM_LITERAL
:
19984 case BFD_RELOC_ARM_CP_OFF_IMM
:
19988 /* Other PC-relative relocations are un-offset. */
19994 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19995 Otherwise we have no need to default values of symbols. */
19998 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20001 if (name
[0] == '_' && name
[1] == 'G'
20002 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20006 if (symbol_find (name
))
20007 as_bad (_("GOT already in the symbol table"));
20009 GOT_symbol
= symbol_new (name
, undefined_section
,
20010 (valueT
) 0, & zero_address_frag
);
20020 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20021 computed as two separate immediate values, added together. We
20022 already know that this value cannot be computed by just one ARM
20025 static unsigned int
20026 validate_immediate_twopart (unsigned int val
,
20027 unsigned int * highpart
)
20032 for (i
= 0; i
< 32; i
+= 2)
20033 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20039 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20041 else if (a
& 0xff0000)
20043 if (a
& 0xff000000)
20045 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20049 gas_assert (a
& 0xff000000);
20050 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20053 return (a
& 0xff) | (i
<< 7);
20060 validate_offset_imm (unsigned int val
, int hwse
)
20062 if ((hwse
&& val
> 255) || val
> 4095)
20067 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20068 negative immediate constant by altering the instruction. A bit of
20073 by inverting the second operand, and
20076 by negating the second operand. */
20079 negate_data_op (unsigned long * instruction
,
20080 unsigned long value
)
20083 unsigned long negated
, inverted
;
20085 negated
= encode_arm_immediate (-value
);
20086 inverted
= encode_arm_immediate (~value
);
20088 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20091 /* First negates. */
20092 case OPCODE_SUB
: /* ADD <-> SUB */
20093 new_inst
= OPCODE_ADD
;
20098 new_inst
= OPCODE_SUB
;
20102 case OPCODE_CMP
: /* CMP <-> CMN */
20103 new_inst
= OPCODE_CMN
;
20108 new_inst
= OPCODE_CMP
;
20112 /* Now Inverted ops. */
20113 case OPCODE_MOV
: /* MOV <-> MVN */
20114 new_inst
= OPCODE_MVN
;
20119 new_inst
= OPCODE_MOV
;
20123 case OPCODE_AND
: /* AND <-> BIC */
20124 new_inst
= OPCODE_BIC
;
20129 new_inst
= OPCODE_AND
;
20133 case OPCODE_ADC
: /* ADC <-> SBC */
20134 new_inst
= OPCODE_SBC
;
20139 new_inst
= OPCODE_ADC
;
20143 /* We cannot do anything. */
20148 if (value
== (unsigned) FAIL
)
20151 *instruction
&= OPCODE_MASK
;
20152 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20156 /* Like negate_data_op, but for Thumb-2. */
20158 static unsigned int
20159 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20163 unsigned int negated
, inverted
;
20165 negated
= encode_thumb32_immediate (-value
);
20166 inverted
= encode_thumb32_immediate (~value
);
20168 rd
= (*instruction
>> 8) & 0xf;
20169 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20172 /* ADD <-> SUB. Includes CMP <-> CMN. */
20173 case T2_OPCODE_SUB
:
20174 new_inst
= T2_OPCODE_ADD
;
20178 case T2_OPCODE_ADD
:
20179 new_inst
= T2_OPCODE_SUB
;
20183 /* ORR <-> ORN. Includes MOV <-> MVN. */
20184 case T2_OPCODE_ORR
:
20185 new_inst
= T2_OPCODE_ORN
;
20189 case T2_OPCODE_ORN
:
20190 new_inst
= T2_OPCODE_ORR
;
20194 /* AND <-> BIC. TST has no inverted equivalent. */
20195 case T2_OPCODE_AND
:
20196 new_inst
= T2_OPCODE_BIC
;
20203 case T2_OPCODE_BIC
:
20204 new_inst
= T2_OPCODE_AND
;
20209 case T2_OPCODE_ADC
:
20210 new_inst
= T2_OPCODE_SBC
;
20214 case T2_OPCODE_SBC
:
20215 new_inst
= T2_OPCODE_ADC
;
20219 /* We cannot do anything. */
20224 if (value
== (unsigned int)FAIL
)
20227 *instruction
&= T2_OPCODE_MASK
;
20228 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20232 /* Read a 32-bit thumb instruction from buf. */
20233 static unsigned long
20234 get_thumb32_insn (char * buf
)
20236 unsigned long insn
;
20237 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20238 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20244 /* We usually want to set the low bit on the address of thumb function
20245 symbols. In particular .word foo - . should have the low bit set.
20246 Generic code tries to fold the difference of two symbols to
20247 a constant. Prevent this and force a relocation when the first symbols
20248 is a thumb function. */
20251 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20253 if (op
== O_subtract
20254 && l
->X_op
== O_symbol
20255 && r
->X_op
== O_symbol
20256 && THUMB_IS_FUNC (l
->X_add_symbol
))
20258 l
->X_op
= O_subtract
;
20259 l
->X_op_symbol
= r
->X_add_symbol
;
20260 l
->X_add_number
-= r
->X_add_number
;
20264 /* Process as normal. */
20268 /* Encode Thumb2 unconditional branches and calls. The encoding
20269 for the 2 are identical for the immediate values. */
20272 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20274 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20277 addressT S
, I1
, I2
, lo
, hi
;
20279 S
= (value
>> 24) & 0x01;
20280 I1
= (value
>> 23) & 0x01;
20281 I2
= (value
>> 22) & 0x01;
20282 hi
= (value
>> 12) & 0x3ff;
20283 lo
= (value
>> 1) & 0x7ff;
20284 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20285 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20286 newval
|= (S
<< 10) | hi
;
20287 newval2
&= ~T2I1I2MASK
;
20288 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20289 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20290 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20294 md_apply_fix (fixS
* fixP
,
20298 offsetT value
= * valP
;
20300 unsigned int newimm
;
20301 unsigned long temp
;
20303 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20305 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20307 /* Note whether this will delete the relocation. */
20309 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20312 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20313 consistency with the behaviour on 32-bit hosts. Remember value
20315 value
&= 0xffffffff;
20316 value
^= 0x80000000;
20317 value
-= 0x80000000;
20320 fixP
->fx_addnumber
= value
;
20322 /* Same treatment for fixP->fx_offset. */
20323 fixP
->fx_offset
&= 0xffffffff;
20324 fixP
->fx_offset
^= 0x80000000;
20325 fixP
->fx_offset
-= 0x80000000;
20327 switch (fixP
->fx_r_type
)
20329 case BFD_RELOC_NONE
:
20330 /* This will need to go in the object file. */
20334 case BFD_RELOC_ARM_IMMEDIATE
:
20335 /* We claim that this fixup has been processed here,
20336 even if in fact we generate an error because we do
20337 not have a reloc for it, so tc_gen_reloc will reject it. */
20340 if (fixP
->fx_addsy
)
20342 const char *msg
= 0;
20344 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20345 msg
= _("undefined symbol %s used as an immediate value");
20346 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20347 msg
= _("symbol %s is in a different section");
20348 else if (S_IS_WEAK (fixP
->fx_addsy
))
20349 msg
= _("symbol %s is weak and may be overridden later");
20353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20354 msg
, S_GET_NAME (fixP
->fx_addsy
));
20359 newimm
= encode_arm_immediate (value
);
20360 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20362 /* If the instruction will fail, see if we can fix things up by
20363 changing the opcode. */
20364 if (newimm
== (unsigned int) FAIL
20365 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20368 _("invalid constant (%lx) after fixup"),
20369 (unsigned long) value
);
20373 newimm
|= (temp
& 0xfffff000);
20374 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20377 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20379 unsigned int highpart
= 0;
20380 unsigned int newinsn
= 0xe1a00000; /* nop. */
20382 if (fixP
->fx_addsy
)
20384 const char *msg
= 0;
20386 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20387 msg
= _("undefined symbol %s used as an immediate value");
20388 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20389 msg
= _("symbol %s is in a different section");
20390 else if (S_IS_WEAK (fixP
->fx_addsy
))
20391 msg
= _("symbol %s is weak and may be overridden later");
20395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20396 msg
, S_GET_NAME (fixP
->fx_addsy
));
20401 newimm
= encode_arm_immediate (value
);
20402 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20404 /* If the instruction will fail, see if we can fix things up by
20405 changing the opcode. */
20406 if (newimm
== (unsigned int) FAIL
20407 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20409 /* No ? OK - try using two ADD instructions to generate
20411 newimm
= validate_immediate_twopart (value
, & highpart
);
20413 /* Yes - then make sure that the second instruction is
20415 if (newimm
!= (unsigned int) FAIL
)
20417 /* Still No ? Try using a negated value. */
20418 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20419 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20420 /* Otherwise - give up. */
20423 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20424 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20429 /* Replace the first operand in the 2nd instruction (which
20430 is the PC) with the destination register. We have
20431 already added in the PC in the first instruction and we
20432 do not want to do it again. */
20433 newinsn
&= ~ 0xf0000;
20434 newinsn
|= ((newinsn
& 0x0f000) << 4);
20437 newimm
|= (temp
& 0xfffff000);
20438 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20440 highpart
|= (newinsn
& 0xfffff000);
20441 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20445 case BFD_RELOC_ARM_OFFSET_IMM
:
20446 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20449 case BFD_RELOC_ARM_LITERAL
:
20455 if (validate_offset_imm (value
, 0) == FAIL
)
20457 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20459 _("invalid literal constant: pool needs to be closer"));
20461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20462 _("bad immediate value for offset (%ld)"),
20467 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20468 newval
&= 0xff7ff000;
20469 newval
|= value
| (sign
? INDEX_UP
: 0);
20470 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20473 case BFD_RELOC_ARM_OFFSET_IMM8
:
20474 case BFD_RELOC_ARM_HWLITERAL
:
20480 if (validate_offset_imm (value
, 1) == FAIL
)
20482 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20484 _("invalid literal constant: pool needs to be closer"));
20486 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20491 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20492 newval
&= 0xff7ff0f0;
20493 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20494 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20497 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20498 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20500 _("bad immediate value for offset (%ld)"), (long) value
);
20503 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20505 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20508 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20509 /* This is a complicated relocation used for all varieties of Thumb32
20510 load/store instruction with immediate offset:
20512 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20513 *4, optional writeback(W)
20514 (doubleword load/store)
20516 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20517 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20518 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20519 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20520 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20522 Uppercase letters indicate bits that are already encoded at
20523 this point. Lowercase letters are our problem. For the
20524 second block of instructions, the secondary opcode nybble
20525 (bits 8..11) is present, and bit 23 is zero, even if this is
20526 a PC-relative operation. */
20527 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20529 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20531 if ((newval
& 0xf0000000) == 0xe0000000)
20533 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20535 newval
|= (1 << 23);
20538 if (value
% 4 != 0)
20540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20541 _("offset not a multiple of 4"));
20547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20548 _("offset out of range"));
20553 else if ((newval
& 0x000f0000) == 0x000f0000)
20555 /* PC-relative, 12-bit offset. */
20557 newval
|= (1 << 23);
20562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20563 _("offset out of range"));
20568 else if ((newval
& 0x00000100) == 0x00000100)
20570 /* Writeback: 8-bit, +/- offset. */
20572 newval
|= (1 << 9);
20577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20578 _("offset out of range"));
20583 else if ((newval
& 0x00000f00) == 0x00000e00)
20585 /* T-instruction: positive 8-bit offset. */
20586 if (value
< 0 || value
> 0xff)
20588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20589 _("offset out of range"));
20597 /* Positive 12-bit or negative 8-bit offset. */
20601 newval
|= (1 << 23);
20611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20612 _("offset out of range"));
20619 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20620 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20623 case BFD_RELOC_ARM_SHIFT_IMM
:
20624 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20625 if (((unsigned long) value
) > 32
20627 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20630 _("shift expression is too large"));
20635 /* Shifts of zero must be done as lsl. */
20637 else if (value
== 32)
20639 newval
&= 0xfffff07f;
20640 newval
|= (value
& 0x1f) << 7;
20641 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20644 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20645 case BFD_RELOC_ARM_T32_ADD_IMM
:
20646 case BFD_RELOC_ARM_T32_IMM12
:
20647 case BFD_RELOC_ARM_T32_ADD_PC12
:
20648 /* We claim that this fixup has been processed here,
20649 even if in fact we generate an error because we do
20650 not have a reloc for it, so tc_gen_reloc will reject it. */
20654 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20656 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20657 _("undefined symbol %s used as an immediate value"),
20658 S_GET_NAME (fixP
->fx_addsy
));
20662 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20664 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20667 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20668 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20670 newimm
= encode_thumb32_immediate (value
);
20671 if (newimm
== (unsigned int) FAIL
)
20672 newimm
= thumb32_negate_data_op (&newval
, value
);
20674 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20675 && newimm
== (unsigned int) FAIL
)
20677 /* Turn add/sum into addw/subw. */
20678 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20679 newval
= (newval
& 0xfeffffff) | 0x02000000;
20680 /* No flat 12-bit imm encoding for addsw/subsw. */
20681 if ((newval
& 0x00100000) == 0)
20683 /* 12 bit immediate for addw/subw. */
20687 newval
^= 0x00a00000;
20690 newimm
= (unsigned int) FAIL
;
20696 if (newimm
== (unsigned int)FAIL
)
20698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20699 _("invalid constant (%lx) after fixup"),
20700 (unsigned long) value
);
20704 newval
|= (newimm
& 0x800) << 15;
20705 newval
|= (newimm
& 0x700) << 4;
20706 newval
|= (newimm
& 0x0ff);
20708 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20709 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20712 case BFD_RELOC_ARM_SMC
:
20713 if (((unsigned long) value
) > 0xffff)
20714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20715 _("invalid smc expression"));
20716 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20717 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20718 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20721 case BFD_RELOC_ARM_HVC
:
20722 if (((unsigned long) value
) > 0xffff)
20723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20724 _("invalid hvc expression"));
20725 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20726 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20727 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20730 case BFD_RELOC_ARM_SWI
:
20731 if (fixP
->tc_fix_data
!= 0)
20733 if (((unsigned long) value
) > 0xff)
20734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20735 _("invalid swi expression"));
20736 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20738 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20742 if (((unsigned long) value
) > 0x00ffffff)
20743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20744 _("invalid swi expression"));
20745 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20747 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20751 case BFD_RELOC_ARM_MULTI
:
20752 if (((unsigned long) value
) > 0xffff)
20753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20754 _("invalid expression in load/store multiple"));
20755 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20756 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20760 case BFD_RELOC_ARM_PCREL_CALL
:
20762 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20764 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20765 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20766 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20767 /* Flip the bl to blx. This is a simple flip
20768 bit here because we generate PCREL_CALL for
20769 unconditional bls. */
20771 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20772 newval
= newval
| 0x10000000;
20773 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20779 goto arm_branch_common
;
20781 case BFD_RELOC_ARM_PCREL_JUMP
:
20782 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20784 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20785 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20786 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20788 /* This would map to a bl<cond>, b<cond>,
20789 b<always> to a Thumb function. We
20790 need to force a relocation for this particular
20792 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20796 case BFD_RELOC_ARM_PLT32
:
20798 case BFD_RELOC_ARM_PCREL_BRANCH
:
20800 goto arm_branch_common
;
20802 case BFD_RELOC_ARM_PCREL_BLX
:
20805 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20807 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20808 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20809 && ARM_IS_FUNC (fixP
->fx_addsy
))
20811 /* Flip the blx to a bl and warn. */
20812 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20813 newval
= 0xeb000000;
20814 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20815 _("blx to '%s' an ARM ISA state function changed to bl"),
20817 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20823 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20824 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20828 /* We are going to store value (shifted right by two) in the
20829 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20830 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20831 also be be clear. */
20833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20834 _("misaligned branch destination"));
20835 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20836 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20838 _("branch out of range"));
20840 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20842 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20843 newval
|= (value
>> 2) & 0x00ffffff;
20844 /* Set the H bit on BLX instructions. */
20848 newval
|= 0x01000000;
20850 newval
&= ~0x01000000;
20852 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20856 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20857 /* CBZ can only branch forward. */
20859 /* Attempts to use CBZ to branch to the next instruction
20860 (which, strictly speaking, are prohibited) will be turned into
20863 FIXME: It may be better to remove the instruction completely and
20864 perform relaxation. */
20867 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20868 newval
= 0xbf00; /* NOP encoding T1 */
20869 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20875 _("branch out of range"));
20877 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20879 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20880 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20881 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20886 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20887 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20888 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20889 _("branch out of range"));
20891 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20893 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20894 newval
|= (value
& 0x1ff) >> 1;
20895 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20899 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20900 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20902 _("branch out of range"));
20904 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20906 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20907 newval
|= (value
& 0xfff) >> 1;
20908 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20912 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20914 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20915 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20916 && ARM_IS_FUNC (fixP
->fx_addsy
)
20917 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20919 /* Force a relocation for a branch 20 bits wide. */
20922 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20924 _("conditional branch out of range"));
20926 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20929 addressT S
, J1
, J2
, lo
, hi
;
20931 S
= (value
& 0x00100000) >> 20;
20932 J2
= (value
& 0x00080000) >> 19;
20933 J1
= (value
& 0x00040000) >> 18;
20934 hi
= (value
& 0x0003f000) >> 12;
20935 lo
= (value
& 0x00000ffe) >> 1;
20937 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20938 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20939 newval
|= (S
<< 10) | hi
;
20940 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20941 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20942 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20946 case BFD_RELOC_THUMB_PCREL_BLX
:
20948 /* If there is a blx from a thumb state function to
20949 another thumb function flip this to a bl and warn
20953 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20954 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20955 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20957 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20958 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20959 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20961 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20962 newval
= newval
| 0x1000;
20963 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20964 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20969 goto thumb_bl_common
;
20971 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20973 /* A bl from Thumb state ISA to an internal ARM state function
20974 is converted to a blx. */
20976 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20977 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20978 && ARM_IS_FUNC (fixP
->fx_addsy
)
20979 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20981 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20982 newval
= newval
& ~0x1000;
20983 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20984 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20991 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20992 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20993 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20996 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20997 /* For a BLX instruction, make sure that the relocation is rounded up
20998 to a word boundary. This follows the semantics of the instruction
20999 which specifies that bit 1 of the target address will come from bit
21000 1 of the base address. */
21001 value
= (value
+ 1) & ~ 1;
21004 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21006 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21009 _("branch out of range"));
21011 else if ((value
& ~0x1ffffff)
21012 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21015 _("Thumb2 branch out of range"));
21019 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21020 encode_thumb2_b_bl_offset (buf
, value
);
21024 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21025 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
21026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21027 _("branch out of range"));
21029 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21030 encode_thumb2_b_bl_offset (buf
, value
);
21035 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21036 md_number_to_chars (buf
, value
, 1);
21040 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21041 md_number_to_chars (buf
, value
, 2);
21045 case BFD_RELOC_ARM_TLS_CALL
:
21046 case BFD_RELOC_ARM_THM_TLS_CALL
:
21047 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21048 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21049 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21052 case BFD_RELOC_ARM_TLS_GOTDESC
:
21053 case BFD_RELOC_ARM_TLS_GD32
:
21054 case BFD_RELOC_ARM_TLS_LE32
:
21055 case BFD_RELOC_ARM_TLS_IE32
:
21056 case BFD_RELOC_ARM_TLS_LDM32
:
21057 case BFD_RELOC_ARM_TLS_LDO32
:
21058 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21061 case BFD_RELOC_ARM_GOT32
:
21062 case BFD_RELOC_ARM_GOTOFF
:
21063 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21064 md_number_to_chars (buf
, 0, 4);
21067 case BFD_RELOC_ARM_GOT_PREL
:
21068 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21069 md_number_to_chars (buf
, value
, 4);
21072 case BFD_RELOC_ARM_TARGET2
:
21073 /* TARGET2 is not partial-inplace, so we need to write the
21074 addend here for REL targets, because it won't be written out
21075 during reloc processing later. */
21076 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21077 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21081 case BFD_RELOC_RVA
:
21083 case BFD_RELOC_ARM_TARGET1
:
21084 case BFD_RELOC_ARM_ROSEGREL32
:
21085 case BFD_RELOC_ARM_SBREL32
:
21086 case BFD_RELOC_32_PCREL
:
21088 case BFD_RELOC_32_SECREL
:
21090 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21092 /* For WinCE we only do this for pcrel fixups. */
21093 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21095 md_number_to_chars (buf
, value
, 4);
21099 case BFD_RELOC_ARM_PREL31
:
21100 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21102 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21103 if ((value
^ (value
>> 1)) & 0x40000000)
21105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21106 _("rel31 relocation overflow"));
21108 newval
|= value
& 0x7fffffff;
21109 md_number_to_chars (buf
, newval
, 4);
21114 case BFD_RELOC_ARM_CP_OFF_IMM
:
21115 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21116 if (value
< -1023 || value
> 1023 || (value
& 3))
21117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21118 _("co-processor offset out of range"));
21123 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21124 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21125 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21127 newval
= get_thumb32_insn (buf
);
21128 newval
&= 0xff7fff00;
21129 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21130 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21131 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21132 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21134 put_thumb32_insn (buf
, newval
);
21137 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21138 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21139 if (value
< -255 || value
> 255)
21140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21141 _("co-processor offset out of range"));
21143 goto cp_off_common
;
21145 case BFD_RELOC_ARM_THUMB_OFFSET
:
21146 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21147 /* Exactly what ranges, and where the offset is inserted depends
21148 on the type of instruction, we can establish this from the
21150 switch (newval
>> 12)
21152 case 4: /* PC load. */
21153 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21154 forced to zero for these loads; md_pcrel_from has already
21155 compensated for this. */
21157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21158 _("invalid offset, target not word aligned (0x%08lX)"),
21159 (((unsigned long) fixP
->fx_frag
->fr_address
21160 + (unsigned long) fixP
->fx_where
) & ~3)
21161 + (unsigned long) value
);
21163 if (value
& ~0x3fc)
21164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21165 _("invalid offset, value too big (0x%08lX)"),
21168 newval
|= value
>> 2;
21171 case 9: /* SP load/store. */
21172 if (value
& ~0x3fc)
21173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21174 _("invalid offset, value too big (0x%08lX)"),
21176 newval
|= value
>> 2;
21179 case 6: /* Word load/store. */
21181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21182 _("invalid offset, value too big (0x%08lX)"),
21184 newval
|= value
<< 4; /* 6 - 2. */
21187 case 7: /* Byte load/store. */
21189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21190 _("invalid offset, value too big (0x%08lX)"),
21192 newval
|= value
<< 6;
21195 case 8: /* Halfword load/store. */
21197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21198 _("invalid offset, value too big (0x%08lX)"),
21200 newval
|= value
<< 5; /* 6 - 1. */
21204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21205 "Unable to process relocation for thumb opcode: %lx",
21206 (unsigned long) newval
);
21209 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21212 case BFD_RELOC_ARM_THUMB_ADD
:
21213 /* This is a complicated relocation, since we use it for all of
21214 the following immediate relocations:
21218 9bit ADD/SUB SP word-aligned
21219 10bit ADD PC/SP word-aligned
21221 The type of instruction being processed is encoded in the
21228 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21230 int rd
= (newval
>> 4) & 0xf;
21231 int rs
= newval
& 0xf;
21232 int subtract
= !!(newval
& 0x8000);
21234 /* Check for HI regs, only very restricted cases allowed:
21235 Adjusting SP, and using PC or SP to get an address. */
21236 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21237 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21239 _("invalid Hi register with immediate"));
21241 /* If value is negative, choose the opposite instruction. */
21245 subtract
= !subtract
;
21247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21248 _("immediate value out of range"));
21253 if (value
& ~0x1fc)
21254 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21255 _("invalid immediate for stack address calculation"));
21256 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21257 newval
|= value
>> 2;
21259 else if (rs
== REG_PC
|| rs
== REG_SP
)
21261 if (subtract
|| value
& ~0x3fc)
21262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21263 _("invalid immediate for address calculation (value = 0x%08lX)"),
21264 (unsigned long) value
);
21265 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21267 newval
|= value
>> 2;
21272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21273 _("immediate value out of range"));
21274 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21275 newval
|= (rd
<< 8) | value
;
21280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21281 _("immediate value out of range"));
21282 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21283 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21286 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21289 case BFD_RELOC_ARM_THUMB_IMM
:
21290 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21291 if (value
< 0 || value
> 255)
21292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21293 _("invalid immediate: %ld is out of range"),
21296 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21299 case BFD_RELOC_ARM_THUMB_SHIFT
:
21300 /* 5bit shift value (0..32). LSL cannot take 32. */
21301 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21302 temp
= newval
& 0xf800;
21303 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21305 _("invalid shift value: %ld"), (long) value
);
21306 /* Shifts of zero must be encoded as LSL. */
21308 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21309 /* Shifts of 32 are encoded as zero. */
21310 else if (value
== 32)
21312 newval
|= value
<< 6;
21313 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21316 case BFD_RELOC_VTABLE_INHERIT
:
21317 case BFD_RELOC_VTABLE_ENTRY
:
21321 case BFD_RELOC_ARM_MOVW
:
21322 case BFD_RELOC_ARM_MOVT
:
21323 case BFD_RELOC_ARM_THUMB_MOVW
:
21324 case BFD_RELOC_ARM_THUMB_MOVT
:
21325 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21327 /* REL format relocations are limited to a 16-bit addend. */
21328 if (!fixP
->fx_done
)
21330 if (value
< -0x8000 || value
> 0x7fff)
21331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21332 _("offset out of range"));
21334 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21335 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21340 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21341 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21343 newval
= get_thumb32_insn (buf
);
21344 newval
&= 0xfbf08f00;
21345 newval
|= (value
& 0xf000) << 4;
21346 newval
|= (value
& 0x0800) << 15;
21347 newval
|= (value
& 0x0700) << 4;
21348 newval
|= (value
& 0x00ff);
21349 put_thumb32_insn (buf
, newval
);
21353 newval
= md_chars_to_number (buf
, 4);
21354 newval
&= 0xfff0f000;
21355 newval
|= value
& 0x0fff;
21356 newval
|= (value
& 0xf000) << 4;
21357 md_number_to_chars (buf
, newval
, 4);
21362 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21363 case BFD_RELOC_ARM_ALU_PC_G0
:
21364 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21365 case BFD_RELOC_ARM_ALU_PC_G1
:
21366 case BFD_RELOC_ARM_ALU_PC_G2
:
21367 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21368 case BFD_RELOC_ARM_ALU_SB_G0
:
21369 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21370 case BFD_RELOC_ARM_ALU_SB_G1
:
21371 case BFD_RELOC_ARM_ALU_SB_G2
:
21372 gas_assert (!fixP
->fx_done
);
21373 if (!seg
->use_rela_p
)
21376 bfd_vma encoded_addend
;
21377 bfd_vma addend_abs
= abs (value
);
21379 /* Check that the absolute value of the addend can be
21380 expressed as an 8-bit constant plus a rotation. */
21381 encoded_addend
= encode_arm_immediate (addend_abs
);
21382 if (encoded_addend
== (unsigned int) FAIL
)
21383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21384 _("the offset 0x%08lX is not representable"),
21385 (unsigned long) addend_abs
);
21387 /* Extract the instruction. */
21388 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21390 /* If the addend is positive, use an ADD instruction.
21391 Otherwise use a SUB. Take care not to destroy the S bit. */
21392 insn
&= 0xff1fffff;
21398 /* Place the encoded addend into the first 12 bits of the
21400 insn
&= 0xfffff000;
21401 insn
|= encoded_addend
;
21403 /* Update the instruction. */
21404 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21408 case BFD_RELOC_ARM_LDR_PC_G0
:
21409 case BFD_RELOC_ARM_LDR_PC_G1
:
21410 case BFD_RELOC_ARM_LDR_PC_G2
:
21411 case BFD_RELOC_ARM_LDR_SB_G0
:
21412 case BFD_RELOC_ARM_LDR_SB_G1
:
21413 case BFD_RELOC_ARM_LDR_SB_G2
:
21414 gas_assert (!fixP
->fx_done
);
21415 if (!seg
->use_rela_p
)
21418 bfd_vma addend_abs
= abs (value
);
21420 /* Check that the absolute value of the addend can be
21421 encoded in 12 bits. */
21422 if (addend_abs
>= 0x1000)
21423 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21424 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21425 (unsigned long) addend_abs
);
21427 /* Extract the instruction. */
21428 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21430 /* If the addend is negative, clear bit 23 of the instruction.
21431 Otherwise set it. */
21433 insn
&= ~(1 << 23);
21437 /* Place the absolute value of the addend into the first 12 bits
21438 of the instruction. */
21439 insn
&= 0xfffff000;
21440 insn
|= addend_abs
;
21442 /* Update the instruction. */
21443 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21447 case BFD_RELOC_ARM_LDRS_PC_G0
:
21448 case BFD_RELOC_ARM_LDRS_PC_G1
:
21449 case BFD_RELOC_ARM_LDRS_PC_G2
:
21450 case BFD_RELOC_ARM_LDRS_SB_G0
:
21451 case BFD_RELOC_ARM_LDRS_SB_G1
:
21452 case BFD_RELOC_ARM_LDRS_SB_G2
:
21453 gas_assert (!fixP
->fx_done
);
21454 if (!seg
->use_rela_p
)
21457 bfd_vma addend_abs
= abs (value
);
21459 /* Check that the absolute value of the addend can be
21460 encoded in 8 bits. */
21461 if (addend_abs
>= 0x100)
21462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21463 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21464 (unsigned long) addend_abs
);
21466 /* Extract the instruction. */
21467 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21469 /* If the addend is negative, clear bit 23 of the instruction.
21470 Otherwise set it. */
21472 insn
&= ~(1 << 23);
21476 /* Place the first four bits of the absolute value of the addend
21477 into the first 4 bits of the instruction, and the remaining
21478 four into bits 8 .. 11. */
21479 insn
&= 0xfffff0f0;
21480 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21482 /* Update the instruction. */
21483 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21487 case BFD_RELOC_ARM_LDC_PC_G0
:
21488 case BFD_RELOC_ARM_LDC_PC_G1
:
21489 case BFD_RELOC_ARM_LDC_PC_G2
:
21490 case BFD_RELOC_ARM_LDC_SB_G0
:
21491 case BFD_RELOC_ARM_LDC_SB_G1
:
21492 case BFD_RELOC_ARM_LDC_SB_G2
:
21493 gas_assert (!fixP
->fx_done
);
21494 if (!seg
->use_rela_p
)
21497 bfd_vma addend_abs
= abs (value
);
21499 /* Check that the absolute value of the addend is a multiple of
21500 four and, when divided by four, fits in 8 bits. */
21501 if (addend_abs
& 0x3)
21502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21503 _("bad offset 0x%08lX (must be word-aligned)"),
21504 (unsigned long) addend_abs
);
21506 if ((addend_abs
>> 2) > 0xff)
21507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21508 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21509 (unsigned long) addend_abs
);
21511 /* Extract the instruction. */
21512 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21514 /* If the addend is negative, clear bit 23 of the instruction.
21515 Otherwise set it. */
21517 insn
&= ~(1 << 23);
21521 /* Place the addend (divided by four) into the first eight
21522 bits of the instruction. */
21523 insn
&= 0xfffffff0;
21524 insn
|= addend_abs
>> 2;
21526 /* Update the instruction. */
21527 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21531 case BFD_RELOC_ARM_V4BX
:
21532 /* This will need to go in the object file. */
21536 case BFD_RELOC_UNUSED
:
21538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21539 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21543 /* Translate internal representation of relocation info to BFD target
21547 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21550 bfd_reloc_code_real_type code
;
21552 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21554 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21555 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21556 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21558 if (fixp
->fx_pcrel
)
21560 if (section
->use_rela_p
)
21561 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21563 fixp
->fx_offset
= reloc
->address
;
21565 reloc
->addend
= fixp
->fx_offset
;
21567 switch (fixp
->fx_r_type
)
21570 if (fixp
->fx_pcrel
)
21572 code
= BFD_RELOC_8_PCREL
;
21577 if (fixp
->fx_pcrel
)
21579 code
= BFD_RELOC_16_PCREL
;
21584 if (fixp
->fx_pcrel
)
21586 code
= BFD_RELOC_32_PCREL
;
21590 case BFD_RELOC_ARM_MOVW
:
21591 if (fixp
->fx_pcrel
)
21593 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21597 case BFD_RELOC_ARM_MOVT
:
21598 if (fixp
->fx_pcrel
)
21600 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21604 case BFD_RELOC_ARM_THUMB_MOVW
:
21605 if (fixp
->fx_pcrel
)
21607 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21611 case BFD_RELOC_ARM_THUMB_MOVT
:
21612 if (fixp
->fx_pcrel
)
21614 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21618 case BFD_RELOC_NONE
:
21619 case BFD_RELOC_ARM_PCREL_BRANCH
:
21620 case BFD_RELOC_ARM_PCREL_BLX
:
21621 case BFD_RELOC_RVA
:
21622 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21623 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21624 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21625 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21626 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21627 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21628 case BFD_RELOC_VTABLE_ENTRY
:
21629 case BFD_RELOC_VTABLE_INHERIT
:
21631 case BFD_RELOC_32_SECREL
:
21633 code
= fixp
->fx_r_type
;
21636 case BFD_RELOC_THUMB_PCREL_BLX
:
21638 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21639 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21642 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21645 case BFD_RELOC_ARM_LITERAL
:
21646 case BFD_RELOC_ARM_HWLITERAL
:
21647 /* If this is called then the a literal has
21648 been referenced across a section boundary. */
21649 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21650 _("literal referenced across section boundary"));
21654 case BFD_RELOC_ARM_TLS_CALL
:
21655 case BFD_RELOC_ARM_THM_TLS_CALL
:
21656 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21657 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21658 case BFD_RELOC_ARM_GOT32
:
21659 case BFD_RELOC_ARM_GOTOFF
:
21660 case BFD_RELOC_ARM_GOT_PREL
:
21661 case BFD_RELOC_ARM_PLT32
:
21662 case BFD_RELOC_ARM_TARGET1
:
21663 case BFD_RELOC_ARM_ROSEGREL32
:
21664 case BFD_RELOC_ARM_SBREL32
:
21665 case BFD_RELOC_ARM_PREL31
:
21666 case BFD_RELOC_ARM_TARGET2
:
21667 case BFD_RELOC_ARM_TLS_LE32
:
21668 case BFD_RELOC_ARM_TLS_LDO32
:
21669 case BFD_RELOC_ARM_PCREL_CALL
:
21670 case BFD_RELOC_ARM_PCREL_JUMP
:
21671 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21672 case BFD_RELOC_ARM_ALU_PC_G0
:
21673 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21674 case BFD_RELOC_ARM_ALU_PC_G1
:
21675 case BFD_RELOC_ARM_ALU_PC_G2
:
21676 case BFD_RELOC_ARM_LDR_PC_G0
:
21677 case BFD_RELOC_ARM_LDR_PC_G1
:
21678 case BFD_RELOC_ARM_LDR_PC_G2
:
21679 case BFD_RELOC_ARM_LDRS_PC_G0
:
21680 case BFD_RELOC_ARM_LDRS_PC_G1
:
21681 case BFD_RELOC_ARM_LDRS_PC_G2
:
21682 case BFD_RELOC_ARM_LDC_PC_G0
:
21683 case BFD_RELOC_ARM_LDC_PC_G1
:
21684 case BFD_RELOC_ARM_LDC_PC_G2
:
21685 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21686 case BFD_RELOC_ARM_ALU_SB_G0
:
21687 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21688 case BFD_RELOC_ARM_ALU_SB_G1
:
21689 case BFD_RELOC_ARM_ALU_SB_G2
:
21690 case BFD_RELOC_ARM_LDR_SB_G0
:
21691 case BFD_RELOC_ARM_LDR_SB_G1
:
21692 case BFD_RELOC_ARM_LDR_SB_G2
:
21693 case BFD_RELOC_ARM_LDRS_SB_G0
:
21694 case BFD_RELOC_ARM_LDRS_SB_G1
:
21695 case BFD_RELOC_ARM_LDRS_SB_G2
:
21696 case BFD_RELOC_ARM_LDC_SB_G0
:
21697 case BFD_RELOC_ARM_LDC_SB_G1
:
21698 case BFD_RELOC_ARM_LDC_SB_G2
:
21699 case BFD_RELOC_ARM_V4BX
:
21700 code
= fixp
->fx_r_type
;
21703 case BFD_RELOC_ARM_TLS_GOTDESC
:
21704 case BFD_RELOC_ARM_TLS_GD32
:
21705 case BFD_RELOC_ARM_TLS_IE32
:
21706 case BFD_RELOC_ARM_TLS_LDM32
:
21707 /* BFD will include the symbol's address in the addend.
21708 But we don't want that, so subtract it out again here. */
21709 if (!S_IS_COMMON (fixp
->fx_addsy
))
21710 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21711 code
= fixp
->fx_r_type
;
21715 case BFD_RELOC_ARM_IMMEDIATE
:
21716 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21717 _("internal relocation (type: IMMEDIATE) not fixed up"));
21720 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21721 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21722 _("ADRL used for a symbol not defined in the same file"));
21725 case BFD_RELOC_ARM_OFFSET_IMM
:
21726 if (section
->use_rela_p
)
21728 code
= fixp
->fx_r_type
;
21732 if (fixp
->fx_addsy
!= NULL
21733 && !S_IS_DEFINED (fixp
->fx_addsy
)
21734 && S_IS_LOCAL (fixp
->fx_addsy
))
21736 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21737 _("undefined local label `%s'"),
21738 S_GET_NAME (fixp
->fx_addsy
));
21742 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21743 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21750 switch (fixp
->fx_r_type
)
21752 case BFD_RELOC_NONE
: type
= "NONE"; break;
21753 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21754 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21755 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21756 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21757 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21758 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21759 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21760 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21761 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21762 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21763 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21764 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21765 default: type
= _("<unknown>"); break;
21767 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21768 _("cannot represent %s relocation in this object file format"),
21775 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21777 && fixp
->fx_addsy
== GOT_symbol
)
21779 code
= BFD_RELOC_ARM_GOTPC
;
21780 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21784 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21786 if (reloc
->howto
== NULL
)
21788 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21789 _("cannot represent %s relocation in this object file format"),
21790 bfd_get_reloc_code_name (code
));
21794 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21795 vtable entry to be used in the relocation's section offset. */
21796 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21797 reloc
->address
= fixp
->fx_offset
;
21802 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21805 cons_fix_new_arm (fragS
* frag
,
21810 bfd_reloc_code_real_type type
;
21814 FIXME: @@ Should look at CPU word size. */
21818 type
= BFD_RELOC_8
;
21821 type
= BFD_RELOC_16
;
21825 type
= BFD_RELOC_32
;
21828 type
= BFD_RELOC_64
;
21833 if (exp
->X_op
== O_secrel
)
21835 exp
->X_op
= O_symbol
;
21836 type
= BFD_RELOC_32_SECREL
;
21840 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21843 #if defined (OBJ_COFF)
21845 arm_validate_fix (fixS
* fixP
)
21847 /* If the destination of the branch is a defined symbol which does not have
21848 the THUMB_FUNC attribute, then we must be calling a function which has
21849 the (interfacearm) attribute. We look for the Thumb entry point to that
21850 function and change the branch to refer to that function instead. */
21851 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21852 && fixP
->fx_addsy
!= NULL
21853 && S_IS_DEFINED (fixP
->fx_addsy
)
21854 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21856 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21863 arm_force_relocation (struct fix
* fixp
)
21865 #if defined (OBJ_COFF) && defined (TE_PE)
21866 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21870 /* In case we have a call or a branch to a function in ARM ISA mode from
21871 a thumb function or vice-versa force the relocation. These relocations
21872 are cleared off for some cores that might have blx and simple transformations
21876 switch (fixp
->fx_r_type
)
21878 case BFD_RELOC_ARM_PCREL_JUMP
:
21879 case BFD_RELOC_ARM_PCREL_CALL
:
21880 case BFD_RELOC_THUMB_PCREL_BLX
:
21881 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21885 case BFD_RELOC_ARM_PCREL_BLX
:
21886 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21887 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21888 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21889 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21898 /* Resolve these relocations even if the symbol is extern or weak.
21899 Technically this is probably wrong due to symbol preemption.
21900 In practice these relocations do not have enough range to be useful
21901 at dynamic link time, and some code (e.g. in the Linux kernel)
21902 expects these references to be resolved. */
21903 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21904 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21905 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
21906 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21907 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21908 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
21909 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
21910 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21911 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21912 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21913 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
21914 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
21915 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
21916 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
21919 /* Always leave these relocations for the linker. */
21920 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21921 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21922 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21925 /* Always generate relocations against function symbols. */
21926 if (fixp
->fx_r_type
== BFD_RELOC_32
21928 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21931 return generic_force_reloc (fixp
);
21934 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21935 /* Relocations against function names must be left unadjusted,
21936 so that the linker can use this information to generate interworking
21937 stubs. The MIPS version of this function
21938 also prevents relocations that are mips-16 specific, but I do not
21939 know why it does this.
21942 There is one other problem that ought to be addressed here, but
21943 which currently is not: Taking the address of a label (rather
21944 than a function) and then later jumping to that address. Such
21945 addresses also ought to have their bottom bit set (assuming that
21946 they reside in Thumb code), but at the moment they will not. */
21949 arm_fix_adjustable (fixS
* fixP
)
21951 if (fixP
->fx_addsy
== NULL
)
21954 /* Preserve relocations against symbols with function type. */
21955 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21958 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21959 && fixP
->fx_subsy
== NULL
)
21962 /* We need the symbol name for the VTABLE entries. */
21963 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21964 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21967 /* Don't allow symbols to be discarded on GOT related relocs. */
21968 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21969 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21970 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21971 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21972 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21973 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21974 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21975 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21976 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
21977 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
21978 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
21979 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
21980 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
21981 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21984 /* Similarly for group relocations. */
21985 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21986 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21987 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21990 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21991 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21992 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21993 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21994 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21995 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21996 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21997 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21998 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22003 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22008 elf32_arm_target_format (void)
22011 return (target_big_endian
22012 ? "elf32-bigarm-symbian"
22013 : "elf32-littlearm-symbian");
22014 #elif defined (TE_VXWORKS)
22015 return (target_big_endian
22016 ? "elf32-bigarm-vxworks"
22017 : "elf32-littlearm-vxworks");
22019 if (target_big_endian
)
22020 return "elf32-bigarm";
22022 return "elf32-littlearm";
22027 armelf_frob_symbol (symbolS
* symp
,
22030 elf_frob_symbol (symp
, puntp
);
22034 /* MD interface: Finalization. */
22039 literal_pool
* pool
;
22041 /* Ensure that all the IT blocks are properly closed. */
22042 check_it_blocks_finished ();
22044 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22046 /* Put it at the end of the relevant section. */
22047 subseg_set (pool
->section
, pool
->sub_section
);
22049 arm_elf_change_section ();
22056 /* Remove any excess mapping symbols generated for alignment frags in
22057 SEC. We may have created a mapping symbol before a zero byte
22058 alignment; remove it if there's a mapping symbol after the
22061 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22062 void *dummy ATTRIBUTE_UNUSED
)
22064 segment_info_type
*seginfo
= seg_info (sec
);
22067 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22070 for (fragp
= seginfo
->frchainP
->frch_root
;
22072 fragp
= fragp
->fr_next
)
22074 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22075 fragS
*next
= fragp
->fr_next
;
22077 /* Variable-sized frags have been converted to fixed size by
22078 this point. But if this was variable-sized to start with,
22079 there will be a fixed-size frag after it. So don't handle
22081 if (sym
== NULL
|| next
== NULL
)
22084 if (S_GET_VALUE (sym
) < next
->fr_address
)
22085 /* Not at the end of this frag. */
22087 know (S_GET_VALUE (sym
) == next
->fr_address
);
22091 if (next
->tc_frag_data
.first_map
!= NULL
)
22093 /* Next frag starts with a mapping symbol. Discard this
22095 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22099 if (next
->fr_next
== NULL
)
22101 /* This mapping symbol is at the end of the section. Discard
22103 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22104 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22108 /* As long as we have empty frags without any mapping symbols,
22110 /* If the next frag is non-empty and does not start with a
22111 mapping symbol, then this mapping symbol is required. */
22112 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22115 next
= next
->fr_next
;
22117 while (next
!= NULL
);
22122 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22126 arm_adjust_symtab (void)
22131 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22133 if (ARM_IS_THUMB (sym
))
22135 if (THUMB_IS_FUNC (sym
))
22137 /* Mark the symbol as a Thumb function. */
22138 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22139 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22140 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22142 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22143 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22145 as_bad (_("%s: unexpected function type: %d"),
22146 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22148 else switch (S_GET_STORAGE_CLASS (sym
))
22151 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22154 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22157 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22165 if (ARM_IS_INTERWORK (sym
))
22166 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22173 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22175 if (ARM_IS_THUMB (sym
))
22177 elf_symbol_type
* elf_sym
;
22179 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22180 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22182 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22183 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22185 /* If it's a .thumb_func, declare it as so,
22186 otherwise tag label as .code 16. */
22187 if (THUMB_IS_FUNC (sym
))
22188 elf_sym
->internal_elf_sym
.st_target_internal
22189 = ST_BRANCH_TO_THUMB
;
22190 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22191 elf_sym
->internal_elf_sym
.st_info
=
22192 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22197 /* Remove any overlapping mapping symbols generated by alignment frags. */
22198 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22199 /* Now do generic ELF adjustments. */
22200 elf_adjust_symtab ();
22204 /* MD interface: Initialization. */
22207 set_constant_flonums (void)
22211 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22212 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22216 /* Auto-select Thumb mode if it's the only available instruction set for the
22217 given architecture. */
22220 autoselect_thumb_from_cpu_variant (void)
22222 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22223 opcode_select (16);
22232 if ( (arm_ops_hsh
= hash_new ()) == NULL
22233 || (arm_cond_hsh
= hash_new ()) == NULL
22234 || (arm_shift_hsh
= hash_new ()) == NULL
22235 || (arm_psr_hsh
= hash_new ()) == NULL
22236 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22237 || (arm_reg_hsh
= hash_new ()) == NULL
22238 || (arm_reloc_hsh
= hash_new ()) == NULL
22239 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22240 as_fatal (_("virtual memory exhausted"));
22242 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22243 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22244 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22245 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22246 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22247 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22248 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22249 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22250 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22251 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22252 (void *) (v7m_psrs
+ i
));
22253 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22254 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22256 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22258 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22259 (void *) (barrier_opt_names
+ i
));
22261 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22262 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22265 set_constant_flonums ();
22267 /* Set the cpu variant based on the command-line options. We prefer
22268 -mcpu= over -march= if both are set (as for GCC); and we prefer
22269 -mfpu= over any other way of setting the floating point unit.
22270 Use of legacy options with new options are faulted. */
22273 if (mcpu_cpu_opt
|| march_cpu_opt
)
22274 as_bad (_("use of old and new-style options to set CPU type"));
22276 mcpu_cpu_opt
= legacy_cpu
;
22278 else if (!mcpu_cpu_opt
)
22279 mcpu_cpu_opt
= march_cpu_opt
;
22284 as_bad (_("use of old and new-style options to set FPU type"));
22286 mfpu_opt
= legacy_fpu
;
22288 else if (!mfpu_opt
)
22290 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22291 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22292 /* Some environments specify a default FPU. If they don't, infer it
22293 from the processor. */
22295 mfpu_opt
= mcpu_fpu_opt
;
22297 mfpu_opt
= march_fpu_opt
;
22299 mfpu_opt
= &fpu_default
;
22305 if (mcpu_cpu_opt
!= NULL
)
22306 mfpu_opt
= &fpu_default
;
22307 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22308 mfpu_opt
= &fpu_arch_vfp_v2
;
22310 mfpu_opt
= &fpu_arch_fpa
;
22316 mcpu_cpu_opt
= &cpu_default
;
22317 selected_cpu
= cpu_default
;
22321 selected_cpu
= *mcpu_cpu_opt
;
22323 mcpu_cpu_opt
= &arm_arch_any
;
22326 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22328 autoselect_thumb_from_cpu_variant ();
22330 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22332 #if defined OBJ_COFF || defined OBJ_ELF
22334 unsigned int flags
= 0;
22336 #if defined OBJ_ELF
22337 flags
= meabi_flags
;
22339 switch (meabi_flags
)
22341 case EF_ARM_EABI_UNKNOWN
:
22343 /* Set the flags in the private structure. */
22344 if (uses_apcs_26
) flags
|= F_APCS26
;
22345 if (support_interwork
) flags
|= F_INTERWORK
;
22346 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22347 if (pic_code
) flags
|= F_PIC
;
22348 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22349 flags
|= F_SOFT_FLOAT
;
22351 switch (mfloat_abi_opt
)
22353 case ARM_FLOAT_ABI_SOFT
:
22354 case ARM_FLOAT_ABI_SOFTFP
:
22355 flags
|= F_SOFT_FLOAT
;
22358 case ARM_FLOAT_ABI_HARD
:
22359 if (flags
& F_SOFT_FLOAT
)
22360 as_bad (_("hard-float conflicts with specified fpu"));
22364 /* Using pure-endian doubles (even if soft-float). */
22365 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22366 flags
|= F_VFP_FLOAT
;
22368 #if defined OBJ_ELF
22369 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22370 flags
|= EF_ARM_MAVERICK_FLOAT
;
22373 case EF_ARM_EABI_VER4
:
22374 case EF_ARM_EABI_VER5
:
22375 /* No additional flags to set. */
22382 bfd_set_private_flags (stdoutput
, flags
);
22384 /* We have run out flags in the COFF header to encode the
22385 status of ATPCS support, so instead we create a dummy,
22386 empty, debug section called .arm.atpcs. */
22391 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22395 bfd_set_section_flags
22396 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22397 bfd_set_section_size (stdoutput
, sec
, 0);
22398 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22404 /* Record the CPU type as well. */
22405 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22406 mach
= bfd_mach_arm_iWMMXt2
;
22407 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22408 mach
= bfd_mach_arm_iWMMXt
;
22409 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22410 mach
= bfd_mach_arm_XScale
;
22411 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22412 mach
= bfd_mach_arm_ep9312
;
22413 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22414 mach
= bfd_mach_arm_5TE
;
22415 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22417 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22418 mach
= bfd_mach_arm_5T
;
22420 mach
= bfd_mach_arm_5
;
22422 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22424 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22425 mach
= bfd_mach_arm_4T
;
22427 mach
= bfd_mach_arm_4
;
22429 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22430 mach
= bfd_mach_arm_3M
;
22431 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22432 mach
= bfd_mach_arm_3
;
22433 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22434 mach
= bfd_mach_arm_2a
;
22435 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22436 mach
= bfd_mach_arm_2
;
22438 mach
= bfd_mach_arm_unknown
;
22440 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22443 /* Command line processing. */
22446 Invocation line includes a switch not recognized by the base assembler.
22447 See if it's a processor-specific option.
22449 This routine is somewhat complicated by the need for backwards
22450 compatibility (since older releases of gcc can't be changed).
22451 The new options try to make the interface as compatible as
22454 New options (supported) are:
22456 -mcpu=<cpu name> Assemble for selected processor
22457 -march=<architecture name> Assemble for selected architecture
22458 -mfpu=<fpu architecture> Assemble for selected FPU.
22459 -EB/-mbig-endian Big-endian
22460 -EL/-mlittle-endian Little-endian
22461 -k Generate PIC code
22462 -mthumb Start in Thumb mode
22463 -mthumb-interwork Code supports ARM/Thumb interworking
22465 -m[no-]warn-deprecated Warn about deprecated features
22467 For now we will also provide support for:
22469 -mapcs-32 32-bit Program counter
22470 -mapcs-26 26-bit Program counter
22471 -macps-float Floats passed in FP registers
22472 -mapcs-reentrant Reentrant code
22474 (sometime these will probably be replaced with -mapcs=<list of options>
22475 and -matpcs=<list of options>)
22477 The remaining options are only supported for back-wards compatibility.
22478 Cpu variants, the arm part is optional:
22479 -m[arm]1 Currently not supported.
22480 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22481 -m[arm]3 Arm 3 processor
22482 -m[arm]6[xx], Arm 6 processors
22483 -m[arm]7[xx][t][[d]m] Arm 7 processors
22484 -m[arm]8[10] Arm 8 processors
22485 -m[arm]9[20][tdmi] Arm 9 processors
22486 -mstrongarm[110[0]] StrongARM processors
22487 -mxscale XScale processors
22488 -m[arm]v[2345[t[e]]] Arm architectures
22489 -mall All (except the ARM1)
22491 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22492 -mfpe-old (No float load/store multiples)
22493 -mvfpxd VFP Single precision
22495 -mno-fpu Disable all floating point instructions
22497 The following CPU names are recognized:
22498 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22499 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22500 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22501 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22502 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22503 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22504 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22508 const char * md_shortopts
= "m:k";
22510 #ifdef ARM_BI_ENDIAN
22511 #define OPTION_EB (OPTION_MD_BASE + 0)
22512 #define OPTION_EL (OPTION_MD_BASE + 1)
22514 #if TARGET_BYTES_BIG_ENDIAN
22515 #define OPTION_EB (OPTION_MD_BASE + 0)
22517 #define OPTION_EL (OPTION_MD_BASE + 1)
22520 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22522 struct option md_longopts
[] =
22525 {"EB", no_argument
, NULL
, OPTION_EB
},
22528 {"EL", no_argument
, NULL
, OPTION_EL
},
22530 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22531 {NULL
, no_argument
, NULL
, 0}
22534 size_t md_longopts_size
= sizeof (md_longopts
);
22536 struct arm_option_table
22538 char *option
; /* Option name to match. */
22539 char *help
; /* Help information. */
22540 int *var
; /* Variable to change. */
22541 int value
; /* What to change it to. */
22542 char *deprecated
; /* If non-null, print this message. */
22545 struct arm_option_table arm_opts
[] =
22547 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22548 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22549 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22550 &support_interwork
, 1, NULL
},
22551 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22552 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22553 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22555 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22556 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22557 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22558 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22561 /* These are recognized by the assembler, but have no affect on code. */
22562 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22563 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22565 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22566 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22567 &warn_on_deprecated
, 0, NULL
},
22568 {NULL
, NULL
, NULL
, 0, NULL
}
22571 struct arm_legacy_option_table
22573 char *option
; /* Option name to match. */
22574 const arm_feature_set
**var
; /* Variable to change. */
22575 const arm_feature_set value
; /* What to change it to. */
22576 char *deprecated
; /* If non-null, print this message. */
22579 const struct arm_legacy_option_table arm_legacy_opts
[] =
22581 /* DON'T add any new processors to this list -- we want the whole list
22582 to go away... Add them to the processors table instead. */
22583 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22584 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22585 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22586 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22587 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22588 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22589 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22590 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22591 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22592 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22593 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22594 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22595 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22596 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22597 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22598 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22599 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22600 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22601 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22602 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22603 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22604 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22605 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22606 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22607 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22608 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22609 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22610 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22611 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22612 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22613 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22614 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22615 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22616 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22617 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22618 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22619 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22620 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22621 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22622 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22623 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22624 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22625 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22626 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22627 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22628 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22629 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22630 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22631 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22632 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22633 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22634 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22635 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22636 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22637 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22638 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22639 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22640 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22641 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22642 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22643 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22644 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22645 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22646 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22647 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22648 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22649 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22650 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22651 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22652 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22653 N_("use -mcpu=strongarm110")},
22654 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22655 N_("use -mcpu=strongarm1100")},
22656 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22657 N_("use -mcpu=strongarm1110")},
22658 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22659 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22660 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22662 /* Architecture variants -- don't add any more to this list either. */
22663 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22664 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22665 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22666 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22667 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22668 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22669 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22670 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22671 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22672 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22673 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22674 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22675 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22676 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22677 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22678 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22679 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22680 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22682 /* Floating point variants -- don't add any more to this list either. */
22683 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22684 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22685 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22686 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22687 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22689 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22692 struct arm_cpu_option_table
22695 const arm_feature_set value
;
22696 /* For some CPUs we assume an FPU unless the user explicitly sets
22698 const arm_feature_set default_fpu
;
22699 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22701 const char *canonical_name
;
22704 /* This list should, at a minimum, contain all the cpu names
22705 recognized by GCC. */
22706 static const struct arm_cpu_option_table arm_cpus
[] =
22708 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22709 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22710 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22711 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22712 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22713 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22714 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22715 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22716 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22717 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22718 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22719 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22720 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22721 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22722 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22723 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22724 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22725 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22726 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22727 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22728 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22729 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22730 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22731 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22732 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22733 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22734 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22735 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22736 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22737 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22738 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22739 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22740 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22741 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22742 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22743 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22744 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22745 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22746 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22747 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22748 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22749 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22750 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22751 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22752 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22753 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22754 /* For V5 or later processors we default to using VFP; but the user
22755 should really set the FPU type explicitly. */
22756 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22757 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22758 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22759 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22760 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22761 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22762 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22763 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22764 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22765 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22766 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22767 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22768 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22769 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22770 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22771 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22772 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22773 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22774 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22775 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22776 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22777 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22778 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22779 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22780 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22781 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22782 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22783 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22784 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22785 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22786 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22787 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22788 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22789 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22790 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22791 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22792 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22793 FPU_NONE
, "Cortex-A5"},
22794 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22795 ARM_FEATURE (0, FPU_VFP_V3
22796 | FPU_NEON_EXT_V1
),
22798 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22799 ARM_FEATURE (0, FPU_VFP_V3
22800 | FPU_NEON_EXT_V1
),
22802 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22803 FPU_ARCH_NEON_VFP_V4
,
22805 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22806 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22808 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22809 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22810 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22811 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22812 /* ??? XSCALE is really an architecture. */
22813 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22814 /* ??? iwmmxt is not a processor. */
22815 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22816 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22817 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22819 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22820 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22823 struct arm_arch_option_table
22826 const arm_feature_set value
;
22827 const arm_feature_set default_fpu
;
22830 /* This list should, at a minimum, contain all the architecture names
22831 recognized by GCC. */
22832 static const struct arm_arch_option_table arm_archs
[] =
22834 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22835 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22836 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22837 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22838 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22839 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22840 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22841 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22842 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22843 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22844 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22845 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22846 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22847 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22848 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22849 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22850 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22851 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22852 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22853 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22854 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22855 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22856 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22857 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22858 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22859 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22860 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22861 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22862 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22863 /* The official spelling of the ARMv7 profile variants is the dashed form.
22864 Accept the non-dashed form for compatibility with old toolchains. */
22865 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22866 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22867 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22868 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22869 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22870 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22871 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22872 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22873 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22874 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22875 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22878 /* ISA extensions in the co-processor and main instruction set space. */
22879 struct arm_option_extension_value_table
22882 const arm_feature_set value
;
22883 const arm_feature_set allowed_archs
;
22886 /* The following table must be in alphabetical order with a NULL last entry.
22888 static const struct arm_option_extension_value_table arm_extensions
[] =
22890 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22891 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22892 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22893 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22894 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22895 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22896 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22897 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22898 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22899 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22900 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22901 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22902 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22903 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22904 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22907 /* ISA floating-point and Advanced SIMD extensions. */
22908 struct arm_option_fpu_value_table
22911 const arm_feature_set value
;
22914 /* This list should, at a minimum, contain all the fpu names
22915 recognized by GCC. */
22916 static const struct arm_option_fpu_value_table arm_fpus
[] =
22918 {"softfpa", FPU_NONE
},
22919 {"fpe", FPU_ARCH_FPE
},
22920 {"fpe2", FPU_ARCH_FPE
},
22921 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22922 {"fpa", FPU_ARCH_FPA
},
22923 {"fpa10", FPU_ARCH_FPA
},
22924 {"fpa11", FPU_ARCH_FPA
},
22925 {"arm7500fe", FPU_ARCH_FPA
},
22926 {"softvfp", FPU_ARCH_VFP
},
22927 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22928 {"vfp", FPU_ARCH_VFP_V2
},
22929 {"vfp9", FPU_ARCH_VFP_V2
},
22930 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22931 {"vfp10", FPU_ARCH_VFP_V2
},
22932 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22933 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22934 {"vfpv2", FPU_ARCH_VFP_V2
},
22935 {"vfpv3", FPU_ARCH_VFP_V3
},
22936 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22937 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22938 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22939 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22940 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22941 {"arm1020t", FPU_ARCH_VFP_V1
},
22942 {"arm1020e", FPU_ARCH_VFP_V2
},
22943 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22944 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22945 {"maverick", FPU_ARCH_MAVERICK
},
22946 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22947 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22948 {"vfpv4", FPU_ARCH_VFP_V4
},
22949 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22950 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22951 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22952 {NULL
, ARM_ARCH_NONE
}
22955 struct arm_option_value_table
22961 static const struct arm_option_value_table arm_float_abis
[] =
22963 {"hard", ARM_FLOAT_ABI_HARD
},
22964 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22965 {"soft", ARM_FLOAT_ABI_SOFT
},
22970 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22971 static const struct arm_option_value_table arm_eabis
[] =
22973 {"gnu", EF_ARM_EABI_UNKNOWN
},
22974 {"4", EF_ARM_EABI_VER4
},
22975 {"5", EF_ARM_EABI_VER5
},
22980 struct arm_long_option_table
22982 char * option
; /* Substring to match. */
22983 char * help
; /* Help information. */
22984 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22985 char * deprecated
; /* If non-null, print this message. */
22989 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22991 arm_feature_set
*ext_set
= (arm_feature_set
*)
22992 xmalloc (sizeof (arm_feature_set
));
22994 /* We insist on extensions being specified in alphabetical order, and with
22995 extensions being added before being removed. We achieve this by having
22996 the global ARM_EXTENSIONS table in alphabetical order, and using the
22997 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22998 or removing it (0) and only allowing it to change in the order
23000 const struct arm_option_extension_value_table
* opt
= NULL
;
23001 int adding_value
= -1;
23003 /* Copy the feature set, so that we can modify it. */
23004 *ext_set
= **opt_p
;
23007 while (str
!= NULL
&& *str
!= 0)
23014 as_bad (_("invalid architectural extension"));
23019 ext
= strchr (str
, '+');
23022 optlen
= ext
- str
;
23024 optlen
= strlen (str
);
23027 && strncmp (str
, "no", 2) == 0)
23029 if (adding_value
!= 0)
23032 opt
= arm_extensions
;
23038 else if (optlen
> 0)
23040 if (adding_value
== -1)
23043 opt
= arm_extensions
;
23045 else if (adding_value
!= 1)
23047 as_bad (_("must specify extensions to add before specifying "
23048 "those to remove"));
23055 as_bad (_("missing architectural extension"));
23059 gas_assert (adding_value
!= -1);
23060 gas_assert (opt
!= NULL
);
23062 /* Scan over the options table trying to find an exact match. */
23063 for (; opt
->name
!= NULL
; opt
++)
23064 if (strncmp (opt
->name
, str
, optlen
) == 0
23065 && strlen (opt
->name
) == optlen
)
23067 /* Check we can apply the extension to this architecture. */
23068 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23070 as_bad (_("extension does not apply to the base architecture"));
23074 /* Add or remove the extension. */
23076 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23078 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23083 if (opt
->name
== NULL
)
23085 /* Did we fail to find an extension because it wasn't specified in
23086 alphabetical order, or because it does not exist? */
23088 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23089 if (strncmp (opt
->name
, str
, optlen
) == 0)
23092 if (opt
->name
== NULL
)
23093 as_bad (_("unknown architectural extension `%s'"), str
);
23095 as_bad (_("architectural extensions must be specified in "
23096 "alphabetical order"));
23102 /* We should skip the extension we've just matched the next time
23114 arm_parse_cpu (char * str
)
23116 const struct arm_cpu_option_table
* opt
;
23117 char * ext
= strchr (str
, '+');
23121 optlen
= ext
- str
;
23123 optlen
= strlen (str
);
23127 as_bad (_("missing cpu name `%s'"), str
);
23131 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23132 if (strncmp (opt
->name
, str
, optlen
) == 0)
23134 mcpu_cpu_opt
= &opt
->value
;
23135 mcpu_fpu_opt
= &opt
->default_fpu
;
23136 if (opt
->canonical_name
)
23137 strcpy (selected_cpu_name
, opt
->canonical_name
);
23142 for (i
= 0; i
< optlen
; i
++)
23143 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23144 selected_cpu_name
[i
] = 0;
23148 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23153 as_bad (_("unknown cpu `%s'"), str
);
23158 arm_parse_arch (char * str
)
23160 const struct arm_arch_option_table
*opt
;
23161 char *ext
= strchr (str
, '+');
23165 optlen
= ext
- str
;
23167 optlen
= strlen (str
);
23171 as_bad (_("missing architecture name `%s'"), str
);
23175 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23176 if (strncmp (opt
->name
, str
, optlen
) == 0)
23178 march_cpu_opt
= &opt
->value
;
23179 march_fpu_opt
= &opt
->default_fpu
;
23180 strcpy (selected_cpu_name
, opt
->name
);
23183 return arm_parse_extension (ext
, &march_cpu_opt
);
23188 as_bad (_("unknown architecture `%s'\n"), str
);
23193 arm_parse_fpu (char * str
)
23195 const struct arm_option_fpu_value_table
* opt
;
23197 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23198 if (streq (opt
->name
, str
))
23200 mfpu_opt
= &opt
->value
;
23204 as_bad (_("unknown floating point format `%s'\n"), str
);
23209 arm_parse_float_abi (char * str
)
23211 const struct arm_option_value_table
* opt
;
23213 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23214 if (streq (opt
->name
, str
))
23216 mfloat_abi_opt
= opt
->value
;
23220 as_bad (_("unknown floating point abi `%s'\n"), str
);
23226 arm_parse_eabi (char * str
)
23228 const struct arm_option_value_table
*opt
;
23230 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23231 if (streq (opt
->name
, str
))
23233 meabi_flags
= opt
->value
;
23236 as_bad (_("unknown EABI `%s'\n"), str
);
23242 arm_parse_it_mode (char * str
)
23244 bfd_boolean ret
= TRUE
;
23246 if (streq ("arm", str
))
23247 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23248 else if (streq ("thumb", str
))
23249 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23250 else if (streq ("always", str
))
23251 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23252 else if (streq ("never", str
))
23253 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23256 as_bad (_("unknown implicit IT mode `%s', should be "\
23257 "arm, thumb, always, or never."), str
);
23264 struct arm_long_option_table arm_long_opts
[] =
23266 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23267 arm_parse_cpu
, NULL
},
23268 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23269 arm_parse_arch
, NULL
},
23270 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23271 arm_parse_fpu
, NULL
},
23272 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23273 arm_parse_float_abi
, NULL
},
23275 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23276 arm_parse_eabi
, NULL
},
23278 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23279 arm_parse_it_mode
, NULL
},
23280 {NULL
, NULL
, 0, NULL
}
23284 md_parse_option (int c
, char * arg
)
23286 struct arm_option_table
*opt
;
23287 const struct arm_legacy_option_table
*fopt
;
23288 struct arm_long_option_table
*lopt
;
23294 target_big_endian
= 1;
23300 target_big_endian
= 0;
23304 case OPTION_FIX_V4BX
:
23309 /* Listing option. Just ignore these, we don't support additional
23314 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23316 if (c
== opt
->option
[0]
23317 && ((arg
== NULL
&& opt
->option
[1] == 0)
23318 || streq (arg
, opt
->option
+ 1)))
23320 /* If the option is deprecated, tell the user. */
23321 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23322 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23323 arg
? arg
: "", _(opt
->deprecated
));
23325 if (opt
->var
!= NULL
)
23326 *opt
->var
= opt
->value
;
23332 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23334 if (c
== fopt
->option
[0]
23335 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23336 || streq (arg
, fopt
->option
+ 1)))
23338 /* If the option is deprecated, tell the user. */
23339 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23340 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23341 arg
? arg
: "", _(fopt
->deprecated
));
23343 if (fopt
->var
!= NULL
)
23344 *fopt
->var
= &fopt
->value
;
23350 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23352 /* These options are expected to have an argument. */
23353 if (c
== lopt
->option
[0]
23355 && strncmp (arg
, lopt
->option
+ 1,
23356 strlen (lopt
->option
+ 1)) == 0)
23358 /* If the option is deprecated, tell the user. */
23359 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23360 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23361 _(lopt
->deprecated
));
23363 /* Call the sup-option parser. */
23364 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23375 md_show_usage (FILE * fp
)
23377 struct arm_option_table
*opt
;
23378 struct arm_long_option_table
*lopt
;
23380 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23382 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23383 if (opt
->help
!= NULL
)
23384 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23386 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23387 if (lopt
->help
!= NULL
)
23388 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23392 -EB assemble code for a big-endian cpu\n"));
23397 -EL assemble code for a little-endian cpu\n"));
23401 --fix-v4bx Allow BX in ARMv4 code\n"));
23409 arm_feature_set flags
;
23410 } cpu_arch_ver_table
;
23412 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23413 least features first. */
23414 static const cpu_arch_ver_table cpu_arch_ver
[] =
23420 {4, ARM_ARCH_V5TE
},
23421 {5, ARM_ARCH_V5TEJ
},
23425 {11, ARM_ARCH_V6M
},
23426 {12, ARM_ARCH_V6SM
},
23427 {8, ARM_ARCH_V6T2
},
23428 {10, ARM_ARCH_V7A
},
23429 {10, ARM_ARCH_V7R
},
23430 {10, ARM_ARCH_V7M
},
23434 /* Set an attribute if it has not already been set by the user. */
23436 aeabi_set_attribute_int (int tag
, int value
)
23439 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23440 || !attributes_set_explicitly
[tag
])
23441 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23445 aeabi_set_attribute_string (int tag
, const char *value
)
23448 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23449 || !attributes_set_explicitly
[tag
])
23450 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23453 /* Set the public EABI object attributes. */
23455 aeabi_set_public_attributes (void)
23459 arm_feature_set flags
;
23460 arm_feature_set tmp
;
23461 const cpu_arch_ver_table
*p
;
23463 /* Choose the architecture based on the capabilities of the requested cpu
23464 (if any) and/or the instructions actually used. */
23465 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23466 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23467 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23468 /*Allow the user to override the reported architecture. */
23471 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23472 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23475 /* We need to make sure that the attributes do not identify us as v6S-M
23476 when the only v6S-M feature in use is the Operating System Extensions. */
23477 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23478 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23479 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23483 for (p
= cpu_arch_ver
; p
->val
; p
++)
23485 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23488 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23492 /* The table lookup above finds the last architecture to contribute
23493 a new feature. Unfortunately, Tag13 is a subset of the union of
23494 v6T2 and v7-M, so it is never seen as contributing a new feature.
23495 We can not search for the last entry which is entirely used,
23496 because if no CPU is specified we build up only those flags
23497 actually used. Perhaps we should separate out the specified
23498 and implicit cases. Avoid taking this path for -march=all by
23499 checking for contradictory v7-A / v7-M features. */
23501 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23502 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23503 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23506 /* Tag_CPU_name. */
23507 if (selected_cpu_name
[0])
23511 q
= selected_cpu_name
;
23512 if (strncmp (q
, "armv", 4) == 0)
23517 for (i
= 0; q
[i
]; i
++)
23518 q
[i
] = TOUPPER (q
[i
]);
23520 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23523 /* Tag_CPU_arch. */
23524 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23526 /* Tag_CPU_arch_profile. */
23527 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23528 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23529 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23530 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23531 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23532 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23534 /* Tag_ARM_ISA_use. */
23535 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23537 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23539 /* Tag_THUMB_ISA_use. */
23540 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23542 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23543 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23545 /* Tag_VFP_arch. */
23546 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23547 aeabi_set_attribute_int (Tag_VFP_arch
,
23548 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23550 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23551 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23552 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23553 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23554 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23555 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23556 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23557 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23558 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23560 /* Tag_ABI_HardFP_use. */
23561 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23562 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23563 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23565 /* Tag_WMMX_arch. */
23566 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23567 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23568 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23569 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23571 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23572 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23573 aeabi_set_attribute_int
23574 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23577 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23578 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23579 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23582 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23583 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23584 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23585 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23587 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23589 /* Tag_MP_extension_use. */
23590 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23591 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23593 /* Tag Virtualization_use. */
23594 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23596 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23599 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23602 /* Add the default contents for the .ARM.attributes section. */
23606 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23609 aeabi_set_public_attributes ();
23611 #endif /* OBJ_ELF */
23614 /* Parse a .cpu directive. */
23617 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23619 const struct arm_cpu_option_table
*opt
;
23623 name
= input_line_pointer
;
23624 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23625 input_line_pointer
++;
23626 saved_char
= *input_line_pointer
;
23627 *input_line_pointer
= 0;
23629 /* Skip the first "all" entry. */
23630 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23631 if (streq (opt
->name
, name
))
23633 mcpu_cpu_opt
= &opt
->value
;
23634 selected_cpu
= opt
->value
;
23635 if (opt
->canonical_name
)
23636 strcpy (selected_cpu_name
, opt
->canonical_name
);
23640 for (i
= 0; opt
->name
[i
]; i
++)
23641 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23642 selected_cpu_name
[i
] = 0;
23644 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23645 *input_line_pointer
= saved_char
;
23646 demand_empty_rest_of_line ();
23649 as_bad (_("unknown cpu `%s'"), name
);
23650 *input_line_pointer
= saved_char
;
23651 ignore_rest_of_line ();
23655 /* Parse a .arch directive. */
23658 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23660 const struct arm_arch_option_table
*opt
;
23664 name
= input_line_pointer
;
23665 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23666 input_line_pointer
++;
23667 saved_char
= *input_line_pointer
;
23668 *input_line_pointer
= 0;
23670 /* Skip the first "all" entry. */
23671 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23672 if (streq (opt
->name
, name
))
23674 mcpu_cpu_opt
= &opt
->value
;
23675 selected_cpu
= opt
->value
;
23676 strcpy (selected_cpu_name
, opt
->name
);
23677 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23678 *input_line_pointer
= saved_char
;
23679 demand_empty_rest_of_line ();
23683 as_bad (_("unknown architecture `%s'\n"), name
);
23684 *input_line_pointer
= saved_char
;
23685 ignore_rest_of_line ();
23689 /* Parse a .object_arch directive. */
23692 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23694 const struct arm_arch_option_table
*opt
;
23698 name
= input_line_pointer
;
23699 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23700 input_line_pointer
++;
23701 saved_char
= *input_line_pointer
;
23702 *input_line_pointer
= 0;
23704 /* Skip the first "all" entry. */
23705 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23706 if (streq (opt
->name
, name
))
23708 object_arch
= &opt
->value
;
23709 *input_line_pointer
= saved_char
;
23710 demand_empty_rest_of_line ();
23714 as_bad (_("unknown architecture `%s'\n"), name
);
23715 *input_line_pointer
= saved_char
;
23716 ignore_rest_of_line ();
23719 /* Parse a .arch_extension directive. */
23722 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23724 const struct arm_option_extension_value_table
*opt
;
23727 int adding_value
= 1;
23729 name
= input_line_pointer
;
23730 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23731 input_line_pointer
++;
23732 saved_char
= *input_line_pointer
;
23733 *input_line_pointer
= 0;
23735 if (strlen (name
) >= 2
23736 && strncmp (name
, "no", 2) == 0)
23742 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23743 if (streq (opt
->name
, name
))
23745 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23747 as_bad (_("architectural extension `%s' is not allowed for the "
23748 "current base architecture"), name
);
23753 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23755 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23757 mcpu_cpu_opt
= &selected_cpu
;
23758 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23759 *input_line_pointer
= saved_char
;
23760 demand_empty_rest_of_line ();
23764 if (opt
->name
== NULL
)
23765 as_bad (_("unknown architecture `%s'\n"), name
);
23767 *input_line_pointer
= saved_char
;
23768 ignore_rest_of_line ();
23771 /* Parse a .fpu directive. */
23774 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23776 const struct arm_option_fpu_value_table
*opt
;
23780 name
= input_line_pointer
;
23781 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23782 input_line_pointer
++;
23783 saved_char
= *input_line_pointer
;
23784 *input_line_pointer
= 0;
23786 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23787 if (streq (opt
->name
, name
))
23789 mfpu_opt
= &opt
->value
;
23790 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23791 *input_line_pointer
= saved_char
;
23792 demand_empty_rest_of_line ();
23796 as_bad (_("unknown floating point format `%s'\n"), name
);
23797 *input_line_pointer
= saved_char
;
23798 ignore_rest_of_line ();
23801 /* Copy symbol information. */
23804 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23806 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23810 /* Given a symbolic attribute NAME, return the proper integer value.
23811 Returns -1 if the attribute is not known. */
23814 arm_convert_symbolic_attribute (const char *name
)
23816 static const struct
23821 attribute_table
[] =
23823 /* When you modify this table you should
23824 also modify the list in doc/c-arm.texi. */
23825 #define T(tag) {#tag, tag}
23826 T (Tag_CPU_raw_name
),
23829 T (Tag_CPU_arch_profile
),
23830 T (Tag_ARM_ISA_use
),
23831 T (Tag_THUMB_ISA_use
),
23835 T (Tag_Advanced_SIMD_arch
),
23836 T (Tag_PCS_config
),
23837 T (Tag_ABI_PCS_R9_use
),
23838 T (Tag_ABI_PCS_RW_data
),
23839 T (Tag_ABI_PCS_RO_data
),
23840 T (Tag_ABI_PCS_GOT_use
),
23841 T (Tag_ABI_PCS_wchar_t
),
23842 T (Tag_ABI_FP_rounding
),
23843 T (Tag_ABI_FP_denormal
),
23844 T (Tag_ABI_FP_exceptions
),
23845 T (Tag_ABI_FP_user_exceptions
),
23846 T (Tag_ABI_FP_number_model
),
23847 T (Tag_ABI_align_needed
),
23848 T (Tag_ABI_align8_needed
),
23849 T (Tag_ABI_align_preserved
),
23850 T (Tag_ABI_align8_preserved
),
23851 T (Tag_ABI_enum_size
),
23852 T (Tag_ABI_HardFP_use
),
23853 T (Tag_ABI_VFP_args
),
23854 T (Tag_ABI_WMMX_args
),
23855 T (Tag_ABI_optimization_goals
),
23856 T (Tag_ABI_FP_optimization_goals
),
23857 T (Tag_compatibility
),
23858 T (Tag_CPU_unaligned_access
),
23859 T (Tag_FP_HP_extension
),
23860 T (Tag_VFP_HP_extension
),
23861 T (Tag_ABI_FP_16bit_format
),
23862 T (Tag_MPextension_use
),
23864 T (Tag_nodefaults
),
23865 T (Tag_also_compatible_with
),
23866 T (Tag_conformance
),
23868 T (Tag_Virtualization_use
),
23869 /* We deliberately do not include Tag_MPextension_use_legacy. */
23877 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23878 if (streq (name
, attribute_table
[i
].name
))
23879 return attribute_table
[i
].tag
;
23885 /* Apply sym value for relocations only in the case that
23886 they are for local symbols and you have the respective
23887 architectural feature for blx and simple switches. */
23889 arm_apply_sym_value (struct fix
* fixP
)
23892 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23893 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
23895 switch (fixP
->fx_r_type
)
23897 case BFD_RELOC_ARM_PCREL_BLX
:
23898 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23899 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23903 case BFD_RELOC_ARM_PCREL_CALL
:
23904 case BFD_RELOC_THUMB_PCREL_BLX
:
23905 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23916 #endif /* OBJ_ELF */