1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[16];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 delim
= get_symbol_name (& name
);
2872 end_name
= input_line_pointer
;
2873 (void) restore_line_pointer (delim
);
2875 if (*input_line_pointer
!= ',')
2878 as_bad (_("expected comma after name \"%s\""), name
);
2880 ignore_rest_of_line ();
2884 input_line_pointer
++;
2887 if (name
[0] == '.' && name
[1] == '\0')
2889 /* XXX - this should not happen to .thumb_set. */
2893 if ((symbolP
= symbol_find (name
)) == NULL
2894 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2897 /* When doing symbol listings, play games with dummy fragments living
2898 outside the normal fragment chain to record the file and line info
2900 if (listing
& LISTING_SYMBOLS
)
2902 extern struct list_info_struct
* listing_tail
;
2903 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2905 memset (dummy_frag
, 0, sizeof (fragS
));
2906 dummy_frag
->fr_type
= rs_fill
;
2907 dummy_frag
->line
= listing_tail
;
2908 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2909 dummy_frag
->fr_symbol
= symbolP
;
2913 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2916 /* "set" symbols are local unless otherwise specified. */
2917 SF_SET_LOCAL (symbolP
);
2918 #endif /* OBJ_COFF */
2919 } /* Make a new symbol. */
2921 symbol_table_insert (symbolP
);
2926 && S_IS_DEFINED (symbolP
)
2927 && S_GET_SEGMENT (symbolP
) != reg_section
)
2928 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2930 pseudo_set (symbolP
);
2932 demand_empty_rest_of_line ();
2934 /* XXX Now we come to the Thumb specific bit of code. */
2936 THUMB_SET_FUNC (symbolP
, 1);
2937 ARM_SET_THUMB (symbolP
, 1);
2938 #if defined OBJ_ELF || defined OBJ_COFF
2939 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2943 /* Directives: Mode selection. */
2945 /* .syntax [unified|divided] - choose the new unified syntax
2946 (same for Arm and Thumb encoding, modulo slight differences in what
2947 can be represented) or the old divergent syntax for each mode. */
2949 s_syntax (int unused ATTRIBUTE_UNUSED
)
2953 delim
= get_symbol_name (& name
);
2955 if (!strcasecmp (name
, "unified"))
2956 unified_syntax
= TRUE
;
2957 else if (!strcasecmp (name
, "divided"))
2958 unified_syntax
= FALSE
;
2961 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2964 (void) restore_line_pointer (delim
);
2965 demand_empty_rest_of_line ();
2968 /* Directives: sectioning and alignment. */
2971 s_bss (int ignore ATTRIBUTE_UNUSED
)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section
, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED
)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg
, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: CodeComposer Studio. */
2997 /* .ref (for CodeComposer Studio syntax only). */
2999 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3001 if (codecomposer_syntax
)
3002 ignore_rest_of_line ();
3004 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3007 /* If name is not NULL, then it is used for marking the beginning of a
3008 function, wherease if it is NULL then it means the function end. */
3010 asmfunc_debug (const char * name
)
3012 static const char * last_name
= NULL
;
3016 gas_assert (last_name
== NULL
);
3019 if (debug_type
== DEBUG_STABS
)
3020 stabs_generate_asm_func (name
, name
);
3024 gas_assert (last_name
!= NULL
);
3026 if (debug_type
== DEBUG_STABS
)
3027 stabs_generate_asm_endfunc (last_name
, last_name
);
3034 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3036 if (codecomposer_syntax
)
3038 switch (asmfunc_state
)
3040 case OUTSIDE_ASMFUNC
:
3041 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3044 case WAITING_ASMFUNC_NAME
:
3045 as_bad (_(".asmfunc repeated."));
3048 case WAITING_ENDASMFUNC
:
3049 as_bad (_(".asmfunc without function."));
3052 demand_empty_rest_of_line ();
3055 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3059 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3061 if (codecomposer_syntax
)
3063 switch (asmfunc_state
)
3065 case OUTSIDE_ASMFUNC
:
3066 as_bad (_(".endasmfunc without a .asmfunc."));
3069 case WAITING_ASMFUNC_NAME
:
3070 as_bad (_(".endasmfunc without function."));
3073 case WAITING_ENDASMFUNC
:
3074 asmfunc_state
= OUTSIDE_ASMFUNC
;
3075 asmfunc_debug (NULL
);
3078 demand_empty_rest_of_line ();
3081 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3085 s_ccs_def (int name
)
3087 if (codecomposer_syntax
)
3090 as_bad (_(".def pseudo-op only available with -mccs flag."));
3093 /* Directives: Literal pools. */
3095 static literal_pool
*
3096 find_literal_pool (void)
3098 literal_pool
* pool
;
3100 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3102 if (pool
->section
== now_seg
3103 && pool
->sub_section
== now_subseg
)
3110 static literal_pool
*
3111 find_or_make_literal_pool (void)
3113 /* Next literal pool ID number. */
3114 static unsigned int latest_pool_num
= 1;
3115 literal_pool
* pool
;
3117 pool
= find_literal_pool ();
3121 /* Create a new pool. */
3122 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3126 pool
->next_free_entry
= 0;
3127 pool
->section
= now_seg
;
3128 pool
->sub_section
= now_subseg
;
3129 pool
->next
= list_of_pools
;
3130 pool
->symbol
= NULL
;
3131 pool
->alignment
= 2;
3133 /* Add it to the list. */
3134 list_of_pools
= pool
;
3137 /* New pools, and emptied pools, will have a NULL symbol. */
3138 if (pool
->symbol
== NULL
)
3140 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3141 (valueT
) 0, &zero_address_frag
);
3142 pool
->id
= latest_pool_num
++;
3149 /* Add the literal in the global 'inst'
3150 structure to the relevant literal pool. */
3153 add_to_lit_pool (unsigned int nbytes
)
3155 #define PADDING_SLOT 0x1
3156 #define LIT_ENTRY_SIZE_MASK 0xFF
3157 literal_pool
* pool
;
3158 unsigned int entry
, pool_size
= 0;
3159 bfd_boolean padding_slot_p
= FALSE
;
3165 imm1
= inst
.operands
[1].imm
;
3166 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3167 : inst
.reloc
.exp
.X_unsigned
? 0
3168 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3169 if (target_big_endian
)
3172 imm2
= inst
.operands
[1].imm
;
3176 pool
= find_or_make_literal_pool ();
3178 /* Check if this literal value is already in the pool. */
3179 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3183 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3184 && (inst
.reloc
.exp
.X_op
== O_constant
)
3185 && (pool
->literals
[entry
].X_add_number
3186 == inst
.reloc
.exp
.X_add_number
)
3187 && (pool
->literals
[entry
].X_md
== nbytes
)
3188 && (pool
->literals
[entry
].X_unsigned
3189 == inst
.reloc
.exp
.X_unsigned
))
3192 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3193 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3194 && (pool
->literals
[entry
].X_add_number
3195 == inst
.reloc
.exp
.X_add_number
)
3196 && (pool
->literals
[entry
].X_add_symbol
3197 == inst
.reloc
.exp
.X_add_symbol
)
3198 && (pool
->literals
[entry
].X_op_symbol
3199 == inst
.reloc
.exp
.X_op_symbol
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
))
3203 else if ((nbytes
== 8)
3204 && !(pool_size
& 0x7)
3205 && ((entry
+ 1) != pool
->next_free_entry
)
3206 && (pool
->literals
[entry
].X_op
== O_constant
)
3207 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3208 && (pool
->literals
[entry
].X_unsigned
3209 == inst
.reloc
.exp
.X_unsigned
)
3210 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3211 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3212 && (pool
->literals
[entry
+ 1].X_unsigned
3213 == inst
.reloc
.exp
.X_unsigned
))
3216 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3217 if (padding_slot_p
&& (nbytes
== 4))
3223 /* Do we need to create a new entry? */
3224 if (entry
== pool
->next_free_entry
)
3226 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3228 inst
.error
= _("literal pool overflow");
3234 /* For 8-byte entries, we align to an 8-byte boundary,
3235 and split it into two 4-byte entries, because on 32-bit
3236 host, 8-byte constants are treated as big num, thus
3237 saved in "generic_bignum" which will be overwritten
3238 by later assignments.
3240 We also need to make sure there is enough space for
3243 We also check to make sure the literal operand is a
3245 if (!(inst
.reloc
.exp
.X_op
== O_constant
3246 || inst
.reloc
.exp
.X_op
== O_big
))
3248 inst
.error
= _("invalid type for literal pool");
3251 else if (pool_size
& 0x7)
3253 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3255 inst
.error
= _("literal pool overflow");
3259 pool
->literals
[entry
] = inst
.reloc
.exp
;
3260 pool
->literals
[entry
].X_add_number
= 0;
3261 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3262 pool
->next_free_entry
+= 1;
3265 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3267 inst
.error
= _("literal pool overflow");
3271 pool
->literals
[entry
] = inst
.reloc
.exp
;
3272 pool
->literals
[entry
].X_op
= O_constant
;
3273 pool
->literals
[entry
].X_add_number
= imm1
;
3274 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3275 pool
->literals
[entry
++].X_md
= 4;
3276 pool
->literals
[entry
] = inst
.reloc
.exp
;
3277 pool
->literals
[entry
].X_op
= O_constant
;
3278 pool
->literals
[entry
].X_add_number
= imm2
;
3279 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3280 pool
->literals
[entry
].X_md
= 4;
3281 pool
->alignment
= 3;
3282 pool
->next_free_entry
+= 1;
3286 pool
->literals
[entry
] = inst
.reloc
.exp
;
3287 pool
->literals
[entry
].X_md
= 4;
3291 /* PR ld/12974: Record the location of the first source line to reference
3292 this entry in the literal pool. If it turns out during linking that the
3293 symbol does not exist we will be able to give an accurate line number for
3294 the (first use of the) missing reference. */
3295 if (debug_type
== DEBUG_DWARF2
)
3296 dwarf2_where (pool
->locs
+ entry
);
3298 pool
->next_free_entry
+= 1;
3300 else if (padding_slot_p
)
3302 pool
->literals
[entry
] = inst
.reloc
.exp
;
3303 pool
->literals
[entry
].X_md
= nbytes
;
3306 inst
.reloc
.exp
.X_op
= O_symbol
;
3307 inst
.reloc
.exp
.X_add_number
= pool_size
;
3308 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3314 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3316 bfd_boolean ret
= TRUE
;
3318 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3320 const char *label
= rest
;
3322 while (!is_end_of_line
[(int) label
[-1]])
3327 as_bad (_("Invalid label '%s'"), label
);
3331 asmfunc_debug (label
);
3333 asmfunc_state
= WAITING_ENDASMFUNC
;
3339 /* Can't use symbol_new here, so have to create a symbol and then at
3340 a later date assign it a value. Thats what these functions do. */
3343 symbol_locate (symbolS
* symbolP
,
3344 const char * name
, /* It is copied, the caller can modify. */
3345 segT segment
, /* Segment identifier (SEG_<something>). */
3346 valueT valu
, /* Symbol value. */
3347 fragS
* frag
) /* Associated fragment. */
3350 char * preserved_copy_of_name
;
3352 name_length
= strlen (name
) + 1; /* +1 for \0. */
3353 obstack_grow (¬es
, name
, name_length
);
3354 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3356 #ifdef tc_canonicalize_symbol_name
3357 preserved_copy_of_name
=
3358 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3361 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3363 S_SET_SEGMENT (symbolP
, segment
);
3364 S_SET_VALUE (symbolP
, valu
);
3365 symbol_clear_list_pointers (symbolP
);
3367 symbol_set_frag (symbolP
, frag
);
3369 /* Link to end of symbol chain. */
3371 extern int symbol_table_frozen
;
3373 if (symbol_table_frozen
)
3377 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3379 obj_symbol_new_hook (symbolP
);
3381 #ifdef tc_symbol_new_hook
3382 tc_symbol_new_hook (symbolP
);
3386 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3387 #endif /* DEBUG_SYMS */
3391 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3394 literal_pool
* pool
;
3397 pool
= find_literal_pool ();
3399 || pool
->symbol
== NULL
3400 || pool
->next_free_entry
== 0)
3403 /* Align pool as you have word accesses.
3404 Only make a frag if we have to. */
3406 frag_align (pool
->alignment
, 0, 0);
3408 record_alignment (now_seg
, 2);
3411 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3412 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3414 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3416 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3417 (valueT
) frag_now_fix (), frag_now
);
3418 symbol_table_insert (pool
->symbol
);
3420 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3422 #if defined OBJ_COFF || defined OBJ_ELF
3423 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3426 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3429 if (debug_type
== DEBUG_DWARF2
)
3430 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3432 /* First output the expression in the instruction to the pool. */
3433 emit_expr (&(pool
->literals
[entry
]),
3434 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3437 /* Mark the pool as empty. */
3438 pool
->next_free_entry
= 0;
3439 pool
->symbol
= NULL
;
3443 /* Forward declarations for functions below, in the MD interface
3445 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3446 static valueT
create_unwind_entry (int);
3447 static void start_unwind_section (const segT
, int);
3448 static void add_unwind_opcode (valueT
, int);
3449 static void flush_pending_unwind (void);
3451 /* Directives: Data. */
3454 s_arm_elf_cons (int nbytes
)
3458 #ifdef md_flush_pending_output
3459 md_flush_pending_output ();
3462 if (is_it_end_of_statement ())
3464 demand_empty_rest_of_line ();
3468 #ifdef md_cons_align
3469 md_cons_align (nbytes
);
3472 mapping_state (MAP_DATA
);
3476 char *base
= input_line_pointer
;
3480 if (exp
.X_op
!= O_symbol
)
3481 emit_expr (&exp
, (unsigned int) nbytes
);
3484 char *before_reloc
= input_line_pointer
;
3485 reloc
= parse_reloc (&input_line_pointer
);
3488 as_bad (_("unrecognized relocation suffix"));
3489 ignore_rest_of_line ();
3492 else if (reloc
== BFD_RELOC_UNUSED
)
3493 emit_expr (&exp
, (unsigned int) nbytes
);
3496 reloc_howto_type
*howto
= (reloc_howto_type
*)
3497 bfd_reloc_type_lookup (stdoutput
,
3498 (bfd_reloc_code_real_type
) reloc
);
3499 int size
= bfd_get_reloc_size (howto
);
3501 if (reloc
== BFD_RELOC_ARM_PLT32
)
3503 as_bad (_("(plt) is only valid on branch targets"));
3504 reloc
= BFD_RELOC_UNUSED
;
3509 as_bad (_("%s relocations do not fit in %d bytes"),
3510 howto
->name
, nbytes
);
3513 /* We've parsed an expression stopping at O_symbol.
3514 But there may be more expression left now that we
3515 have parsed the relocation marker. Parse it again.
3516 XXX Surely there is a cleaner way to do this. */
3517 char *p
= input_line_pointer
;
3519 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3520 memcpy (save_buf
, base
, input_line_pointer
- base
);
3521 memmove (base
+ (input_line_pointer
- before_reloc
),
3522 base
, before_reloc
- base
);
3524 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3526 memcpy (base
, save_buf
, p
- base
);
3528 offset
= nbytes
- size
;
3529 p
= frag_more (nbytes
);
3530 memset (p
, 0, nbytes
);
3531 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3532 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3537 while (*input_line_pointer
++ == ',');
3539 /* Put terminator back into stream. */
3540 input_line_pointer
--;
3541 demand_empty_rest_of_line ();
3544 /* Emit an expression containing a 32-bit thumb instruction.
3545 Implementation based on put_thumb32_insn. */
3548 emit_thumb32_expr (expressionS
* exp
)
3550 expressionS exp_high
= *exp
;
3552 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3553 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3554 exp
->X_add_number
&= 0xffff;
3555 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3558 /* Guess the instruction size based on the opcode. */
3561 thumb_insn_size (int opcode
)
3563 if ((unsigned int) opcode
< 0xe800u
)
3565 else if ((unsigned int) opcode
>= 0xe8000000u
)
3572 emit_insn (expressionS
*exp
, int nbytes
)
3576 if (exp
->X_op
== O_constant
)
3581 size
= thumb_insn_size (exp
->X_add_number
);
3585 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3587 as_bad (_(".inst.n operand too big. "\
3588 "Use .inst.w instead"));
3593 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3594 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3596 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3598 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3599 emit_thumb32_expr (exp
);
3601 emit_expr (exp
, (unsigned int) size
);
3603 it_fsm_post_encode ();
3607 as_bad (_("cannot determine Thumb instruction size. " \
3608 "Use .inst.n/.inst.w instead"));
3611 as_bad (_("constant expression required"));
3616 /* Like s_arm_elf_cons but do not use md_cons_align and
3617 set the mapping state to MAP_ARM/MAP_THUMB. */
3620 s_arm_elf_inst (int nbytes
)
3622 if (is_it_end_of_statement ())
3624 demand_empty_rest_of_line ();
3628 /* Calling mapping_state () here will not change ARM/THUMB,
3629 but will ensure not to be in DATA state. */
3632 mapping_state (MAP_THUMB
);
3637 as_bad (_("width suffixes are invalid in ARM mode"));
3638 ignore_rest_of_line ();
3644 mapping_state (MAP_ARM
);
3653 if (! emit_insn (& exp
, nbytes
))
3655 ignore_rest_of_line ();
3659 while (*input_line_pointer
++ == ',');
3661 /* Put terminator back into stream. */
3662 input_line_pointer
--;
3663 demand_empty_rest_of_line ();
3666 /* Parse a .rel31 directive. */
3669 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3676 if (*input_line_pointer
== '1')
3677 highbit
= 0x80000000;
3678 else if (*input_line_pointer
!= '0')
3679 as_bad (_("expected 0 or 1"));
3681 input_line_pointer
++;
3682 if (*input_line_pointer
!= ',')
3683 as_bad (_("missing comma"));
3684 input_line_pointer
++;
3686 #ifdef md_flush_pending_output
3687 md_flush_pending_output ();
3690 #ifdef md_cons_align
3694 mapping_state (MAP_DATA
);
3699 md_number_to_chars (p
, highbit
, 4);
3700 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3701 BFD_RELOC_ARM_PREL31
);
3703 demand_empty_rest_of_line ();
3706 /* Directives: AEABI stack-unwind tables. */
3708 /* Parse an unwind_fnstart directive. Simply records the current location. */
3711 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3713 demand_empty_rest_of_line ();
3714 if (unwind
.proc_start
)
3716 as_bad (_("duplicate .fnstart directive"));
3720 /* Mark the start of the function. */
3721 unwind
.proc_start
= expr_build_dot ();
3723 /* Reset the rest of the unwind info. */
3724 unwind
.opcode_count
= 0;
3725 unwind
.table_entry
= NULL
;
3726 unwind
.personality_routine
= NULL
;
3727 unwind
.personality_index
= -1;
3728 unwind
.frame_size
= 0;
3729 unwind
.fp_offset
= 0;
3730 unwind
.fp_reg
= REG_SP
;
3732 unwind
.sp_restored
= 0;
3736 /* Parse a handlerdata directive. Creates the exception handling table entry
3737 for the function. */
3740 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3742 demand_empty_rest_of_line ();
3743 if (!unwind
.proc_start
)
3744 as_bad (MISSING_FNSTART
);
3746 if (unwind
.table_entry
)
3747 as_bad (_("duplicate .handlerdata directive"));
3749 create_unwind_entry (1);
3752 /* Parse an unwind_fnend directive. Generates the index table entry. */
3755 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3760 unsigned int marked_pr_dependency
;
3762 demand_empty_rest_of_line ();
3764 if (!unwind
.proc_start
)
3766 as_bad (_(".fnend directive without .fnstart"));
3770 /* Add eh table entry. */
3771 if (unwind
.table_entry
== NULL
)
3772 val
= create_unwind_entry (0);
3776 /* Add index table entry. This is two words. */
3777 start_unwind_section (unwind
.saved_seg
, 1);
3778 frag_align (2, 0, 0);
3779 record_alignment (now_seg
, 2);
3781 ptr
= frag_more (8);
3783 where
= frag_now_fix () - 8;
3785 /* Self relative offset of the function start. */
3786 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3787 BFD_RELOC_ARM_PREL31
);
3789 /* Indicate dependency on EHABI-defined personality routines to the
3790 linker, if it hasn't been done already. */
3791 marked_pr_dependency
3792 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3793 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3794 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3796 static const char *const name
[] =
3798 "__aeabi_unwind_cpp_pr0",
3799 "__aeabi_unwind_cpp_pr1",
3800 "__aeabi_unwind_cpp_pr2"
3802 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3803 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3804 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3805 |= 1 << unwind
.personality_index
;
3809 /* Inline exception table entry. */
3810 md_number_to_chars (ptr
+ 4, val
, 4);
3812 /* Self relative offset of the table entry. */
3813 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3814 BFD_RELOC_ARM_PREL31
);
3816 /* Restore the original section. */
3817 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3819 unwind
.proc_start
= NULL
;
3823 /* Parse an unwind_cantunwind directive. */
3826 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3828 demand_empty_rest_of_line ();
3829 if (!unwind
.proc_start
)
3830 as_bad (MISSING_FNSTART
);
3832 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3833 as_bad (_("personality routine specified for cantunwind frame"));
3835 unwind
.personality_index
= -2;
3839 /* Parse a personalityindex directive. */
3842 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3846 if (!unwind
.proc_start
)
3847 as_bad (MISSING_FNSTART
);
3849 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3850 as_bad (_("duplicate .personalityindex directive"));
3854 if (exp
.X_op
!= O_constant
3855 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3857 as_bad (_("bad personality routine number"));
3858 ignore_rest_of_line ();
3862 unwind
.personality_index
= exp
.X_add_number
;
3864 demand_empty_rest_of_line ();
3868 /* Parse a personality directive. */
3871 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3875 if (!unwind
.proc_start
)
3876 as_bad (MISSING_FNSTART
);
3878 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3879 as_bad (_("duplicate .personality directive"));
3881 c
= get_symbol_name (& name
);
3882 p
= input_line_pointer
;
3884 ++ input_line_pointer
;
3885 unwind
.personality_routine
= symbol_find_or_make (name
);
3887 demand_empty_rest_of_line ();
3891 /* Parse a directive saving core registers. */
3894 s_arm_unwind_save_core (void)
3900 range
= parse_reg_list (&input_line_pointer
);
3903 as_bad (_("expected register list"));
3904 ignore_rest_of_line ();
3908 demand_empty_rest_of_line ();
3910 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3911 into .unwind_save {..., sp...}. We aren't bothered about the value of
3912 ip because it is clobbered by calls. */
3913 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3914 && (range
& 0x3000) == 0x1000)
3916 unwind
.opcode_count
--;
3917 unwind
.sp_restored
= 0;
3918 range
= (range
| 0x2000) & ~0x1000;
3919 unwind
.pending_offset
= 0;
3925 /* See if we can use the short opcodes. These pop a block of up to 8
3926 registers starting with r4, plus maybe r14. */
3927 for (n
= 0; n
< 8; n
++)
3929 /* Break at the first non-saved register. */
3930 if ((range
& (1 << (n
+ 4))) == 0)
3933 /* See if there are any other bits set. */
3934 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3936 /* Use the long form. */
3937 op
= 0x8000 | ((range
>> 4) & 0xfff);
3938 add_unwind_opcode (op
, 2);
3942 /* Use the short form. */
3944 op
= 0xa8; /* Pop r14. */
3946 op
= 0xa0; /* Do not pop r14. */
3948 add_unwind_opcode (op
, 1);
3955 op
= 0xb100 | (range
& 0xf);
3956 add_unwind_opcode (op
, 2);
3959 /* Record the number of bytes pushed. */
3960 for (n
= 0; n
< 16; n
++)
3962 if (range
& (1 << n
))
3963 unwind
.frame_size
+= 4;
3968 /* Parse a directive saving FPA registers. */
3971 s_arm_unwind_save_fpa (int reg
)
3977 /* Get Number of registers to transfer. */
3978 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3981 exp
.X_op
= O_illegal
;
3983 if (exp
.X_op
!= O_constant
)
3985 as_bad (_("expected , <constant>"));
3986 ignore_rest_of_line ();
3990 num_regs
= exp
.X_add_number
;
3992 if (num_regs
< 1 || num_regs
> 4)
3994 as_bad (_("number of registers must be in the range [1:4]"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4004 op
= 0xb4 | (num_regs
- 1);
4005 add_unwind_opcode (op
, 1);
4010 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4011 add_unwind_opcode (op
, 2);
4013 unwind
.frame_size
+= num_regs
* 12;
4017 /* Parse a directive saving VFP registers for ARMv6 and above. */
4020 s_arm_unwind_save_vfp_armv6 (void)
4025 int num_vfpv3_regs
= 0;
4026 int num_regs_below_16
;
4028 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4031 as_bad (_("expected register list"));
4032 ignore_rest_of_line ();
4036 demand_empty_rest_of_line ();
4038 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4039 than FSTMX/FLDMX-style ones). */
4041 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4043 num_vfpv3_regs
= count
;
4044 else if (start
+ count
> 16)
4045 num_vfpv3_regs
= start
+ count
- 16;
4047 if (num_vfpv3_regs
> 0)
4049 int start_offset
= start
> 16 ? start
- 16 : 0;
4050 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4051 add_unwind_opcode (op
, 2);
4054 /* Generate opcode for registers numbered in the range 0 .. 15. */
4055 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4056 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4057 if (num_regs_below_16
> 0)
4059 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4060 add_unwind_opcode (op
, 2);
4063 unwind
.frame_size
+= count
* 8;
4067 /* Parse a directive saving VFP registers for pre-ARMv6. */
4070 s_arm_unwind_save_vfp (void)
4076 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4089 op
= 0xb8 | (count
- 1);
4090 add_unwind_opcode (op
, 1);
4095 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4096 add_unwind_opcode (op
, 2);
4098 unwind
.frame_size
+= count
* 8 + 4;
4102 /* Parse a directive saving iWMMXt data registers. */
4105 s_arm_unwind_save_mmxwr (void)
4113 if (*input_line_pointer
== '{')
4114 input_line_pointer
++;
4118 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4122 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4127 as_tsktsk (_("register list not in ascending order"));
4130 if (*input_line_pointer
== '-')
4132 input_line_pointer
++;
4133 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4136 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4139 else if (reg
>= hi_reg
)
4141 as_bad (_("bad register range"));
4144 for (; reg
< hi_reg
; reg
++)
4148 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4150 skip_past_char (&input_line_pointer
, '}');
4152 demand_empty_rest_of_line ();
4154 /* Generate any deferred opcodes because we're going to be looking at
4156 flush_pending_unwind ();
4158 for (i
= 0; i
< 16; i
++)
4160 if (mask
& (1 << i
))
4161 unwind
.frame_size
+= 8;
4164 /* Attempt to combine with a previous opcode. We do this because gcc
4165 likes to output separate unwind directives for a single block of
4167 if (unwind
.opcode_count
> 0)
4169 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4170 if ((i
& 0xf8) == 0xc0)
4173 /* Only merge if the blocks are contiguous. */
4176 if ((mask
& 0xfe00) == (1 << 9))
4178 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4179 unwind
.opcode_count
--;
4182 else if (i
== 6 && unwind
.opcode_count
>= 2)
4184 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4188 op
= 0xffff << (reg
- 1);
4190 && ((mask
& op
) == (1u << (reg
- 1))))
4192 op
= (1 << (reg
+ i
+ 1)) - 1;
4193 op
&= ~((1 << reg
) - 1);
4195 unwind
.opcode_count
-= 2;
4202 /* We want to generate opcodes in the order the registers have been
4203 saved, ie. descending order. */
4204 for (reg
= 15; reg
>= -1; reg
--)
4206 /* Save registers in blocks. */
4208 || !(mask
& (1 << reg
)))
4210 /* We found an unsaved reg. Generate opcodes to save the
4217 op
= 0xc0 | (hi_reg
- 10);
4218 add_unwind_opcode (op
, 1);
4223 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4224 add_unwind_opcode (op
, 2);
4233 ignore_rest_of_line ();
4237 s_arm_unwind_save_mmxwcg (void)
4244 if (*input_line_pointer
== '{')
4245 input_line_pointer
++;
4247 skip_whitespace (input_line_pointer
);
4251 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4255 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4261 as_tsktsk (_("register list not in ascending order"));
4264 if (*input_line_pointer
== '-')
4266 input_line_pointer
++;
4267 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4270 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4273 else if (reg
>= hi_reg
)
4275 as_bad (_("bad register range"));
4278 for (; reg
< hi_reg
; reg
++)
4282 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4284 skip_past_char (&input_line_pointer
, '}');
4286 demand_empty_rest_of_line ();
4288 /* Generate any deferred opcodes because we're going to be looking at
4290 flush_pending_unwind ();
4292 for (reg
= 0; reg
< 16; reg
++)
4294 if (mask
& (1 << reg
))
4295 unwind
.frame_size
+= 4;
4298 add_unwind_opcode (op
, 2);
4301 ignore_rest_of_line ();
4305 /* Parse an unwind_save directive.
4306 If the argument is non-zero, this is a .vsave directive. */
4309 s_arm_unwind_save (int arch_v6
)
4312 struct reg_entry
*reg
;
4313 bfd_boolean had_brace
= FALSE
;
4315 if (!unwind
.proc_start
)
4316 as_bad (MISSING_FNSTART
);
4318 /* Figure out what sort of save we have. */
4319 peek
= input_line_pointer
;
4327 reg
= arm_reg_parse_multi (&peek
);
4331 as_bad (_("register expected"));
4332 ignore_rest_of_line ();
4341 as_bad (_("FPA .unwind_save does not take a register list"));
4342 ignore_rest_of_line ();
4345 input_line_pointer
= peek
;
4346 s_arm_unwind_save_fpa (reg
->number
);
4350 s_arm_unwind_save_core ();
4355 s_arm_unwind_save_vfp_armv6 ();
4357 s_arm_unwind_save_vfp ();
4360 case REG_TYPE_MMXWR
:
4361 s_arm_unwind_save_mmxwr ();
4364 case REG_TYPE_MMXWCG
:
4365 s_arm_unwind_save_mmxwcg ();
4369 as_bad (_(".unwind_save does not support this kind of register"));
4370 ignore_rest_of_line ();
4375 /* Parse an unwind_movsp directive. */
4378 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4384 if (!unwind
.proc_start
)
4385 as_bad (MISSING_FNSTART
);
4387 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4390 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4391 ignore_rest_of_line ();
4395 /* Optional constant. */
4396 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4398 if (immediate_for_directive (&offset
) == FAIL
)
4404 demand_empty_rest_of_line ();
4406 if (reg
== REG_SP
|| reg
== REG_PC
)
4408 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4412 if (unwind
.fp_reg
!= REG_SP
)
4413 as_bad (_("unexpected .unwind_movsp directive"));
4415 /* Generate opcode to restore the value. */
4417 add_unwind_opcode (op
, 1);
4419 /* Record the information for later. */
4420 unwind
.fp_reg
= reg
;
4421 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4422 unwind
.sp_restored
= 1;
4425 /* Parse an unwind_pad directive. */
4428 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 if (immediate_for_directive (&offset
) == FAIL
)
4440 as_bad (_("stack increment must be multiple of 4"));
4441 ignore_rest_of_line ();
4445 /* Don't generate any opcodes, just record the details for later. */
4446 unwind
.frame_size
+= offset
;
4447 unwind
.pending_offset
+= offset
;
4449 demand_empty_rest_of_line ();
4452 /* Parse an unwind_setfp directive. */
4455 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4461 if (!unwind
.proc_start
)
4462 as_bad (MISSING_FNSTART
);
4464 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4465 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4468 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4472 as_bad (_("expected <reg>, <reg>"));
4473 ignore_rest_of_line ();
4477 /* Optional constant. */
4478 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4480 if (immediate_for_directive (&offset
) == FAIL
)
4486 demand_empty_rest_of_line ();
4488 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4490 as_bad (_("register must be either sp or set by a previous"
4491 "unwind_movsp directive"));
4495 /* Don't generate any opcodes, just record the information for later. */
4496 unwind
.fp_reg
= fp_reg
;
4498 if (sp_reg
== REG_SP
)
4499 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4501 unwind
.fp_offset
-= offset
;
4504 /* Parse an unwind_raw directive. */
4507 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4510 /* This is an arbitrary limit. */
4511 unsigned char op
[16];
4514 if (!unwind
.proc_start
)
4515 as_bad (MISSING_FNSTART
);
4518 if (exp
.X_op
== O_constant
4519 && skip_past_comma (&input_line_pointer
) != FAIL
)
4521 unwind
.frame_size
+= exp
.X_add_number
;
4525 exp
.X_op
= O_illegal
;
4527 if (exp
.X_op
!= O_constant
)
4529 as_bad (_("expected <offset>, <opcode>"));
4530 ignore_rest_of_line ();
4536 /* Parse the opcode. */
4541 as_bad (_("unwind opcode too long"));
4542 ignore_rest_of_line ();
4544 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4546 as_bad (_("invalid unwind opcode"));
4547 ignore_rest_of_line ();
4550 op
[count
++] = exp
.X_add_number
;
4552 /* Parse the next byte. */
4553 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 /* Add the opcode bytes in reverse order. */
4561 add_unwind_opcode (op
[count
], 1);
4563 demand_empty_rest_of_line ();
4567 /* Parse a .eabi_attribute directive. */
4570 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4572 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4574 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4575 attributes_set_explicitly
[tag
] = 1;
4578 /* Emit a tls fix for the symbol. */
4581 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4585 #ifdef md_flush_pending_output
4586 md_flush_pending_output ();
4589 #ifdef md_cons_align
4593 /* Since we're just labelling the code, there's no need to define a
4596 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4597 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4598 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4599 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4601 #endif /* OBJ_ELF */
4603 static void s_arm_arch (int);
4604 static void s_arm_object_arch (int);
4605 static void s_arm_cpu (int);
4606 static void s_arm_fpu (int);
4607 static void s_arm_arch_extension (int);
4612 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4619 if (exp
.X_op
== O_symbol
)
4620 exp
.X_op
= O_secrel
;
4622 emit_expr (&exp
, 4);
4624 while (*input_line_pointer
++ == ',');
4626 input_line_pointer
--;
4627 demand_empty_rest_of_line ();
4631 /* This table describes all the machine specific pseudo-ops the assembler
4632 has to support. The fields are:
4633 pseudo-op name without dot
4634 function to call to execute this pseudo-op
4635 Integer arg to pass to the function. */
4637 const pseudo_typeS md_pseudo_table
[] =
4639 /* Never called because '.req' does not start a line. */
4640 { "req", s_req
, 0 },
4641 /* Following two are likewise never called. */
4644 { "unreq", s_unreq
, 0 },
4645 { "bss", s_bss
, 0 },
4646 { "align", s_align_ptwo
, 2 },
4647 { "arm", s_arm
, 0 },
4648 { "thumb", s_thumb
, 0 },
4649 { "code", s_code
, 0 },
4650 { "force_thumb", s_force_thumb
, 0 },
4651 { "thumb_func", s_thumb_func
, 0 },
4652 { "thumb_set", s_thumb_set
, 0 },
4653 { "even", s_even
, 0 },
4654 { "ltorg", s_ltorg
, 0 },
4655 { "pool", s_ltorg
, 0 },
4656 { "syntax", s_syntax
, 0 },
4657 { "cpu", s_arm_cpu
, 0 },
4658 { "arch", s_arm_arch
, 0 },
4659 { "object_arch", s_arm_object_arch
, 0 },
4660 { "fpu", s_arm_fpu
, 0 },
4661 { "arch_extension", s_arm_arch_extension
, 0 },
4663 { "word", s_arm_elf_cons
, 4 },
4664 { "long", s_arm_elf_cons
, 4 },
4665 { "inst.n", s_arm_elf_inst
, 2 },
4666 { "inst.w", s_arm_elf_inst
, 4 },
4667 { "inst", s_arm_elf_inst
, 0 },
4668 { "rel31", s_arm_rel31
, 0 },
4669 { "fnstart", s_arm_unwind_fnstart
, 0 },
4670 { "fnend", s_arm_unwind_fnend
, 0 },
4671 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4672 { "personality", s_arm_unwind_personality
, 0 },
4673 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4674 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4675 { "save", s_arm_unwind_save
, 0 },
4676 { "vsave", s_arm_unwind_save
, 1 },
4677 { "movsp", s_arm_unwind_movsp
, 0 },
4678 { "pad", s_arm_unwind_pad
, 0 },
4679 { "setfp", s_arm_unwind_setfp
, 0 },
4680 { "unwind_raw", s_arm_unwind_raw
, 0 },
4681 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4682 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4686 /* These are used for dwarf. */
4690 /* These are used for dwarf2. */
4691 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4692 { "loc", dwarf2_directive_loc
, 0 },
4693 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4695 { "extend", float_cons
, 'x' },
4696 { "ldouble", float_cons
, 'x' },
4697 { "packed", float_cons
, 'p' },
4699 {"secrel32", pe_directive_secrel
, 0},
4702 /* These are for compatibility with CodeComposer Studio. */
4703 {"ref", s_ccs_ref
, 0},
4704 {"def", s_ccs_def
, 0},
4705 {"asmfunc", s_ccs_asmfunc
, 0},
4706 {"endasmfunc", s_ccs_endasmfunc
, 0},
4711 /* Parser functions used exclusively in instruction operands. */
4713 /* Generic immediate-value read function for use in insn parsing.
4714 STR points to the beginning of the immediate (the leading #);
4715 VAL receives the value; if the value is outside [MIN, MAX]
4716 issue an error. PREFIX_OPT is true if the immediate prefix is
4720 parse_immediate (char **str
, int *val
, int min
, int max
,
4721 bfd_boolean prefix_opt
)
4724 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4725 if (exp
.X_op
!= O_constant
)
4727 inst
.error
= _("constant expression required");
4731 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4733 inst
.error
= _("immediate value out of range");
4737 *val
= exp
.X_add_number
;
4741 /* Less-generic immediate-value read function with the possibility of loading a
4742 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4743 instructions. Puts the result directly in inst.operands[i]. */
4746 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4747 bfd_boolean allow_symbol_p
)
4750 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4753 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4755 if (exp_p
->X_op
== O_constant
)
4757 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4758 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4759 O_constant. We have to be careful not to break compilation for
4760 32-bit X_add_number, though. */
4761 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4763 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4764 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4766 inst
.operands
[i
].regisimm
= 1;
4769 else if (exp_p
->X_op
== O_big
4770 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4772 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4774 /* Bignums have their least significant bits in
4775 generic_bignum[0]. Make sure we put 32 bits in imm and
4776 32 bits in reg, in a (hopefully) portable way. */
4777 gas_assert (parts
!= 0);
4779 /* Make sure that the number is not too big.
4780 PR 11972: Bignums can now be sign-extended to the
4781 size of a .octa so check that the out of range bits
4782 are all zero or all one. */
4783 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4785 LITTLENUM_TYPE m
= -1;
4787 if (generic_bignum
[parts
* 2] != 0
4788 && generic_bignum
[parts
* 2] != m
)
4791 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4792 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4796 inst
.operands
[i
].imm
= 0;
4797 for (j
= 0; j
< parts
; j
++, idx
++)
4798 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4799 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4800 inst
.operands
[i
].reg
= 0;
4801 for (j
= 0; j
< parts
; j
++, idx
++)
4802 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4803 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4804 inst
.operands
[i
].regisimm
= 1;
4806 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4814 /* Returns the pseudo-register number of an FPA immediate constant,
4815 or FAIL if there isn't a valid constant here. */
4818 parse_fpa_immediate (char ** str
)
4820 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4826 /* First try and match exact strings, this is to guarantee
4827 that some formats will work even for cross assembly. */
4829 for (i
= 0; fp_const
[i
]; i
++)
4831 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4835 *str
+= strlen (fp_const
[i
]);
4836 if (is_end_of_line
[(unsigned char) **str
])
4842 /* Just because we didn't get a match doesn't mean that the constant
4843 isn't valid, just that it is in a format that we don't
4844 automatically recognize. Try parsing it with the standard
4845 expression routines. */
4847 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4849 /* Look for a raw floating point number. */
4850 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4851 && is_end_of_line
[(unsigned char) *save_in
])
4853 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4855 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4857 if (words
[j
] != fp_values
[i
][j
])
4861 if (j
== MAX_LITTLENUMS
)
4869 /* Try and parse a more complex expression, this will probably fail
4870 unless the code uses a floating point prefix (eg "0f"). */
4871 save_in
= input_line_pointer
;
4872 input_line_pointer
= *str
;
4873 if (expression (&exp
) == absolute_section
4874 && exp
.X_op
== O_big
4875 && exp
.X_add_number
< 0)
4877 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4879 #define X_PRECISION 5
4880 #define E_PRECISION 15L
4881 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4885 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4887 if (words
[j
] != fp_values
[i
][j
])
4891 if (j
== MAX_LITTLENUMS
)
4893 *str
= input_line_pointer
;
4894 input_line_pointer
= save_in
;
4901 *str
= input_line_pointer
;
4902 input_line_pointer
= save_in
;
4903 inst
.error
= _("invalid FPA immediate expression");
4907 /* Returns 1 if a number has "quarter-precision" float format
4908 0baBbbbbbc defgh000 00000000 00000000. */
4911 is_quarter_float (unsigned imm
)
4913 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4914 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4918 /* Detect the presence of a floating point or integer zero constant,
4922 parse_ifimm_zero (char **in
)
4926 if (!is_immediate_prefix (**in
))
4931 /* Accept #0x0 as a synonym for #0. */
4932 if (strncmp (*in
, "0x", 2) == 0)
4935 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4940 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4941 &generic_floating_point_number
);
4944 && generic_floating_point_number
.sign
== '+'
4945 && (generic_floating_point_number
.low
4946 > generic_floating_point_number
.leader
))
4952 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4953 0baBbbbbbc defgh000 00000000 00000000.
4954 The zero and minus-zero cases need special handling, since they can't be
4955 encoded in the "quarter-precision" float format, but can nonetheless be
4956 loaded as integer constants. */
4959 parse_qfloat_immediate (char **ccp
, int *immed
)
4963 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4964 int found_fpchar
= 0;
4966 skip_past_char (&str
, '#');
4968 /* We must not accidentally parse an integer as a floating-point number. Make
4969 sure that the value we parse is not an integer by checking for special
4970 characters '.' or 'e'.
4971 FIXME: This is a horrible hack, but doing better is tricky because type
4972 information isn't in a very usable state at parse time. */
4974 skip_whitespace (fpnum
);
4976 if (strncmp (fpnum
, "0x", 2) == 0)
4980 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4981 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4991 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4993 unsigned fpword
= 0;
4996 /* Our FP word must be 32 bits (single-precision FP). */
4997 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4999 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5003 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5016 /* Shift operands. */
5019 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5022 struct asm_shift_name
5025 enum shift_kind kind
;
5028 /* Third argument to parse_shift. */
5029 enum parse_shift_mode
5031 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5032 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5033 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5034 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5035 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5038 /* Parse a <shift> specifier on an ARM data processing instruction.
5039 This has three forms:
5041 (LSL|LSR|ASL|ASR|ROR) Rs
5042 (LSL|LSR|ASL|ASR|ROR) #imm
5045 Note that ASL is assimilated to LSL in the instruction encoding, and
5046 RRX to ROR #0 (which cannot be written as such). */
5049 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5051 const struct asm_shift_name
*shift_name
;
5052 enum shift_kind shift
;
5057 for (p
= *str
; ISALPHA (*p
); p
++)
5062 inst
.error
= _("shift expression expected");
5066 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5069 if (shift_name
== NULL
)
5071 inst
.error
= _("shift expression expected");
5075 shift
= shift_name
->kind
;
5079 case NO_SHIFT_RESTRICT
:
5080 case SHIFT_IMMEDIATE
: break;
5082 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5083 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5085 inst
.error
= _("'LSL' or 'ASR' required");
5090 case SHIFT_LSL_IMMEDIATE
:
5091 if (shift
!= SHIFT_LSL
)
5093 inst
.error
= _("'LSL' required");
5098 case SHIFT_ASR_IMMEDIATE
:
5099 if (shift
!= SHIFT_ASR
)
5101 inst
.error
= _("'ASR' required");
5109 if (shift
!= SHIFT_RRX
)
5111 /* Whitespace can appear here if the next thing is a bare digit. */
5112 skip_whitespace (p
);
5114 if (mode
== NO_SHIFT_RESTRICT
5115 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5117 inst
.operands
[i
].imm
= reg
;
5118 inst
.operands
[i
].immisreg
= 1;
5120 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5123 inst
.operands
[i
].shift_kind
= shift
;
5124 inst
.operands
[i
].shifted
= 1;
5129 /* Parse a <shifter_operand> for an ARM data processing instruction:
5132 #<immediate>, <rotate>
5136 where <shift> is defined by parse_shift above, and <rotate> is a
5137 multiple of 2 between 0 and 30. Validation of immediate operands
5138 is deferred to md_apply_fix. */
5141 parse_shifter_operand (char **str
, int i
)
5146 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5148 inst
.operands
[i
].reg
= value
;
5149 inst
.operands
[i
].isreg
= 1;
5151 /* parse_shift will override this if appropriate */
5152 inst
.reloc
.exp
.X_op
= O_constant
;
5153 inst
.reloc
.exp
.X_add_number
= 0;
5155 if (skip_past_comma (str
) == FAIL
)
5158 /* Shift operation on register. */
5159 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5162 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5165 if (skip_past_comma (str
) == SUCCESS
)
5167 /* #x, y -- ie explicit rotation by Y. */
5168 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5171 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5173 inst
.error
= _("constant expression expected");
5177 value
= exp
.X_add_number
;
5178 if (value
< 0 || value
> 30 || value
% 2 != 0)
5180 inst
.error
= _("invalid rotation");
5183 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5185 inst
.error
= _("invalid constant");
5189 /* Encode as specified. */
5190 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5194 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5195 inst
.reloc
.pc_rel
= 0;
5199 /* Group relocation information. Each entry in the table contains the
5200 textual name of the relocation as may appear in assembler source
5201 and must end with a colon.
5202 Along with this textual name are the relocation codes to be used if
5203 the corresponding instruction is an ALU instruction (ADD or SUB only),
5204 an LDR, an LDRS, or an LDC. */
5206 struct group_reloc_table_entry
5217 /* Varieties of non-ALU group relocation. */
5224 static struct group_reloc_table_entry group_reloc_table
[] =
5225 { /* Program counter relative: */
5227 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5232 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5233 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5234 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5235 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5237 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5242 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5243 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5244 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5245 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5247 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5248 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5249 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5250 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5251 /* Section base relative */
5253 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5258 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5259 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5260 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5261 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5263 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5268 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5269 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5270 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5271 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5273 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5274 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5278 /* Given the address of a pointer pointing to the textual name of a group
5279 relocation as may appear in assembler source, attempt to find its details
5280 in group_reloc_table. The pointer will be updated to the character after
5281 the trailing colon. On failure, FAIL will be returned; SUCCESS
5282 otherwise. On success, *entry will be updated to point at the relevant
5283 group_reloc_table entry. */
5286 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5289 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5291 int length
= strlen (group_reloc_table
[i
].name
);
5293 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5294 && (*str
)[length
] == ':')
5296 *out
= &group_reloc_table
[i
];
5297 *str
+= (length
+ 1);
5305 /* Parse a <shifter_operand> for an ARM data processing instruction
5306 (as for parse_shifter_operand) where group relocations are allowed:
5309 #<immediate>, <rotate>
5310 #:<group_reloc>:<expression>
5314 where <group_reloc> is one of the strings defined in group_reloc_table.
5315 The hashes are optional.
5317 Everything else is as for parse_shifter_operand. */
5319 static parse_operand_result
5320 parse_shifter_operand_group_reloc (char **str
, int i
)
5322 /* Determine if we have the sequence of characters #: or just :
5323 coming next. If we do, then we check for a group relocation.
5324 If we don't, punt the whole lot to parse_shifter_operand. */
5326 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5327 || (*str
)[0] == ':')
5329 struct group_reloc_table_entry
*entry
;
5331 if ((*str
)[0] == '#')
5336 /* Try to parse a group relocation. Anything else is an error. */
5337 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5339 inst
.error
= _("unknown group relocation");
5340 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5343 /* We now have the group relocation table entry corresponding to
5344 the name in the assembler source. Next, we parse the expression. */
5345 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5346 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5348 /* Record the relocation type (always the ALU variant here). */
5349 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5350 gas_assert (inst
.reloc
.type
!= 0);
5352 return PARSE_OPERAND_SUCCESS
;
5355 return parse_shifter_operand (str
, i
) == SUCCESS
5356 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5358 /* Never reached. */
5361 /* Parse a Neon alignment expression. Information is written to
5362 inst.operands[i]. We assume the initial ':' has been skipped.
5364 align .imm = align << 8, .immisalign=1, .preind=0 */
5365 static parse_operand_result
5366 parse_neon_alignment (char **str
, int i
)
5371 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5373 if (exp
.X_op
!= O_constant
)
5375 inst
.error
= _("alignment must be constant");
5376 return PARSE_OPERAND_FAIL
;
5379 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5380 inst
.operands
[i
].immisalign
= 1;
5381 /* Alignments are not pre-indexes. */
5382 inst
.operands
[i
].preind
= 0;
5385 return PARSE_OPERAND_SUCCESS
;
5388 /* Parse all forms of an ARM address expression. Information is written
5389 to inst.operands[i] and/or inst.reloc.
5391 Preindexed addressing (.preind=1):
5393 [Rn, #offset] .reg=Rn .reloc.exp=offset
5394 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5395 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5396 .shift_kind=shift .reloc.exp=shift_imm
5398 These three may have a trailing ! which causes .writeback to be set also.
5400 Postindexed addressing (.postind=1, .writeback=1):
5402 [Rn], #offset .reg=Rn .reloc.exp=offset
5403 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5404 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5405 .shift_kind=shift .reloc.exp=shift_imm
5407 Unindexed addressing (.preind=0, .postind=0):
5409 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5413 [Rn]{!} shorthand for [Rn,#0]{!}
5414 =immediate .isreg=0 .reloc.exp=immediate
5415 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5417 It is the caller's responsibility to check for addressing modes not
5418 supported by the instruction, and to set inst.reloc.type. */
5420 static parse_operand_result
5421 parse_address_main (char **str
, int i
, int group_relocations
,
5422 group_reloc_type group_type
)
5427 if (skip_past_char (&p
, '[') == FAIL
)
5429 if (skip_past_char (&p
, '=') == FAIL
)
5431 /* Bare address - translate to PC-relative offset. */
5432 inst
.reloc
.pc_rel
= 1;
5433 inst
.operands
[i
].reg
= REG_PC
;
5434 inst
.operands
[i
].isreg
= 1;
5435 inst
.operands
[i
].preind
= 1;
5437 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5438 return PARSE_OPERAND_FAIL
;
5440 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5441 /*allow_symbol_p=*/TRUE
))
5442 return PARSE_OPERAND_FAIL
;
5445 return PARSE_OPERAND_SUCCESS
;
5448 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5449 skip_whitespace (p
);
5451 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5453 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5454 return PARSE_OPERAND_FAIL
;
5456 inst
.operands
[i
].reg
= reg
;
5457 inst
.operands
[i
].isreg
= 1;
5459 if (skip_past_comma (&p
) == SUCCESS
)
5461 inst
.operands
[i
].preind
= 1;
5464 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5466 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5468 inst
.operands
[i
].imm
= reg
;
5469 inst
.operands
[i
].immisreg
= 1;
5471 if (skip_past_comma (&p
) == SUCCESS
)
5472 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5473 return PARSE_OPERAND_FAIL
;
5475 else if (skip_past_char (&p
, ':') == SUCCESS
)
5477 /* FIXME: '@' should be used here, but it's filtered out by generic
5478 code before we get to see it here. This may be subject to
5480 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5482 if (result
!= PARSE_OPERAND_SUCCESS
)
5487 if (inst
.operands
[i
].negative
)
5489 inst
.operands
[i
].negative
= 0;
5493 if (group_relocations
5494 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5496 struct group_reloc_table_entry
*entry
;
5498 /* Skip over the #: or : sequence. */
5504 /* Try to parse a group relocation. Anything else is an
5506 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5508 inst
.error
= _("unknown group relocation");
5509 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5512 /* We now have the group relocation table entry corresponding to
5513 the name in the assembler source. Next, we parse the
5515 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5516 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5518 /* Record the relocation type. */
5522 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5526 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5530 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5537 if (inst
.reloc
.type
== 0)
5539 inst
.error
= _("this group relocation is not allowed on this instruction");
5540 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5546 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5547 return PARSE_OPERAND_FAIL
;
5548 /* If the offset is 0, find out if it's a +0 or -0. */
5549 if (inst
.reloc
.exp
.X_op
== O_constant
5550 && inst
.reloc
.exp
.X_add_number
== 0)
5552 skip_whitespace (q
);
5556 skip_whitespace (q
);
5559 inst
.operands
[i
].negative
= 1;
5564 else if (skip_past_char (&p
, ':') == SUCCESS
)
5566 /* FIXME: '@' should be used here, but it's filtered out by generic code
5567 before we get to see it here. This may be subject to change. */
5568 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5570 if (result
!= PARSE_OPERAND_SUCCESS
)
5574 if (skip_past_char (&p
, ']') == FAIL
)
5576 inst
.error
= _("']' expected");
5577 return PARSE_OPERAND_FAIL
;
5580 if (skip_past_char (&p
, '!') == SUCCESS
)
5581 inst
.operands
[i
].writeback
= 1;
5583 else if (skip_past_comma (&p
) == SUCCESS
)
5585 if (skip_past_char (&p
, '{') == SUCCESS
)
5587 /* [Rn], {expr} - unindexed, with option */
5588 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5589 0, 255, TRUE
) == FAIL
)
5590 return PARSE_OPERAND_FAIL
;
5592 if (skip_past_char (&p
, '}') == FAIL
)
5594 inst
.error
= _("'}' expected at end of 'option' field");
5595 return PARSE_OPERAND_FAIL
;
5597 if (inst
.operands
[i
].preind
)
5599 inst
.error
= _("cannot combine index with option");
5600 return PARSE_OPERAND_FAIL
;
5603 return PARSE_OPERAND_SUCCESS
;
5607 inst
.operands
[i
].postind
= 1;
5608 inst
.operands
[i
].writeback
= 1;
5610 if (inst
.operands
[i
].preind
)
5612 inst
.error
= _("cannot combine pre- and post-indexing");
5613 return PARSE_OPERAND_FAIL
;
5617 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5619 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5621 /* We might be using the immediate for alignment already. If we
5622 are, OR the register number into the low-order bits. */
5623 if (inst
.operands
[i
].immisalign
)
5624 inst
.operands
[i
].imm
|= reg
;
5626 inst
.operands
[i
].imm
= reg
;
5627 inst
.operands
[i
].immisreg
= 1;
5629 if (skip_past_comma (&p
) == SUCCESS
)
5630 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5631 return PARSE_OPERAND_FAIL
;
5636 if (inst
.operands
[i
].negative
)
5638 inst
.operands
[i
].negative
= 0;
5641 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5642 return PARSE_OPERAND_FAIL
;
5643 /* If the offset is 0, find out if it's a +0 or -0. */
5644 if (inst
.reloc
.exp
.X_op
== O_constant
5645 && inst
.reloc
.exp
.X_add_number
== 0)
5647 skip_whitespace (q
);
5651 skip_whitespace (q
);
5654 inst
.operands
[i
].negative
= 1;
5660 /* If at this point neither .preind nor .postind is set, we have a
5661 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5662 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5664 inst
.operands
[i
].preind
= 1;
5665 inst
.reloc
.exp
.X_op
= O_constant
;
5666 inst
.reloc
.exp
.X_add_number
= 0;
5669 return PARSE_OPERAND_SUCCESS
;
5673 parse_address (char **str
, int i
)
5675 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5679 static parse_operand_result
5680 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5682 return parse_address_main (str
, i
, 1, type
);
5685 /* Parse an operand for a MOVW or MOVT instruction. */
5687 parse_half (char **str
)
5692 skip_past_char (&p
, '#');
5693 if (strncasecmp (p
, ":lower16:", 9) == 0)
5694 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5695 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5696 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5698 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5701 skip_whitespace (p
);
5704 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5707 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5709 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5711 inst
.error
= _("constant expression expected");
5714 if (inst
.reloc
.exp
.X_add_number
< 0
5715 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5717 inst
.error
= _("immediate value out of range");
5725 /* Miscellaneous. */
5727 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5728 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5730 parse_psr (char **str
, bfd_boolean lhs
)
5733 unsigned long psr_field
;
5734 const struct asm_psr
*psr
;
5736 bfd_boolean is_apsr
= FALSE
;
5737 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5739 /* PR gas/12698: If the user has specified -march=all then m_profile will
5740 be TRUE, but we want to ignore it in this case as we are building for any
5741 CPU type, including non-m variants. */
5742 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5745 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5746 feature for ease of use and backwards compatibility. */
5748 if (strncasecmp (p
, "SPSR", 4) == 0)
5751 goto unsupported_psr
;
5753 psr_field
= SPSR_BIT
;
5755 else if (strncasecmp (p
, "CPSR", 4) == 0)
5758 goto unsupported_psr
;
5762 else if (strncasecmp (p
, "APSR", 4) == 0)
5764 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5765 and ARMv7-R architecture CPUs. */
5774 while (ISALNUM (*p
) || *p
== '_');
5776 if (strncasecmp (start
, "iapsr", 5) == 0
5777 || strncasecmp (start
, "eapsr", 5) == 0
5778 || strncasecmp (start
, "xpsr", 4) == 0
5779 || strncasecmp (start
, "psr", 3) == 0)
5780 p
= start
+ strcspn (start
, "rR") + 1;
5782 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5788 /* If APSR is being written, a bitfield may be specified. Note that
5789 APSR itself is handled above. */
5790 if (psr
->field
<= 3)
5792 psr_field
= psr
->field
;
5798 /* M-profile MSR instructions have the mask field set to "10", except
5799 *PSR variants which modify APSR, which may use a different mask (and
5800 have been handled already). Do that by setting the PSR_f field
5802 return psr
->field
| (lhs
? PSR_f
: 0);
5805 goto unsupported_psr
;
5811 /* A suffix follows. */
5817 while (ISALNUM (*p
) || *p
== '_');
5821 /* APSR uses a notation for bits, rather than fields. */
5822 unsigned int nzcvq_bits
= 0;
5823 unsigned int g_bit
= 0;
5826 for (bit
= start
; bit
!= p
; bit
++)
5828 switch (TOLOWER (*bit
))
5831 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5835 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5839 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5843 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5847 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5851 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5855 inst
.error
= _("unexpected bit specified after APSR");
5860 if (nzcvq_bits
== 0x1f)
5865 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5867 inst
.error
= _("selected processor does not "
5868 "support DSP extension");
5875 if ((nzcvq_bits
& 0x20) != 0
5876 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5877 || (g_bit
& 0x2) != 0)
5879 inst
.error
= _("bad bitmask specified after APSR");
5885 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5890 psr_field
|= psr
->field
;
5896 goto error
; /* Garbage after "[CS]PSR". */
5898 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5899 is deprecated, but allow it anyway. */
5903 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5906 else if (!m_profile
)
5907 /* These bits are never right for M-profile devices: don't set them
5908 (only code paths which read/write APSR reach here). */
5909 psr_field
|= (PSR_c
| PSR_f
);
5915 inst
.error
= _("selected processor does not support requested special "
5916 "purpose register");
5920 inst
.error
= _("flag for {c}psr instruction expected");
5924 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5925 value suitable for splatting into the AIF field of the instruction. */
5928 parse_cps_flags (char **str
)
5937 case '\0': case ',':
5940 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5941 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5942 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5945 inst
.error
= _("unrecognized CPS flag");
5950 if (saw_a_flag
== 0)
5952 inst
.error
= _("missing CPS flags");
5960 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5961 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5964 parse_endian_specifier (char **str
)
5969 if (strncasecmp (s
, "BE", 2))
5971 else if (strncasecmp (s
, "LE", 2))
5975 inst
.error
= _("valid endian specifiers are be or le");
5979 if (ISALNUM (s
[2]) || s
[2] == '_')
5981 inst
.error
= _("valid endian specifiers are be or le");
5986 return little_endian
;
5989 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5990 value suitable for poking into the rotate field of an sxt or sxta
5991 instruction, or FAIL on error. */
5994 parse_ror (char **str
)
5999 if (strncasecmp (s
, "ROR", 3) == 0)
6003 inst
.error
= _("missing rotation field after comma");
6007 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6012 case 0: *str
= s
; return 0x0;
6013 case 8: *str
= s
; return 0x1;
6014 case 16: *str
= s
; return 0x2;
6015 case 24: *str
= s
; return 0x3;
6018 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6023 /* Parse a conditional code (from conds[] below). The value returned is in the
6024 range 0 .. 14, or FAIL. */
6026 parse_cond (char **str
)
6029 const struct asm_cond
*c
;
6031 /* Condition codes are always 2 characters, so matching up to
6032 3 characters is sufficient. */
6037 while (ISALPHA (*q
) && n
< 3)
6039 cond
[n
] = TOLOWER (*q
);
6044 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6047 inst
.error
= _("condition required");
6055 /* If the given feature available in the selected CPU, mark it as used.
6056 Returns TRUE iff feature is available. */
6058 mark_feature_used (const arm_feature_set
*feature
)
6060 /* Ensure the option is valid on the current architecture. */
6061 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6064 /* Add the appropriate architecture feature for the barrier option used.
6067 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6069 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6074 /* Parse an option for a barrier instruction. Returns the encoding for the
6077 parse_barrier (char **str
)
6080 const struct asm_barrier_opt
*o
;
6083 while (ISALPHA (*q
))
6086 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6091 if (!mark_feature_used (&o
->arch
))
6098 /* Parse the operands of a table branch instruction. Similar to a memory
6101 parse_tb (char **str
)
6106 if (skip_past_char (&p
, '[') == FAIL
)
6108 inst
.error
= _("'[' expected");
6112 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6114 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6117 inst
.operands
[0].reg
= reg
;
6119 if (skip_past_comma (&p
) == FAIL
)
6121 inst
.error
= _("',' expected");
6125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6127 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6130 inst
.operands
[0].imm
= reg
;
6132 if (skip_past_comma (&p
) == SUCCESS
)
6134 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6136 if (inst
.reloc
.exp
.X_add_number
!= 1)
6138 inst
.error
= _("invalid shift");
6141 inst
.operands
[0].shifted
= 1;
6144 if (skip_past_char (&p
, ']') == FAIL
)
6146 inst
.error
= _("']' expected");
6153 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6154 information on the types the operands can take and how they are encoded.
6155 Up to four operands may be read; this function handles setting the
6156 ".present" field for each read operand itself.
6157 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6158 else returns FAIL. */
6161 parse_neon_mov (char **str
, int *which_operand
)
6163 int i
= *which_operand
, val
;
6164 enum arm_reg_type rtype
;
6166 struct neon_type_el optype
;
6168 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6170 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6171 inst
.operands
[i
].reg
= val
;
6172 inst
.operands
[i
].isscalar
= 1;
6173 inst
.operands
[i
].vectype
= optype
;
6174 inst
.operands
[i
++].present
= 1;
6176 if (skip_past_comma (&ptr
) == FAIL
)
6179 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6182 inst
.operands
[i
].reg
= val
;
6183 inst
.operands
[i
].isreg
= 1;
6184 inst
.operands
[i
].present
= 1;
6186 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6189 /* Cases 0, 1, 2, 3, 5 (D only). */
6190 if (skip_past_comma (&ptr
) == FAIL
)
6193 inst
.operands
[i
].reg
= val
;
6194 inst
.operands
[i
].isreg
= 1;
6195 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6196 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6197 inst
.operands
[i
].isvec
= 1;
6198 inst
.operands
[i
].vectype
= optype
;
6199 inst
.operands
[i
++].present
= 1;
6201 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6203 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6204 Case 13: VMOV <Sd>, <Rm> */
6205 inst
.operands
[i
].reg
= val
;
6206 inst
.operands
[i
].isreg
= 1;
6207 inst
.operands
[i
].present
= 1;
6209 if (rtype
== REG_TYPE_NQ
)
6211 first_error (_("can't use Neon quad register here"));
6214 else if (rtype
!= REG_TYPE_VFS
)
6217 if (skip_past_comma (&ptr
) == FAIL
)
6219 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6221 inst
.operands
[i
].reg
= val
;
6222 inst
.operands
[i
].isreg
= 1;
6223 inst
.operands
[i
].present
= 1;
6226 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6229 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6230 Case 1: VMOV<c><q> <Dd>, <Dm>
6231 Case 8: VMOV.F32 <Sd>, <Sm>
6232 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6234 inst
.operands
[i
].reg
= val
;
6235 inst
.operands
[i
].isreg
= 1;
6236 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6237 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6238 inst
.operands
[i
].isvec
= 1;
6239 inst
.operands
[i
].vectype
= optype
;
6240 inst
.operands
[i
].present
= 1;
6242 if (skip_past_comma (&ptr
) == SUCCESS
)
6247 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6250 inst
.operands
[i
].reg
= val
;
6251 inst
.operands
[i
].isreg
= 1;
6252 inst
.operands
[i
++].present
= 1;
6254 if (skip_past_comma (&ptr
) == FAIL
)
6257 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6260 inst
.operands
[i
].reg
= val
;
6261 inst
.operands
[i
].isreg
= 1;
6262 inst
.operands
[i
].present
= 1;
6265 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6266 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6267 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6268 Case 10: VMOV.F32 <Sd>, #<imm>
6269 Case 11: VMOV.F64 <Dd>, #<imm> */
6270 inst
.operands
[i
].immisfloat
= 1;
6271 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6273 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6274 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6278 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6282 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6285 inst
.operands
[i
].reg
= val
;
6286 inst
.operands
[i
].isreg
= 1;
6287 inst
.operands
[i
++].present
= 1;
6289 if (skip_past_comma (&ptr
) == FAIL
)
6292 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6294 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6295 inst
.operands
[i
].reg
= val
;
6296 inst
.operands
[i
].isscalar
= 1;
6297 inst
.operands
[i
].present
= 1;
6298 inst
.operands
[i
].vectype
= optype
;
6300 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6302 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
++].present
= 1;
6307 if (skip_past_comma (&ptr
) == FAIL
)
6310 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6313 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6317 inst
.operands
[i
].reg
= val
;
6318 inst
.operands
[i
].isreg
= 1;
6319 inst
.operands
[i
].isvec
= 1;
6320 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6321 inst
.operands
[i
].vectype
= optype
;
6322 inst
.operands
[i
].present
= 1;
6324 if (rtype
== REG_TYPE_VFS
)
6328 if (skip_past_comma (&ptr
) == FAIL
)
6330 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6333 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6336 inst
.operands
[i
].reg
= val
;
6337 inst
.operands
[i
].isreg
= 1;
6338 inst
.operands
[i
].isvec
= 1;
6339 inst
.operands
[i
].issingle
= 1;
6340 inst
.operands
[i
].vectype
= optype
;
6341 inst
.operands
[i
].present
= 1;
6344 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6348 inst
.operands
[i
].reg
= val
;
6349 inst
.operands
[i
].isreg
= 1;
6350 inst
.operands
[i
].isvec
= 1;
6351 inst
.operands
[i
].issingle
= 1;
6352 inst
.operands
[i
].vectype
= optype
;
6353 inst
.operands
[i
].present
= 1;
6358 first_error (_("parse error"));
6362 /* Successfully parsed the operands. Update args. */
6368 first_error (_("expected comma"));
6372 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6376 /* Use this macro when the operand constraints are different
6377 for ARM and THUMB (e.g. ldrd). */
6378 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6379 ((arm_operand) | ((thumb_operand) << 16))
6381 /* Matcher codes for parse_operands. */
6382 enum operand_parse_code
6384 OP_stop
, /* end of line */
6386 OP_RR
, /* ARM register */
6387 OP_RRnpc
, /* ARM register, not r15 */
6388 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6389 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6390 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6391 optional trailing ! */
6392 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6393 OP_RCP
, /* Coprocessor number */
6394 OP_RCN
, /* Coprocessor register */
6395 OP_RF
, /* FPA register */
6396 OP_RVS
, /* VFP single precision register */
6397 OP_RVD
, /* VFP double precision register (0..15) */
6398 OP_RND
, /* Neon double precision register (0..31) */
6399 OP_RNQ
, /* Neon quad precision register */
6400 OP_RVSD
, /* VFP single or double precision register */
6401 OP_RNDQ
, /* Neon double or quad precision register */
6402 OP_RNSDQ
, /* Neon single, double or quad precision register */
6403 OP_RNSC
, /* Neon scalar D[X] */
6404 OP_RVC
, /* VFP control register */
6405 OP_RMF
, /* Maverick F register */
6406 OP_RMD
, /* Maverick D register */
6407 OP_RMFX
, /* Maverick FX register */
6408 OP_RMDX
, /* Maverick DX register */
6409 OP_RMAX
, /* Maverick AX register */
6410 OP_RMDS
, /* Maverick DSPSC register */
6411 OP_RIWR
, /* iWMMXt wR register */
6412 OP_RIWC
, /* iWMMXt wC register */
6413 OP_RIWG
, /* iWMMXt wCG register */
6414 OP_RXA
, /* XScale accumulator register */
6416 OP_REGLST
, /* ARM register list */
6417 OP_VRSLST
, /* VFP single-precision register list */
6418 OP_VRDLST
, /* VFP double-precision register list */
6419 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6420 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6421 OP_NSTRLST
, /* Neon element/structure list */
6423 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6424 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6425 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6426 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6427 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6428 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6429 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6430 OP_VMOV
, /* Neon VMOV operands. */
6431 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6432 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6433 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6435 OP_I0
, /* immediate zero */
6436 OP_I7
, /* immediate value 0 .. 7 */
6437 OP_I15
, /* 0 .. 15 */
6438 OP_I16
, /* 1 .. 16 */
6439 OP_I16z
, /* 0 .. 16 */
6440 OP_I31
, /* 0 .. 31 */
6441 OP_I31w
, /* 0 .. 31, optional trailing ! */
6442 OP_I32
, /* 1 .. 32 */
6443 OP_I32z
, /* 0 .. 32 */
6444 OP_I63
, /* 0 .. 63 */
6445 OP_I63s
, /* -64 .. 63 */
6446 OP_I64
, /* 1 .. 64 */
6447 OP_I64z
, /* 0 .. 64 */
6448 OP_I255
, /* 0 .. 255 */
6450 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6451 OP_I7b
, /* 0 .. 7 */
6452 OP_I15b
, /* 0 .. 15 */
6453 OP_I31b
, /* 0 .. 31 */
6455 OP_SH
, /* shifter operand */
6456 OP_SHG
, /* shifter operand with possible group relocation */
6457 OP_ADDR
, /* Memory address expression (any mode) */
6458 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6459 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6460 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6461 OP_EXP
, /* arbitrary expression */
6462 OP_EXPi
, /* same, with optional immediate prefix */
6463 OP_EXPr
, /* same, with optional relocation suffix */
6464 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6466 OP_CPSF
, /* CPS flags */
6467 OP_ENDI
, /* Endianness specifier */
6468 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6469 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6470 OP_COND
, /* conditional code */
6471 OP_TB
, /* Table branch. */
6473 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6475 OP_RRnpc_I0
, /* ARM register or literal 0 */
6476 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6477 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6478 OP_RF_IF
, /* FPA register or immediate */
6479 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6480 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6482 /* Optional operands. */
6483 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6484 OP_oI31b
, /* 0 .. 31 */
6485 OP_oI32b
, /* 1 .. 32 */
6486 OP_oI32z
, /* 0 .. 32 */
6487 OP_oIffffb
, /* 0 .. 65535 */
6488 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6490 OP_oRR
, /* ARM register */
6491 OP_oRRnpc
, /* ARM register, not the PC */
6492 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6493 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6494 OP_oRND
, /* Optional Neon double precision register */
6495 OP_oRNQ
, /* Optional Neon quad precision register */
6496 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6497 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6498 OP_oSHll
, /* LSL immediate */
6499 OP_oSHar
, /* ASR immediate */
6500 OP_oSHllar
, /* LSL or ASR immediate */
6501 OP_oROR
, /* ROR 0/8/16/24 */
6502 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6504 /* Some pre-defined mixed (ARM/THUMB) operands. */
6505 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6506 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6507 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6509 OP_FIRST_OPTIONAL
= OP_oI7b
6512 /* Generic instruction operand parser. This does no encoding and no
6513 semantic validation; it merely squirrels values away in the inst
6514 structure. Returns SUCCESS or FAIL depending on whether the
6515 specified grammar matched. */
6517 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6519 unsigned const int *upat
= pattern
;
6520 char *backtrack_pos
= 0;
6521 const char *backtrack_error
= 0;
6522 int i
, val
= 0, backtrack_index
= 0;
6523 enum arm_reg_type rtype
;
6524 parse_operand_result result
;
6525 unsigned int op_parse_code
;
6527 #define po_char_or_fail(chr) \
6530 if (skip_past_char (&str, chr) == FAIL) \
6535 #define po_reg_or_fail(regtype) \
6538 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6539 & inst.operands[i].vectype); \
6542 first_error (_(reg_expected_msgs[regtype])); \
6545 inst.operands[i].reg = val; \
6546 inst.operands[i].isreg = 1; \
6547 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6548 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6549 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6550 || rtype == REG_TYPE_VFD \
6551 || rtype == REG_TYPE_NQ); \
6555 #define po_reg_or_goto(regtype, label) \
6558 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6559 & inst.operands[i].vectype); \
6563 inst.operands[i].reg = val; \
6564 inst.operands[i].isreg = 1; \
6565 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6566 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6567 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6568 || rtype == REG_TYPE_VFD \
6569 || rtype == REG_TYPE_NQ); \
6573 #define po_imm_or_fail(min, max, popt) \
6576 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6578 inst.operands[i].imm = val; \
6582 #define po_scalar_or_goto(elsz, label) \
6585 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6588 inst.operands[i].reg = val; \
6589 inst.operands[i].isscalar = 1; \
6593 #define po_misc_or_fail(expr) \
6601 #define po_misc_or_fail_no_backtrack(expr) \
6605 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6606 backtrack_pos = 0; \
6607 if (result != PARSE_OPERAND_SUCCESS) \
6612 #define po_barrier_or_imm(str) \
6615 val = parse_barrier (&str); \
6616 if (val == FAIL && ! ISALPHA (*str)) \
6619 /* ISB can only take SY as an option. */ \
6620 || ((inst.instruction & 0xf0) == 0x60 \
6623 inst.error = _("invalid barrier type"); \
6624 backtrack_pos = 0; \
6630 skip_whitespace (str
);
6632 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6634 op_parse_code
= upat
[i
];
6635 if (op_parse_code
>= 1<<16)
6636 op_parse_code
= thumb
? (op_parse_code
>> 16)
6637 : (op_parse_code
& ((1<<16)-1));
6639 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6641 /* Remember where we are in case we need to backtrack. */
6642 gas_assert (!backtrack_pos
);
6643 backtrack_pos
= str
;
6644 backtrack_error
= inst
.error
;
6645 backtrack_index
= i
;
6648 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6649 po_char_or_fail (',');
6651 switch (op_parse_code
)
6659 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6660 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6661 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6662 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6663 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6664 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6666 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6668 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6670 /* Also accept generic coprocessor regs for unknown registers. */
6672 po_reg_or_fail (REG_TYPE_CN
);
6674 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6675 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6676 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6677 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6678 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6679 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6680 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6681 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6682 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6683 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6685 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6687 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6688 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6690 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6692 /* Neon scalar. Using an element size of 8 means that some invalid
6693 scalars are accepted here, so deal with those in later code. */
6694 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6698 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6701 po_imm_or_fail (0, 0, TRUE
);
6706 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6711 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6714 if (parse_ifimm_zero (&str
))
6715 inst
.operands
[i
].imm
= 0;
6719 = _("only floating point zero is allowed as immediate value");
6727 po_scalar_or_goto (8, try_rr
);
6730 po_reg_or_fail (REG_TYPE_RN
);
6736 po_scalar_or_goto (8, try_nsdq
);
6739 po_reg_or_fail (REG_TYPE_NSDQ
);
6745 po_scalar_or_goto (8, try_ndq
);
6748 po_reg_or_fail (REG_TYPE_NDQ
);
6754 po_scalar_or_goto (8, try_vfd
);
6757 po_reg_or_fail (REG_TYPE_VFD
);
6762 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6763 not careful then bad things might happen. */
6764 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6769 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6772 /* There's a possibility of getting a 64-bit immediate here, so
6773 we need special handling. */
6774 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6777 inst
.error
= _("immediate value is out of range");
6785 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6788 po_imm_or_fail (0, 63, TRUE
);
6793 po_char_or_fail ('[');
6794 po_reg_or_fail (REG_TYPE_RN
);
6795 po_char_or_fail (']');
6801 po_reg_or_fail (REG_TYPE_RN
);
6802 if (skip_past_char (&str
, '!') == SUCCESS
)
6803 inst
.operands
[i
].writeback
= 1;
6807 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6808 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6809 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6810 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6811 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6812 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6813 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6814 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6815 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6816 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6817 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6818 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6820 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6822 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6823 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6825 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6826 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6827 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6828 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6830 /* Immediate variants */
6832 po_char_or_fail ('{');
6833 po_imm_or_fail (0, 255, TRUE
);
6834 po_char_or_fail ('}');
6838 /* The expression parser chokes on a trailing !, so we have
6839 to find it first and zap it. */
6842 while (*s
&& *s
!= ',')
6847 inst
.operands
[i
].writeback
= 1;
6849 po_imm_or_fail (0, 31, TRUE
);
6857 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6862 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6867 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6869 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6871 val
= parse_reloc (&str
);
6874 inst
.error
= _("unrecognized relocation suffix");
6877 else if (val
!= BFD_RELOC_UNUSED
)
6879 inst
.operands
[i
].imm
= val
;
6880 inst
.operands
[i
].hasreloc
= 1;
6885 /* Operand for MOVW or MOVT. */
6887 po_misc_or_fail (parse_half (&str
));
6890 /* Register or expression. */
6891 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6892 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6894 /* Register or immediate. */
6895 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6896 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6898 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6900 if (!is_immediate_prefix (*str
))
6903 val
= parse_fpa_immediate (&str
);
6906 /* FPA immediates are encoded as registers 8-15.
6907 parse_fpa_immediate has already applied the offset. */
6908 inst
.operands
[i
].reg
= val
;
6909 inst
.operands
[i
].isreg
= 1;
6912 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6913 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6915 /* Two kinds of register. */
6918 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6920 || (rege
->type
!= REG_TYPE_MMXWR
6921 && rege
->type
!= REG_TYPE_MMXWC
6922 && rege
->type
!= REG_TYPE_MMXWCG
))
6924 inst
.error
= _("iWMMXt data or control register expected");
6927 inst
.operands
[i
].reg
= rege
->number
;
6928 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6934 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6936 || (rege
->type
!= REG_TYPE_MMXWC
6937 && rege
->type
!= REG_TYPE_MMXWCG
))
6939 inst
.error
= _("iWMMXt control register expected");
6942 inst
.operands
[i
].reg
= rege
->number
;
6943 inst
.operands
[i
].isreg
= 1;
6948 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6949 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6950 case OP_oROR
: val
= parse_ror (&str
); break;
6951 case OP_COND
: val
= parse_cond (&str
); break;
6952 case OP_oBARRIER_I15
:
6953 po_barrier_or_imm (str
); break;
6955 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6961 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6962 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6964 inst
.error
= _("Banked registers are not available with this "
6970 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6974 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6977 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6979 if (strncasecmp (str
, "APSR_", 5) == 0)
6986 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6987 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6988 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6989 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6990 default: found
= 16;
6994 inst
.operands
[i
].isvec
= 1;
6995 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6996 inst
.operands
[i
].reg
= REG_PC
;
7003 po_misc_or_fail (parse_tb (&str
));
7006 /* Register lists. */
7008 val
= parse_reg_list (&str
);
7011 inst
.operands
[i
].writeback
= 1;
7017 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7021 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7025 /* Allow Q registers too. */
7026 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7031 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7033 inst
.operands
[i
].issingle
= 1;
7038 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7043 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7044 &inst
.operands
[i
].vectype
);
7047 /* Addressing modes */
7049 po_misc_or_fail (parse_address (&str
, i
));
7053 po_misc_or_fail_no_backtrack (
7054 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7058 po_misc_or_fail_no_backtrack (
7059 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7063 po_misc_or_fail_no_backtrack (
7064 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7068 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7072 po_misc_or_fail_no_backtrack (
7073 parse_shifter_operand_group_reloc (&str
, i
));
7077 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7081 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7085 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7089 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7092 /* Various value-based sanity checks and shared operations. We
7093 do not signal immediate failures for the register constraints;
7094 this allows a syntax error to take precedence. */
7095 switch (op_parse_code
)
7103 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7104 inst
.error
= BAD_PC
;
7109 if (inst
.operands
[i
].isreg
)
7111 if (inst
.operands
[i
].reg
== REG_PC
)
7112 inst
.error
= BAD_PC
;
7113 else if (inst
.operands
[i
].reg
== REG_SP
)
7114 inst
.error
= BAD_SP
;
7119 if (inst
.operands
[i
].isreg
7120 && inst
.operands
[i
].reg
== REG_PC
7121 && (inst
.operands
[i
].writeback
|| thumb
))
7122 inst
.error
= BAD_PC
;
7131 case OP_oBARRIER_I15
:
7140 inst
.operands
[i
].imm
= val
;
7147 /* If we get here, this operand was successfully parsed. */
7148 inst
.operands
[i
].present
= 1;
7152 inst
.error
= BAD_ARGS
;
7157 /* The parse routine should already have set inst.error, but set a
7158 default here just in case. */
7160 inst
.error
= _("syntax error");
7164 /* Do not backtrack over a trailing optional argument that
7165 absorbed some text. We will only fail again, with the
7166 'garbage following instruction' error message, which is
7167 probably less helpful than the current one. */
7168 if (backtrack_index
== i
&& backtrack_pos
!= str
7169 && upat
[i
+1] == OP_stop
)
7172 inst
.error
= _("syntax error");
7176 /* Try again, skipping the optional argument at backtrack_pos. */
7177 str
= backtrack_pos
;
7178 inst
.error
= backtrack_error
;
7179 inst
.operands
[backtrack_index
].present
= 0;
7180 i
= backtrack_index
;
7184 /* Check that we have parsed all the arguments. */
7185 if (*str
!= '\0' && !inst
.error
)
7186 inst
.error
= _("garbage following instruction");
7188 return inst
.error
? FAIL
: SUCCESS
;
7191 #undef po_char_or_fail
7192 #undef po_reg_or_fail
7193 #undef po_reg_or_goto
7194 #undef po_imm_or_fail
7195 #undef po_scalar_or_fail
7196 #undef po_barrier_or_imm
7198 /* Shorthand macro for instruction encoding functions issuing errors. */
7199 #define constraint(expr, err) \
7210 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7211 instructions are unpredictable if these registers are used. This
7212 is the BadReg predicate in ARM's Thumb-2 documentation. */
7213 #define reject_bad_reg(reg) \
7215 if (reg == REG_SP || reg == REG_PC) \
7217 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7222 /* If REG is R13 (the stack pointer), warn that its use is
7224 #define warn_deprecated_sp(reg) \
7226 if (warn_on_deprecated && reg == REG_SP) \
7227 as_tsktsk (_("use of r13 is deprecated")); \
7230 /* Functions for operand encoding. ARM, then Thumb. */
7232 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7234 /* If VAL can be encoded in the immediate field of an ARM instruction,
7235 return the encoded form. Otherwise, return FAIL. */
7238 encode_arm_immediate (unsigned int val
)
7242 for (i
= 0; i
< 32; i
+= 2)
7243 if ((a
= rotate_left (val
, i
)) <= 0xff)
7244 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7249 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7250 return the encoded form. Otherwise, return FAIL. */
7252 encode_thumb32_immediate (unsigned int val
)
7259 for (i
= 1; i
<= 24; i
++)
7262 if ((val
& ~(0xff << i
)) == 0)
7263 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7267 if (val
== ((a
<< 16) | a
))
7269 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7273 if (val
== ((a
<< 16) | a
))
7274 return 0x200 | (a
>> 8);
7278 /* Encode a VFP SP or DP register number into inst.instruction. */
7281 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7283 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7286 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7289 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7292 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7297 first_error (_("D register out of range for selected VFP version"));
7305 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7309 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7313 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7317 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7321 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7325 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7333 /* Encode a <shift> in an ARM-format instruction. The immediate,
7334 if any, is handled by md_apply_fix. */
7336 encode_arm_shift (int i
)
7338 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7339 inst
.instruction
|= SHIFT_ROR
<< 5;
7342 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7343 if (inst
.operands
[i
].immisreg
)
7345 inst
.instruction
|= SHIFT_BY_REG
;
7346 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7349 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7354 encode_arm_shifter_operand (int i
)
7356 if (inst
.operands
[i
].isreg
)
7358 inst
.instruction
|= inst
.operands
[i
].reg
;
7359 encode_arm_shift (i
);
7363 inst
.instruction
|= INST_IMMEDIATE
;
7364 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7365 inst
.instruction
|= inst
.operands
[i
].imm
;
7369 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7371 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7374 Generate an error if the operand is not a register. */
7375 constraint (!inst
.operands
[i
].isreg
,
7376 _("Instruction does not support =N addresses"));
7378 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7380 if (inst
.operands
[i
].preind
)
7384 inst
.error
= _("instruction does not accept preindexed addressing");
7387 inst
.instruction
|= PRE_INDEX
;
7388 if (inst
.operands
[i
].writeback
)
7389 inst
.instruction
|= WRITE_BACK
;
7392 else if (inst
.operands
[i
].postind
)
7394 gas_assert (inst
.operands
[i
].writeback
);
7396 inst
.instruction
|= WRITE_BACK
;
7398 else /* unindexed - only for coprocessor */
7400 inst
.error
= _("instruction does not accept unindexed addressing");
7404 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7405 && (((inst
.instruction
& 0x000f0000) >> 16)
7406 == ((inst
.instruction
& 0x0000f000) >> 12)))
7407 as_warn ((inst
.instruction
& LOAD_BIT
)
7408 ? _("destination register same as write-back base")
7409 : _("source register same as write-back base"));
7412 /* inst.operands[i] was set up by parse_address. Encode it into an
7413 ARM-format mode 2 load or store instruction. If is_t is true,
7414 reject forms that cannot be used with a T instruction (i.e. not
7417 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7419 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7421 encode_arm_addr_mode_common (i
, is_t
);
7423 if (inst
.operands
[i
].immisreg
)
7425 constraint ((inst
.operands
[i
].imm
== REG_PC
7426 || (is_pc
&& inst
.operands
[i
].writeback
)),
7428 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7429 inst
.instruction
|= inst
.operands
[i
].imm
;
7430 if (!inst
.operands
[i
].negative
)
7431 inst
.instruction
|= INDEX_UP
;
7432 if (inst
.operands
[i
].shifted
)
7434 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7435 inst
.instruction
|= SHIFT_ROR
<< 5;
7438 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7439 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7443 else /* immediate offset in inst.reloc */
7445 if (is_pc
&& !inst
.reloc
.pc_rel
)
7447 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7449 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7450 cannot use PC in addressing.
7451 PC cannot be used in writeback addressing, either. */
7452 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7455 /* Use of PC in str is deprecated for ARMv7. */
7456 if (warn_on_deprecated
7458 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7459 as_tsktsk (_("use of PC in this instruction is deprecated"));
7462 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7464 /* Prefer + for zero encoded value. */
7465 if (!inst
.operands
[i
].negative
)
7466 inst
.instruction
|= INDEX_UP
;
7467 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7472 /* inst.operands[i] was set up by parse_address. Encode it into an
7473 ARM-format mode 3 load or store instruction. Reject forms that
7474 cannot be used with such instructions. If is_t is true, reject
7475 forms that cannot be used with a T instruction (i.e. not
7478 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7480 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7482 inst
.error
= _("instruction does not accept scaled register index");
7486 encode_arm_addr_mode_common (i
, is_t
);
7488 if (inst
.operands
[i
].immisreg
)
7490 constraint ((inst
.operands
[i
].imm
== REG_PC
7491 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7493 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7495 inst
.instruction
|= inst
.operands
[i
].imm
;
7496 if (!inst
.operands
[i
].negative
)
7497 inst
.instruction
|= INDEX_UP
;
7499 else /* immediate offset in inst.reloc */
7501 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7502 && inst
.operands
[i
].writeback
),
7504 inst
.instruction
|= HWOFFSET_IMM
;
7505 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7507 /* Prefer + for zero encoded value. */
7508 if (!inst
.operands
[i
].negative
)
7509 inst
.instruction
|= INDEX_UP
;
7511 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7516 /* Write immediate bits [7:0] to the following locations:
7518 |28/24|23 19|18 16|15 4|3 0|
7519 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7521 This function is used by VMOV/VMVN/VORR/VBIC. */
7524 neon_write_immbits (unsigned immbits
)
7526 inst
.instruction
|= immbits
& 0xf;
7527 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7528 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7531 /* Invert low-order SIZE bits of XHI:XLO. */
7534 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7536 unsigned immlo
= xlo
? *xlo
: 0;
7537 unsigned immhi
= xhi
? *xhi
: 0;
7542 immlo
= (~immlo
) & 0xff;
7546 immlo
= (~immlo
) & 0xffff;
7550 immhi
= (~immhi
) & 0xffffffff;
7554 immlo
= (~immlo
) & 0xffffffff;
7568 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7572 neon_bits_same_in_bytes (unsigned imm
)
7574 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7575 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7576 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7577 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7580 /* For immediate of above form, return 0bABCD. */
7583 neon_squash_bits (unsigned imm
)
7585 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7586 | ((imm
& 0x01000000) >> 21);
7589 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7592 neon_qfloat_bits (unsigned imm
)
7594 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7597 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7598 the instruction. *OP is passed as the initial value of the op field, and
7599 may be set to a different value depending on the constant (i.e.
7600 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7601 MVN). If the immediate looks like a repeated pattern then also
7602 try smaller element sizes. */
7605 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7606 unsigned *immbits
, int *op
, int size
,
7607 enum neon_el_type type
)
7609 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7611 if (type
== NT_float
&& !float_p
)
7614 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7616 if (size
!= 32 || *op
== 1)
7618 *immbits
= neon_qfloat_bits (immlo
);
7624 if (neon_bits_same_in_bytes (immhi
)
7625 && neon_bits_same_in_bytes (immlo
))
7629 *immbits
= (neon_squash_bits (immhi
) << 4)
7630 | neon_squash_bits (immlo
);
7641 if (immlo
== (immlo
& 0x000000ff))
7646 else if (immlo
== (immlo
& 0x0000ff00))
7648 *immbits
= immlo
>> 8;
7651 else if (immlo
== (immlo
& 0x00ff0000))
7653 *immbits
= immlo
>> 16;
7656 else if (immlo
== (immlo
& 0xff000000))
7658 *immbits
= immlo
>> 24;
7661 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7663 *immbits
= (immlo
>> 8) & 0xff;
7666 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7668 *immbits
= (immlo
>> 16) & 0xff;
7672 if ((immlo
& 0xffff) != (immlo
>> 16))
7679 if (immlo
== (immlo
& 0x000000ff))
7684 else if (immlo
== (immlo
& 0x0000ff00))
7686 *immbits
= immlo
>> 8;
7690 if ((immlo
& 0xff) != (immlo
>> 8))
7695 if (immlo
== (immlo
& 0x000000ff))
7697 /* Don't allow MVN with 8-bit immediate. */
7707 #if defined BFD_HOST_64_BIT
7708 /* Returns TRUE if double precision value V may be cast
7709 to single precision without loss of accuracy. */
7712 is_double_a_single (bfd_int64_t v
)
7714 int exp
= (int)((v
>> 52) & 0x7FF);
7715 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7717 return (exp
== 0 || exp
== 0x7FF
7718 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7719 && (mantissa
& 0x1FFFFFFFl
) == 0;
7722 /* Returns a double precision value casted to single precision
7723 (ignoring the least significant bits in exponent and mantissa). */
7726 double_to_single (bfd_int64_t v
)
7728 int sign
= (int) ((v
>> 63) & 1l);
7729 int exp
= (int) ((v
>> 52) & 0x7FF);
7730 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7736 exp
= exp
- 1023 + 127;
7745 /* No denormalized numbers. */
7751 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7753 #endif /* BFD_HOST_64_BIT */
7762 static void do_vfp_nsyn_opcode (const char *);
7764 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7765 Determine whether it can be performed with a move instruction; if
7766 it can, convert inst.instruction to that move instruction and
7767 return TRUE; if it can't, convert inst.instruction to a literal-pool
7768 load and return FALSE. If this is not a valid thing to do in the
7769 current context, set inst.error and return TRUE.
7771 inst.operands[i] describes the destination register. */
7774 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7777 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7778 bfd_boolean arm_p
= (t
== CONST_ARM
);
7781 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7785 if ((inst
.instruction
& tbit
) == 0)
7787 inst
.error
= _("invalid pseudo operation");
7791 if (inst
.reloc
.exp
.X_op
!= O_constant
7792 && inst
.reloc
.exp
.X_op
!= O_symbol
7793 && inst
.reloc
.exp
.X_op
!= O_big
)
7795 inst
.error
= _("constant expression expected");
7799 if (inst
.reloc
.exp
.X_op
== O_constant
7800 || inst
.reloc
.exp
.X_op
== O_big
)
7802 #if defined BFD_HOST_64_BIT
7807 if (inst
.reloc
.exp
.X_op
== O_big
)
7809 LITTLENUM_TYPE w
[X_PRECISION
];
7812 if (inst
.reloc
.exp
.X_add_number
== -1)
7814 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7816 /* FIXME: Should we check words w[2..5] ? */
7821 #if defined BFD_HOST_64_BIT
7823 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7824 << LITTLENUM_NUMBER_OF_BITS
)
7825 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7826 << LITTLENUM_NUMBER_OF_BITS
)
7827 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7828 << LITTLENUM_NUMBER_OF_BITS
)
7829 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7831 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7832 | (l
[0] & LITTLENUM_MASK
);
7836 v
= inst
.reloc
.exp
.X_add_number
;
7838 if (!inst
.operands
[i
].issingle
)
7842 if ((v
& ~0xFF) == 0)
7844 /* This can be done with a mov(1) instruction. */
7845 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7846 inst
.instruction
|= v
;
7850 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)
7851 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7853 /* Check if on thumb2 it can be done with a mov.w or mvn.w instruction. */
7854 unsigned int newimm
;
7855 bfd_boolean isNegated
;
7857 newimm
= encode_thumb32_immediate (v
);
7858 if (newimm
!= (unsigned int) FAIL
)
7862 newimm
= encode_thumb32_immediate (~ v
);
7863 if (newimm
!= (unsigned int) FAIL
)
7867 if (newimm
!= (unsigned int) FAIL
)
7869 inst
.instruction
= 0xf04f0000 | (inst
.operands
[i
].reg
<< 8);
7870 inst
.instruction
|= (isNegated
?0x200000:0);
7871 inst
.instruction
|= (newimm
& 0x800) << 15;
7872 inst
.instruction
|= (newimm
& 0x700) << 4;
7873 inst
.instruction
|= (newimm
& 0x0ff);
7876 else if ((v
& ~0xFFFF) == 0 || (v
& ~0xFFFF0000) == 0)
7878 /* The number may be loaded with a movw/movt instruction. */
7881 if ((inst
.reloc
.exp
.X_add_number
& ~0xFFFF) == 0)
7883 inst
.instruction
= 0xf2400000;
7888 inst
.instruction
= 0xf2c00000;
7892 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7893 inst
.instruction
|= (imm
& 0xf000) << 4;
7894 inst
.instruction
|= (imm
& 0x0800) << 15;
7895 inst
.instruction
|= (imm
& 0x0700) << 4;
7896 inst
.instruction
|= (imm
& 0x00ff);
7903 int value
= encode_arm_immediate (v
);
7907 /* This can be done with a mov instruction. */
7908 inst
.instruction
&= LITERAL_MASK
;
7909 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7910 inst
.instruction
|= value
& 0xfff;
7914 value
= encode_arm_immediate (~ v
);
7917 /* This can be done with a mvn instruction. */
7918 inst
.instruction
&= LITERAL_MASK
;
7919 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7920 inst
.instruction
|= value
& 0xfff;
7924 else if (t
== CONST_VEC
)
7927 unsigned immbits
= 0;
7928 unsigned immlo
= inst
.operands
[1].imm
;
7929 unsigned immhi
= inst
.operands
[1].regisimm
7930 ? inst
.operands
[1].reg
7931 : inst
.reloc
.exp
.X_unsigned
7933 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7934 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7935 &op
, 64, NT_invtype
);
7939 neon_invert_size (&immlo
, &immhi
, 64);
7941 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7942 &op
, 64, NT_invtype
);
7947 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7953 /* Fill other bits in vmov encoding for both thumb and arm. */
7955 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
7957 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
7958 neon_write_immbits (immbits
);
7966 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7967 if (inst
.operands
[i
].issingle
7968 && is_quarter_float (inst
.operands
[1].imm
)
7969 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
7971 inst
.operands
[1].imm
=
7972 neon_qfloat_bits (v
);
7973 do_vfp_nsyn_opcode ("fconsts");
7977 /* If our host does not support a 64-bit type then we cannot perform
7978 the following optimization. This mean that there will be a
7979 discrepancy between the output produced by an assembler built for
7980 a 32-bit-only host and the output produced from a 64-bit host, but
7981 this cannot be helped. */
7982 #if defined BFD_HOST_64_BIT
7983 else if (!inst
.operands
[1].issingle
7984 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
7986 if (is_double_a_single (v
)
7987 && is_quarter_float (double_to_single (v
)))
7989 inst
.operands
[1].imm
=
7990 neon_qfloat_bits (double_to_single (v
));
7991 do_vfp_nsyn_opcode ("fconstd");
7999 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8000 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8003 inst
.operands
[1].reg
= REG_PC
;
8004 inst
.operands
[1].isreg
= 1;
8005 inst
.operands
[1].preind
= 1;
8006 inst
.reloc
.pc_rel
= 1;
8007 inst
.reloc
.type
= (thumb_p
8008 ? BFD_RELOC_ARM_THUMB_OFFSET
8010 ? BFD_RELOC_ARM_HWLITERAL
8011 : BFD_RELOC_ARM_LITERAL
));
8015 /* inst.operands[i] was set up by parse_address. Encode it into an
8016 ARM-format instruction. Reject all forms which cannot be encoded
8017 into a coprocessor load/store instruction. If wb_ok is false,
8018 reject use of writeback; if unind_ok is false, reject use of
8019 unindexed addressing. If reloc_override is not 0, use it instead
8020 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8021 (in which case it is preserved). */
8024 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8026 if (!inst
.operands
[i
].isreg
)
8029 if (! inst
.operands
[0].isvec
)
8031 inst
.error
= _("invalid co-processor operand");
8034 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8038 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8040 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8042 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8044 gas_assert (!inst
.operands
[i
].writeback
);
8047 inst
.error
= _("instruction does not support unindexed addressing");
8050 inst
.instruction
|= inst
.operands
[i
].imm
;
8051 inst
.instruction
|= INDEX_UP
;
8055 if (inst
.operands
[i
].preind
)
8056 inst
.instruction
|= PRE_INDEX
;
8058 if (inst
.operands
[i
].writeback
)
8060 if (inst
.operands
[i
].reg
== REG_PC
)
8062 inst
.error
= _("pc may not be used with write-back");
8067 inst
.error
= _("instruction does not support writeback");
8070 inst
.instruction
|= WRITE_BACK
;
8074 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8075 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8076 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8077 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8080 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8082 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8085 /* Prefer + for zero encoded value. */
8086 if (!inst
.operands
[i
].negative
)
8087 inst
.instruction
|= INDEX_UP
;
8092 /* Functions for instruction encoding, sorted by sub-architecture.
8093 First some generics; their names are taken from the conventional
8094 bit positions for register arguments in ARM format instructions. */
8104 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8111 inst
.instruction
|= inst
.operands
[1].reg
;
8117 inst
.instruction
|= inst
.operands
[0].reg
;
8118 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8124 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8125 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8131 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8132 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8136 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8138 if (ARM_CPU_IS_ANY (cpu_variant
))
8140 as_tsktsk ("%s", msg
);
8143 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8155 unsigned Rn
= inst
.operands
[2].reg
;
8156 /* Enforce restrictions on SWP instruction. */
8157 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8159 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8160 _("Rn must not overlap other operands"));
8162 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8164 if (!check_obsolete (&arm_ext_v8
,
8165 _("swp{b} use is obsoleted for ARMv8 and later"))
8166 && warn_on_deprecated
8167 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8168 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8172 inst
.instruction
|= inst
.operands
[1].reg
;
8173 inst
.instruction
|= Rn
<< 16;
8179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8181 inst
.instruction
|= inst
.operands
[2].reg
;
8187 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8188 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8189 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8190 || inst
.reloc
.exp
.X_add_number
!= 0),
8192 inst
.instruction
|= inst
.operands
[0].reg
;
8193 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8194 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8200 inst
.instruction
|= inst
.operands
[0].imm
;
8206 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8207 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8210 /* ARM instructions, in alphabetical order by function name (except
8211 that wrapper functions appear immediately after the function they
8214 /* This is a pseudo-op of the form "adr rd, label" to be converted
8215 into a relative address of the form "add rd, pc, #label-.-8". */
8220 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8222 /* Frag hacking will turn this into a sub instruction if the offset turns
8223 out to be negative. */
8224 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8225 inst
.reloc
.pc_rel
= 1;
8226 inst
.reloc
.exp
.X_add_number
-= 8;
8229 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8230 into a relative address of the form:
8231 add rd, pc, #low(label-.-8)"
8232 add rd, rd, #high(label-.-8)" */
8237 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8239 /* Frag hacking will turn this into a sub instruction if the offset turns
8240 out to be negative. */
8241 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8242 inst
.reloc
.pc_rel
= 1;
8243 inst
.size
= INSN_SIZE
* 2;
8244 inst
.reloc
.exp
.X_add_number
-= 8;
8250 if (!inst
.operands
[1].present
)
8251 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8253 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8254 encode_arm_shifter_operand (2);
8260 if (inst
.operands
[0].present
)
8261 inst
.instruction
|= inst
.operands
[0].imm
;
8263 inst
.instruction
|= 0xf;
8269 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8270 constraint (msb
> 32, _("bit-field extends past end of register"));
8271 /* The instruction encoding stores the LSB and MSB,
8272 not the LSB and width. */
8273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8274 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8275 inst
.instruction
|= (msb
- 1) << 16;
8283 /* #0 in second position is alternative syntax for bfc, which is
8284 the same instruction but with REG_PC in the Rm field. */
8285 if (!inst
.operands
[1].isreg
)
8286 inst
.operands
[1].reg
= REG_PC
;
8288 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8289 constraint (msb
> 32, _("bit-field extends past end of register"));
8290 /* The instruction encoding stores the LSB and MSB,
8291 not the LSB and width. */
8292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8293 inst
.instruction
|= inst
.operands
[1].reg
;
8294 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8295 inst
.instruction
|= (msb
- 1) << 16;
8301 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8302 _("bit-field extends past end of register"));
8303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8304 inst
.instruction
|= inst
.operands
[1].reg
;
8305 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8306 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8309 /* ARM V5 breakpoint instruction (argument parse)
8310 BKPT <16 bit unsigned immediate>
8311 Instruction is not conditional.
8312 The bit pattern given in insns[] has the COND_ALWAYS condition,
8313 and it is an error if the caller tried to override that. */
8318 /* Top 12 of 16 bits to bits 19:8. */
8319 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8321 /* Bottom 4 of 16 bits to bits 3:0. */
8322 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8326 encode_branch (int default_reloc
)
8328 if (inst
.operands
[0].hasreloc
)
8330 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8331 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8332 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8333 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8334 ? BFD_RELOC_ARM_PLT32
8335 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8338 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8339 inst
.reloc
.pc_rel
= 1;
8346 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8347 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8350 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8357 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8359 if (inst
.cond
== COND_ALWAYS
)
8360 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8362 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8366 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8369 /* ARM V5 branch-link-exchange instruction (argument parse)
8370 BLX <target_addr> ie BLX(1)
8371 BLX{<condition>} <Rm> ie BLX(2)
8372 Unfortunately, there are two different opcodes for this mnemonic.
8373 So, the insns[].value is not used, and the code here zaps values
8374 into inst.instruction.
8375 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8380 if (inst
.operands
[0].isreg
)
8382 /* Arg is a register; the opcode provided by insns[] is correct.
8383 It is not illegal to do "blx pc", just useless. */
8384 if (inst
.operands
[0].reg
== REG_PC
)
8385 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8387 inst
.instruction
|= inst
.operands
[0].reg
;
8391 /* Arg is an address; this instruction cannot be executed
8392 conditionally, and the opcode must be adjusted.
8393 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8394 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8395 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8396 inst
.instruction
= 0xfa000000;
8397 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8404 bfd_boolean want_reloc
;
8406 if (inst
.operands
[0].reg
== REG_PC
)
8407 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8409 inst
.instruction
|= inst
.operands
[0].reg
;
8410 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8411 it is for ARMv4t or earlier. */
8412 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8413 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8417 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8422 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8426 /* ARM v5TEJ. Jump to Jazelle code. */
8431 if (inst
.operands
[0].reg
== REG_PC
)
8432 as_tsktsk (_("use of r15 in bxj is not really useful"));
8434 inst
.instruction
|= inst
.operands
[0].reg
;
8437 /* Co-processor data operation:
8438 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8439 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8443 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8444 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8445 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8446 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8447 inst
.instruction
|= inst
.operands
[4].reg
;
8448 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8454 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8455 encode_arm_shifter_operand (1);
8458 /* Transfer between coprocessor and ARM registers.
8459 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8464 No special properties. */
8466 struct deprecated_coproc_regs_s
8473 arm_feature_set deprecated
;
8474 arm_feature_set obsoleted
;
8475 const char *dep_msg
;
8476 const char *obs_msg
;
8479 #define DEPR_ACCESS_V8 \
8480 N_("This coprocessor register access is deprecated in ARMv8")
8482 /* Table of all deprecated coprocessor registers. */
8483 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8485 {15, 0, 7, 10, 5, /* CP15DMB. */
8486 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8487 DEPR_ACCESS_V8
, NULL
},
8488 {15, 0, 7, 10, 4, /* CP15DSB. */
8489 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8490 DEPR_ACCESS_V8
, NULL
},
8491 {15, 0, 7, 5, 4, /* CP15ISB. */
8492 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8493 DEPR_ACCESS_V8
, NULL
},
8494 {14, 6, 1, 0, 0, /* TEEHBR. */
8495 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8496 DEPR_ACCESS_V8
, NULL
},
8497 {14, 6, 0, 0, 0, /* TEECR. */
8498 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8499 DEPR_ACCESS_V8
, NULL
},
8502 #undef DEPR_ACCESS_V8
8504 static const size_t deprecated_coproc_reg_count
=
8505 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8513 Rd
= inst
.operands
[2].reg
;
8516 if (inst
.instruction
== 0xee000010
8517 || inst
.instruction
== 0xfe000010)
8519 reject_bad_reg (Rd
);
8522 constraint (Rd
== REG_SP
, BAD_SP
);
8527 if (inst
.instruction
== 0xe000010)
8528 constraint (Rd
== REG_PC
, BAD_PC
);
8531 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8533 const struct deprecated_coproc_regs_s
*r
=
8534 deprecated_coproc_regs
+ i
;
8536 if (inst
.operands
[0].reg
== r
->cp
8537 && inst
.operands
[1].imm
== r
->opc1
8538 && inst
.operands
[3].reg
== r
->crn
8539 && inst
.operands
[4].reg
== r
->crm
8540 && inst
.operands
[5].imm
== r
->opc2
)
8542 if (! ARM_CPU_IS_ANY (cpu_variant
)
8543 && warn_on_deprecated
8544 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8545 as_tsktsk ("%s", r
->dep_msg
);
8549 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8550 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8551 inst
.instruction
|= Rd
<< 12;
8552 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8553 inst
.instruction
|= inst
.operands
[4].reg
;
8554 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8557 /* Transfer between coprocessor register and pair of ARM registers.
8558 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8563 Two XScale instructions are special cases of these:
8565 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8566 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8568 Result unpredictable if Rd or Rn is R15. */
8575 Rd
= inst
.operands
[2].reg
;
8576 Rn
= inst
.operands
[3].reg
;
8580 reject_bad_reg (Rd
);
8581 reject_bad_reg (Rn
);
8585 constraint (Rd
== REG_PC
, BAD_PC
);
8586 constraint (Rn
== REG_PC
, BAD_PC
);
8589 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8590 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8591 inst
.instruction
|= Rd
<< 12;
8592 inst
.instruction
|= Rn
<< 16;
8593 inst
.instruction
|= inst
.operands
[4].reg
;
8599 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8600 if (inst
.operands
[1].present
)
8602 inst
.instruction
|= CPSI_MMOD
;
8603 inst
.instruction
|= inst
.operands
[1].imm
;
8610 inst
.instruction
|= inst
.operands
[0].imm
;
8616 unsigned Rd
, Rn
, Rm
;
8618 Rd
= inst
.operands
[0].reg
;
8619 Rn
= (inst
.operands
[1].present
8620 ? inst
.operands
[1].reg
: Rd
);
8621 Rm
= inst
.operands
[2].reg
;
8623 constraint ((Rd
== REG_PC
), BAD_PC
);
8624 constraint ((Rn
== REG_PC
), BAD_PC
);
8625 constraint ((Rm
== REG_PC
), BAD_PC
);
8627 inst
.instruction
|= Rd
<< 16;
8628 inst
.instruction
|= Rn
<< 0;
8629 inst
.instruction
|= Rm
<< 8;
8635 /* There is no IT instruction in ARM mode. We
8636 process it to do the validation as if in
8637 thumb mode, just in case the code gets
8638 assembled for thumb using the unified syntax. */
8643 set_it_insn_type (IT_INSN
);
8644 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8645 now_it
.cc
= inst
.operands
[0].imm
;
8649 /* If there is only one register in the register list,
8650 then return its register number. Otherwise return -1. */
8652 only_one_reg_in_list (int range
)
8654 int i
= ffs (range
) - 1;
8655 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8659 encode_ldmstm(int from_push_pop_mnem
)
8661 int base_reg
= inst
.operands
[0].reg
;
8662 int range
= inst
.operands
[1].imm
;
8665 inst
.instruction
|= base_reg
<< 16;
8666 inst
.instruction
|= range
;
8668 if (inst
.operands
[1].writeback
)
8669 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8671 if (inst
.operands
[0].writeback
)
8673 inst
.instruction
|= WRITE_BACK
;
8674 /* Check for unpredictable uses of writeback. */
8675 if (inst
.instruction
& LOAD_BIT
)
8677 /* Not allowed in LDM type 2. */
8678 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8679 && ((range
& (1 << REG_PC
)) == 0))
8680 as_warn (_("writeback of base register is UNPREDICTABLE"));
8681 /* Only allowed if base reg not in list for other types. */
8682 else if (range
& (1 << base_reg
))
8683 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8687 /* Not allowed for type 2. */
8688 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8689 as_warn (_("writeback of base register is UNPREDICTABLE"));
8690 /* Only allowed if base reg not in list, or first in list. */
8691 else if ((range
& (1 << base_reg
))
8692 && (range
& ((1 << base_reg
) - 1)))
8693 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8697 /* If PUSH/POP has only one register, then use the A2 encoding. */
8698 one_reg
= only_one_reg_in_list (range
);
8699 if (from_push_pop_mnem
&& one_reg
>= 0)
8701 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8703 inst
.instruction
&= A_COND_MASK
;
8704 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8705 inst
.instruction
|= one_reg
<< 12;
8712 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8715 /* ARMv5TE load-consecutive (argument parse)
8724 constraint (inst
.operands
[0].reg
% 2 != 0,
8725 _("first transfer register must be even"));
8726 constraint (inst
.operands
[1].present
8727 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8728 _("can only transfer two consecutive registers"));
8729 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8730 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8732 if (!inst
.operands
[1].present
)
8733 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8735 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8736 register and the first register written; we have to diagnose
8737 overlap between the base and the second register written here. */
8739 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8740 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8741 as_warn (_("base register written back, and overlaps "
8742 "second transfer register"));
8744 if (!(inst
.instruction
& V4_STR_BIT
))
8746 /* For an index-register load, the index register must not overlap the
8747 destination (even if not write-back). */
8748 if (inst
.operands
[2].immisreg
8749 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8750 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8751 as_warn (_("index register overlaps transfer register"));
8753 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8754 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8760 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8761 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8762 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8763 || inst
.operands
[1].negative
8764 /* This can arise if the programmer has written
8766 or if they have mistakenly used a register name as the last
8769 It is very difficult to distinguish between these two cases
8770 because "rX" might actually be a label. ie the register
8771 name has been occluded by a symbol of the same name. So we
8772 just generate a general 'bad addressing mode' type error
8773 message and leave it up to the programmer to discover the
8774 true cause and fix their mistake. */
8775 || (inst
.operands
[1].reg
== REG_PC
),
8778 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8779 || inst
.reloc
.exp
.X_add_number
!= 0,
8780 _("offset must be zero in ARM encoding"));
8782 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8784 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8785 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8786 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8792 constraint (inst
.operands
[0].reg
% 2 != 0,
8793 _("even register required"));
8794 constraint (inst
.operands
[1].present
8795 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8796 _("can only load two consecutive registers"));
8797 /* If op 1 were present and equal to PC, this function wouldn't
8798 have been called in the first place. */
8799 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8802 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8805 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8806 which is not a multiple of four is UNPREDICTABLE. */
8808 check_ldr_r15_aligned (void)
8810 constraint (!(inst
.operands
[1].immisreg
)
8811 && (inst
.operands
[0].reg
== REG_PC
8812 && inst
.operands
[1].reg
== REG_PC
8813 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8814 _("ldr to register 15 must be 4-byte alligned"));
8820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8821 if (!inst
.operands
[1].isreg
)
8822 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8824 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8825 check_ldr_r15_aligned ();
8831 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8833 if (inst
.operands
[1].preind
)
8835 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8836 || inst
.reloc
.exp
.X_add_number
!= 0,
8837 _("this instruction requires a post-indexed address"));
8839 inst
.operands
[1].preind
= 0;
8840 inst
.operands
[1].postind
= 1;
8841 inst
.operands
[1].writeback
= 1;
8843 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8844 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8847 /* Halfword and signed-byte load/store operations. */
8852 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8853 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8854 if (!inst
.operands
[1].isreg
)
8855 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8857 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8863 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8865 if (inst
.operands
[1].preind
)
8867 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8868 || inst
.reloc
.exp
.X_add_number
!= 0,
8869 _("this instruction requires a post-indexed address"));
8871 inst
.operands
[1].preind
= 0;
8872 inst
.operands
[1].postind
= 1;
8873 inst
.operands
[1].writeback
= 1;
8875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8876 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8879 /* Co-processor register load/store.
8880 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8884 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8885 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8886 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8892 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8893 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8894 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8895 && !(inst
.instruction
& 0x00400000))
8896 as_tsktsk (_("Rd and Rm should be different in mla"));
8898 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8899 inst
.instruction
|= inst
.operands
[1].reg
;
8900 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8901 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8908 encode_arm_shifter_operand (1);
8911 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8918 top
= (inst
.instruction
& 0x00400000) != 0;
8919 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8920 _(":lower16: not allowed this instruction"));
8921 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8922 _(":upper16: not allowed instruction"));
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8926 imm
= inst
.reloc
.exp
.X_add_number
;
8927 /* The value is in two pieces: 0:11, 16:19. */
8928 inst
.instruction
|= (imm
& 0x00000fff);
8929 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8934 do_vfp_nsyn_mrs (void)
8936 if (inst
.operands
[0].isvec
)
8938 if (inst
.operands
[1].reg
!= 1)
8939 first_error (_("operand 1 must be FPSCR"));
8940 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8941 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8942 do_vfp_nsyn_opcode ("fmstat");
8944 else if (inst
.operands
[1].isvec
)
8945 do_vfp_nsyn_opcode ("fmrx");
8953 do_vfp_nsyn_msr (void)
8955 if (inst
.operands
[0].isvec
)
8956 do_vfp_nsyn_opcode ("fmxr");
8966 unsigned Rt
= inst
.operands
[0].reg
;
8968 if (thumb_mode
&& Rt
== REG_SP
)
8970 inst
.error
= BAD_SP
;
8974 /* APSR_ sets isvec. All other refs to PC are illegal. */
8975 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8977 inst
.error
= BAD_PC
;
8981 /* If we get through parsing the register name, we just insert the number
8982 generated into the instruction without further validation. */
8983 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8984 inst
.instruction
|= (Rt
<< 12);
8990 unsigned Rt
= inst
.operands
[1].reg
;
8993 reject_bad_reg (Rt
);
8994 else if (Rt
== REG_PC
)
8996 inst
.error
= BAD_PC
;
9000 /* If we get through parsing the register name, we just insert the number
9001 generated into the instruction without further validation. */
9002 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9003 inst
.instruction
|= (Rt
<< 12);
9011 if (do_vfp_nsyn_mrs () == SUCCESS
)
9014 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9017 if (inst
.operands
[1].isreg
)
9019 br
= inst
.operands
[1].reg
;
9020 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9021 as_bad (_("bad register for mrs"));
9025 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9026 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9028 _("'APSR', 'CPSR' or 'SPSR' expected"));
9029 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9032 inst
.instruction
|= br
;
9035 /* Two possible forms:
9036 "{C|S}PSR_<field>, Rm",
9037 "{C|S}PSR_f, #expression". */
9042 if (do_vfp_nsyn_msr () == SUCCESS
)
9045 inst
.instruction
|= inst
.operands
[0].imm
;
9046 if (inst
.operands
[1].isreg
)
9047 inst
.instruction
|= inst
.operands
[1].reg
;
9050 inst
.instruction
|= INST_IMMEDIATE
;
9051 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9052 inst
.reloc
.pc_rel
= 0;
9059 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9061 if (!inst
.operands
[2].present
)
9062 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9063 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9064 inst
.instruction
|= inst
.operands
[1].reg
;
9065 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9067 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9068 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9069 as_tsktsk (_("Rd and Rm should be different in mul"));
9072 /* Long Multiply Parser
9073 UMULL RdLo, RdHi, Rm, Rs
9074 SMULL RdLo, RdHi, Rm, Rs
9075 UMLAL RdLo, RdHi, Rm, Rs
9076 SMLAL RdLo, RdHi, Rm, Rs. */
9081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9082 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9083 inst
.instruction
|= inst
.operands
[2].reg
;
9084 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9086 /* rdhi and rdlo must be different. */
9087 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9088 as_tsktsk (_("rdhi and rdlo must be different"));
9090 /* rdhi, rdlo and rm must all be different before armv6. */
9091 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9092 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9093 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9094 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9100 if (inst
.operands
[0].present
9101 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9103 /* Architectural NOP hints are CPSR sets with no bits selected. */
9104 inst
.instruction
&= 0xf0000000;
9105 inst
.instruction
|= 0x0320f000;
9106 if (inst
.operands
[0].present
)
9107 inst
.instruction
|= inst
.operands
[0].imm
;
9111 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9112 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9113 Condition defaults to COND_ALWAYS.
9114 Error if Rd, Rn or Rm are R15. */
9119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9120 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9121 inst
.instruction
|= inst
.operands
[2].reg
;
9122 if (inst
.operands
[3].present
)
9123 encode_arm_shift (3);
9126 /* ARM V6 PKHTB (Argument Parse). */
9131 if (!inst
.operands
[3].present
)
9133 /* If the shift specifier is omitted, turn the instruction
9134 into pkhbt rd, rm, rn. */
9135 inst
.instruction
&= 0xfff00010;
9136 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9137 inst
.instruction
|= inst
.operands
[1].reg
;
9138 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9142 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9143 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9144 inst
.instruction
|= inst
.operands
[2].reg
;
9145 encode_arm_shift (3);
9149 /* ARMv5TE: Preload-Cache
9150 MP Extensions: Preload for write
9154 Syntactically, like LDR with B=1, W=0, L=1. */
9159 constraint (!inst
.operands
[0].isreg
,
9160 _("'[' expected after PLD mnemonic"));
9161 constraint (inst
.operands
[0].postind
,
9162 _("post-indexed expression used in preload instruction"));
9163 constraint (inst
.operands
[0].writeback
,
9164 _("writeback used in preload instruction"));
9165 constraint (!inst
.operands
[0].preind
,
9166 _("unindexed addressing used in preload instruction"));
9167 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9170 /* ARMv7: PLI <addr_mode> */
9174 constraint (!inst
.operands
[0].isreg
,
9175 _("'[' expected after PLI mnemonic"));
9176 constraint (inst
.operands
[0].postind
,
9177 _("post-indexed expression used in preload instruction"));
9178 constraint (inst
.operands
[0].writeback
,
9179 _("writeback used in preload instruction"));
9180 constraint (!inst
.operands
[0].preind
,
9181 _("unindexed addressing used in preload instruction"));
9182 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9183 inst
.instruction
&= ~PRE_INDEX
;
9189 constraint (inst
.operands
[0].writeback
,
9190 _("push/pop do not support {reglist}^"));
9191 inst
.operands
[1] = inst
.operands
[0];
9192 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9193 inst
.operands
[0].isreg
= 1;
9194 inst
.operands
[0].writeback
= 1;
9195 inst
.operands
[0].reg
= REG_SP
;
9196 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9199 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9200 word at the specified address and the following word
9202 Unconditionally executed.
9203 Error if Rn is R15. */
9208 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9209 if (inst
.operands
[0].writeback
)
9210 inst
.instruction
|= WRITE_BACK
;
9213 /* ARM V6 ssat (argument parse). */
9218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9219 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9220 inst
.instruction
|= inst
.operands
[2].reg
;
9222 if (inst
.operands
[3].present
)
9223 encode_arm_shift (3);
9226 /* ARM V6 usat (argument parse). */
9231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9232 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9233 inst
.instruction
|= inst
.operands
[2].reg
;
9235 if (inst
.operands
[3].present
)
9236 encode_arm_shift (3);
9239 /* ARM V6 ssat16 (argument parse). */
9244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9245 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9246 inst
.instruction
|= inst
.operands
[2].reg
;
9252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9253 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9254 inst
.instruction
|= inst
.operands
[2].reg
;
9257 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9258 preserving the other bits.
9260 setend <endian_specifier>, where <endian_specifier> is either
9266 if (warn_on_deprecated
9267 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9268 as_tsktsk (_("setend use is deprecated for ARMv8"));
9270 if (inst
.operands
[0].imm
)
9271 inst
.instruction
|= 0x200;
9277 unsigned int Rm
= (inst
.operands
[1].present
9278 ? inst
.operands
[1].reg
9279 : inst
.operands
[0].reg
);
9281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9282 inst
.instruction
|= Rm
;
9283 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9285 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9286 inst
.instruction
|= SHIFT_BY_REG
;
9287 /* PR 12854: Error on extraneous shifts. */
9288 constraint (inst
.operands
[2].shifted
,
9289 _("extraneous shift as part of operand to shift insn"));
9292 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9298 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9299 inst
.reloc
.pc_rel
= 0;
9305 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9306 inst
.reloc
.pc_rel
= 0;
9312 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9313 inst
.reloc
.pc_rel
= 0;
9319 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9320 _("selected processor does not support SETPAN instruction"));
9322 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9328 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9329 _("selected processor does not support SETPAN instruction"));
9331 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9334 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9335 SMLAxy{cond} Rd,Rm,Rs,Rn
9336 SMLAWy{cond} Rd,Rm,Rs,Rn
9337 Error if any register is R15. */
9342 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9343 inst
.instruction
|= inst
.operands
[1].reg
;
9344 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9345 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9348 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9349 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9350 Error if any register is R15.
9351 Warning if Rdlo == Rdhi. */
9356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9357 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9358 inst
.instruction
|= inst
.operands
[2].reg
;
9359 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9361 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9362 as_tsktsk (_("rdhi and rdlo must be different"));
9365 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9366 SMULxy{cond} Rd,Rm,Rs
9367 Error if any register is R15. */
9372 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9373 inst
.instruction
|= inst
.operands
[1].reg
;
9374 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9377 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9378 the same for both ARM and Thumb-2. */
9385 if (inst
.operands
[0].present
)
9387 reg
= inst
.operands
[0].reg
;
9388 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9393 inst
.instruction
|= reg
<< 16;
9394 inst
.instruction
|= inst
.operands
[1].imm
;
9395 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9396 inst
.instruction
|= WRITE_BACK
;
9399 /* ARM V6 strex (argument parse). */
9404 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9405 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9406 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9407 || inst
.operands
[2].negative
9408 /* See comment in do_ldrex(). */
9409 || (inst
.operands
[2].reg
== REG_PC
),
9412 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9413 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9415 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9416 || inst
.reloc
.exp
.X_add_number
!= 0,
9417 _("offset must be zero in ARM encoding"));
9419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9420 inst
.instruction
|= inst
.operands
[1].reg
;
9421 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9422 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9428 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9429 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9430 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9431 || inst
.operands
[2].negative
,
9434 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9435 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9443 constraint (inst
.operands
[1].reg
% 2 != 0,
9444 _("even register required"));
9445 constraint (inst
.operands
[2].present
9446 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9447 _("can only store two consecutive registers"));
9448 /* If op 2 were present and equal to PC, this function wouldn't
9449 have been called in the first place. */
9450 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9452 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9453 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9454 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9458 inst
.instruction
|= inst
.operands
[1].reg
;
9459 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9466 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9467 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9475 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9476 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9481 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9482 extends it to 32-bits, and adds the result to a value in another
9483 register. You can specify a rotation by 0, 8, 16, or 24 bits
9484 before extracting the 16-bit value.
9485 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9486 Condition defaults to COND_ALWAYS.
9487 Error if any register uses R15. */
9492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9493 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9494 inst
.instruction
|= inst
.operands
[2].reg
;
9495 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9500 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9501 Condition defaults to COND_ALWAYS.
9502 Error if any register uses R15. */
9507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9508 inst
.instruction
|= inst
.operands
[1].reg
;
9509 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9512 /* VFP instructions. In a logical order: SP variant first, monad
9513 before dyad, arithmetic then move then load/store. */
9516 do_vfp_sp_monadic (void)
9518 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9519 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9523 do_vfp_sp_dyadic (void)
9525 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9526 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9527 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9531 do_vfp_sp_compare_z (void)
9533 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9537 do_vfp_dp_sp_cvt (void)
9539 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9540 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9544 do_vfp_sp_dp_cvt (void)
9546 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9547 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9551 do_vfp_reg_from_sp (void)
9553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9554 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9558 do_vfp_reg2_from_sp2 (void)
9560 constraint (inst
.operands
[2].imm
!= 2,
9561 _("only two consecutive VFP SP registers allowed here"));
9562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9563 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9564 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9568 do_vfp_sp_from_reg (void)
9570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9571 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9575 do_vfp_sp2_from_reg2 (void)
9577 constraint (inst
.operands
[0].imm
!= 2,
9578 _("only two consecutive VFP SP registers allowed here"));
9579 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9580 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9581 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9585 do_vfp_sp_ldst (void)
9587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9588 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9592 do_vfp_dp_ldst (void)
9594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9595 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9600 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9602 if (inst
.operands
[0].writeback
)
9603 inst
.instruction
|= WRITE_BACK
;
9605 constraint (ldstm_type
!= VFP_LDSTMIA
,
9606 _("this addressing mode requires base-register writeback"));
9607 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9608 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9609 inst
.instruction
|= inst
.operands
[1].imm
;
9613 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9617 if (inst
.operands
[0].writeback
)
9618 inst
.instruction
|= WRITE_BACK
;
9620 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9621 _("this addressing mode requires base-register writeback"));
9623 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9624 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9626 count
= inst
.operands
[1].imm
<< 1;
9627 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9630 inst
.instruction
|= count
;
9634 do_vfp_sp_ldstmia (void)
9636 vfp_sp_ldstm (VFP_LDSTMIA
);
9640 do_vfp_sp_ldstmdb (void)
9642 vfp_sp_ldstm (VFP_LDSTMDB
);
9646 do_vfp_dp_ldstmia (void)
9648 vfp_dp_ldstm (VFP_LDSTMIA
);
9652 do_vfp_dp_ldstmdb (void)
9654 vfp_dp_ldstm (VFP_LDSTMDB
);
9658 do_vfp_xp_ldstmia (void)
9660 vfp_dp_ldstm (VFP_LDSTMIAX
);
9664 do_vfp_xp_ldstmdb (void)
9666 vfp_dp_ldstm (VFP_LDSTMDBX
);
9670 do_vfp_dp_rd_rm (void)
9672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9673 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9677 do_vfp_dp_rn_rd (void)
9679 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9680 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9684 do_vfp_dp_rd_rn (void)
9686 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9691 do_vfp_dp_rd_rn_rm (void)
9693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9695 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9701 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9705 do_vfp_dp_rm_rd_rn (void)
9707 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9708 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9709 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9712 /* VFPv3 instructions. */
9714 do_vfp_sp_const (void)
9716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9717 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9718 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9722 do_vfp_dp_const (void)
9724 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9725 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9726 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9730 vfp_conv (int srcsize
)
9732 int immbits
= srcsize
- inst
.operands
[1].imm
;
9734 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9736 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9737 i.e. immbits must be in range 0 - 16. */
9738 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9741 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9743 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9744 i.e. immbits must be in range 0 - 31. */
9745 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9749 inst
.instruction
|= (immbits
& 1) << 5;
9750 inst
.instruction
|= (immbits
>> 1);
9754 do_vfp_sp_conv_16 (void)
9756 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9761 do_vfp_dp_conv_16 (void)
9763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9768 do_vfp_sp_conv_32 (void)
9770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9775 do_vfp_dp_conv_32 (void)
9777 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9781 /* FPA instructions. Also in a logical order. */
9786 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9787 inst
.instruction
|= inst
.operands
[1].reg
;
9791 do_fpa_ldmstm (void)
9793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9794 switch (inst
.operands
[1].imm
)
9796 case 1: inst
.instruction
|= CP_T_X
; break;
9797 case 2: inst
.instruction
|= CP_T_Y
; break;
9798 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9803 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9805 /* The instruction specified "ea" or "fd", so we can only accept
9806 [Rn]{!}. The instruction does not really support stacking or
9807 unstacking, so we have to emulate these by setting appropriate
9808 bits and offsets. */
9809 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9810 || inst
.reloc
.exp
.X_add_number
!= 0,
9811 _("this instruction does not support indexing"));
9813 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9814 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9816 if (!(inst
.instruction
& INDEX_UP
))
9817 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9819 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9821 inst
.operands
[2].preind
= 0;
9822 inst
.operands
[2].postind
= 1;
9826 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9829 /* iWMMXt instructions: strictly in alphabetical order. */
9832 do_iwmmxt_tandorc (void)
9834 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9838 do_iwmmxt_textrc (void)
9840 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9841 inst
.instruction
|= inst
.operands
[1].imm
;
9845 do_iwmmxt_textrm (void)
9847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9848 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9849 inst
.instruction
|= inst
.operands
[2].imm
;
9853 do_iwmmxt_tinsr (void)
9855 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9856 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9857 inst
.instruction
|= inst
.operands
[2].imm
;
9861 do_iwmmxt_tmia (void)
9863 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9864 inst
.instruction
|= inst
.operands
[1].reg
;
9865 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9869 do_iwmmxt_waligni (void)
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9873 inst
.instruction
|= inst
.operands
[2].reg
;
9874 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9878 do_iwmmxt_wmerge (void)
9880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9882 inst
.instruction
|= inst
.operands
[2].reg
;
9883 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9887 do_iwmmxt_wmov (void)
9889 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9891 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9892 inst
.instruction
|= inst
.operands
[1].reg
;
9896 do_iwmmxt_wldstbh (void)
9899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9901 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9903 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9904 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9908 do_iwmmxt_wldstw (void)
9910 /* RIWR_RIWC clears .isreg for a control register. */
9911 if (!inst
.operands
[0].isreg
)
9913 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9914 inst
.instruction
|= 0xf0000000;
9917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9918 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9922 do_iwmmxt_wldstd (void)
9924 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9925 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9926 && inst
.operands
[1].immisreg
)
9928 inst
.instruction
&= ~0x1a000ff;
9929 inst
.instruction
|= (0xfU
<< 28);
9930 if (inst
.operands
[1].preind
)
9931 inst
.instruction
|= PRE_INDEX
;
9932 if (!inst
.operands
[1].negative
)
9933 inst
.instruction
|= INDEX_UP
;
9934 if (inst
.operands
[1].writeback
)
9935 inst
.instruction
|= WRITE_BACK
;
9936 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9937 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9938 inst
.instruction
|= inst
.operands
[1].imm
;
9941 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9945 do_iwmmxt_wshufh (void)
9947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9948 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9949 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9950 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9954 do_iwmmxt_wzero (void)
9956 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9957 inst
.instruction
|= inst
.operands
[0].reg
;
9958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9959 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9963 do_iwmmxt_wrwrwr_or_imm5 (void)
9965 if (inst
.operands
[2].isreg
)
9968 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9969 _("immediate operand requires iWMMXt2"));
9971 if (inst
.operands
[2].imm
== 0)
9973 switch ((inst
.instruction
>> 20) & 0xf)
9979 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9980 inst
.operands
[2].imm
= 16;
9981 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9987 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9988 inst
.operands
[2].imm
= 32;
9989 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9996 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9998 wrn
= (inst
.instruction
>> 16) & 0xf;
9999 inst
.instruction
&= 0xff0fff0f;
10000 inst
.instruction
|= wrn
;
10001 /* Bail out here; the instruction is now assembled. */
10006 /* Map 32 -> 0, etc. */
10007 inst
.operands
[2].imm
&= 0x1f;
10008 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10012 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10013 operations first, then control, shift, and load/store. */
10015 /* Insns like "foo X,Y,Z". */
10018 do_mav_triple (void)
10020 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10021 inst
.instruction
|= inst
.operands
[1].reg
;
10022 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10025 /* Insns like "foo W,X,Y,Z".
10026 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10032 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10033 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10034 inst
.instruction
|= inst
.operands
[3].reg
;
10037 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10039 do_mav_dspsc (void)
10041 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10044 /* Maverick shift immediate instructions.
10045 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10046 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10049 do_mav_shift (void)
10051 int imm
= inst
.operands
[2].imm
;
10053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10054 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10056 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10057 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10058 Bit 4 should be 0. */
10059 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10061 inst
.instruction
|= imm
;
10064 /* XScale instructions. Also sorted arithmetic before move. */
10066 /* Xscale multiply-accumulate (argument parse)
10069 MIAxycc acc0,Rm,Rs. */
10074 inst
.instruction
|= inst
.operands
[1].reg
;
10075 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10078 /* Xscale move-accumulator-register (argument parse)
10080 MARcc acc0,RdLo,RdHi. */
10085 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10086 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10089 /* Xscale move-register-accumulator (argument parse)
10091 MRAcc RdLo,RdHi,acc0. */
10096 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10098 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10101 /* Encoding functions relevant only to Thumb. */
10103 /* inst.operands[i] is a shifted-register operand; encode
10104 it into inst.instruction in the format used by Thumb32. */
10107 encode_thumb32_shifted_operand (int i
)
10109 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10110 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10112 constraint (inst
.operands
[i
].immisreg
,
10113 _("shift by register not allowed in thumb mode"));
10114 inst
.instruction
|= inst
.operands
[i
].reg
;
10115 if (shift
== SHIFT_RRX
)
10116 inst
.instruction
|= SHIFT_ROR
<< 4;
10119 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10120 _("expression too complex"));
10122 constraint (value
> 32
10123 || (value
== 32 && (shift
== SHIFT_LSL
10124 || shift
== SHIFT_ROR
)),
10125 _("shift expression is too large"));
10129 else if (value
== 32)
10132 inst
.instruction
|= shift
<< 4;
10133 inst
.instruction
|= (value
& 0x1c) << 10;
10134 inst
.instruction
|= (value
& 0x03) << 6;
10139 /* inst.operands[i] was set up by parse_address. Encode it into a
10140 Thumb32 format load or store instruction. Reject forms that cannot
10141 be used with such instructions. If is_t is true, reject forms that
10142 cannot be used with a T instruction; if is_d is true, reject forms
10143 that cannot be used with a D instruction. If it is a store insn,
10144 reject PC in Rn. */
10147 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10149 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10151 constraint (!inst
.operands
[i
].isreg
,
10152 _("Instruction does not support =N addresses"));
10154 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10155 if (inst
.operands
[i
].immisreg
)
10157 constraint (is_pc
, BAD_PC_ADDRESSING
);
10158 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10159 constraint (inst
.operands
[i
].negative
,
10160 _("Thumb does not support negative register indexing"));
10161 constraint (inst
.operands
[i
].postind
,
10162 _("Thumb does not support register post-indexing"));
10163 constraint (inst
.operands
[i
].writeback
,
10164 _("Thumb does not support register indexing with writeback"));
10165 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10166 _("Thumb supports only LSL in shifted register indexing"));
10168 inst
.instruction
|= inst
.operands
[i
].imm
;
10169 if (inst
.operands
[i
].shifted
)
10171 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10172 _("expression too complex"));
10173 constraint (inst
.reloc
.exp
.X_add_number
< 0
10174 || inst
.reloc
.exp
.X_add_number
> 3,
10175 _("shift out of range"));
10176 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10178 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10180 else if (inst
.operands
[i
].preind
)
10182 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10183 constraint (is_t
&& inst
.operands
[i
].writeback
,
10184 _("cannot use writeback with this instruction"));
10185 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10186 BAD_PC_ADDRESSING
);
10190 inst
.instruction
|= 0x01000000;
10191 if (inst
.operands
[i
].writeback
)
10192 inst
.instruction
|= 0x00200000;
10196 inst
.instruction
|= 0x00000c00;
10197 if (inst
.operands
[i
].writeback
)
10198 inst
.instruction
|= 0x00000100;
10200 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10202 else if (inst
.operands
[i
].postind
)
10204 gas_assert (inst
.operands
[i
].writeback
);
10205 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10206 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10209 inst
.instruction
|= 0x00200000;
10211 inst
.instruction
|= 0x00000900;
10212 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10214 else /* unindexed - only for coprocessor */
10215 inst
.error
= _("instruction does not accept unindexed addressing");
10218 /* Table of Thumb instructions which exist in both 16- and 32-bit
10219 encodings (the latter only in post-V6T2 cores). The index is the
10220 value used in the insns table below. When there is more than one
10221 possible 16-bit encoding for the instruction, this table always
10223 Also contains several pseudo-instructions used during relaxation. */
10224 #define T16_32_TAB \
10225 X(_adc, 4140, eb400000), \
10226 X(_adcs, 4140, eb500000), \
10227 X(_add, 1c00, eb000000), \
10228 X(_adds, 1c00, eb100000), \
10229 X(_addi, 0000, f1000000), \
10230 X(_addis, 0000, f1100000), \
10231 X(_add_pc,000f, f20f0000), \
10232 X(_add_sp,000d, f10d0000), \
10233 X(_adr, 000f, f20f0000), \
10234 X(_and, 4000, ea000000), \
10235 X(_ands, 4000, ea100000), \
10236 X(_asr, 1000, fa40f000), \
10237 X(_asrs, 1000, fa50f000), \
10238 X(_b, e000, f000b000), \
10239 X(_bcond, d000, f0008000), \
10240 X(_bic, 4380, ea200000), \
10241 X(_bics, 4380, ea300000), \
10242 X(_cmn, 42c0, eb100f00), \
10243 X(_cmp, 2800, ebb00f00), \
10244 X(_cpsie, b660, f3af8400), \
10245 X(_cpsid, b670, f3af8600), \
10246 X(_cpy, 4600, ea4f0000), \
10247 X(_dec_sp,80dd, f1ad0d00), \
10248 X(_eor, 4040, ea800000), \
10249 X(_eors, 4040, ea900000), \
10250 X(_inc_sp,00dd, f10d0d00), \
10251 X(_ldmia, c800, e8900000), \
10252 X(_ldr, 6800, f8500000), \
10253 X(_ldrb, 7800, f8100000), \
10254 X(_ldrh, 8800, f8300000), \
10255 X(_ldrsb, 5600, f9100000), \
10256 X(_ldrsh, 5e00, f9300000), \
10257 X(_ldr_pc,4800, f85f0000), \
10258 X(_ldr_pc2,4800, f85f0000), \
10259 X(_ldr_sp,9800, f85d0000), \
10260 X(_lsl, 0000, fa00f000), \
10261 X(_lsls, 0000, fa10f000), \
10262 X(_lsr, 0800, fa20f000), \
10263 X(_lsrs, 0800, fa30f000), \
10264 X(_mov, 2000, ea4f0000), \
10265 X(_movs, 2000, ea5f0000), \
10266 X(_mul, 4340, fb00f000), \
10267 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10268 X(_mvn, 43c0, ea6f0000), \
10269 X(_mvns, 43c0, ea7f0000), \
10270 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10271 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10272 X(_orr, 4300, ea400000), \
10273 X(_orrs, 4300, ea500000), \
10274 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10275 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10276 X(_rev, ba00, fa90f080), \
10277 X(_rev16, ba40, fa90f090), \
10278 X(_revsh, bac0, fa90f0b0), \
10279 X(_ror, 41c0, fa60f000), \
10280 X(_rors, 41c0, fa70f000), \
10281 X(_sbc, 4180, eb600000), \
10282 X(_sbcs, 4180, eb700000), \
10283 X(_stmia, c000, e8800000), \
10284 X(_str, 6000, f8400000), \
10285 X(_strb, 7000, f8000000), \
10286 X(_strh, 8000, f8200000), \
10287 X(_str_sp,9000, f84d0000), \
10288 X(_sub, 1e00, eba00000), \
10289 X(_subs, 1e00, ebb00000), \
10290 X(_subi, 8000, f1a00000), \
10291 X(_subis, 8000, f1b00000), \
10292 X(_sxtb, b240, fa4ff080), \
10293 X(_sxth, b200, fa0ff080), \
10294 X(_tst, 4200, ea100f00), \
10295 X(_uxtb, b2c0, fa5ff080), \
10296 X(_uxth, b280, fa1ff080), \
10297 X(_nop, bf00, f3af8000), \
10298 X(_yield, bf10, f3af8001), \
10299 X(_wfe, bf20, f3af8002), \
10300 X(_wfi, bf30, f3af8003), \
10301 X(_sev, bf40, f3af8004), \
10302 X(_sevl, bf50, f3af8005), \
10303 X(_udf, de00, f7f0a000)
10305 /* To catch errors in encoding functions, the codes are all offset by
10306 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10307 as 16-bit instructions. */
10308 #define X(a,b,c) T_MNEM##a
10309 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10312 #define X(a,b,c) 0x##b
10313 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10314 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10317 #define X(a,b,c) 0x##c
10318 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10319 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10320 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10324 /* Thumb instruction encoders, in alphabetical order. */
10326 /* ADDW or SUBW. */
10329 do_t_add_sub_w (void)
10333 Rd
= inst
.operands
[0].reg
;
10334 Rn
= inst
.operands
[1].reg
;
10336 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10337 is the SP-{plus,minus}-immediate form of the instruction. */
10339 constraint (Rd
== REG_PC
, BAD_PC
);
10341 reject_bad_reg (Rd
);
10343 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10344 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10347 /* Parse an add or subtract instruction. We get here with inst.instruction
10348 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10351 do_t_add_sub (void)
10355 Rd
= inst
.operands
[0].reg
;
10356 Rs
= (inst
.operands
[1].present
10357 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10358 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10361 set_it_insn_type_last ();
10363 if (unified_syntax
)
10366 bfd_boolean narrow
;
10369 flags
= (inst
.instruction
== T_MNEM_adds
10370 || inst
.instruction
== T_MNEM_subs
);
10372 narrow
= !in_it_block ();
10374 narrow
= in_it_block ();
10375 if (!inst
.operands
[2].isreg
)
10379 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10381 add
= (inst
.instruction
== T_MNEM_add
10382 || inst
.instruction
== T_MNEM_adds
);
10384 if (inst
.size_req
!= 4)
10386 /* Attempt to use a narrow opcode, with relaxation if
10388 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10389 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10390 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10391 opcode
= T_MNEM_add_sp
;
10392 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10393 opcode
= T_MNEM_add_pc
;
10394 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10397 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10399 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10403 inst
.instruction
= THUMB_OP16(opcode
);
10404 inst
.instruction
|= (Rd
<< 4) | Rs
;
10405 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10406 if (inst
.size_req
!= 2)
10407 inst
.relax
= opcode
;
10410 constraint (inst
.size_req
== 2, BAD_HIREG
);
10412 if (inst
.size_req
== 4
10413 || (inst
.size_req
!= 2 && !opcode
))
10417 constraint (add
, BAD_PC
);
10418 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10419 _("only SUBS PC, LR, #const allowed"));
10420 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10421 _("expression too complex"));
10422 constraint (inst
.reloc
.exp
.X_add_number
< 0
10423 || inst
.reloc
.exp
.X_add_number
> 0xff,
10424 _("immediate value out of range"));
10425 inst
.instruction
= T2_SUBS_PC_LR
10426 | inst
.reloc
.exp
.X_add_number
;
10427 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10430 else if (Rs
== REG_PC
)
10432 /* Always use addw/subw. */
10433 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10434 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10438 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10439 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10442 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10444 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10446 inst
.instruction
|= Rd
<< 8;
10447 inst
.instruction
|= Rs
<< 16;
10452 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10453 unsigned int shift
= inst
.operands
[2].shift_kind
;
10455 Rn
= inst
.operands
[2].reg
;
10456 /* See if we can do this with a 16-bit instruction. */
10457 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10459 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10464 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10465 || inst
.instruction
== T_MNEM_add
)
10467 : T_OPCODE_SUB_R3
);
10468 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10472 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10474 /* Thumb-1 cores (except v6-M) require at least one high
10475 register in a narrow non flag setting add. */
10476 if (Rd
> 7 || Rn
> 7
10477 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10478 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10485 inst
.instruction
= T_OPCODE_ADD_HI
;
10486 inst
.instruction
|= (Rd
& 8) << 4;
10487 inst
.instruction
|= (Rd
& 7);
10488 inst
.instruction
|= Rn
<< 3;
10494 constraint (Rd
== REG_PC
, BAD_PC
);
10495 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10496 constraint (Rs
== REG_PC
, BAD_PC
);
10497 reject_bad_reg (Rn
);
10499 /* If we get here, it can't be done in 16 bits. */
10500 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10501 _("shift must be constant"));
10502 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10503 inst
.instruction
|= Rd
<< 8;
10504 inst
.instruction
|= Rs
<< 16;
10505 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10506 _("shift value over 3 not allowed in thumb mode"));
10507 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10508 _("only LSL shift allowed in thumb mode"));
10509 encode_thumb32_shifted_operand (2);
10514 constraint (inst
.instruction
== T_MNEM_adds
10515 || inst
.instruction
== T_MNEM_subs
,
10518 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10520 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10521 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10524 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10525 ? 0x0000 : 0x8000);
10526 inst
.instruction
|= (Rd
<< 4) | Rs
;
10527 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10531 Rn
= inst
.operands
[2].reg
;
10532 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10534 /* We now have Rd, Rs, and Rn set to registers. */
10535 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10537 /* Can't do this for SUB. */
10538 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10539 inst
.instruction
= T_OPCODE_ADD_HI
;
10540 inst
.instruction
|= (Rd
& 8) << 4;
10541 inst
.instruction
|= (Rd
& 7);
10543 inst
.instruction
|= Rn
<< 3;
10545 inst
.instruction
|= Rs
<< 3;
10547 constraint (1, _("dest must overlap one source register"));
10551 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10552 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10553 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10563 Rd
= inst
.operands
[0].reg
;
10564 reject_bad_reg (Rd
);
10566 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10568 /* Defer to section relaxation. */
10569 inst
.relax
= inst
.instruction
;
10570 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10571 inst
.instruction
|= Rd
<< 4;
10573 else if (unified_syntax
&& inst
.size_req
!= 2)
10575 /* Generate a 32-bit opcode. */
10576 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10577 inst
.instruction
|= Rd
<< 8;
10578 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10579 inst
.reloc
.pc_rel
= 1;
10583 /* Generate a 16-bit opcode. */
10584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10585 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10586 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10587 inst
.reloc
.pc_rel
= 1;
10589 inst
.instruction
|= Rd
<< 4;
10593 /* Arithmetic instructions for which there is just one 16-bit
10594 instruction encoding, and it allows only two low registers.
10595 For maximal compatibility with ARM syntax, we allow three register
10596 operands even when Thumb-32 instructions are not available, as long
10597 as the first two are identical. For instance, both "sbc r0,r1" and
10598 "sbc r0,r0,r1" are allowed. */
10604 Rd
= inst
.operands
[0].reg
;
10605 Rs
= (inst
.operands
[1].present
10606 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10607 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10608 Rn
= inst
.operands
[2].reg
;
10610 reject_bad_reg (Rd
);
10611 reject_bad_reg (Rs
);
10612 if (inst
.operands
[2].isreg
)
10613 reject_bad_reg (Rn
);
10615 if (unified_syntax
)
10617 if (!inst
.operands
[2].isreg
)
10619 /* For an immediate, we always generate a 32-bit opcode;
10620 section relaxation will shrink it later if possible. */
10621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10622 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10623 inst
.instruction
|= Rd
<< 8;
10624 inst
.instruction
|= Rs
<< 16;
10625 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10629 bfd_boolean narrow
;
10631 /* See if we can do this with a 16-bit instruction. */
10632 if (THUMB_SETS_FLAGS (inst
.instruction
))
10633 narrow
= !in_it_block ();
10635 narrow
= in_it_block ();
10637 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10639 if (inst
.operands
[2].shifted
)
10641 if (inst
.size_req
== 4)
10647 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10648 inst
.instruction
|= Rd
;
10649 inst
.instruction
|= Rn
<< 3;
10653 /* If we get here, it can't be done in 16 bits. */
10654 constraint (inst
.operands
[2].shifted
10655 && inst
.operands
[2].immisreg
,
10656 _("shift must be constant"));
10657 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10658 inst
.instruction
|= Rd
<< 8;
10659 inst
.instruction
|= Rs
<< 16;
10660 encode_thumb32_shifted_operand (2);
10665 /* On its face this is a lie - the instruction does set the
10666 flags. However, the only supported mnemonic in this mode
10667 says it doesn't. */
10668 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10670 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10671 _("unshifted register required"));
10672 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10673 constraint (Rd
!= Rs
,
10674 _("dest and source1 must be the same register"));
10676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10677 inst
.instruction
|= Rd
;
10678 inst
.instruction
|= Rn
<< 3;
10682 /* Similarly, but for instructions where the arithmetic operation is
10683 commutative, so we can allow either of them to be different from
10684 the destination operand in a 16-bit instruction. For instance, all
10685 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10692 Rd
= inst
.operands
[0].reg
;
10693 Rs
= (inst
.operands
[1].present
10694 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10695 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10696 Rn
= inst
.operands
[2].reg
;
10698 reject_bad_reg (Rd
);
10699 reject_bad_reg (Rs
);
10700 if (inst
.operands
[2].isreg
)
10701 reject_bad_reg (Rn
);
10703 if (unified_syntax
)
10705 if (!inst
.operands
[2].isreg
)
10707 /* For an immediate, we always generate a 32-bit opcode;
10708 section relaxation will shrink it later if possible. */
10709 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10710 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10711 inst
.instruction
|= Rd
<< 8;
10712 inst
.instruction
|= Rs
<< 16;
10713 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10717 bfd_boolean narrow
;
10719 /* See if we can do this with a 16-bit instruction. */
10720 if (THUMB_SETS_FLAGS (inst
.instruction
))
10721 narrow
= !in_it_block ();
10723 narrow
= in_it_block ();
10725 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10727 if (inst
.operands
[2].shifted
)
10729 if (inst
.size_req
== 4)
10736 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10737 inst
.instruction
|= Rd
;
10738 inst
.instruction
|= Rn
<< 3;
10743 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10744 inst
.instruction
|= Rd
;
10745 inst
.instruction
|= Rs
<< 3;
10750 /* If we get here, it can't be done in 16 bits. */
10751 constraint (inst
.operands
[2].shifted
10752 && inst
.operands
[2].immisreg
,
10753 _("shift must be constant"));
10754 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10755 inst
.instruction
|= Rd
<< 8;
10756 inst
.instruction
|= Rs
<< 16;
10757 encode_thumb32_shifted_operand (2);
10762 /* On its face this is a lie - the instruction does set the
10763 flags. However, the only supported mnemonic in this mode
10764 says it doesn't. */
10765 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10767 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10768 _("unshifted register required"));
10769 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10771 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10772 inst
.instruction
|= Rd
;
10775 inst
.instruction
|= Rn
<< 3;
10777 inst
.instruction
|= Rs
<< 3;
10779 constraint (1, _("dest must overlap one source register"));
10787 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10788 constraint (msb
> 32, _("bit-field extends past end of register"));
10789 /* The instruction encoding stores the LSB and MSB,
10790 not the LSB and width. */
10791 Rd
= inst
.operands
[0].reg
;
10792 reject_bad_reg (Rd
);
10793 inst
.instruction
|= Rd
<< 8;
10794 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10795 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10796 inst
.instruction
|= msb
- 1;
10805 Rd
= inst
.operands
[0].reg
;
10806 reject_bad_reg (Rd
);
10808 /* #0 in second position is alternative syntax for bfc, which is
10809 the same instruction but with REG_PC in the Rm field. */
10810 if (!inst
.operands
[1].isreg
)
10814 Rn
= inst
.operands
[1].reg
;
10815 reject_bad_reg (Rn
);
10818 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10819 constraint (msb
> 32, _("bit-field extends past end of register"));
10820 /* The instruction encoding stores the LSB and MSB,
10821 not the LSB and width. */
10822 inst
.instruction
|= Rd
<< 8;
10823 inst
.instruction
|= Rn
<< 16;
10824 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10825 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10826 inst
.instruction
|= msb
- 1;
10834 Rd
= inst
.operands
[0].reg
;
10835 Rn
= inst
.operands
[1].reg
;
10837 reject_bad_reg (Rd
);
10838 reject_bad_reg (Rn
);
10840 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10841 _("bit-field extends past end of register"));
10842 inst
.instruction
|= Rd
<< 8;
10843 inst
.instruction
|= Rn
<< 16;
10844 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10845 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10846 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10849 /* ARM V5 Thumb BLX (argument parse)
10850 BLX <target_addr> which is BLX(1)
10851 BLX <Rm> which is BLX(2)
10852 Unfortunately, there are two different opcodes for this mnemonic.
10853 So, the insns[].value is not used, and the code here zaps values
10854 into inst.instruction.
10856 ??? How to take advantage of the additional two bits of displacement
10857 available in Thumb32 mode? Need new relocation? */
10862 set_it_insn_type_last ();
10864 if (inst
.operands
[0].isreg
)
10866 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10867 /* We have a register, so this is BLX(2). */
10868 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10872 /* No register. This must be BLX(1). */
10873 inst
.instruction
= 0xf000e800;
10874 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10886 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10888 if (in_it_block ())
10890 /* Conditional branches inside IT blocks are encoded as unconditional
10892 cond
= COND_ALWAYS
;
10897 if (cond
!= COND_ALWAYS
)
10898 opcode
= T_MNEM_bcond
;
10900 opcode
= inst
.instruction
;
10903 && (inst
.size_req
== 4
10904 || (inst
.size_req
!= 2
10905 && (inst
.operands
[0].hasreloc
10906 || inst
.reloc
.exp
.X_op
== O_constant
))))
10908 inst
.instruction
= THUMB_OP32(opcode
);
10909 if (cond
== COND_ALWAYS
)
10910 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10913 gas_assert (cond
!= 0xF);
10914 inst
.instruction
|= cond
<< 22;
10915 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10920 inst
.instruction
= THUMB_OP16(opcode
);
10921 if (cond
== COND_ALWAYS
)
10922 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10925 inst
.instruction
|= cond
<< 8;
10926 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10928 /* Allow section relaxation. */
10929 if (unified_syntax
&& inst
.size_req
!= 2)
10930 inst
.relax
= opcode
;
10932 inst
.reloc
.type
= reloc
;
10933 inst
.reloc
.pc_rel
= 1;
10936 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10937 between the two is the maximum immediate allowed - which is passed in
10940 do_t_bkpt_hlt1 (int range
)
10942 constraint (inst
.cond
!= COND_ALWAYS
,
10943 _("instruction is always unconditional"));
10944 if (inst
.operands
[0].present
)
10946 constraint (inst
.operands
[0].imm
> range
,
10947 _("immediate value out of range"));
10948 inst
.instruction
|= inst
.operands
[0].imm
;
10951 set_it_insn_type (NEUTRAL_IT_INSN
);
10957 do_t_bkpt_hlt1 (63);
10963 do_t_bkpt_hlt1 (255);
10967 do_t_branch23 (void)
10969 set_it_insn_type_last ();
10970 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10972 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10973 this file. We used to simply ignore the PLT reloc type here --
10974 the branch encoding is now needed to deal with TLSCALL relocs.
10975 So if we see a PLT reloc now, put it back to how it used to be to
10976 keep the preexisting behaviour. */
10977 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10978 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10980 #if defined(OBJ_COFF)
10981 /* If the destination of the branch is a defined symbol which does not have
10982 the THUMB_FUNC attribute, then we must be calling a function which has
10983 the (interfacearm) attribute. We look for the Thumb entry point to that
10984 function and change the branch to refer to that function instead. */
10985 if ( inst
.reloc
.exp
.X_op
== O_symbol
10986 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10987 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10988 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10989 inst
.reloc
.exp
.X_add_symbol
=
10990 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10997 set_it_insn_type_last ();
10998 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10999 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11000 should cause the alignment to be checked once it is known. This is
11001 because BX PC only works if the instruction is word aligned. */
11009 set_it_insn_type_last ();
11010 Rm
= inst
.operands
[0].reg
;
11011 reject_bad_reg (Rm
);
11012 inst
.instruction
|= Rm
<< 16;
11021 Rd
= inst
.operands
[0].reg
;
11022 Rm
= inst
.operands
[1].reg
;
11024 reject_bad_reg (Rd
);
11025 reject_bad_reg (Rm
);
11027 inst
.instruction
|= Rd
<< 8;
11028 inst
.instruction
|= Rm
<< 16;
11029 inst
.instruction
|= Rm
;
11035 set_it_insn_type (OUTSIDE_IT_INSN
);
11036 inst
.instruction
|= inst
.operands
[0].imm
;
11042 set_it_insn_type (OUTSIDE_IT_INSN
);
11044 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11045 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11047 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11048 inst
.instruction
= 0xf3af8000;
11049 inst
.instruction
|= imod
<< 9;
11050 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11051 if (inst
.operands
[1].present
)
11052 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11056 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11057 && (inst
.operands
[0].imm
& 4),
11058 _("selected processor does not support 'A' form "
11059 "of this instruction"));
11060 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11061 _("Thumb does not support the 2-argument "
11062 "form of this instruction"));
11063 inst
.instruction
|= inst
.operands
[0].imm
;
11067 /* THUMB CPY instruction (argument parse). */
11072 if (inst
.size_req
== 4)
11074 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11075 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11076 inst
.instruction
|= inst
.operands
[1].reg
;
11080 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11081 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11082 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11089 set_it_insn_type (OUTSIDE_IT_INSN
);
11090 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11091 inst
.instruction
|= inst
.operands
[0].reg
;
11092 inst
.reloc
.pc_rel
= 1;
11093 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11099 inst
.instruction
|= inst
.operands
[0].imm
;
11105 unsigned Rd
, Rn
, Rm
;
11107 Rd
= inst
.operands
[0].reg
;
11108 Rn
= (inst
.operands
[1].present
11109 ? inst
.operands
[1].reg
: Rd
);
11110 Rm
= inst
.operands
[2].reg
;
11112 reject_bad_reg (Rd
);
11113 reject_bad_reg (Rn
);
11114 reject_bad_reg (Rm
);
11116 inst
.instruction
|= Rd
<< 8;
11117 inst
.instruction
|= Rn
<< 16;
11118 inst
.instruction
|= Rm
;
11124 if (unified_syntax
&& inst
.size_req
== 4)
11125 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11127 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11133 unsigned int cond
= inst
.operands
[0].imm
;
11135 set_it_insn_type (IT_INSN
);
11136 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11138 now_it
.warn_deprecated
= FALSE
;
11140 /* If the condition is a negative condition, invert the mask. */
11141 if ((cond
& 0x1) == 0x0)
11143 unsigned int mask
= inst
.instruction
& 0x000f;
11145 if ((mask
& 0x7) == 0)
11147 /* No conversion needed. */
11148 now_it
.block_length
= 1;
11150 else if ((mask
& 0x3) == 0)
11153 now_it
.block_length
= 2;
11155 else if ((mask
& 0x1) == 0)
11158 now_it
.block_length
= 3;
11163 now_it
.block_length
= 4;
11166 inst
.instruction
&= 0xfff0;
11167 inst
.instruction
|= mask
;
11170 inst
.instruction
|= cond
<< 4;
11173 /* Helper function used for both push/pop and ldm/stm. */
11175 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11179 load
= (inst
.instruction
& (1 << 20)) != 0;
11181 if (mask
& (1 << 13))
11182 inst
.error
= _("SP not allowed in register list");
11184 if ((mask
& (1 << base
)) != 0
11186 inst
.error
= _("having the base register in the register list when "
11187 "using write back is UNPREDICTABLE");
11191 if (mask
& (1 << 15))
11193 if (mask
& (1 << 14))
11194 inst
.error
= _("LR and PC should not both be in register list");
11196 set_it_insn_type_last ();
11201 if (mask
& (1 << 15))
11202 inst
.error
= _("PC not allowed in register list");
11205 if ((mask
& (mask
- 1)) == 0)
11207 /* Single register transfers implemented as str/ldr. */
11210 if (inst
.instruction
& (1 << 23))
11211 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11213 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11217 if (inst
.instruction
& (1 << 23))
11218 inst
.instruction
= 0x00800000; /* ia -> [base] */
11220 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11223 inst
.instruction
|= 0xf8400000;
11225 inst
.instruction
|= 0x00100000;
11227 mask
= ffs (mask
) - 1;
11230 else if (writeback
)
11231 inst
.instruction
|= WRITE_BACK
;
11233 inst
.instruction
|= mask
;
11234 inst
.instruction
|= base
<< 16;
11240 /* This really doesn't seem worth it. */
11241 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11242 _("expression too complex"));
11243 constraint (inst
.operands
[1].writeback
,
11244 _("Thumb load/store multiple does not support {reglist}^"));
11246 if (unified_syntax
)
11248 bfd_boolean narrow
;
11252 /* See if we can use a 16-bit instruction. */
11253 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11254 && inst
.size_req
!= 4
11255 && !(inst
.operands
[1].imm
& ~0xff))
11257 mask
= 1 << inst
.operands
[0].reg
;
11259 if (inst
.operands
[0].reg
<= 7)
11261 if (inst
.instruction
== T_MNEM_stmia
11262 ? inst
.operands
[0].writeback
11263 : (inst
.operands
[0].writeback
11264 == !(inst
.operands
[1].imm
& mask
)))
11266 if (inst
.instruction
== T_MNEM_stmia
11267 && (inst
.operands
[1].imm
& mask
)
11268 && (inst
.operands
[1].imm
& (mask
- 1)))
11269 as_warn (_("value stored for r%d is UNKNOWN"),
11270 inst
.operands
[0].reg
);
11272 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11273 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11274 inst
.instruction
|= inst
.operands
[1].imm
;
11277 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11279 /* This means 1 register in reg list one of 3 situations:
11280 1. Instruction is stmia, but without writeback.
11281 2. lmdia without writeback, but with Rn not in
11283 3. ldmia with writeback, but with Rn in reglist.
11284 Case 3 is UNPREDICTABLE behaviour, so we handle
11285 case 1 and 2 which can be converted into a 16-bit
11286 str or ldr. The SP cases are handled below. */
11287 unsigned long opcode
;
11288 /* First, record an error for Case 3. */
11289 if (inst
.operands
[1].imm
& mask
11290 && inst
.operands
[0].writeback
)
11292 _("having the base register in the register list when "
11293 "using write back is UNPREDICTABLE");
11295 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11297 inst
.instruction
= THUMB_OP16 (opcode
);
11298 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11299 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11303 else if (inst
.operands
[0] .reg
== REG_SP
)
11305 if (inst
.operands
[0].writeback
)
11308 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11309 ? T_MNEM_push
: T_MNEM_pop
);
11310 inst
.instruction
|= inst
.operands
[1].imm
;
11313 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11316 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11317 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11318 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11326 if (inst
.instruction
< 0xffff)
11327 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11329 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11330 inst
.operands
[0].writeback
);
11335 constraint (inst
.operands
[0].reg
> 7
11336 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11337 constraint (inst
.instruction
!= T_MNEM_ldmia
11338 && inst
.instruction
!= T_MNEM_stmia
,
11339 _("Thumb-2 instruction only valid in unified syntax"));
11340 if (inst
.instruction
== T_MNEM_stmia
)
11342 if (!inst
.operands
[0].writeback
)
11343 as_warn (_("this instruction will write back the base register"));
11344 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11345 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11346 as_warn (_("value stored for r%d is UNKNOWN"),
11347 inst
.operands
[0].reg
);
11351 if (!inst
.operands
[0].writeback
11352 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11353 as_warn (_("this instruction will write back the base register"));
11354 else if (inst
.operands
[0].writeback
11355 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11356 as_warn (_("this instruction will not write back the base register"));
11359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11360 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11361 inst
.instruction
|= inst
.operands
[1].imm
;
11368 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11369 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11370 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11371 || inst
.operands
[1].negative
,
11374 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11377 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11378 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11384 if (!inst
.operands
[1].present
)
11386 constraint (inst
.operands
[0].reg
== REG_LR
,
11387 _("r14 not allowed as first register "
11388 "when second register is omitted"));
11389 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11391 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11395 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11396 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11402 unsigned long opcode
;
11405 if (inst
.operands
[0].isreg
11406 && !inst
.operands
[0].preind
11407 && inst
.operands
[0].reg
== REG_PC
)
11408 set_it_insn_type_last ();
11410 opcode
= inst
.instruction
;
11411 if (unified_syntax
)
11413 if (!inst
.operands
[1].isreg
)
11415 if (opcode
<= 0xffff)
11416 inst
.instruction
= THUMB_OP32 (opcode
);
11417 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11420 if (inst
.operands
[1].isreg
11421 && !inst
.operands
[1].writeback
11422 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11423 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11424 && opcode
<= 0xffff
11425 && inst
.size_req
!= 4)
11427 /* Insn may have a 16-bit form. */
11428 Rn
= inst
.operands
[1].reg
;
11429 if (inst
.operands
[1].immisreg
)
11431 inst
.instruction
= THUMB_OP16 (opcode
);
11433 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11435 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11436 reject_bad_reg (inst
.operands
[1].imm
);
11438 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11439 && opcode
!= T_MNEM_ldrsb
)
11440 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11441 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11448 if (inst
.reloc
.pc_rel
)
11449 opcode
= T_MNEM_ldr_pc2
;
11451 opcode
= T_MNEM_ldr_pc
;
11455 if (opcode
== T_MNEM_ldr
)
11456 opcode
= T_MNEM_ldr_sp
;
11458 opcode
= T_MNEM_str_sp
;
11460 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11464 inst
.instruction
= inst
.operands
[0].reg
;
11465 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11467 inst
.instruction
|= THUMB_OP16 (opcode
);
11468 if (inst
.size_req
== 2)
11469 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11471 inst
.relax
= opcode
;
11475 /* Definitely a 32-bit variant. */
11477 /* Warning for Erratum 752419. */
11478 if (opcode
== T_MNEM_ldr
11479 && inst
.operands
[0].reg
== REG_SP
11480 && inst
.operands
[1].writeback
== 1
11481 && !inst
.operands
[1].immisreg
)
11483 if (no_cpu_selected ()
11484 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11485 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11486 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11487 as_warn (_("This instruction may be unpredictable "
11488 "if executed on M-profile cores "
11489 "with interrupts enabled."));
11492 /* Do some validations regarding addressing modes. */
11493 if (inst
.operands
[1].immisreg
)
11494 reject_bad_reg (inst
.operands
[1].imm
);
11496 constraint (inst
.operands
[1].writeback
== 1
11497 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11500 inst
.instruction
= THUMB_OP32 (opcode
);
11501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11502 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11503 check_ldr_r15_aligned ();
11507 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11509 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11511 /* Only [Rn,Rm] is acceptable. */
11512 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11513 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11514 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11515 || inst
.operands
[1].negative
,
11516 _("Thumb does not support this addressing mode"));
11517 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11521 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11522 if (!inst
.operands
[1].isreg
)
11523 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11526 constraint (!inst
.operands
[1].preind
11527 || inst
.operands
[1].shifted
11528 || inst
.operands
[1].writeback
,
11529 _("Thumb does not support this addressing mode"));
11530 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11532 constraint (inst
.instruction
& 0x0600,
11533 _("byte or halfword not valid for base register"));
11534 constraint (inst
.operands
[1].reg
== REG_PC
11535 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11536 _("r15 based store not allowed"));
11537 constraint (inst
.operands
[1].immisreg
,
11538 _("invalid base register for register offset"));
11540 if (inst
.operands
[1].reg
== REG_PC
)
11541 inst
.instruction
= T_OPCODE_LDR_PC
;
11542 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11543 inst
.instruction
= T_OPCODE_LDR_SP
;
11545 inst
.instruction
= T_OPCODE_STR_SP
;
11547 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11548 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11552 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11553 if (!inst
.operands
[1].immisreg
)
11555 /* Immediate offset. */
11556 inst
.instruction
|= inst
.operands
[0].reg
;
11557 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11558 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11562 /* Register offset. */
11563 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11564 constraint (inst
.operands
[1].negative
,
11565 _("Thumb does not support this addressing mode"));
11568 switch (inst
.instruction
)
11570 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11571 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11572 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11573 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11574 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11575 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11576 case 0x5600 /* ldrsb */:
11577 case 0x5e00 /* ldrsh */: break;
11581 inst
.instruction
|= inst
.operands
[0].reg
;
11582 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11583 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11589 if (!inst
.operands
[1].present
)
11591 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11592 constraint (inst
.operands
[0].reg
== REG_LR
,
11593 _("r14 not allowed here"));
11594 constraint (inst
.operands
[0].reg
== REG_R12
,
11595 _("r12 not allowed here"));
11598 if (inst
.operands
[2].writeback
11599 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11600 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11601 as_warn (_("base register written back, and overlaps "
11602 "one of transfer registers"));
11604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11605 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11606 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11613 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11619 unsigned Rd
, Rn
, Rm
, Ra
;
11621 Rd
= inst
.operands
[0].reg
;
11622 Rn
= inst
.operands
[1].reg
;
11623 Rm
= inst
.operands
[2].reg
;
11624 Ra
= inst
.operands
[3].reg
;
11626 reject_bad_reg (Rd
);
11627 reject_bad_reg (Rn
);
11628 reject_bad_reg (Rm
);
11629 reject_bad_reg (Ra
);
11631 inst
.instruction
|= Rd
<< 8;
11632 inst
.instruction
|= Rn
<< 16;
11633 inst
.instruction
|= Rm
;
11634 inst
.instruction
|= Ra
<< 12;
11640 unsigned RdLo
, RdHi
, Rn
, Rm
;
11642 RdLo
= inst
.operands
[0].reg
;
11643 RdHi
= inst
.operands
[1].reg
;
11644 Rn
= inst
.operands
[2].reg
;
11645 Rm
= inst
.operands
[3].reg
;
11647 reject_bad_reg (RdLo
);
11648 reject_bad_reg (RdHi
);
11649 reject_bad_reg (Rn
);
11650 reject_bad_reg (Rm
);
11652 inst
.instruction
|= RdLo
<< 12;
11653 inst
.instruction
|= RdHi
<< 8;
11654 inst
.instruction
|= Rn
<< 16;
11655 inst
.instruction
|= Rm
;
11659 do_t_mov_cmp (void)
11663 Rn
= inst
.operands
[0].reg
;
11664 Rm
= inst
.operands
[1].reg
;
11667 set_it_insn_type_last ();
11669 if (unified_syntax
)
11671 int r0off
= (inst
.instruction
== T_MNEM_mov
11672 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11673 unsigned long opcode
;
11674 bfd_boolean narrow
;
11675 bfd_boolean low_regs
;
11677 low_regs
= (Rn
<= 7 && Rm
<= 7);
11678 opcode
= inst
.instruction
;
11679 if (in_it_block ())
11680 narrow
= opcode
!= T_MNEM_movs
;
11682 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11683 if (inst
.size_req
== 4
11684 || inst
.operands
[1].shifted
)
11687 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11688 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11689 && !inst
.operands
[1].shifted
11693 inst
.instruction
= T2_SUBS_PC_LR
;
11697 if (opcode
== T_MNEM_cmp
)
11699 constraint (Rn
== REG_PC
, BAD_PC
);
11702 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11704 warn_deprecated_sp (Rm
);
11705 /* R15 was documented as a valid choice for Rm in ARMv6,
11706 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11707 tools reject R15, so we do too. */
11708 constraint (Rm
== REG_PC
, BAD_PC
);
11711 reject_bad_reg (Rm
);
11713 else if (opcode
== T_MNEM_mov
11714 || opcode
== T_MNEM_movs
)
11716 if (inst
.operands
[1].isreg
)
11718 if (opcode
== T_MNEM_movs
)
11720 reject_bad_reg (Rn
);
11721 reject_bad_reg (Rm
);
11725 /* This is mov.n. */
11726 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11727 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11729 as_tsktsk (_("Use of r%u as a source register is "
11730 "deprecated when r%u is the destination "
11731 "register."), Rm
, Rn
);
11736 /* This is mov.w. */
11737 constraint (Rn
== REG_PC
, BAD_PC
);
11738 constraint (Rm
== REG_PC
, BAD_PC
);
11739 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11743 reject_bad_reg (Rn
);
11746 if (!inst
.operands
[1].isreg
)
11748 /* Immediate operand. */
11749 if (!in_it_block () && opcode
== T_MNEM_mov
)
11751 if (low_regs
&& narrow
)
11753 inst
.instruction
= THUMB_OP16 (opcode
);
11754 inst
.instruction
|= Rn
<< 8;
11755 if (inst
.size_req
== 2)
11756 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11758 inst
.relax
= opcode
;
11762 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11763 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11764 inst
.instruction
|= Rn
<< r0off
;
11765 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11768 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11769 && (inst
.instruction
== T_MNEM_mov
11770 || inst
.instruction
== T_MNEM_movs
))
11772 /* Register shifts are encoded as separate shift instructions. */
11773 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11775 if (in_it_block ())
11780 if (inst
.size_req
== 4)
11783 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11789 switch (inst
.operands
[1].shift_kind
)
11792 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11795 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11798 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11801 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11807 inst
.instruction
= opcode
;
11810 inst
.instruction
|= Rn
;
11811 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11816 inst
.instruction
|= CONDS_BIT
;
11818 inst
.instruction
|= Rn
<< 8;
11819 inst
.instruction
|= Rm
<< 16;
11820 inst
.instruction
|= inst
.operands
[1].imm
;
11825 /* Some mov with immediate shift have narrow variants.
11826 Register shifts are handled above. */
11827 if (low_regs
&& inst
.operands
[1].shifted
11828 && (inst
.instruction
== T_MNEM_mov
11829 || inst
.instruction
== T_MNEM_movs
))
11831 if (in_it_block ())
11832 narrow
= (inst
.instruction
== T_MNEM_mov
);
11834 narrow
= (inst
.instruction
== T_MNEM_movs
);
11839 switch (inst
.operands
[1].shift_kind
)
11841 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11842 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11843 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11844 default: narrow
= FALSE
; break;
11850 inst
.instruction
|= Rn
;
11851 inst
.instruction
|= Rm
<< 3;
11852 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11856 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11857 inst
.instruction
|= Rn
<< r0off
;
11858 encode_thumb32_shifted_operand (1);
11862 switch (inst
.instruction
)
11865 /* In v4t or v5t a move of two lowregs produces unpredictable
11866 results. Don't allow this. */
11869 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11870 "MOV Rd, Rs with two low registers is not "
11871 "permitted on this architecture");
11872 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11876 inst
.instruction
= T_OPCODE_MOV_HR
;
11877 inst
.instruction
|= (Rn
& 0x8) << 4;
11878 inst
.instruction
|= (Rn
& 0x7);
11879 inst
.instruction
|= Rm
<< 3;
11883 /* We know we have low registers at this point.
11884 Generate LSLS Rd, Rs, #0. */
11885 inst
.instruction
= T_OPCODE_LSL_I
;
11886 inst
.instruction
|= Rn
;
11887 inst
.instruction
|= Rm
<< 3;
11893 inst
.instruction
= T_OPCODE_CMP_LR
;
11894 inst
.instruction
|= Rn
;
11895 inst
.instruction
|= Rm
<< 3;
11899 inst
.instruction
= T_OPCODE_CMP_HR
;
11900 inst
.instruction
|= (Rn
& 0x8) << 4;
11901 inst
.instruction
|= (Rn
& 0x7);
11902 inst
.instruction
|= Rm
<< 3;
11909 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11911 /* PR 10443: Do not silently ignore shifted operands. */
11912 constraint (inst
.operands
[1].shifted
,
11913 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11915 if (inst
.operands
[1].isreg
)
11917 if (Rn
< 8 && Rm
< 8)
11919 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11920 since a MOV instruction produces unpredictable results. */
11921 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11922 inst
.instruction
= T_OPCODE_ADD_I3
;
11924 inst
.instruction
= T_OPCODE_CMP_LR
;
11926 inst
.instruction
|= Rn
;
11927 inst
.instruction
|= Rm
<< 3;
11931 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11932 inst
.instruction
= T_OPCODE_MOV_HR
;
11934 inst
.instruction
= T_OPCODE_CMP_HR
;
11940 constraint (Rn
> 7,
11941 _("only lo regs allowed with immediate"));
11942 inst
.instruction
|= Rn
<< 8;
11943 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11954 top
= (inst
.instruction
& 0x00800000) != 0;
11955 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11957 constraint (top
, _(":lower16: not allowed this instruction"));
11958 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11960 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11962 constraint (!top
, _(":upper16: not allowed this instruction"));
11963 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11966 Rd
= inst
.operands
[0].reg
;
11967 reject_bad_reg (Rd
);
11969 inst
.instruction
|= Rd
<< 8;
11970 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11972 imm
= inst
.reloc
.exp
.X_add_number
;
11973 inst
.instruction
|= (imm
& 0xf000) << 4;
11974 inst
.instruction
|= (imm
& 0x0800) << 15;
11975 inst
.instruction
|= (imm
& 0x0700) << 4;
11976 inst
.instruction
|= (imm
& 0x00ff);
11981 do_t_mvn_tst (void)
11985 Rn
= inst
.operands
[0].reg
;
11986 Rm
= inst
.operands
[1].reg
;
11988 if (inst
.instruction
== T_MNEM_cmp
11989 || inst
.instruction
== T_MNEM_cmn
)
11990 constraint (Rn
== REG_PC
, BAD_PC
);
11992 reject_bad_reg (Rn
);
11993 reject_bad_reg (Rm
);
11995 if (unified_syntax
)
11997 int r0off
= (inst
.instruction
== T_MNEM_mvn
11998 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11999 bfd_boolean narrow
;
12001 if (inst
.size_req
== 4
12002 || inst
.instruction
> 0xffff
12003 || inst
.operands
[1].shifted
12004 || Rn
> 7 || Rm
> 7)
12006 else if (inst
.instruction
== T_MNEM_cmn
12007 || inst
.instruction
== T_MNEM_tst
)
12009 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12010 narrow
= !in_it_block ();
12012 narrow
= in_it_block ();
12014 if (!inst
.operands
[1].isreg
)
12016 /* For an immediate, we always generate a 32-bit opcode;
12017 section relaxation will shrink it later if possible. */
12018 if (inst
.instruction
< 0xffff)
12019 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12020 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12021 inst
.instruction
|= Rn
<< r0off
;
12022 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12026 /* See if we can do this with a 16-bit instruction. */
12029 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12030 inst
.instruction
|= Rn
;
12031 inst
.instruction
|= Rm
<< 3;
12035 constraint (inst
.operands
[1].shifted
12036 && inst
.operands
[1].immisreg
,
12037 _("shift must be constant"));
12038 if (inst
.instruction
< 0xffff)
12039 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12040 inst
.instruction
|= Rn
<< r0off
;
12041 encode_thumb32_shifted_operand (1);
12047 constraint (inst
.instruction
> 0xffff
12048 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12049 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12050 _("unshifted register required"));
12051 constraint (Rn
> 7 || Rm
> 7,
12054 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12055 inst
.instruction
|= Rn
;
12056 inst
.instruction
|= Rm
<< 3;
12065 if (do_vfp_nsyn_mrs () == SUCCESS
)
12068 Rd
= inst
.operands
[0].reg
;
12069 reject_bad_reg (Rd
);
12070 inst
.instruction
|= Rd
<< 8;
12072 if (inst
.operands
[1].isreg
)
12074 unsigned br
= inst
.operands
[1].reg
;
12075 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12076 as_bad (_("bad register for mrs"));
12078 inst
.instruction
|= br
& (0xf << 16);
12079 inst
.instruction
|= (br
& 0x300) >> 4;
12080 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12084 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12086 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12088 /* PR gas/12698: The constraint is only applied for m_profile.
12089 If the user has specified -march=all, we want to ignore it as
12090 we are building for any CPU type, including non-m variants. */
12091 bfd_boolean m_profile
=
12092 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12093 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12094 "not support requested special purpose register"));
12097 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12099 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12100 _("'APSR', 'CPSR' or 'SPSR' expected"));
12102 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12103 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12104 inst
.instruction
|= 0xf0000;
12114 if (do_vfp_nsyn_msr () == SUCCESS
)
12117 constraint (!inst
.operands
[1].isreg
,
12118 _("Thumb encoding does not support an immediate here"));
12120 if (inst
.operands
[0].isreg
)
12121 flags
= (int)(inst
.operands
[0].reg
);
12123 flags
= inst
.operands
[0].imm
;
12125 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12127 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12129 /* PR gas/12698: The constraint is only applied for m_profile.
12130 If the user has specified -march=all, we want to ignore it as
12131 we are building for any CPU type, including non-m variants. */
12132 bfd_boolean m_profile
=
12133 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12134 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12135 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12136 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12137 && bits
!= PSR_f
)) && m_profile
,
12138 _("selected processor does not support requested special "
12139 "purpose register"));
12142 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12143 "requested special purpose register"));
12145 Rn
= inst
.operands
[1].reg
;
12146 reject_bad_reg (Rn
);
12148 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12149 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12150 inst
.instruction
|= (flags
& 0x300) >> 4;
12151 inst
.instruction
|= (flags
& 0xff);
12152 inst
.instruction
|= Rn
<< 16;
12158 bfd_boolean narrow
;
12159 unsigned Rd
, Rn
, Rm
;
12161 if (!inst
.operands
[2].present
)
12162 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12164 Rd
= inst
.operands
[0].reg
;
12165 Rn
= inst
.operands
[1].reg
;
12166 Rm
= inst
.operands
[2].reg
;
12168 if (unified_syntax
)
12170 if (inst
.size_req
== 4
12176 else if (inst
.instruction
== T_MNEM_muls
)
12177 narrow
= !in_it_block ();
12179 narrow
= in_it_block ();
12183 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12184 constraint (Rn
> 7 || Rm
> 7,
12191 /* 16-bit MULS/Conditional MUL. */
12192 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12193 inst
.instruction
|= Rd
;
12196 inst
.instruction
|= Rm
<< 3;
12198 inst
.instruction
|= Rn
<< 3;
12200 constraint (1, _("dest must overlap one source register"));
12204 constraint (inst
.instruction
!= T_MNEM_mul
,
12205 _("Thumb-2 MUL must not set flags"));
12207 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12208 inst
.instruction
|= Rd
<< 8;
12209 inst
.instruction
|= Rn
<< 16;
12210 inst
.instruction
|= Rm
<< 0;
12212 reject_bad_reg (Rd
);
12213 reject_bad_reg (Rn
);
12214 reject_bad_reg (Rm
);
12221 unsigned RdLo
, RdHi
, Rn
, Rm
;
12223 RdLo
= inst
.operands
[0].reg
;
12224 RdHi
= inst
.operands
[1].reg
;
12225 Rn
= inst
.operands
[2].reg
;
12226 Rm
= inst
.operands
[3].reg
;
12228 reject_bad_reg (RdLo
);
12229 reject_bad_reg (RdHi
);
12230 reject_bad_reg (Rn
);
12231 reject_bad_reg (Rm
);
12233 inst
.instruction
|= RdLo
<< 12;
12234 inst
.instruction
|= RdHi
<< 8;
12235 inst
.instruction
|= Rn
<< 16;
12236 inst
.instruction
|= Rm
;
12239 as_tsktsk (_("rdhi and rdlo must be different"));
12245 set_it_insn_type (NEUTRAL_IT_INSN
);
12247 if (unified_syntax
)
12249 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12251 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12252 inst
.instruction
|= inst
.operands
[0].imm
;
12256 /* PR9722: Check for Thumb2 availability before
12257 generating a thumb2 nop instruction. */
12258 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12260 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12261 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12264 inst
.instruction
= 0x46c0;
12269 constraint (inst
.operands
[0].present
,
12270 _("Thumb does not support NOP with hints"));
12271 inst
.instruction
= 0x46c0;
12278 if (unified_syntax
)
12280 bfd_boolean narrow
;
12282 if (THUMB_SETS_FLAGS (inst
.instruction
))
12283 narrow
= !in_it_block ();
12285 narrow
= in_it_block ();
12286 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12288 if (inst
.size_req
== 4)
12293 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12294 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12295 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12299 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12300 inst
.instruction
|= inst
.operands
[0].reg
;
12301 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12306 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12308 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12310 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12311 inst
.instruction
|= inst
.operands
[0].reg
;
12312 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12321 Rd
= inst
.operands
[0].reg
;
12322 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12324 reject_bad_reg (Rd
);
12325 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12326 reject_bad_reg (Rn
);
12328 inst
.instruction
|= Rd
<< 8;
12329 inst
.instruction
|= Rn
<< 16;
12331 if (!inst
.operands
[2].isreg
)
12333 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12334 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12340 Rm
= inst
.operands
[2].reg
;
12341 reject_bad_reg (Rm
);
12343 constraint (inst
.operands
[2].shifted
12344 && inst
.operands
[2].immisreg
,
12345 _("shift must be constant"));
12346 encode_thumb32_shifted_operand (2);
12353 unsigned Rd
, Rn
, Rm
;
12355 Rd
= inst
.operands
[0].reg
;
12356 Rn
= inst
.operands
[1].reg
;
12357 Rm
= inst
.operands
[2].reg
;
12359 reject_bad_reg (Rd
);
12360 reject_bad_reg (Rn
);
12361 reject_bad_reg (Rm
);
12363 inst
.instruction
|= Rd
<< 8;
12364 inst
.instruction
|= Rn
<< 16;
12365 inst
.instruction
|= Rm
;
12366 if (inst
.operands
[3].present
)
12368 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12369 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12370 _("expression too complex"));
12371 inst
.instruction
|= (val
& 0x1c) << 10;
12372 inst
.instruction
|= (val
& 0x03) << 6;
12379 if (!inst
.operands
[3].present
)
12383 inst
.instruction
&= ~0x00000020;
12385 /* PR 10168. Swap the Rm and Rn registers. */
12386 Rtmp
= inst
.operands
[1].reg
;
12387 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12388 inst
.operands
[2].reg
= Rtmp
;
12396 if (inst
.operands
[0].immisreg
)
12397 reject_bad_reg (inst
.operands
[0].imm
);
12399 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12403 do_t_push_pop (void)
12407 constraint (inst
.operands
[0].writeback
,
12408 _("push/pop do not support {reglist}^"));
12409 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12410 _("expression too complex"));
12412 mask
= inst
.operands
[0].imm
;
12413 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12414 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12415 else if (inst
.size_req
!= 4
12416 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12417 ? REG_LR
: REG_PC
)))
12419 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12420 inst
.instruction
|= THUMB_PP_PC_LR
;
12421 inst
.instruction
|= mask
& 0xff;
12423 else if (unified_syntax
)
12425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12426 encode_thumb2_ldmstm (13, mask
, TRUE
);
12430 inst
.error
= _("invalid register list to push/pop instruction");
12440 Rd
= inst
.operands
[0].reg
;
12441 Rm
= inst
.operands
[1].reg
;
12443 reject_bad_reg (Rd
);
12444 reject_bad_reg (Rm
);
12446 inst
.instruction
|= Rd
<< 8;
12447 inst
.instruction
|= Rm
<< 16;
12448 inst
.instruction
|= Rm
;
12456 Rd
= inst
.operands
[0].reg
;
12457 Rm
= inst
.operands
[1].reg
;
12459 reject_bad_reg (Rd
);
12460 reject_bad_reg (Rm
);
12462 if (Rd
<= 7 && Rm
<= 7
12463 && inst
.size_req
!= 4)
12465 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12466 inst
.instruction
|= Rd
;
12467 inst
.instruction
|= Rm
<< 3;
12469 else if (unified_syntax
)
12471 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12472 inst
.instruction
|= Rd
<< 8;
12473 inst
.instruction
|= Rm
<< 16;
12474 inst
.instruction
|= Rm
;
12477 inst
.error
= BAD_HIREG
;
12485 Rd
= inst
.operands
[0].reg
;
12486 Rm
= inst
.operands
[1].reg
;
12488 reject_bad_reg (Rd
);
12489 reject_bad_reg (Rm
);
12491 inst
.instruction
|= Rd
<< 8;
12492 inst
.instruction
|= Rm
;
12500 Rd
= inst
.operands
[0].reg
;
12501 Rs
= (inst
.operands
[1].present
12502 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12503 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12505 reject_bad_reg (Rd
);
12506 reject_bad_reg (Rs
);
12507 if (inst
.operands
[2].isreg
)
12508 reject_bad_reg (inst
.operands
[2].reg
);
12510 inst
.instruction
|= Rd
<< 8;
12511 inst
.instruction
|= Rs
<< 16;
12512 if (!inst
.operands
[2].isreg
)
12514 bfd_boolean narrow
;
12516 if ((inst
.instruction
& 0x00100000) != 0)
12517 narrow
= !in_it_block ();
12519 narrow
= in_it_block ();
12521 if (Rd
> 7 || Rs
> 7)
12524 if (inst
.size_req
== 4 || !unified_syntax
)
12527 if (inst
.reloc
.exp
.X_op
!= O_constant
12528 || inst
.reloc
.exp
.X_add_number
!= 0)
12531 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12532 relaxation, but it doesn't seem worth the hassle. */
12535 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12536 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12537 inst
.instruction
|= Rs
<< 3;
12538 inst
.instruction
|= Rd
;
12542 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12543 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12547 encode_thumb32_shifted_operand (2);
12553 if (warn_on_deprecated
12554 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12555 as_tsktsk (_("setend use is deprecated for ARMv8"));
12557 set_it_insn_type (OUTSIDE_IT_INSN
);
12558 if (inst
.operands
[0].imm
)
12559 inst
.instruction
|= 0x8;
12565 if (!inst
.operands
[1].present
)
12566 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12568 if (unified_syntax
)
12570 bfd_boolean narrow
;
12573 switch (inst
.instruction
)
12576 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12578 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12580 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12582 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12586 if (THUMB_SETS_FLAGS (inst
.instruction
))
12587 narrow
= !in_it_block ();
12589 narrow
= in_it_block ();
12590 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12592 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12594 if (inst
.operands
[2].isreg
12595 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12596 || inst
.operands
[2].reg
> 7))
12598 if (inst
.size_req
== 4)
12601 reject_bad_reg (inst
.operands
[0].reg
);
12602 reject_bad_reg (inst
.operands
[1].reg
);
12606 if (inst
.operands
[2].isreg
)
12608 reject_bad_reg (inst
.operands
[2].reg
);
12609 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12610 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12611 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12612 inst
.instruction
|= inst
.operands
[2].reg
;
12614 /* PR 12854: Error on extraneous shifts. */
12615 constraint (inst
.operands
[2].shifted
,
12616 _("extraneous shift as part of operand to shift insn"));
12620 inst
.operands
[1].shifted
= 1;
12621 inst
.operands
[1].shift_kind
= shift_kind
;
12622 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12623 ? T_MNEM_movs
: T_MNEM_mov
);
12624 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12625 encode_thumb32_shifted_operand (1);
12626 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12627 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12632 if (inst
.operands
[2].isreg
)
12634 switch (shift_kind
)
12636 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12637 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12638 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12639 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12643 inst
.instruction
|= inst
.operands
[0].reg
;
12644 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12646 /* PR 12854: Error on extraneous shifts. */
12647 constraint (inst
.operands
[2].shifted
,
12648 _("extraneous shift as part of operand to shift insn"));
12652 switch (shift_kind
)
12654 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12655 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12656 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12659 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12660 inst
.instruction
|= inst
.operands
[0].reg
;
12661 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12667 constraint (inst
.operands
[0].reg
> 7
12668 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12669 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12671 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12673 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12674 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12675 _("source1 and dest must be same register"));
12677 switch (inst
.instruction
)
12679 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12680 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12681 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12682 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12686 inst
.instruction
|= inst
.operands
[0].reg
;
12687 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12689 /* PR 12854: Error on extraneous shifts. */
12690 constraint (inst
.operands
[2].shifted
,
12691 _("extraneous shift as part of operand to shift insn"));
12695 switch (inst
.instruction
)
12697 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12698 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12699 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12700 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12703 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12704 inst
.instruction
|= inst
.operands
[0].reg
;
12705 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12713 unsigned Rd
, Rn
, Rm
;
12715 Rd
= inst
.operands
[0].reg
;
12716 Rn
= inst
.operands
[1].reg
;
12717 Rm
= inst
.operands
[2].reg
;
12719 reject_bad_reg (Rd
);
12720 reject_bad_reg (Rn
);
12721 reject_bad_reg (Rm
);
12723 inst
.instruction
|= Rd
<< 8;
12724 inst
.instruction
|= Rn
<< 16;
12725 inst
.instruction
|= Rm
;
12731 unsigned Rd
, Rn
, Rm
;
12733 Rd
= inst
.operands
[0].reg
;
12734 Rm
= inst
.operands
[1].reg
;
12735 Rn
= inst
.operands
[2].reg
;
12737 reject_bad_reg (Rd
);
12738 reject_bad_reg (Rn
);
12739 reject_bad_reg (Rm
);
12741 inst
.instruction
|= Rd
<< 8;
12742 inst
.instruction
|= Rn
<< 16;
12743 inst
.instruction
|= Rm
;
12749 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12751 _("SMC is not permitted on this architecture"));
12752 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12753 _("expression too complex"));
12754 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12755 inst
.instruction
|= (value
& 0xf000) >> 12;
12756 inst
.instruction
|= (value
& 0x0ff0);
12757 inst
.instruction
|= (value
& 0x000f) << 16;
12758 /* PR gas/15623: SMC instructions must be last in an IT block. */
12759 set_it_insn_type_last ();
12765 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12767 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12768 inst
.instruction
|= (value
& 0x0fff);
12769 inst
.instruction
|= (value
& 0xf000) << 4;
12773 do_t_ssat_usat (int bias
)
12777 Rd
= inst
.operands
[0].reg
;
12778 Rn
= inst
.operands
[2].reg
;
12780 reject_bad_reg (Rd
);
12781 reject_bad_reg (Rn
);
12783 inst
.instruction
|= Rd
<< 8;
12784 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12785 inst
.instruction
|= Rn
<< 16;
12787 if (inst
.operands
[3].present
)
12789 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12791 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12793 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12794 _("expression too complex"));
12796 if (shift_amount
!= 0)
12798 constraint (shift_amount
> 31,
12799 _("shift expression is too large"));
12801 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12802 inst
.instruction
|= 0x00200000; /* sh bit. */
12804 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12805 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12813 do_t_ssat_usat (1);
12821 Rd
= inst
.operands
[0].reg
;
12822 Rn
= inst
.operands
[2].reg
;
12824 reject_bad_reg (Rd
);
12825 reject_bad_reg (Rn
);
12827 inst
.instruction
|= Rd
<< 8;
12828 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12829 inst
.instruction
|= Rn
<< 16;
12835 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12836 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12837 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12838 || inst
.operands
[2].negative
,
12841 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12843 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12844 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12845 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12846 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12852 if (!inst
.operands
[2].present
)
12853 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12855 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12856 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12857 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12860 inst
.instruction
|= inst
.operands
[0].reg
;
12861 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12862 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12863 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12869 unsigned Rd
, Rn
, Rm
;
12871 Rd
= inst
.operands
[0].reg
;
12872 Rn
= inst
.operands
[1].reg
;
12873 Rm
= inst
.operands
[2].reg
;
12875 reject_bad_reg (Rd
);
12876 reject_bad_reg (Rn
);
12877 reject_bad_reg (Rm
);
12879 inst
.instruction
|= Rd
<< 8;
12880 inst
.instruction
|= Rn
<< 16;
12881 inst
.instruction
|= Rm
;
12882 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12890 Rd
= inst
.operands
[0].reg
;
12891 Rm
= inst
.operands
[1].reg
;
12893 reject_bad_reg (Rd
);
12894 reject_bad_reg (Rm
);
12896 if (inst
.instruction
<= 0xffff
12897 && inst
.size_req
!= 4
12898 && Rd
<= 7 && Rm
<= 7
12899 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12901 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12902 inst
.instruction
|= Rd
;
12903 inst
.instruction
|= Rm
<< 3;
12905 else if (unified_syntax
)
12907 if (inst
.instruction
<= 0xffff)
12908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12909 inst
.instruction
|= Rd
<< 8;
12910 inst
.instruction
|= Rm
;
12911 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12915 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12916 _("Thumb encoding does not support rotation"));
12917 constraint (1, BAD_HIREG
);
12924 /* We have to do the following check manually as ARM_EXT_OS only applies
12926 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12928 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12929 /* This only applies to the v6m howver, not later architectures. */
12930 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12931 as_bad (_("SVC is not permitted on this architecture"));
12932 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12935 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12944 half
= (inst
.instruction
& 0x10) != 0;
12945 set_it_insn_type_last ();
12946 constraint (inst
.operands
[0].immisreg
,
12947 _("instruction requires register index"));
12949 Rn
= inst
.operands
[0].reg
;
12950 Rm
= inst
.operands
[0].imm
;
12952 constraint (Rn
== REG_SP
, BAD_SP
);
12953 reject_bad_reg (Rm
);
12955 constraint (!half
&& inst
.operands
[0].shifted
,
12956 _("instruction does not allow shifted index"));
12957 inst
.instruction
|= (Rn
<< 16) | Rm
;
12963 if (!inst
.operands
[0].present
)
12964 inst
.operands
[0].imm
= 0;
12966 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12968 constraint (inst
.size_req
== 2,
12969 _("immediate value out of range"));
12970 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12971 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12972 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12976 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12977 inst
.instruction
|= inst
.operands
[0].imm
;
12980 set_it_insn_type (NEUTRAL_IT_INSN
);
12987 do_t_ssat_usat (0);
12995 Rd
= inst
.operands
[0].reg
;
12996 Rn
= inst
.operands
[2].reg
;
12998 reject_bad_reg (Rd
);
12999 reject_bad_reg (Rn
);
13001 inst
.instruction
|= Rd
<< 8;
13002 inst
.instruction
|= inst
.operands
[1].imm
;
13003 inst
.instruction
|= Rn
<< 16;
13006 /* Neon instruction encoder helpers. */
13008 /* Encodings for the different types for various Neon opcodes. */
13010 /* An "invalid" code for the following tables. */
13013 struct neon_tab_entry
13016 unsigned float_or_poly
;
13017 unsigned scalar_or_imm
;
13020 /* Map overloaded Neon opcodes to their respective encodings. */
13021 #define NEON_ENC_TAB \
13022 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13023 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13024 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13025 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13026 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13027 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13028 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13029 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13030 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13031 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13032 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13033 /* Register variants of the following two instructions are encoded as
13034 vcge / vcgt with the operands reversed. */ \
13035 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13036 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13037 X(vfma, N_INV, 0x0000c10, N_INV), \
13038 X(vfms, N_INV, 0x0200c10, N_INV), \
13039 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13040 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13041 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13042 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13043 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13044 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13045 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13046 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13047 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13048 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13049 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13050 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13051 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13052 X(vshl, 0x0000400, N_INV, 0x0800510), \
13053 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13054 X(vand, 0x0000110, N_INV, 0x0800030), \
13055 X(vbic, 0x0100110, N_INV, 0x0800030), \
13056 X(veor, 0x1000110, N_INV, N_INV), \
13057 X(vorn, 0x0300110, N_INV, 0x0800010), \
13058 X(vorr, 0x0200110, N_INV, 0x0800010), \
13059 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13060 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13061 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13062 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13063 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13064 X(vst1, 0x0000000, 0x0800000, N_INV), \
13065 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13066 X(vst2, 0x0000100, 0x0800100, N_INV), \
13067 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13068 X(vst3, 0x0000200, 0x0800200, N_INV), \
13069 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13070 X(vst4, 0x0000300, 0x0800300, N_INV), \
13071 X(vmovn, 0x1b20200, N_INV, N_INV), \
13072 X(vtrn, 0x1b20080, N_INV, N_INV), \
13073 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13074 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13075 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13076 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13077 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13078 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13079 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13080 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13081 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13082 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13083 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13084 X(vseleq, 0xe000a00, N_INV, N_INV), \
13085 X(vselvs, 0xe100a00, N_INV, N_INV), \
13086 X(vselge, 0xe200a00, N_INV, N_INV), \
13087 X(vselgt, 0xe300a00, N_INV, N_INV), \
13088 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13089 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13090 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13091 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13092 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13093 X(aes, 0x3b00300, N_INV, N_INV), \
13094 X(sha3op, 0x2000c00, N_INV, N_INV), \
13095 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13096 X(sha2op, 0x3ba0380, N_INV, N_INV)
13100 #define X(OPC,I,F,S) N_MNEM_##OPC
13105 static const struct neon_tab_entry neon_enc_tab
[] =
13107 #define X(OPC,I,F,S) { (I), (F), (S) }
13112 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13113 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13114 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13115 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13116 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13117 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13118 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13119 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13120 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13121 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13122 #define NEON_ENC_SINGLE_(X) \
13123 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13124 #define NEON_ENC_DOUBLE_(X) \
13125 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13126 #define NEON_ENC_FPV8_(X) \
13127 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13129 #define NEON_ENCODE(type, inst) \
13132 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13133 inst.is_neon = 1; \
13137 #define check_neon_suffixes \
13140 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13142 as_bad (_("invalid neon suffix for non neon instruction")); \
13148 /* Define shapes for instruction operands. The following mnemonic characters
13149 are used in this table:
13151 F - VFP S<n> register
13152 D - Neon D<n> register
13153 Q - Neon Q<n> register
13157 L - D<n> register list
13159 This table is used to generate various data:
13160 - enumerations of the form NS_DDR to be used as arguments to
13162 - a table classifying shapes into single, double, quad, mixed.
13163 - a table used to drive neon_select_shape. */
13165 #define NEON_SHAPE_DEF \
13166 X(3, (D, D, D), DOUBLE), \
13167 X(3, (Q, Q, Q), QUAD), \
13168 X(3, (D, D, I), DOUBLE), \
13169 X(3, (Q, Q, I), QUAD), \
13170 X(3, (D, D, S), DOUBLE), \
13171 X(3, (Q, Q, S), QUAD), \
13172 X(2, (D, D), DOUBLE), \
13173 X(2, (Q, Q), QUAD), \
13174 X(2, (D, S), DOUBLE), \
13175 X(2, (Q, S), QUAD), \
13176 X(2, (D, R), DOUBLE), \
13177 X(2, (Q, R), QUAD), \
13178 X(2, (D, I), DOUBLE), \
13179 X(2, (Q, I), QUAD), \
13180 X(3, (D, L, D), DOUBLE), \
13181 X(2, (D, Q), MIXED), \
13182 X(2, (Q, D), MIXED), \
13183 X(3, (D, Q, I), MIXED), \
13184 X(3, (Q, D, I), MIXED), \
13185 X(3, (Q, D, D), MIXED), \
13186 X(3, (D, Q, Q), MIXED), \
13187 X(3, (Q, Q, D), MIXED), \
13188 X(3, (Q, D, S), MIXED), \
13189 X(3, (D, Q, S), MIXED), \
13190 X(4, (D, D, D, I), DOUBLE), \
13191 X(4, (Q, Q, Q, I), QUAD), \
13192 X(2, (F, F), SINGLE), \
13193 X(3, (F, F, F), SINGLE), \
13194 X(2, (F, I), SINGLE), \
13195 X(2, (F, D), MIXED), \
13196 X(2, (D, F), MIXED), \
13197 X(3, (F, F, I), MIXED), \
13198 X(4, (R, R, F, F), SINGLE), \
13199 X(4, (F, F, R, R), SINGLE), \
13200 X(3, (D, R, R), DOUBLE), \
13201 X(3, (R, R, D), DOUBLE), \
13202 X(2, (S, R), SINGLE), \
13203 X(2, (R, S), SINGLE), \
13204 X(2, (F, R), SINGLE), \
13205 X(2, (R, F), SINGLE)
13207 #define S2(A,B) NS_##A##B
13208 #define S3(A,B,C) NS_##A##B##C
13209 #define S4(A,B,C,D) NS_##A##B##C##D
13211 #define X(N, L, C) S##N L
13224 enum neon_shape_class
13232 #define X(N, L, C) SC_##C
13234 static enum neon_shape_class neon_shape_class
[] =
13252 /* Register widths of above. */
13253 static unsigned neon_shape_el_size
[] =
13264 struct neon_shape_info
13267 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13270 #define S2(A,B) { SE_##A, SE_##B }
13271 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13272 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13274 #define X(N, L, C) { N, S##N L }
13276 static struct neon_shape_info neon_shape_tab
[] =
13286 /* Bit masks used in type checking given instructions.
13287 'N_EQK' means the type must be the same as (or based on in some way) the key
13288 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13289 set, various other bits can be set as well in order to modify the meaning of
13290 the type constraint. */
13292 enum neon_type_mask
13316 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13317 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13318 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13319 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13320 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13321 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13322 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13323 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13324 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13325 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13326 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13328 N_MAX_NONSPECIAL
= N_P64
13331 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13333 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13334 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13335 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13336 #define N_SUF_32 (N_SU_32 | N_F32)
13337 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13338 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13340 /* Pass this as the first type argument to neon_check_type to ignore types
13342 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13344 /* Select a "shape" for the current instruction (describing register types or
13345 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13346 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13347 function of operand parsing, so this function doesn't need to be called.
13348 Shapes should be listed in order of decreasing length. */
13350 static enum neon_shape
13351 neon_select_shape (enum neon_shape shape
, ...)
13354 enum neon_shape first_shape
= shape
;
13356 /* Fix missing optional operands. FIXME: we don't know at this point how
13357 many arguments we should have, so this makes the assumption that we have
13358 > 1. This is true of all current Neon opcodes, I think, but may not be
13359 true in the future. */
13360 if (!inst
.operands
[1].present
)
13361 inst
.operands
[1] = inst
.operands
[0];
13363 va_start (ap
, shape
);
13365 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13370 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13372 if (!inst
.operands
[j
].present
)
13378 switch (neon_shape_tab
[shape
].el
[j
])
13381 if (!(inst
.operands
[j
].isreg
13382 && inst
.operands
[j
].isvec
13383 && inst
.operands
[j
].issingle
13384 && !inst
.operands
[j
].isquad
))
13389 if (!(inst
.operands
[j
].isreg
13390 && inst
.operands
[j
].isvec
13391 && !inst
.operands
[j
].isquad
13392 && !inst
.operands
[j
].issingle
))
13397 if (!(inst
.operands
[j
].isreg
13398 && !inst
.operands
[j
].isvec
))
13403 if (!(inst
.operands
[j
].isreg
13404 && inst
.operands
[j
].isvec
13405 && inst
.operands
[j
].isquad
13406 && !inst
.operands
[j
].issingle
))
13411 if (!(!inst
.operands
[j
].isreg
13412 && !inst
.operands
[j
].isscalar
))
13417 if (!(!inst
.operands
[j
].isreg
13418 && inst
.operands
[j
].isscalar
))
13428 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13429 /* We've matched all the entries in the shape table, and we don't
13430 have any left over operands which have not been matched. */
13436 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13437 first_error (_("invalid instruction shape"));
13442 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13443 means the Q bit should be set). */
13446 neon_quad (enum neon_shape shape
)
13448 return neon_shape_class
[shape
] == SC_QUAD
;
13452 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13455 /* Allow modification to be made to types which are constrained to be
13456 based on the key element, based on bits set alongside N_EQK. */
13457 if ((typebits
& N_EQK
) != 0)
13459 if ((typebits
& N_HLF
) != 0)
13461 else if ((typebits
& N_DBL
) != 0)
13463 if ((typebits
& N_SGN
) != 0)
13464 *g_type
= NT_signed
;
13465 else if ((typebits
& N_UNS
) != 0)
13466 *g_type
= NT_unsigned
;
13467 else if ((typebits
& N_INT
) != 0)
13468 *g_type
= NT_integer
;
13469 else if ((typebits
& N_FLT
) != 0)
13470 *g_type
= NT_float
;
13471 else if ((typebits
& N_SIZ
) != 0)
13472 *g_type
= NT_untyped
;
13476 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13477 operand type, i.e. the single type specified in a Neon instruction when it
13478 is the only one given. */
13480 static struct neon_type_el
13481 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13483 struct neon_type_el dest
= *key
;
13485 gas_assert ((thisarg
& N_EQK
) != 0);
13487 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13492 /* Convert Neon type and size into compact bitmask representation. */
13494 static enum neon_type_mask
13495 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13502 case 8: return N_8
;
13503 case 16: return N_16
;
13504 case 32: return N_32
;
13505 case 64: return N_64
;
13513 case 8: return N_I8
;
13514 case 16: return N_I16
;
13515 case 32: return N_I32
;
13516 case 64: return N_I64
;
13524 case 16: return N_F16
;
13525 case 32: return N_F32
;
13526 case 64: return N_F64
;
13534 case 8: return N_P8
;
13535 case 16: return N_P16
;
13536 case 64: return N_P64
;
13544 case 8: return N_S8
;
13545 case 16: return N_S16
;
13546 case 32: return N_S32
;
13547 case 64: return N_S64
;
13555 case 8: return N_U8
;
13556 case 16: return N_U16
;
13557 case 32: return N_U32
;
13558 case 64: return N_U64
;
13569 /* Convert compact Neon bitmask type representation to a type and size. Only
13570 handles the case where a single bit is set in the mask. */
13573 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13574 enum neon_type_mask mask
)
13576 if ((mask
& N_EQK
) != 0)
13579 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13581 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13583 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13585 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13590 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13592 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13593 *type
= NT_unsigned
;
13594 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13595 *type
= NT_integer
;
13596 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13597 *type
= NT_untyped
;
13598 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13600 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13608 /* Modify a bitmask of allowed types. This is only needed for type
13612 modify_types_allowed (unsigned allowed
, unsigned mods
)
13615 enum neon_el_type type
;
13621 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13623 if (el_type_of_type_chk (&type
, &size
,
13624 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13626 neon_modify_type_size (mods
, &type
, &size
);
13627 destmask
|= type_chk_of_el_type (type
, size
);
13634 /* Check type and return type classification.
13635 The manual states (paraphrase): If one datatype is given, it indicates the
13637 - the second operand, if there is one
13638 - the operand, if there is no second operand
13639 - the result, if there are no operands.
13640 This isn't quite good enough though, so we use a concept of a "key" datatype
13641 which is set on a per-instruction basis, which is the one which matters when
13642 only one data type is written.
13643 Note: this function has side-effects (e.g. filling in missing operands). All
13644 Neon instructions should call it before performing bit encoding. */
13646 static struct neon_type_el
13647 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13650 unsigned i
, pass
, key_el
= 0;
13651 unsigned types
[NEON_MAX_TYPE_ELS
];
13652 enum neon_el_type k_type
= NT_invtype
;
13653 unsigned k_size
= -1u;
13654 struct neon_type_el badtype
= {NT_invtype
, -1};
13655 unsigned key_allowed
= 0;
13657 /* Optional registers in Neon instructions are always (not) in operand 1.
13658 Fill in the missing operand here, if it was omitted. */
13659 if (els
> 1 && !inst
.operands
[1].present
)
13660 inst
.operands
[1] = inst
.operands
[0];
13662 /* Suck up all the varargs. */
13664 for (i
= 0; i
< els
; i
++)
13666 unsigned thisarg
= va_arg (ap
, unsigned);
13667 if (thisarg
== N_IGNORE_TYPE
)
13672 types
[i
] = thisarg
;
13673 if ((thisarg
& N_KEY
) != 0)
13678 if (inst
.vectype
.elems
> 0)
13679 for (i
= 0; i
< els
; i
++)
13680 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13682 first_error (_("types specified in both the mnemonic and operands"));
13686 /* Duplicate inst.vectype elements here as necessary.
13687 FIXME: No idea if this is exactly the same as the ARM assembler,
13688 particularly when an insn takes one register and one non-register
13690 if (inst
.vectype
.elems
== 1 && els
> 1)
13693 inst
.vectype
.elems
= els
;
13694 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13695 for (j
= 0; j
< els
; j
++)
13697 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13700 else if (inst
.vectype
.elems
== 0 && els
> 0)
13703 /* No types were given after the mnemonic, so look for types specified
13704 after each operand. We allow some flexibility here; as long as the
13705 "key" operand has a type, we can infer the others. */
13706 for (j
= 0; j
< els
; j
++)
13707 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13708 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13710 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13712 for (j
= 0; j
< els
; j
++)
13713 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13714 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13719 first_error (_("operand types can't be inferred"));
13723 else if (inst
.vectype
.elems
!= els
)
13725 first_error (_("type specifier has the wrong number of parts"));
13729 for (pass
= 0; pass
< 2; pass
++)
13731 for (i
= 0; i
< els
; i
++)
13733 unsigned thisarg
= types
[i
];
13734 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13735 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13736 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13737 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13739 /* Decay more-specific signed & unsigned types to sign-insensitive
13740 integer types if sign-specific variants are unavailable. */
13741 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13742 && (types_allowed
& N_SU_ALL
) == 0)
13743 g_type
= NT_integer
;
13745 /* If only untyped args are allowed, decay any more specific types to
13746 them. Some instructions only care about signs for some element
13747 sizes, so handle that properly. */
13748 if (((types_allowed
& N_UNT
) == 0)
13749 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13750 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13751 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13752 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13753 g_type
= NT_untyped
;
13757 if ((thisarg
& N_KEY
) != 0)
13761 key_allowed
= thisarg
& ~N_KEY
;
13766 if ((thisarg
& N_VFP
) != 0)
13768 enum neon_shape_el regshape
;
13769 unsigned regwidth
, match
;
13771 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13774 first_error (_("invalid instruction shape"));
13777 regshape
= neon_shape_tab
[ns
].el
[i
];
13778 regwidth
= neon_shape_el_size
[regshape
];
13780 /* In VFP mode, operands must match register widths. If we
13781 have a key operand, use its width, else use the width of
13782 the current operand. */
13788 if (regwidth
!= match
)
13790 first_error (_("operand size must match register width"));
13795 if ((thisarg
& N_EQK
) == 0)
13797 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13799 if ((given_type
& types_allowed
) == 0)
13801 first_error (_("bad type in Neon instruction"));
13807 enum neon_el_type mod_k_type
= k_type
;
13808 unsigned mod_k_size
= k_size
;
13809 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13810 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13812 first_error (_("inconsistent types in Neon instruction"));
13820 return inst
.vectype
.el
[key_el
];
13823 /* Neon-style VFP instruction forwarding. */
13825 /* Thumb VFP instructions have 0xE in the condition field. */
13828 do_vfp_cond_or_thumb (void)
13833 inst
.instruction
|= 0xe0000000;
13835 inst
.instruction
|= inst
.cond
<< 28;
13838 /* Look up and encode a simple mnemonic, for use as a helper function for the
13839 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13840 etc. It is assumed that operand parsing has already been done, and that the
13841 operands are in the form expected by the given opcode (this isn't necessarily
13842 the same as the form in which they were parsed, hence some massaging must
13843 take place before this function is called).
13844 Checks current arch version against that in the looked-up opcode. */
13847 do_vfp_nsyn_opcode (const char *opname
)
13849 const struct asm_opcode
*opcode
;
13851 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13857 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13864 inst
.instruction
= opcode
->tvalue
;
13865 opcode
->tencode ();
13869 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13870 opcode
->aencode ();
13875 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13877 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13882 do_vfp_nsyn_opcode ("fadds");
13884 do_vfp_nsyn_opcode ("fsubs");
13889 do_vfp_nsyn_opcode ("faddd");
13891 do_vfp_nsyn_opcode ("fsubd");
13895 /* Check operand types to see if this is a VFP instruction, and if so call
13899 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13901 enum neon_shape rs
;
13902 struct neon_type_el et
;
13907 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13908 et
= neon_check_type (2, rs
,
13909 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13913 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13914 et
= neon_check_type (3, rs
,
13915 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13922 if (et
.type
!= NT_invtype
)
13933 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13935 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13940 do_vfp_nsyn_opcode ("fmacs");
13942 do_vfp_nsyn_opcode ("fnmacs");
13947 do_vfp_nsyn_opcode ("fmacd");
13949 do_vfp_nsyn_opcode ("fnmacd");
13954 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13956 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13961 do_vfp_nsyn_opcode ("ffmas");
13963 do_vfp_nsyn_opcode ("ffnmas");
13968 do_vfp_nsyn_opcode ("ffmad");
13970 do_vfp_nsyn_opcode ("ffnmad");
13975 do_vfp_nsyn_mul (enum neon_shape rs
)
13978 do_vfp_nsyn_opcode ("fmuls");
13980 do_vfp_nsyn_opcode ("fmuld");
13984 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13986 int is_neg
= (inst
.instruction
& 0x80) != 0;
13987 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13992 do_vfp_nsyn_opcode ("fnegs");
13994 do_vfp_nsyn_opcode ("fabss");
13999 do_vfp_nsyn_opcode ("fnegd");
14001 do_vfp_nsyn_opcode ("fabsd");
14005 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14006 insns belong to Neon, and are handled elsewhere. */
14009 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14011 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14015 do_vfp_nsyn_opcode ("fldmdbs");
14017 do_vfp_nsyn_opcode ("fldmias");
14022 do_vfp_nsyn_opcode ("fstmdbs");
14024 do_vfp_nsyn_opcode ("fstmias");
14029 do_vfp_nsyn_sqrt (void)
14031 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14032 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14035 do_vfp_nsyn_opcode ("fsqrts");
14037 do_vfp_nsyn_opcode ("fsqrtd");
14041 do_vfp_nsyn_div (void)
14043 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14044 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14045 N_F32
| N_F64
| N_KEY
| N_VFP
);
14048 do_vfp_nsyn_opcode ("fdivs");
14050 do_vfp_nsyn_opcode ("fdivd");
14054 do_vfp_nsyn_nmul (void)
14056 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14057 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14058 N_F32
| N_F64
| N_KEY
| N_VFP
);
14062 NEON_ENCODE (SINGLE
, inst
);
14063 do_vfp_sp_dyadic ();
14067 NEON_ENCODE (DOUBLE
, inst
);
14068 do_vfp_dp_rd_rn_rm ();
14070 do_vfp_cond_or_thumb ();
14074 do_vfp_nsyn_cmp (void)
14076 if (inst
.operands
[1].isreg
)
14078 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14079 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14083 NEON_ENCODE (SINGLE
, inst
);
14084 do_vfp_sp_monadic ();
14088 NEON_ENCODE (DOUBLE
, inst
);
14089 do_vfp_dp_rd_rm ();
14094 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14095 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14097 switch (inst
.instruction
& 0x0fffffff)
14100 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14103 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14111 NEON_ENCODE (SINGLE
, inst
);
14112 do_vfp_sp_compare_z ();
14116 NEON_ENCODE (DOUBLE
, inst
);
14120 do_vfp_cond_or_thumb ();
14124 nsyn_insert_sp (void)
14126 inst
.operands
[1] = inst
.operands
[0];
14127 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14128 inst
.operands
[0].reg
= REG_SP
;
14129 inst
.operands
[0].isreg
= 1;
14130 inst
.operands
[0].writeback
= 1;
14131 inst
.operands
[0].present
= 1;
14135 do_vfp_nsyn_push (void)
14138 if (inst
.operands
[1].issingle
)
14139 do_vfp_nsyn_opcode ("fstmdbs");
14141 do_vfp_nsyn_opcode ("fstmdbd");
14145 do_vfp_nsyn_pop (void)
14148 if (inst
.operands
[1].issingle
)
14149 do_vfp_nsyn_opcode ("fldmias");
14151 do_vfp_nsyn_opcode ("fldmiad");
14154 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14155 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14158 neon_dp_fixup (struct arm_it
* insn
)
14160 unsigned int i
= insn
->instruction
;
14165 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14176 insn
->instruction
= i
;
14179 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14183 neon_logbits (unsigned x
)
14185 return ffs (x
) - 4;
14188 #define LOW4(R) ((R) & 0xf)
14189 #define HI1(R) (((R) >> 4) & 1)
14191 /* Encode insns with bit pattern:
14193 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14194 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14196 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14197 different meaning for some instruction. */
14200 neon_three_same (int isquad
, int ubit
, int size
)
14202 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14203 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14204 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14205 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14206 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14207 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14208 inst
.instruction
|= (isquad
!= 0) << 6;
14209 inst
.instruction
|= (ubit
!= 0) << 24;
14211 inst
.instruction
|= neon_logbits (size
) << 20;
14213 neon_dp_fixup (&inst
);
14216 /* Encode instructions of the form:
14218 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14219 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14221 Don't write size if SIZE == -1. */
14224 neon_two_same (int qbit
, int ubit
, int size
)
14226 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14227 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14228 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14229 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14230 inst
.instruction
|= (qbit
!= 0) << 6;
14231 inst
.instruction
|= (ubit
!= 0) << 24;
14234 inst
.instruction
|= neon_logbits (size
) << 18;
14236 neon_dp_fixup (&inst
);
14239 /* Neon instruction encoders, in approximate order of appearance. */
14242 do_neon_dyadic_i_su (void)
14244 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14245 struct neon_type_el et
= neon_check_type (3, rs
,
14246 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14247 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14251 do_neon_dyadic_i64_su (void)
14253 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14254 struct neon_type_el et
= neon_check_type (3, rs
,
14255 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14256 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14260 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14263 unsigned size
= et
.size
>> 3;
14264 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14265 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14266 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14267 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14268 inst
.instruction
|= (isquad
!= 0) << 6;
14269 inst
.instruction
|= immbits
<< 16;
14270 inst
.instruction
|= (size
>> 3) << 7;
14271 inst
.instruction
|= (size
& 0x7) << 19;
14273 inst
.instruction
|= (uval
!= 0) << 24;
14275 neon_dp_fixup (&inst
);
14279 do_neon_shl_imm (void)
14281 if (!inst
.operands
[2].isreg
)
14283 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14284 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14285 int imm
= inst
.operands
[2].imm
;
14287 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14288 _("immediate out of range for shift"));
14289 NEON_ENCODE (IMMED
, inst
);
14290 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14294 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14295 struct neon_type_el et
= neon_check_type (3, rs
,
14296 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14299 /* VSHL/VQSHL 3-register variants have syntax such as:
14301 whereas other 3-register operations encoded by neon_three_same have
14304 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14306 tmp
= inst
.operands
[2].reg
;
14307 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14308 inst
.operands
[1].reg
= tmp
;
14309 NEON_ENCODE (INTEGER
, inst
);
14310 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14315 do_neon_qshl_imm (void)
14317 if (!inst
.operands
[2].isreg
)
14319 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14320 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14321 int imm
= inst
.operands
[2].imm
;
14323 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14324 _("immediate out of range for shift"));
14325 NEON_ENCODE (IMMED
, inst
);
14326 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14330 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14331 struct neon_type_el et
= neon_check_type (3, rs
,
14332 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14335 /* See note in do_neon_shl_imm. */
14336 tmp
= inst
.operands
[2].reg
;
14337 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14338 inst
.operands
[1].reg
= tmp
;
14339 NEON_ENCODE (INTEGER
, inst
);
14340 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14345 do_neon_rshl (void)
14347 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14348 struct neon_type_el et
= neon_check_type (3, rs
,
14349 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14352 tmp
= inst
.operands
[2].reg
;
14353 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14354 inst
.operands
[1].reg
= tmp
;
14355 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14359 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14361 /* Handle .I8 pseudo-instructions. */
14364 /* Unfortunately, this will make everything apart from zero out-of-range.
14365 FIXME is this the intended semantics? There doesn't seem much point in
14366 accepting .I8 if so. */
14367 immediate
|= immediate
<< 8;
14373 if (immediate
== (immediate
& 0x000000ff))
14375 *immbits
= immediate
;
14378 else if (immediate
== (immediate
& 0x0000ff00))
14380 *immbits
= immediate
>> 8;
14383 else if (immediate
== (immediate
& 0x00ff0000))
14385 *immbits
= immediate
>> 16;
14388 else if (immediate
== (immediate
& 0xff000000))
14390 *immbits
= immediate
>> 24;
14393 if ((immediate
& 0xffff) != (immediate
>> 16))
14394 goto bad_immediate
;
14395 immediate
&= 0xffff;
14398 if (immediate
== (immediate
& 0x000000ff))
14400 *immbits
= immediate
;
14403 else if (immediate
== (immediate
& 0x0000ff00))
14405 *immbits
= immediate
>> 8;
14410 first_error (_("immediate value out of range"));
14415 do_neon_logic (void)
14417 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14419 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14420 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14421 /* U bit and size field were set as part of the bitmask. */
14422 NEON_ENCODE (INTEGER
, inst
);
14423 neon_three_same (neon_quad (rs
), 0, -1);
14427 const int three_ops_form
= (inst
.operands
[2].present
14428 && !inst
.operands
[2].isreg
);
14429 const int immoperand
= (three_ops_form
? 2 : 1);
14430 enum neon_shape rs
= (three_ops_form
14431 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14432 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14433 struct neon_type_el et
= neon_check_type (2, rs
,
14434 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14435 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14439 if (et
.type
== NT_invtype
)
14442 if (three_ops_form
)
14443 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14444 _("first and second operands shall be the same register"));
14446 NEON_ENCODE (IMMED
, inst
);
14448 immbits
= inst
.operands
[immoperand
].imm
;
14451 /* .i64 is a pseudo-op, so the immediate must be a repeating
14453 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14454 inst
.operands
[immoperand
].reg
: 0))
14456 /* Set immbits to an invalid constant. */
14457 immbits
= 0xdeadbeef;
14464 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14468 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14472 /* Pseudo-instruction for VBIC. */
14473 neon_invert_size (&immbits
, 0, et
.size
);
14474 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14478 /* Pseudo-instruction for VORR. */
14479 neon_invert_size (&immbits
, 0, et
.size
);
14480 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14490 inst
.instruction
|= neon_quad (rs
) << 6;
14491 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14492 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14493 inst
.instruction
|= cmode
<< 8;
14494 neon_write_immbits (immbits
);
14496 neon_dp_fixup (&inst
);
14501 do_neon_bitfield (void)
14503 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14504 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14505 neon_three_same (neon_quad (rs
), 0, -1);
14509 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14512 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14513 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14515 if (et
.type
== NT_float
)
14517 NEON_ENCODE (FLOAT
, inst
);
14518 neon_three_same (neon_quad (rs
), 0, -1);
14522 NEON_ENCODE (INTEGER
, inst
);
14523 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14528 do_neon_dyadic_if_su (void)
14530 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14534 do_neon_dyadic_if_su_d (void)
14536 /* This version only allow D registers, but that constraint is enforced during
14537 operand parsing so we don't need to do anything extra here. */
14538 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14542 do_neon_dyadic_if_i_d (void)
14544 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14545 affected if we specify unsigned args. */
14546 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14549 enum vfp_or_neon_is_neon_bits
14552 NEON_CHECK_ARCH
= 2,
14553 NEON_CHECK_ARCH8
= 4
14556 /* Call this function if an instruction which may have belonged to the VFP or
14557 Neon instruction sets, but turned out to be a Neon instruction (due to the
14558 operand types involved, etc.). We have to check and/or fix-up a couple of
14561 - Make sure the user hasn't attempted to make a Neon instruction
14563 - Alter the value in the condition code field if necessary.
14564 - Make sure that the arch supports Neon instructions.
14566 Which of these operations take place depends on bits from enum
14567 vfp_or_neon_is_neon_bits.
14569 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14570 current instruction's condition is COND_ALWAYS, the condition field is
14571 changed to inst.uncond_value. This is necessary because instructions shared
14572 between VFP and Neon may be conditional for the VFP variants only, and the
14573 unconditional Neon version must have, e.g., 0xF in the condition field. */
14576 vfp_or_neon_is_neon (unsigned check
)
14578 /* Conditions are always legal in Thumb mode (IT blocks). */
14579 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14581 if (inst
.cond
!= COND_ALWAYS
)
14583 first_error (_(BAD_COND
));
14586 if (inst
.uncond_value
!= -1)
14587 inst
.instruction
|= inst
.uncond_value
<< 28;
14590 if ((check
& NEON_CHECK_ARCH
)
14591 && !mark_feature_used (&fpu_neon_ext_v1
))
14593 first_error (_(BAD_FPU
));
14597 if ((check
& NEON_CHECK_ARCH8
)
14598 && !mark_feature_used (&fpu_neon_ext_armv8
))
14600 first_error (_(BAD_FPU
));
14608 do_neon_addsub_if_i (void)
14610 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14613 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14616 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14617 affected if we specify unsigned args. */
14618 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14621 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14623 V<op> A,B (A is operand 0, B is operand 2)
14628 so handle that case specially. */
14631 neon_exchange_operands (void)
14633 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14634 if (inst
.operands
[1].present
)
14636 /* Swap operands[1] and operands[2]. */
14637 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14638 inst
.operands
[1] = inst
.operands
[2];
14639 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14643 inst
.operands
[1] = inst
.operands
[2];
14644 inst
.operands
[2] = inst
.operands
[0];
14649 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14651 if (inst
.operands
[2].isreg
)
14654 neon_exchange_operands ();
14655 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14659 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14660 struct neon_type_el et
= neon_check_type (2, rs
,
14661 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14663 NEON_ENCODE (IMMED
, inst
);
14664 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14665 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14666 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14667 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14668 inst
.instruction
|= neon_quad (rs
) << 6;
14669 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14670 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14672 neon_dp_fixup (&inst
);
14679 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14683 do_neon_cmp_inv (void)
14685 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14691 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14694 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14695 scalars, which are encoded in 5 bits, M : Rm.
14696 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14697 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14701 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14703 unsigned regno
= NEON_SCALAR_REG (scalar
);
14704 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14709 if (regno
> 7 || elno
> 3)
14711 return regno
| (elno
<< 3);
14714 if (regno
> 15 || elno
> 1)
14716 return regno
| (elno
<< 4);
14720 first_error (_("scalar out of range for multiply instruction"));
14726 /* Encode multiply / multiply-accumulate scalar instructions. */
14729 neon_mul_mac (struct neon_type_el et
, int ubit
)
14733 /* Give a more helpful error message if we have an invalid type. */
14734 if (et
.type
== NT_invtype
)
14737 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14740 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14741 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14742 inst
.instruction
|= LOW4 (scalar
);
14743 inst
.instruction
|= HI1 (scalar
) << 5;
14744 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14745 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14746 inst
.instruction
|= (ubit
!= 0) << 24;
14748 neon_dp_fixup (&inst
);
14752 do_neon_mac_maybe_scalar (void)
14754 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14757 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14760 if (inst
.operands
[2].isscalar
)
14762 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14763 struct neon_type_el et
= neon_check_type (3, rs
,
14764 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14765 NEON_ENCODE (SCALAR
, inst
);
14766 neon_mul_mac (et
, neon_quad (rs
));
14770 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14771 affected if we specify unsigned args. */
14772 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14777 do_neon_fmac (void)
14779 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14782 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14785 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14791 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14792 struct neon_type_el et
= neon_check_type (3, rs
,
14793 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14794 neon_three_same (neon_quad (rs
), 0, et
.size
);
14797 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14798 same types as the MAC equivalents. The polynomial type for this instruction
14799 is encoded the same as the integer type. */
14804 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14807 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14810 if (inst
.operands
[2].isscalar
)
14811 do_neon_mac_maybe_scalar ();
14813 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14817 do_neon_qdmulh (void)
14819 if (inst
.operands
[2].isscalar
)
14821 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14822 struct neon_type_el et
= neon_check_type (3, rs
,
14823 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14824 NEON_ENCODE (SCALAR
, inst
);
14825 neon_mul_mac (et
, neon_quad (rs
));
14829 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14830 struct neon_type_el et
= neon_check_type (3, rs
,
14831 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14832 NEON_ENCODE (INTEGER
, inst
);
14833 /* The U bit (rounding) comes from bit mask. */
14834 neon_three_same (neon_quad (rs
), 0, et
.size
);
14839 do_neon_fcmp_absolute (void)
14841 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14842 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14843 /* Size field comes from bit mask. */
14844 neon_three_same (neon_quad (rs
), 1, -1);
14848 do_neon_fcmp_absolute_inv (void)
14850 neon_exchange_operands ();
14851 do_neon_fcmp_absolute ();
14855 do_neon_step (void)
14857 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14858 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14859 neon_three_same (neon_quad (rs
), 0, -1);
14863 do_neon_abs_neg (void)
14865 enum neon_shape rs
;
14866 struct neon_type_el et
;
14868 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14871 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14874 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14875 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14877 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14878 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14879 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14880 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14881 inst
.instruction
|= neon_quad (rs
) << 6;
14882 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14883 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14885 neon_dp_fixup (&inst
);
14891 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14892 struct neon_type_el et
= neon_check_type (2, rs
,
14893 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14894 int imm
= inst
.operands
[2].imm
;
14895 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14896 _("immediate out of range for insert"));
14897 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14903 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14904 struct neon_type_el et
= neon_check_type (2, rs
,
14905 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14906 int imm
= inst
.operands
[2].imm
;
14907 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14908 _("immediate out of range for insert"));
14909 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14913 do_neon_qshlu_imm (void)
14915 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14916 struct neon_type_el et
= neon_check_type (2, rs
,
14917 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14918 int imm
= inst
.operands
[2].imm
;
14919 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14920 _("immediate out of range for shift"));
14921 /* Only encodes the 'U present' variant of the instruction.
14922 In this case, signed types have OP (bit 8) set to 0.
14923 Unsigned types have OP set to 1. */
14924 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14925 /* The rest of the bits are the same as other immediate shifts. */
14926 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14930 do_neon_qmovn (void)
14932 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14933 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14934 /* Saturating move where operands can be signed or unsigned, and the
14935 destination has the same signedness. */
14936 NEON_ENCODE (INTEGER
, inst
);
14937 if (et
.type
== NT_unsigned
)
14938 inst
.instruction
|= 0xc0;
14940 inst
.instruction
|= 0x80;
14941 neon_two_same (0, 1, et
.size
/ 2);
14945 do_neon_qmovun (void)
14947 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14948 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14949 /* Saturating move with unsigned results. Operands must be signed. */
14950 NEON_ENCODE (INTEGER
, inst
);
14951 neon_two_same (0, 1, et
.size
/ 2);
14955 do_neon_rshift_sat_narrow (void)
14957 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14958 or unsigned. If operands are unsigned, results must also be unsigned. */
14959 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14960 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14961 int imm
= inst
.operands
[2].imm
;
14962 /* This gets the bounds check, size encoding and immediate bits calculation
14966 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14967 VQMOVN.I<size> <Dd>, <Qm>. */
14970 inst
.operands
[2].present
= 0;
14971 inst
.instruction
= N_MNEM_vqmovn
;
14976 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14977 _("immediate out of range"));
14978 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14982 do_neon_rshift_sat_narrow_u (void)
14984 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14985 or unsigned. If operands are unsigned, results must also be unsigned. */
14986 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14987 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14988 int imm
= inst
.operands
[2].imm
;
14989 /* This gets the bounds check, size encoding and immediate bits calculation
14993 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14994 VQMOVUN.I<size> <Dd>, <Qm>. */
14997 inst
.operands
[2].present
= 0;
14998 inst
.instruction
= N_MNEM_vqmovun
;
15003 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15004 _("immediate out of range"));
15005 /* FIXME: The manual is kind of unclear about what value U should have in
15006 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15008 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15012 do_neon_movn (void)
15014 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15015 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15016 NEON_ENCODE (INTEGER
, inst
);
15017 neon_two_same (0, 1, et
.size
/ 2);
15021 do_neon_rshift_narrow (void)
15023 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15024 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15025 int imm
= inst
.operands
[2].imm
;
15026 /* This gets the bounds check, size encoding and immediate bits calculation
15030 /* If immediate is zero then we are a pseudo-instruction for
15031 VMOVN.I<size> <Dd>, <Qm> */
15034 inst
.operands
[2].present
= 0;
15035 inst
.instruction
= N_MNEM_vmovn
;
15040 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15041 _("immediate out of range for narrowing operation"));
15042 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15046 do_neon_shll (void)
15048 /* FIXME: Type checking when lengthening. */
15049 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15050 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15051 unsigned imm
= inst
.operands
[2].imm
;
15053 if (imm
== et
.size
)
15055 /* Maximum shift variant. */
15056 NEON_ENCODE (INTEGER
, inst
);
15057 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15058 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15059 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15060 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15061 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15063 neon_dp_fixup (&inst
);
15067 /* A more-specific type check for non-max versions. */
15068 et
= neon_check_type (2, NS_QDI
,
15069 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15070 NEON_ENCODE (IMMED
, inst
);
15071 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15075 /* Check the various types for the VCVT instruction, and return which version
15076 the current instruction is. */
15078 #define CVT_FLAVOUR_VAR \
15079 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15080 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15081 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15082 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15083 /* Half-precision conversions. */ \
15084 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15085 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15086 /* VFP instructions. */ \
15087 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15088 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15089 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15090 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15091 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15092 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15093 /* VFP instructions with bitshift. */ \
15094 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15095 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15096 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15097 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15098 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15099 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15100 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15101 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15103 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15104 neon_cvt_flavour_##C,
15106 /* The different types of conversions we can do. */
15107 enum neon_cvt_flavour
15110 neon_cvt_flavour_invalid
,
15111 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15116 static enum neon_cvt_flavour
15117 get_neon_cvt_flavour (enum neon_shape rs
)
15119 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15120 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15121 if (et.type != NT_invtype) \
15123 inst.error = NULL; \
15124 return (neon_cvt_flavour_##C); \
15127 struct neon_type_el et
;
15128 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15129 || rs
== NS_FF
) ? N_VFP
: 0;
15130 /* The instruction versions which take an immediate take one register
15131 argument, which is extended to the width of the full register. Thus the
15132 "source" and "destination" registers must have the same width. Hack that
15133 here by making the size equal to the key (wider, in this case) operand. */
15134 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15138 return neon_cvt_flavour_invalid
;
15153 /* Neon-syntax VFP conversions. */
15156 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15158 const char *opname
= 0;
15160 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15162 /* Conversions with immediate bitshift. */
15163 const char *enc
[] =
15165 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15171 if (flavour
< (int) ARRAY_SIZE (enc
))
15173 opname
= enc
[flavour
];
15174 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15175 _("operands 0 and 1 must be the same register"));
15176 inst
.operands
[1] = inst
.operands
[2];
15177 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15182 /* Conversions without bitshift. */
15183 const char *enc
[] =
15185 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15191 if (flavour
< (int) ARRAY_SIZE (enc
))
15192 opname
= enc
[flavour
];
15196 do_vfp_nsyn_opcode (opname
);
15200 do_vfp_nsyn_cvtz (void)
15202 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15203 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15204 const char *enc
[] =
15206 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15212 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15213 do_vfp_nsyn_opcode (enc
[flavour
]);
15217 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15218 enum neon_cvt_mode mode
)
15223 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15224 D register operands. */
15225 if (flavour
== neon_cvt_flavour_s32_f64
15226 || flavour
== neon_cvt_flavour_u32_f64
)
15227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15230 set_it_insn_type (OUTSIDE_IT_INSN
);
15234 case neon_cvt_flavour_s32_f64
:
15238 case neon_cvt_flavour_s32_f32
:
15242 case neon_cvt_flavour_u32_f64
:
15246 case neon_cvt_flavour_u32_f32
:
15251 first_error (_("invalid instruction shape"));
15257 case neon_cvt_mode_a
: rm
= 0; break;
15258 case neon_cvt_mode_n
: rm
= 1; break;
15259 case neon_cvt_mode_p
: rm
= 2; break;
15260 case neon_cvt_mode_m
: rm
= 3; break;
15261 default: first_error (_("invalid rounding mode")); return;
15264 NEON_ENCODE (FPV8
, inst
);
15265 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15266 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15267 inst
.instruction
|= sz
<< 8;
15268 inst
.instruction
|= op
<< 7;
15269 inst
.instruction
|= rm
<< 16;
15270 inst
.instruction
|= 0xf0000000;
15271 inst
.is_neon
= TRUE
;
15275 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15277 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15278 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15279 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15281 /* PR11109: Handle round-to-zero for VCVT conversions. */
15282 if (mode
== neon_cvt_mode_z
15283 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15284 && (flavour
== neon_cvt_flavour_s32_f32
15285 || flavour
== neon_cvt_flavour_u32_f32
15286 || flavour
== neon_cvt_flavour_s32_f64
15287 || flavour
== neon_cvt_flavour_u32_f64
)
15288 && (rs
== NS_FD
|| rs
== NS_FF
))
15290 do_vfp_nsyn_cvtz ();
15294 /* VFP rather than Neon conversions. */
15295 if (flavour
>= neon_cvt_flavour_first_fp
)
15297 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15298 do_vfp_nsyn_cvt (rs
, flavour
);
15300 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15311 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15313 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15316 /* Fixed-point conversion with #0 immediate is encoded as an
15317 integer conversion. */
15318 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15320 immbits
= 32 - inst
.operands
[2].imm
;
15321 NEON_ENCODE (IMMED
, inst
);
15322 if (flavour
!= neon_cvt_flavour_invalid
)
15323 inst
.instruction
|= enctab
[flavour
];
15324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15325 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15326 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15327 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15328 inst
.instruction
|= neon_quad (rs
) << 6;
15329 inst
.instruction
|= 1 << 21;
15330 inst
.instruction
|= immbits
<< 16;
15332 neon_dp_fixup (&inst
);
15338 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15340 NEON_ENCODE (FLOAT
, inst
);
15341 set_it_insn_type (OUTSIDE_IT_INSN
);
15343 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15346 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15347 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15348 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15349 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15350 inst
.instruction
|= neon_quad (rs
) << 6;
15351 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15352 inst
.instruction
|= mode
<< 8;
15354 inst
.instruction
|= 0xfc000000;
15356 inst
.instruction
|= 0xf0000000;
15362 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15364 NEON_ENCODE (INTEGER
, inst
);
15366 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15369 if (flavour
!= neon_cvt_flavour_invalid
)
15370 inst
.instruction
|= enctab
[flavour
];
15372 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15374 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15375 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15376 inst
.instruction
|= neon_quad (rs
) << 6;
15377 inst
.instruction
|= 2 << 18;
15379 neon_dp_fixup (&inst
);
15384 /* Half-precision conversions for Advanced SIMD -- neon. */
15389 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15391 as_bad (_("operand size must match register width"));
15396 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15398 as_bad (_("operand size must match register width"));
15403 inst
.instruction
= 0x3b60600;
15405 inst
.instruction
= 0x3b60700;
15407 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15408 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15409 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15410 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15411 neon_dp_fixup (&inst
);
15415 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15416 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15417 do_vfp_nsyn_cvt (rs
, flavour
);
15419 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15424 do_neon_cvtr (void)
15426 do_neon_cvt_1 (neon_cvt_mode_x
);
15432 do_neon_cvt_1 (neon_cvt_mode_z
);
15436 do_neon_cvta (void)
15438 do_neon_cvt_1 (neon_cvt_mode_a
);
15442 do_neon_cvtn (void)
15444 do_neon_cvt_1 (neon_cvt_mode_n
);
15448 do_neon_cvtp (void)
15450 do_neon_cvt_1 (neon_cvt_mode_p
);
15454 do_neon_cvtm (void)
15456 do_neon_cvt_1 (neon_cvt_mode_m
);
15460 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15463 mark_feature_used (&fpu_vfp_ext_armv8
);
15465 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15466 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15467 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15468 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15469 inst
.instruction
|= to
? 0x10000 : 0;
15470 inst
.instruction
|= t
? 0x80 : 0;
15471 inst
.instruction
|= is_double
? 0x100 : 0;
15472 do_vfp_cond_or_thumb ();
15476 do_neon_cvttb_1 (bfd_boolean t
)
15478 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15482 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15485 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15487 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15490 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15492 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15494 /* The VCVTB and VCVTT instructions with D-register operands
15495 don't work for SP only targets. */
15496 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15500 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15502 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15504 /* The VCVTB and VCVTT instructions with D-register operands
15505 don't work for SP only targets. */
15506 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15510 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15517 do_neon_cvtb (void)
15519 do_neon_cvttb_1 (FALSE
);
15524 do_neon_cvtt (void)
15526 do_neon_cvttb_1 (TRUE
);
15530 neon_move_immediate (void)
15532 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15533 struct neon_type_el et
= neon_check_type (2, rs
,
15534 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15535 unsigned immlo
, immhi
= 0, immbits
;
15536 int op
, cmode
, float_p
;
15538 constraint (et
.type
== NT_invtype
,
15539 _("operand size must be specified for immediate VMOV"));
15541 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15542 op
= (inst
.instruction
& (1 << 5)) != 0;
15544 immlo
= inst
.operands
[1].imm
;
15545 if (inst
.operands
[1].regisimm
)
15546 immhi
= inst
.operands
[1].reg
;
15548 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15549 _("immediate has bits set outside the operand size"));
15551 float_p
= inst
.operands
[1].immisfloat
;
15553 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15554 et
.size
, et
.type
)) == FAIL
)
15556 /* Invert relevant bits only. */
15557 neon_invert_size (&immlo
, &immhi
, et
.size
);
15558 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15559 with one or the other; those cases are caught by
15560 neon_cmode_for_move_imm. */
15562 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15563 &op
, et
.size
, et
.type
)) == FAIL
)
15565 first_error (_("immediate out of range"));
15570 inst
.instruction
&= ~(1 << 5);
15571 inst
.instruction
|= op
<< 5;
15573 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15574 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15575 inst
.instruction
|= neon_quad (rs
) << 6;
15576 inst
.instruction
|= cmode
<< 8;
15578 neon_write_immbits (immbits
);
15584 if (inst
.operands
[1].isreg
)
15586 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15588 NEON_ENCODE (INTEGER
, inst
);
15589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15591 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15592 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15593 inst
.instruction
|= neon_quad (rs
) << 6;
15597 NEON_ENCODE (IMMED
, inst
);
15598 neon_move_immediate ();
15601 neon_dp_fixup (&inst
);
15604 /* Encode instructions of form:
15606 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15607 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15610 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15612 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15613 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15614 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15615 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15616 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15617 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15618 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15619 inst
.instruction
|= neon_logbits (size
) << 20;
15621 neon_dp_fixup (&inst
);
15625 do_neon_dyadic_long (void)
15627 /* FIXME: Type checking for lengthening op. */
15628 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15629 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15630 neon_mixed_length (et
, et
.size
);
15634 do_neon_abal (void)
15636 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15637 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15638 neon_mixed_length (et
, et
.size
);
15642 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15644 if (inst
.operands
[2].isscalar
)
15646 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15647 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15648 NEON_ENCODE (SCALAR
, inst
);
15649 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15653 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15654 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15655 NEON_ENCODE (INTEGER
, inst
);
15656 neon_mixed_length (et
, et
.size
);
15661 do_neon_mac_maybe_scalar_long (void)
15663 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15667 do_neon_dyadic_wide (void)
15669 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15670 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15671 neon_mixed_length (et
, et
.size
);
15675 do_neon_dyadic_narrow (void)
15677 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15678 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15679 /* Operand sign is unimportant, and the U bit is part of the opcode,
15680 so force the operand type to integer. */
15681 et
.type
= NT_integer
;
15682 neon_mixed_length (et
, et
.size
/ 2);
15686 do_neon_mul_sat_scalar_long (void)
15688 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15692 do_neon_vmull (void)
15694 if (inst
.operands
[2].isscalar
)
15695 do_neon_mac_maybe_scalar_long ();
15698 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15699 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15701 if (et
.type
== NT_poly
)
15702 NEON_ENCODE (POLY
, inst
);
15704 NEON_ENCODE (INTEGER
, inst
);
15706 /* For polynomial encoding the U bit must be zero, and the size must
15707 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15708 obviously, as 0b10). */
15711 /* Check we're on the correct architecture. */
15712 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15714 _("Instruction form not available on this architecture.");
15719 neon_mixed_length (et
, et
.size
);
15726 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15727 struct neon_type_el et
= neon_check_type (3, rs
,
15728 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15729 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15731 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15732 _("shift out of range"));
15733 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15734 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15735 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15736 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15737 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15738 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15739 inst
.instruction
|= neon_quad (rs
) << 6;
15740 inst
.instruction
|= imm
<< 8;
15742 neon_dp_fixup (&inst
);
15748 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15749 struct neon_type_el et
= neon_check_type (2, rs
,
15750 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15751 unsigned op
= (inst
.instruction
>> 7) & 3;
15752 /* N (width of reversed regions) is encoded as part of the bitmask. We
15753 extract it here to check the elements to be reversed are smaller.
15754 Otherwise we'd get a reserved instruction. */
15755 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15756 gas_assert (elsize
!= 0);
15757 constraint (et
.size
>= elsize
,
15758 _("elements must be smaller than reversal region"));
15759 neon_two_same (neon_quad (rs
), 1, et
.size
);
15765 if (inst
.operands
[1].isscalar
)
15767 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15768 struct neon_type_el et
= neon_check_type (2, rs
,
15769 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15770 unsigned sizebits
= et
.size
>> 3;
15771 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15772 int logsize
= neon_logbits (et
.size
);
15773 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15775 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15778 NEON_ENCODE (SCALAR
, inst
);
15779 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15780 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15781 inst
.instruction
|= LOW4 (dm
);
15782 inst
.instruction
|= HI1 (dm
) << 5;
15783 inst
.instruction
|= neon_quad (rs
) << 6;
15784 inst
.instruction
|= x
<< 17;
15785 inst
.instruction
|= sizebits
<< 16;
15787 neon_dp_fixup (&inst
);
15791 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15792 struct neon_type_el et
= neon_check_type (2, rs
,
15793 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15794 /* Duplicate ARM register to lanes of vector. */
15795 NEON_ENCODE (ARMREG
, inst
);
15798 case 8: inst
.instruction
|= 0x400000; break;
15799 case 16: inst
.instruction
|= 0x000020; break;
15800 case 32: inst
.instruction
|= 0x000000; break;
15803 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15804 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15805 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15806 inst
.instruction
|= neon_quad (rs
) << 21;
15807 /* The encoding for this instruction is identical for the ARM and Thumb
15808 variants, except for the condition field. */
15809 do_vfp_cond_or_thumb ();
15813 /* VMOV has particularly many variations. It can be one of:
15814 0. VMOV<c><q> <Qd>, <Qm>
15815 1. VMOV<c><q> <Dd>, <Dm>
15816 (Register operations, which are VORR with Rm = Rn.)
15817 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15818 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15820 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15821 (ARM register to scalar.)
15822 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15823 (Two ARM registers to vector.)
15824 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15825 (Scalar to ARM register.)
15826 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15827 (Vector to two ARM registers.)
15828 8. VMOV.F32 <Sd>, <Sm>
15829 9. VMOV.F64 <Dd>, <Dm>
15830 (VFP register moves.)
15831 10. VMOV.F32 <Sd>, #imm
15832 11. VMOV.F64 <Dd>, #imm
15833 (VFP float immediate load.)
15834 12. VMOV <Rd>, <Sm>
15835 (VFP single to ARM reg.)
15836 13. VMOV <Sd>, <Rm>
15837 (ARM reg to VFP single.)
15838 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15839 (Two ARM regs to two VFP singles.)
15840 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15841 (Two VFP singles to two ARM regs.)
15843 These cases can be disambiguated using neon_select_shape, except cases 1/9
15844 and 3/11 which depend on the operand type too.
15846 All the encoded bits are hardcoded by this function.
15848 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15849 Cases 5, 7 may be used with VFPv2 and above.
15851 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15852 can specify a type where it doesn't make sense to, and is ignored). */
15857 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15858 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15860 struct neon_type_el et
;
15861 const char *ldconst
= 0;
15865 case NS_DD
: /* case 1/9. */
15866 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15867 /* It is not an error here if no type is given. */
15869 if (et
.type
== NT_float
&& et
.size
== 64)
15871 do_vfp_nsyn_opcode ("fcpyd");
15874 /* fall through. */
15876 case NS_QQ
: /* case 0/1. */
15878 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15880 /* The architecture manual I have doesn't explicitly state which
15881 value the U bit should have for register->register moves, but
15882 the equivalent VORR instruction has U = 0, so do that. */
15883 inst
.instruction
= 0x0200110;
15884 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15885 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15886 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15887 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15888 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15889 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15890 inst
.instruction
|= neon_quad (rs
) << 6;
15892 neon_dp_fixup (&inst
);
15896 case NS_DI
: /* case 3/11. */
15897 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15899 if (et
.type
== NT_float
&& et
.size
== 64)
15901 /* case 11 (fconstd). */
15902 ldconst
= "fconstd";
15903 goto encode_fconstd
;
15905 /* fall through. */
15907 case NS_QI
: /* case 2/3. */
15908 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15910 inst
.instruction
= 0x0800010;
15911 neon_move_immediate ();
15912 neon_dp_fixup (&inst
);
15915 case NS_SR
: /* case 4. */
15917 unsigned bcdebits
= 0;
15919 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15920 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15922 /* .<size> is optional here, defaulting to .32. */
15923 if (inst
.vectype
.elems
== 0
15924 && inst
.operands
[0].vectype
.type
== NT_invtype
15925 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15927 inst
.vectype
.el
[0].type
= NT_untyped
;
15928 inst
.vectype
.el
[0].size
= 32;
15929 inst
.vectype
.elems
= 1;
15932 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15933 logsize
= neon_logbits (et
.size
);
15935 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15937 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15938 && et
.size
!= 32, _(BAD_FPU
));
15939 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15940 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15944 case 8: bcdebits
= 0x8; break;
15945 case 16: bcdebits
= 0x1; break;
15946 case 32: bcdebits
= 0x0; break;
15950 bcdebits
|= x
<< logsize
;
15952 inst
.instruction
= 0xe000b10;
15953 do_vfp_cond_or_thumb ();
15954 inst
.instruction
|= LOW4 (dn
) << 16;
15955 inst
.instruction
|= HI1 (dn
) << 7;
15956 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15957 inst
.instruction
|= (bcdebits
& 3) << 5;
15958 inst
.instruction
|= (bcdebits
>> 2) << 21;
15962 case NS_DRR
: /* case 5 (fmdrr). */
15963 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15966 inst
.instruction
= 0xc400b10;
15967 do_vfp_cond_or_thumb ();
15968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15970 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15971 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15974 case NS_RS
: /* case 6. */
15977 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15978 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15979 unsigned abcdebits
= 0;
15981 /* .<dt> is optional here, defaulting to .32. */
15982 if (inst
.vectype
.elems
== 0
15983 && inst
.operands
[0].vectype
.type
== NT_invtype
15984 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15986 inst
.vectype
.el
[0].type
= NT_untyped
;
15987 inst
.vectype
.el
[0].size
= 32;
15988 inst
.vectype
.elems
= 1;
15991 et
= neon_check_type (2, NS_NULL
,
15992 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15993 logsize
= neon_logbits (et
.size
);
15995 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15997 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15998 && et
.size
!= 32, _(BAD_FPU
));
15999 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16000 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16004 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16005 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16006 case 32: abcdebits
= 0x00; break;
16010 abcdebits
|= x
<< logsize
;
16011 inst
.instruction
= 0xe100b10;
16012 do_vfp_cond_or_thumb ();
16013 inst
.instruction
|= LOW4 (dn
) << 16;
16014 inst
.instruction
|= HI1 (dn
) << 7;
16015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16016 inst
.instruction
|= (abcdebits
& 3) << 5;
16017 inst
.instruction
|= (abcdebits
>> 2) << 21;
16021 case NS_RRD
: /* case 7 (fmrrd). */
16022 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16025 inst
.instruction
= 0xc500b10;
16026 do_vfp_cond_or_thumb ();
16027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16028 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16029 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16030 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16033 case NS_FF
: /* case 8 (fcpys). */
16034 do_vfp_nsyn_opcode ("fcpys");
16037 case NS_FI
: /* case 10 (fconsts). */
16038 ldconst
= "fconsts";
16040 if (is_quarter_float (inst
.operands
[1].imm
))
16042 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16043 do_vfp_nsyn_opcode (ldconst
);
16046 first_error (_("immediate out of range"));
16049 case NS_RF
: /* case 12 (fmrs). */
16050 do_vfp_nsyn_opcode ("fmrs");
16053 case NS_FR
: /* case 13 (fmsr). */
16054 do_vfp_nsyn_opcode ("fmsr");
16057 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16058 (one of which is a list), but we have parsed four. Do some fiddling to
16059 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16061 case NS_RRFF
: /* case 14 (fmrrs). */
16062 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16063 _("VFP registers must be adjacent"));
16064 inst
.operands
[2].imm
= 2;
16065 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16066 do_vfp_nsyn_opcode ("fmrrs");
16069 case NS_FFRR
: /* case 15 (fmsrr). */
16070 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16071 _("VFP registers must be adjacent"));
16072 inst
.operands
[1] = inst
.operands
[2];
16073 inst
.operands
[2] = inst
.operands
[3];
16074 inst
.operands
[0].imm
= 2;
16075 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16076 do_vfp_nsyn_opcode ("fmsrr");
16080 /* neon_select_shape has determined that the instruction
16081 shape is wrong and has already set the error message. */
16090 do_neon_rshift_round_imm (void)
16092 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16093 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16094 int imm
= inst
.operands
[2].imm
;
16096 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16099 inst
.operands
[2].present
= 0;
16104 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16105 _("immediate out of range for shift"));
16106 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16111 do_neon_movl (void)
16113 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16114 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16115 unsigned sizebits
= et
.size
>> 3;
16116 inst
.instruction
|= sizebits
<< 19;
16117 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16123 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16124 struct neon_type_el et
= neon_check_type (2, rs
,
16125 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16126 NEON_ENCODE (INTEGER
, inst
);
16127 neon_two_same (neon_quad (rs
), 1, et
.size
);
16131 do_neon_zip_uzp (void)
16133 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16134 struct neon_type_el et
= neon_check_type (2, rs
,
16135 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16136 if (rs
== NS_DD
&& et
.size
== 32)
16138 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16139 inst
.instruction
= N_MNEM_vtrn
;
16143 neon_two_same (neon_quad (rs
), 1, et
.size
);
16147 do_neon_sat_abs_neg (void)
16149 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16150 struct neon_type_el et
= neon_check_type (2, rs
,
16151 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16152 neon_two_same (neon_quad (rs
), 1, et
.size
);
16156 do_neon_pair_long (void)
16158 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16159 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16160 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16161 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16162 neon_two_same (neon_quad (rs
), 1, et
.size
);
16166 do_neon_recip_est (void)
16168 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16169 struct neon_type_el et
= neon_check_type (2, rs
,
16170 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16171 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16172 neon_two_same (neon_quad (rs
), 1, et
.size
);
16178 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16179 struct neon_type_el et
= neon_check_type (2, rs
,
16180 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16181 neon_two_same (neon_quad (rs
), 1, et
.size
);
16187 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16188 struct neon_type_el et
= neon_check_type (2, rs
,
16189 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16190 neon_two_same (neon_quad (rs
), 1, et
.size
);
16196 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16197 struct neon_type_el et
= neon_check_type (2, rs
,
16198 N_EQK
| N_INT
, N_8
| N_KEY
);
16199 neon_two_same (neon_quad (rs
), 1, et
.size
);
16205 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16206 neon_two_same (neon_quad (rs
), 1, -1);
16210 do_neon_tbl_tbx (void)
16212 unsigned listlenbits
;
16213 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16215 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16217 first_error (_("bad list length for table lookup"));
16221 listlenbits
= inst
.operands
[1].imm
- 1;
16222 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16223 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16224 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16225 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16226 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16227 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16228 inst
.instruction
|= listlenbits
<< 8;
16230 neon_dp_fixup (&inst
);
16234 do_neon_ldm_stm (void)
16236 /* P, U and L bits are part of bitmask. */
16237 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16238 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16240 if (inst
.operands
[1].issingle
)
16242 do_vfp_nsyn_ldm_stm (is_dbmode
);
16246 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16247 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16249 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16250 _("register list must contain at least 1 and at most 16 "
16253 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16254 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16255 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16256 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16258 inst
.instruction
|= offsetbits
;
16260 do_vfp_cond_or_thumb ();
16264 do_neon_ldr_str (void)
16266 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16268 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16269 And is UNPREDICTABLE in thumb mode. */
16271 && inst
.operands
[1].reg
== REG_PC
16272 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16275 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16276 else if (warn_on_deprecated
)
16277 as_tsktsk (_("Use of PC here is deprecated"));
16280 if (inst
.operands
[0].issingle
)
16283 do_vfp_nsyn_opcode ("flds");
16285 do_vfp_nsyn_opcode ("fsts");
16290 do_vfp_nsyn_opcode ("fldd");
16292 do_vfp_nsyn_opcode ("fstd");
16296 /* "interleave" version also handles non-interleaving register VLD1/VST1
16300 do_neon_ld_st_interleave (void)
16302 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16303 N_8
| N_16
| N_32
| N_64
);
16304 unsigned alignbits
= 0;
16306 /* The bits in this table go:
16307 0: register stride of one (0) or two (1)
16308 1,2: register list length, minus one (1, 2, 3, 4).
16309 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16310 We use -1 for invalid entries. */
16311 const int typetable
[] =
16313 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16314 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16315 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16316 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16320 if (et
.type
== NT_invtype
)
16323 if (inst
.operands
[1].immisalign
)
16324 switch (inst
.operands
[1].imm
>> 8)
16326 case 64: alignbits
= 1; break;
16328 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16329 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16330 goto bad_alignment
;
16334 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16335 goto bad_alignment
;
16340 first_error (_("bad alignment"));
16344 inst
.instruction
|= alignbits
<< 4;
16345 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16347 /* Bits [4:6] of the immediate in a list specifier encode register stride
16348 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16349 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16350 up the right value for "type" in a table based on this value and the given
16351 list style, then stick it back. */
16352 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16353 | (((inst
.instruction
>> 8) & 3) << 3);
16355 typebits
= typetable
[idx
];
16357 constraint (typebits
== -1, _("bad list type for instruction"));
16358 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16359 _("bad element type for instruction"));
16361 inst
.instruction
&= ~0xf00;
16362 inst
.instruction
|= typebits
<< 8;
16365 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16366 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16367 otherwise. The variable arguments are a list of pairs of legal (size, align)
16368 values, terminated with -1. */
16371 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16374 int result
= FAIL
, thissize
, thisalign
;
16376 if (!inst
.operands
[1].immisalign
)
16382 va_start (ap
, do_align
);
16386 thissize
= va_arg (ap
, int);
16387 if (thissize
== -1)
16389 thisalign
= va_arg (ap
, int);
16391 if (size
== thissize
&& align
== thisalign
)
16394 while (result
!= SUCCESS
);
16398 if (result
== SUCCESS
)
16401 first_error (_("unsupported alignment for instruction"));
16407 do_neon_ld_st_lane (void)
16409 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16410 int align_good
, do_align
= 0;
16411 int logsize
= neon_logbits (et
.size
);
16412 int align
= inst
.operands
[1].imm
>> 8;
16413 int n
= (inst
.instruction
>> 8) & 3;
16414 int max_el
= 64 / et
.size
;
16416 if (et
.type
== NT_invtype
)
16419 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16420 _("bad list length"));
16421 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16422 _("scalar index out of range"));
16423 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16425 _("stride of 2 unavailable when element size is 8"));
16429 case 0: /* VLD1 / VST1. */
16430 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16432 if (align_good
== FAIL
)
16436 unsigned alignbits
= 0;
16439 case 16: alignbits
= 0x1; break;
16440 case 32: alignbits
= 0x3; break;
16443 inst
.instruction
|= alignbits
<< 4;
16447 case 1: /* VLD2 / VST2. */
16448 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16450 if (align_good
== FAIL
)
16453 inst
.instruction
|= 1 << 4;
16456 case 2: /* VLD3 / VST3. */
16457 constraint (inst
.operands
[1].immisalign
,
16458 _("can't use alignment with this instruction"));
16461 case 3: /* VLD4 / VST4. */
16462 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16463 16, 64, 32, 64, 32, 128, -1);
16464 if (align_good
== FAIL
)
16468 unsigned alignbits
= 0;
16471 case 8: alignbits
= 0x1; break;
16472 case 16: alignbits
= 0x1; break;
16473 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16476 inst
.instruction
|= alignbits
<< 4;
16483 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16484 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16485 inst
.instruction
|= 1 << (4 + logsize
);
16487 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16488 inst
.instruction
|= logsize
<< 10;
16491 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16494 do_neon_ld_dup (void)
16496 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16497 int align_good
, do_align
= 0;
16499 if (et
.type
== NT_invtype
)
16502 switch ((inst
.instruction
>> 8) & 3)
16504 case 0: /* VLD1. */
16505 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16506 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16507 &do_align
, 16, 16, 32, 32, -1);
16508 if (align_good
== FAIL
)
16510 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16513 case 2: inst
.instruction
|= 1 << 5; break;
16514 default: first_error (_("bad list length")); return;
16516 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16519 case 1: /* VLD2. */
16520 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16521 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16522 if (align_good
== FAIL
)
16524 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16525 _("bad list length"));
16526 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16527 inst
.instruction
|= 1 << 5;
16528 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16531 case 2: /* VLD3. */
16532 constraint (inst
.operands
[1].immisalign
,
16533 _("can't use alignment with this instruction"));
16534 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16535 _("bad list length"));
16536 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16537 inst
.instruction
|= 1 << 5;
16538 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16541 case 3: /* VLD4. */
16543 int align
= inst
.operands
[1].imm
>> 8;
16544 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16545 16, 64, 32, 64, 32, 128, -1);
16546 if (align_good
== FAIL
)
16548 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16549 _("bad list length"));
16550 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16551 inst
.instruction
|= 1 << 5;
16552 if (et
.size
== 32 && align
== 128)
16553 inst
.instruction
|= 0x3 << 6;
16555 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16562 inst
.instruction
|= do_align
<< 4;
16565 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16566 apart from bits [11:4]. */
16569 do_neon_ldx_stx (void)
16571 if (inst
.operands
[1].isreg
)
16572 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16574 switch (NEON_LANE (inst
.operands
[0].imm
))
16576 case NEON_INTERLEAVE_LANES
:
16577 NEON_ENCODE (INTERLV
, inst
);
16578 do_neon_ld_st_interleave ();
16581 case NEON_ALL_LANES
:
16582 NEON_ENCODE (DUP
, inst
);
16583 if (inst
.instruction
== N_INV
)
16585 first_error ("only loads support such operands");
16592 NEON_ENCODE (LANE
, inst
);
16593 do_neon_ld_st_lane ();
16596 /* L bit comes from bit mask. */
16597 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16598 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16599 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16601 if (inst
.operands
[1].postind
)
16603 int postreg
= inst
.operands
[1].imm
& 0xf;
16604 constraint (!inst
.operands
[1].immisreg
,
16605 _("post-index must be a register"));
16606 constraint (postreg
== 0xd || postreg
== 0xf,
16607 _("bad register for post-index"));
16608 inst
.instruction
|= postreg
;
16612 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16613 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16614 || inst
.reloc
.exp
.X_add_number
!= 0,
16617 if (inst
.operands
[1].writeback
)
16619 inst
.instruction
|= 0xd;
16622 inst
.instruction
|= 0xf;
16626 inst
.instruction
|= 0xf9000000;
16628 inst
.instruction
|= 0xf4000000;
16633 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16635 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16636 D register operands. */
16637 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16638 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16641 NEON_ENCODE (FPV8
, inst
);
16644 do_vfp_sp_dyadic ();
16646 do_vfp_dp_rd_rn_rm ();
16649 inst
.instruction
|= 0x100;
16651 inst
.instruction
|= 0xf0000000;
16657 set_it_insn_type (OUTSIDE_IT_INSN
);
16659 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16660 first_error (_("invalid instruction shape"));
16666 set_it_insn_type (OUTSIDE_IT_INSN
);
16668 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16671 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16674 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16678 do_vrint_1 (enum neon_cvt_mode mode
)
16680 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16681 struct neon_type_el et
;
16686 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16687 D register operands. */
16688 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16692 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16693 if (et
.type
!= NT_invtype
)
16695 /* VFP encodings. */
16696 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16697 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16698 set_it_insn_type (OUTSIDE_IT_INSN
);
16700 NEON_ENCODE (FPV8
, inst
);
16702 do_vfp_sp_monadic ();
16704 do_vfp_dp_rd_rm ();
16708 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16709 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16710 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16711 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16712 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16713 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16714 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16718 inst
.instruction
|= (rs
== NS_DD
) << 8;
16719 do_vfp_cond_or_thumb ();
16723 /* Neon encodings (or something broken...). */
16725 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16727 if (et
.type
== NT_invtype
)
16730 set_it_insn_type (OUTSIDE_IT_INSN
);
16731 NEON_ENCODE (FLOAT
, inst
);
16733 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16736 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16738 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16739 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16740 inst
.instruction
|= neon_quad (rs
) << 6;
16743 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16744 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16745 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16746 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16747 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16748 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16749 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16754 inst
.instruction
|= 0xfc000000;
16756 inst
.instruction
|= 0xf0000000;
16763 do_vrint_1 (neon_cvt_mode_x
);
16769 do_vrint_1 (neon_cvt_mode_z
);
16775 do_vrint_1 (neon_cvt_mode_r
);
16781 do_vrint_1 (neon_cvt_mode_a
);
16787 do_vrint_1 (neon_cvt_mode_n
);
16793 do_vrint_1 (neon_cvt_mode_p
);
16799 do_vrint_1 (neon_cvt_mode_m
);
16802 /* Crypto v1 instructions. */
16804 do_crypto_2op_1 (unsigned elttype
, int op
)
16806 set_it_insn_type (OUTSIDE_IT_INSN
);
16808 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16814 NEON_ENCODE (INTEGER
, inst
);
16815 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16816 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16817 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16818 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16820 inst
.instruction
|= op
<< 6;
16823 inst
.instruction
|= 0xfc000000;
16825 inst
.instruction
|= 0xf0000000;
16829 do_crypto_3op_1 (int u
, int op
)
16831 set_it_insn_type (OUTSIDE_IT_INSN
);
16833 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16834 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16839 NEON_ENCODE (INTEGER
, inst
);
16840 neon_three_same (1, u
, 8 << op
);
16846 do_crypto_2op_1 (N_8
, 0);
16852 do_crypto_2op_1 (N_8
, 1);
16858 do_crypto_2op_1 (N_8
, 2);
16864 do_crypto_2op_1 (N_8
, 3);
16870 do_crypto_3op_1 (0, 0);
16876 do_crypto_3op_1 (0, 1);
16882 do_crypto_3op_1 (0, 2);
16888 do_crypto_3op_1 (0, 3);
16894 do_crypto_3op_1 (1, 0);
16900 do_crypto_3op_1 (1, 1);
16904 do_sha256su1 (void)
16906 do_crypto_3op_1 (1, 2);
16912 do_crypto_2op_1 (N_32
, -1);
16918 do_crypto_2op_1 (N_32
, 0);
16922 do_sha256su0 (void)
16924 do_crypto_2op_1 (N_32
, 1);
16928 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16930 unsigned int Rd
= inst
.operands
[0].reg
;
16931 unsigned int Rn
= inst
.operands
[1].reg
;
16932 unsigned int Rm
= inst
.operands
[2].reg
;
16934 set_it_insn_type (OUTSIDE_IT_INSN
);
16935 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16936 inst
.instruction
|= LOW4 (Rn
) << 16;
16937 inst
.instruction
|= LOW4 (Rm
);
16938 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16939 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16941 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16942 as_warn (UNPRED_REG ("r15"));
16943 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16944 as_warn (UNPRED_REG ("r13"));
16984 /* Overall per-instruction processing. */
16986 /* We need to be able to fix up arbitrary expressions in some statements.
16987 This is so that we can handle symbols that are an arbitrary distance from
16988 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16989 which returns part of an address in a form which will be valid for
16990 a data instruction. We do this by pushing the expression into a symbol
16991 in the expr_section, and creating a fix for that. */
16994 fix_new_arm (fragS
* frag
,
17008 /* Create an absolute valued symbol, so we have something to
17009 refer to in the object file. Unfortunately for us, gas's
17010 generic expression parsing will already have folded out
17011 any use of .set foo/.type foo %function that may have
17012 been used to set type information of the target location,
17013 that's being specified symbolically. We have to presume
17014 the user knows what they are doing. */
17018 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17020 symbol
= symbol_find_or_make (name
);
17021 S_SET_SEGMENT (symbol
, absolute_section
);
17022 symbol_set_frag (symbol
, &zero_address_frag
);
17023 S_SET_VALUE (symbol
, exp
->X_add_number
);
17024 exp
->X_op
= O_symbol
;
17025 exp
->X_add_symbol
= symbol
;
17026 exp
->X_add_number
= 0;
17032 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17033 (enum bfd_reloc_code_real
) reloc
);
17037 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17038 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17042 /* Mark whether the fix is to a THUMB instruction, or an ARM
17044 new_fix
->tc_fix_data
= thumb_mode
;
17047 /* Create a frg for an instruction requiring relaxation. */
17049 output_relax_insn (void)
17055 /* The size of the instruction is unknown, so tie the debug info to the
17056 start of the instruction. */
17057 dwarf2_emit_insn (0);
17059 switch (inst
.reloc
.exp
.X_op
)
17062 sym
= inst
.reloc
.exp
.X_add_symbol
;
17063 offset
= inst
.reloc
.exp
.X_add_number
;
17067 offset
= inst
.reloc
.exp
.X_add_number
;
17070 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17074 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17075 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17076 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17079 /* Write a 32-bit thumb instruction to buf. */
17081 put_thumb32_insn (char * buf
, unsigned long insn
)
17083 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17084 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17088 output_inst (const char * str
)
17094 as_bad ("%s -- `%s'", inst
.error
, str
);
17099 output_relax_insn ();
17102 if (inst
.size
== 0)
17105 to
= frag_more (inst
.size
);
17106 /* PR 9814: Record the thumb mode into the current frag so that we know
17107 what type of NOP padding to use, if necessary. We override any previous
17108 setting so that if the mode has changed then the NOPS that we use will
17109 match the encoding of the last instruction in the frag. */
17110 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17112 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17114 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17115 put_thumb32_insn (to
, inst
.instruction
);
17117 else if (inst
.size
> INSN_SIZE
)
17119 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17120 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17121 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17124 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17126 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17127 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17128 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17131 dwarf2_emit_insn (inst
.size
);
17135 output_it_inst (int cond
, int mask
, char * to
)
17137 unsigned long instruction
= 0xbf00;
17140 instruction
|= mask
;
17141 instruction
|= cond
<< 4;
17145 to
= frag_more (2);
17147 dwarf2_emit_insn (2);
17151 md_number_to_chars (to
, instruction
, 2);
17156 /* Tag values used in struct asm_opcode's tag field. */
17159 OT_unconditional
, /* Instruction cannot be conditionalized.
17160 The ARM condition field is still 0xE. */
17161 OT_unconditionalF
, /* Instruction cannot be conditionalized
17162 and carries 0xF in its ARM condition field. */
17163 OT_csuffix
, /* Instruction takes a conditional suffix. */
17164 OT_csuffixF
, /* Some forms of the instruction take a conditional
17165 suffix, others place 0xF where the condition field
17167 OT_cinfix3
, /* Instruction takes a conditional infix,
17168 beginning at character index 3. (In
17169 unified mode, it becomes a suffix.) */
17170 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17171 tsts, cmps, cmns, and teqs. */
17172 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17173 character index 3, even in unified mode. Used for
17174 legacy instructions where suffix and infix forms
17175 may be ambiguous. */
17176 OT_csuf_or_in3
, /* Instruction takes either a conditional
17177 suffix or an infix at character index 3. */
17178 OT_odd_infix_unc
, /* This is the unconditional variant of an
17179 instruction that takes a conditional infix
17180 at an unusual position. In unified mode,
17181 this variant will accept a suffix. */
17182 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17183 are the conditional variants of instructions that
17184 take conditional infixes in unusual positions.
17185 The infix appears at character index
17186 (tag - OT_odd_infix_0). These are not accepted
17187 in unified mode. */
17190 /* Subroutine of md_assemble, responsible for looking up the primary
17191 opcode from the mnemonic the user wrote. STR points to the
17192 beginning of the mnemonic.
17194 This is not simply a hash table lookup, because of conditional
17195 variants. Most instructions have conditional variants, which are
17196 expressed with a _conditional affix_ to the mnemonic. If we were
17197 to encode each conditional variant as a literal string in the opcode
17198 table, it would have approximately 20,000 entries.
17200 Most mnemonics take this affix as a suffix, and in unified syntax,
17201 'most' is upgraded to 'all'. However, in the divided syntax, some
17202 instructions take the affix as an infix, notably the s-variants of
17203 the arithmetic instructions. Of those instructions, all but six
17204 have the infix appear after the third character of the mnemonic.
17206 Accordingly, the algorithm for looking up primary opcodes given
17209 1. Look up the identifier in the opcode table.
17210 If we find a match, go to step U.
17212 2. Look up the last two characters of the identifier in the
17213 conditions table. If we find a match, look up the first N-2
17214 characters of the identifier in the opcode table. If we
17215 find a match, go to step CE.
17217 3. Look up the fourth and fifth characters of the identifier in
17218 the conditions table. If we find a match, extract those
17219 characters from the identifier, and look up the remaining
17220 characters in the opcode table. If we find a match, go
17225 U. Examine the tag field of the opcode structure, in case this is
17226 one of the six instructions with its conditional infix in an
17227 unusual place. If it is, the tag tells us where to find the
17228 infix; look it up in the conditions table and set inst.cond
17229 accordingly. Otherwise, this is an unconditional instruction.
17230 Again set inst.cond accordingly. Return the opcode structure.
17232 CE. Examine the tag field to make sure this is an instruction that
17233 should receive a conditional suffix. If it is not, fail.
17234 Otherwise, set inst.cond from the suffix we already looked up,
17235 and return the opcode structure.
17237 CM. Examine the tag field to make sure this is an instruction that
17238 should receive a conditional infix after the third character.
17239 If it is not, fail. Otherwise, undo the edits to the current
17240 line of input and proceed as for case CE. */
17242 static const struct asm_opcode
*
17243 opcode_lookup (char **str
)
17247 const struct asm_opcode
*opcode
;
17248 const struct asm_cond
*cond
;
17251 /* Scan up to the end of the mnemonic, which must end in white space,
17252 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17253 for (base
= end
= *str
; *end
!= '\0'; end
++)
17254 if (*end
== ' ' || *end
== '.')
17260 /* Handle a possible width suffix and/or Neon type suffix. */
17265 /* The .w and .n suffixes are only valid if the unified syntax is in
17267 if (unified_syntax
&& end
[1] == 'w')
17269 else if (unified_syntax
&& end
[1] == 'n')
17274 inst
.vectype
.elems
= 0;
17276 *str
= end
+ offset
;
17278 if (end
[offset
] == '.')
17280 /* See if we have a Neon type suffix (possible in either unified or
17281 non-unified ARM syntax mode). */
17282 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17285 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17291 /* Look for unaffixed or special-case affixed mnemonic. */
17292 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17297 if (opcode
->tag
< OT_odd_infix_0
)
17299 inst
.cond
= COND_ALWAYS
;
17303 if (warn_on_deprecated
&& unified_syntax
)
17304 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17305 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17306 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17309 inst
.cond
= cond
->value
;
17313 /* Cannot have a conditional suffix on a mnemonic of less than two
17315 if (end
- base
< 3)
17318 /* Look for suffixed mnemonic. */
17320 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17321 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17323 if (opcode
&& cond
)
17326 switch (opcode
->tag
)
17328 case OT_cinfix3_legacy
:
17329 /* Ignore conditional suffixes matched on infix only mnemonics. */
17333 case OT_cinfix3_deprecated
:
17334 case OT_odd_infix_unc
:
17335 if (!unified_syntax
)
17337 /* else fall through */
17341 case OT_csuf_or_in3
:
17342 inst
.cond
= cond
->value
;
17345 case OT_unconditional
:
17346 case OT_unconditionalF
:
17348 inst
.cond
= cond
->value
;
17351 /* Delayed diagnostic. */
17352 inst
.error
= BAD_COND
;
17353 inst
.cond
= COND_ALWAYS
;
17362 /* Cannot have a usual-position infix on a mnemonic of less than
17363 six characters (five would be a suffix). */
17364 if (end
- base
< 6)
17367 /* Look for infixed mnemonic in the usual position. */
17369 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17373 memcpy (save
, affix
, 2);
17374 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17375 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17377 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17378 memcpy (affix
, save
, 2);
17381 && (opcode
->tag
== OT_cinfix3
17382 || opcode
->tag
== OT_cinfix3_deprecated
17383 || opcode
->tag
== OT_csuf_or_in3
17384 || opcode
->tag
== OT_cinfix3_legacy
))
17387 if (warn_on_deprecated
&& unified_syntax
17388 && (opcode
->tag
== OT_cinfix3
17389 || opcode
->tag
== OT_cinfix3_deprecated
))
17390 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17392 inst
.cond
= cond
->value
;
17399 /* This function generates an initial IT instruction, leaving its block
17400 virtually open for the new instructions. Eventually,
17401 the mask will be updated by now_it_add_mask () each time
17402 a new instruction needs to be included in the IT block.
17403 Finally, the block is closed with close_automatic_it_block ().
17404 The block closure can be requested either from md_assemble (),
17405 a tencode (), or due to a label hook. */
17408 new_automatic_it_block (int cond
)
17410 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17411 now_it
.mask
= 0x18;
17413 now_it
.block_length
= 1;
17414 mapping_state (MAP_THUMB
);
17415 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17416 now_it
.warn_deprecated
= FALSE
;
17417 now_it
.insn_cond
= TRUE
;
17420 /* Close an automatic IT block.
17421 See comments in new_automatic_it_block (). */
17424 close_automatic_it_block (void)
17426 now_it
.mask
= 0x10;
17427 now_it
.block_length
= 0;
17430 /* Update the mask of the current automatically-generated IT
17431 instruction. See comments in new_automatic_it_block (). */
17434 now_it_add_mask (int cond
)
17436 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17437 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17438 | ((bitvalue) << (nbit)))
17439 const int resulting_bit
= (cond
& 1);
17441 now_it
.mask
&= 0xf;
17442 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17444 (5 - now_it
.block_length
));
17445 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17447 ((5 - now_it
.block_length
) - 1) );
17448 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17451 #undef SET_BIT_VALUE
17454 /* The IT blocks handling machinery is accessed through the these functions:
17455 it_fsm_pre_encode () from md_assemble ()
17456 set_it_insn_type () optional, from the tencode functions
17457 set_it_insn_type_last () ditto
17458 in_it_block () ditto
17459 it_fsm_post_encode () from md_assemble ()
17460 force_automatic_it_block_close () from label habdling functions
17463 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17464 initializing the IT insn type with a generic initial value depending
17465 on the inst.condition.
17466 2) During the tencode function, two things may happen:
17467 a) The tencode function overrides the IT insn type by
17468 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17469 b) The tencode function queries the IT block state by
17470 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17472 Both set_it_insn_type and in_it_block run the internal FSM state
17473 handling function (handle_it_state), because: a) setting the IT insn
17474 type may incur in an invalid state (exiting the function),
17475 and b) querying the state requires the FSM to be updated.
17476 Specifically we want to avoid creating an IT block for conditional
17477 branches, so it_fsm_pre_encode is actually a guess and we can't
17478 determine whether an IT block is required until the tencode () routine
17479 has decided what type of instruction this actually it.
17480 Because of this, if set_it_insn_type and in_it_block have to be used,
17481 set_it_insn_type has to be called first.
17483 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17484 determines the insn IT type depending on the inst.cond code.
17485 When a tencode () routine encodes an instruction that can be
17486 either outside an IT block, or, in the case of being inside, has to be
17487 the last one, set_it_insn_type_last () will determine the proper
17488 IT instruction type based on the inst.cond code. Otherwise,
17489 set_it_insn_type can be called for overriding that logic or
17490 for covering other cases.
17492 Calling handle_it_state () may not transition the IT block state to
17493 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17494 still queried. Instead, if the FSM determines that the state should
17495 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17496 after the tencode () function: that's what it_fsm_post_encode () does.
17498 Since in_it_block () calls the state handling function to get an
17499 updated state, an error may occur (due to invalid insns combination).
17500 In that case, inst.error is set.
17501 Therefore, inst.error has to be checked after the execution of
17502 the tencode () routine.
17504 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17505 any pending state change (if any) that didn't take place in
17506 handle_it_state () as explained above. */
17509 it_fsm_pre_encode (void)
17511 if (inst
.cond
!= COND_ALWAYS
)
17512 inst
.it_insn_type
= INSIDE_IT_INSN
;
17514 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17516 now_it
.state_handled
= 0;
17519 /* IT state FSM handling function. */
17522 handle_it_state (void)
17524 now_it
.state_handled
= 1;
17525 now_it
.insn_cond
= FALSE
;
17527 switch (now_it
.state
)
17529 case OUTSIDE_IT_BLOCK
:
17530 switch (inst
.it_insn_type
)
17532 case OUTSIDE_IT_INSN
:
17535 case INSIDE_IT_INSN
:
17536 case INSIDE_IT_LAST_INSN
:
17537 if (thumb_mode
== 0)
17540 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17541 as_tsktsk (_("Warning: conditional outside an IT block"\
17546 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17547 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17549 /* Automatically generate the IT instruction. */
17550 new_automatic_it_block (inst
.cond
);
17551 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17552 close_automatic_it_block ();
17556 inst
.error
= BAD_OUT_IT
;
17562 case IF_INSIDE_IT_LAST_INSN
:
17563 case NEUTRAL_IT_INSN
:
17567 now_it
.state
= MANUAL_IT_BLOCK
;
17568 now_it
.block_length
= 0;
17573 case AUTOMATIC_IT_BLOCK
:
17574 /* Three things may happen now:
17575 a) We should increment current it block size;
17576 b) We should close current it block (closing insn or 4 insns);
17577 c) We should close current it block and start a new one (due
17578 to incompatible conditions or
17579 4 insns-length block reached). */
17581 switch (inst
.it_insn_type
)
17583 case OUTSIDE_IT_INSN
:
17584 /* The closure of the block shall happen immediatelly,
17585 so any in_it_block () call reports the block as closed. */
17586 force_automatic_it_block_close ();
17589 case INSIDE_IT_INSN
:
17590 case INSIDE_IT_LAST_INSN
:
17591 case IF_INSIDE_IT_LAST_INSN
:
17592 now_it
.block_length
++;
17594 if (now_it
.block_length
> 4
17595 || !now_it_compatible (inst
.cond
))
17597 force_automatic_it_block_close ();
17598 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17599 new_automatic_it_block (inst
.cond
);
17603 now_it
.insn_cond
= TRUE
;
17604 now_it_add_mask (inst
.cond
);
17607 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17608 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17609 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17610 close_automatic_it_block ();
17613 case NEUTRAL_IT_INSN
:
17614 now_it
.block_length
++;
17615 now_it
.insn_cond
= TRUE
;
17617 if (now_it
.block_length
> 4)
17618 force_automatic_it_block_close ();
17620 now_it_add_mask (now_it
.cc
& 1);
17624 close_automatic_it_block ();
17625 now_it
.state
= MANUAL_IT_BLOCK
;
17630 case MANUAL_IT_BLOCK
:
17632 /* Check conditional suffixes. */
17633 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17636 now_it
.mask
&= 0x1f;
17637 is_last
= (now_it
.mask
== 0x10);
17638 now_it
.insn_cond
= TRUE
;
17640 switch (inst
.it_insn_type
)
17642 case OUTSIDE_IT_INSN
:
17643 inst
.error
= BAD_NOT_IT
;
17646 case INSIDE_IT_INSN
:
17647 if (cond
!= inst
.cond
)
17649 inst
.error
= BAD_IT_COND
;
17654 case INSIDE_IT_LAST_INSN
:
17655 case IF_INSIDE_IT_LAST_INSN
:
17656 if (cond
!= inst
.cond
)
17658 inst
.error
= BAD_IT_COND
;
17663 inst
.error
= BAD_BRANCH
;
17668 case NEUTRAL_IT_INSN
:
17669 /* The BKPT instruction is unconditional even in an IT block. */
17673 inst
.error
= BAD_IT_IT
;
17683 struct depr_insn_mask
17685 unsigned long pattern
;
17686 unsigned long mask
;
17687 const char* description
;
17690 /* List of 16-bit instruction patterns deprecated in an IT block in
17692 static const struct depr_insn_mask depr_it_insns
[] = {
17693 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17694 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17695 { 0xa000, 0xb800, N_("ADR") },
17696 { 0x4800, 0xf800, N_("Literal loads") },
17697 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17698 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17699 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17700 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17701 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17706 it_fsm_post_encode (void)
17710 if (!now_it
.state_handled
)
17711 handle_it_state ();
17713 if (now_it
.insn_cond
17714 && !now_it
.warn_deprecated
17715 && warn_on_deprecated
17716 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17718 if (inst
.instruction
>= 0x10000)
17720 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17721 "deprecated in ARMv8"));
17722 now_it
.warn_deprecated
= TRUE
;
17726 const struct depr_insn_mask
*p
= depr_it_insns
;
17728 while (p
->mask
!= 0)
17730 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17732 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17733 "of the following class are deprecated in ARMv8: "
17734 "%s"), p
->description
);
17735 now_it
.warn_deprecated
= TRUE
;
17743 if (now_it
.block_length
> 1)
17745 as_tsktsk (_("IT blocks containing more than one conditional "
17746 "instruction are deprecated in ARMv8"));
17747 now_it
.warn_deprecated
= TRUE
;
17751 is_last
= (now_it
.mask
== 0x10);
17754 now_it
.state
= OUTSIDE_IT_BLOCK
;
17760 force_automatic_it_block_close (void)
17762 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17764 close_automatic_it_block ();
17765 now_it
.state
= OUTSIDE_IT_BLOCK
;
17773 if (!now_it
.state_handled
)
17774 handle_it_state ();
17776 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17780 md_assemble (char *str
)
17783 const struct asm_opcode
* opcode
;
17785 /* Align the previous label if needed. */
17786 if (last_label_seen
!= NULL
)
17788 symbol_set_frag (last_label_seen
, frag_now
);
17789 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17790 S_SET_SEGMENT (last_label_seen
, now_seg
);
17793 memset (&inst
, '\0', sizeof (inst
));
17794 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17796 opcode
= opcode_lookup (&p
);
17799 /* It wasn't an instruction, but it might be a register alias of
17800 the form alias .req reg, or a Neon .dn/.qn directive. */
17801 if (! create_register_alias (str
, p
)
17802 && ! create_neon_reg_alias (str
, p
))
17803 as_bad (_("bad instruction `%s'"), str
);
17808 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17809 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17811 /* The value which unconditional instructions should have in place of the
17812 condition field. */
17813 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17817 arm_feature_set variant
;
17819 variant
= cpu_variant
;
17820 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17821 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17822 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17823 /* Check that this instruction is supported for this CPU. */
17824 if (!opcode
->tvariant
17825 || (thumb_mode
== 1
17826 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17828 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
17831 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17832 && opcode
->tencode
!= do_t_branch
)
17834 as_bad (_("Thumb does not support conditional execution"));
17838 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17840 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17841 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17842 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17844 /* Two things are addressed here.
17845 1) Implicit require narrow instructions on Thumb-1.
17846 This avoids relaxation accidentally introducing Thumb-2
17848 2) Reject wide instructions in non Thumb-2 cores. */
17849 if (inst
.size_req
== 0)
17851 else if (inst
.size_req
== 4)
17853 as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str
);
17859 inst
.instruction
= opcode
->tvalue
;
17861 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17863 /* Prepare the it_insn_type for those encodings that don't set
17865 it_fsm_pre_encode ();
17867 opcode
->tencode ();
17869 it_fsm_post_encode ();
17872 if (!(inst
.error
|| inst
.relax
))
17874 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17875 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17876 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17878 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17883 /* Something has gone badly wrong if we try to relax a fixed size
17885 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17887 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17888 *opcode
->tvariant
);
17889 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17890 set those bits when Thumb-2 32-bit instructions are seen. ie.
17891 anything other than bl/blx and v6-M instructions.
17892 The impact of relaxable instructions will be considered later after we
17893 finish all relaxation. */
17894 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17895 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17896 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17897 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17900 check_neon_suffixes
;
17904 mapping_state (MAP_THUMB
);
17907 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17911 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17912 is_bx
= (opcode
->aencode
== do_bx
);
17914 /* Check that this instruction is supported for this CPU. */
17915 if (!(is_bx
&& fix_v4bx
)
17916 && !(opcode
->avariant
&&
17917 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17919 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
17924 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17928 inst
.instruction
= opcode
->avalue
;
17929 if (opcode
->tag
== OT_unconditionalF
)
17930 inst
.instruction
|= 0xFU
<< 28;
17932 inst
.instruction
|= inst
.cond
<< 28;
17933 inst
.size
= INSN_SIZE
;
17934 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17936 it_fsm_pre_encode ();
17937 opcode
->aencode ();
17938 it_fsm_post_encode ();
17940 /* Arm mode bx is marked as both v4T and v5 because it's still required
17941 on a hypothetical non-thumb v5 core. */
17943 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17945 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17946 *opcode
->avariant
);
17948 check_neon_suffixes
;
17952 mapping_state (MAP_ARM
);
17957 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17965 check_it_blocks_finished (void)
17970 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17971 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17972 == MANUAL_IT_BLOCK
)
17974 as_warn (_("section '%s' finished with an open IT block."),
17978 if (now_it
.state
== MANUAL_IT_BLOCK
)
17979 as_warn (_("file finished with an open IT block."));
17983 /* Various frobbings of labels and their addresses. */
17986 arm_start_line_hook (void)
17988 last_label_seen
= NULL
;
17992 arm_frob_label (symbolS
* sym
)
17994 last_label_seen
= sym
;
17996 ARM_SET_THUMB (sym
, thumb_mode
);
17998 #if defined OBJ_COFF || defined OBJ_ELF
17999 ARM_SET_INTERWORK (sym
, support_interwork
);
18002 force_automatic_it_block_close ();
18004 /* Note - do not allow local symbols (.Lxxx) to be labelled
18005 as Thumb functions. This is because these labels, whilst
18006 they exist inside Thumb code, are not the entry points for
18007 possible ARM->Thumb calls. Also, these labels can be used
18008 as part of a computed goto or switch statement. eg gcc
18009 can generate code that looks like this:
18011 ldr r2, [pc, .Laaa]
18021 The first instruction loads the address of the jump table.
18022 The second instruction converts a table index into a byte offset.
18023 The third instruction gets the jump address out of the table.
18024 The fourth instruction performs the jump.
18026 If the address stored at .Laaa is that of a symbol which has the
18027 Thumb_Func bit set, then the linker will arrange for this address
18028 to have the bottom bit set, which in turn would mean that the
18029 address computation performed by the third instruction would end
18030 up with the bottom bit set. Since the ARM is capable of unaligned
18031 word loads, the instruction would then load the incorrect address
18032 out of the jump table, and chaos would ensue. */
18033 if (label_is_thumb_function_name
18034 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18035 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18037 /* When the address of a Thumb function is taken the bottom
18038 bit of that address should be set. This will allow
18039 interworking between Arm and Thumb functions to work
18042 THUMB_SET_FUNC (sym
, 1);
18044 label_is_thumb_function_name
= FALSE
;
18047 dwarf2_emit_label (sym
);
18051 arm_data_in_code (void)
18053 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18055 *input_line_pointer
= '/';
18056 input_line_pointer
+= 5;
18057 *input_line_pointer
= 0;
18065 arm_canonicalize_symbol_name (char * name
)
18069 if (thumb_mode
&& (len
= strlen (name
)) > 5
18070 && streq (name
+ len
- 5, "/data"))
18071 *(name
+ len
- 5) = 0;
18076 /* Table of all register names defined by default. The user can
18077 define additional names with .req. Note that all register names
18078 should appear in both upper and lowercase variants. Some registers
18079 also have mixed-case names. */
18081 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18082 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18083 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18084 #define REGSET(p,t) \
18085 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18086 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18087 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18088 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18089 #define REGSETH(p,t) \
18090 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18091 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18092 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18093 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18094 #define REGSET2(p,t) \
18095 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18096 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18097 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18098 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18099 #define SPLRBANK(base,bank,t) \
18100 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18101 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18102 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18103 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18104 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18105 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18107 static const struct reg_entry reg_names
[] =
18109 /* ARM integer registers. */
18110 REGSET(r
, RN
), REGSET(R
, RN
),
18112 /* ATPCS synonyms. */
18113 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18114 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18115 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18117 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18118 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18119 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18121 /* Well-known aliases. */
18122 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18123 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18125 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18126 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18128 /* Coprocessor numbers. */
18129 REGSET(p
, CP
), REGSET(P
, CP
),
18131 /* Coprocessor register numbers. The "cr" variants are for backward
18133 REGSET(c
, CN
), REGSET(C
, CN
),
18134 REGSET(cr
, CN
), REGSET(CR
, CN
),
18136 /* ARM banked registers. */
18137 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18138 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18139 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18140 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18141 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18142 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18143 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18145 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18146 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18147 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18148 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18149 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18150 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18151 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18152 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18154 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18155 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18156 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18157 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18158 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18159 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18160 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18161 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18162 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18164 /* FPA registers. */
18165 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18166 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18168 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18169 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18171 /* VFP SP registers. */
18172 REGSET(s
,VFS
), REGSET(S
,VFS
),
18173 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18175 /* VFP DP Registers. */
18176 REGSET(d
,VFD
), REGSET(D
,VFD
),
18177 /* Extra Neon DP registers. */
18178 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18180 /* Neon QP registers. */
18181 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18183 /* VFP control registers. */
18184 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18185 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18186 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18187 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18188 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18189 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18191 /* Maverick DSP coprocessor registers. */
18192 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18193 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18195 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18196 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18197 REGDEF(dspsc
,0,DSPSC
),
18199 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18200 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18201 REGDEF(DSPSC
,0,DSPSC
),
18203 /* iWMMXt data registers - p0, c0-15. */
18204 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18206 /* iWMMXt control registers - p1, c0-3. */
18207 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18208 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18209 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18210 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18212 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18213 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18214 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18215 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18216 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18218 /* XScale accumulator registers. */
18219 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18225 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18226 within psr_required_here. */
18227 static const struct asm_psr psrs
[] =
18229 /* Backward compatibility notation. Note that "all" is no longer
18230 truly all possible PSR bits. */
18231 {"all", PSR_c
| PSR_f
},
18235 /* Individual flags. */
18241 /* Combinations of flags. */
18242 {"fs", PSR_f
| PSR_s
},
18243 {"fx", PSR_f
| PSR_x
},
18244 {"fc", PSR_f
| PSR_c
},
18245 {"sf", PSR_s
| PSR_f
},
18246 {"sx", PSR_s
| PSR_x
},
18247 {"sc", PSR_s
| PSR_c
},
18248 {"xf", PSR_x
| PSR_f
},
18249 {"xs", PSR_x
| PSR_s
},
18250 {"xc", PSR_x
| PSR_c
},
18251 {"cf", PSR_c
| PSR_f
},
18252 {"cs", PSR_c
| PSR_s
},
18253 {"cx", PSR_c
| PSR_x
},
18254 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18255 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18256 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18257 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18258 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18259 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18260 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18261 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18262 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18263 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18264 {"scf", PSR_s
| PSR_c
| PSR_f
},
18265 {"scx", PSR_s
| PSR_c
| PSR_x
},
18266 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18267 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18268 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18269 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18270 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18271 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18272 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18273 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18274 {"csf", PSR_c
| PSR_s
| PSR_f
},
18275 {"csx", PSR_c
| PSR_s
| PSR_x
},
18276 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18277 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18278 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18279 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18280 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18281 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18282 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18283 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18284 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18285 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18286 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18287 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18288 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18289 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18290 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18291 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18292 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18293 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18294 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18295 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18296 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18297 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18298 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18299 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18300 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18301 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18304 /* Table of V7M psr names. */
18305 static const struct asm_psr v7m_psrs
[] =
18307 {"apsr", 0 }, {"APSR", 0 },
18308 {"iapsr", 1 }, {"IAPSR", 1 },
18309 {"eapsr", 2 }, {"EAPSR", 2 },
18310 {"psr", 3 }, {"PSR", 3 },
18311 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18312 {"ipsr", 5 }, {"IPSR", 5 },
18313 {"epsr", 6 }, {"EPSR", 6 },
18314 {"iepsr", 7 }, {"IEPSR", 7 },
18315 {"msp", 8 }, {"MSP", 8 },
18316 {"psp", 9 }, {"PSP", 9 },
18317 {"primask", 16}, {"PRIMASK", 16},
18318 {"basepri", 17}, {"BASEPRI", 17},
18319 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18320 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18321 {"faultmask", 19}, {"FAULTMASK", 19},
18322 {"control", 20}, {"CONTROL", 20}
18325 /* Table of all shift-in-operand names. */
18326 static const struct asm_shift_name shift_names
[] =
18328 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18329 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18330 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18331 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18332 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18333 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18336 /* Table of all explicit relocation names. */
18338 static struct reloc_entry reloc_names
[] =
18340 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18341 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18342 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18343 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18344 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18345 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18346 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18347 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18348 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18349 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18350 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18351 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18352 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18353 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18354 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18355 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18356 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18357 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18361 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18362 static const struct asm_cond conds
[] =
18366 {"cs", 0x2}, {"hs", 0x2},
18367 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18381 #define UL_BARRIER(L,U,CODE,FEAT) \
18382 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18383 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18385 static struct asm_barrier_opt barrier_opt_names
[] =
18387 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18388 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18389 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18390 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18391 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18392 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18393 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18394 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18395 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18396 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18397 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18398 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18399 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18400 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18401 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18402 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18407 /* Table of ARM-format instructions. */
18409 /* Macros for gluing together operand strings. N.B. In all cases
18410 other than OPS0, the trailing OP_stop comes from default
18411 zero-initialization of the unspecified elements of the array. */
18412 #define OPS0() { OP_stop, }
18413 #define OPS1(a) { OP_##a, }
18414 #define OPS2(a,b) { OP_##a,OP_##b, }
18415 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18416 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18417 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18418 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18420 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18421 This is useful when mixing operands for ARM and THUMB, i.e. using the
18422 MIX_ARM_THUMB_OPERANDS macro.
18423 In order to use these macros, prefix the number of operands with _
18425 #define OPS_1(a) { a, }
18426 #define OPS_2(a,b) { a,b, }
18427 #define OPS_3(a,b,c) { a,b,c, }
18428 #define OPS_4(a,b,c,d) { a,b,c,d, }
18429 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18430 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18432 /* These macros abstract out the exact format of the mnemonic table and
18433 save some repeated characters. */
18435 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18436 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18437 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18438 THUMB_VARIANT, do_##ae, do_##te }
18440 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18441 a T_MNEM_xyz enumerator. */
18442 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18443 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18444 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18445 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18447 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18448 infix after the third character. */
18449 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18450 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18451 THUMB_VARIANT, do_##ae, do_##te }
18452 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18453 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18454 THUMB_VARIANT, do_##ae, do_##te }
18455 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18456 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18457 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18458 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18459 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18460 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18461 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18462 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18464 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18465 field is still 0xE. Many of the Thumb variants can be executed
18466 conditionally, so this is checked separately. */
18467 #define TUE(mnem, op, top, nops, ops, ae, te) \
18468 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18469 THUMB_VARIANT, do_##ae, do_##te }
18471 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18472 Used by mnemonics that have very minimal differences in the encoding for
18473 ARM and Thumb variants and can be handled in a common function. */
18474 #define TUEc(mnem, op, top, nops, ops, en) \
18475 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18476 THUMB_VARIANT, do_##en, do_##en }
18478 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18479 condition code field. */
18480 #define TUF(mnem, op, top, nops, ops, ae, te) \
18481 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18482 THUMB_VARIANT, do_##ae, do_##te }
18484 /* ARM-only variants of all the above. */
18485 #define CE(mnem, op, nops, ops, ae) \
18486 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18488 #define C3(mnem, op, nops, ops, ae) \
18489 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18491 /* Legacy mnemonics that always have conditional infix after the third
18493 #define CL(mnem, op, nops, ops, ae) \
18494 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18495 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18497 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18498 #define cCE(mnem, op, nops, ops, ae) \
18499 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18501 /* Legacy coprocessor instructions where conditional infix and conditional
18502 suffix are ambiguous. For consistency this includes all FPA instructions,
18503 not just the potentially ambiguous ones. */
18504 #define cCL(mnem, op, nops, ops, ae) \
18505 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18506 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18508 /* Coprocessor, takes either a suffix or a position-3 infix
18509 (for an FPA corner case). */
18510 #define C3E(mnem, op, nops, ops, ae) \
18511 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18512 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18514 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18515 { m1 #m2 m3, OPS##nops ops, \
18516 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18517 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18519 #define CM(m1, m2, op, nops, ops, ae) \
18520 xCM_ (m1, , m2, op, nops, ops, ae), \
18521 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18522 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18523 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18524 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18525 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18526 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18527 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18528 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18529 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18530 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18531 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18532 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18533 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18534 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18535 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18536 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18537 xCM_ (m1, le, m2, op, nops, ops, ae), \
18538 xCM_ (m1, al, m2, op, nops, ops, ae)
18540 #define UE(mnem, op, nops, ops, ae) \
18541 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18543 #define UF(mnem, op, nops, ops, ae) \
18544 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18546 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18547 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18548 use the same encoding function for each. */
18549 #define NUF(mnem, op, nops, ops, enc) \
18550 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18551 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18553 /* Neon data processing, version which indirects through neon_enc_tab for
18554 the various overloaded versions of opcodes. */
18555 #define nUF(mnem, op, nops, ops, enc) \
18556 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18557 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18559 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18561 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18562 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18563 THUMB_VARIANT, do_##enc, do_##enc }
18565 #define NCE(mnem, op, nops, ops, enc) \
18566 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18568 #define NCEF(mnem, op, nops, ops, enc) \
18569 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18571 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18572 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18573 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18574 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18576 #define nCE(mnem, op, nops, ops, enc) \
18577 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18579 #define nCEF(mnem, op, nops, ops, enc) \
18580 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18584 static const struct asm_opcode insns
[] =
18586 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18587 #define THUMB_VARIANT & arm_ext_v4t
18588 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18589 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18590 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18591 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18592 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18593 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18594 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18595 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18596 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18597 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18598 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18599 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18600 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18601 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18602 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18603 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18605 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18606 for setting PSR flag bits. They are obsolete in V6 and do not
18607 have Thumb equivalents. */
18608 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18609 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18610 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18611 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18612 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18613 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18614 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18615 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18616 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18618 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18619 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18620 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18621 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18623 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18624 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18625 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18627 OP_ADDRGLDR
),ldst
, t_ldst
),
18628 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18630 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18631 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18632 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18633 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18634 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18635 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18637 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18638 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18639 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18640 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18643 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18644 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18645 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18646 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18648 /* Thumb-compatibility pseudo ops. */
18649 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18650 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18651 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18652 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18653 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18654 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18655 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18656 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18657 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18658 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18659 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18660 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18662 /* These may simplify to neg. */
18663 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18664 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18666 #undef THUMB_VARIANT
18667 #define THUMB_VARIANT & arm_ext_v6
18669 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18671 /* V1 instructions with no Thumb analogue prior to V6T2. */
18672 #undef THUMB_VARIANT
18673 #define THUMB_VARIANT & arm_ext_v6t2
18675 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18676 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18677 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18679 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18680 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18681 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18682 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18684 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18685 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18687 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18688 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18690 /* V1 instructions with no Thumb analogue at all. */
18691 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18692 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18694 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18695 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18696 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18697 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18698 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18699 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18700 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18701 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18704 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18705 #undef THUMB_VARIANT
18706 #define THUMB_VARIANT & arm_ext_v4t
18708 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18709 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18711 #undef THUMB_VARIANT
18712 #define THUMB_VARIANT & arm_ext_v6t2
18714 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18715 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18717 /* Generic coprocessor instructions. */
18718 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18719 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18720 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18721 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18722 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18723 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18724 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18727 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18729 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18730 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18733 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18734 #undef THUMB_VARIANT
18735 #define THUMB_VARIANT & arm_ext_msr
18737 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18738 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18741 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18742 #undef THUMB_VARIANT
18743 #define THUMB_VARIANT & arm_ext_v6t2
18745 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18746 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18747 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18748 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18749 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18750 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18751 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18752 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18755 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18756 #undef THUMB_VARIANT
18757 #define THUMB_VARIANT & arm_ext_v4t
18759 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18760 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18761 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18762 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18763 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18764 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18767 #define ARM_VARIANT & arm_ext_v4t_5
18769 /* ARM Architecture 4T. */
18770 /* Note: bx (and blx) are required on V5, even if the processor does
18771 not support Thumb. */
18772 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18775 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18776 #undef THUMB_VARIANT
18777 #define THUMB_VARIANT & arm_ext_v5t
18779 /* Note: blx has 2 variants; the .value coded here is for
18780 BLX(2). Only this variant has conditional execution. */
18781 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18782 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18784 #undef THUMB_VARIANT
18785 #define THUMB_VARIANT & arm_ext_v6t2
18787 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18788 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18789 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18790 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18791 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18792 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18793 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18794 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18797 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18798 #undef THUMB_VARIANT
18799 #define THUMB_VARIANT & arm_ext_v5exp
18801 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18802 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18803 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18804 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18806 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18807 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18809 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18810 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18811 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18812 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18814 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18815 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18816 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18817 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18819 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18820 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18822 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18823 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18824 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18825 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18828 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18829 #undef THUMB_VARIANT
18830 #define THUMB_VARIANT & arm_ext_v6t2
18832 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18833 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18835 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18836 ADDRGLDRS
), ldrd
, t_ldstd
),
18838 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18839 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18842 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18844 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18847 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18848 #undef THUMB_VARIANT
18849 #define THUMB_VARIANT & arm_ext_v6
18851 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18852 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18853 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18854 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18855 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18856 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18857 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18858 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18859 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18860 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18862 #undef THUMB_VARIANT
18863 #define THUMB_VARIANT & arm_ext_v6t2
18865 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18866 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18868 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18869 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18871 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18872 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18874 /* ARM V6 not included in V7M. */
18875 #undef THUMB_VARIANT
18876 #define THUMB_VARIANT & arm_ext_v6_notm
18877 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18878 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18879 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18880 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18881 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18882 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18883 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18884 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18885 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18886 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18887 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18888 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18889 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18890 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18891 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18892 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18893 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18894 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18896 /* ARM V6 not included in V7M (eg. integer SIMD). */
18897 #undef THUMB_VARIANT
18898 #define THUMB_VARIANT & arm_ext_v6_dsp
18899 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18900 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18901 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18902 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18903 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18904 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18905 /* Old name for QASX. */
18906 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18907 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18908 /* Old name for QSAX. */
18909 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18910 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18911 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18912 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18913 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18914 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18915 /* Old name for SASX. */
18916 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18917 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18918 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18919 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18920 /* Old name for SHASX. */
18921 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18922 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18923 /* Old name for SHSAX. */
18924 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18925 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18926 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18927 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18928 /* Old name for SSAX. */
18929 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18930 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18931 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18932 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18933 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18934 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18935 /* Old name for UASX. */
18936 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18937 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18940 /* Old name for UHASX. */
18941 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18942 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18943 /* Old name for UHSAX. */
18944 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18945 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18946 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18948 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 /* Old name for UQASX. */
18951 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18952 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 /* Old name for UQSAX. */
18954 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18955 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18956 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18957 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18958 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18959 /* Old name for USAX. */
18960 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18961 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18963 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18964 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18965 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18966 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18967 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18968 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18969 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18970 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18971 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18972 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18973 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18974 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18975 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18976 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18977 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18978 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18979 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18980 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18981 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18982 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18983 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18984 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18985 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18986 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18987 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18988 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18989 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18990 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18991 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18992 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18993 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18996 #define ARM_VARIANT & arm_ext_v6k
18997 #undef THUMB_VARIANT
18998 #define THUMB_VARIANT & arm_ext_v6k
19000 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19001 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19002 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19003 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19005 #undef THUMB_VARIANT
19006 #define THUMB_VARIANT & arm_ext_v6_notm
19007 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19009 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19010 RRnpcb
), strexd
, t_strexd
),
19012 #undef THUMB_VARIANT
19013 #define THUMB_VARIANT & arm_ext_v6t2
19014 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19016 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19018 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19020 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19022 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19025 #define ARM_VARIANT & arm_ext_sec
19026 #undef THUMB_VARIANT
19027 #define THUMB_VARIANT & arm_ext_sec
19029 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19032 #define ARM_VARIANT & arm_ext_virt
19033 #undef THUMB_VARIANT
19034 #define THUMB_VARIANT & arm_ext_virt
19036 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19037 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19040 #define ARM_VARIANT & arm_ext_pan
19041 #undef THUMB_VARIANT
19042 #define THUMB_VARIANT & arm_ext_pan
19044 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19047 #define ARM_VARIANT & arm_ext_v6t2
19048 #undef THUMB_VARIANT
19049 #define THUMB_VARIANT & arm_ext_v6t2
19051 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19052 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19053 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19054 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19056 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19057 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19058 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19059 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19061 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19062 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19063 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19064 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19066 /* Thumb-only instructions. */
19068 #define ARM_VARIANT NULL
19069 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19070 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19072 /* ARM does not really have an IT instruction, so always allow it.
19073 The opcode is copied from Thumb in order to allow warnings in
19074 -mimplicit-it=[never | arm] modes. */
19076 #define ARM_VARIANT & arm_ext_v1
19078 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19079 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19080 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19081 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19082 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19083 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19084 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19085 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19086 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19087 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19088 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19089 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19090 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19091 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19092 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19093 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19094 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19095 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19097 /* Thumb2 only instructions. */
19099 #define ARM_VARIANT NULL
19101 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19102 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19103 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19104 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19105 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19106 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19108 /* Hardware division instructions. */
19110 #define ARM_VARIANT & arm_ext_adiv
19111 #undef THUMB_VARIANT
19112 #define THUMB_VARIANT & arm_ext_div
19114 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19115 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19117 /* ARM V6M/V7 instructions. */
19119 #define ARM_VARIANT & arm_ext_barrier
19120 #undef THUMB_VARIANT
19121 #define THUMB_VARIANT & arm_ext_barrier
19123 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19124 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19125 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19127 /* ARM V7 instructions. */
19129 #define ARM_VARIANT & arm_ext_v7
19130 #undef THUMB_VARIANT
19131 #define THUMB_VARIANT & arm_ext_v7
19133 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19134 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19137 #define ARM_VARIANT & arm_ext_mp
19138 #undef THUMB_VARIANT
19139 #define THUMB_VARIANT & arm_ext_mp
19141 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19143 /* AArchv8 instructions. */
19145 #define ARM_VARIANT & arm_ext_v8
19146 #undef THUMB_VARIANT
19147 #define THUMB_VARIANT & arm_ext_v8
19149 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19150 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19151 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19152 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19154 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19155 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19156 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19158 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19160 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19162 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19164 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19165 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19166 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19167 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19168 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19169 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19171 /* ARMv8 T32 only. */
19173 #define ARM_VARIANT NULL
19174 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19175 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19176 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19178 /* FP for ARMv8. */
19180 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19181 #undef THUMB_VARIANT
19182 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19184 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19185 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19186 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19187 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19188 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19189 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19190 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19191 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19192 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19193 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19194 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19195 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19196 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19197 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19198 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19199 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19200 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19202 /* Crypto v1 extensions. */
19204 #define ARM_VARIANT & fpu_crypto_ext_armv8
19205 #undef THUMB_VARIANT
19206 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19208 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19209 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19210 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19211 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19212 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19213 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19214 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19215 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19216 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19217 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19218 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19219 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19220 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19221 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19224 #define ARM_VARIANT & crc_ext_armv8
19225 #undef THUMB_VARIANT
19226 #define THUMB_VARIANT & crc_ext_armv8
19227 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19228 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19229 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19230 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19231 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19232 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19235 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19236 #undef THUMB_VARIANT
19237 #define THUMB_VARIANT NULL
19239 cCE("wfs", e200110
, 1, (RR
), rd
),
19240 cCE("rfs", e300110
, 1, (RR
), rd
),
19241 cCE("wfc", e400110
, 1, (RR
), rd
),
19242 cCE("rfc", e500110
, 1, (RR
), rd
),
19244 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19245 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19246 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19247 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19249 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19250 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19251 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19252 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19254 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19255 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19257 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19258 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19261 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19263 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19267 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19270 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19271 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19276 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19280 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19283 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19284 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19285 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19289 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19340 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19353 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19366 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19379 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19392 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19405 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19418 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19431 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19444 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19454 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19455 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19456 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19457 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19458 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19459 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19460 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19462 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19463 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19464 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19465 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19466 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19467 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19468 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19469 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19470 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19471 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19472 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19473 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19475 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19476 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19477 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19478 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19479 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19480 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19481 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19482 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19483 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19484 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19485 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19486 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19488 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19491 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19492 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19493 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19497 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19501 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19504 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19505 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19506 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19509 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19522 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19535 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19548 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19561 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19574 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19587 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19600 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19613 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19623 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19624 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19625 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19626 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19627 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19628 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19629 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19631 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19632 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19633 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19634 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19636 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19637 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19638 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19639 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19640 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19641 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19642 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19643 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19644 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19645 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19646 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19647 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19649 /* The implementation of the FIX instruction is broken on some
19650 assemblers, in that it accepts a precision specifier as well as a
19651 rounding specifier, despite the fact that this is meaningless.
19652 To be more compatible, we accept it as well, though of course it
19653 does not set any bits. */
19654 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19655 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19656 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19657 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19658 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19659 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19660 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19661 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19662 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19663 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19664 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19665 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19666 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19668 /* Instructions that were new with the real FPA, call them V2. */
19670 #define ARM_VARIANT & fpu_fpa_ext_v2
19672 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19673 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19674 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19675 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19676 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19677 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19680 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19682 /* Moves and type conversions. */
19683 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19684 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19685 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19686 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19687 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19688 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19689 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19690 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19691 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19692 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19693 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19694 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19695 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19696 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19698 /* Memory operations. */
19699 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19700 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19701 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19702 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19703 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19704 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19705 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19706 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19707 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19708 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19709 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19710 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19711 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19712 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19713 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19714 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19715 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19716 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19718 /* Monadic operations. */
19719 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19720 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19721 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19723 /* Dyadic operations. */
19724 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19725 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19726 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19727 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19728 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19729 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19730 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19731 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19732 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19735 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19736 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19737 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19738 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19740 /* Double precision load/store are still present on single precision
19741 implementations. */
19742 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19743 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19744 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19745 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19746 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19747 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19748 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19749 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19750 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19751 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19754 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19756 /* Moves and type conversions. */
19757 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19758 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19759 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19760 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19761 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19762 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19763 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19764 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19765 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19766 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19767 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19768 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19769 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19771 /* Monadic operations. */
19772 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19773 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19774 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19776 /* Dyadic operations. */
19777 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19778 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19779 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19780 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19781 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19782 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19783 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19784 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19785 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19788 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19789 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19790 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19791 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19794 #define ARM_VARIANT & fpu_vfp_ext_v2
19796 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19797 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19798 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19799 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19801 /* Instructions which may belong to either the Neon or VFP instruction sets.
19802 Individual encoder functions perform additional architecture checks. */
19804 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19805 #undef THUMB_VARIANT
19806 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19808 /* These mnemonics are unique to VFP. */
19809 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19810 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19811 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19812 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19813 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19814 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19815 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19816 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19817 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19818 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19820 /* Mnemonics shared by Neon and VFP. */
19821 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19822 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19823 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19825 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19826 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19828 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19829 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19831 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19832 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19833 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19834 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19835 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19836 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19837 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19838 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19840 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19841 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19842 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19843 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19846 /* NOTE: All VMOV encoding is special-cased! */
19847 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19848 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19850 #undef THUMB_VARIANT
19851 #define THUMB_VARIANT & fpu_neon_ext_v1
19853 #define ARM_VARIANT & fpu_neon_ext_v1
19855 /* Data processing with three registers of the same length. */
19856 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19857 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19858 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19859 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19860 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19861 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19862 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19863 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19864 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19865 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19866 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19867 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19868 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19869 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19870 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19871 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19872 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19873 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19874 /* If not immediate, fall back to neon_dyadic_i64_su.
19875 shl_imm should accept I8 I16 I32 I64,
19876 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19877 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19878 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19879 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19880 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19881 /* Logic ops, types optional & ignored. */
19882 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19883 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19884 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19885 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19886 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19887 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19888 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19889 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19890 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19891 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19892 /* Bitfield ops, untyped. */
19893 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19894 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19895 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19896 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19897 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19898 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19899 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19900 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19901 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19902 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19903 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19904 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19905 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19906 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19907 back to neon_dyadic_if_su. */
19908 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19909 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19910 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19911 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19912 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19913 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19914 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19915 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19916 /* Comparison. Type I8 I16 I32 F32. */
19917 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19918 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19919 /* As above, D registers only. */
19920 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19921 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19922 /* Int and float variants, signedness unimportant. */
19923 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19924 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19925 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19926 /* Add/sub take types I8 I16 I32 I64 F32. */
19927 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19928 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19929 /* vtst takes sizes 8, 16, 32. */
19930 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19931 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19932 /* VMUL takes I8 I16 I32 F32 P8. */
19933 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19934 /* VQD{R}MULH takes S16 S32. */
19935 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19936 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19937 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19938 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19939 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19940 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19941 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19942 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19943 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19944 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19945 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19946 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19947 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19948 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19949 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19950 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19951 /* ARM v8.1 extension. */
19952 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19953 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19954 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19955 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19957 /* Two address, int/float. Types S8 S16 S32 F32. */
19958 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19959 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19961 /* Data processing with two registers and a shift amount. */
19962 /* Right shifts, and variants with rounding.
19963 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19964 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19965 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19966 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19967 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19968 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19969 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19970 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19971 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19972 /* Shift and insert. Sizes accepted 8 16 32 64. */
19973 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19974 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19975 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19976 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19977 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19978 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19979 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19980 /* Right shift immediate, saturating & narrowing, with rounding variants.
19981 Types accepted S16 S32 S64 U16 U32 U64. */
19982 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19983 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19984 /* As above, unsigned. Types accepted S16 S32 S64. */
19985 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19986 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19987 /* Right shift narrowing. Types accepted I16 I32 I64. */
19988 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19989 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19990 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19991 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19992 /* CVT with optional immediate for fixed-point variant. */
19993 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19995 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19996 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19998 /* Data processing, three registers of different lengths. */
19999 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20000 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20001 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20002 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20003 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20004 /* If not scalar, fall back to neon_dyadic_long.
20005 Vector types as above, scalar types S16 S32 U16 U32. */
20006 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20007 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20008 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20009 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20010 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20011 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20012 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20013 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20014 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20015 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20016 /* Saturating doubling multiplies. Types S16 S32. */
20017 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20018 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20019 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20020 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20021 S16 S32 U16 U32. */
20022 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20024 /* Extract. Size 8. */
20025 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20026 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20028 /* Two registers, miscellaneous. */
20029 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20030 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20031 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20032 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20033 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20034 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20035 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20036 /* Vector replicate. Sizes 8 16 32. */
20037 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20038 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20039 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20040 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20041 /* VMOVN. Types I16 I32 I64. */
20042 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20043 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20044 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20045 /* VQMOVUN. Types S16 S32 S64. */
20046 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20047 /* VZIP / VUZP. Sizes 8 16 32. */
20048 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20049 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20050 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20051 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20052 /* VQABS / VQNEG. Types S8 S16 S32. */
20053 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20054 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20055 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20056 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20057 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20058 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20059 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20060 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20061 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20062 /* Reciprocal estimates. Types U32 F32. */
20063 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20064 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20065 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20066 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20067 /* VCLS. Types S8 S16 S32. */
20068 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20069 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20070 /* VCLZ. Types I8 I16 I32. */
20071 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20072 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20073 /* VCNT. Size 8. */
20074 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20075 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20076 /* Two address, untyped. */
20077 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20078 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20079 /* VTRN. Sizes 8 16 32. */
20080 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20081 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20083 /* Table lookup. Size 8. */
20084 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20085 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20087 #undef THUMB_VARIANT
20088 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20090 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20092 /* Neon element/structure load/store. */
20093 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20094 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20095 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20096 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20097 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20098 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20099 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20100 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20102 #undef THUMB_VARIANT
20103 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20105 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20106 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20107 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20108 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20109 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20110 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20111 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20112 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20113 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20114 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20116 #undef THUMB_VARIANT
20117 #define THUMB_VARIANT & fpu_vfp_ext_v3
20119 #define ARM_VARIANT & fpu_vfp_ext_v3
20121 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20122 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20123 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20124 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20125 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20126 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20127 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20128 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20129 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20132 #define ARM_VARIANT & fpu_vfp_ext_fma
20133 #undef THUMB_VARIANT
20134 #define THUMB_VARIANT & fpu_vfp_ext_fma
20135 /* Mnemonics shared by Neon and VFP. These are included in the
20136 VFP FMA variant; NEON and VFP FMA always includes the NEON
20137 FMA instructions. */
20138 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20139 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20140 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20141 the v form should always be used. */
20142 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20143 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20144 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20145 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20146 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20147 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20149 #undef THUMB_VARIANT
20151 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20153 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20154 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20155 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20156 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20157 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20158 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20159 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20160 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20163 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20165 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20166 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20167 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20168 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20169 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20170 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20171 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20172 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20173 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20174 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20175 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20176 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20177 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20178 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20179 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20180 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20181 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20182 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20183 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20184 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20185 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20186 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20187 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20188 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20189 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20190 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20191 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20192 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20193 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20194 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20195 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20196 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20197 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20198 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20199 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20200 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20201 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20202 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20203 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20204 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20205 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20206 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20207 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20208 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20209 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20210 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20211 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20212 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20213 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20214 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20215 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20216 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20217 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20218 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20219 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20220 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20221 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20222 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20223 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20224 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20225 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20226 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20227 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20231 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20232 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20233 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20234 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20235 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20236 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20254 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20257 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20258 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20259 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20260 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20261 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20262 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20266 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20267 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20268 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20269 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20270 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20271 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20272 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20273 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20274 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20275 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20276 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20277 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20278 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20279 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20280 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20281 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20282 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20283 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20284 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20285 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20286 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20287 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20288 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20289 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20290 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20291 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20292 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20293 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20294 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20295 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20296 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20297 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20298 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20299 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20300 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20301 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20302 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20303 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20304 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20305 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20306 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20307 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20308 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20309 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20310 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20311 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20312 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20313 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20314 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20315 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20316 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20317 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20318 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20319 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20320 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20321 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20322 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20323 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20324 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20325 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20326 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20329 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20331 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20332 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20333 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20334 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20335 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20336 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20337 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20338 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20339 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20340 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20341 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20342 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20343 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20344 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20345 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20346 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20347 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20348 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20351 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20352 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20353 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20354 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20355 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20356 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20357 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20358 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20359 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20360 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20361 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20365 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20366 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20367 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20368 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20369 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20370 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20371 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20376 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20379 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20380 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20381 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20382 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20383 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20384 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20385 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20386 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20387 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20390 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20392 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20393 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20394 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20395 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20396 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20397 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20398 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20399 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20400 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20401 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20402 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20403 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20404 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20405 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20406 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20407 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20408 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20409 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20410 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20411 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20412 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20413 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20414 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20415 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20416 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20417 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20418 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20419 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20420 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20421 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20422 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20423 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20424 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20425 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20426 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20427 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20428 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20429 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20430 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20431 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20432 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20433 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20434 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20435 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20436 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20437 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20438 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20439 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20440 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20441 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20442 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20443 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20444 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20445 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20446 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20447 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20448 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20449 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20450 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20451 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20452 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20453 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20454 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20455 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20456 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20457 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20458 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20459 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20460 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20461 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20462 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20463 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20464 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20465 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20466 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20467 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20470 #undef THUMB_VARIANT
20496 /* MD interface: bits in the object file. */
20498 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20499 for use in the a.out file, and stores them in the array pointed to by buf.
20500 This knows about the endian-ness of the target machine and does
20501 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20502 2 (short) and 4 (long) Floating numbers are put out as a series of
20503 LITTLENUMS (shorts, here at least). */
20506 md_number_to_chars (char * buf
, valueT val
, int n
)
20508 if (target_big_endian
)
20509 number_to_chars_bigendian (buf
, val
, n
);
20511 number_to_chars_littleendian (buf
, val
, n
);
20515 md_chars_to_number (char * buf
, int n
)
20518 unsigned char * where
= (unsigned char *) buf
;
20520 if (target_big_endian
)
20525 result
|= (*where
++ & 255);
20533 result
|= (where
[n
] & 255);
20540 /* MD interface: Sections. */
20542 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20543 that an rs_machine_dependent frag may reach. */
20546 arm_frag_max_var (fragS
*fragp
)
20548 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20549 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20551 Note that we generate relaxable instructions even for cases that don't
20552 really need it, like an immediate that's a trivial constant. So we're
20553 overestimating the instruction size for some of those cases. Rather
20554 than putting more intelligence here, it would probably be better to
20555 avoid generating a relaxation frag in the first place when it can be
20556 determined up front that a short instruction will suffice. */
20558 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20562 /* Estimate the size of a frag before relaxing. Assume everything fits in
20566 md_estimate_size_before_relax (fragS
* fragp
,
20567 segT segtype ATTRIBUTE_UNUSED
)
20573 /* Convert a machine dependent frag. */
20576 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20578 unsigned long insn
;
20579 unsigned long old_op
;
20587 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20589 old_op
= bfd_get_16(abfd
, buf
);
20590 if (fragp
->fr_symbol
)
20592 exp
.X_op
= O_symbol
;
20593 exp
.X_add_symbol
= fragp
->fr_symbol
;
20597 exp
.X_op
= O_constant
;
20599 exp
.X_add_number
= fragp
->fr_offset
;
20600 opcode
= fragp
->fr_subtype
;
20603 case T_MNEM_ldr_pc
:
20604 case T_MNEM_ldr_pc2
:
20605 case T_MNEM_ldr_sp
:
20606 case T_MNEM_str_sp
:
20613 if (fragp
->fr_var
== 4)
20615 insn
= THUMB_OP32 (opcode
);
20616 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20618 insn
|= (old_op
& 0x700) << 4;
20622 insn
|= (old_op
& 7) << 12;
20623 insn
|= (old_op
& 0x38) << 13;
20625 insn
|= 0x00000c00;
20626 put_thumb32_insn (buf
, insn
);
20627 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20631 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20633 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20636 if (fragp
->fr_var
== 4)
20638 insn
= THUMB_OP32 (opcode
);
20639 insn
|= (old_op
& 0xf0) << 4;
20640 put_thumb32_insn (buf
, insn
);
20641 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20645 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20646 exp
.X_add_number
-= 4;
20654 if (fragp
->fr_var
== 4)
20656 int r0off
= (opcode
== T_MNEM_mov
20657 || opcode
== T_MNEM_movs
) ? 0 : 8;
20658 insn
= THUMB_OP32 (opcode
);
20659 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20660 insn
|= (old_op
& 0x700) << r0off
;
20661 put_thumb32_insn (buf
, insn
);
20662 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20666 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20671 if (fragp
->fr_var
== 4)
20673 insn
= THUMB_OP32(opcode
);
20674 put_thumb32_insn (buf
, insn
);
20675 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20678 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20682 if (fragp
->fr_var
== 4)
20684 insn
= THUMB_OP32(opcode
);
20685 insn
|= (old_op
& 0xf00) << 14;
20686 put_thumb32_insn (buf
, insn
);
20687 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20690 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20693 case T_MNEM_add_sp
:
20694 case T_MNEM_add_pc
:
20695 case T_MNEM_inc_sp
:
20696 case T_MNEM_dec_sp
:
20697 if (fragp
->fr_var
== 4)
20699 /* ??? Choose between add and addw. */
20700 insn
= THUMB_OP32 (opcode
);
20701 insn
|= (old_op
& 0xf0) << 4;
20702 put_thumb32_insn (buf
, insn
);
20703 if (opcode
== T_MNEM_add_pc
)
20704 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20706 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20709 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20717 if (fragp
->fr_var
== 4)
20719 insn
= THUMB_OP32 (opcode
);
20720 insn
|= (old_op
& 0xf0) << 4;
20721 insn
|= (old_op
& 0xf) << 16;
20722 put_thumb32_insn (buf
, insn
);
20723 if (insn
& (1 << 20))
20724 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20726 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20729 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20735 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20736 (enum bfd_reloc_code_real
) reloc_type
);
20737 fixp
->fx_file
= fragp
->fr_file
;
20738 fixp
->fx_line
= fragp
->fr_line
;
20739 fragp
->fr_fix
+= fragp
->fr_var
;
20741 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20742 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20743 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20744 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20747 /* Return the size of a relaxable immediate operand instruction.
20748 SHIFT and SIZE specify the form of the allowable immediate. */
20750 relax_immediate (fragS
*fragp
, int size
, int shift
)
20756 /* ??? Should be able to do better than this. */
20757 if (fragp
->fr_symbol
)
20760 low
= (1 << shift
) - 1;
20761 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20762 offset
= fragp
->fr_offset
;
20763 /* Force misaligned offsets to 32-bit variant. */
20766 if (offset
& ~mask
)
20771 /* Get the address of a symbol during relaxation. */
20773 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20779 sym
= fragp
->fr_symbol
;
20780 sym_frag
= symbol_get_frag (sym
);
20781 know (S_GET_SEGMENT (sym
) != absolute_section
20782 || sym_frag
== &zero_address_frag
);
20783 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20785 /* If frag has yet to be reached on this pass, assume it will
20786 move by STRETCH just as we did. If this is not so, it will
20787 be because some frag between grows, and that will force
20791 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20795 /* Adjust stretch for any alignment frag. Note that if have
20796 been expanding the earlier code, the symbol may be
20797 defined in what appears to be an earlier frag. FIXME:
20798 This doesn't handle the fr_subtype field, which specifies
20799 a maximum number of bytes to skip when doing an
20801 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20803 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20806 stretch
= - ((- stretch
)
20807 & ~ ((1 << (int) f
->fr_offset
) - 1));
20809 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20821 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20824 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20829 /* Assume worst case for symbols not known to be in the same section. */
20830 if (fragp
->fr_symbol
== NULL
20831 || !S_IS_DEFINED (fragp
->fr_symbol
)
20832 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20833 || S_IS_WEAK (fragp
->fr_symbol
))
20836 val
= relaxed_symbol_addr (fragp
, stretch
);
20837 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20838 addr
= (addr
+ 4) & ~3;
20839 /* Force misaligned targets to 32-bit variant. */
20843 if (val
< 0 || val
> 1020)
20848 /* Return the size of a relaxable add/sub immediate instruction. */
20850 relax_addsub (fragS
*fragp
, asection
*sec
)
20855 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20856 op
= bfd_get_16(sec
->owner
, buf
);
20857 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20858 return relax_immediate (fragp
, 8, 0);
20860 return relax_immediate (fragp
, 3, 0);
20863 /* Return TRUE iff the definition of symbol S could be pre-empted
20864 (overridden) at link or load time. */
20866 symbol_preemptible (symbolS
*s
)
20868 /* Weak symbols can always be pre-empted. */
20872 /* Non-global symbols cannot be pre-empted. */
20873 if (! S_IS_EXTERNAL (s
))
20877 /* In ELF, a global symbol can be marked protected, or private. In that
20878 case it can't be pre-empted (other definitions in the same link unit
20879 would violate the ODR). */
20880 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20884 /* Other global symbols might be pre-empted. */
20888 /* Return the size of a relaxable branch instruction. BITS is the
20889 size of the offset field in the narrow instruction. */
20892 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20898 /* Assume worst case for symbols not known to be in the same section. */
20899 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20900 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20901 || S_IS_WEAK (fragp
->fr_symbol
))
20905 /* A branch to a function in ARM state will require interworking. */
20906 if (S_IS_DEFINED (fragp
->fr_symbol
)
20907 && ARM_IS_FUNC (fragp
->fr_symbol
))
20911 if (symbol_preemptible (fragp
->fr_symbol
))
20914 val
= relaxed_symbol_addr (fragp
, stretch
);
20915 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20918 /* Offset is a signed value *2 */
20920 if (val
>= limit
|| val
< -limit
)
20926 /* Relax a machine dependent frag. This returns the amount by which
20927 the current size of the frag should change. */
20930 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20935 oldsize
= fragp
->fr_var
;
20936 switch (fragp
->fr_subtype
)
20938 case T_MNEM_ldr_pc2
:
20939 newsize
= relax_adr (fragp
, sec
, stretch
);
20941 case T_MNEM_ldr_pc
:
20942 case T_MNEM_ldr_sp
:
20943 case T_MNEM_str_sp
:
20944 newsize
= relax_immediate (fragp
, 8, 2);
20948 newsize
= relax_immediate (fragp
, 5, 2);
20952 newsize
= relax_immediate (fragp
, 5, 1);
20956 newsize
= relax_immediate (fragp
, 5, 0);
20959 newsize
= relax_adr (fragp
, sec
, stretch
);
20965 newsize
= relax_immediate (fragp
, 8, 0);
20968 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20971 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20973 case T_MNEM_add_sp
:
20974 case T_MNEM_add_pc
:
20975 newsize
= relax_immediate (fragp
, 8, 2);
20977 case T_MNEM_inc_sp
:
20978 case T_MNEM_dec_sp
:
20979 newsize
= relax_immediate (fragp
, 7, 2);
20985 newsize
= relax_addsub (fragp
, sec
);
20991 fragp
->fr_var
= newsize
;
20992 /* Freeze wide instructions that are at or before the same location as
20993 in the previous pass. This avoids infinite loops.
20994 Don't freeze them unconditionally because targets may be artificially
20995 misaligned by the expansion of preceding frags. */
20996 if (stretch
<= 0 && newsize
> 2)
20998 md_convert_frag (sec
->owner
, sec
, fragp
);
21002 return newsize
- oldsize
;
21005 /* Round up a section size to the appropriate boundary. */
21008 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21011 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21012 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21014 /* For a.out, force the section size to be aligned. If we don't do
21015 this, BFD will align it for us, but it will not write out the
21016 final bytes of the section. This may be a bug in BFD, but it is
21017 easier to fix it here since that is how the other a.out targets
21021 align
= bfd_get_section_alignment (stdoutput
, segment
);
21022 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
21029 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21030 of an rs_align_code fragment. */
21033 arm_handle_align (fragS
* fragP
)
21035 static char const arm_noop
[2][2][4] =
21038 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21039 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21042 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21043 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21046 static char const thumb_noop
[2][2][2] =
21049 {0xc0, 0x46}, /* LE */
21050 {0x46, 0xc0}, /* BE */
21053 {0x00, 0xbf}, /* LE */
21054 {0xbf, 0x00} /* BE */
21057 static char const wide_thumb_noop
[2][4] =
21058 { /* Wide Thumb-2 */
21059 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21060 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21063 unsigned bytes
, fix
, noop_size
;
21066 const char *narrow_noop
= NULL
;
21071 if (fragP
->fr_type
!= rs_align_code
)
21074 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21075 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21078 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21079 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21081 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21083 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21085 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21086 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21088 narrow_noop
= thumb_noop
[1][target_big_endian
];
21089 noop
= wide_thumb_noop
[target_big_endian
];
21092 noop
= thumb_noop
[0][target_big_endian
];
21100 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21101 ? selected_cpu
: arm_arch_none
,
21103 [target_big_endian
];
21110 fragP
->fr_var
= noop_size
;
21112 if (bytes
& (noop_size
- 1))
21114 fix
= bytes
& (noop_size
- 1);
21116 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21118 memset (p
, 0, fix
);
21125 if (bytes
& noop_size
)
21127 /* Insert a narrow noop. */
21128 memcpy (p
, narrow_noop
, noop_size
);
21130 bytes
-= noop_size
;
21134 /* Use wide noops for the remainder */
21138 while (bytes
>= noop_size
)
21140 memcpy (p
, noop
, noop_size
);
21142 bytes
-= noop_size
;
21146 fragP
->fr_fix
+= fix
;
21149 /* Called from md_do_align. Used to create an alignment
21150 frag in a code section. */
21153 arm_frag_align_code (int n
, int max
)
21157 /* We assume that there will never be a requirement
21158 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21159 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21164 _("alignments greater than %d bytes not supported in .text sections."),
21165 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21166 as_fatal ("%s", err_msg
);
21169 p
= frag_var (rs_align_code
,
21170 MAX_MEM_FOR_RS_ALIGN_CODE
,
21172 (relax_substateT
) max
,
21179 /* Perform target specific initialisation of a frag.
21180 Note - despite the name this initialisation is not done when the frag
21181 is created, but only when its type is assigned. A frag can be created
21182 and used a long time before its type is set, so beware of assuming that
21183 this initialisationis performed first. */
21187 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21189 /* Record whether this frag is in an ARM or a THUMB area. */
21190 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21193 #else /* OBJ_ELF is defined. */
21195 arm_init_frag (fragS
* fragP
, int max_chars
)
21197 int frag_thumb_mode
;
21199 /* If the current ARM vs THUMB mode has not already
21200 been recorded into this frag then do so now. */
21201 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21202 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21204 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21206 /* Record a mapping symbol for alignment frags. We will delete this
21207 later if the alignment ends up empty. */
21208 switch (fragP
->fr_type
)
21211 case rs_align_test
:
21213 mapping_state_2 (MAP_DATA
, max_chars
);
21215 case rs_align_code
:
21216 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21223 /* When we change sections we need to issue a new mapping symbol. */
21226 arm_elf_change_section (void)
21228 /* Link an unlinked unwind index table section to the .text section. */
21229 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21230 && elf_linked_to_section (now_seg
) == NULL
)
21231 elf_linked_to_section (now_seg
) = text_section
;
21235 arm_elf_section_type (const char * str
, size_t len
)
21237 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21238 return SHT_ARM_EXIDX
;
21243 /* Code to deal with unwinding tables. */
21245 static void add_unwind_adjustsp (offsetT
);
21247 /* Generate any deferred unwind frame offset. */
21250 flush_pending_unwind (void)
21254 offset
= unwind
.pending_offset
;
21255 unwind
.pending_offset
= 0;
21257 add_unwind_adjustsp (offset
);
21260 /* Add an opcode to this list for this function. Two-byte opcodes should
21261 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21265 add_unwind_opcode (valueT op
, int length
)
21267 /* Add any deferred stack adjustment. */
21268 if (unwind
.pending_offset
)
21269 flush_pending_unwind ();
21271 unwind
.sp_restored
= 0;
21273 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21275 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21276 if (unwind
.opcodes
)
21277 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21278 unwind
.opcode_alloc
);
21280 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21285 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21287 unwind
.opcode_count
++;
21291 /* Add unwind opcodes to adjust the stack pointer. */
21294 add_unwind_adjustsp (offsetT offset
)
21298 if (offset
> 0x200)
21300 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21305 /* Long form: 0xb2, uleb128. */
21306 /* This might not fit in a word so add the individual bytes,
21307 remembering the list is built in reverse order. */
21308 o
= (valueT
) ((offset
- 0x204) >> 2);
21310 add_unwind_opcode (0, 1);
21312 /* Calculate the uleb128 encoding of the offset. */
21316 bytes
[n
] = o
& 0x7f;
21322 /* Add the insn. */
21324 add_unwind_opcode (bytes
[n
- 1], 1);
21325 add_unwind_opcode (0xb2, 1);
21327 else if (offset
> 0x100)
21329 /* Two short opcodes. */
21330 add_unwind_opcode (0x3f, 1);
21331 op
= (offset
- 0x104) >> 2;
21332 add_unwind_opcode (op
, 1);
21334 else if (offset
> 0)
21336 /* Short opcode. */
21337 op
= (offset
- 4) >> 2;
21338 add_unwind_opcode (op
, 1);
21340 else if (offset
< 0)
21343 while (offset
> 0x100)
21345 add_unwind_opcode (0x7f, 1);
21348 op
= ((offset
- 4) >> 2) | 0x40;
21349 add_unwind_opcode (op
, 1);
21353 /* Finish the list of unwind opcodes for this function. */
21355 finish_unwind_opcodes (void)
21359 if (unwind
.fp_used
)
21361 /* Adjust sp as necessary. */
21362 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21363 flush_pending_unwind ();
21365 /* After restoring sp from the frame pointer. */
21366 op
= 0x90 | unwind
.fp_reg
;
21367 add_unwind_opcode (op
, 1);
21370 flush_pending_unwind ();
21374 /* Start an exception table entry. If idx is nonzero this is an index table
21378 start_unwind_section (const segT text_seg
, int idx
)
21380 const char * text_name
;
21381 const char * prefix
;
21382 const char * prefix_once
;
21383 const char * group_name
;
21387 size_t sec_name_len
;
21394 prefix
= ELF_STRING_ARM_unwind
;
21395 prefix_once
= ELF_STRING_ARM_unwind_once
;
21396 type
= SHT_ARM_EXIDX
;
21400 prefix
= ELF_STRING_ARM_unwind_info
;
21401 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21402 type
= SHT_PROGBITS
;
21405 text_name
= segment_name (text_seg
);
21406 if (streq (text_name
, ".text"))
21409 if (strncmp (text_name
, ".gnu.linkonce.t.",
21410 strlen (".gnu.linkonce.t.")) == 0)
21412 prefix
= prefix_once
;
21413 text_name
+= strlen (".gnu.linkonce.t.");
21416 prefix_len
= strlen (prefix
);
21417 text_len
= strlen (text_name
);
21418 sec_name_len
= prefix_len
+ text_len
;
21419 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21420 memcpy (sec_name
, prefix
, prefix_len
);
21421 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21422 sec_name
[prefix_len
+ text_len
] = '\0';
21428 /* Handle COMDAT group. */
21429 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21431 group_name
= elf_group_name (text_seg
);
21432 if (group_name
== NULL
)
21434 as_bad (_("Group section `%s' has no group signature"),
21435 segment_name (text_seg
));
21436 ignore_rest_of_line ();
21439 flags
|= SHF_GROUP
;
21443 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21445 /* Set the section link for index tables. */
21447 elf_linked_to_section (now_seg
) = text_seg
;
21451 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21452 personality routine data. Returns zero, or the index table value for
21453 an inline entry. */
21456 create_unwind_entry (int have_data
)
21461 /* The current word of data. */
21463 /* The number of bytes left in this word. */
21466 finish_unwind_opcodes ();
21468 /* Remember the current text section. */
21469 unwind
.saved_seg
= now_seg
;
21470 unwind
.saved_subseg
= now_subseg
;
21472 start_unwind_section (now_seg
, 0);
21474 if (unwind
.personality_routine
== NULL
)
21476 if (unwind
.personality_index
== -2)
21479 as_bad (_("handlerdata in cantunwind frame"));
21480 return 1; /* EXIDX_CANTUNWIND. */
21483 /* Use a default personality routine if none is specified. */
21484 if (unwind
.personality_index
== -1)
21486 if (unwind
.opcode_count
> 3)
21487 unwind
.personality_index
= 1;
21489 unwind
.personality_index
= 0;
21492 /* Space for the personality routine entry. */
21493 if (unwind
.personality_index
== 0)
21495 if (unwind
.opcode_count
> 3)
21496 as_bad (_("too many unwind opcodes for personality routine 0"));
21500 /* All the data is inline in the index table. */
21503 while (unwind
.opcode_count
> 0)
21505 unwind
.opcode_count
--;
21506 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21510 /* Pad with "finish" opcodes. */
21512 data
= (data
<< 8) | 0xb0;
21519 /* We get two opcodes "free" in the first word. */
21520 size
= unwind
.opcode_count
- 2;
21524 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21525 if (unwind
.personality_index
!= -1)
21527 as_bad (_("attempt to recreate an unwind entry"));
21531 /* An extra byte is required for the opcode count. */
21532 size
= unwind
.opcode_count
+ 1;
21535 size
= (size
+ 3) >> 2;
21537 as_bad (_("too many unwind opcodes"));
21539 frag_align (2, 0, 0);
21540 record_alignment (now_seg
, 2);
21541 unwind
.table_entry
= expr_build_dot ();
21543 /* Allocate the table entry. */
21544 ptr
= frag_more ((size
<< 2) + 4);
21545 /* PR 13449: Zero the table entries in case some of them are not used. */
21546 memset (ptr
, 0, (size
<< 2) + 4);
21547 where
= frag_now_fix () - ((size
<< 2) + 4);
21549 switch (unwind
.personality_index
)
21552 /* ??? Should this be a PLT generating relocation? */
21553 /* Custom personality routine. */
21554 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21555 BFD_RELOC_ARM_PREL31
);
21560 /* Set the first byte to the number of additional words. */
21561 data
= size
> 0 ? size
- 1 : 0;
21565 /* ABI defined personality routines. */
21567 /* Three opcodes bytes are packed into the first word. */
21574 /* The size and first two opcode bytes go in the first word. */
21575 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21580 /* Should never happen. */
21584 /* Pack the opcodes into words (MSB first), reversing the list at the same
21586 while (unwind
.opcode_count
> 0)
21590 md_number_to_chars (ptr
, data
, 4);
21595 unwind
.opcode_count
--;
21597 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21600 /* Finish off the last word. */
21603 /* Pad with "finish" opcodes. */
21605 data
= (data
<< 8) | 0xb0;
21607 md_number_to_chars (ptr
, data
, 4);
21612 /* Add an empty descriptor if there is no user-specified data. */
21613 ptr
= frag_more (4);
21614 md_number_to_chars (ptr
, 0, 4);
21621 /* Initialize the DWARF-2 unwind information for this procedure. */
21624 tc_arm_frame_initial_instructions (void)
21626 cfi_add_CFA_def_cfa (REG_SP
, 0);
21628 #endif /* OBJ_ELF */
21630 /* Convert REGNAME to a DWARF-2 register number. */
21633 tc_arm_regname_to_dw2regnum (char *regname
)
21635 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21639 /* PR 16694: Allow VFP registers as well. */
21640 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21644 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21653 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21657 exp
.X_op
= O_secrel
;
21658 exp
.X_add_symbol
= symbol
;
21659 exp
.X_add_number
= 0;
21660 emit_expr (&exp
, size
);
21664 /* MD interface: Symbol and relocation handling. */
21666 /* Return the address within the segment that a PC-relative fixup is
21667 relative to. For ARM, PC-relative fixups applied to instructions
21668 are generally relative to the location of the fixup plus 8 bytes.
21669 Thumb branches are offset by 4, and Thumb loads relative to PC
21670 require special handling. */
21673 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21675 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21677 /* If this is pc-relative and we are going to emit a relocation
21678 then we just want to put out any pipeline compensation that the linker
21679 will need. Otherwise we want to use the calculated base.
21680 For WinCE we skip the bias for externals as well, since this
21681 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21683 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21684 || (arm_force_relocation (fixP
)
21686 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21692 switch (fixP
->fx_r_type
)
21694 /* PC relative addressing on the Thumb is slightly odd as the
21695 bottom two bits of the PC are forced to zero for the
21696 calculation. This happens *after* application of the
21697 pipeline offset. However, Thumb adrl already adjusts for
21698 this, so we need not do it again. */
21699 case BFD_RELOC_ARM_THUMB_ADD
:
21702 case BFD_RELOC_ARM_THUMB_OFFSET
:
21703 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21704 case BFD_RELOC_ARM_T32_ADD_PC12
:
21705 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21706 return (base
+ 4) & ~3;
21708 /* Thumb branches are simply offset by +4. */
21709 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21710 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21711 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21712 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21713 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21716 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21718 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21719 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21720 && ARM_IS_FUNC (fixP
->fx_addsy
)
21721 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21722 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21725 /* BLX is like branches above, but forces the low two bits of PC to
21727 case BFD_RELOC_THUMB_PCREL_BLX
:
21729 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21730 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21731 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21732 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21733 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21734 return (base
+ 4) & ~3;
21736 /* ARM mode branches are offset by +8. However, the Windows CE
21737 loader expects the relocation not to take this into account. */
21738 case BFD_RELOC_ARM_PCREL_BLX
:
21740 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21741 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21742 && ARM_IS_FUNC (fixP
->fx_addsy
)
21743 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21744 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21747 case BFD_RELOC_ARM_PCREL_CALL
:
21749 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21750 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21751 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21752 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21753 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21756 case BFD_RELOC_ARM_PCREL_BRANCH
:
21757 case BFD_RELOC_ARM_PCREL_JUMP
:
21758 case BFD_RELOC_ARM_PLT32
:
21760 /* When handling fixups immediately, because we have already
21761 discovered the value of a symbol, or the address of the frag involved
21762 we must account for the offset by +8, as the OS loader will never see the reloc.
21763 see fixup_segment() in write.c
21764 The S_IS_EXTERNAL test handles the case of global symbols.
21765 Those need the calculated base, not just the pipe compensation the linker will need. */
21767 && fixP
->fx_addsy
!= NULL
21768 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21769 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21777 /* ARM mode loads relative to PC are also offset by +8. Unlike
21778 branches, the Windows CE loader *does* expect the relocation
21779 to take this into account. */
21780 case BFD_RELOC_ARM_OFFSET_IMM
:
21781 case BFD_RELOC_ARM_OFFSET_IMM8
:
21782 case BFD_RELOC_ARM_HWLITERAL
:
21783 case BFD_RELOC_ARM_LITERAL
:
21784 case BFD_RELOC_ARM_CP_OFF_IMM
:
21788 /* Other PC-relative relocations are un-offset. */
21794 static bfd_boolean flag_warn_syms
= TRUE
;
21797 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21799 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21800 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21801 does mean that the resulting code might be very confusing to the reader.
21802 Also this warning can be triggered if the user omits an operand before
21803 an immediate address, eg:
21807 GAS treats this as an assignment of the value of the symbol foo to a
21808 symbol LDR, and so (without this code) it will not issue any kind of
21809 warning or error message.
21811 Note - ARM instructions are case-insensitive but the strings in the hash
21812 table are all stored in lower case, so we must first ensure that name is
21814 if (flag_warn_syms
&& arm_ops_hsh
)
21816 char * nbuf
= strdup (name
);
21819 for (p
= nbuf
; *p
; p
++)
21821 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21823 static struct hash_control
* already_warned
= NULL
;
21825 if (already_warned
== NULL
)
21826 already_warned
= hash_new ();
21827 /* Only warn about the symbol once. To keep the code
21828 simple we let hash_insert do the lookup for us. */
21829 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21830 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21839 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21840 Otherwise we have no need to default values of symbols. */
21843 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21846 if (name
[0] == '_' && name
[1] == 'G'
21847 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21851 if (symbol_find (name
))
21852 as_bad (_("GOT already in the symbol table"));
21854 GOT_symbol
= symbol_new (name
, undefined_section
,
21855 (valueT
) 0, & zero_address_frag
);
21865 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21866 computed as two separate immediate values, added together. We
21867 already know that this value cannot be computed by just one ARM
21870 static unsigned int
21871 validate_immediate_twopart (unsigned int val
,
21872 unsigned int * highpart
)
21877 for (i
= 0; i
< 32; i
+= 2)
21878 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21884 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21886 else if (a
& 0xff0000)
21888 if (a
& 0xff000000)
21890 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21894 gas_assert (a
& 0xff000000);
21895 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21898 return (a
& 0xff) | (i
<< 7);
21905 validate_offset_imm (unsigned int val
, int hwse
)
21907 if ((hwse
&& val
> 255) || val
> 4095)
21912 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21913 negative immediate constant by altering the instruction. A bit of
21918 by inverting the second operand, and
21921 by negating the second operand. */
21924 negate_data_op (unsigned long * instruction
,
21925 unsigned long value
)
21928 unsigned long negated
, inverted
;
21930 negated
= encode_arm_immediate (-value
);
21931 inverted
= encode_arm_immediate (~value
);
21933 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21936 /* First negates. */
21937 case OPCODE_SUB
: /* ADD <-> SUB */
21938 new_inst
= OPCODE_ADD
;
21943 new_inst
= OPCODE_SUB
;
21947 case OPCODE_CMP
: /* CMP <-> CMN */
21948 new_inst
= OPCODE_CMN
;
21953 new_inst
= OPCODE_CMP
;
21957 /* Now Inverted ops. */
21958 case OPCODE_MOV
: /* MOV <-> MVN */
21959 new_inst
= OPCODE_MVN
;
21964 new_inst
= OPCODE_MOV
;
21968 case OPCODE_AND
: /* AND <-> BIC */
21969 new_inst
= OPCODE_BIC
;
21974 new_inst
= OPCODE_AND
;
21978 case OPCODE_ADC
: /* ADC <-> SBC */
21979 new_inst
= OPCODE_SBC
;
21984 new_inst
= OPCODE_ADC
;
21988 /* We cannot do anything. */
21993 if (value
== (unsigned) FAIL
)
21996 *instruction
&= OPCODE_MASK
;
21997 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22001 /* Like negate_data_op, but for Thumb-2. */
22003 static unsigned int
22004 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22008 unsigned int negated
, inverted
;
22010 negated
= encode_thumb32_immediate (-value
);
22011 inverted
= encode_thumb32_immediate (~value
);
22013 rd
= (*instruction
>> 8) & 0xf;
22014 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22017 /* ADD <-> SUB. Includes CMP <-> CMN. */
22018 case T2_OPCODE_SUB
:
22019 new_inst
= T2_OPCODE_ADD
;
22023 case T2_OPCODE_ADD
:
22024 new_inst
= T2_OPCODE_SUB
;
22028 /* ORR <-> ORN. Includes MOV <-> MVN. */
22029 case T2_OPCODE_ORR
:
22030 new_inst
= T2_OPCODE_ORN
;
22034 case T2_OPCODE_ORN
:
22035 new_inst
= T2_OPCODE_ORR
;
22039 /* AND <-> BIC. TST has no inverted equivalent. */
22040 case T2_OPCODE_AND
:
22041 new_inst
= T2_OPCODE_BIC
;
22048 case T2_OPCODE_BIC
:
22049 new_inst
= T2_OPCODE_AND
;
22054 case T2_OPCODE_ADC
:
22055 new_inst
= T2_OPCODE_SBC
;
22059 case T2_OPCODE_SBC
:
22060 new_inst
= T2_OPCODE_ADC
;
22064 /* We cannot do anything. */
22069 if (value
== (unsigned int)FAIL
)
22072 *instruction
&= T2_OPCODE_MASK
;
22073 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22077 /* Read a 32-bit thumb instruction from buf. */
22078 static unsigned long
22079 get_thumb32_insn (char * buf
)
22081 unsigned long insn
;
22082 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22083 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22089 /* We usually want to set the low bit on the address of thumb function
22090 symbols. In particular .word foo - . should have the low bit set.
22091 Generic code tries to fold the difference of two symbols to
22092 a constant. Prevent this and force a relocation when the first symbols
22093 is a thumb function. */
22096 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22098 if (op
== O_subtract
22099 && l
->X_op
== O_symbol
22100 && r
->X_op
== O_symbol
22101 && THUMB_IS_FUNC (l
->X_add_symbol
))
22103 l
->X_op
= O_subtract
;
22104 l
->X_op_symbol
= r
->X_add_symbol
;
22105 l
->X_add_number
-= r
->X_add_number
;
22109 /* Process as normal. */
22113 /* Encode Thumb2 unconditional branches and calls. The encoding
22114 for the 2 are identical for the immediate values. */
22117 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22119 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22122 addressT S
, I1
, I2
, lo
, hi
;
22124 S
= (value
>> 24) & 0x01;
22125 I1
= (value
>> 23) & 0x01;
22126 I2
= (value
>> 22) & 0x01;
22127 hi
= (value
>> 12) & 0x3ff;
22128 lo
= (value
>> 1) & 0x7ff;
22129 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22130 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22131 newval
|= (S
<< 10) | hi
;
22132 newval2
&= ~T2I1I2MASK
;
22133 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22134 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22135 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22139 md_apply_fix (fixS
* fixP
,
22143 offsetT value
= * valP
;
22145 unsigned int newimm
;
22146 unsigned long temp
;
22148 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22150 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22152 /* Note whether this will delete the relocation. */
22154 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22157 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22158 consistency with the behaviour on 32-bit hosts. Remember value
22160 value
&= 0xffffffff;
22161 value
^= 0x80000000;
22162 value
-= 0x80000000;
22165 fixP
->fx_addnumber
= value
;
22167 /* Same treatment for fixP->fx_offset. */
22168 fixP
->fx_offset
&= 0xffffffff;
22169 fixP
->fx_offset
^= 0x80000000;
22170 fixP
->fx_offset
-= 0x80000000;
22172 switch (fixP
->fx_r_type
)
22174 case BFD_RELOC_NONE
:
22175 /* This will need to go in the object file. */
22179 case BFD_RELOC_ARM_IMMEDIATE
:
22180 /* We claim that this fixup has been processed here,
22181 even if in fact we generate an error because we do
22182 not have a reloc for it, so tc_gen_reloc will reject it. */
22185 if (fixP
->fx_addsy
)
22187 const char *msg
= 0;
22189 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22190 msg
= _("undefined symbol %s used as an immediate value");
22191 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22192 msg
= _("symbol %s is in a different section");
22193 else if (S_IS_WEAK (fixP
->fx_addsy
))
22194 msg
= _("symbol %s is weak and may be overridden later");
22198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22199 msg
, S_GET_NAME (fixP
->fx_addsy
));
22204 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22206 /* If the offset is negative, we should use encoding A2 for ADR. */
22207 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22208 newimm
= negate_data_op (&temp
, value
);
22211 newimm
= encode_arm_immediate (value
);
22213 /* If the instruction will fail, see if we can fix things up by
22214 changing the opcode. */
22215 if (newimm
== (unsigned int) FAIL
)
22216 newimm
= negate_data_op (&temp
, value
);
22219 if (newimm
== (unsigned int) FAIL
)
22221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22222 _("invalid constant (%lx) after fixup"),
22223 (unsigned long) value
);
22227 newimm
|= (temp
& 0xfffff000);
22228 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22231 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22233 unsigned int highpart
= 0;
22234 unsigned int newinsn
= 0xe1a00000; /* nop. */
22236 if (fixP
->fx_addsy
)
22238 const char *msg
= 0;
22240 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22241 msg
= _("undefined symbol %s used as an immediate value");
22242 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22243 msg
= _("symbol %s is in a different section");
22244 else if (S_IS_WEAK (fixP
->fx_addsy
))
22245 msg
= _("symbol %s is weak and may be overridden later");
22249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22250 msg
, S_GET_NAME (fixP
->fx_addsy
));
22255 newimm
= encode_arm_immediate (value
);
22256 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22258 /* If the instruction will fail, see if we can fix things up by
22259 changing the opcode. */
22260 if (newimm
== (unsigned int) FAIL
22261 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22263 /* No ? OK - try using two ADD instructions to generate
22265 newimm
= validate_immediate_twopart (value
, & highpart
);
22267 /* Yes - then make sure that the second instruction is
22269 if (newimm
!= (unsigned int) FAIL
)
22271 /* Still No ? Try using a negated value. */
22272 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22273 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22274 /* Otherwise - give up. */
22277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22278 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22283 /* Replace the first operand in the 2nd instruction (which
22284 is the PC) with the destination register. We have
22285 already added in the PC in the first instruction and we
22286 do not want to do it again. */
22287 newinsn
&= ~ 0xf0000;
22288 newinsn
|= ((newinsn
& 0x0f000) << 4);
22291 newimm
|= (temp
& 0xfffff000);
22292 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22294 highpart
|= (newinsn
& 0xfffff000);
22295 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22299 case BFD_RELOC_ARM_OFFSET_IMM
:
22300 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22303 case BFD_RELOC_ARM_LITERAL
:
22309 if (validate_offset_imm (value
, 0) == FAIL
)
22311 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22313 _("invalid literal constant: pool needs to be closer"));
22315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22316 _("bad immediate value for offset (%ld)"),
22321 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22323 newval
&= 0xfffff000;
22326 newval
&= 0xff7ff000;
22327 newval
|= value
| (sign
? INDEX_UP
: 0);
22329 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22332 case BFD_RELOC_ARM_OFFSET_IMM8
:
22333 case BFD_RELOC_ARM_HWLITERAL
:
22339 if (validate_offset_imm (value
, 1) == FAIL
)
22341 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22343 _("invalid literal constant: pool needs to be closer"));
22345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22346 _("bad immediate value for 8-bit offset (%ld)"),
22351 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22353 newval
&= 0xfffff0f0;
22356 newval
&= 0xff7ff0f0;
22357 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22359 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22362 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22363 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22365 _("bad immediate value for offset (%ld)"), (long) value
);
22368 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22370 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22373 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22374 /* This is a complicated relocation used for all varieties of Thumb32
22375 load/store instruction with immediate offset:
22377 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22378 *4, optional writeback(W)
22379 (doubleword load/store)
22381 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22382 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22383 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22384 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22385 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22387 Uppercase letters indicate bits that are already encoded at
22388 this point. Lowercase letters are our problem. For the
22389 second block of instructions, the secondary opcode nybble
22390 (bits 8..11) is present, and bit 23 is zero, even if this is
22391 a PC-relative operation. */
22392 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22394 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22396 if ((newval
& 0xf0000000) == 0xe0000000)
22398 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22400 newval
|= (1 << 23);
22403 if (value
% 4 != 0)
22405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22406 _("offset not a multiple of 4"));
22412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22413 _("offset out of range"));
22418 else if ((newval
& 0x000f0000) == 0x000f0000)
22420 /* PC-relative, 12-bit offset. */
22422 newval
|= (1 << 23);
22427 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22428 _("offset out of range"));
22433 else if ((newval
& 0x00000100) == 0x00000100)
22435 /* Writeback: 8-bit, +/- offset. */
22437 newval
|= (1 << 9);
22442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22443 _("offset out of range"));
22448 else if ((newval
& 0x00000f00) == 0x00000e00)
22450 /* T-instruction: positive 8-bit offset. */
22451 if (value
< 0 || value
> 0xff)
22453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22454 _("offset out of range"));
22462 /* Positive 12-bit or negative 8-bit offset. */
22466 newval
|= (1 << 23);
22476 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22477 _("offset out of range"));
22484 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22485 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22488 case BFD_RELOC_ARM_SHIFT_IMM
:
22489 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22490 if (((unsigned long) value
) > 32
22492 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22495 _("shift expression is too large"));
22500 /* Shifts of zero must be done as lsl. */
22502 else if (value
== 32)
22504 newval
&= 0xfffff07f;
22505 newval
|= (value
& 0x1f) << 7;
22506 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22509 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22510 case BFD_RELOC_ARM_T32_ADD_IMM
:
22511 case BFD_RELOC_ARM_T32_IMM12
:
22512 case BFD_RELOC_ARM_T32_ADD_PC12
:
22513 /* We claim that this fixup has been processed here,
22514 even if in fact we generate an error because we do
22515 not have a reloc for it, so tc_gen_reloc will reject it. */
22519 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22522 _("undefined symbol %s used as an immediate value"),
22523 S_GET_NAME (fixP
->fx_addsy
));
22527 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22529 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22532 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22533 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22535 newimm
= encode_thumb32_immediate (value
);
22536 if (newimm
== (unsigned int) FAIL
)
22537 newimm
= thumb32_negate_data_op (&newval
, value
);
22539 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22540 && newimm
== (unsigned int) FAIL
)
22542 /* Turn add/sum into addw/subw. */
22543 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22544 newval
= (newval
& 0xfeffffff) | 0x02000000;
22545 /* No flat 12-bit imm encoding for addsw/subsw. */
22546 if ((newval
& 0x00100000) == 0)
22548 /* 12 bit immediate for addw/subw. */
22552 newval
^= 0x00a00000;
22555 newimm
= (unsigned int) FAIL
;
22561 if (newimm
== (unsigned int)FAIL
)
22563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22564 _("invalid constant (%lx) after fixup"),
22565 (unsigned long) value
);
22569 newval
|= (newimm
& 0x800) << 15;
22570 newval
|= (newimm
& 0x700) << 4;
22571 newval
|= (newimm
& 0x0ff);
22573 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22574 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22577 case BFD_RELOC_ARM_SMC
:
22578 if (((unsigned long) value
) > 0xffff)
22579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22580 _("invalid smc expression"));
22581 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22582 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22586 case BFD_RELOC_ARM_HVC
:
22587 if (((unsigned long) value
) > 0xffff)
22588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22589 _("invalid hvc expression"));
22590 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22591 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22592 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22595 case BFD_RELOC_ARM_SWI
:
22596 if (fixP
->tc_fix_data
!= 0)
22598 if (((unsigned long) value
) > 0xff)
22599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22600 _("invalid swi expression"));
22601 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22603 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22607 if (((unsigned long) value
) > 0x00ffffff)
22608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22609 _("invalid swi expression"));
22610 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22612 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22616 case BFD_RELOC_ARM_MULTI
:
22617 if (((unsigned long) value
) > 0xffff)
22618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22619 _("invalid expression in load/store multiple"));
22620 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22621 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22625 case BFD_RELOC_ARM_PCREL_CALL
:
22627 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22629 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22630 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22631 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22632 /* Flip the bl to blx. This is a simple flip
22633 bit here because we generate PCREL_CALL for
22634 unconditional bls. */
22636 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22637 newval
= newval
| 0x10000000;
22638 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22644 goto arm_branch_common
;
22646 case BFD_RELOC_ARM_PCREL_JUMP
:
22647 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22649 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22650 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22651 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22653 /* This would map to a bl<cond>, b<cond>,
22654 b<always> to a Thumb function. We
22655 need to force a relocation for this particular
22657 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22661 case BFD_RELOC_ARM_PLT32
:
22663 case BFD_RELOC_ARM_PCREL_BRANCH
:
22665 goto arm_branch_common
;
22667 case BFD_RELOC_ARM_PCREL_BLX
:
22670 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22672 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22673 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22674 && ARM_IS_FUNC (fixP
->fx_addsy
))
22676 /* Flip the blx to a bl and warn. */
22677 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22678 newval
= 0xeb000000;
22679 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22680 _("blx to '%s' an ARM ISA state function changed to bl"),
22682 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22688 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22689 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22693 /* We are going to store value (shifted right by two) in the
22694 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22695 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22696 also be be clear. */
22698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22699 _("misaligned branch destination"));
22700 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22701 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22704 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22706 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22707 newval
|= (value
>> 2) & 0x00ffffff;
22708 /* Set the H bit on BLX instructions. */
22712 newval
|= 0x01000000;
22714 newval
&= ~0x01000000;
22716 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22720 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22721 /* CBZ can only branch forward. */
22723 /* Attempts to use CBZ to branch to the next instruction
22724 (which, strictly speaking, are prohibited) will be turned into
22727 FIXME: It may be better to remove the instruction completely and
22728 perform relaxation. */
22731 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22732 newval
= 0xbf00; /* NOP encoding T1 */
22733 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22740 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22742 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22743 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22744 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22749 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22750 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22753 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22755 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22756 newval
|= (value
& 0x1ff) >> 1;
22757 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22761 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22762 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22765 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22767 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22768 newval
|= (value
& 0xfff) >> 1;
22769 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22773 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22775 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22776 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22777 && ARM_IS_FUNC (fixP
->fx_addsy
)
22778 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22780 /* Force a relocation for a branch 20 bits wide. */
22783 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22785 _("conditional branch out of range"));
22787 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22790 addressT S
, J1
, J2
, lo
, hi
;
22792 S
= (value
& 0x00100000) >> 20;
22793 J2
= (value
& 0x00080000) >> 19;
22794 J1
= (value
& 0x00040000) >> 18;
22795 hi
= (value
& 0x0003f000) >> 12;
22796 lo
= (value
& 0x00000ffe) >> 1;
22798 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22799 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22800 newval
|= (S
<< 10) | hi
;
22801 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22802 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22803 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22807 case BFD_RELOC_THUMB_PCREL_BLX
:
22808 /* If there is a blx from a thumb state function to
22809 another thumb function flip this to a bl and warn
22813 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22814 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22815 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22817 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22818 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22819 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22821 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22822 newval
= newval
| 0x1000;
22823 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22824 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22829 goto thumb_bl_common
;
22831 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22832 /* A bl from Thumb state ISA to an internal ARM state function
22833 is converted to a blx. */
22835 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22836 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22837 && ARM_IS_FUNC (fixP
->fx_addsy
)
22838 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22840 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22841 newval
= newval
& ~0x1000;
22842 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22843 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22849 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22850 /* For a BLX instruction, make sure that the relocation is rounded up
22851 to a word boundary. This follows the semantics of the instruction
22852 which specifies that bit 1 of the target address will come from bit
22853 1 of the base address. */
22854 value
= (value
+ 3) & ~ 3;
22857 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22858 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22859 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22862 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22864 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22866 else if ((value
& ~0x1ffffff)
22867 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22869 _("Thumb2 branch out of range"));
22872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22873 encode_thumb2_b_bl_offset (buf
, value
);
22877 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22878 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22881 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22882 encode_thumb2_b_bl_offset (buf
, value
);
22887 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22892 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22893 md_number_to_chars (buf
, value
, 2);
22897 case BFD_RELOC_ARM_TLS_CALL
:
22898 case BFD_RELOC_ARM_THM_TLS_CALL
:
22899 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22900 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22901 case BFD_RELOC_ARM_TLS_GOTDESC
:
22902 case BFD_RELOC_ARM_TLS_GD32
:
22903 case BFD_RELOC_ARM_TLS_LE32
:
22904 case BFD_RELOC_ARM_TLS_IE32
:
22905 case BFD_RELOC_ARM_TLS_LDM32
:
22906 case BFD_RELOC_ARM_TLS_LDO32
:
22907 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22910 case BFD_RELOC_ARM_GOT32
:
22911 case BFD_RELOC_ARM_GOTOFF
:
22914 case BFD_RELOC_ARM_GOT_PREL
:
22915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22916 md_number_to_chars (buf
, value
, 4);
22919 case BFD_RELOC_ARM_TARGET2
:
22920 /* TARGET2 is not partial-inplace, so we need to write the
22921 addend here for REL targets, because it won't be written out
22922 during reloc processing later. */
22923 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22924 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22928 case BFD_RELOC_RVA
:
22930 case BFD_RELOC_ARM_TARGET1
:
22931 case BFD_RELOC_ARM_ROSEGREL32
:
22932 case BFD_RELOC_ARM_SBREL32
:
22933 case BFD_RELOC_32_PCREL
:
22935 case BFD_RELOC_32_SECREL
:
22937 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22939 /* For WinCE we only do this for pcrel fixups. */
22940 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22942 md_number_to_chars (buf
, value
, 4);
22946 case BFD_RELOC_ARM_PREL31
:
22947 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22949 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22950 if ((value
^ (value
>> 1)) & 0x40000000)
22952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22953 _("rel31 relocation overflow"));
22955 newval
|= value
& 0x7fffffff;
22956 md_number_to_chars (buf
, newval
, 4);
22961 case BFD_RELOC_ARM_CP_OFF_IMM
:
22962 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22963 if (value
< -1023 || value
> 1023 || (value
& 3))
22964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22965 _("co-processor offset out of range"));
22970 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22971 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22972 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22974 newval
= get_thumb32_insn (buf
);
22976 newval
&= 0xffffff00;
22979 newval
&= 0xff7fff00;
22980 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22982 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22983 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22984 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22986 put_thumb32_insn (buf
, newval
);
22989 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22990 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22991 if (value
< -255 || value
> 255)
22992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22993 _("co-processor offset out of range"));
22995 goto cp_off_common
;
22997 case BFD_RELOC_ARM_THUMB_OFFSET
:
22998 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22999 /* Exactly what ranges, and where the offset is inserted depends
23000 on the type of instruction, we can establish this from the
23002 switch (newval
>> 12)
23004 case 4: /* PC load. */
23005 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23006 forced to zero for these loads; md_pcrel_from has already
23007 compensated for this. */
23009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23010 _("invalid offset, target not word aligned (0x%08lX)"),
23011 (((unsigned long) fixP
->fx_frag
->fr_address
23012 + (unsigned long) fixP
->fx_where
) & ~3)
23013 + (unsigned long) value
);
23015 if (value
& ~0x3fc)
23016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23017 _("invalid offset, value too big (0x%08lX)"),
23020 newval
|= value
>> 2;
23023 case 9: /* SP load/store. */
23024 if (value
& ~0x3fc)
23025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23026 _("invalid offset, value too big (0x%08lX)"),
23028 newval
|= value
>> 2;
23031 case 6: /* Word load/store. */
23033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23034 _("invalid offset, value too big (0x%08lX)"),
23036 newval
|= value
<< 4; /* 6 - 2. */
23039 case 7: /* Byte load/store. */
23041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23042 _("invalid offset, value too big (0x%08lX)"),
23044 newval
|= value
<< 6;
23047 case 8: /* Halfword load/store. */
23049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23050 _("invalid offset, value too big (0x%08lX)"),
23052 newval
|= value
<< 5; /* 6 - 1. */
23056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23057 "Unable to process relocation for thumb opcode: %lx",
23058 (unsigned long) newval
);
23061 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23064 case BFD_RELOC_ARM_THUMB_ADD
:
23065 /* This is a complicated relocation, since we use it for all of
23066 the following immediate relocations:
23070 9bit ADD/SUB SP word-aligned
23071 10bit ADD PC/SP word-aligned
23073 The type of instruction being processed is encoded in the
23080 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23082 int rd
= (newval
>> 4) & 0xf;
23083 int rs
= newval
& 0xf;
23084 int subtract
= !!(newval
& 0x8000);
23086 /* Check for HI regs, only very restricted cases allowed:
23087 Adjusting SP, and using PC or SP to get an address. */
23088 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23089 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23091 _("invalid Hi register with immediate"));
23093 /* If value is negative, choose the opposite instruction. */
23097 subtract
= !subtract
;
23099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23100 _("immediate value out of range"));
23105 if (value
& ~0x1fc)
23106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23107 _("invalid immediate for stack address calculation"));
23108 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23109 newval
|= value
>> 2;
23111 else if (rs
== REG_PC
|| rs
== REG_SP
)
23113 /* PR gas/18541. If the addition is for a defined symbol
23114 within range of an ADR instruction then accept it. */
23117 && fixP
->fx_addsy
!= NULL
)
23121 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23122 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23123 || S_IS_WEAK (fixP
->fx_addsy
))
23125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23126 _("address calculation needs a strongly defined nearby symbol"));
23130 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23132 /* Round up to the next 4-byte boundary. */
23137 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23141 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23142 _("symbol too far away"));
23152 if (subtract
|| value
& ~0x3fc)
23153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23154 _("invalid immediate for address calculation (value = 0x%08lX)"),
23155 (unsigned long) (subtract
? - value
: value
));
23156 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23158 newval
|= value
>> 2;
23163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23164 _("immediate value out of range"));
23165 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23166 newval
|= (rd
<< 8) | value
;
23171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23172 _("immediate value out of range"));
23173 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23174 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23177 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23180 case BFD_RELOC_ARM_THUMB_IMM
:
23181 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23182 if (value
< 0 || value
> 255)
23183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23184 _("invalid immediate: %ld is out of range"),
23187 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23190 case BFD_RELOC_ARM_THUMB_SHIFT
:
23191 /* 5bit shift value (0..32). LSL cannot take 32. */
23192 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23193 temp
= newval
& 0xf800;
23194 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23195 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23196 _("invalid shift value: %ld"), (long) value
);
23197 /* Shifts of zero must be encoded as LSL. */
23199 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23200 /* Shifts of 32 are encoded as zero. */
23201 else if (value
== 32)
23203 newval
|= value
<< 6;
23204 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23207 case BFD_RELOC_VTABLE_INHERIT
:
23208 case BFD_RELOC_VTABLE_ENTRY
:
23212 case BFD_RELOC_ARM_MOVW
:
23213 case BFD_RELOC_ARM_MOVT
:
23214 case BFD_RELOC_ARM_THUMB_MOVW
:
23215 case BFD_RELOC_ARM_THUMB_MOVT
:
23216 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23218 /* REL format relocations are limited to a 16-bit addend. */
23219 if (!fixP
->fx_done
)
23221 if (value
< -0x8000 || value
> 0x7fff)
23222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23223 _("offset out of range"));
23225 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23226 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23231 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23232 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23234 newval
= get_thumb32_insn (buf
);
23235 newval
&= 0xfbf08f00;
23236 newval
|= (value
& 0xf000) << 4;
23237 newval
|= (value
& 0x0800) << 15;
23238 newval
|= (value
& 0x0700) << 4;
23239 newval
|= (value
& 0x00ff);
23240 put_thumb32_insn (buf
, newval
);
23244 newval
= md_chars_to_number (buf
, 4);
23245 newval
&= 0xfff0f000;
23246 newval
|= value
& 0x0fff;
23247 newval
|= (value
& 0xf000) << 4;
23248 md_number_to_chars (buf
, newval
, 4);
23253 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23254 case BFD_RELOC_ARM_ALU_PC_G0
:
23255 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23256 case BFD_RELOC_ARM_ALU_PC_G1
:
23257 case BFD_RELOC_ARM_ALU_PC_G2
:
23258 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23259 case BFD_RELOC_ARM_ALU_SB_G0
:
23260 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23261 case BFD_RELOC_ARM_ALU_SB_G1
:
23262 case BFD_RELOC_ARM_ALU_SB_G2
:
23263 gas_assert (!fixP
->fx_done
);
23264 if (!seg
->use_rela_p
)
23267 bfd_vma encoded_addend
;
23268 bfd_vma addend_abs
= abs (value
);
23270 /* Check that the absolute value of the addend can be
23271 expressed as an 8-bit constant plus a rotation. */
23272 encoded_addend
= encode_arm_immediate (addend_abs
);
23273 if (encoded_addend
== (unsigned int) FAIL
)
23274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23275 _("the offset 0x%08lX is not representable"),
23276 (unsigned long) addend_abs
);
23278 /* Extract the instruction. */
23279 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23281 /* If the addend is positive, use an ADD instruction.
23282 Otherwise use a SUB. Take care not to destroy the S bit. */
23283 insn
&= 0xff1fffff;
23289 /* Place the encoded addend into the first 12 bits of the
23291 insn
&= 0xfffff000;
23292 insn
|= encoded_addend
;
23294 /* Update the instruction. */
23295 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23299 case BFD_RELOC_ARM_LDR_PC_G0
:
23300 case BFD_RELOC_ARM_LDR_PC_G1
:
23301 case BFD_RELOC_ARM_LDR_PC_G2
:
23302 case BFD_RELOC_ARM_LDR_SB_G0
:
23303 case BFD_RELOC_ARM_LDR_SB_G1
:
23304 case BFD_RELOC_ARM_LDR_SB_G2
:
23305 gas_assert (!fixP
->fx_done
);
23306 if (!seg
->use_rela_p
)
23309 bfd_vma addend_abs
= abs (value
);
23311 /* Check that the absolute value of the addend can be
23312 encoded in 12 bits. */
23313 if (addend_abs
>= 0x1000)
23314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23315 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23316 (unsigned long) addend_abs
);
23318 /* Extract the instruction. */
23319 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23321 /* If the addend is negative, clear bit 23 of the instruction.
23322 Otherwise set it. */
23324 insn
&= ~(1 << 23);
23328 /* Place the absolute value of the addend into the first 12 bits
23329 of the instruction. */
23330 insn
&= 0xfffff000;
23331 insn
|= addend_abs
;
23333 /* Update the instruction. */
23334 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23338 case BFD_RELOC_ARM_LDRS_PC_G0
:
23339 case BFD_RELOC_ARM_LDRS_PC_G1
:
23340 case BFD_RELOC_ARM_LDRS_PC_G2
:
23341 case BFD_RELOC_ARM_LDRS_SB_G0
:
23342 case BFD_RELOC_ARM_LDRS_SB_G1
:
23343 case BFD_RELOC_ARM_LDRS_SB_G2
:
23344 gas_assert (!fixP
->fx_done
);
23345 if (!seg
->use_rela_p
)
23348 bfd_vma addend_abs
= abs (value
);
23350 /* Check that the absolute value of the addend can be
23351 encoded in 8 bits. */
23352 if (addend_abs
>= 0x100)
23353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23354 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23355 (unsigned long) addend_abs
);
23357 /* Extract the instruction. */
23358 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23360 /* If the addend is negative, clear bit 23 of the instruction.
23361 Otherwise set it. */
23363 insn
&= ~(1 << 23);
23367 /* Place the first four bits of the absolute value of the addend
23368 into the first 4 bits of the instruction, and the remaining
23369 four into bits 8 .. 11. */
23370 insn
&= 0xfffff0f0;
23371 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23373 /* Update the instruction. */
23374 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23378 case BFD_RELOC_ARM_LDC_PC_G0
:
23379 case BFD_RELOC_ARM_LDC_PC_G1
:
23380 case BFD_RELOC_ARM_LDC_PC_G2
:
23381 case BFD_RELOC_ARM_LDC_SB_G0
:
23382 case BFD_RELOC_ARM_LDC_SB_G1
:
23383 case BFD_RELOC_ARM_LDC_SB_G2
:
23384 gas_assert (!fixP
->fx_done
);
23385 if (!seg
->use_rela_p
)
23388 bfd_vma addend_abs
= abs (value
);
23390 /* Check that the absolute value of the addend is a multiple of
23391 four and, when divided by four, fits in 8 bits. */
23392 if (addend_abs
& 0x3)
23393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23394 _("bad offset 0x%08lX (must be word-aligned)"),
23395 (unsigned long) addend_abs
);
23397 if ((addend_abs
>> 2) > 0xff)
23398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23399 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23400 (unsigned long) addend_abs
);
23402 /* Extract the instruction. */
23403 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23405 /* If the addend is negative, clear bit 23 of the instruction.
23406 Otherwise set it. */
23408 insn
&= ~(1 << 23);
23412 /* Place the addend (divided by four) into the first eight
23413 bits of the instruction. */
23414 insn
&= 0xfffffff0;
23415 insn
|= addend_abs
>> 2;
23417 /* Update the instruction. */
23418 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23422 case BFD_RELOC_ARM_V4BX
:
23423 /* This will need to go in the object file. */
23427 case BFD_RELOC_UNUSED
:
23429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23430 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23434 /* Translate internal representation of relocation info to BFD target
23438 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23441 bfd_reloc_code_real_type code
;
23443 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23445 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23446 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23447 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23449 if (fixp
->fx_pcrel
)
23451 if (section
->use_rela_p
)
23452 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23454 fixp
->fx_offset
= reloc
->address
;
23456 reloc
->addend
= fixp
->fx_offset
;
23458 switch (fixp
->fx_r_type
)
23461 if (fixp
->fx_pcrel
)
23463 code
= BFD_RELOC_8_PCREL
;
23468 if (fixp
->fx_pcrel
)
23470 code
= BFD_RELOC_16_PCREL
;
23475 if (fixp
->fx_pcrel
)
23477 code
= BFD_RELOC_32_PCREL
;
23481 case BFD_RELOC_ARM_MOVW
:
23482 if (fixp
->fx_pcrel
)
23484 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23488 case BFD_RELOC_ARM_MOVT
:
23489 if (fixp
->fx_pcrel
)
23491 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23495 case BFD_RELOC_ARM_THUMB_MOVW
:
23496 if (fixp
->fx_pcrel
)
23498 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23502 case BFD_RELOC_ARM_THUMB_MOVT
:
23503 if (fixp
->fx_pcrel
)
23505 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23509 case BFD_RELOC_NONE
:
23510 case BFD_RELOC_ARM_PCREL_BRANCH
:
23511 case BFD_RELOC_ARM_PCREL_BLX
:
23512 case BFD_RELOC_RVA
:
23513 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23514 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23515 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23516 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23517 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23518 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23519 case BFD_RELOC_VTABLE_ENTRY
:
23520 case BFD_RELOC_VTABLE_INHERIT
:
23522 case BFD_RELOC_32_SECREL
:
23524 code
= fixp
->fx_r_type
;
23527 case BFD_RELOC_THUMB_PCREL_BLX
:
23529 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23530 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23533 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23536 case BFD_RELOC_ARM_LITERAL
:
23537 case BFD_RELOC_ARM_HWLITERAL
:
23538 /* If this is called then the a literal has
23539 been referenced across a section boundary. */
23540 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23541 _("literal referenced across section boundary"));
23545 case BFD_RELOC_ARM_TLS_CALL
:
23546 case BFD_RELOC_ARM_THM_TLS_CALL
:
23547 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23548 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23549 case BFD_RELOC_ARM_GOT32
:
23550 case BFD_RELOC_ARM_GOTOFF
:
23551 case BFD_RELOC_ARM_GOT_PREL
:
23552 case BFD_RELOC_ARM_PLT32
:
23553 case BFD_RELOC_ARM_TARGET1
:
23554 case BFD_RELOC_ARM_ROSEGREL32
:
23555 case BFD_RELOC_ARM_SBREL32
:
23556 case BFD_RELOC_ARM_PREL31
:
23557 case BFD_RELOC_ARM_TARGET2
:
23558 case BFD_RELOC_ARM_TLS_LDO32
:
23559 case BFD_RELOC_ARM_PCREL_CALL
:
23560 case BFD_RELOC_ARM_PCREL_JUMP
:
23561 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23562 case BFD_RELOC_ARM_ALU_PC_G0
:
23563 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23564 case BFD_RELOC_ARM_ALU_PC_G1
:
23565 case BFD_RELOC_ARM_ALU_PC_G2
:
23566 case BFD_RELOC_ARM_LDR_PC_G0
:
23567 case BFD_RELOC_ARM_LDR_PC_G1
:
23568 case BFD_RELOC_ARM_LDR_PC_G2
:
23569 case BFD_RELOC_ARM_LDRS_PC_G0
:
23570 case BFD_RELOC_ARM_LDRS_PC_G1
:
23571 case BFD_RELOC_ARM_LDRS_PC_G2
:
23572 case BFD_RELOC_ARM_LDC_PC_G0
:
23573 case BFD_RELOC_ARM_LDC_PC_G1
:
23574 case BFD_RELOC_ARM_LDC_PC_G2
:
23575 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23576 case BFD_RELOC_ARM_ALU_SB_G0
:
23577 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23578 case BFD_RELOC_ARM_ALU_SB_G1
:
23579 case BFD_RELOC_ARM_ALU_SB_G2
:
23580 case BFD_RELOC_ARM_LDR_SB_G0
:
23581 case BFD_RELOC_ARM_LDR_SB_G1
:
23582 case BFD_RELOC_ARM_LDR_SB_G2
:
23583 case BFD_RELOC_ARM_LDRS_SB_G0
:
23584 case BFD_RELOC_ARM_LDRS_SB_G1
:
23585 case BFD_RELOC_ARM_LDRS_SB_G2
:
23586 case BFD_RELOC_ARM_LDC_SB_G0
:
23587 case BFD_RELOC_ARM_LDC_SB_G1
:
23588 case BFD_RELOC_ARM_LDC_SB_G2
:
23589 case BFD_RELOC_ARM_V4BX
:
23590 code
= fixp
->fx_r_type
;
23593 case BFD_RELOC_ARM_TLS_GOTDESC
:
23594 case BFD_RELOC_ARM_TLS_GD32
:
23595 case BFD_RELOC_ARM_TLS_LE32
:
23596 case BFD_RELOC_ARM_TLS_IE32
:
23597 case BFD_RELOC_ARM_TLS_LDM32
:
23598 /* BFD will include the symbol's address in the addend.
23599 But we don't want that, so subtract it out again here. */
23600 if (!S_IS_COMMON (fixp
->fx_addsy
))
23601 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23602 code
= fixp
->fx_r_type
;
23606 case BFD_RELOC_ARM_IMMEDIATE
:
23607 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23608 _("internal relocation (type: IMMEDIATE) not fixed up"));
23611 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23612 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23613 _("ADRL used for a symbol not defined in the same file"));
23616 case BFD_RELOC_ARM_OFFSET_IMM
:
23617 if (section
->use_rela_p
)
23619 code
= fixp
->fx_r_type
;
23623 if (fixp
->fx_addsy
!= NULL
23624 && !S_IS_DEFINED (fixp
->fx_addsy
)
23625 && S_IS_LOCAL (fixp
->fx_addsy
))
23627 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23628 _("undefined local label `%s'"),
23629 S_GET_NAME (fixp
->fx_addsy
));
23633 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23634 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23641 switch (fixp
->fx_r_type
)
23643 case BFD_RELOC_NONE
: type
= "NONE"; break;
23644 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23645 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23646 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23647 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23648 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23649 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23650 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23651 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23652 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23653 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23654 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23655 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23656 default: type
= _("<unknown>"); break;
23658 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23659 _("cannot represent %s relocation in this object file format"),
23666 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23668 && fixp
->fx_addsy
== GOT_symbol
)
23670 code
= BFD_RELOC_ARM_GOTPC
;
23671 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23675 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23677 if (reloc
->howto
== NULL
)
23679 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23680 _("cannot represent %s relocation in this object file format"),
23681 bfd_get_reloc_code_name (code
));
23685 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23686 vtable entry to be used in the relocation's section offset. */
23687 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23688 reloc
->address
= fixp
->fx_offset
;
23693 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23696 cons_fix_new_arm (fragS
* frag
,
23700 bfd_reloc_code_real_type reloc
)
23705 FIXME: @@ Should look at CPU word size. */
23709 reloc
= BFD_RELOC_8
;
23712 reloc
= BFD_RELOC_16
;
23716 reloc
= BFD_RELOC_32
;
23719 reloc
= BFD_RELOC_64
;
23724 if (exp
->X_op
== O_secrel
)
23726 exp
->X_op
= O_symbol
;
23727 reloc
= BFD_RELOC_32_SECREL
;
23731 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23734 #if defined (OBJ_COFF)
23736 arm_validate_fix (fixS
* fixP
)
23738 /* If the destination of the branch is a defined symbol which does not have
23739 the THUMB_FUNC attribute, then we must be calling a function which has
23740 the (interfacearm) attribute. We look for the Thumb entry point to that
23741 function and change the branch to refer to that function instead. */
23742 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23743 && fixP
->fx_addsy
!= NULL
23744 && S_IS_DEFINED (fixP
->fx_addsy
)
23745 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23747 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23754 arm_force_relocation (struct fix
* fixp
)
23756 #if defined (OBJ_COFF) && defined (TE_PE)
23757 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23761 /* In case we have a call or a branch to a function in ARM ISA mode from
23762 a thumb function or vice-versa force the relocation. These relocations
23763 are cleared off for some cores that might have blx and simple transformations
23767 switch (fixp
->fx_r_type
)
23769 case BFD_RELOC_ARM_PCREL_JUMP
:
23770 case BFD_RELOC_ARM_PCREL_CALL
:
23771 case BFD_RELOC_THUMB_PCREL_BLX
:
23772 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23776 case BFD_RELOC_ARM_PCREL_BLX
:
23777 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23778 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23779 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23780 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23789 /* Resolve these relocations even if the symbol is extern or weak.
23790 Technically this is probably wrong due to symbol preemption.
23791 In practice these relocations do not have enough range to be useful
23792 at dynamic link time, and some code (e.g. in the Linux kernel)
23793 expects these references to be resolved. */
23794 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23795 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23796 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23797 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23798 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23799 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23800 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23801 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23802 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23803 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23804 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23805 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23806 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23807 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23810 /* Always leave these relocations for the linker. */
23811 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23812 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23813 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23816 /* Always generate relocations against function symbols. */
23817 if (fixp
->fx_r_type
== BFD_RELOC_32
23819 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23822 return generic_force_reloc (fixp
);
23825 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23826 /* Relocations against function names must be left unadjusted,
23827 so that the linker can use this information to generate interworking
23828 stubs. The MIPS version of this function
23829 also prevents relocations that are mips-16 specific, but I do not
23830 know why it does this.
23833 There is one other problem that ought to be addressed here, but
23834 which currently is not: Taking the address of a label (rather
23835 than a function) and then later jumping to that address. Such
23836 addresses also ought to have their bottom bit set (assuming that
23837 they reside in Thumb code), but at the moment they will not. */
23840 arm_fix_adjustable (fixS
* fixP
)
23842 if (fixP
->fx_addsy
== NULL
)
23845 /* Preserve relocations against symbols with function type. */
23846 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23849 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23850 && fixP
->fx_subsy
== NULL
)
23853 /* We need the symbol name for the VTABLE entries. */
23854 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23855 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23858 /* Don't allow symbols to be discarded on GOT related relocs. */
23859 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23860 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23861 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23862 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23863 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23864 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23865 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23866 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23867 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23868 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23869 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23870 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23871 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23872 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23875 /* Similarly for group relocations. */
23876 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23877 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23878 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23881 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23882 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23883 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23884 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23885 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23886 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23887 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23888 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23889 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23894 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23899 elf32_arm_target_format (void)
23902 return (target_big_endian
23903 ? "elf32-bigarm-symbian"
23904 : "elf32-littlearm-symbian");
23905 #elif defined (TE_VXWORKS)
23906 return (target_big_endian
23907 ? "elf32-bigarm-vxworks"
23908 : "elf32-littlearm-vxworks");
23909 #elif defined (TE_NACL)
23910 return (target_big_endian
23911 ? "elf32-bigarm-nacl"
23912 : "elf32-littlearm-nacl");
23914 if (target_big_endian
)
23915 return "elf32-bigarm";
23917 return "elf32-littlearm";
23922 armelf_frob_symbol (symbolS
* symp
,
23925 elf_frob_symbol (symp
, puntp
);
23929 /* MD interface: Finalization. */
23934 literal_pool
* pool
;
23936 /* Ensure that all the IT blocks are properly closed. */
23937 check_it_blocks_finished ();
23939 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23941 /* Put it at the end of the relevant section. */
23942 subseg_set (pool
->section
, pool
->sub_section
);
23944 arm_elf_change_section ();
23951 /* Remove any excess mapping symbols generated for alignment frags in
23952 SEC. We may have created a mapping symbol before a zero byte
23953 alignment; remove it if there's a mapping symbol after the
23956 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23957 void *dummy ATTRIBUTE_UNUSED
)
23959 segment_info_type
*seginfo
= seg_info (sec
);
23962 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23965 for (fragp
= seginfo
->frchainP
->frch_root
;
23967 fragp
= fragp
->fr_next
)
23969 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23970 fragS
*next
= fragp
->fr_next
;
23972 /* Variable-sized frags have been converted to fixed size by
23973 this point. But if this was variable-sized to start with,
23974 there will be a fixed-size frag after it. So don't handle
23976 if (sym
== NULL
|| next
== NULL
)
23979 if (S_GET_VALUE (sym
) < next
->fr_address
)
23980 /* Not at the end of this frag. */
23982 know (S_GET_VALUE (sym
) == next
->fr_address
);
23986 if (next
->tc_frag_data
.first_map
!= NULL
)
23988 /* Next frag starts with a mapping symbol. Discard this
23990 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23994 if (next
->fr_next
== NULL
)
23996 /* This mapping symbol is at the end of the section. Discard
23998 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23999 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24003 /* As long as we have empty frags without any mapping symbols,
24005 /* If the next frag is non-empty and does not start with a
24006 mapping symbol, then this mapping symbol is required. */
24007 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24010 next
= next
->fr_next
;
24012 while (next
!= NULL
);
24017 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24021 arm_adjust_symtab (void)
24026 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24028 if (ARM_IS_THUMB (sym
))
24030 if (THUMB_IS_FUNC (sym
))
24032 /* Mark the symbol as a Thumb function. */
24033 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24034 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24035 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24037 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24038 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24040 as_bad (_("%s: unexpected function type: %d"),
24041 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24043 else switch (S_GET_STORAGE_CLASS (sym
))
24046 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24049 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24052 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24060 if (ARM_IS_INTERWORK (sym
))
24061 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24068 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24070 if (ARM_IS_THUMB (sym
))
24072 elf_symbol_type
* elf_sym
;
24074 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24075 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24077 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24078 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24080 /* If it's a .thumb_func, declare it as so,
24081 otherwise tag label as .code 16. */
24082 if (THUMB_IS_FUNC (sym
))
24083 elf_sym
->internal_elf_sym
.st_target_internal
24084 = ST_BRANCH_TO_THUMB
;
24085 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24086 elf_sym
->internal_elf_sym
.st_info
=
24087 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24092 /* Remove any overlapping mapping symbols generated by alignment frags. */
24093 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24094 /* Now do generic ELF adjustments. */
24095 elf_adjust_symtab ();
24099 /* MD interface: Initialization. */
24102 set_constant_flonums (void)
24106 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24107 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24111 /* Auto-select Thumb mode if it's the only available instruction set for the
24112 given architecture. */
24115 autoselect_thumb_from_cpu_variant (void)
24117 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24118 opcode_select (16);
24127 if ( (arm_ops_hsh
= hash_new ()) == NULL
24128 || (arm_cond_hsh
= hash_new ()) == NULL
24129 || (arm_shift_hsh
= hash_new ()) == NULL
24130 || (arm_psr_hsh
= hash_new ()) == NULL
24131 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24132 || (arm_reg_hsh
= hash_new ()) == NULL
24133 || (arm_reloc_hsh
= hash_new ()) == NULL
24134 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24135 as_fatal (_("virtual memory exhausted"));
24137 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24138 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24139 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24140 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24141 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24142 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24143 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24144 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24145 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24146 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24147 (void *) (v7m_psrs
+ i
));
24148 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24149 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24151 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24153 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24154 (void *) (barrier_opt_names
+ i
));
24156 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24158 struct reloc_entry
* entry
= reloc_names
+ i
;
24160 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24161 /* This makes encode_branch() use the EABI versions of this relocation. */
24162 entry
->reloc
= BFD_RELOC_UNUSED
;
24164 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24168 set_constant_flonums ();
24170 /* Set the cpu variant based on the command-line options. We prefer
24171 -mcpu= over -march= if both are set (as for GCC); and we prefer
24172 -mfpu= over any other way of setting the floating point unit.
24173 Use of legacy options with new options are faulted. */
24176 if (mcpu_cpu_opt
|| march_cpu_opt
)
24177 as_bad (_("use of old and new-style options to set CPU type"));
24179 mcpu_cpu_opt
= legacy_cpu
;
24181 else if (!mcpu_cpu_opt
)
24182 mcpu_cpu_opt
= march_cpu_opt
;
24187 as_bad (_("use of old and new-style options to set FPU type"));
24189 mfpu_opt
= legacy_fpu
;
24191 else if (!mfpu_opt
)
24193 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24194 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24195 /* Some environments specify a default FPU. If they don't, infer it
24196 from the processor. */
24198 mfpu_opt
= mcpu_fpu_opt
;
24200 mfpu_opt
= march_fpu_opt
;
24202 mfpu_opt
= &fpu_default
;
24208 if (mcpu_cpu_opt
!= NULL
)
24209 mfpu_opt
= &fpu_default
;
24210 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24211 mfpu_opt
= &fpu_arch_vfp_v2
;
24213 mfpu_opt
= &fpu_arch_fpa
;
24219 mcpu_cpu_opt
= &cpu_default
;
24220 selected_cpu
= cpu_default
;
24222 else if (no_cpu_selected ())
24223 selected_cpu
= cpu_default
;
24226 selected_cpu
= *mcpu_cpu_opt
;
24228 mcpu_cpu_opt
= &arm_arch_any
;
24231 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24233 autoselect_thumb_from_cpu_variant ();
24235 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24237 #if defined OBJ_COFF || defined OBJ_ELF
24239 unsigned int flags
= 0;
24241 #if defined OBJ_ELF
24242 flags
= meabi_flags
;
24244 switch (meabi_flags
)
24246 case EF_ARM_EABI_UNKNOWN
:
24248 /* Set the flags in the private structure. */
24249 if (uses_apcs_26
) flags
|= F_APCS26
;
24250 if (support_interwork
) flags
|= F_INTERWORK
;
24251 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24252 if (pic_code
) flags
|= F_PIC
;
24253 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24254 flags
|= F_SOFT_FLOAT
;
24256 switch (mfloat_abi_opt
)
24258 case ARM_FLOAT_ABI_SOFT
:
24259 case ARM_FLOAT_ABI_SOFTFP
:
24260 flags
|= F_SOFT_FLOAT
;
24263 case ARM_FLOAT_ABI_HARD
:
24264 if (flags
& F_SOFT_FLOAT
)
24265 as_bad (_("hard-float conflicts with specified fpu"));
24269 /* Using pure-endian doubles (even if soft-float). */
24270 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24271 flags
|= F_VFP_FLOAT
;
24273 #if defined OBJ_ELF
24274 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24275 flags
|= EF_ARM_MAVERICK_FLOAT
;
24278 case EF_ARM_EABI_VER4
:
24279 case EF_ARM_EABI_VER5
:
24280 /* No additional flags to set. */
24287 bfd_set_private_flags (stdoutput
, flags
);
24289 /* We have run out flags in the COFF header to encode the
24290 status of ATPCS support, so instead we create a dummy,
24291 empty, debug section called .arm.atpcs. */
24296 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24300 bfd_set_section_flags
24301 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24302 bfd_set_section_size (stdoutput
, sec
, 0);
24303 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24309 /* Record the CPU type as well. */
24310 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24311 mach
= bfd_mach_arm_iWMMXt2
;
24312 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24313 mach
= bfd_mach_arm_iWMMXt
;
24314 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24315 mach
= bfd_mach_arm_XScale
;
24316 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24317 mach
= bfd_mach_arm_ep9312
;
24318 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24319 mach
= bfd_mach_arm_5TE
;
24320 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24322 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24323 mach
= bfd_mach_arm_5T
;
24325 mach
= bfd_mach_arm_5
;
24327 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24329 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24330 mach
= bfd_mach_arm_4T
;
24332 mach
= bfd_mach_arm_4
;
24334 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24335 mach
= bfd_mach_arm_3M
;
24336 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24337 mach
= bfd_mach_arm_3
;
24338 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24339 mach
= bfd_mach_arm_2a
;
24340 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24341 mach
= bfd_mach_arm_2
;
24343 mach
= bfd_mach_arm_unknown
;
24345 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24348 /* Command line processing. */
24351 Invocation line includes a switch not recognized by the base assembler.
24352 See if it's a processor-specific option.
24354 This routine is somewhat complicated by the need for backwards
24355 compatibility (since older releases of gcc can't be changed).
24356 The new options try to make the interface as compatible as
24359 New options (supported) are:
24361 -mcpu=<cpu name> Assemble for selected processor
24362 -march=<architecture name> Assemble for selected architecture
24363 -mfpu=<fpu architecture> Assemble for selected FPU.
24364 -EB/-mbig-endian Big-endian
24365 -EL/-mlittle-endian Little-endian
24366 -k Generate PIC code
24367 -mthumb Start in Thumb mode
24368 -mthumb-interwork Code supports ARM/Thumb interworking
24370 -m[no-]warn-deprecated Warn about deprecated features
24371 -m[no-]warn-syms Warn when symbols match instructions
24373 For now we will also provide support for:
24375 -mapcs-32 32-bit Program counter
24376 -mapcs-26 26-bit Program counter
24377 -macps-float Floats passed in FP registers
24378 -mapcs-reentrant Reentrant code
24380 (sometime these will probably be replaced with -mapcs=<list of options>
24381 and -matpcs=<list of options>)
24383 The remaining options are only supported for back-wards compatibility.
24384 Cpu variants, the arm part is optional:
24385 -m[arm]1 Currently not supported.
24386 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24387 -m[arm]3 Arm 3 processor
24388 -m[arm]6[xx], Arm 6 processors
24389 -m[arm]7[xx][t][[d]m] Arm 7 processors
24390 -m[arm]8[10] Arm 8 processors
24391 -m[arm]9[20][tdmi] Arm 9 processors
24392 -mstrongarm[110[0]] StrongARM processors
24393 -mxscale XScale processors
24394 -m[arm]v[2345[t[e]]] Arm architectures
24395 -mall All (except the ARM1)
24397 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24398 -mfpe-old (No float load/store multiples)
24399 -mvfpxd VFP Single precision
24401 -mno-fpu Disable all floating point instructions
24403 The following CPU names are recognized:
24404 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24405 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24406 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24407 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24408 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24409 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24410 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24414 const char * md_shortopts
= "m:k";
24416 #ifdef ARM_BI_ENDIAN
24417 #define OPTION_EB (OPTION_MD_BASE + 0)
24418 #define OPTION_EL (OPTION_MD_BASE + 1)
24420 #if TARGET_BYTES_BIG_ENDIAN
24421 #define OPTION_EB (OPTION_MD_BASE + 0)
24423 #define OPTION_EL (OPTION_MD_BASE + 1)
24426 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24428 struct option md_longopts
[] =
24431 {"EB", no_argument
, NULL
, OPTION_EB
},
24434 {"EL", no_argument
, NULL
, OPTION_EL
},
24436 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24437 {NULL
, no_argument
, NULL
, 0}
24441 size_t md_longopts_size
= sizeof (md_longopts
);
24443 struct arm_option_table
24445 char *option
; /* Option name to match. */
24446 char *help
; /* Help information. */
24447 int *var
; /* Variable to change. */
24448 int value
; /* What to change it to. */
24449 char *deprecated
; /* If non-null, print this message. */
24452 struct arm_option_table arm_opts
[] =
24454 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24455 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24456 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24457 &support_interwork
, 1, NULL
},
24458 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24459 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24460 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24462 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24463 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24464 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24465 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24468 /* These are recognized by the assembler, but have no affect on code. */
24469 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24470 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24472 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24473 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24474 &warn_on_deprecated
, 0, NULL
},
24475 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24476 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24477 {NULL
, NULL
, NULL
, 0, NULL
}
24480 struct arm_legacy_option_table
24482 char *option
; /* Option name to match. */
24483 const arm_feature_set
**var
; /* Variable to change. */
24484 const arm_feature_set value
; /* What to change it to. */
24485 char *deprecated
; /* If non-null, print this message. */
24488 const struct arm_legacy_option_table arm_legacy_opts
[] =
24490 /* DON'T add any new processors to this list -- we want the whole list
24491 to go away... Add them to the processors table instead. */
24492 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24493 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24494 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24495 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24496 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24497 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24498 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24499 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24500 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24501 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24502 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24503 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24504 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24505 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24506 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24507 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24508 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24509 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24510 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24511 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24512 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24513 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24514 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24515 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24516 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24517 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24518 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24519 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24520 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24521 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24522 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24523 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24524 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24525 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24526 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24527 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24528 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24529 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24530 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24531 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24532 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24533 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24534 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24535 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24536 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24537 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24538 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24539 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24540 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24541 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24542 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24543 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24544 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24545 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24546 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24547 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24548 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24549 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24550 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24551 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24552 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24553 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24554 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24555 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24556 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24557 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24558 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24559 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24560 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24561 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24562 N_("use -mcpu=strongarm110")},
24563 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24564 N_("use -mcpu=strongarm1100")},
24565 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24566 N_("use -mcpu=strongarm1110")},
24567 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24568 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24569 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24571 /* Architecture variants -- don't add any more to this list either. */
24572 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24573 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24574 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24575 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24576 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24577 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24578 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24579 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24580 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24581 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24582 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24583 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24584 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24585 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24586 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24587 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24588 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24589 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24591 /* Floating point variants -- don't add any more to this list either. */
24592 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24593 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24594 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24595 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24596 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24598 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24601 struct arm_cpu_option_table
24605 const arm_feature_set value
;
24606 /* For some CPUs we assume an FPU unless the user explicitly sets
24608 const arm_feature_set default_fpu
;
24609 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24611 const char *canonical_name
;
24614 /* This list should, at a minimum, contain all the cpu names
24615 recognized by GCC. */
24616 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24617 static const struct arm_cpu_option_table arm_cpus
[] =
24619 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24620 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24621 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24622 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24623 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24624 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24625 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24626 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24627 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24628 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24629 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24630 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24631 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24632 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24633 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24634 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24635 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24636 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24637 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24638 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24639 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24640 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24641 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24642 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24643 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24644 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24645 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24646 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24647 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24648 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24649 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24650 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24651 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24652 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24653 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24654 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24655 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24656 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24657 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24658 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24659 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24660 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24661 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24662 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24663 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24664 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24665 /* For V5 or later processors we default to using VFP; but the user
24666 should really set the FPU type explicitly. */
24667 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24668 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24669 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24670 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24671 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24672 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24673 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24674 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24675 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24676 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24677 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24678 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24679 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24680 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24681 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24682 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24683 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24684 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24685 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24686 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24688 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24689 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24690 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24691 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24692 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24693 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24694 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24695 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24696 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24698 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24699 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24700 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24701 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24702 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24703 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
24704 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
24705 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24706 FPU_NONE
, "Cortex-A5"),
24707 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24709 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24710 ARM_FEATURE_COPROC (FPU_VFP_V3
24711 | FPU_NEON_EXT_V1
),
24713 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24714 ARM_FEATURE_COPROC (FPU_VFP_V3
24715 | FPU_NEON_EXT_V1
),
24717 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24719 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24721 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24723 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24725 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24727 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24729 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24730 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24732 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24733 FPU_NONE
, "Cortex-R5"),
24734 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24735 FPU_ARCH_VFP_V3D16
,
24737 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24738 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24739 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24740 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24741 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24742 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24743 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24746 /* ??? XSCALE is really an architecture. */
24747 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24748 /* ??? iwmmxt is not a processor. */
24749 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24750 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24751 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24753 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24754 FPU_ARCH_MAVERICK
, "ARM920T"),
24755 /* Marvell processors. */
24756 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24758 FPU_ARCH_VFP_V3D16
, NULL
),
24759 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24761 FPU_ARCH_NEON_VFP_V4
, NULL
),
24762 /* APM X-Gene family. */
24763 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24765 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24768 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24772 struct arm_arch_option_table
24776 const arm_feature_set value
;
24777 const arm_feature_set default_fpu
;
24780 /* This list should, at a minimum, contain all the architecture names
24781 recognized by GCC. */
24782 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24783 static const struct arm_arch_option_table arm_archs
[] =
24785 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24786 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24787 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24788 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24789 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24790 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24791 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24792 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24793 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24794 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24795 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24796 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24797 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24798 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24799 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24800 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24801 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24802 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24803 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24804 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24805 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24806 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
24807 kept to preserve existing behaviour. */
24808 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24809 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24810 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24811 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24812 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24813 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
24814 kept to preserve existing behaviour. */
24815 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24816 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24817 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24818 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24819 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24820 /* The official spelling of the ARMv7 profile variants is the dashed form.
24821 Accept the non-dashed form for compatibility with old toolchains. */
24822 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24823 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24824 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24825 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24826 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24827 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24828 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24829 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24830 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24831 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24832 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24833 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24834 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24835 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24837 #undef ARM_ARCH_OPT
24839 /* ISA extensions in the co-processor and main instruction set space. */
24840 struct arm_option_extension_value_table
24844 const arm_feature_set merge_value
;
24845 const arm_feature_set clear_value
;
24846 const arm_feature_set allowed_archs
;
24849 /* The following table must be in alphabetical order with a NULL last entry.
24851 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24852 static const struct arm_option_extension_value_table arm_extensions
[] =
24854 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24855 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24856 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24857 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24858 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24859 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24860 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24861 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24862 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24863 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24864 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24865 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24866 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24867 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24868 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24869 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24870 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24871 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24872 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24873 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24874 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24875 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24876 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24877 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24878 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24879 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24880 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24881 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24882 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24883 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24884 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24885 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24887 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24888 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24889 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24890 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24891 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24892 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24893 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24894 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24898 /* ISA floating-point and Advanced SIMD extensions. */
24899 struct arm_option_fpu_value_table
24902 const arm_feature_set value
;
24905 /* This list should, at a minimum, contain all the fpu names
24906 recognized by GCC. */
24907 static const struct arm_option_fpu_value_table arm_fpus
[] =
24909 {"softfpa", FPU_NONE
},
24910 {"fpe", FPU_ARCH_FPE
},
24911 {"fpe2", FPU_ARCH_FPE
},
24912 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24913 {"fpa", FPU_ARCH_FPA
},
24914 {"fpa10", FPU_ARCH_FPA
},
24915 {"fpa11", FPU_ARCH_FPA
},
24916 {"arm7500fe", FPU_ARCH_FPA
},
24917 {"softvfp", FPU_ARCH_VFP
},
24918 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24919 {"vfp", FPU_ARCH_VFP_V2
},
24920 {"vfp9", FPU_ARCH_VFP_V2
},
24921 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24922 {"vfp10", FPU_ARCH_VFP_V2
},
24923 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24924 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24925 {"vfpv2", FPU_ARCH_VFP_V2
},
24926 {"vfpv3", FPU_ARCH_VFP_V3
},
24927 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24928 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24929 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24930 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24931 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24932 {"arm1020t", FPU_ARCH_VFP_V1
},
24933 {"arm1020e", FPU_ARCH_VFP_V2
},
24934 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24935 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24936 {"maverick", FPU_ARCH_MAVERICK
},
24937 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24938 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24939 {"vfpv4", FPU_ARCH_VFP_V4
},
24940 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24941 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24942 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24943 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24944 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24945 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24946 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24947 {"crypto-neon-fp-armv8",
24948 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24949 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
24950 {"crypto-neon-fp-armv8.1",
24951 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
24952 {NULL
, ARM_ARCH_NONE
}
24955 struct arm_option_value_table
24961 static const struct arm_option_value_table arm_float_abis
[] =
24963 {"hard", ARM_FLOAT_ABI_HARD
},
24964 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24965 {"soft", ARM_FLOAT_ABI_SOFT
},
24970 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24971 static const struct arm_option_value_table arm_eabis
[] =
24973 {"gnu", EF_ARM_EABI_UNKNOWN
},
24974 {"4", EF_ARM_EABI_VER4
},
24975 {"5", EF_ARM_EABI_VER5
},
24980 struct arm_long_option_table
24982 char * option
; /* Substring to match. */
24983 char * help
; /* Help information. */
24984 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24985 char * deprecated
; /* If non-null, print this message. */
24989 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24991 arm_feature_set
*ext_set
= (arm_feature_set
*)
24992 xmalloc (sizeof (arm_feature_set
));
24994 /* We insist on extensions being specified in alphabetical order, and with
24995 extensions being added before being removed. We achieve this by having
24996 the global ARM_EXTENSIONS table in alphabetical order, and using the
24997 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24998 or removing it (0) and only allowing it to change in the order
25000 const struct arm_option_extension_value_table
* opt
= NULL
;
25001 int adding_value
= -1;
25003 /* Copy the feature set, so that we can modify it. */
25004 *ext_set
= **opt_p
;
25007 while (str
!= NULL
&& *str
!= 0)
25014 as_bad (_("invalid architectural extension"));
25019 ext
= strchr (str
, '+');
25024 len
= strlen (str
);
25026 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25028 if (adding_value
!= 0)
25031 opt
= arm_extensions
;
25039 if (adding_value
== -1)
25042 opt
= arm_extensions
;
25044 else if (adding_value
!= 1)
25046 as_bad (_("must specify extensions to add before specifying "
25047 "those to remove"));
25054 as_bad (_("missing architectural extension"));
25058 gas_assert (adding_value
!= -1);
25059 gas_assert (opt
!= NULL
);
25061 /* Scan over the options table trying to find an exact match. */
25062 for (; opt
->name
!= NULL
; opt
++)
25063 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25065 /* Check we can apply the extension to this architecture. */
25066 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25068 as_bad (_("extension does not apply to the base architecture"));
25072 /* Add or remove the extension. */
25074 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25076 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25081 if (opt
->name
== NULL
)
25083 /* Did we fail to find an extension because it wasn't specified in
25084 alphabetical order, or because it does not exist? */
25086 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25087 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25090 if (opt
->name
== NULL
)
25091 as_bad (_("unknown architectural extension `%s'"), str
);
25093 as_bad (_("architectural extensions must be specified in "
25094 "alphabetical order"));
25100 /* We should skip the extension we've just matched the next time
25112 arm_parse_cpu (char *str
)
25114 const struct arm_cpu_option_table
*opt
;
25115 char *ext
= strchr (str
, '+');
25121 len
= strlen (str
);
25125 as_bad (_("missing cpu name `%s'"), str
);
25129 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25130 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25132 mcpu_cpu_opt
= &opt
->value
;
25133 mcpu_fpu_opt
= &opt
->default_fpu
;
25134 if (opt
->canonical_name
)
25135 strcpy (selected_cpu_name
, opt
->canonical_name
);
25140 for (i
= 0; i
< len
; i
++)
25141 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25142 selected_cpu_name
[i
] = 0;
25146 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25151 as_bad (_("unknown cpu `%s'"), str
);
25156 arm_parse_arch (char *str
)
25158 const struct arm_arch_option_table
*opt
;
25159 char *ext
= strchr (str
, '+');
25165 len
= strlen (str
);
25169 as_bad (_("missing architecture name `%s'"), str
);
25173 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25174 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25176 march_cpu_opt
= &opt
->value
;
25177 march_fpu_opt
= &opt
->default_fpu
;
25178 strcpy (selected_cpu_name
, opt
->name
);
25181 return arm_parse_extension (ext
, &march_cpu_opt
);
25186 as_bad (_("unknown architecture `%s'\n"), str
);
25191 arm_parse_fpu (char * str
)
25193 const struct arm_option_fpu_value_table
* opt
;
25195 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25196 if (streq (opt
->name
, str
))
25198 mfpu_opt
= &opt
->value
;
25202 as_bad (_("unknown floating point format `%s'\n"), str
);
25207 arm_parse_float_abi (char * str
)
25209 const struct arm_option_value_table
* opt
;
25211 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25212 if (streq (opt
->name
, str
))
25214 mfloat_abi_opt
= opt
->value
;
25218 as_bad (_("unknown floating point abi `%s'\n"), str
);
25224 arm_parse_eabi (char * str
)
25226 const struct arm_option_value_table
*opt
;
25228 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25229 if (streq (opt
->name
, str
))
25231 meabi_flags
= opt
->value
;
25234 as_bad (_("unknown EABI `%s'\n"), str
);
25240 arm_parse_it_mode (char * str
)
25242 bfd_boolean ret
= TRUE
;
25244 if (streq ("arm", str
))
25245 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25246 else if (streq ("thumb", str
))
25247 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25248 else if (streq ("always", str
))
25249 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25250 else if (streq ("never", str
))
25251 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25254 as_bad (_("unknown implicit IT mode `%s', should be "\
25255 "arm, thumb, always, or never."), str
);
25263 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25265 codecomposer_syntax
= TRUE
;
25266 arm_comment_chars
[0] = ';';
25267 arm_line_separator_chars
[0] = 0;
25271 struct arm_long_option_table arm_long_opts
[] =
25273 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25274 arm_parse_cpu
, NULL
},
25275 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25276 arm_parse_arch
, NULL
},
25277 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25278 arm_parse_fpu
, NULL
},
25279 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25280 arm_parse_float_abi
, NULL
},
25282 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25283 arm_parse_eabi
, NULL
},
25285 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25286 arm_parse_it_mode
, NULL
},
25287 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25288 arm_ccs_mode
, NULL
},
25289 {NULL
, NULL
, 0, NULL
}
25293 md_parse_option (int c
, char * arg
)
25295 struct arm_option_table
*opt
;
25296 const struct arm_legacy_option_table
*fopt
;
25297 struct arm_long_option_table
*lopt
;
25303 target_big_endian
= 1;
25309 target_big_endian
= 0;
25313 case OPTION_FIX_V4BX
:
25318 /* Listing option. Just ignore these, we don't support additional
25323 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25325 if (c
== opt
->option
[0]
25326 && ((arg
== NULL
&& opt
->option
[1] == 0)
25327 || streq (arg
, opt
->option
+ 1)))
25329 /* If the option is deprecated, tell the user. */
25330 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25331 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25332 arg
? arg
: "", _(opt
->deprecated
));
25334 if (opt
->var
!= NULL
)
25335 *opt
->var
= opt
->value
;
25341 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25343 if (c
== fopt
->option
[0]
25344 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25345 || streq (arg
, fopt
->option
+ 1)))
25347 /* If the option is deprecated, tell the user. */
25348 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25349 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25350 arg
? arg
: "", _(fopt
->deprecated
));
25352 if (fopt
->var
!= NULL
)
25353 *fopt
->var
= &fopt
->value
;
25359 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25361 /* These options are expected to have an argument. */
25362 if (c
== lopt
->option
[0]
25364 && strncmp (arg
, lopt
->option
+ 1,
25365 strlen (lopt
->option
+ 1)) == 0)
25367 /* If the option is deprecated, tell the user. */
25368 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25369 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25370 _(lopt
->deprecated
));
25372 /* Call the sup-option parser. */
25373 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25384 md_show_usage (FILE * fp
)
25386 struct arm_option_table
*opt
;
25387 struct arm_long_option_table
*lopt
;
25389 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25391 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25392 if (opt
->help
!= NULL
)
25393 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25395 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25396 if (lopt
->help
!= NULL
)
25397 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25401 -EB assemble code for a big-endian cpu\n"));
25406 -EL assemble code for a little-endian cpu\n"));
25410 --fix-v4bx Allow BX in ARMv4 code\n"));
25418 arm_feature_set flags
;
25419 } cpu_arch_ver_table
;
25421 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25422 least features first. */
25423 static const cpu_arch_ver_table cpu_arch_ver
[] =
25429 {4, ARM_ARCH_V5TE
},
25430 {5, ARM_ARCH_V5TEJ
},
25434 {11, ARM_ARCH_V6M
},
25435 {12, ARM_ARCH_V6SM
},
25436 {8, ARM_ARCH_V6T2
},
25437 {10, ARM_ARCH_V7VE
},
25438 {10, ARM_ARCH_V7R
},
25439 {10, ARM_ARCH_V7M
},
25440 {14, ARM_ARCH_V8A
},
25444 /* Set an attribute if it has not already been set by the user. */
25446 aeabi_set_attribute_int (int tag
, int value
)
25449 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25450 || !attributes_set_explicitly
[tag
])
25451 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25455 aeabi_set_attribute_string (int tag
, const char *value
)
25458 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25459 || !attributes_set_explicitly
[tag
])
25460 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25463 /* Set the public EABI object attributes. */
25465 aeabi_set_public_attributes (void)
25470 int fp16_optional
= 0;
25471 arm_feature_set flags
;
25472 arm_feature_set tmp
;
25473 const cpu_arch_ver_table
*p
;
25475 /* Choose the architecture based on the capabilities of the requested cpu
25476 (if any) and/or the instructions actually used. */
25477 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25478 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25479 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25481 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25482 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25484 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25485 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25487 selected_cpu
= flags
;
25489 /* Allow the user to override the reported architecture. */
25492 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25493 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25496 /* We need to make sure that the attributes do not identify us as v6S-M
25497 when the only v6S-M feature in use is the Operating System Extensions. */
25498 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25499 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25500 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25504 for (p
= cpu_arch_ver
; p
->val
; p
++)
25506 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25509 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25513 /* The table lookup above finds the last architecture to contribute
25514 a new feature. Unfortunately, Tag13 is a subset of the union of
25515 v6T2 and v7-M, so it is never seen as contributing a new feature.
25516 We can not search for the last entry which is entirely used,
25517 because if no CPU is specified we build up only those flags
25518 actually used. Perhaps we should separate out the specified
25519 and implicit cases. Avoid taking this path for -march=all by
25520 checking for contradictory v7-A / v7-M features. */
25522 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25523 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25524 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25527 /* Tag_CPU_name. */
25528 if (selected_cpu_name
[0])
25532 q
= selected_cpu_name
;
25533 if (strncmp (q
, "armv", 4) == 0)
25538 for (i
= 0; q
[i
]; i
++)
25539 q
[i
] = TOUPPER (q
[i
]);
25541 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25544 /* Tag_CPU_arch. */
25545 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25547 /* Tag_CPU_arch_profile. */
25548 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25550 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25552 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25557 if (profile
!= '\0')
25558 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25560 /* Tag_ARM_ISA_use. */
25561 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25563 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25565 /* Tag_THUMB_ISA_use. */
25566 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25568 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25569 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25571 /* Tag_VFP_arch. */
25572 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25573 aeabi_set_attribute_int (Tag_VFP_arch
,
25574 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25576 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25577 aeabi_set_attribute_int (Tag_VFP_arch
,
25578 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25580 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25583 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25585 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25587 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25590 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25591 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25592 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25593 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25594 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25596 /* Tag_ABI_HardFP_use. */
25597 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25598 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25599 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25601 /* Tag_WMMX_arch. */
25602 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25603 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25604 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25605 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25607 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25608 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25609 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25610 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25612 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25614 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25618 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25623 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25624 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25625 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25629 We set Tag_DIV_use to two when integer divide instructions have been used
25630 in ARM state, or when Thumb integer divide instructions have been used,
25631 but we have no architecture profile set, nor have we any ARM instructions.
25633 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25636 For new architectures we will have to check these tests. */
25637 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25638 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25639 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25640 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25641 || (profile
== '\0'
25642 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25643 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25644 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25646 /* Tag_MP_extension_use. */
25647 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25648 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25650 /* Tag Virtualization_use. */
25651 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25653 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25656 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25659 /* Add the default contents for the .ARM.attributes section. */
25663 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25666 aeabi_set_public_attributes ();
25668 #endif /* OBJ_ELF */
25671 /* Parse a .cpu directive. */
25674 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25676 const struct arm_cpu_option_table
*opt
;
25680 name
= input_line_pointer
;
25681 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25682 input_line_pointer
++;
25683 saved_char
= *input_line_pointer
;
25684 *input_line_pointer
= 0;
25686 /* Skip the first "all" entry. */
25687 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25688 if (streq (opt
->name
, name
))
25690 mcpu_cpu_opt
= &opt
->value
;
25691 selected_cpu
= opt
->value
;
25692 if (opt
->canonical_name
)
25693 strcpy (selected_cpu_name
, opt
->canonical_name
);
25697 for (i
= 0; opt
->name
[i
]; i
++)
25698 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25700 selected_cpu_name
[i
] = 0;
25702 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25703 *input_line_pointer
= saved_char
;
25704 demand_empty_rest_of_line ();
25707 as_bad (_("unknown cpu `%s'"), name
);
25708 *input_line_pointer
= saved_char
;
25709 ignore_rest_of_line ();
25713 /* Parse a .arch directive. */
25716 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25718 const struct arm_arch_option_table
*opt
;
25722 name
= input_line_pointer
;
25723 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25724 input_line_pointer
++;
25725 saved_char
= *input_line_pointer
;
25726 *input_line_pointer
= 0;
25728 /* Skip the first "all" entry. */
25729 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25730 if (streq (opt
->name
, name
))
25732 mcpu_cpu_opt
= &opt
->value
;
25733 selected_cpu
= opt
->value
;
25734 strcpy (selected_cpu_name
, opt
->name
);
25735 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25736 *input_line_pointer
= saved_char
;
25737 demand_empty_rest_of_line ();
25741 as_bad (_("unknown architecture `%s'\n"), name
);
25742 *input_line_pointer
= saved_char
;
25743 ignore_rest_of_line ();
25747 /* Parse a .object_arch directive. */
25750 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25752 const struct arm_arch_option_table
*opt
;
25756 name
= input_line_pointer
;
25757 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25758 input_line_pointer
++;
25759 saved_char
= *input_line_pointer
;
25760 *input_line_pointer
= 0;
25762 /* Skip the first "all" entry. */
25763 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25764 if (streq (opt
->name
, name
))
25766 object_arch
= &opt
->value
;
25767 *input_line_pointer
= saved_char
;
25768 demand_empty_rest_of_line ();
25772 as_bad (_("unknown architecture `%s'\n"), name
);
25773 *input_line_pointer
= saved_char
;
25774 ignore_rest_of_line ();
25777 /* Parse a .arch_extension directive. */
25780 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25782 const struct arm_option_extension_value_table
*opt
;
25785 int adding_value
= 1;
25787 name
= input_line_pointer
;
25788 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25789 input_line_pointer
++;
25790 saved_char
= *input_line_pointer
;
25791 *input_line_pointer
= 0;
25793 if (strlen (name
) >= 2
25794 && strncmp (name
, "no", 2) == 0)
25800 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25801 if (streq (opt
->name
, name
))
25803 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25805 as_bad (_("architectural extension `%s' is not allowed for the "
25806 "current base architecture"), name
);
25811 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25814 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25816 mcpu_cpu_opt
= &selected_cpu
;
25817 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25818 *input_line_pointer
= saved_char
;
25819 demand_empty_rest_of_line ();
25823 if (opt
->name
== NULL
)
25824 as_bad (_("unknown architecture extension `%s'\n"), name
);
25826 *input_line_pointer
= saved_char
;
25827 ignore_rest_of_line ();
25830 /* Parse a .fpu directive. */
25833 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25835 const struct arm_option_fpu_value_table
*opt
;
25839 name
= input_line_pointer
;
25840 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25841 input_line_pointer
++;
25842 saved_char
= *input_line_pointer
;
25843 *input_line_pointer
= 0;
25845 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25846 if (streq (opt
->name
, name
))
25848 mfpu_opt
= &opt
->value
;
25849 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25850 *input_line_pointer
= saved_char
;
25851 demand_empty_rest_of_line ();
25855 as_bad (_("unknown floating point format `%s'\n"), name
);
25856 *input_line_pointer
= saved_char
;
25857 ignore_rest_of_line ();
25860 /* Copy symbol information. */
25863 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25865 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25869 /* Given a symbolic attribute NAME, return the proper integer value.
25870 Returns -1 if the attribute is not known. */
25873 arm_convert_symbolic_attribute (const char *name
)
25875 static const struct
25880 attribute_table
[] =
25882 /* When you modify this table you should
25883 also modify the list in doc/c-arm.texi. */
25884 #define T(tag) {#tag, tag}
25885 T (Tag_CPU_raw_name
),
25888 T (Tag_CPU_arch_profile
),
25889 T (Tag_ARM_ISA_use
),
25890 T (Tag_THUMB_ISA_use
),
25894 T (Tag_Advanced_SIMD_arch
),
25895 T (Tag_PCS_config
),
25896 T (Tag_ABI_PCS_R9_use
),
25897 T (Tag_ABI_PCS_RW_data
),
25898 T (Tag_ABI_PCS_RO_data
),
25899 T (Tag_ABI_PCS_GOT_use
),
25900 T (Tag_ABI_PCS_wchar_t
),
25901 T (Tag_ABI_FP_rounding
),
25902 T (Tag_ABI_FP_denormal
),
25903 T (Tag_ABI_FP_exceptions
),
25904 T (Tag_ABI_FP_user_exceptions
),
25905 T (Tag_ABI_FP_number_model
),
25906 T (Tag_ABI_align_needed
),
25907 T (Tag_ABI_align8_needed
),
25908 T (Tag_ABI_align_preserved
),
25909 T (Tag_ABI_align8_preserved
),
25910 T (Tag_ABI_enum_size
),
25911 T (Tag_ABI_HardFP_use
),
25912 T (Tag_ABI_VFP_args
),
25913 T (Tag_ABI_WMMX_args
),
25914 T (Tag_ABI_optimization_goals
),
25915 T (Tag_ABI_FP_optimization_goals
),
25916 T (Tag_compatibility
),
25917 T (Tag_CPU_unaligned_access
),
25918 T (Tag_FP_HP_extension
),
25919 T (Tag_VFP_HP_extension
),
25920 T (Tag_ABI_FP_16bit_format
),
25921 T (Tag_MPextension_use
),
25923 T (Tag_nodefaults
),
25924 T (Tag_also_compatible_with
),
25925 T (Tag_conformance
),
25927 T (Tag_Virtualization_use
),
25928 /* We deliberately do not include Tag_MPextension_use_legacy. */
25936 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25937 if (streq (name
, attribute_table
[i
].name
))
25938 return attribute_table
[i
].tag
;
25944 /* Apply sym value for relocations only in the case that they are for
25945 local symbols in the same segment as the fixup and you have the
25946 respective architectural feature for blx and simple switches. */
25948 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25951 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25952 /* PR 17444: If the local symbol is in a different section then a reloc
25953 will always be generated for it, so applying the symbol value now
25954 will result in a double offset being stored in the relocation. */
25955 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25956 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25958 switch (fixP
->fx_r_type
)
25960 case BFD_RELOC_ARM_PCREL_BLX
:
25961 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25962 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25966 case BFD_RELOC_ARM_PCREL_CALL
:
25967 case BFD_RELOC_THUMB_PCREL_BLX
:
25968 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25979 #endif /* OBJ_ELF */